fix(i2c): drain TX FIFO before a repeated START - #134
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Update `third_party/esp-idf` from `1d89388f11383182b35c06fe44278847235b3a53` to `bf81d4c8cdaeaee5a13feca0c8aea60988f12807`, incorporating two merged I2C fixes: - [toitware/esp-idf#134](toitware/esp-idf#134): drain the controller TX FIFO before a repeated START so the next address cannot overwrite pending write data. - [toitware/esp-idf#135](toitware/esp-idf#135): refresh the target RX FIFO count between interrupt causes, preventing a 20-byte write from being reported as 40 bytes with a corrupt suffix. Includes a deterministic two-device Unity regression.
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Long combined I2C write/read transactions on ESP32-H2 can NACK when the write fills the TX FIFO: the repeated-START handler queues the next address before the preceding data has drained. A 63-byte write reproduced the failure, while separate write/read transactions passed.
Extend the existing FIFO drain sequence for consecutive writes to also cover a following repeated START on targets without
SOC_I2C_STOP_INDEPENDENT. This uses END to drain and resume; it does not insert a STOP, so the combined transaction is preserved. The shared command path handles synchronous and asynchronous transfers.Validation:
The hardware regression is included in the companion Toit ESP32-H2 support PR: toitlang/toit#3240 (
tests/hw/esp32h2/i2c-repeated-start.toit).