Add Vivado xsim DPI-C co-simulation backend for RogueTcpStream, RogueTcpMemory, and RogueSideBand

[ruck314]

Description

Adds a Vivado xsim/SystemVerilog DPI-C co-simulation backend for RogueTcpStream, RogueTcpMemory, and RogueSideBand alongside the existing GHDL/VHPIDIRECT and VCS/VHPI paths. The VHDL forwarding entities, SystemVerilog DPI leaves, and C adapters reuse the shared axi/simlink/shared/*Core.h ZeroMQ models and link into one RogueTcpDpi.so built by xsc.

Each elaborated model now owns an independent DPI chandle, native model state, ZeroMQ context, and two-port endpoint pair. Explicit create/update/destroy APIs, normal/fallback cleanup, cross-model port collision checks, and multi-instance regressions support established multi-link users without changing the public VHDL interfaces or Rogue TCP wire formats.

The xsim usage guide now references only checked-in examples and documents the clock/reset, unique-port, peer, and connected-and-draining transport requirements for external targets.

Details

This pull request is stacked on #1450 because it uses that pull request's backend split and shared C cores. It does not depend on #1450's later GHDL integer-handle implementation; after #1450 merges, this pull request can be retargeted to pre-release and any real integration conflicts resolved then.

The shared cores retain the established synchronous ZeroMQ send behavior used by VCS/VHPI and GHDL/VHPIDIRECT. Peers must be connected and draining before HDL produces outbound traffic. No-peer, saturation, linger, retry-queue, and worker-thread hardening is intentionally deferred to a separate cross-backend change so xsim does not acquire different transport semantics.

Validation:

• The original backend was exercised end-to-end with Vivado 2025.2 and the rogue_v6.13.0 environment; the Stream PRBS loopback reported rxCount == 10 and rxErrors == 0.
• The new host-native DPI adapter regression passes four tests, including four Stream, two Memory, and two SideBand contexts exchanging isolated tagged ZeroMQ traffic, lifecycle reuse, and negative ownership/port cases.
• The checked-in Vivado regression elaborates the same eight-instance VHDL/SV topology, pulses reset twice, rejects duplicate port pairs, and compiles the C adapters against an xelab -dpiheader generated ABI. It skips explicitly when Vivado tools are unavailable; the new multi-instance xsim flow still needs a recorded Vivado-enabled run before merge.
• Warning-enabled C compilation, Python lint, VSG, direct GHDL analysis of the xsim VHDL harness, and git diff --check pass locally.

Pairs with the ruckus-side xsc / -sv_lib RogueTcpDpi orchestration in slaclab/ruckus#399.

Related

• RogueTcp Stream/Memory/SideBand: GHDL VHPIDIRECT cosim + cocotb CI coverage #1450 — GHDL/VHPIDIRECT backend and shared simlink cores
• Vivado xsim DPI-C Rogue co-simulation orchestration ruckus#399 — Vivado xsim DPI orchestration

[bengineerd]

Requesting changes for per-instance DPI state and runnable usage documentation. The focused static checks and GHDL analysis are otherwise clean.