Vivado xsim DPI-C Rogue co-simulation orchestration#399
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Add the ruckus-side orchestration for a Vivado xsim SystemVerilog DPI-C co-simulation backend, alongside the existing GHDL (VHPIDIRECT) and VCS (VHPI) paths. Pairs with the surf axi/simlink/xsim/ DPI backends (RogueTcpStream/RogueTcpMemory/RogueSideBand), which link into one combined RogueTcpDpi.so. Additive only -- the GHDL and VCS paths are unchanged. - run/pre/xsim.tcl: the xsim.compile.tcl.pre hook -- detects the Rogue co-sim sources, builds RogueTcpDpi.so via xsc, and stages it for the xsim run. Registered unconditionally by project.tcl; a fast no-op for non-Rogue projects. Fails fast with a pointer to "make vcs" when the surf version predates axi/simlink/xsim/ (legacy sim + src VHPI layout), and enforces the Vivado 2023.1+ floor the xsc link driver requires. - sources.tcl: bind the DPI library via xelab -sv_lib RogueTcpDpi at project generation (guarded on the xsim Rogue backend). - project.tcl: register the pre-compile hook and DPI/xsc project properties. - xsim.tcl: batch-path parity for the DPI .so (LD_LIBRARY_PATH, libstdc++ LD_PRELOAD, libzmq check). - gui.tcl: set the libstdc++ LD_PRELOAD and RogueTcpDpi.so LD_LIBRARY_PATH at GUI startup, before Run Simulation. launch_simulation freezes the xsim subprocess environment before the run/pre hook fires, so the preload must be established here to reach the GUI-launched xsim; otherwise the co-sim dies with 'GLIBCXX_3.4.29 not found'. - proc/sim_management.tcl: shared RogueSimSources / RogueCheckLibZmq / RoguePreloadLibStdCpp procs used by both the VCS and xsim flows. Backend selection: surf's simlink loader chose its backend by sniffing VCS_VERSION, which is set whenever VCS is sourced -- even for a Vivado xsim run. Export RUCKUS_SIM_BACKEND per make target (xsim/gui -> xsim, vcs -> vcs) so the backend follows the invoked target regardless of which tools are on the environment. Older surf ignores the variable, so the change is backward compatible. Simulation variables: VIVADO_PROJECT_SIM now defaults to empty so the sim_1 top configured by the target's ruckus.tcl (set_property top ... [get_filesets sim_1]) is honored by "make xsim"; set it only to override the top. VIVADO_PROJECT_SIM_TIME now defaults to "all" so a batch "make xsim" co-sim free-runs until the testbench calls $finish/$stop or is interrupted -- the old "1000 ns" default exited before the external peer connected. Pass a time value (e.g. "1000 ns") to bound a run. The libstdc++ LD_PRELOAD resolves a compatible libstdc++ dynamically (libzmq's prefix -> active gcc -> RHEL/Rocky and Debian system paths) instead of a hardcoded Debian-only path; Vivado injects an older libstdc++ via LD_LIBRARY_PATH, which LD_PRELOAD outranks. Missing/old libzmq fails fast with a clear diagnostic. All three modules are handled by one uniform flow. Verified end-to-end against Vivado 2025.2 + the rogue_v6.13.0 conda env: the surf RogueTcpStream loopback demo reports rxCount == 10 / rxErrors == 0.
- how-to/xsim_rogue_cosim.rst: GUI and batch co-sim guide, including the batch "make xsim VIVADO_PROJECT_SIM=<DemoTb>" invocation. The sim free-runs under the default VIVADO_PROJECT_SIM_TIME=all while the external peer drives it. Covers automatic backend selection, the surf axi/simlink/xsim/ requirement, and troubleshooting. - reference/makefile_reference.rst: note the co-sim DPI auto-build on the gui/xsim targets and cross-reference the co-sim usage of VIVADO_PROJECT_SIM / VIVADO_PROJECT_SIM_TIME (default "all"). - how-to/index.rst: add the how-to to the toctree.
The "wis" target and vivado/wis.tcl generated an init_wis.tcl script to seed a Windows Vivado session's environment variables without Cygwin. It is no longer used. Drop the target, the script, and its entry in the makefile reference documentation.
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Summary
Adds the ruckus-side orchestration for the new Vivado xsim SystemVerilog DPI-C co-simulation backend, alongside the existing GHDL (VHPIDIRECT) and VCS (VHPI) paths. Pairs with the surf
axi/simlink/xsim/DPI backends forRogueTcpStream,RogueTcpMemory, andRogueSideBand, which link into one combinedRogueTcpDpi.so(slaclab/surf#1452).Additive only — the GHDL and VCS co-sim paths are unchanged.
Changes (
vivado/)DPI build & bind
run/pre/xsim.tcl(new): thexsim.compile.tcl.prehook — detects the Rogue co-sim sources, builds the combinedRogueTcpDpi.soviaxsc, and stages it for the xsim run. Registered unconditionally byproject.tcl; a fast no-op for non-Rogue projects. Lives under the standardrun/pre/hook directory.sources.tcl: register the DPI shared library viaxelab -sv_lib RogueTcpDpiat project generation (guarded on the xsim Rogue backend).project.tcl: register the pre-compile hook and DPI /xscproject properties.xsim.tcl: batch-path parity for the DPI.so(LD_LIBRARY_PATH, libstdc++LD_PRELOAD, libzmq check).Robustness / diagnostics
RogueTcpStream/RogueTcpMemory/RogueSideBand) handled by one uniform flow.LD_PRELOADresolves a libstdc++ new enough for the co-sim's libzmq dynamically (libzmq's prefix → activegcc→ RHEL/Rocky and Debian system paths), prepending rather than clobberingLD_PRELOAD. This fixes the earlier hardcoded Debian-only path that silently no-op'd on RHEL/Rocky. (Vivado's loader injects its own older libstdc++ viaLD_LIBRARY_PATH;LD_PRELOADoutranks it, so it is the robust override.)Shared procs (
vivado/proc/sim_management.tcl)RogueSimSources {backend}— Rogue co-sim source detector, shared by the VCS and xsim flows.RogueCheckLibZmq— the libzmq availability check.RoguePreloadLibStdCpp— the libstdc++LD_PRELOADresolver.Docs
docs/how-to/xsim_rogue_cosim.rst— GUI and batch co-sim how-to, including the batchmake xsim VIVADO_PROJECT_SIM=<DemoTb> VIVADO_PROJECT_SIM_TIME=allinvocation (the sim must free-run while the external peer drives it).docs/reference/makefile_reference.rst— cross-referenced co-sim usage ofVIVADO_PROJECT_SIM/VIVADO_PROJECT_SIM_TIME.