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[hardware] 🐛 Fix false illegal on unaligned widening reduction #478

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[hardware] 🐛 Fix false illegal on unaligned widening reduction #478

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1 change: 1 addition & 0 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Force cheshire's sim scripts re-generation
- Fix u-boot to support RVV-linux
- Fixed src emul check for vector integer extension operation
- Fix false illegal-instruction on a widening reduction (vwredsum/vwredsumu) with an unaligned vd

### Added

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33 changes: 21 additions & 12 deletions hardware/src/ara_dispatcher.sv
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Expand Up @@ -931,18 +931,27 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(

// Instructions with an integer LMUL have extra constraints on the registers they can
// access.
unique case (ara_req.emul)
LMUL_2: if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000 ||
(insn.varith_type.rs2 & 5'b00001) != 5'b00000 ||
(insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = 1'b1;
LMUL_4: if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000 ||
(insn.varith_type.rs2 & 5'b00011) != 5'b00000 ||
(insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = 1'b1;
LMUL_8: if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000 ||
(insn.varith_type.rs2 & 5'b00111) != 5'b00000 ||
(insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = 1'b1;
default:;
endcase
if (ara_req.op inside {VWREDSUMU, VWREDSUM}) begin
unique case (csr_vtype_q.vlmul)
LMUL_2: if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = 1'b1;
LMUL_4: if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = 1'b1;
LMUL_8: if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = 1'b1;
default:;
endcase
end else begin
unique case (ara_req.emul)
LMUL_2: if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000 ||
(insn.varith_type.rs2 & 5'b00001) != 5'b00000 ||
(insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = 1'b1;
LMUL_4: if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000 ||
(insn.varith_type.rs2 & 5'b00011) != 5'b00000 ||
(insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = 1'b1;
LMUL_8: if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000 ||
(insn.varith_type.rs2 & 5'b00111) != 5'b00000 ||
(insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = 1'b1;
default:;
endcase
end

// Instruction is invalid if the vtype is invalid
if (csr_vtype_q.vill) illegal_insn = 1'b1;
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