[seveibar]

Status: this RFC is an isolated experiment, not a production routing implementation. The concrete solver implementation and fresh 47/47 DDR routing proof are now tracked in bus-lanes-solver #102. That PR does not yet implement automatic capacitor relocation or establish whole-board completion.

DDR routing can fail before carrier search because nearby decouplers leave no legal BGA escape. This proposes a bounded placement preflight that moves only eligible capacitors, verifies a collective escape assignment, and passes owned escape reservations to downstream routing.

Includes an executable experimental planner, a six-layer AM3352 fixture with RAM at (0, -25) mm, native validation reports, integration/rollout details, and reproduction instructions. Production routing defaults are unchanged; the experiment directory is excluded from the library TypeScript project.

Independent evidence

• A control retaining the previous manual capacitor nudges already had feasible escapes; no improvement there.
• On the new-layout regression with those nudges removed, the planner recovered joint 47/47 escape feasibility from 45/47 individually escapable connections. It independently selected C_U1_K8 +0.3 mm Y and C_DDR11 +0.5 mm Y in 97 assessments / 176.185 seconds.
• The complete-DDR control failed escape assignment in 1.559 seconds. After planning, it advanced to shared-layer routing but timed out at 120 seconds.
• A fresh 11-connection byte lane passed all 11 native checks and the length/skew/clearance checks. Neither all 47 DDR connections nor the whole board completed.

Validation and limits

The planner test and targeted strict TypeScript check pass. The fixture uses a different placement of the earlier populated AM3352 circuit, including USB and power circuitry; it is not a new schematic. Both proposal experiments use the same pinned solver plus a disclosed common investigation patch, so these results are not a clean-upstream speed benchmark. The other proposal's supervisor is not used here.

This remains draft: the requested independent complete-board proof is still outstanding. The proposal also requires decoupling electrical constraints, persisted escape reservations, faster incremental assessment, and held-out complete-board regressions before rollout.

See proposal and reproduction instructions and machine-readable evidence.

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Project	Deployment	Actions	Updated
tscircuit-core-benchmarks	Ready	Preview	Oct 27, 2026 6:36am UTC