Release Candidate v2.73.0

.github/workflows/surf_ci.yml

@@ -27,9 +27,9 @@ jobs:
     runs-on: ubuntu-24.04
 
     steps:
-      - uses: actions/checkout@v4
+      - uses: actions/checkout@9c091bb21b7c1c1d1991bb908d89e4e9dddfe3e0 # v7.0.0
 
-      - uses: actions/setup-python@v5
+      - uses: actions/setup-python@ece7cb06caefa5fff74198d8649806c4678c61a1 # v6.3.0
         with:
           python-version: 3.12
 
@@ -83,9 +83,9 @@ jobs:
     runs-on: ubuntu-24.04
 
     steps:
-      - uses: actions/checkout@v4
+      - uses: actions/checkout@9c091bb21b7c1c1d1991bb908d89e4e9dddfe3e0 # v7.0.0
 
-      - uses: actions/setup-python@v5
+      - uses: actions/setup-python@ece7cb06caefa5fff74198d8649806c4678c61a1 # v6.3.0
         with:
           python-version: 3.12
 
@@ -107,7 +107,7 @@ jobs:
       - name: Parallel Regression Tests
         run: |
           make MODULES=$PWD import
-          python -m pytest --cov -v -n auto --dist=worksteal tests/axi tests/base tests/dsp tests/protocols
+          python -m pytest --cov -v -n auto --dist=worksteal tests/axi tests/base tests/dsp tests/protocols tests/ethernet/RoCEv2 tests/ethernet/UdpEngine
 
       - name: Code Coverage
         run: |
@@ -121,7 +121,7 @@ jobs:
     runs-on: ubuntu-24.04
 
     steps:
-      - uses: actions/checkout@v4
+      - uses: actions/checkout@9c091bb21b7c1c1d1991bb908d89e4e9dddfe3e0 # v7.0.0
 
       - name: Install documentation tools
         run: |
@@ -134,7 +134,7 @@ jobs:
 
       - name: Deploy Documentation
         if: startsWith(github.ref, 'refs/tags/')
-        uses: peaceiris/actions-gh-pages@v3
+        uses: peaceiris/actions-gh-pages@84c30a85c19949d7eee79c4ff27748b70285e453 # v4.1.0
         with:
           github_token: ${{ secrets.GH_TOKEN }}
           publish_dir: doxygen/html

axi/axi-lite/rtl/AxiDualPortRam.vhd

@@ -3,6 +3,13 @@
 -------------------------------------------------------------------------------
 -- Description: A wrapper of StdLib DualPortRam that places an AxiLite
 -- interface on the read/write port.
+--
+-- Supported RAM memory configurations:
+--
+--    SYNTH_MODE_G                 |    MEMORY_TYPE_G   | READ_LATENCY_G
+-- "xpm", "altera_mf", "inferred" | "block" or "ultra" |      1 ~ 3
+--       "xpm"                     |  "distributed"     |      0 ~ 3
+--       "inferred"                |  "distributed"     |      0 ~ 1
 -------------------------------------------------------------------------------
 -- This file is part of 'SLAC Firmware Standard Library'.
 -- It is subject to the license terms in the LICENSE.txt file found in the
@@ -82,6 +89,8 @@ architecture rtl of AxiDualPortRam is
    constant RAM_WIDTH_C      : natural := ADDR_AXI_WORDS_C*32;
    constant STRB_WIDTH_C     : natural := minimum(4, ADDR_AXI_BYTES_C);
 
+   constant RAM_READ_LATENCY_C : natural := ite(SYNTH_MODE_G = "xpm", READ_LATENCY_G, ite(READ_LATENCY_G >= 2, 2, 1));
+
    type StateType is (
       IDLE_S,
       RD_S);
@@ -118,88 +127,55 @@ architecture rtl of AxiDualPortRam is
 
 begin
 
-   ------------------------------------------------------------
-   --       Supported RAM memory configurations
-   ------------------------------------------------------------
-   --    SYNTH_MODE_G     |    MEMORY_TYPE_G   | READ_LATENCY_G
-   ------------------------------------------------------------
-   -- "XPM" or "inferred" | "block" or "ultra" |      1 ~ 3
-   ------------------------------------------------------------
-   --       "XPM"         |  "distributed"     |      0 ~ 3
-   ------------------------------------------------------------
-   --       "inferred"    |  "distributed"     |      0 ~ 1
-   ------------------------------------------------------------
    assert
       (MEMORY_TYPE_G /= "distributed" and (READ_LATENCY_G >= 1 and READ_LATENCY_G      <= 3)) or
       (SYNTH_MODE_G = "xpm" and MEMORY_TYPE_G = "distributed" and (READ_LATENCY_G      <= 3)) or
       (SYNTH_MODE_G = "inferred" and MEMORY_TYPE_G = "distributed" and (READ_LATENCY_G <= 1))
       report "RAM memory configuration not supported" severity failure;
 
-   GEN_XPM : if (SYNTH_MODE_G = "xpm") generate
-      U_RAM : entity surf.TrueDualPortRamXpm
+   GEN_VENDOR : if (SYNTH_MODE_G /= "inferred") generate
+      U_RAM : entity surf.TrueDualPortRam
          generic map (
             TPD_G               => TPD_G,
             RST_POLARITY_G      => RST_POLARITY_G,
+            SYNTH_MODE_G        => SYNTH_MODE_G,
             COMMON_CLK_G        => COMMON_CLK_G,
             MEMORY_TYPE_G       => MEMORY_TYPE_G,
             MEMORY_INIT_FILE_G  => MEMORY_INIT_FILE_G,
             MEMORY_INIT_PARAM_G => MEMORY_INIT_PARAM_G,
-            WRITE_MODE_G        => ite(MEMORY_TYPE_G = "distributed", "read_first", "no_change"),
-            READ_LATENCY_G      => READ_LATENCY_G,
+            MODE_G              => ite(MEMORY_TYPE_G = "distributed", "read-first", "no-change"),
+            READ_LATENCY_G      => RAM_READ_LATENCY_C,
+            READ_LATENCY_A_G    => RAM_READ_LATENCY_C,
+            READ_LATENCY_B_G    => RAM_READ_LATENCY_C,
             DATA_WIDTH_G        => DATA_WIDTH_G,
             BYTE_WR_EN_G        => true,
             BYTE_WIDTH_G        => 8,
             ADDR_WIDTH_G        => ADDR_WIDTH_G)
          port map (
             -- Port A
-            clka  => axiClk,
-            ena   => '1',
-            wea   => r.axiWrStrobe(ADDR_AXI_BYTES_C-1 downto 0),
-            rsta  => NOT_RST_C,
-            addra => r.axiAddr,
-            dina  => axiWrDataFanout(DATA_WIDTH_G-1 downto 0),
-            douta => axiDout(DATA_WIDTH_G-1 downto 0),
-            -- Port B
-            clkb  => clk,
-            enb   => en,
-            web   => weByteMask,
-            rstb  => NOT_RST_C,
-            addrb => addr,
-            dinb  => din,
-            doutb => doutInt);
-   end generate;
-
-   GEN_ALTERA : if (SYNTH_MODE_G = "altera_mf") generate
-      U_RAM : entity surf.TrueDualPortRamAlteraMf
-         generic map (
-            TPD_G          => TPD_G,
-            RST_POLARITY_G => RST_POLARITY_G,
-            COMMON_CLK_G   => COMMON_CLK_G,
-            MEMORY_TYPE_G  => MEMORY_TYPE_G,
-            READ_LATENCY_G => READ_LATENCY_G,
-            DATA_WIDTH_G   => DATA_WIDTH_G,
-            BYTE_WR_EN_G   => true,
-            BYTE_WIDTH_G   => 8,
-            ADDR_WIDTH_G   => ADDR_WIDTH_G)
-         port map (
-            -- Port A
-            clka  => axiClk,
-            ena   => '1',
-            wea   => r.axiWrStrobe(ADDR_AXI_BYTES_C-1 downto 0),
-            rsta  => NOT_RST_C,
-            addra => r.axiAddr,
-            dina  => axiWrDataFanout(DATA_WIDTH_G-1 downto 0),
-            douta => axiDout(DATA_WIDTH_G-1 downto 0),
+            clka    => axiClk,
+            ena     => '1',
+            wea     => '1',
+            weaByte => r.axiWrStrobe(ADDR_AXI_BYTES_C-1 downto 0),
+            rsta    => NOT_RST_C,
+            addra   => r.axiAddr,
+            dina    => axiWrDataFanout(DATA_WIDTH_G-1 downto 0),
+            douta   => axiDout(DATA_WIDTH_G-1 downto 0),
             -- Port B
-            clkb  => clk,
-            enb   => en,
-            web   => weByteMask,
-            rstb  => NOT_RST_C,
-            addrb => addr,
-            dinb  => din,
-            doutb => doutInt);
-   end generate;
-
+            clkb    => clk,
+            enb     => en,
+            web     => we,
+            webByte => weByteMask,
+            rstb    => NOT_RST_C,
+            addrb   => addr,
+            dinb    => din,
+            doutb   => doutInt);
+   end generate GEN_VENDOR;
+
+   -- Keep the inferred read-only/simple-dual cases on DualPortRam for
+   -- compatibility. Those paths preserve the legacy inferred distributed RAM
+   -- behavior, including READ_LATENCY_G = 0 support, that the selector
+   -- wrappers intentionally do not imply.
    GEN_INFERRED : if (SYNTH_MODE_G = "inferred") generate
 
       -- AXI read only, sys writable or read only (rom)
@@ -270,16 +246,17 @@ begin
       AXI_RW_SYS_RW : if (AXI_WR_EN_G and SYS_WR_EN_G) generate
          U_TrueDualPortRam_1 : entity surf.TrueDualPortRam
             generic map (
-               TPD_G          => TPD_G,
-               RST_POLARITY_G => RST_POLARITY_G,
-               RST_ASYNC_G    => RST_ASYNC_G,
-               BYTE_WR_EN_G   => true,
-               DOA_REG_G      => ite(READ_LATENCY_G >= 2, true, false),
-               DOB_REG_G      => ite(READ_LATENCY_G >= 2, true, false),
-               DATA_WIDTH_G   => DATA_WIDTH_G,
-               BYTE_WIDTH_G   => 8,
-               ADDR_WIDTH_G   => ADDR_WIDTH_G,
-               INIT_G         => INIT_G)
+               TPD_G            => TPD_G,
+               RST_POLARITY_G   => RST_POLARITY_G,
+               RST_ASYNC_G      => RST_ASYNC_G,
+               BYTE_WR_EN_G     => true,
+               DATA_WIDTH_G     => DATA_WIDTH_G,
+               BYTE_WIDTH_G     => 8,
+               ADDR_WIDTH_G     => ADDR_WIDTH_G,
+               INIT_G           => INIT_G,
+               READ_LATENCY_G   => RAM_READ_LATENCY_C,
+               READ_LATENCY_A_G => RAM_READ_LATENCY_C,
+               READ_LATENCY_B_G => RAM_READ_LATENCY_C)
             port map (
                clka    => axiClk,                                    -- [in]
                ena     => '1',                                       -- [in]

axi/axi-lite/rtl/AxiLiteSequencerRam.vhd

@@ -86,6 +86,8 @@ architecture rtl of AxiLiteSequencerRam is
    constant AXI_RAM_ADDR_LOW_C  : integer := AXI_DEC_ADDR_RANGE_C'high+1;
    subtype AXI_RAM_ADDR_RANGE_C is integer range AXI_RAM_ADDR_HIGH_C downto AXI_RAM_ADDR_LOW_C;
 
+   constant RAM_READ_LATENCY_C : natural := ite(SYNTH_MODE_G = "inferred", ite(READ_LATENCY_G >= 2, 2, 1), READ_LATENCY_G);
+
    type StateType is (
       IDLE_S,
       S_AXI_RD_S,
@@ -138,6 +140,10 @@ architecture rtl of AxiLiteSequencerRam is
 
 begin
 
+   assert (SYNTH_MODE_G /= "inferred") or (READ_LATENCY_G >= 1)
+      report "AxiLiteSequencerRam: inferred mode requires READ_LATENCY_G >= 1"
+      severity failure;
+
    U_AxiLiteMaster : entity surf.AxiLiteMaster
       generic map (
          TPD_G          => TPD_G,
@@ -153,83 +159,34 @@ begin
          axilReadMaster  => mAxilReadMaster,
          axilReadSlave   => mAxilReadSlave);
 
-   GEN_XPM : if (SYNTH_MODE_G = "xpm") generate
-      U_RAM : entity surf.TrueDualPortRamXpm
-         generic map (
-            TPD_G               => TPD_G,
-            RST_POLARITY_G      => RST_POLARITY_G,
-            COMMON_CLK_G        => true,
-            MEMORY_TYPE_G       => MEMORY_TYPE_G,
-            MEMORY_INIT_FILE_G  => MEMORY_INIT_FILE_G,
-            MEMORY_INIT_PARAM_G => MEMORY_INIT_PARAM_G,
-            READ_LATENCY_G      => READ_LATENCY_G,
-            DATA_WIDTH_G        => 64,
-            BYTE_WR_EN_G        => true,
-            BYTE_WIDTH_G        => 8,
-            ADDR_WIDTH_G        => ADDR_WIDTH_G)
-         port map (
-            -- Port A
-            clka  => axilClk,
-            wea   => r.wstrb,
-            addra => r.addr,
-            dina  => r.din,
-            douta => dout,
-            -- Port B
-            clkb  => axilClk,
-            addrb => r.seqAddr,
-            doutb => seqData);
-   end generate;
-
-   GEN_ALTERA : if (SYNTH_MODE_G = "altera_mf") generate
-      U_RAM : entity surf.TrueDualPortRamAlteraMf
-         generic map (
-            TPD_G          => TPD_G,
-            RST_POLARITY_G => RST_POLARITY_G,
-            COMMON_CLK_G   => true,
-            MEMORY_TYPE_G  => MEMORY_TYPE_G,
-            READ_LATENCY_G => READ_LATENCY_G,
-            DATA_WIDTH_G   => 64,
-            BYTE_WR_EN_G   => true,
-            BYTE_WIDTH_G   => 8,
-            ADDR_WIDTH_G   => ADDR_WIDTH_G)
-         port map (
-            -- Port A
-            clka  => axilClk,
-            wea   => r.wstrb,
-            addra => r.addr,
-            dina  => r.din,
-            douta => dout,
-            -- Port B
-            clkb  => axilClk,
-            addrb => r.seqAddr,
-            doutb => seqData);
-   end generate;
-
-   GEN_INFERRED : if (SYNTH_MODE_G = "inferred") generate
-      U_RAM : entity surf.TrueDualPortRam
-         generic map (
-            TPD_G          => TPD_G,
-            RST_POLARITY_G => RST_POLARITY_G,
-            RST_ASYNC_G    => RST_ASYNC_G,
-            BYTE_WR_EN_G   => true,
-            DOA_REG_G      => ite(READ_LATENCY_G >= 2, true, false),
-            DOB_REG_G      => ite(READ_LATENCY_G >= 2, true, false),
-            DATA_WIDTH_G   => 64,
-            BYTE_WIDTH_G   => 8,
-            ADDR_WIDTH_G   => ADDR_WIDTH_G)
-         port map (
-            -- Port A
-            clka    => axilClk,
-            wea     => '1',
-            weaByte => r.wstrb,
-            addra   => r.addr,
-            dina    => r.din,
-            douta   => dout,
-            -- Port B
-            clkb    => axilClk,
-            addrb   => r.seqAddr,
-            doutb   => seqData);
-   end generate;
+   U_RAM : entity surf.TrueDualPortRam
+      generic map (
+         TPD_G               => TPD_G,
+         RST_POLARITY_G      => RST_POLARITY_G,
+         RST_ASYNC_G         => RST_ASYNC_G,
+         SYNTH_MODE_G        => SYNTH_MODE_G,
+         COMMON_CLK_G        => true,
+         MEMORY_TYPE_G       => MEMORY_TYPE_G,
+         MEMORY_INIT_FILE_G  => MEMORY_INIT_FILE_G,
+         MEMORY_INIT_PARAM_G => MEMORY_INIT_PARAM_G,
+         READ_LATENCY_G      => RAM_READ_LATENCY_C,
+         READ_LATENCY_A_G    => RAM_READ_LATENCY_C,
+         READ_LATENCY_B_G    => RAM_READ_LATENCY_C,
+         BYTE_WR_EN_G        => true,
+         DATA_WIDTH_G        => 64,
+         BYTE_WIDTH_G        => 8,
+         ADDR_WIDTH_G        => ADDR_WIDTH_G)
+      port map (
+         -- Port A
+         clka    => axilClk,
+         weaByte => r.wstrb,
+         addra   => r.addr,
+         dina    => r.din,
+         douta   => dout,
+         -- Port B
+         clkb    => axilClk,
+         addrb   => r.seqAddr,
+         doutb   => seqData);
 
    comb : process (ack, axilRst, dout, extSize, extStart, r, sAxilReadMaster,
                    sAxilWriteMaster, seqData) is