Sahil Maurya Research Scholar · A²DSL, SCEE ❝ Engineer by profession, poet by heart ❞ |
Ph.D. Research Scholar at the Advanced Architecture for Digital System Lab (A²DSL), School of Computing and Electrical Engineering, IIT Mandi, under Dr. Bikram Paul. 🔬 Research: VLSI design, hardware security, RISC-V architectures, post-quantum cryptography, and efficient FPGA/ASIC implementations — quantum-resistant cryptographic accelerators for NIST algorithms (CRYSTALS-Kyber, Dilithium) with optimized Power, Performance, and Area (PPA). 🎓 M.Tech Batch Topper — VLSI & Embedded Systems, IIIT Guwahati (CGPA 9.11, 1st Rank) Born in Lucknow — the City of Nawabs 🕌 — "a little old-school, hopelessly romantic, and forever in love with its tehzeeb."
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Four Tier-1 Conference Papers — expand for full details
| # | Year | Paper | Venue |
|---|---|---|---|
| 1 | 2027 | Reproducible Co-Design of Domain-Aware Sleep Switches & Staggered Wake-Up Schedules 🎤 Oral | VLSID 2027 |
| 2 | 2026 | Towards Efficient PQC: Optimized K2RED, Plantard & Approximate Modular Multipliers | IEEE ISVLSI 2026 |
| 3 | 2025 | Neuromorphic Adaptive Precision RISC-V Processor with Real-Time Precision Scaling — 40–52% ⚡ energy ↓ | IEEE HiPC 2025W |
| 4 | 2024 | Approximate Modular Multipliers for R-LWE on FPGAs & ASICs — 34% area ↓, 33% power ↓ | IEEE SILCON 2024 |
🎤 Full Publication Details (click to expand)
1. Reproducible Co-Design of Domain-Aware Sleep Switches and Staggered Wake-Up Schedules
- Venue: VLSI Design (VLSID 2027) — Tier-1 Conference
- Authors: Sahil Maurya, Om Maheshwari, Bikram Paul
- Status: ✅ Accepted for Oral Presentation 🎉
2. Towards Efficient Post-Quantum Cryptography: Implementations of Optimized K2RED, Plantard, and Approximate Modular Multipliers
- Venue: IEEE ISVLSI 2026 — Tier-1 Conference
- Authors: Sahil Maurya, Bikram Paul
- Status: Published · Certificate of Recognition 🏅
3. Neuromorphic Adaptive Precision RISC-V Processor with Real-Time Precision Scaling and Neuronal State Management
- Venue: IEEE HiPC 2025 Workshop (HiPCW) — Tier-1 Conference, Hyderabad
- Authors: Om Maheshwari, Sahil Maurya, Bikram Paul
- Highlight: First RISC-V processor with real-time precision scaling — 40–52% energy reduction
- DOI: 10.1109/HiPCW66559.2025.00026 · IEEE Xplore · PDF
4. Approximate Modular Multipliers for R-LWE Cryptosystems on FPGAs and ASICs
- Venue: IEEE Silchar Subsection Conference (SILCON 2024)
- Authors: Sahil Maurya, Babita Jajodia
- Highlight: 34% area reduction, 33% power savings with <1% accuracy loss
- DOI: 10.1109/SILCON63976.2024.10910421 · IEEE Xplore
📋 Complete Awards List (click to expand)
| 🎖️ Honor | Issuer | Year |
|---|---|---|
| Certificate of Recognition — IEEE ISVLSI 2026 (Tier-1) | IEEE Computer Society Annual Symposium on VLSI | 2026 |
| VLSID Fellow (Tier-1) — 3× consecutive | International Conference on VLSI Design | 2024–26 |
| Certificate of Participation — 32nd IEEE HiPC 2025 | IEEE HiPC, Hyderabad | 2025 |
| Batch Topper — M.Tech VLSI & Embedded Systems (CGPA 9.11, 1st Rank) | IIIT Guwahati | 2023 |
| 2nd Prize — Creative Writing Competition | EN-LIT, Lucknow University | — |
| Period | Institute | Degree | Score |
|---|---|---|---|
| 2025 – Present | IIT Mandi | Ph.D. Research Scholar, SCEE (A²DSL) | CGPA 8.33/10 |
| 2021 – 2023 | IIIT Guwahati | M.Tech, VLSI & Embedded Systems | CGPA 9.11 · Batch Topper 🥇 |
| 2017 – 2021 | University of Lucknow | B.Tech, ECE | 66.1% |
| 2014 – 2016 | UP Board | Higher Secondary & Secondary | 85% · 85% |
📜 Certifications (click to expand)
| 🏅 Certification | Issuer | Year |
|---|---|---|
| System Design Using Verilog HDL | Udemy | 2022 |
| VSD Static Timing Analysis — Parts 1 & 2 | Udemy | 2025 |
| Python for Data Science, AI & Development | Coursera | 2023 |
| Cadence RTL to GDS Flow | Entuple Technology | 2024 |
| VLSI Design Flow using Vivado | CoreEL / Xilinx | 2024 |
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| GF180nm Mixed-Signal ASIC |
SkyWater 130nm RISC-V SoC |
ASAP 7nm PQC Accelerator |
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| Nangate 45nm Synthesis |
RISC-V SoC Floorplan & Routing |
I/O Planning Full Adder |
🔬 Featured Research Project — Kyber NTT Accelerator (click to expand)
CRYSTALS-Kyber NTT Hardware Accelerator — Post-Quantum Cryptography · ASIC
- High-throughput, side-channel resistant NTT architecture
- 245 MHz clock · 1.28 Gbps throughput
- NIST-standardized PQC for quantum-resistant communication
Other projects: Toom-Cook Multipliers (FPGA) · Approximate Modular Multiplier (R-LWE) · IoT Weather Monitoring System
Technology · Shayari · Ishq · Zindagi
| Blog | Theme |
|---|---|
| Play with FPGA: A Love Letter to Reconfigurable Silicon ❤️ | Engineering · Failure · Love |
| Teaching Assistant — VL-401: RTL Design & Verification | Teaching · IIT Mandi |
🎧 Blog Platform Features (click to expand)
- 🎧 Audio narration — poori story sun sakte ho (Voice 1/2/3 sweet modes)
- 🎙 Podcast mode — 2-voice (Host ♀ + Storyteller ♂), Hindi/English dono
- 🅷 Hindi translation — koi bhi blog Hindi me padho/suno
- 📖 Book mode — page-by-page flipping jaise real book
- 🌓 Night/Light themes + backgrounds
- 👀 Live reader counter per blog
- 🔗 "Link copied ✓" share buttons (WhatsApp, X)
🏔️ IIT Mandi Moments (click to expand) — Kamand Valley, lab, campus life
Ph.D. life at IIT Mandi — moments from the Himalayas.
Joined IIT Mandi — A²DSL · Research Poster
🎓 IIITG Moments (click to expand) — convocation, campus, M.Tech life
M.Tech memories — the topper years at IIIT Guwahati.
IIITG Convocation 🎓 · Convocation Day · IIIT Guwahati Campus
🎉 Life Moments (click to expand) — lake views, friends, dreams
Lake View · Friends · Aviation Dream · With Arpit
Recent Moment
2021 ▶ B.Tech, ECE — University of Lucknow
2023 ▶ M.Tech Batch Topper — IIIT Guwahati (CGPA 9.11) 🥇
2024 ▶ VLSID Fellow · Cadence RTL→GDSII Certified
2025 ▶ Joined IIT Mandi — Ph.D., A²DSL (Dr. Bikram Paul)
▶ HiPC 2025 — Presented Neuromorphic RISC-V Paper
2026 ▶ ISVLSI 2026 — Certificate of Recognition
2027 ▶ VLSID 2027 — Oral Presentation (Upcoming) 🎤
🤝 Academic References (click to expand)
| Name | Role |
|---|---|
| Dr. Bikram Paul | Ph.D. Supervisor — Assistant Professor, SCEE, IIT Mandi |
| Dr. Babita Jajodia | M.Tech Supervisor — Assistant Professor, IIIT Guwahati |
| Dr. Rakesh Biswas | M.Tech Thesis Panelist, IIIT Guwahati |
| Dr. Siddharth Singh | B.Tech Supervisor — HOD, Lucknow University |
