[HW] A series of fixes - #353

Draft

mp-17 wants to merge 20 commits into

mainfrom

Commits on Jun 27, 2024

Rename CSRs in ara dispatcher

MaistoV
authored and
mp-17
committed
8d4fd75
Stall Ara upon operations on vector CSRs

MaistoV
authored and
mp-17
committed
9591d0d
Change "errors" to "exceptions"

MaistoV
authored and
mp-17
committed
893956d
Extend and fix Ara exception reporting from VLSU

MaistoV
authored and
mp-17
committed
594ae68
Set vstart=0 for succesful vector instructions

MaistoV
authored and
mp-17
committed
46883c8
[hardware] Fix vstart handling in dispatcher
mp-17
committed
61cf0ab
[hardware] :bug: Fix reshuffling bug in dispatcher
mp-17
committed
2c751e0
[hardware] :bug: Fix eew_q update during reshuffle
mp-17
committed
be2248d
[hardware] :bug: Suboptimal fix to reshuffle with LMUL > 1
mp-17
committed
6c0ff5e
[hardware] :bug: Fix reshuffle
mp-17
committed
880b60d
[hardware] :bug: Consider LMUL when deciding if to reshuffle vd
mp-17
committed
7f95d00
[hardware] Bump CVA6
mp-17
committed
5995015
Add time-multiplexing for VCPOP and VFIRST

moimfeld
authored and
mp-17
committed
5bf20c0
Mask Unit clean-up

moimfeld
authored and
mp-17
committed
eb35e0b
[hardware] :bug: Fix NP2 slide with unbalanced packets
mp-17
committed
0766174
[hardware] Check for LMUL legality only if corresponding vreg is used
mp-17
committed
c7f7621
[hardware] VMSBF does not go through VALU
mp-17
committed
edb3549
[apps] Add random insn generator for verification
mp-17
committed
60293d1

Commits on Aug 26, 2024

[hardware] :bug: Fix legality checks for vmadc/vmsbc
mp-17
committed
e99e7b6
[hardware] Add constraint on VLENB
mp-17
committed
765714c