Multi-group CachePool with coherence-free write-through private L1 cache

.gitignore

@@ -40,3 +40,9 @@ hardware/bootrom/bootrom.elf
 hardware/bootrom/bootrom.sv
 # Configuration auto-generated files
 config/cachepool.hjson
+
+sim.sh
+CLAUDE.md
+scratchpad.txt
+claude_doc
+temp

Bender.local

@@ -5,5 +5,5 @@
 overrides:
   axi:                { git: "https://github.com/pulp-platform/axi.git",                version: =0.39.1-beta   }
   register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8          }
-  Insitu-Cache:       { git: "https://github.com/pulp-platform/Insitu-Cache.git",       rev:     zexin/cachepool_dev  }
+
 

Bender.lock

@@ -42,8 +42,8 @@ packages:
     - scm
     - tech_cells_generic
   common_cells:
-    revision: 9ca8a7655f741e7dd5736669a20a301325194c28
-    version: 1.39.0
+    revision: 1281545696eb3fcba50ec5b4275993476a3c710e
+    version: 1.40.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -56,14 +56,14 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   dram_rtl_sim:
-    revision: fc831811ac0e1b374814f64bb7a53abd8e6171b4
+    revision: null
     version: null
     source:
-      Git: https://github.com/pulp-platform/dram_rtl_sim.git
+      Path: hardware/deps/dram_rtl_sim
     dependencies:
     - axi
   floo_noc:
-    revision: 97306733f33acbb646c7e403c03a674fc1404b44
+    revision: a7d46c0aed7475a02de94f888a25495ae74d706f
     version: null
     source:
       Git: https://github.com/pulp-platform/FlooNoC.git
@@ -96,6 +96,12 @@ packages:
       Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
     dependencies:
     - common_cells
+  hpdcache:
+    revision: null
+    version: null
+    source:
+      Path: ../cv-hpdcache
+    dependencies: []
   idma:
     revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e
     version: 0.6.5
@@ -109,10 +115,10 @@ packages:
     - obi
     - register_interface
   insitu-cache:
-    revision: fa761ddebc946f9b46509d84945bf41ee1a9ec49
+    revision: null
     version: null
     source:
-      Git: https://github.com/pulp-platform/Insitu-Cache.git
+      Path: ../Insitu-Cache
     dependencies:
     - axi
     - common_cells
@@ -150,10 +156,10 @@ packages:
     dependencies:
     - tech_cells_generic
   spatz:
-    revision: 944e9042379fbe1db69567655cffd7a2e260ff16
+    revision: null
     version: null
     source:
-      Git: https://github.com/pulp-platform/spatz.git
+      Path: hardware/deps/spatz
     dependencies:
     - axi
     - axi_riscv_atomics
@@ -165,8 +171,8 @@ packages:
     - riscv-dbg
     - tech_cells_generic
   tech_cells_generic:
-    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
-    version: 0.2.13
+    revision: 3a3de73632a06826b1bd9c65a0a2e92b32016845
+    version: 0.2.14
     source:
       Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:

Bender.yml

@@ -6,18 +6,20 @@ package:
   name: cachepool
 
 dependencies:
-  axi:                 { git: "https://github.com/pulp-platform/axi.git",                version: =0.39.1-beta         }
-  axi_riscv_atomics:   { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",  version: 0.7.0                }
-  common_cells:        { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.28.0               }
-  FPnew:               { git: "https://github.com/pulp-platform/cvfpu.git",              rev:     pulp-v0.1.3          }
-  register_interface:  { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8                }
-  riscv-dbg:           { git: "https://github.com/pulp-platform/riscv-dbg.git",          version: 0.7.0                }
-  tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11               }
-  Insitu-Cache:        { git: "https://github.com/pulp-platform/Insitu-Cache.git",       rev:     zexin/cachepool_dev  }
-  dram_rtl_sim:        { git: "https://github.com/pulp-platform/dram_rtl_sim.git",       rev:     cachepool            }
-  floo_noc:            { git: "https://github.com/pulp-platform/FlooNoC.git",            rev:     main                 }
-  cluster_icache:      { git: "https://github.com/pulp-platform/cluster_icache.git",     rev:     main                 }
-  spatz:               { git: "https://github.com/pulp-platform/spatz.git",              rev:     cachepool-32b        }
+  axi:                 { git: "https://github.com/pulp-platform/axi.git",                version: =0.39.1-beta            }
+  axi_riscv_atomics:   { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",  version: 0.7.0                   }
+  common_cells:        { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.28.0                  }
+  FPnew:               { git: "https://github.com/pulp-platform/cvfpu.git",              rev:     pulp-v0.1.3             }
+  register_interface:  { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8                   }
+  riscv-dbg:           { git: "https://github.com/pulp-platform/riscv-dbg.git",          version: 0.7.0                   }
+  tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11                  }
+  # Insitu-Cache:        { git: "https://github.com/pulp-platform/Insitu-Cache.git",       rev:     zexin/cachepool_dev  }
+  Insitu-Cache:        { git: "https://github.com/HHT1228/Insitu-Cache.git",             rev:     hohung/cachepool/wt-l1  }
+  hpdcache:            { git: "https://github.com/HHT1228/cv-hpdcache.git",              rev:     cachepool/no_coherence  }
+  dram_rtl_sim:        { git: "https://github.com/pulp-platform/dram_rtl_sim.git",       rev:     cachepool               }
+  floo_noc:            { git: "https://github.com/pulp-platform/FlooNoC.git",            rev:     main                    }
+  cluster_icache:      { git: "https://github.com/pulp-platform/cluster_icache.git",     rev:     main                    }
+  spatz:               { git: "https://github.com/pulp-platform/spatz.git",              rev:     cachepool-32b           }
 
 workspace:
   checkout_dir: "./hardware/deps"
@@ -41,6 +43,8 @@ sources:
   # Level 1
   - hardware/src/cachepool_pkg.sv
   - hardware/src/cachepool_cc.sv
+  # Private L1 data cache (per-core HPDcache wrapper) — must precede the tile
+  - hardware/src/cachepool_l1_ctrl.sv
   # Barrier
   - hardware/src/cachepool_tile_barrier.sv
   - hardware/src/cachepool_cluster_barrier.sv

Makefile

@@ -16,8 +16,8 @@ CACHEPOOL_DIR := $(shell git rev-parse --show-toplevel 2>/dev/null || echo $$CAC
 SOFTWARE_DIR ?= ${CACHEPOOL_DIR}/software
 
 # Host compilers (for DPI, simulators, tools)
-CXX ?= /usr/pack/gcc-11.2.0-af/linux-x64/bin/g++
-CC  ?= /usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc
+CXX := /usr/pack/gcc-11.2.0-af/linux-x64/bin/g++
+CC  := /usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc
 CXX_PATH ?= $(shell realpath -P $(CXX))
 CC_PATH  ?= $(shell realpath -P $(CC))
 GCC_LIB  ?= /usr/pack/gcc-11.2.0-af/linux-x64/lib64
@@ -147,7 +147,7 @@ $(BOOTROM_DIR)/bootdata.cc: $(SCRIPTS_DIR)/generate_bootdata.py $(HJSON_OUT)
 	${PYTHON} $< -c $(HJSON_OUT) -d $(BOOTROM_DIR) -t bootdata.cc.tpl -o $@
 
 $(BOOTROM_DIR)/bootrom.elf $(BOOTROM_DIR)/bootrom.dump $(BOOTROM_DIR)/bootrom.bin: \
-  $(BOOTROM_DIR)/bootrom.S $(BOOTROM_DIR)/bootdata_bootrom.cc $(BOOTROM_DIR)/bootrom.ld Makefile
+  $(BOOTROM_DIR)/bootrom.S $(BOOTROM_DIR)/bootdata_bootrom.cc $(BOOTROM_DIR)/bootrom.ld
 	riscv -riscv64-gcc-9.5.0 riscv64-unknown-elf-gcc \
 		-mabi=ilp32 -march=rv32imaf -static -nostartfiles \
 		-T$(BOOTROM_DIR)/bootrom.ld \
@@ -187,6 +187,20 @@ $(FLOO_NOC): install-floogen $(FLOO_CFG)
 clean-floonoc:
 	rm -f $(FLOO_NOC)
 
+#########################
+# Peripheral registers  #
+#########################
+# The LP1 (private-L1) CMO peripheral has one register slot per core.  The slot
+# count (NumLp1CmoRegs) is baked into the generated reg_pkg/reg_top/C-header by
+# regtool, so it must be regenerated whenever the config's core count changes --
+# analogous to update-floonoc for the mesh.  We force the regen (-B) because the
+# generated .sv/.h are committed and may be newer than the (unchanged) schema.
+PERIPH_REG_DIR ?= $(ROOT_DIR)/hardware/cachepool_peripheral
+
+.PHONY: update-periph-reg
+update-periph-reg:
+	$(MAKE) -C $(PERIPH_REG_DIR) -B all NUM_LP1_CMO_REGS=$(num_cores)
+
 ###########
 # DramSys #
 ###########
@@ -195,7 +209,7 @@ VSIM_FLAGS :=
 VSIM_BENDER =
 
 .PHONY: dram-build
-dram-build: $(DRAMSYS_PATH)/README.md dram-clean dram-config
+dram-build: $(DRAMSYS_PATH)/README.md dram-config
 	cd $(DRAMSYS_PATH) && \
 	if [ ! -d "build" ]; then \
 		mkdir build && cd build; \
@@ -358,34 +372,29 @@ clean.data:
 clean.sw:
 	rm -rf ${SOFTWARE_DIR}/build
 
+# Common CMake flags shared by sw and vsim targets.
+# vsim appends -DSNITCH_SIMULATOR to point tests at the compiled binary.
+SW_CMAKE_FLAGS = \
+  -DENABLE_CACHEPOOL_TESTS=${ENABLE_CACHEPOOL_TESTS} \
+  -DCACHEPOOL_DIR=$(CACHEPOOL_DIR) \
+  -DRUNTIME_DIR=${SOFTWARE_DIR} \
+  -DSPATZ_SW_DIR=$(SPATZ_SW_DIR) \
+  -DLLVM_PATH=${LLVM_INSTALL_DIR} \
+  -DGCC_PATH=${GCC_INSTALL_DIR} \
+  -DPYTHON=${PYTHON} \
+  -DBUILD_TESTS=ON
+
 .PHONY: sw
-sw: generate bootrom gen-data clean.sw
-	echo ${SOFTWARE_DIR}
+sw: generate bootrom gen-data
 	mkdir -p ${SOFTWARE_DIR}/build
-	cd ${SOFTWARE_DIR}/build && ${CMAKE} \
-	  -DENABLE_CACHEPOOL_TESTS=${ENABLE_CACHEPOOL_TESTS} \
-	  -DCACHEPOOL_DIR=$(CACHEPOOL_DIR) \
-	  -DRUNTIME_DIR=${SOFTWARE_DIR} \
-	  -DSPATZ_SW_DIR=$(SPATZ_SW_DIR) \
-	  -DLLVM_PATH=${LLVM_INSTALL_DIR} \
-	  -DGCC_PATH=${GCC_INSTALL_DIR} \
-	  -DPYTHON=${PYTHON} \
-	  -DBUILD_TESTS=ON .. && $(MAKE)
+	cd ${SOFTWARE_DIR}/build && ${CMAKE} ${SW_CMAKE_FLAGS} .. && $(MAKE)
 
 .PHONY: vsim
 vsim: generate bootrom gen-data dpi ${SIMBIN_DIR}/cachepool_cluster.vsim
-	echo ${SOFTWARE_DIR}
 	mkdir -p ${SOFTWARE_DIR}/build
-	cd ${SOFTWARE_DIR}/build && ${CMAKE} \
-	  -DENABLE_CACHEPOOL_TESTS=${ENABLE_CACHEPOOL_TESTS} \
-	  -DCACHEPOOL_DIR=$(CACHEPOOL_DIR) \
-	  -DRUNTIME_DIR=${SOFTWARE_DIR} \
-	  -DSPATZ_SW_DIR=$(SPATZ_SW_DIR) \
-	  -DLLVM_PATH=${LLVM_INSTALL_DIR} \
-	  -DGCC_PATH=${GCC_INSTALL_DIR} \
-	  -DPYTHON=${PYTHON} \
+	cd ${SOFTWARE_DIR}/build && ${CMAKE} ${SW_CMAKE_FLAGS} \
 	  -DSNITCH_SIMULATOR=${SIMBIN_DIR}/cachepool_cluster.vsim \
-	  -DBUILD_TESTS=ON .. && $(MAKE)
+	  .. && $(MAKE)
 
 .PHONY: clean
 clean: clean.sw clean.vsim clean.data
@@ -432,6 +441,7 @@ help:
 	@echo "*cache-init*:     source the insitu-cache environment (requires bender checkout)"
 	@echo "*bootrom*:        compile and generate the bootrom SystemVerilog module"
 	@echo "*update-floonoc*: regenerate FlooNoC package from FLOO_CFG (run after changing group count)"
+	@echo "*update-periph-reg*: regenerate the peripheral registers with NumLp1CmoRegs=num_cores (run after changing core count)"
 	@echo "*install-floogen*: install the floogen Python tool (required by update-floonoc)"
 	@echo "*clean-floonoc*:  remove the generated FlooNoC package"
 	@echo ""