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    • Northcape

      Public
      Implementation of the Northcape capability architecture in hardware (Bredi SoC) as well as its associated operating system (Skadi OS).
      C
      0000Updated Jul 20, 2026Jul 20, 2026
    • Code for our 2023 IEEE S&P Paper "The Leaky Web: Automated Discovery of Cross-Site Information Leaks in Browsers and the Web"
      Jupyter Notebook
      MIT License
      21600Updated Jul 16, 2026Jul 16, 2026
    • Code for our 2024 IEEE S&P Paper "To Auth or Not To Auth? A Comparative Analysis of the Pre- and Post-Login Security Landscape"
      TypeScript
      MIT License
      41320Updated Jul 16, 2026Jul 16, 2026
    • Code for our 2024 ACM AsiaCCS Paper "Who's Breaking the Rules? Studying Conformance to the HTTP Specifications and its Security Impact"
      Python
      MIT License
      21820Updated Jul 16, 2026Jul 16, 2026
    • C
      0000Updated Jun 15, 2026Jun 15, 2026
    • Open-source artifact for our 2026 IEEE S&P Paper "LeakyLinks: Measuring the Security and Privacy Risks of URL Scanning Services"
      Python
      MIT License
      0800Updated Jun 10, 2026Jun 10, 2026
    • Jupyter Notebook
      MIT License
      1000Updated May 23, 2026May 23, 2026
    • Crucible

      Public
      C
      1300Updated Apr 29, 2026Apr 29, 2026
    • TACO

      Public
      TACO Model Checker for Threshold Automata
      Rust
      Apache License 2.0
      2600Updated Apr 22, 2026Apr 22, 2026
    • trevex

      Public
      Automated Vulnerability Detection Framework for Transient Execution Vulnerabilities (IEEE S&P '26)
      C
      MIT License
      33500Updated Apr 17, 2026Apr 17, 2026
    • Artifact for the paper "RISCy Cache Coherence: Timer-Free Architectural Cache Attacks via Instruction/Data Cache Incoherence".
      C
      MIT License
      1700Updated Apr 13, 2026Apr 13, 2026
    • scase

      Public
      Automated Framework for recovering Secrets from Side-Channel Traces. (USENIX Security '25)
      C
      21400Updated Apr 12, 2026Apr 12, 2026
    • Artifact for the IEEE S&P 2025 paper: "Rapid Reversing of Non-Linear CPU Cache Slice Functions: Unlocking Physical Address Leakage"
      C
      42000Updated Apr 3, 2026Apr 3, 2026
    • Artifact for the paper "RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs".
      Verilog
      MIT License
      01000Updated Mar 16, 2026Mar 16, 2026
    • InstrSem

      Public
      Python
      1800Updated Mar 9, 2026Mar 9, 2026
    • RISCover

      Public
      Differential CPU fuzzing framework from the paper "RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RIS…
      Python
      MIT License
      32600Updated Mar 1, 2026Mar 1, 2026
    • StackWarp

      Public
      Proof-of-concept for the paper "StackWarp: Breaking AMD SEV-SNP Integrity via Deterministic Stack-Pointer Manipulation through the CPU’s Stack Engine" (USENIX S…
      C
      MIT License
      59900Updated Jan 30, 2026Jan 30, 2026
    • codeseal

      Public
      JavaScript
      BSD 3-Clause "New" or "Revised" License
      0000Updated Jan 20, 2026Jan 20, 2026
    • Vivado 2023.2 project built around the CVA6 RISC-V CPU and a software stack including u-boot and embedded linux.
      Tcl
      01400Updated Jan 7, 2026Jan 7, 2026
    • cva6

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      Assembly
      Other
      999000Updated Jan 7, 2026Jan 7, 2026
    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      100000Updated Jan 6, 2026Jan 6, 2026
    • Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
      C
      MIT License
      128910Updated Nov 10, 2025Nov 10, 2025
    • Architectural cache side channel fuzzer from the research paper "ExfilState: Automated Discovery of Timer-Free Cache Side Channels on ARM CPUs".
      C
      MIT License
      0800Updated Oct 14, 2025Oct 14, 2025
    • Artifact for the paper "ExfilState: Automated Discovery of Timer-Free Cache Side Channels on ARM CPUs".
      C
      MIT License
      1700Updated Oct 12, 2025Oct 12, 2025
    • StyleMail

      Public
      CSS
      0300Updated Sep 26, 2025Sep 26, 2025
    • Code for our 2025 ACM CCS Paper "Head(er)s Up! Detecting Security Header Inconsistencies in Browsers"
      Python
      Other
      0300Updated Sep 16, 2025Sep 16, 2025
    • Proof-of-concept implementation for the paper "Hammulator: Simulate Now - Exploit Later" (DRAMSec 2023)
      C
      MIT License
      21900Updated Sep 15, 2025Sep 15, 2025
    • C
      0000Updated Aug 7, 2025Aug 7, 2025
    • C
      0500Updated Jul 4, 2025Jul 4, 2025
    • IaC for Proxmox VE clusters.
      Python
      MIT License
      180100Updated Jun 5, 2025Jun 5, 2025
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