Document the timing diagrams for the WB bus as used in serv?

[filmil]

It seems that the user manual is missing the expected timing diagrams for the various bus transactions. It would be nice to have at least a pointer to the correct timing diagrams if they are sufficiently similar to WB. The simplified WB for the serving configuration does not have this, and it makes me a bit unsure on how to ack a transaction properly. It would be nice to know for sure without guesswork.

[olofk]

Good point. The instruction bus is somewhat described here https://serv.readthedocs.io/en/latest/internals.html#fetch but there is nothing simular for the data bus. It does work the same though. Peripherals are activated when they get an stb or cyc (these signals are technically different but treated as one signal in most simple wishbone devices) and raises ack for one cycle to terminate the transaction. For reads, the peripheral outputs valid data during the cycle when ack is raised.

[filmil]

Thanks for the comment.

One thing I'm not sure about is if there is some timing requirement between cyc = '1' and ack = '1'. Is there a required max delay between asserted cyc and asserted ack in the response? It is also unclear if it is possible to complete multiple back-to-back transactions while cyc = '1'.

And, the relationship between cyc and stb, since only stb is documented, but the interface has cyc. In any case, a diagram would go a long way to explain. I am grateful for the verbal explanation, but a diagram would really hammer the point in. Cheers!