SPI

[MMIO]	description
0xbf010000	SPI0
0xbf159000	SPI1

SPI transfers are split into a command part and a TX or RX part.

The number of command and TX/RX bytes are configured in TRXLEN and CONTROL. CS# is automatically asserted, and deasserted once the configured number of bytes have been transferred

Clocking

The SPI bit clock is derived from the clock generated in the clock controller: f_bits = f_spi0 / 8

f_spi0 is determined by the lower 3 bits in 0xbf50004c:

value	clock rate	comment
0	27 MHz	"slow" clock
3	400 MHz
4	13.5 MHz	"slow" clock / 2
7	200 MHz	default

Registers

offset	type	name	description
0x000	u32	TRXFIFO	FIFO access for TX/RX part. Accepts 32 bits at a time.
0x100	u32
0x104	u32
0x120	u32	TRXLEN	length of TX/RX part
0x124	u32	CONTROL	control register
0x140	u32	STATUS	status register
0x148	u32	CMDFIFO	write here to put a byte into the command FIFO

0x124: CONTROL

bits	bit mask	name	description
30	0x40000000		set to zero
29:24	0x3f000000		set to zero
21,13	0x00202000		?? (overlaps with the next definition -- probably a bug.)
21:16	0x003f0000		command length
15:14	0x0000c000		set to zero?
12:9	0x00001e00		set to zero
3	0x00000008		set to zero
2:0	0x00000007		3: perform TX transfer, 5: perform RX transfer

Notes:

• Full duplex is not possible. If RX and TX are used together, the effect is RX only
• If only GO is specified, command bytes are transferred as expected.

0x140: STATUS

bits	bit mask	name	description
16	0x00010000	BUSY	the controller is busy with a transfer
13:8	0x00003f00	TXLVL	TX FIFO level, max. 0x1f, filled by CMDFIFO and TRXFIFO writes
5:0	0x0000003f	RXLVL	RX FIFO level