fix(linalg): preserve half-kernel fallback on AVX-512 hosts

[lance-gatefixer]

Root cause

SIMD_SUPPORT reports one exclusive tier. An Avx512FP16 host therefore never reaches match arms limited to Avx2 | Avx512, and falls through to scalar f16/bf16 implementations whenever the optional Sapphire Rapids C object could not be compiled—even though the fallback x86 object is present.

Fix

• Centralize half-precision backend selection and route AVX-512 tiers to the fallback object only when its actual ISA requirements are available (F16C+FMA for f16, AVX2+FMA for bf16).
• Preserve the existing 1e-6 f16 L2 accuracy contract with lane-partitioned AVX2 reductions.
• Check cosine input lengths before every newly reachable FFI call and cover the selector with a host-independent dispatch matrix.

Validation

• cargo test --profile ci -p lance-linalg --lib --features fp16kernels (470 passed, 1 ignored)
• Forced both optional AVX-512 C builds to fail, then ran cargo test --profile ci -p lance-linalg --lib f16 --features fp16kernels (34 passed, 1 ignored)
• cargo clippy --all --tests --benches -- -D warnings
• cargo clippy -p lance-linalg --all-targets --features fp16kernels -- -D warnings
• cargo fmt --all -- --check

Fixes #8876

[lance-gatekeeper]

✅ Gate recommendation: approve.

The exclusive-tier fallback is fixed at the right boundary: native kernels remain preferred, each half type requires its emitted fallback ISA, and scalar remains the safe default. The testable selector covers the build/tier matrix, while the newly reachable path preserves the existing f16 accuracy and equal-length FFI contracts.