fix(linalg): make SIMD slice conversions baseline-safe

[lance-gatefixer]

Summary

• replace AVX-only x86 unaligned loads with baseline-safe pointer reads for the f32, f64, and i32 SIMD register types
• cover both slice and array conversions, plus the scalar gather fallback, on hosts without AVX
• preserve AVX code generation when the caller is compiled with AVX enabled, without adding a runtime branch to each load

Root cause

The safe From implementations delegated to SIMD::load_unaligned, whose x86_64 arms directly called AVX load intrinsics. A downstream generic x86_64 build could therefore reach an AVX instruction on a host that does not support AVX. Reading the register representation as plain unaligned data lets LLVM select instructions from the caller's actual CPU baseline instead.

Validation

• focused constructor and gather tests in the default build
• RUSTFLAGS='-C target-cpu=x86-64-v2' focused release tests under qemu-x86_64 -cpu Nehalem
• cargo test -p lance-linalg --lib (460 passed, 1 ignored)
• cargo fmt --all -- --check
• cargo clippy --all --tests --benches -- -D warnings

Fixes #8872

[lance-gatekeeper]

✅ Gate recommendation: approve.

The raw unaligned-register reads fix the safe constructor and scalar-gather load boundary while preserving exact lane data. Letting the compiler legalize the same bit copy for the caller baseline is preferable to per-load runtime detection because baseline builds stay safe and AVX-enabled callers retain a branch-free vector load.