Feature/a2a3 llvm#908
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Full binary ops coverage
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SummaryReview failed at stage Findings未生成结构化 findings，因为 review 过程提前失败。 Log Tail |
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Code Review
This pull request implements a direct pointer-based lowering pipeline for A3 (dav-c220-vec) targets, introducing the LowerPTOToUBufOps pass and corresponding LLVM lowering patterns. The code review identified several critical and high-severity issues that must be addressed: a syntax/compilation error in VPTOLLVMEmitter.cpp due to a leftover lambda block; multiple checks in ptoas.cpp and LowerPTOToUBufOps.cpp that restrict the pipeline to "a3" and break "a2" support; an overly restrictive check in VPTOLLVMEmitter.cpp that excludes "dav-c220-cube" and triggers invalid A5 DMA lowering; redundant dead loop generation when headRepeats is zero; and a typo in a macro name in VPTO.cpp.
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We already have some ST cases in test/tilelib-st. Maybe you can reuse them by just changing the target from a5 to a3.
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The naming of this test suite is not clear. I suggest reuse the TileOp ST cases we already have in tilelib-st, which will be completed soon.
For vpto level test, you should place them under the test/vpto directory.
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I can move these tests under test/tilelib-st if that is the preferred repository layout, but I’m worried we would lose clarity and potentially coverage.
The current pytest suite is a comprehensive PTODSL e2e sweep for the new A2/A3 VPTO elementwise path. It covers binary, unary, scalar, bitwise, shift, fused, log, and reciprocal ops across multiple dtypes and dispatch shapes.
My concern with test/tilelib-st is that the folder name is not very descriptive for this purpose: these are specifically PTODSL end-to-end tests for the A2/A3 VPTO lowering pipeline. Moving them there may make that less obvious.
If you still prefer the ST layout, I can migrate them, but I’d like to preserve the current breadth of coverage.
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Retriggering CI for latest head c80521f. |
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How many "non-elementwise" vector ops are left? (gather/scatter/reduce/...) Is it too big to also include them into this PR? |
deriveLoadCbufToCbControl / deriveLoadCbufToCaControl called the raw Type::getIntOrFloatBitWidth() accessor, which asserts on non-int/float element types (FP4 packed, hifloat8, f8, ...). In assert builds this crashed ptoas mid-pass (~60 VPTO/UB low-precision lit tests) with 'only integers and floats have a bitwidth'. Use pto::getPTOStorageElemBitWidth() instead, matching the sibling deriveLoadCbufToCaMxControl / deriveLoadCbufToCbMxControl functions and the rest of the codebase. The existing (elemBitWidth == 0 || % 8) guard already matches the helper's 0-on-unknown contract.
As you said, only the gather/scatter/reduce are missing. Not a large addition, I will add them in this PR. |
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Review: A2/A3 VPTO elementwise
Deep pass over the lowering (LowerPTOToUBufOps), the LLVM intrinsic emitter, the CLI/pipeline wiring, the ODS/verifiers/effects, and the PTODSL surface. Overall the A2/A3 elementwise path is well-built: the intrinsic emission is internally consistent with the design docs, the new ops (vaddrelu/vdup/vln) and the txor tmp-scratch effects modeling are correct, and most of the earlier Gemini review was against a stale commit and is addressed at HEAD.
The findings that stand out are all cases where this A2/A3 PR reaches into the shared A5 / VPTO device-emission path:
- P2
buildVPTOEmissionOptionsnow mis-targets A5 VPTO cube kernels (dav-c310-vecinstead ofdav-c310-cube). Inline onptoas.cpp:2651. - P2
usesCANN900Loweringflipped to unconditionalfalsedisables the CANN900 emitter for all targets/CANN versions, not just A3. Inline onVPTOLLVMEmitterDispatcher.cpp:15. - P2 The lowering silently drops each tile's valid-shape, so the valid-shape-aware dispatch modes (and the lit tests named after them) are effectively dead, and every op processes padding. Inline on
LowerPTOToUBufOps.cpp:252. - P3 The PTODSL native launch-wrapper compile doesn't receive
target_arch. Inline ontoolchain.py:173.
Verified clean (not bugs at HEAD)
txor'stmpis a required operand and WRITE-modeled ingetEffects; PlanMemory gives it a distinct buffer andLowerPTOToUBufOpsdecomposestxoratomically -> no aliasing/missing-sync bug (the recurring scratch-effect bug class is not present here).taddreluA2/A3-only:TAddReluOp::verify+dispatchVerifierByArchreject a5, and the dtype gatei16/f16/f32matches the availableVADDRELUintrinsics; PTODSL has a trace-time guard plus negative tests.vaddrelu/vdup/vlnintrinsic names, operand order, and config-word layouts match the design doc and the lit tests; the CBuf storage-bit-width fix (2ca1095) is sound.- Gemini's
== "dav-c220-vec"cube-exclusion flag is a false alarm: the elementwise op-pattern/legality sites (10994/11166) are vector-only by design andmarchis neverdav-c220-cubeon this path. Gemini's leftover-lambda compile error andVERITYtypo were on a stale commit and are not present at HEAD.
Lower-priority notes
- UB op verifiers only check the UB memory-role, not that
dst/srcshare element type/shape; a hand-written.ptowith mismatched pointer element types picks the intrinsic fromsrc0and miscompiles with no diagnostic (VPTOLLVMEmitter.cpp:4744). Compiler-generated IR is always consistent, so this is a robustness gap. set_maskhardware state is written byUBSetMask*but not read by the compute ops, so ordering is positional only; safe today (no scheduler on this IR post-lowering) but latent if one is added.vduprejects bf16 (clean compile error, not a miscompile); scalar-tile bf16 would pass an i64 bit-pattern toVMULS.bf16(out of scope per doc, unguarded)._ptoas_build_backend:build_editable(skip_install=True)no longer validates the runtime payload landed where the.pthpoints;_find_llvm_dirauto-probe may select an Ascend-shipped LLVM over the vpto-patched one on env-unset machines.
CI
The Codex review bot failed on INSUFFICIENT_BALANCE (not a code signal). No CI checks are reported on the branch, and the PR is currently CONFLICTING with main.
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I found five correctness issues while reviewing the A2/A3 VPTO lowering and PTODSL integration. Inline details and reproductions are included below.
# Conflicts: # tools/ptoas/ptoas.cpp
# Conflicts: # lib/PTO/Transforms/VPTOExpandWrapperOps.cpp
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Review update:
The two test-layout discussions remain open intentionally. @Zhendong404, please re-review the refreshed head. |
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@learning-chip I have a parallel PR adding gather ops (castigli#2). I will do the same for scatter and reduce. However, given the cost keeping in sync with main, I would prefer to merge this PR first as it is and have 3 small follow ups for the missing vector ops. Is that OK? |
This is ok for me -- @zhangstevenunity ok to merge this? |
A3 板测失败
失败用例
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A3 板测失败详情：PR #908comm_p2p_binding_variants
comm_p2p
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A5 板测成功
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A2/A3 VPTO Elementwise PR Summary
Summary
This branch adds the A2/A3 VPTO UB lowering path for tile elementwise operations and validates it end-to-end on A3 hardware. The implementation routes A2/A3 through the planned-memory UB pipeline (from A5 pipeline), lowers supported PTO tile ops to VPTO UB ops, and emits LLVM intrinsics.
What Changed
PTOViewToMemref -> PTOPlanMemory -> PTOResolveReservedBuffers -> PTOMaterializeTileHandles -> LowerPTOToUBufOps.tadd,tsub,tmul,tdiv,tmax,tmin,tand,tor,txor,tshls, andtshrs.tabs,trelu,tneg,texp,tlog,tsqrt,trsqrt, andtrecip.tadds,tmuls,tmaxs, andtmins.taddrelu, including PTO IR, UB IR, lowering, LLVM intrinsic emission, PTODSL wrappers, and tests.vaddrelu,vdup, andvln.alloc_tile addrvalues and models scratch usage for ops such astxor.pto.tile.*APIs.Validation
Verified after merging current
mainwith the LLVM 21 docker image:60/604/480/80192/192120/120Total A2/A3 shared VPTO elementwise hardware coverage validated on A3:
392tests.