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@hkustgz-zhang-lab

ZHANG-LAB

Synthesis and Verification Group in HKUST(GZ)

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  1. HW-Formal-Paper HW-Formal-Paper Public

    Recent papers related to hardware formal verification.

    78 12

  2. ABCPaperCheck ABCPaperCheck Public

    Research paper based on or related to ABC.

    74 13

  3. Forbench Forbench Public

    [ICCAD'26] Forbench: Symbolic Simulation Helps Make Your Testbench More Formal

    Verilog 15 1

  4. eqcheck-script eqcheck-script Public

    Some notes regarding equivalence checking using Yosys and ABC

    8

  5. eqguide eqguide Public

    Logic Equivalence Checking Tool

    C++ 8

  6. FORWORD FORWORD Public

    Forked from yangziyiiii/FORWORD

    [DATE 2026] FORWORD: Accelerating Formal Datapath Verification via Word-Level Sweeping

    Verilog 6

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