GitHub - fusesoc/fusesoc-public: Public library of FuseSoC cores · GitHub

Name		Name	Last commit message	Last commit date
README.md		README.md
award-winning_openrisc_or1k_bootloaders_0.9.1.core		award-winning_openrisc_or1k_bootloaders_0.9.1.core
award-winning_openrisc_or1k_bootloaders_0.9.1.core.sig		award-winning_openrisc_or1k_bootloaders_0.9.1.core.sig
award-winning_serv_serv_1.3.0.core		award-winning_serv_serv_1.3.0.core
award-winning_serv_serv_1.3.0.core.sig		award-winning_serv_serv_1.3.0.core.sig
award-winning_serv_serv_1.4.0.core		award-winning_serv_serv_1.4.0.core
award-winning_serv_servant_1.3.0.core		award-winning_serv_servant_1.3.0.core
award-winning_serv_servant_1.3.0.core.sig		award-winning_serv_servant_1.3.0.core.sig
award-winning_serv_servant_1.4.0.core		award-winning_serv_servant_1.4.0.core
award-winning_serv_servile_1.3.0.core		award-winning_serv_servile_1.3.0.core
award-winning_serv_servile_1.3.0.core.sig		award-winning_serv_servile_1.3.0.core.sig
award-winning_serv_servile_1.4.0.core		award-winning_serv_servile_1.4.0.core
award-winning_serv_serving_1.4.0.core		award-winning_serv_serving_1.4.0.core
award-winning_soc_subservient_0.2.2.core		award-winning_soc_subservient_0.2.2.core
award-winning_soc_underserved_0.1.0.core		award-winning_soc_underserved_0.1.0.core
award-winning_utils_1_cdc_utils_0.1.0.core		award-winning_utils_1_cdc_utils_0.1.0.core
award-winning_utils_1_cdc_utils_0.1.0.core.sig		award-winning_utils_1_cdc_utils_0.1.0.core.sig
award-winning_utils_1_fifo_1.3.0.core		award-winning_utils_1_fifo_1.3.0.core
award-winning_utils_1_fifo_1.3.0.core.sig		award-winning_utils_1_fifo_1.3.0.core.sig
award-winning_utils_1_spi_ram_loader_0.0.1.core		award-winning_utils_1_spi_ram_loader_0.0.1.core
award-winning_utils_1_stream_utils_1.3.0.core		award-winning_utils_1_stream_utils_1.3.0.core
award-winning_utils_1_stream_utils_1.3.0.core.sig		award-winning_utils_1_stream_utils_1.3.0.core.sig
award-winning_utils_cdc_utils_0.1.0.core		award-winning_utils_cdc_utils_0.1.0.core
award-winning_utils_cdc_utils_0.1.0.core.sig		award-winning_utils_cdc_utils_0.1.0.core.sig
award-winning_utils_spi_ram_loader_0.0.2.core		award-winning_utils_spi_ram_loader_0.0.2.core
award-winning_wishbone_wb_bfm_1.2.1.core		award-winning_wishbone_wb_bfm_1.2.1.core
award-winning_wishbone_wb_bfm_1.2.1.core.sig		award-winning_wishbone_wb_bfm_1.2.1.core.sig
award-winning_wishbone_wb_common_1.0.3.core		award-winning_wishbone_wb_common_1.0.3.core
award-winning_wishbone_wb_common_1.0.3.core.sig		award-winning_wishbone_wb_common_1.0.3.core.sig
award-winning_wishbone_wb_intercon_1.4.2.core		award-winning_wishbone_wb_intercon_1.4.2.core
award-winning_wishbone_wb_ram_1.1.0.core		award-winning_wishbone_wb_ram_1.1.0.core
bespoke-silicon-group_basejump_stl_hard_0.0.1.core		bespoke-silicon-group_basejump_stl_hard_0.0.1.core
bespoke-silicon-group_basejump_stl_hard_0.0.1.core.sig		bespoke-silicon-group_basejump_stl_hard_0.0.1.core.sig
bespoke-silicon-group_basejump_stl_nonsynth_0.0.1.core		bespoke-silicon-group_basejump_stl_nonsynth_0.0.1.core
bespoke-silicon-group_basejump_stl_nonsynth_0.0.1.core.sig		bespoke-silicon-group_basejump_stl_nonsynth_0.0.1.core.sig
bespoke-silicon-group_basejump_stl_rtl_0.0.1.core		bespoke-silicon-group_basejump_stl_rtl_0.0.1.core
bespoke-silicon-group_basejump_stl_rtl_0.0.1.core.sig		bespoke-silicon-group_basejump_stl_rtl_0.0.1.core.sig
bmartini__1_verilog-arbiter_0.0.0.core		bmartini__1_verilog-arbiter_0.0.0.core
bmartini__1_verilog-arbiter_0.0.0.core.sig		bmartini__1_verilog-arbiter_0.0.0.core.sig
bmartini__verilog-arbiter_0.0.0.core		bmartini__verilog-arbiter_0.0.0.core
bmartini__verilog-arbiter_0.0.0.core.sig		bmartini__verilog-arbiter_0.0.0.core.sig
bsg-external__1_hardfloat_0.0.1.core		bsg-external__1_hardfloat_0.0.1.core
bsg-external__1_hardfloat_0.0.1.core.sig		bsg-external__1_hardfloat_0.0.1.core.sig
bsg-external__2_hardfloat_0.0.1.core		bsg-external__2_hardfloat_0.0.1.core
bsg-external__2_hardfloat_0.0.1.core.sig		bsg-external__2_hardfloat_0.0.1.core.sig
bsg-external__hardfloat_0.0.1.core		bsg-external__hardfloat_0.0.1.core
bsg-external__hardfloat_0.0.1.core.sig		bsg-external__hardfloat_0.0.1.core.sig
fusesoc_utils_blinky_1.1.0.core		fusesoc_utils_blinky_1.1.0.core
fusesoc_utils_blinky_1.1.0.core.sig		fusesoc_utils_blinky_1.1.0.core.sig
fusesoc_utils_generators_0.1.7.core		fusesoc_utils_generators_0.1.7.core
fusesoc_utils_generators_0.1.7.core.sig		fusesoc_utils_generators_0.1.7.core.sig
fusesoc_utils_vlog_tb_utils_1.1.0.core		fusesoc_utils_vlog_tb_utils_1.1.0.core
fusesoc_utils_vlog_tb_utils_1.1.0.core.sig		fusesoc_utils_vlog_tb_utils_1.1.0.core.sig
iobundle_py2hwsw_iob_cache_axi_0.7.1.core		iobundle_py2hwsw_iob_cache_axi_0.7.1.core
iobundle_py2hwsw_iob_cache_axi_0.7.1.core.sig		iobundle_py2hwsw_iob_cache_axi_0.7.1.core.sig
iobundle_py2hwsw_iob_cache_iob_0.7.1.core		iobundle_py2hwsw_iob_cache_iob_0.7.1.core
iobundle_py2hwsw_iob_cache_iob_0.7.1.core.sig		iobundle_py2hwsw_iob_cache_iob_0.7.1.core.sig
iobundle_py2hwsw_iob_eth_0.1.0.core		iobundle_py2hwsw_iob_eth_0.1.0.core
iobundle_py2hwsw_iob_eth_0.1.0.core.sig		iobundle_py2hwsw_iob_eth_0.1.0.core.sig
iobundle_py2hwsw_iob_uart16550_0.1.5.core		iobundle_py2hwsw_iob_uart16550_0.1.5.core
iobundle_py2hwsw_iob_uart16550_0.1.5.core.sig		iobundle_py2hwsw_iob_uart16550_0.1.5.core.sig
open-logic_open-logic_axi_3.3.0.core		open-logic_open-logic_axi_3.3.0.core
open-logic_open-logic_axi_3.3.0.core.sig		open-logic_open-logic_axi_3.3.0.core.sig
open-logic_open-logic_base_3.3.0.core		open-logic_open-logic_base_3.3.0.core
open-logic_open-logic_base_3.3.0.core.sig		open-logic_open-logic_base_3.3.0.core.sig
open-logic_open-logic_en_cl_fix_2.2.0.core		open-logic_open-logic_en_cl_fix_2.2.0.core
open-logic_open-logic_en_cl_fix_2.2.0.core.sig		open-logic_open-logic_en_cl_fix_2.2.0.core.sig
open-logic_open-logic_fix_3.3.0.core		open-logic_open-logic_fix_3.3.0.core
open-logic_open-logic_fix_3.3.0.core.sig		open-logic_open-logic_fix_3.3.0.core.sig
open-logic_open-logic_intf_3.3.0.core		open-logic_open-logic_intf_3.3.0.core
open-logic_open-logic_intf_3.3.0.core.sig		open-logic_open-logic_intf_3.3.0.core.sig
open-logic_tutorials_olo_fix_tutorial_3.3.0.core		open-logic_tutorials_olo_fix_tutorial_3.3.0.core
open-logic_tutorials_olo_fix_tutorial_3.3.0.core.sig		open-logic_tutorials_olo_fix_tutorial_3.3.0.core.sig
open-logic_tutorials_quartus_tutorial_3.3.0.core		open-logic_tutorials_quartus_tutorial_3.3.0.core
open-logic_tutorials_quartus_tutorial_3.3.0.core.sig		open-logic_tutorials_quartus_tutorial_3.3.0.core.sig
open-logic_tutorials_vivado_tutorial_3.3.0.core		open-logic_tutorials_vivado_tutorial_3.3.0.core
open-logic_tutorials_vivado_tutorial_3.3.0.core.sig		open-logic_tutorials_vivado_tutorial_3.3.0.core.sig
pulp-platform__2_common_cells_1.20.0.core		pulp-platform__2_common_cells_1.20.0.core
pulp-platform__2_common_cells_1.20.0.core.sig		pulp-platform__2_common_cells_1.20.0.core.sig
pulp-platform__common_cells_1.20.0.core		pulp-platform__common_cells_1.20.0.core
pulp-platform__common_cells_1.20.0.core.sig		pulp-platform__common_cells_1.20.0.core.sig
sifferman__ternip_0.1.0.core		sifferman__ternip_0.1.0.core

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