Minor power and port direction fixes

[mole99]

I just noticed that I never sent these fixes when I was working on Panamax FPGA.

[RTimothyEdwards]

Everything looks good except for sio_vohref. This is definitely an input in the SIO pad module. Is there a reason behind that change?

[mole99]

I need to check that, it's been quite a while ^^
I'll probably get around to it after ORConf.

[mole99]

I took a closer look and now remember: Yosys ties all undriven signals low by default in LibreLane. This would apply to sio_vohref and some of the other signals.
Therefore, all analog signals are set to inout to make it clear that they are analog and should not be driven (since the wiring is added manually).

At ORConf we were discussing how analog routing could be automated in OpenROAD: It seems with a Non Default Rule (NDR) and the set_nets_to_route command during global route, it should be possible to first route all analog wires (we need to set don't touch to prevent buffer insertion) and then route all digital wires afterwards. This way we can keep the analog connections in the netlist, convenient for LVS afterwards.