Rename oneAPI backend to Altera, remove oneAPI compatibility

README.md

@@ -55,7 +55,7 @@ hls4ml.utils.fetch_example_list()
 ```
 
 ### Building a project.
-We will build the project using Xilinx Vivado HLS, which can be downloaded and installed from [here](https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html). Alongside Vivado HLS, hls4ml also supports Vitis HLS, Intel HLS, Catapult HLS and has some experimental support dor Intel oneAPI. The target back-end can be changed using the argument backend when building the model.
+We will build the project using Xilinx Vivado HLS, which can be downloaded and installed from [here](https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html). Alongside Vivado HLS, hls4ml also supports Vitis HLS, Intel HLS, Catapult HLS and has experimental support for the Altera backend. The target back-end can be changed using the argument backend when building the model.
 
 ```Python
 # Use Vivado HLS to synthesize the model

docs/api/configuration.rst

@@ -54,7 +54,7 @@ for Keras models:
         model,
         granularity='name',
         default_precision='fixed<16,6>',
-        backend='oneAPI')
+        backend='Altera')
 
 or for PyTorch models:
 

docs/backend/oneapi.rst → docs/backend/altera.rst

@@ -1,24 +1,28 @@
 ======
-oneAPI
+Altera
 ======
 
-The **oneAPI** backend of hls4ml is designed for deploying NNs on Intel/Altera FPGAs. It will eventually
-replace the **Quartus** backend, which targeted Intel HLS. (Quartus continues to be used with IP produced by the
-**oneAPI** backend.) This section discusses details of the **oneAPI** backend.
+The **Altera** backend of hls4ml is designed for deploying neural networks on Intel/Altera FPGAs.
+It is based on the SYCL FPGA flow that was previously provided through **Intel oneAPI** and is now continued
+by the **Altera HLS IP Gen** toolchain. The functionality and terminology used by hls4ml remain largely unchanged.
 
-The **oneAPI** code uses SYCL kernels to implement the logic that is deployed on FPGAs. It naturally leads to the
+The **Altera** backend is intended to supersede the **Quartus** backend, which targets the discontinued
+Intel HLS Compiler. Quartus Prime continues to be used to integrate the IP generated by the Altera HLS IP Gen flow
+into FPGA designs.
+
+The **Altera** backend uses SYCL kernels to implement the logic that is deployed on FPGAs. It naturally leads to the
 accelerator style of programming. In the SYCL HLS (IP Component) flow, which is currently the only flow supported, the
 kernel becomes the IP, and the "host code" becomes the testbench. An accelerator flow, with easier deployment on
 PCIe accelerator boards, is planned to be added in the future.
 
 The produced work areas use cmake to build the projects in a style based
-`oneAPI-samples <https://github.com/oneapi-src/oneAPI-samples/tree/main/DirectProgramming/C%2B%2BSYCL_FPGA>`_.
+`Altera HLS IP Gen hls-samples <https://github.com/altera-fpga/hls-samples>`_ (or deprecated `oneAPI-samples <https://github.com/oneapi-src/oneAPI-samples/tree/main/DirectProgramming/C%2B%2BSYCL_FPGA>`_).
 The standard ``fpga_emu``, ``report``, ``fpga_sim``, and ``fpga`` make targets are supported. Additionally, ``make lib``
 produces the library used for calling the ``predict`` function from hls4ml. The ``compile`` and ``build`` commands
 in hls4ml interact with the cmake system, so one does not need to manually use the build system, but it there
 if desired.
 
-The **oneAPI** backend, like the **Quartus** backend, only implements the ``Resource`` strategy for the layers. There
+The **Altera** backend, like the **Quartus** backend, only implements the ``Resource`` strategy for the layers. There
 is no ``Latency`` implementation of any of the layers.
 
 Note:  currently tracing and external weights (i.e. setting BramFactor) are not supported.
@@ -27,7 +31,7 @@ io_parallel and io_stream
 =========================
 
 As mentioned in the :ref:`I/O Types` section, ``io_parallel`` is for small models, while ``io_stream`` is for
-larger models. In ``oneAPI``, there is an additional difference: ``io_stream`` implements each layer on its
+larger models. In ``Altera``, there is an additional difference: ``io_stream`` implements each layer on its
 own ``task_sequence``. Thus, the layers run in parallel, with pipes connecting the inputs and outputs. This
 is similar in style to the `dataflow` implementation on Vitis HLS, but more explicit. It is also a change
 relative to the Intel HLS-based ``Quartus`` backend. On the other hand, ``io_parallel`` always uses a single task,

docs/backend/quartus.rst

@@ -3,10 +3,10 @@ Quartus
 =======
 
 .. warning::
-    The **Quartus** backend is deprecated and will be removed in a future version. Users should migrate to the **oneAPI** backend.
+    The **Quartus** backend is deprecated and will be removed in a future version. Users should migrate to the **Altera** backend.
 
-The **Quartus** backend of hls4ml is designed for deploying NNs on Intel/Altera FPGAs. It uses the discontinued Intel HLS compiler. The **oneAPI** backend should be preferred for new projects.
-The **oneAPI** backend contains the migrated the HLS code from this backend, with significantly better io_stream support, though the **oneAPI** backend does not yet support profiling, tracing,
+The **Quartus** backend of hls4ml is designed for deploying NNs on Intel/Altera FPGAs. It uses the discontinued Intel HLS compiler. The **Altera** backend should be preferred for new projects.
+The **Altera** backend contains the migrated the HLS code from this backend, with significantly better io_stream support, though the **Altera** backend does not yet support profiling, tracing,
 or the BramFactor option supported by the **Quartus** backend.  Nevertheless, little or no further development is expected for this backend.
 
 The **Quartus** backend only implements the ``Resource`` strategy for the layers. There is no ``Latency`` implementation of any of the layers.

docs/index.rst

@@ -35,7 +35,7 @@
 
     backend/vitis
     backend/accelerator
-    backend/oneapi
+    backend/altera
     backend/catapult
     backend/quartus
     backend/sr

docs/intro/setup.rst

@@ -60,7 +60,7 @@ The following Python packages are all optional and are only required if you inte
    * `Brevitas <https://xilinx.github.io/brevitas/>`_: Based on PyTorch. See `frontend/pytorch <../frontend/pytorch.html>`_ for more details.
    * `QONNX <https://github.com/fastmachinelearning/qonnx>`_: Based on ONNX. See `frontend/onnx <../frontend/onnx.html>`_ for more details.
 
-Running C simulation from Python requires a C++11-compatible compiler. On Linux, a GCC C++ compiler ``g++`` is required. Any version from a recent Linux should work. On MacOS, when the *clang*-based ``g++`` finds issues with ``ap_types`` headers, one may still need to install GCC, using ``brew`` for example. For the oneAPI backend, one must have `oneAPI=2025.0` (2025.1 is known **not to work**) installed, along with the FPGA compiler, to run C/SYCL simulations.
+Running C simulation from Python requires a C++11-compatible compiler. On Linux, a GCC C++ compiler ``g++`` is required. Any version from a recent Linux should work. On MacOS, if the *clang*-based ``g++`` finds issues with header files, one may want to install GCC, using ``brew`` for example. For the Altera backend, one must have Altera HLS IP Gen installed to run C/SYCL simulations.
 
 Specific functionalities may need additional Python packages. If any needed is missing, ``hls4ml`` will raise an error and prompt you to install the missing packages.
 
@@ -72,7 +72,7 @@ To run FPGA synthesis, installation of following tools is required:
 
 * Intel Quartus 20.1 to 21.4 for the synthesis for Intel/Altera FPGAs using the ``Quartus`` backend.
 
-* oneAPI 2024.1 to 2025.0 with the FPGA compiler and recent Intel/Altera Quartus for Intel/Altera FPGAs using the ``oneAPI`` backend. Newer versions of ``OneAPI`` removed FPGA support and **will to work** with ``hls4ml``.
+* Altera HLS IP Gen and recent Intel/Altera Quartus for Intel/Altera FPGAs using the ``Altera`` backend.
 
 Catapult HLS 2024.1_1 or 2024.2 can be used to synthesize both for ASICs and FPGAs.
 

docs/intro/status.rst

@@ -44,10 +44,10 @@ Neural network architectures:
 HLS backends:
 
 * Vivado HLS
-* Intel HLS
+* Intel HLS (deprecated)
 * Vitis HLS
 * Catapult HLS
-* oneAPI (experimental)
+* Altera
 * XLS (experimental)
 
 A summary of the on-going status of the ``hls4ml`` tool is in the table below.
@@ -81,7 +81,7 @@ A summary of the on-going status of the ``hls4ml`` tool is in the table below.
 +-----------------------+-----+-----+--------------+--------+--------+-----+
 | Catapult HLS          | ✅  | ✅  | ✅           | ❌     | ❌     | ❌  |
 +-----------------------+-----+-----+--------------+--------+--------+-----+
-| oneAPI (experimental) | ✅  | ✅  | ✅           | ❌     | ✅     | ❌  |
+| Altera                | ✅  | ✅  | ✅           | ❌     | ✅     | ❌  |
 +-----------------------+-----+-----+--------------+--------+--------+-----+
 | XLS (experimental)    | ✅  | ✅  | ❌           | ❌     | ❌     | ❌  |
 +-----------------------+-----+-----+--------------+--------+--------+-----+
@@ -94,7 +94,7 @@ Other feature notes:
   - Intel HLS versions 20.1 to 21.4, versions > 21.4 have not been tested.
   - Vitis HLS versions 2022.2 to 2024.1. Versions > 2024.1 are less tested.
   - Catapult HLS versions 2024.1_1 to 2024.2
-  - oneAPI versions 2024.1 to 2025.0. Any future versions are known to not work.
+  - Altera HLS IP Gen (Beta) 2026.1
 
 * ``hls4ml`` supports Linux [*]_ and requires python >=3.10. hls4ml does not require a specific Linux distribution version and we recommend following the requirements of the HLS tool you are using.
 * Windows and macOS are not supported. Setting up ``hls4ml`` on these platforms, for example using the Windows Subsystem for Linux (WSL), should be possible, but we do not provide support for such use cases.