[add][docs] add Part 5 VitisUnified accelerator backend tutorials - #130
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[add][docs] add Part 5 VitisUnified accelerator backend tutorials#130Tanawin1701d wants to merge 1 commit into
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- Add 5_accelerator_backends/vitis_unified/5_vu_{a..f}: predict, csim, cosim, FIFO depth optimization, bitfile build, and Vitis platform setup guide
- Use absolute output_dir for VitisUnified projects (backend resolves v++ --config relative to the workspace cwd)
- Add create_simple_unet Keras model to models.py for the Part 5 notebooks
- Add Part 5 screenshots (images/part5f_*.png) and register notebooks in _toc.yml
- Document Part 5 requirements (Vitis/Vivado 2023.2, hls4ml PR #1376) in README
TODO:
- [ ] Pin VitisUnified backend in environment.yml once hls4ml PR #1376 is merged
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Add Part 5: VitisUnified accelerator backend tutorials
This PR adds a new Part 5 with a set of notebooks for the VitisUnified backend
(hls4ml PR fastmachinelearning/hls4ml#1376), which produces a bitstream plus a PYNQ driver for
a SoC board (zcu102 or kv260).
What's added
New directory
5_accelerator_backends/vitis_unified/:5_vu_a_predict.ipynbpredict()matches the plain Vitis backend5_vu_b_csim.ipynb5_vu_c_cosim.ipynb5_vu_d_fifo_depth.ipynbvitisunified:fifo_depth_optimizationflow and inspectfifo_depths.json5_vu_e_bitfile.ipynbexport/files (system.bit,system.hwh, PYNQ driver) to copy to the board5_vu_f_platform_setup.mdaxi_streammode and the kv260Supporting changes:
models.py: addcreate_simple_unet()(small Keras U-Net with one skip connection; random weights, since these notebooks exercise the flow, not accuracy)._toc.yml: register the Part 5 chapters.README.md: new "Accelerator backends (Part 5)" section with the Vitis/Vivado 2023.2 requirement and thepip installline for PR #1376.images/part5f_*.png: screenshots for the platform setup guide.