[RyuJIT Wasm] SIMD Codegen for ExtractScalar/ReplaceScalar, Unsigned Compares

src/coreclr/jit/codegen.h

@@ -226,6 +226,8 @@ class CodeGen final : public CodeGenInterface
     void                       ensureCurrentFuncIsUnwindable();
     void                       genEmitIf(WasmValueType blockType = WasmValueType::Invalid);
     void                       genEmitEndIf();
+    void                       genEmitBeginBlock(WasmValueType blockType = WasmValueType::Invalid);
+    void                       genEmitEndBlock();
     void                       genEmitFunctionEnd(bool emitTerminalUnreachable = true);
 #endif
 
@@ -1085,6 +1087,10 @@ class CodeGen final : public CodeGenInterface
 
 #endif // TARGET_ARM64
 
+#if defined(TARGET_WASM)
+    void genHWIntrinsicJumpTableFallback(GenTreeHWIntrinsic* node, HWIntrinsic info);
+#endif
+
 #endif // FEATURE_HW_INTRINSICS
 
 #if !defined(TARGET_64BIT)

src/coreclr/jit/codegenwasm.cpp

@@ -2274,9 +2274,10 @@ void CodeGen::genEmitNullCheck(regNumber reg)
 void CodeGen::genRangeCheck(GenTree* tree)
 {
     assert(tree->OperIs(GT_BOUNDS_CHECK));
-    genConsumeOperands(tree->AsOp());
+    GenTreeBoundsChk* boundsCheck = tree->AsBoundsChk();
+    genConsumeOperands(boundsCheck->AsOp());
     GetEmitter()->emitIns(INS_I_ge_u);
-    genJumpToThrowHlpBlk(SCK_RNGCHK_FAIL);
+    genJumpToThrowHlpBlk(boundsCheck->gtThrowKind);
 }
 
 //------------------------------------------------------------------------
@@ -3797,6 +3798,38 @@ void CodeGen::genEmitEndIf()
     GetEmitter()->emitIns(INS_end);
 }
 
+// ------------------------------------------------------------------------
+// genEmitBeginBlock: Emit a 'block' instruction.
+//
+// Notes:
+//   The block is not modeled as part of wasmControlFlowStack.
+//   This is used for jump tables which don't have corresponding BasicBlock's
+//   and which will be emitted within a single block with known offsets for each case.
+void CodeGen::genEmitBeginBlock(WasmValueType blockType)
+{
+    wasmExtraControlFlowDepth++;
+    if (blockType != WasmValueType::Invalid)
+    {
+        GetEmitter()->emitIns_BlockTy(INS_block, blockType);
+    }
+    else
+    {
+        GetEmitter()->emitIns(INS_block);
+    }
+}
+
+// -----------------------------------------------------------------------
+// genEmitEndBlock: Emit an 'end' instruction closing a 'block'.
+//
+// Notes:
+//   Removes the added stack depth from genEmitBeginBlock.
+void CodeGen::genEmitEndBlock()
+{
+    assert(wasmExtraControlFlowDepth > 0);
+    wasmExtraControlFlowDepth--;
+    GetEmitter()->emitIns(INS_end);
+}
+
 //------------------------------------------------------------------------
 // inst_JMP: Emit a jump instruction.
 //
@@ -3849,34 +3882,34 @@ void CodeGen::genWasmEmitterUnitTestsSimd()
     DROP
 
     // Extract lane: v128 -> scalar (i32/i64/f32/f64), then drop
-#define TEST_EXTRACT_LANE(bytes, ins, attr, lane) \
+#define TEST_EXTRACT_LANE(bytes, ins, lane) \
     PUSH_V128(bytes);                             \
-    emit->emitIns_Lane(ins, attr, lane);              \
+    emit->emitIns_Lane(ins, lane);              \
     DROP
 
     // Replace lane: [v128, scalar] -> v128, then drop
-#define TEST_REPLACE_LANE_I32(bytes, ins, attr, lane) \
+#define TEST_REPLACE_LANE_I32(bytes, ins, lane) \
     PUSH_V128(bytes);                                 \
     PUSH_I32(42);                                     \
-    emit->emitIns_Lane(ins, attr, lane);                  \
+    emit->emitIns_Lane(ins, lane);                  \
     DROP
 
-#define TEST_REPLACE_LANE_I64(bytes, ins, attr, lane) \
+#define TEST_REPLACE_LANE_I64(bytes, ins, lane) \
     PUSH_V128(bytes);                                 \
     PUSH_I64(42);                                     \
-    emit->emitIns_Lane(ins, attr, lane);                  \
+    emit->emitIns_Lane(ins, lane);                  \
     DROP
 
-#define TEST_REPLACE_LANE_F32(bytes, ins, attr, lane) \
+#define TEST_REPLACE_LANE_F32(bytes, ins, lane) \
     PUSH_V128(bytes);                                 \
     PUSH_F32(0);                                      \
-    emit->emitIns_Lane(ins, attr, lane);                  \
+    emit->emitIns_Lane(ins, lane);                  \
     DROP
 
-#define TEST_REPLACE_LANE_F64(bytes, ins, attr, lane) \
+#define TEST_REPLACE_LANE_F64(bytes, ins, lane) \
     PUSH_V128(bytes);                                 \
     PUSH_F64(0);                                      \
-    emit->emitIns_Lane(ins, attr, lane);                  \
+    emit->emitIns_Lane(ins, lane);                  \
     DROP
 
     // Load lane: [i32_addr, v128] -> v128, then drop
@@ -3918,30 +3951,30 @@ void CodeGen::genWasmEmitterUnitTestsSimd()
 
     // --- IF_LANE: extract/replace lane instructions ---
     // i8x16 lanes (0..15)
-    TEST_EXTRACT_LANE(v128Ones, INS_i8x16_extract_lane_s, EA_1BYTE, 0);
-    TEST_EXTRACT_LANE(v128Ones, INS_i8x16_extract_lane_u, EA_1BYTE, 15);
-    TEST_REPLACE_LANE_I32(v128Ones, INS_i8x16_replace_lane, EA_1BYTE, 7);
+    TEST_EXTRACT_LANE(v128Ones, INS_i8x16_extract_lane_s, 0);
+    TEST_EXTRACT_LANE(v128Ones, INS_i8x16_extract_lane_u, 15);
+    TEST_REPLACE_LANE_I32(v128Ones, INS_i8x16_replace_lane, 7);
 
     // i16x8 lanes (0..7)
-    TEST_EXTRACT_LANE(v128Ones, INS_i16x8_extract_lane_s, EA_2BYTE, 0);
-    TEST_EXTRACT_LANE(v128Ones, INS_i16x8_extract_lane_u, EA_2BYTE, 7);
-    TEST_REPLACE_LANE_I32(v128Ones, INS_i16x8_replace_lane, EA_2BYTE, 3);
+    TEST_EXTRACT_LANE(v128Ones, INS_i16x8_extract_lane_s, 0);
+    TEST_EXTRACT_LANE(v128Ones, INS_i16x8_extract_lane_u, 7);
+    TEST_REPLACE_LANE_I32(v128Ones, INS_i16x8_replace_lane, 3);
 
     // i32x4 lanes (0..3)
-    TEST_EXTRACT_LANE(v128Ones, INS_i32x4_extract_lane, EA_4BYTE, 0);
-    TEST_REPLACE_LANE_I32(v128Ones, INS_i32x4_replace_lane, EA_4BYTE, 3);
+    TEST_EXTRACT_LANE(v128Ones, INS_i32x4_extract_lane, 0);
+    TEST_REPLACE_LANE_I32(v128Ones, INS_i32x4_replace_lane, 3);
 
     // i64x2 lanes (0..1)
-    TEST_EXTRACT_LANE(v128Ones, INS_i64x2_extract_lane, EA_8BYTE, 0);
-    TEST_REPLACE_LANE_I64(v128Ones, INS_i64x2_replace_lane, EA_8BYTE, 1);
+    TEST_EXTRACT_LANE(v128Ones, INS_i64x2_extract_lane, 0);
+    TEST_REPLACE_LANE_I64(v128Ones, INS_i64x2_replace_lane, 1);
 
     // f32x4 lanes (0..3)
-    TEST_EXTRACT_LANE(v128Ones, INS_f32x4_extract_lane, EA_4BYTE, 3);
-    TEST_REPLACE_LANE_F32(v128Ones, INS_f32x4_replace_lane, EA_4BYTE, 0);
+    TEST_EXTRACT_LANE(v128Ones, INS_f32x4_extract_lane, 3);
+    TEST_REPLACE_LANE_F32(v128Ones, INS_f32x4_replace_lane, 0);
 
     // f64x2 lanes (0..1)
-    TEST_EXTRACT_LANE(v128Ones, INS_f64x2_extract_lane, EA_8BYTE, 0);
-    TEST_REPLACE_LANE_F64(v128Ones, INS_f64x2_replace_lane, EA_8BYTE, 1);
+    TEST_EXTRACT_LANE(v128Ones, INS_f64x2_extract_lane, 0);
+    TEST_REPLACE_LANE_F64(v128Ones, INS_f64x2_replace_lane, 1);
 
     // --- IF_MEMARG_LANE: load/store lane with memarg ---
     TEST_LOAD_LANE(v128Ones, INS_v128_load8_lane, EA_1BYTE, 0, 5);

src/coreclr/jit/compiler.h

@@ -10164,16 +10164,16 @@ class Compiler
         return sizeBytes;
     }
 
-    // Get the number of elements of baseType of SIMD vector given by its size and baseType
-    static int getSIMDVectorLength(unsigned simdSize, var_types baseType);
-
     // Get the number of elements of baseType of SIMD vector given by its type handle
     int getSIMDVectorLength(CORINFO_CLASS_HANDLE typeHnd);
 
     // Get preferred alignment of SIMD type.
     int getSIMDTypeAlignment(var_types simdType);
 
 public:
+    // Get the number of elements of baseType of SIMD vector given by its size and baseType
+    static int getSIMDVectorLength(unsigned simdSize, var_types baseType);
+
     // Get the number of bytes in a System.Numeric.Vector<T> for the current compilation.
     // Note - cannot be used for System.Runtime.Intrinsic
     uint32_t getVectorTByteLength()

src/coreclr/jit/emitwasm.cpp

@@ -106,7 +106,7 @@ void emitter::emitIns_I(instruction ins, emitAttr attr, cnsval_ssize_t imm)
 //   ins         - instruction to emit
 //   attr        - emit attributes
 //   imm         - immediate value (depth in control flow stack)
-//   targetBlock - block at that depth
+//   targetBlock - block at that depth (may be null, in the case of jump table which doesn't target a real block)
 //
 void emitter::emitIns_J(instruction ins, emitAttr attr, cnsval_ssize_t imm, BasicBlock* targetBlock)
 {
@@ -116,7 +116,7 @@ void emitter::emitIns_J(instruction ins, emitAttr attr, cnsval_ssize_t imm, Basi
     id->idIns(ins);
     id->idInsFmt(fmt);
 
-    if (m_debugInfoSize > 0)
+    if (m_debugInfoSize > 0 && targetBlock != nullptr)
     {
         id->idDebugOnlyInfo()->idTargetBlock = targetBlock;
     }
@@ -463,14 +463,34 @@ void emitter::emitIns_V128Imm(instruction ins, const uint8_t bytes[16])
 //
 // Arguments:
 //   ins     - instruction (e.g., INS_i8x16_extract_lane_s)
-//   attr    - emit attribute indicating the lane element size
 //   laneIdx - lane index byte
 //
-void emitter::emitIns_Lane(instruction ins, emitAttr attr, uint8_t laneIdx)
+void emitter::emitIns_Lane(instruction ins, uint8_t laneIdx)
 {
-    instrDesc* id       = emitNewInstrSC(attr, laneIdx);
-    insFormat  fmt      = emitInsFormat(ins);
-    uint8_t    elemSize = CodeGenInterface::instSimdElemSize(ins);
+    uint8_t elemSize = CodeGenInterface::instSimdElemSize(ins);
+
+    // Add element width as an emit attribute
+    emitAttr attr = EA_UNKNOWN;
+    switch (elemSize)
+    {
+        case 1:
+            attr = EA_1BYTE;
+            break;
+        case 2:
+            attr = EA_2BYTE;
+            break;
+        case 4:
+            attr = EA_4BYTE;
+            break;
+        case 8:
+            attr = EA_8BYTE;
+            break;
+        default:
+            unreached();
+    }
+
+    instrDesc* id  = emitNewInstrSC(attr, laneIdx);
+    insFormat  fmt = emitInsFormat(ins);
     assert(fmt == IF_LANE);
     assert(isValidVectorIndex(elemSize, laneIdx));
 

src/coreclr/jit/emitwasm.h

@@ -34,7 +34,7 @@ void emitIns_S_R(instruction ins, emitAttr attr, regNumber ireg, int varx, int o
 
 // Packed SIMD instruction emit functions
 void emitIns_V128Imm(instruction ins, const uint8_t bytes[16]);
-void emitIns_Lane(instruction ins, emitAttr attr, uint8_t laneIdx);
+void emitIns_Lane(instruction ins, uint8_t laneIdx);
 void emitIns_MemargLane(instruction ins, emitAttr attr, cnsval_ssize_t offset, uint8_t laneIdx);
 
 void emitAddressConstant(void* address);

src/coreclr/jit/gentree.h

@@ -539,6 +539,10 @@ enum GenTreeFlags : unsigned
 #ifdef FEATURE_HW_INTRINSICS
     GTF_HW_EM_OP                  = 0x10000000, // GT_HWINTRINSIC -- node is used as an operand to an embedded mask
     GTF_HW_USER_CALL              = 0x20000000, // GT_HWINTRINSIC -- node is implemented via a user call
+#ifdef TARGET_WASM
+    GTF_HW_NEEDS_JUMP_TABLE       = 0x40000000, // GT_HWINTRINSIC -- (WASM) intrinsic has a non-constant immediate
+                                                //                   operand and requires a jump-table fallback at codegen
+#endif // TARGET_WASM
 #endif // FEATURE_HW_INTRINSICS
 };
 
@@ -2456,6 +2460,19 @@ struct GenTree
         gtFlags |= GTF_HW_EM_OP;
     }
 
+#ifdef TARGET_WASM
+    bool NeedsJumpTableFallback() const
+    {
+        return OperIsHWIntrinsic() && ((gtFlags & GTF_HW_NEEDS_JUMP_TABLE) != 0);
+    }
+
+    void SetNeedsJumpTableFallback()
+    {
+        assert(OperIsHWIntrinsic());
+        gtFlags |= GTF_HW_NEEDS_JUMP_TABLE;
+    }
+#endif // TARGET_WASM
+
 #endif // FEATURE_HW_INTRINSICS
 
     static bool HandleKindDataIsInvariant(GenTreeFlags flags);

src/coreclr/jit/hwintrinsic.cpp

@@ -2322,7 +2322,7 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic        intrinsic,
         immUpperBound   = HWIntrinsicInfo::lookupImmUpperBound(intrinsic);
         hasFullRangeImm = HWIntrinsicInfo::HasFullRangeImm(intrinsic);
 #elif defined(TARGET_WASM)
-        immUpperBound = HWIntrinsicInfo::lookupImmUpperBound(intrinsic, simdBaseType);
+        immUpperBound = HWIntrinsicInfo::lookupImmUpperBound(intrinsic, simdSize, simdBaseType);
 #endif
 
         if (!CheckHWIntrinsicImmRange(intrinsic, simdBaseType, immOp1, mustExpand, immLowerBound, immUpperBound,
@@ -2642,6 +2642,16 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic        intrinsic,
                     op2 = addRangeCheckIfNeeded(intrinsic, op2, immLowerBound, immUpperBound);
                 }
                 else
+#elif defined(TARGET_WASM)
+                // On WASM, PackedSimd.ReplaceScalar takes the lane immediate as the middle
+                // (op2) operand: ReplaceScalar(Vector128<T> vector, byte imm, T value). Other
+                // 3-arg PackedSimd immediate intrinsics (LoadScalarAndInsert, StoreSelectedScalar)
+                // put the immediate at op3 and fall through to the default handling below.
+                if (intrinsic == NI_PackedSimd_ReplaceScalar)
+                {
+                    op2 = addRangeCheckIfNeeded(intrinsic, op2, immLowerBound, immUpperBound);
+                }
+                else
 #endif
                 {
                     op3 = addRangeCheckIfNeeded(intrinsic, op3, immLowerBound, immUpperBound);