Skip to content

FPU: prevent a coprocessor divide/sqrt from corrupting scalar FP registers #3813

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
emiliengnr wants to merge 1 commit into
base: master
Choose a base branch
from
Open

FPU: prevent a coprocessor divide/sqrt from corrupting scalar FP registers #3813

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
22 changes: 15 additions & 7 deletions src/main/scala/tile/FPU.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -966,18 +966,26 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
// The scalar register write must never take a coprocessor divide/sqrt's
// address or data. io.cp_resp keeps using waddr/wdata above. A scalar
// pipelined result and a coprocessor divide/sqrt can complete on the same
// cycle, so select scalar sources here.
val divSqrt_wen_scalar = divSqrt_wen && !divSqrt_cp
val waddr_scalar = Mux(divSqrt_wen_scalar, divSqrt_waddr, wbInfo(0).rd)
val wtypeTag_scalar = Mux(divSqrt_wen_scalar, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata_scalar = box(Mux(divSqrt_wen_scalar, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag_scalar)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen_scalar) {
assert(consistent(wdata_scalar))
regfile(waddr_scalar) := wdata_scalar
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
printf("f%d p%d 0x%x\n", waddr_scalar, waddr_scalar + 32.U, ieee(wdata_scalar))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrdst := waddr_scalar
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
frfWriteBundle(1).wrdata := ieee(wdata_scalar)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen_scalar, waddr_scalar + 32.U, ieee(wdata_scalar))
}

when (wb_cp && (wen(0) || divSqrt_wen)) {
Expand Down