add: support ASID in the TLB and PTW - #3776

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iansseijelly wants to merge 7 commits into

chipsalliance:masterfrom

iansseijelly:asid

Commits on Oct 5, 2025

Enhance TraceEncoderController to include hartId and fix formatting in TraceCoreIngress
iansseijelly
committed
f82a9d4

Commits on Oct 6, 2025

add: context into the trace core interface bundle
iansseijelly
committed
bff9532

Commits on Oct 9, 2025

add: make the sink target 8 wide instead of 1
iansseijelly
committed
8efb6c1

Commits on Oct 13, 2025

staging: tlb changes
iansseijelly
committed
ea8b573

Commits on Oct 29, 2025

fix: some asid fixes
iansseijelly
committed
70635c0

Commits on Nov 22, 2025

fix: better asid support
iansseijelly
committed
98146ed

Commits on Feb 5, 2026

clean: clenaup unuseful resets as they are guarded by valid
iansseijelly
committed
b2880cb