Skip to content

perf(shader): reuse packed f16 operand lanes - #5811

Merged
adriadam10 merged 1 commit into
boykopovar:mainfrom
MarcZX10:codex/packed-f16-reuse-operands-4042
Oct 14, 2026
Merged

adriadam10 merged 1 commit into
boykopovar:mainfrom
MarcZX10:codex/packed-f16-reuse-operands-4042

Conversation

@MarcZX10

Copy link
Copy Markdown
Contributor

What

packedFloat16 emits the packed f16 operand selection and lane extraction once to form a native f16x2 add/multiply. When it emits the exact NaN/overflow repair path, it recomputes the same selected low/high halves for those operands. Cache each half lazily during the translation and reuse it for the result and repair logic. This avoids duplicate IR for extraction, OP_SEL, absolute value, and negate handling. The instruction result and existing repair rules are unchanged.

This is the smaller follow-up suggested in the review of closed #5057 after the guarded repair path showed no Palworld gain and grew the SPIR-V module. It makes no title-level performance claim. It depends on #4072, which changes the same packed-f16 translation function.

Tested

  • The changed translation unit compiled with the repository's Release C++20 compiler flags (GCC 12.2).
  • git diff --check passed.
  • Focused execution tests were not run: the available stale CMake build expanded the test target into a broad rebuild of unrelated dependencies, so I stopped it before running out-of-scope work.

Checklist

  • Based on current main; no other open PR implements this reuse
  • One topic per PR; follow-ups go in a new PR
  • No comments in code except technical debt
  • Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed under Silent stubs in their library's technical debt file
  • No notes, investigation .md files or images added to the repository (attach them to this PR)
  • New third-party code is a submodule built from source
  • Generic behaviour, not specific to one title
  • Depends on: perf(shader): compute v_pk_fma_f16 and v_pk_fmac_f16 with OpFmaKHR #4072
  • Unblocks: none
  • GPUs tested: none; this is an IR reuse change
  • AI-assisted: yes

@github-actions github-actions Bot added the shader core/shader label Oct 14, 2026
@adriadam10 adriadam10 self-assigned this Oct 14, 2026
@adriadam10

Copy link
Copy Markdown
Collaborator

Checked the diff: sourceLaneBits only memoizes laneBits per (source, half) within one packedFloat16 call. The emitted operations and bit rules are unchanged, and straight-line IR means the cached value dominates every use. Ran build + ctest for the AGC driver (including PackedFloat16Native, PackedAlu, Float16MinMaxBits, Fp16Overflow, Float16FmaRounding, Dx10Clamp); all pass. The only failure is agc_driver_tessellation, which also fails on main. The diff applies cleanly on main, so the #4072 dependency isn't needed. Merging once the full build is green.

@adriadam10
adriadam10 merged commit 066b58f into boykopovar:main Oct 14, 2026
8 checks passed
@Ondra97 Ondra97 mentioned this pull request Oct 14, 2026
11 tasks done
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

shader core/shader

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants