perf(shader): take the f32 mul, fma and add result fixups only when needed

[ErenYeager1836]

What

v_mul_f32, v_fma_f32, v_add_f32 and v_sub_f32 compute two fixups on every result: the AMD NaN result (the first NaN operand, quieted, or the default NaN) and, for products, the flush of results that are tiny after rounding to 24 bits. Both change the result only when it is a NaN or its magnitude is at most 2^-126. They were straight-line selects, so a v_mul_f32 took 16.5 SASS instructions on an RTX 4060 where the multiply is one.

The translator now wraps the fixed result in a select that takes it only when the host result is NaN (add and sub) or NaN or at most 2^-126 in magnitude (mul and fma, round to nearest even). That select is flagged as rarely true, and the SPIR-V backend moves the instructions used only by its rare arm into a branch. The rare arm is the same IR as before, so results are unchanged. Loop headers, continue targets and values shared between the two halves of a wave64 program keep plain selects.

Carried from @karanvora2599 with original attribution preserved.

Tested

• Windows 11: python tools/check_conventions.py --base upstream/main passes with 0 errors.

Checklist

• Based on current main; no other open PR implements the same functions
• One topic per PR; follow-ups go in a new PR
• No comments in code except technical debt
• Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed under Silent stubs in their library's technical debt file
• No notes, investigation .md files or images added to the repository (attach them to this PR)
• New third-party code is a submodule built from source
• Generic behaviour, not specific to one title
• Depends on: none
• Unblocks: none
• AI-assisted: yes

[karanvora2599]

@ErenYeager1836, this is #4322's commit without #4287 under it. I closed #4322 because branching the rare arms makes pipeline creation much slower (details in #4322):

• simonbbby measured the large f8d1fab9 pixel shader of Surround Sound Studio (PPSA99051). Its SPIR-V grew 34%, and the RTX 3090's pipeline build went from 2.2 s to 3.8 s. RADV cold runs went from 3 of 3 passing to 0 of 4 at the title's normal wait.
• On an RTX 4060, pipeline creation for independent f32 chains went up 47% at 1,024 ops and 119% at 4,096 ops.

NVIDIA's pipeline creation time is already the worst stall we have (#2292), so please close this one.

[CnRJay]

Adding to the comment above. This trade-off is measured, and it went the wrong way. Moving the rare arm into a branch removes a few ALU instructions per v_mul_f32 at run time. It also turns every one of these ops into a selection construct: thousands of extra basic blocks in large shaders, which is what drives the 34% SPIR-V growth and the 47–119% longer pipeline builds reported in #4322. Driver compilers also tend to flatten short branches like these back into selects (if-conversion), so the run-time gain may not survive anyway, while the compile-time cost is always paid.

The description's "Tested" covers only the conventions check, with no GPU and no shader. Since this re-opens a change closed for a measured compile-time regression, it would need new measurements that answer #4322: pipeline creation time on the same large shaders and GPU time of a title's frame, on at least NVIDIA and RADV, before it could be considered.

The same applies to #5334, #5337 and #5399, which also carry closed PRs over unchanged. If there's new evidence for any of them, putting it in the PR description up front would save the reviewers a round trip.

[oneandonlydean]

Closing: this is #4322's commit, and #4322 was closed because branching the rare arms makes pipeline creation much slower (measurements there, as karanvora2599 says above). Reopen with numbers from a title scene if that changes.