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perf(agc): reuse frontend within shader registration pairs - #2526
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adriadam10 merged 1 commit intoOct 10, 2026
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Retain an immutable decoded program and structured control flow while preparing the registration variants for one shader. Match owned code, stage and the complete SWAPPC inputs before reuse. Translate and plan each variant separately using its current inputs. Keep cache keys and persisted artifact layouts unchanged. Provide a cache-neutral off switch for controlled comparisons. Cover identity, lifetime, failed replacements and variant equivalence.
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Checked on Linux (merged onto current main): scoped build + ctest 299/299, |
SleglJan
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…ion-frontend-pair perf(agc): reuse frontend within shader registration pairs
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…ne program PrepareRegistered prepares every registered pixel shader twice: with the plan's layout, then with pushConstantSizeBytes = 0. The layout is not part of the source key, so both requests share one SourceEntry, but the first variant consumes the entry's front-end program. On a cold cache the second layout therefore ran PrepareResourceProgram again (translation, SSA, the fold and eliminator passes, SrtWalker, ResourceTracker) and the interface passes after it, although none of them reads the layout. Only decode, CFG and structurization were shared through the context (boykopovar#2526). A ShaderPreparationContext now keeps the program it last emitted from, after the interface step, together with its source entry. Another layout of the same source at the same code address resets the binding allocation and emits from that program, as the registration word-limit fallback already does within one variant, and copies the compiled information out instead of moving it. A different source or code address builds a program as before. Building another program through the context releases the kept one first, and the program dies with the context, so no program outlives the registration that built it (the rule of boykopovar#471). ResourcePrograms() counts the programs built through a context. Disk-cache loads and stores, the emission-failure memo and the variant order are unchanged. APS5_NO_PERF_LAYOUT_PAIR=1 restores the previous path; it is a neutral switch, so it does not change disk-cache keys. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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What
Preparing normal and partial-thread compute variants repeats decoding and control-flow construction for the same program. Keep one immutable frontend until that registration pair finishes.
Reuse requires identical owned code words, stage, fetch-call allowance and user-data register range. Each variant still translates, plans resources and emits from separate mutable IR with its current inputs. Failed construction preserves the previous frontend.
APS5_NO_PERF_FRONTEND_PAIR=1disables reuse for same-build comparisons without changing disk-cache keys. Persisted layouts and shader interfaces are unchanged.This complements #2327's removal of the earlier registration precheck and #2363's publication-lock change; neither shares the frontend between variants.
One same-build integration replay, reuse on then off, reduced pair preparation from 198.414 s to 113.562 s (42.8%); both SPIR-V variants were byte-identical. It used exact captured code with reconstructed historical context and no header. This is one offline preparation comparison, not standalone timing, an exact captured request or FPS.
Tested
Windows 11, MinGW-w64 GCC 15.2.0,
-DBUILD_TESTING=ON: full build, libs and registration passed on main0c0dc1e9plus feature (tree07a69b63). Windows: 558 passes/3 skips. Linux/lavapipe: 541 passes/29 skips, 570 total; executed tests passed three times.agc_shader_frontend_pairand_offran; no full-suite failures.Skip gates and control
Windows upstream skip checker passed; strict local NVIDIA gate failed for two offscreen VideoOut skips. Both exact built modes passed native SDL; the third skip is the intentional missing-Vulkan negative case.
Linux's 29 skip names match #2521's run. Individual skip output was not captured; the current JUnit skip gate was not run.
Removing only the three cached-hit return lines, with API/tests unchanged, makes ON fail the required reuse assertion (exit 8) and OFF pass (exit 0), no skips. This controls the cache-hit mechanism, not bare main or end-to-end registration counts.
Not tested: standalone title or console behavior.
Checklist
main; no other open PR implements the same functionsNotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt.mdfiles or images added to the repository (attach them to this PR)