fix(shader): quiet signaling NaN halves in v_pack_b32_f16 in IEEE mode

[CouchRiv]

What

Part of #981, a follow-up to #1867. In a shader with IEEE_MODE=1, v_pack_b32_f16 returns a signaling NaN half unchanged:

v_pack_b32_f16 v10, 0x0000, 0x7c01   hardware 7e010000, recompiler 7c010000
v_pack_b32_f16 v10, 0x0000, 0xfd23   hardware ff230000, recompiler fd230000

The hardware quiets each signaling NaN half it packs (after neg and abs) when IEEE=1, and copies the bits when IEEE=0. This is the rule #1867 measured for the unary instructions. The recompiler always copied the bits. vPackB32F16 now passes each NaN half through quietNan16. IEEE=0, and shaders without a known float mode, behave as before.

Halves (src0, src1)	IEEE=0	IEEE=1
0x7c01, 0x7dff	7dff7c01	7fff7e01
0x0000, 0xfd23	fd230000	ff230000
0x7c01, 0x7fff (op_sel, high halves)	7fff7c01	7fff7e01
-0x7c01, |0x7dff|	7dfffc01	7ffffe01
quiet NaN, inf, normal, denormal	unchanged	unchanged

Which title needs it

No known title needs it yet. It extends the rule #1867 measured to one more instruction, and it only changes shaders running with IEEE=1, which titles we know do not use (they use 0xc0, IEEE=0).

Tested

CachyOS Linux, GCC 16.2, RTX 4070 Ti (NVIDIA 615.71) and Radeon 610M (RADV, Mesa 26.2.4). Measured on RDNA2 (gfx1036) with the HW oracle.

• agc_driver_vop3_pack_ldexp gets a second shader: 4 forms of v_pack_b32_f16 (plain, op_sel, neg/abs) × 32 rows of signaling, quiet and ordinary halves. It runs with no mode, IEEE=0 and IEEE=1 and checks the hardware tables bit for bit. The hardware gave the same results with DX10 clamp on or off and f32 denormals kept or flushed.
• Without the fix the test fails on both drivers: lane 0 IEEE=1 v_pack_b32_f16 v10, v4, v5 is 0x7dff7c01, expected 0x7fff7e01.
• A differential run of 424 rows (f16 values with signaling NaNs, high-half garbage) in 4 float modes: 78 rows differed with IEEE=1 before, 0 after, on both drivers.
• Full Release ctest 498/498 on NVIDIA and on RADV; check_conventions.py and git diff --check pass.
• Not tested: a title, since none is known to run with IEEE=1.

Checklist

• Based on current main; no other open PR implements the same functions
• One topic per PR; follow-ups go in a new PR
• No comments in code except technical debt
• Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt
• No notes, investigation .md files or images added to the repository (attach them to this PR)
• New third-party code is a submodule built from source
• Generic behaviour, not specific to one title
• Depends on: none (fix(shader): quiet signaling NaNs only in IEEE mode #1867 merged)
• AI-assisted: yes

🤖 Generated with Claude Code

[popcoder565]

Native Windows run, since no Windows results were posted. Setup: Windows 10 (19045), RTX 3060 Laptop (NVIDIA 616.92), MinGW-w64 GCC 15.2.0 (WinLibs r7), Release. Head 77cc1da2, merged onto main d70b899 in one build with 33 other AGC/shader PRs that had no Windows run.

• This PR's tests pass: agc_driver_vop3_pack_ldexp. None of them reported skipping a case.
• Full ctest in that build: 514 of 515. The one failure is fix(agc): defer a shader whose code does not decode instead of aborting the title #2257's new test, which is registered without the Windows PATH setup.

No title was run.

🤖 Addressed by Claude Code

[adriadam10]

Rebased onto current main (mechanical conflict in docs/dev/TechnicalDebt.md after #2000; your sentence about v_pack_b32_f16 is kept in the "Signaling NaN inputs" entry). The code and test are unchanged. The earlier red linux/windows jobs were agc_shader_fusion_tests failing to find spirv/unified1/spirv.hpp, which main fixed in 37bc6f2; unrelated to this PR. Full build and ctest on the rebased head: 630/630 pass, including agc_driver_vop3_pack_ldexp. Merging once CI is green.