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Decode the remaining three SOPP opcodes from the AMD RDNA 2 ISA to achieve 100% SOPP instruction coverage (37/37): - s_sethalt (SOPP 0x0d): sets or clears the wavefront HALT status bits; translated as a control NOP. - s_sendmsghalt (SOPP 0x11): sends a message to the message processor and halts execution; translated via sSendmsg. - s_code_end (SOPP 0x1f): safety prefetch padding placed after shader termination; translated as a control NOP.
This was referenced Oct 7, 2026
This was referenced Oct 7, 2026
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Closing this one. Checked on gfx1035 hardware (HW oracle) and against the decoder:
What remains correct is |
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What
Identified from the AMD RDNA 1 + RDNA 2 instruction specification (
tools/rdna_isa.txt) to complete 100% of the SOPP instruction family (37/37):s_sethalt(SOPP opcode0x0d): sets or clears the wavefront HALT status bits for debugging; translated as a control NOP in emulation.s_sendmsghalt(SOPP opcode0x11): sends a message to the message processor and halts wavefront execution; translated viasSendmsg.s_code_end(SOPP opcode0x1f): safety prefetch padding emitted after shader termination (s_endpgm) to prevent prefetch hardware from fetching unmapped pages; translated as a control NOP.TechnicalDebt.mdupdated under Functional in the same commit.Tested
agc_sopp_control_decodeunit test passed (verifies decoding of each opcode, operand values, instruction family, and whole-program sequences).Checklist
main; no other open PR implements the same functionsNotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt.mdfiles or images added to the repository (attach them to this PR)