Thunderbolt: M1/M2 Pro display, M1 PCIe and resume recovery

Documentation/admin-guide/kernel-parameters.txt

@@ -7601,6 +7601,43 @@ Kernel parameters
 			See Documentation/admin-guide/mm/transhuge.rst for more
 			details.
 
+	thunderbolt.dp_video_counter=
+			[HW,ARM64]
+			Format: <bool>
+			Enable diagnostic counter 0 on the DP video path's
+			host and downstream ingress hops on the right-hand
+			USB-C route of the Apple M2 Pro and M2 Max laptops. Read counters through Thunderbolt
+			debugfs. This is a load-time setting. Default: false.
+
+	thunderbolt_apple.dp_display=
+			[HW,ARM64]
+			Format: <bool>
+			Drive displays behind Thunderbolt DisplayPort tunnels
+			on Apple t8103 and t600x (M1, M1 Pro and M1 Max):
+			route a display pipeline to the host router's DP IN
+			adapter whenever the connection manager sets up a DP
+			tunnel. Set to 0 to leave displays behind a dock dark.
+			Default: true
+
+	thunderbolt_apple.dpin_aux=
+			[HW,ARM64]
+			Format: <bool>
+			Pulse the experimental DP IN analog start control on
+			the Apple M2 Pro and M2 Max laptops at the next DP
+			tunnel activation. Writes to
+			the module parameter do not access a live controller.
+			Default: false (leave analog registers alone until
+			DPRX negotiation finishes or times out).
+
+	thunderbolt_apple.dpin_mode_value=
+			[HW,ARM64]
+			Format: <uint> (0-15)
+			Experimental DP IN MODE_A/MODE_B value on the Apple
+			M2 Pro and M2 Max laptops.
+			Sampled for each adapter activation; values above 15
+			make activation fail. Default: 8. The value is empirical
+			and does not select the negotiated DisplayPort rate.
+
 	tlbi=		[X86-64]
 			Format: {ipi}
 			ipi: switch to IPI-based TLB flushing

Documentation/devicetree/bindings/pci/apple,pcie.yaml

@@ -36,6 +36,16 @@ description: |
   distributed over the root ports as the OS sees fit by programming
   the PCIe controller's port registers.
 
+$defs:
+  tunable:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    items:
+      items:
+        - description: Register offset
+        - description: Mask of bits to clear
+        - description: Bits to set
+    description: Register initialization tuples for one controller region.
+
 properties:
   compatible:
     oneOf:
@@ -85,8 +95,34 @@ properties:
   power-domains:
     maxItems: 1
 
+  resets:
+    description:
+      Reset of a tunneled (PCIe-C) controller and its DART, for controllers
+      the kernel initializes itself.
+    maxItems: 1
+
   dma-coherent: true
 
+  apple,pciec-kernel-init:
+    type: boolean
+    description: The kernel initializes the tunneled controller from reset.
+
+  apple,tunable-rc:
+    $ref: '#/$defs/tunable'
+    description: Root-complex register initialization tuples.
+
+  apple,tunable-fabric:
+    $ref: '#/$defs/tunable'
+    description: Initialization tuples for the fabric register region.
+
+  apple,tunable-debug:
+    $ref: '#/$defs/tunable'
+    description: Initialization tuples for the debug register region.
+
+  apple,tunable-oe-fabric:
+    $ref: '#/$defs/tunable'
+    description: Initialization tuples for the oe-fabric register region.
+
   apple,piodma:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
@@ -108,6 +144,10 @@ patternProperties:
 
       interrupt-controller: true
 
+      apple,tunable:
+        $ref: '#/$defs/tunable'
+        description: Initialization tuples relative to this port's registers.
+
     required:
       - interrupt-controller
       - "#interrupt-cells"
@@ -189,14 +229,20 @@ allOf:
                 - const: fabric
                 - const: debug
                 - const: ltssm
-                - const: intr2axi
+                - enum: [intr2axi, oe-fabric]
         interrupts:
           maxItems: 1
         ranges:
           minItems: 3
           maxItems: 3
     else:
       properties:
+        resets: false
+        apple,pciec-kernel-init: false
+        apple,tunable-rc: false
+        apple,tunable-fabric: false
+        apple,tunable-debug: false
+        apple,tunable-oe-fabric: false
         ranges:
           maxItems: 2
       allOf:
@@ -239,6 +285,8 @@ allOf:
                   - const: phy3
       patternProperties:
         "^pci@":
+          properties:
+            apple,tunable: false
           required:
             - reset-gpios
 

Documentation/devicetree/bindings/thunderbolt/apple,t8103-usb4-acio.yaml

@@ -40,14 +40,21 @@ properties:
           - const: apple,t8103-usb4-acio
 
   reg:
+    minItems: 2
     items:
       - description: Root complex and co-processor control registers
       - description: SRAM used for communication with the co-processor
+      - description: |
+          PCIe adapter configuration space of the USB4 router. Present where
+          the root complex exposes the adapter separately, so that the tunnel
+          can be configured before a PCIe-C link is brought up.
 
   reg-names:
+    minItems: 2
     items:
       - const: rc
       - const: sram
+      - const: pcie-adapter
 
   mboxes:
     maxItems: 1
@@ -66,7 +73,11 @@ properties:
       apple,pcie-tunnel is present, the fourth domain powers its PCIe-C
       controller and is enabled only after the USB4 PCIe tunnel is active.
 
-  thunderbolt-switch: true
+  thunderbolt-switch:
+    type: boolean
+    description:
+      Marks this root complex as the USB4/Thunderbolt switch that the Type-C
+      PD controller hands cable information to, so the Type-C mux can find it.
 
   apple,pcie-tunnel:
     $ref: /schemas/types.yaml#/definitions/phandle
@@ -86,6 +97,18 @@ properties:
       Tree, converted by the bootloader and used to configure the root complex
       after the co-processor has booted.
 
+  apple,tunable-pcie-adapter:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    items:
+      items:
+        - description: Register offset
+        - description: Mask of bits to clear
+        - description: Bits to set
+    description: |
+      As apple,tunable-rc, but applied to the PCIe adapter configuration space
+      named by the pcie-adapter reg entry. Only meaningful where that entry is
+      present.
+
   '#address-cells':
     const: 1
 

MAINTAINERS

@@ -2601,6 +2601,7 @@ F:	drivers/i2c/busses/i2c-pasemi-core.c
 F:	drivers/i2c/busses/i2c-pasemi-platform.c
 F:	drivers/input/misc/macsmc-input.c
 F:	drivers/input/touchscreen/apple_z2.c
+F:	drivers/iommu/apple-dart-test.c
 F:	drivers/iommu/apple-dart.c
 F:	drivers/iommu/io-pgtable-dart.c
 F:	drivers/irqchip/irq-apple-aic.c
@@ -2619,6 +2620,8 @@ F:	drivers/soc/apple/*
 F:	drivers/spi/spi-apple.c
 F:	drivers/spmi/spmi-apple-controller.c
 F:	drivers/thunderbolt/apple.c
+F:	drivers/usb/dwc3/dwc3-apple-state-test.c
+F:	drivers/usb/dwc3/dwc3-apple-state.h
 F:	drivers/usb/dwc3/dwc3-apple.c
 F:	drivers/usb/typec/tipd/spmi.c
 F:	drivers/video/backlight/apple_dwi_bl.c

arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi

@@ -26,6 +26,33 @@
 		disp0_piodma = &disp0_piodma;
 		keyboard = &keyboard;
 		sio = &sio;
+		/* m1n1 writes this machine's Thunderbolt calibration onto these
+		 * aliases. usb4-N-* is current m1n1; usb4_N_* is the 1.6.1 bootloader.
+		 */
+		usb4-0-acio = &usb4_0_acio;
+		usb4-0-nhi = &usb4_0_nhi;
+		usb4-0-pcie-adapter = &usb4_0_acio;
+		usb4-0-pcie = &apciec0;
+		usb4_0_rc = &usb4_0_acio;
+		usb4_0_nhi = &usb4_0_nhi;
+		usb4_0_pcie_adapter = &usb4_0_acio;
+		usb4_0_pcie = &apciec0;
+		usb4-1-acio = &usb4_1_acio;
+		usb4-1-nhi = &usb4_1_nhi;
+		usb4-1-pcie-adapter = &usb4_1_acio;
+		usb4-1-pcie = &apciec1;
+		usb4_1_rc = &usb4_1_acio;
+		usb4_1_nhi = &usb4_1_nhi;
+		usb4_1_pcie_adapter = &usb4_1_acio;
+		usb4_1_pcie = &apciec1;
+		usb4-2-acio = &usb4_2_acio;
+		usb4-2-nhi = &usb4_2_nhi;
+		usb4-2-pcie-adapter = &usb4_2_acio;
+		usb4-2-pcie = &apciec2;
+		usb4_2_rc = &usb4_2_acio;
+		usb4_2_nhi = &usb4_2_nhi;
+		usb4_2_pcie_adapter = &usb4_2_acio;
+		usb4_2_pcie = &apciec2;
 	};
 };
 
@@ -72,8 +99,11 @@
 	       <&atcphy1 PHY_TYPE_DP>, <&atcphy2 PHY_TYPE_DP>;
 	phy-names = "dp-phy", "typec0", "typec1", "typec2";
 	mux-controls = <&atcphy3_xbar 0>, <&atcphy0_xbar 0>,
-		       <&atcphy1_xbar 0>, <&atcphy2_xbar 0>;
-	mux-control-names = "dp-xbar", "typec0", "typec1", "typec2";
+		       <&atcphy1_xbar 0>, <&atcphy2_xbar 0>,
+		       <&atcphy0_xbar 1>, <&atcphy1_xbar 1>,
+		       <&atcphy2_xbar 1>;
+	mux-control-names = "dp-xbar", "typec0", "typec1", "typec2",
+			    "typec0-usb4", "typec1-usb4", "typec2-usb4";
 	mux-index = <0>;
 	apple,dptx-phy = <3>;
 	apple,typec-mux-indices = <0 0 0>;
@@ -150,8 +180,11 @@
 	       <&atcphy2 PHY_TYPE_DP>;
 	phy-names = "typec0", "typec1", "typec2";
 	mux-controls = <&atcphy0_xbar 0>, <&atcphy1_xbar 0>,
-		       <&atcphy2_xbar 0>;
-	mux-control-names = "typec0", "typec1", "typec2";
+		       <&atcphy2_xbar 0>,
+		       <&atcphy0_xbar 1>, <&atcphy1_xbar 1>,
+		       <&atcphy2_xbar 1>;
+	mux-control-names = "typec0", "typec1", "typec2",
+			    "typec0-usb4", "typec1-usb4", "typec2-usb4";
 	apple,typec-mux-indices = <2 2 2>;
 	apple,typec-dptx-phys = <0 1 2>;
 

arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi

@@ -25,6 +25,41 @@
 / {
 	aliases {
 		dcpext1 = &dcpext1;
+		/* Same Thunderbolt aliases as the 14/16-inch boards. This mini
+		 * brings up a fourth controller.
+		 */
+		usb4-0-acio = &usb4_0_acio;
+		usb4-0-nhi = &usb4_0_nhi;
+		usb4-0-pcie-adapter = &usb4_0_acio;
+		usb4-0-pcie = &apciec0;
+		usb4_0_rc = &usb4_0_acio;
+		usb4_0_nhi = &usb4_0_nhi;
+		usb4_0_pcie_adapter = &usb4_0_acio;
+		usb4_0_pcie = &apciec0;
+		usb4-1-acio = &usb4_1_acio;
+		usb4-1-nhi = &usb4_1_nhi;
+		usb4-1-pcie-adapter = &usb4_1_acio;
+		usb4-1-pcie = &apciec1;
+		usb4_1_rc = &usb4_1_acio;
+		usb4_1_nhi = &usb4_1_nhi;
+		usb4_1_pcie_adapter = &usb4_1_acio;
+		usb4_1_pcie = &apciec1;
+		usb4-2-acio = &usb4_2_acio;
+		usb4-2-nhi = &usb4_2_nhi;
+		usb4-2-pcie-adapter = &usb4_2_acio;
+		usb4-2-pcie = &apciec2;
+		usb4_2_rc = &usb4_2_acio;
+		usb4_2_nhi = &usb4_2_nhi;
+		usb4_2_pcie_adapter = &usb4_2_acio;
+		usb4_2_pcie = &apciec2;
+		usb4-3-acio = &usb4_3_acio;
+		usb4-3-nhi = &usb4_3_nhi;
+		usb4-3-pcie-adapter = &usb4_3_acio;
+		usb4-3-pcie = &apciec3;
+		usb4_3_rc = &usb4_3_acio;
+		usb4_3_nhi = &usb4_3_nhi;
+		usb4_3_pcie_adapter = &usb4_3_acio;
+		usb4_3_pcie = &apciec3;
 	};
 };
 

arch/arm64/boot/dts/apple/t8103-pciec-tunables.dtsi

@@ -0,0 +1,50 @@
+/* t8103 Thunderbolt PCIe configuration, shared by both ports.
+ * Offsets are relative to the region named by each property.
+ */
+apple,pciec-kernel-init;
+apple,tunable-rc =
+	<0x718 0x7c000 0x0>,
+	<0x8bc 0x1 0x0>,
+	<0x78 0x7000 0x0>,
+	<0x814 0xffffffff 0xf060>;
+apple,tunable-fabric =
+	<0x4 0x1f001f 0x180018>,
+	<0x8 0x1 0x1>,
+	<0xc 0x1 0x1>,
+	<0x10 0x801f 0x4>,
+	<0x18 0x3ff 0x280>,
+	<0x44 0x1 0x1>,
+	<0x94 0x801f 0x4>,
+	<0x9c 0x801f 0x4>,
+	<0x20 0x801f 0x4>,
+	<0x28 0x3f 0x20>,
+	<0x2c 0x801f 0x4>,
+	<0x34 0x3f 0x20>,
+	<0x38 0x801f 0x4>,
+	<0x40 0x10001 0x10001>,
+	<0x48 0x1 0x1>,
+	<0x4c 0x801f 0x4>,
+	<0x54 0x7f007f 0x4b004b>,
+	<0x58 0x801f 0x4>,
+	<0x60 0x801f 0x4>,
+	<0x68 0x1 0x1>,
+	<0x6c 0x801f 0x4>,
+	<0x74 0x1 0x1>,
+	<0x78 0x801f 0x4>,
+	<0x84 0x801f 0x4>,
+	<0x8c 0x1 0x1>,
+	<0x90 0x1 0x1>,
+	<0xa4 0x801f 0x4>;
+apple,tunable-debug =
+	<0x1000 0x1 0x0>;
+apple,tunable-oe-fabric =
+	<0x4 0x70007 0x40004>,
+	<0x8 0x1 0x1>,
+	<0xc 0x1 0x1>,
+	<0x10 0x801f 0x4>,
+	<0x18 0x7f007f 0x450045>,
+	<0x1c 0x801f 0x4>,
+	<0x24 0x801f 0x4>,
+	<0x2c 0x1 0x1>,
+	<0x30 0x1 0x1>,
+	<0x34 0x801f 0x4>;