I build AI systems that run where the hardware actually is: INT4 quantization, on-device inference, and multi-agent pipelines with no cloud dependency.

My work sits between the model and the machine. On the software side that means weight compression and inference optimization inside Intel's OpenVINO and NNCF toolchain. On the hardware side it means RISC-V ISA specification work for the Linux Foundation, and RV32I processors written in Chisel.

Right now: Google Summer of Code 2026 contributor at Intel (OpenVINO), building a fully local 5-agent desktop automation system. Next: applying for PhD programs starting Fall 2027 in efficient ML, model compression, and computer architecture.

My research interest is making large models cheap enough to run on hardware people already own, and measuring honestly whether they still work after you shrink them.

Research Assistant, MERL Lab · Jul 2023 to Dec 2025 · merledu/ai4org

A fully on-premise framework for reducing LLM hallucination, with no external API calls at any stage.

• Multi-discriminator GAN pipeline paired with a REINFORCE reinforcement learning optimization loop
• FAISS semantic retrieval for grounded generation
• Fine-tuned TinyLlama, GPT-2, LLaMA-2, and Mistral-7B using PEFT, LoRA, and SFT
• Trained on dual AMD RX 7900 XTX with gradient checkpointing, plus CI/CD for reproducible runs

PyTorch Transformers PEFT/LoRA FAISS GANs REINFORCE RL ROCm

Research Assistant, MERL Lab · merledu/ArcheV

A standardized evaluation framework for LLM-generated RISC-V assembly, built because general code benchmarks say almost nothing about whether a model understands an ISA.

• Scores functional correctness, syntactic validity, and ISA edge-case coverage
• Reproducible JSON output for cross-model comparison
• RTL-level verification of generated programs

Python Verilog llama.cpp RISC-V

Vermithor (5-stage pipelined) · Vahgar (single cycle)

RV32I cores written in Chisel (Scala), with hazard detection, forwarding, and Verilator-based verification.

Chisel Scala Verilator RISC-V

Open to PhD supervision in: model compression and quantization · efficient / on-device inference · hardware-aware ML · LLM evaluation and benchmarking · ML for computer architecture

May 2026 to Sep 2026 · Google-sponsored · Remote · Mentors: Ethan Yang, Zhuo Wu

Building a privacy-preserving GUI desktop automation agent that runs entirely on-device, with zero cloud dependency.

5-Agent Pipeline (A2A Protocol + MCP Server)
──────────────────────────────────────────────────────────────────
Router  →  Planning  →  UI Grounding  →  Action Exec  →  Reflection
           Qwen3        UI-TARS VLM      Native Win32    Self-correct
           INT4         INT4 via OVMS    input           retry loop

• INT4 weight compression, KV caching, and prefix caching for a sub-second per-step budget on consumer hardware
• Four one-way layers (ui → core → agents → desktop) so the desktop layer reports facts and never makes decisions
• 107 commits restructuring the project into a release-ready state

➡️ Shehrozkashif/OpenVINO-Autonomous-GUI-Agent

Dec 2025 to Mar 2026 · Santa Clara, CA · Remote

• Stateful LLM compression: migrated OpenVINO's LLM compression examples to the default stateful inference flow, removing manual past_key_values handling (nncf #3814, merged)
• Transpose-aware LoRA correction: correct handling of MatMul layers with transposed activations in INT4/INT8 quantized LLMs, threading act_ch_axis through to LoRA so activation statistics are read on the right axis (nncf #3845, nncf #3864, in review)
• PyTorch frontend: proper support for the prim::isinstance operator (openvino #33803, in review)

Apr 2026 to Jun 2026 · Walnut Creek, CA · Remote

• Production LangChain RAG pipelines with FAISS for enterprise knowledge management
• Full retrieval stack: ingestion, semantic chunking, embedding, FAISS indexing, retrieval
• Agentic workflows for autonomous multi-step task execution
• Owned model monitoring loops covering retrieval quality, relevance, and latency

Proprietary codebase, private repository. Happy to walk through the architecture on a call.

Jan 2026 to Apr 2026 · Remote

• Built Verimate, an AI platform that generates UVM verification plans and testbenches from RTL/chip designs, for the semiconductor sector
• LangChain, FAISS, Gemini API, and GPU-accelerated local LLMs
• Reduced the manual effort in the hardware verification cycle

Proprietary codebase, private repository. Happy to walk through the architecture on a call.

Mar 2025 to Jun 2025 · Remote · Mentored by engineers from Qualcomm, Ventana, and Synopsys

• 6 merged PRs into the canonical machine-readable RISC-V ISA specification
• Implemented the Zilsd, Zclsd, and Zcmop extensions (load/store pair and compressed may-be-operation instructions for RV32)
• Ruby tooling, SimpleCov test coverage reporting, GitHub Actions CI, schema and IDL fixes
• Hypervisor-mode CSR contribution currently in review

12 merged pull requests into production and research codebases, plus 4 currently in review.

Inference and compression

LLM and agents

Hardware and systems

Languages

BSc Software Engineering, UIT University, Karachi

IBM AI Engineer Professional Certificate (Coursera, 2025), covering RAG and LangChain applications, AI agents, advanced fine-tuning for LLMs, transformers, and deep learning with PyTorch

📬 Let's talk

Open to: PhD positions (Fall 2027) · founding and early-stage engineering · LLM inference and infrastructure · edge AI optimization · research collaboration

Based in the UAE. Open to remote, and to relocation.

"The gap between a model and a system is where most people give up. That's where I live."