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Flydsl attn res - #4610

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flydsl-attn-res
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Flydsl attn res#4610
anhminhnguyenhoang wants to merge 11 commits into
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flydsl-attn-res

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anhminhnguyenhoang and others added 4 commits August 4, 2026 06:07
This gives correctness tests a simple golden implementation to compare against the future FlyDSL kernel.

Co-authored-by: Cursor <cursoragent@cursor.com>
Implements the nine-source online softmax path for D=7168 with a correctness test against the torch reference.

Co-authored-by: Cursor <cursoragent@cursor.com>
Add compile-time flags for delta, snapshot write, and output RMSNorm,
with tests for mix-only and fused append at num_blocks 0 and 7.

Co-authored-by: Cursor <cursoragent@cursor.com>
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github-actions Bot commented Aug 6, 2026

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🏷️ CI Guide

Runs automatically on every PR:

  • ✅ Pre-checks (submodule verification, code formatting)
  • ✅ Aiter op tests (gfx942 + gfx950)
  • ✅ Triton tests on MI35X (only when aiter/ops/triton/** or related paths are changed)

Extended tests (opt-in via labels):

Label Tests
ci:triton-300x Run an additional Triton test job on MI300X in PRs; main branch always runs both MI35X and MI300X
ci:sglang SGLang integration tests: DeepSeek-R1-MXFP4 accuracy, Qwen 3.5 accuracy
ci:atom ATOM benchmark: DeepSeek-R1-0528, GPT-OSS-120B
ci:atom_full ATOM accuracy suite for PR and main models from ATOM models_accuracy.json
ci:vllm vLLM benchmark: GPT-OSS-120B, DeepSeek-R1-0528, Kimi-K2.5
ci:all All standard extended tests (excludes ci:atom_full)

Only add ci:atom_full for FlyDSL or Triton upgrades.
Add labels via the sidebar or gh pr edit 4610 --add-label <label>

anhminhnguyenhoang and others added 7 commits August 7, 2026 05:57
Let delta, snapshot, and output RMSNorm specialize independently while keeping canonical append writes, and match the kernel's FP32-to-BF16 prefix update in the torch reference.

Co-authored-by: Cursor <cursoragent@cursor.com>
Tensor rows may now carry trailing padding, which callers need when a
hidden dimension is stored in a wider buffer. The kernel already handled
this: raw tensors pass their strides to FlyDSL at launch, so a padded row
is addressed correctly without recompiling. Only the host-side
is_contiguous() gate stood in the way.

That gate is replaced by a layout check requiring a unit trailing stride
and 16-byte-aligned row starts, which is what the 128-bit copy needs. A
padding of 7 elements leaves rows 2-byte aligned and is rejected with a
clear error; supporting it would cost a narrower, slower copy path.

Tests cover padding of 8 and 16 across the flag surface, verify padding
columns are never written, and check the rejected layouts.

Co-authored-by: Cursor <cursoragent@cursor.com>
Derive wave-aligned block threads from D, use shuffle-only reductions for single-wave rows, and extend tests and benchmarks for D=1024 while keeping D=7168 unchanged.

Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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