Skip to content
@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

Pinned Loading

  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 7.4k 968

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    Markdown 448 153

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 102 40

  4. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 191 113

  5. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 73 77

  6. NEMU NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    C 353 147

Repositories

Showing 10 of 111 repositories
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan's past year of commit activity
    Scala 7,353 MulanPSL-2.0 968 156 194 Updated Oct 28, 2026
  • NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    OpenXiangShan/NEMU's past year of commit activity
    C 353 147 40 46 Updated Oct 28, 2026
  • tutorial Public

    XiangShan Tutorial Website

    OpenXiangShan/tutorial's past year of commit activity
    Markdown 7 CC-BY-4.0 0 0 0 Updated Oct 28, 2026
  • XiangShanLab Public

    XiangShanLab is the open-source XiangShan ecosystem's entry layer — a learning, practice, and collaboration hub spanning the RISC-V processor core and its specialized domains, making high-performance processor design learnable, doable, and participable, and welcoming collaborators from academia and industry to join real open-source development.

    OpenXiangShan/XiangShanLab's past year of commit activity
    Scala 58 35 61 4 Updated Oct 28, 2026
  • GEM5 Public
    OpenXiangShan/GEM5's past year of commit activity
    C++ 167 BSD-3-Clause 96 18 103 Updated Oct 28, 2026
  • xs-env Public

    XiangShan Frontend Develop Environment

    OpenXiangShan/xs-env's past year of commit activity
    Shell 73 77 0 0 Updated Oct 28, 2026
  • XSCache Public

    Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.

    OpenXiangShan/XSCache's past year of commit activity
    Scala 3 8 0 12 Updated Oct 28, 2026
  • gsim Public
    OpenXiangShan/gsim's past year of commit activity
    C++ 91 14 4 11 Updated Oct 28, 2026
  • XiangShan-doc Public

    Documentation for XiangShan

    OpenXiangShan/XiangShan-doc's past year of commit activity
    Markdown 448 CC-BY-4.0 153 7 0 Updated Oct 28, 2026
  • OpenXiangShan/XiangShan-Dashboard's past year of commit activity
    Vue 2 2 0 4 Updated Oct 28, 2026