Verilog attributes not kept when verilog is generated

[fjullien]

Hi,

I'm working on a case were I use custom Verilog attributes. For example:

...
  wire leaf0_y;
  wire leaf1_y;
  wire leaf2_y;

  (* myattr="test" *)
  wire [5:0]    test_mid;
...

I can see the attribut being present in the ast and I can find the hdlAttributes in the parsed module.
However, we I generate the Verilog, the attributes are not present.

...
    wire leaf0_y;
    wire leaf1_y;
    wire leaf2_y;
    wire[5:0] test_mid;
...

Is this a known behavior?

[Thomasb81]

Well attribute are a way to attach vendor data to some verilog statement.

If attributes are not reproduced by the feature you use to do the regeneration, that's probably that no-one has need this feature before...

[fjullien]

I used ToVerilog2005() to produce the output.

Shouldn't the generation of attributes not be conditional?

If the original source code has them, they should be present in the regeneration.
If one wants to use hdlConvertor to add a module to the original code base, I think they might not want to modify the other parts of the code (i.e. keep existing attributes).

I may not be using hdlConvertor correctly though...

I ended up using this:

class MyToVerilog2005(ToVerilog2005):
    def __init__(self, *args, **kwargs):
        super().__init__(*args, **kwargs)

    def visit_HdlIdDef(self, var):
        w = self.out.write
        if var.hdlAttributes is not None:
            self.visit_hdlAttributes(var.hdlAttributes)
            w("\n")

        super().visit_HdlIdDef(var)

        return True

[Thomasb81]

Shouldn't the generation of attributes not be conditional?

Here is what the standard say about attribute:

The standard does not specify what are those additional properties. Reasonably you can't use an attribute define by someone who did not share with you the definition.
Usually attribute are documented in tool vendor manual for those who use them.

I don't know the answer to your question. We are here in tooling world, soon as you are able to read and produce standard file, it seems ok for to me.

The way you address it at your end is 100% valid. My guess is that if @Nic30 create a python class to export data into verilog it is to allow library user a customization through class inheritance.

If you see an interest to re-produce attribute for everyone, fill free to propose a PR.