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Implement prefetching #9723
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dd9035f
Add standalone prefetch facility as a free function and wire it to re…
gonidelis 50e1a50
enable prefetching on the reducebykey benchmark side
gonidelis 9112b58
Address #9496 review feedback carried over to the new design
gonidelis 010f57a
Test reduce_by_key correctness under every load_prefetch level
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,136 @@ | ||
| // SPDX-FileCopyrightText: Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. | ||
| // SPDX-License-Identifier: BSD-3 | ||
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| //! @file | ||
| //! Cooperative global-memory prefetch hints for tiles of data, placed explicitly by algorithm agents (or kernel | ||
| //! authors) at points in the kernel schedule where the hint has lead time before the corresponding loads. | ||
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| #pragma once | ||
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| #include <cub/config.cuh> | ||
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| #if defined(_CCCL_IMPLICIT_SYSTEM_HEADER_GCC) | ||
| # pragma GCC system_header | ||
| #elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_CLANG) | ||
| # pragma clang system_header | ||
| #elif defined(_CCCL_IMPLICIT_SYSTEM_HEADER_MSVC) | ||
| # pragma system_header | ||
| #endif // no system header | ||
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| #include <cub/util_type.cuh> | ||
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| #include <cuda/__cmath/round_up.h> | ||
| #include <cuda/__memcpy_async/elect_one.h> | ||
| #include <cuda/__memory/align_down.h> | ||
| #include <cuda/__ptx/ptx_helper_functions.h> | ||
| #include <cuda/std/__host_stdlib/ostream> | ||
| #include <cuda/std/__iterator/concepts.h> | ||
| #include <cuda/std/__memory/pointer_traits.h> | ||
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| #include <nv/target> | ||
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| CUB_NAMESPACE_BEGIN | ||
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| namespace detail | ||
| { | ||
| //! Enumerates the cache levels a tile prefetch hint can target. | ||
| enum class LoadPrefetch : int | ||
| { | ||
| //! No prefetch hint emitted. | ||
| none, | ||
| //! Emit an L2 prefetch hint (``prefetch.global.L2``) to all affected cache lines. | ||
| l2, | ||
| //! Emit an L1 prefetch hint (``prefetch.global.L1``) to all affected cache lines. Falls back to L2 on | ||
| //! architectures that do not support real L1 prefetch. | ||
| l1, | ||
| //! Emit a TMA bulk prefetch into L2 (``cp.async.bulk.prefetch``) for the whole tile. | ||
| //! Requires SM_90 or later (Hopper/Blackwell). Falls back to a no-op on older architectures. | ||
| bulk_l2, | ||
| }; | ||
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| #if _CCCL_HOSTED() && !defined(_CCCL_DOXYGEN_INVOKED) | ||
| inline ::std::ostream& operator<<(::std::ostream& os, LoadPrefetch prefetch) | ||
| { | ||
| switch (prefetch) | ||
| { | ||
| case LoadPrefetch::none: | ||
| return os << "detail::LoadPrefetch::none"; | ||
| case LoadPrefetch::l2: | ||
| return os << "detail::LoadPrefetch::l2"; | ||
| case LoadPrefetch::l1: | ||
| return os << "detail::LoadPrefetch::l1"; | ||
| case LoadPrefetch::bulk_l2: | ||
| return os << "detail::LoadPrefetch::bulk_l2"; | ||
| default: | ||
| return os << "<unknown detail::LoadPrefetch: " << static_cast<int>(prefetch) << ">"; | ||
| } | ||
| } | ||
| #endif // _CCCL_HOSTED() && !_CCCL_DOXYGEN_INVOKED | ||
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| //! Prefetch hints require a raw address, so only contiguous iterators qualify. Notably, | ||
| //! cub::CacheModifiedInputIterator does not: it routes loads through an explicit cache path | ||
| //! (e.g. ``LOAD_NC``) that a prefetch hint would defeat. | ||
| template <typename RandomAccessIterator> | ||
| inline constexpr bool can_prefetch_from = | ||
| ::cuda::std::contiguous_iterator<RandomAccessIterator> && ::cuda::std::__can_to_address<RandomAccessIterator>; | ||
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| //! Cooperatively emit prefetch hints covering the tile ``[block_src_it, block_src_it + items_to_prefetch)``. | ||
| //! For ``LoadPrefetch::l1``/``l2``, the calling thread block's threads stride the tile's address range in | ||
| //! ``PrefetchStride``-byte steps, each issuing one hint per cache line. For ``LoadPrefetch::bulk_l2``, one | ||
| //! elected thread issues a single TMA bulk prefetch for the whole tile. Silently a no-op for | ||
| //! ``LoadPrefetch::none`` and for iterator types that do not satisfy ``can_prefetch_from``, so call sites | ||
| //! need no enablement check of their own. | ||
| template <int ThreadsPerBlock, | ||
| LoadPrefetch Prefetch = LoadPrefetch::l2, | ||
| int PrefetchStride = 128, | ||
| typename RandomAccessIterator> | ||
| _CCCL_DEVICE _CCCL_FORCEINLINE void | ||
| prefetch_tile(int linear_tid, RandomAccessIterator block_src_it, int items_to_prefetch) | ||
| { | ||
| if constexpr (Prefetch != LoadPrefetch::none && can_prefetch_from<RandomAccessIterator>) | ||
| { | ||
| using input_t = cub::detail::it_value_t<RandomAccessIterator>; | ||
| const unsigned int total_bytes = static_cast<unsigned int>(items_to_prefetch) * unsigned{sizeof(input_t)}; | ||
| const auto* const src_ptr = reinterpret_cast<const char*>(::cuda::std::to_address(block_src_it)); | ||
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| if constexpr (Prefetch == LoadPrefetch::bulk_l2) | ||
| { | ||
| // One elected thread issues a single TMA bulk prefetch for the whole tile. | ||
| // cp.async.bulk.prefetch is fire-and-forget: no commit_group/wait_group needed. | ||
| // Requires SM_90+; a no-op on older architectures. | ||
| NV_IF_TARGET(NV_PROVIDES_SM_90, (if (::cuda::device::__block_elect_one()) { | ||
| // srcMem must be 16-byte aligned per PTX ISA; align base down and extend size to compensate | ||
| const auto* const aligned_base = ::cuda::align_down(src_ptr, 16); | ||
| const unsigned int prefix = static_cast<unsigned int>(src_ptr - aligned_base); | ||
| const unsigned int aligned_size = ::cuda::round_up(total_bytes + prefix, 16u); | ||
| if (aligned_size > 0) | ||
| { | ||
| asm volatile("cp.async.bulk.prefetch.L2.global [%0], %1;" | ||
| : | ||
| : "l"(::cuda::ptx::__as_ptr_gmem(aligned_base)), "r"(aligned_size) | ||
| : "memory"); | ||
| } | ||
| })) | ||
| } | ||
| else | ||
| { | ||
| _CCCL_PRAGMA_NOUNROLL() | ||
| for (unsigned int offset = static_cast<unsigned int>(linear_tid) * PrefetchStride; offset < total_bytes; | ||
| offset += static_cast<unsigned int>(ThreadsPerBlock) * PrefetchStride) | ||
| { | ||
| // TODO: replace with cuda::ptx::prefetch_L1/L2 once exposed in libcudacxx | ||
| if constexpr (Prefetch == LoadPrefetch::l1) | ||
| { | ||
| asm volatile("prefetch.global.L1 [%0];" : : "l"(::cuda::ptx::__as_ptr_gmem(src_ptr + offset)) : "memory"); | ||
| } | ||
| else | ||
| { | ||
| asm volatile("prefetch.global.L2 [%0];" : : "l"(::cuda::ptx::__as_ptr_gmem(src_ptr + offset)) : "memory"); | ||
| } | ||
| } | ||
| } | ||
| } | ||
| } | ||
| } // namespace detail | ||
|
|
||
| CUB_NAMESPACE_END |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,105 @@ | ||
| // SPDX-FileCopyrightText: Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. | ||
| // SPDX-License-Identifier: BSD-3-Clause | ||
|
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| // Should precede any includes | ||
| struct stream_registry_factory_t; | ||
| #define CUB_DETAIL_DEFAULT_KERNEL_LAUNCHER_FACTORY stream_registry_factory_t | ||
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| #include "insert_nested_NVTX_range_guard.h" | ||
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| #include <cub/device/device_reduce.cuh> | ||
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| #include <thrust/device_vector.h> | ||
| #include <thrust/host_vector.h> | ||
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| #include <cuda/devices> | ||
| #include <cuda/std/functional> | ||
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| #include "catch2_test_env_launch_helper.h" | ||
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| DECLARE_LAUNCH_WRAPPER(cub::DeviceReduce::ReduceByKey, device_reduce_by_key); | ||
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| // %PARAM% TEST_LAUNCH lid 0:1:2 | ||
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| #include <c2h/catch2_test_helper.h> | ||
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| template <cub::detail::LoadPrefetch PrefetchLevel> | ||
| struct reduce_by_key_prefetch_tuning | ||
| { | ||
| _CCCL_API constexpr auto operator()(cuda::compute_capability) const -> cub::ReduceByKeyPolicy | ||
| { | ||
| return {128, 11, cub::BLOCK_LOAD_DIRECT, cub::LOAD_DEFAULT, cub::BLOCK_SCAN_WARP_SCANS, {}, PrefetchLevel}; | ||
| } | ||
| }; | ||
|
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| using load_prefetch_levels = | ||
| c2h::enum_type_list<cub::detail::LoadPrefetch, | ||
| cub::detail::LoadPrefetch::none, | ||
| cub::detail::LoadPrefetch::l2, | ||
| cub::detail::LoadPrefetch::l1, | ||
| cub::detail::LoadPrefetch::bulk_l2>; | ||
|
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| #if TEST_LAUNCH != 1 | ||
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| // Prefetch hints must never affect results: run the same reduction under every LoadPrefetch level | ||
| // (bulk_l2 is a no-op below SM90) and expect output identical to a sequential host reference. | ||
| C2H_TEST("Device ReduceByKey is correct under every load_prefetch level", "[reduce][device]", load_prefetch_levels) | ||
| { | ||
| constexpr auto prefetch_level = c2h::get<0, TestType>::value; | ||
|
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| // Cover a single partial tile, and many tiles with a ragged final tile | ||
| const int num_items = GENERATE(values({42, (1 << 20) + 3})); | ||
| CAPTURE(num_items); | ||
|
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| // Deterministic keys with short runs, and values that vary within each run | ||
| thrust::host_vector<int> h_keys(num_items); | ||
| thrust::host_vector<int> h_values(num_items); | ||
| for (int i = 0; i < num_items; ++i) | ||
| { | ||
| h_keys[i] = (i / 3) % 5; | ||
| h_values[i] = i % 7; | ||
| } | ||
| thrust::device_vector<int> d_keys_in(h_keys); | ||
| thrust::device_vector<int> d_values_in(h_values); | ||
|
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| c2h::device_vector<int> d_unique_out(num_items, thrust::no_init); | ||
| c2h::device_vector<int> d_aggregates_out(num_items, thrust::no_init); | ||
| c2h::device_vector<int> d_num_runs_out(1, thrust::no_init); | ||
|
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| // Raw pointers on purpose: the agent wraps pointer inputs in CacheModifiedInputIterator and | ||
| // unwraps them for the prefetch hint — the code path production dispatch actually takes. | ||
| device_reduce_by_key( | ||
| thrust::raw_pointer_cast(d_keys_in.data()), | ||
| thrust::raw_pointer_cast(d_unique_out.data()), | ||
| thrust::raw_pointer_cast(d_values_in.data()), | ||
| thrust::raw_pointer_cast(d_aggregates_out.data()), | ||
| thrust::raw_pointer_cast(d_num_runs_out.data()), | ||
| cuda::std::plus<>{}, | ||
| num_items, | ||
| cuda::execution::tune(reduce_by_key_prefetch_tuning<prefetch_level>{})); | ||
|
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| // Sequential host reference | ||
| thrust::host_vector<int> expected_unique; | ||
| thrust::host_vector<int> expected_aggregates; | ||
| for (int i = 0; i < num_items; ++i) | ||
| { | ||
| if (i == 0 || h_keys[i] != h_keys[i - 1]) | ||
| { | ||
| expected_unique.push_back(h_keys[i]); | ||
| expected_aggregates.push_back(h_values[i]); | ||
| } | ||
| else | ||
| { | ||
| expected_aggregates.back() += h_values[i]; | ||
| } | ||
| } | ||
|
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| const auto num_runs = static_cast<size_t>(d_num_runs_out[0]); | ||
| REQUIRE(num_runs == expected_unique.size()); | ||
| d_unique_out.resize(num_runs); | ||
| d_aggregates_out.resize(num_runs); | ||
| REQUIRE(d_unique_out == expected_unique); | ||
| REQUIRE(d_aggregates_out == expected_aggregates); | ||
| } | ||
|
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| #endif // TEST_LAUNCH != 1 |
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🩺 Stability & Availability | 🟠 Major | ⚡ Quick win
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important: gate the prefetch hints on
num_remaining > 0.prefetch_tilecasts the count tounsigned, so a block that lands past the end turns a negativenum_remaininginto a huge byte request and can issue a runaway prefetch before the existingConsumeTileguard skips the tile.