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Changes register alias name handling for RVE based cores
CI
#34:
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f14847a
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7m 42s
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applies clang-format
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#33:
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adds some decoder debugging aids
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updates src/vm/interp/vm_tgc5c.cpp with latest CoreDSL changes
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updates interp/vm_tgc5c according to latest coredsl gen
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fixes mideleg write behavior for 64bit
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applies clang-format
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fixes wrong mideleg behavior
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fixes core registrations
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#26:
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fixes PMP size for tests
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changes default number of PMP addr registers to 16 (standard for RV32)
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adds option to exclude generic cores from build to speedup build
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updates core hash in FetchContent
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Feature/iif upgrades
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updates core hash in FetchContent
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Merge branch 'main' into feature/iif_upgrades
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fixes [m|s]i[p|e] read/write access and use of respective registers
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updates dbt-rise-core commit for standalone build
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updates dbt-rise-core commit for standalone build
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fixes compilation issues
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adds support for AIA registers in 32bit mode
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#12:
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removes douple specified define
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feat(pmp): extend to 64 entries with configurable NUM_ENTRIES
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