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feat(bench): add rigtorp SPSCQueue C++ contender via FFI - #11
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Vendor rigtorp/SPSCQueue header (MIT licensed) and expose it through a thin C wrapper compiled by the cc crate. New bench-contenders-cpp feature flag enables rigtorp benchmarks in the same coherent matrix (single, burst_100, burst_1000 × u64, msg48, msg64). Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Benchmark ReportCommit: LinuxCPU: Latency (ns/op, lower is better)Single Push+Pop
Burst 100
Burst 1000
Batch 100
Batch 1000
Full Drain
Instructions per Op (lower is better)Full results (all fields)
macOSCPU: Latency (ns/op, lower is better)Single Push+Pop
Burst 100
Burst 1000
Batch 100
Batch 1000
Full Drain
Instructions per Op (lower is better)Full results (all fields)
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Replace Relaxed atomic loads of own head/tail position with Cell-based local caches, matching the rtrb optimization pattern. The producer and consumer now read their own position from a Cell (register-friendly) and only use atomic stores for cross-thread publishing. Group producer-local fields (head_local + tail_remote) and consumer-local fields (tail_local + head_remote) into dedicated cache structs that share a single CachePadded line each — zero additional memory overhead. Results on M4 Pro (before → after): - copy/single/u64: 2.21ns → 1.80ns (-19%) - copy/burst/100/msg48: 372ns → 181ns (-51%) - copy/burst/1000/u64: 4044ns → 2790ns (-31%) - inline/burst/100/u64: 383ns → 209ns (-45%) - inline/burst/1000/u64: 4260ns → 2683ns (-37%) Mantis now sweeps all 9 benchmark categories vs rtrb, crossbeam, and rigtorp C++. The burst_1000/u64 result flipped from losing to rtrb by 12% to beating it by 20%. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
On x86, Cell::set before atomic store creates a store-forwarding dependency that hurts the next iteration's Cell::get. Moving it after the atomic store takes it off the critical path. Also update CLAUDE.md to document nightly-only toolchain. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
On ARM, Cell-based local caching avoids implicit ordering overhead of atomic self-loads (66-79% improvement in burst workloads). On x86 (TSO), Relaxed atomic load is already a plain mov instruction, so the Cell adds store-forwarding overhead without benefit. Use cfg(target_arch = "aarch64") to enable Cell caching only on ARM. x86 falls back to Relaxed atomic self-load (zero overhead on TSO). Remote index caching (tail_remote/head_remote) remains unconditional. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
These fields are only used on ARM where Cell-based local caching avoids atomic self-load overhead. On x86 they were dead fields causing clippy errors. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Document why head_local/tail_local use cfg(target_arch = "aarch64"): ARM Relaxed atomics carry implicit ordering overhead (store buffer drain, coherence protocol), while x86 TSO makes them a plain mov. Cell caching wins on ARM but adds store-forwarding cost on x86. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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Summary
crates/bench/cpp/rigtorp_ffi.cpp) compiled viacccrate at-O3 -std=c++17RigtorpU64,RigtorpMsg48,RigtorpMsg64)bench-contenders-cppfeature flag — enabled by--all-featuresin CIrigtorp-cppimplementationLocal Results (M4 Pro,
-C target-cpu=native)Single Push+Pop (ns/op)
Burst 1000 (ns/op)
Test plan
cargo +nightly clippy --bench spsc --all-features -- -D warningspassescargo fmt --all --checkpassesnormalizefilter handlesspsc/rigtorp/prefix🤖 Generated with Claude Code