UNIVERSITY OF WEST ATTICA
SCHOOL OF ENGINEERING
DEPARTMENT OF COMPUTER ENGINEERING AND INFORMATICS

University of West Attica · Department of Computer Engineering and Informatics

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Digital Circuit Design

Sequential Circuits

Vasileios Evangelos Athanasiou
Student ID: 19390005

GitHub · LinkedIn

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Supervision

Supervisor: Ioannis Vogiatzis, Professor

UNIWA Profile · LinkedIn

Supervisor: Panagiotis Karkazis, Associate Professor

UNIWA Profile · LinkedIn

Co-supervisor: Athanasios Milidonis, Postdoctoral Researcher

Scholar · LinkedIn

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Athens, May 2023

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README

Sequential Circuits

The project focuses on modeling, simulating, and verifying sequential logic circuits using VHDL.
Each circuit is implemented using a clear architectural style and is accompanied by a testbench to validate its behavior under different timing and control conditions.

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Table of Contents

Section	Folder / File	Description
1	assign/	Laboratory assignment material
1.1	assign/Lab4a_UniWA-BSc-DSD_VHDL#2a.pdf	Laboratory exercise description (English)
1.2	assign/Εργαστήριο4α_ΠΑΔΑ-ΣΨΣ_VHDL.pdf	Laboratory exercise description (Greek)
2	docs/	Theoretical documentation on sequential circuits
2.1	docs/Sequential-Circuits.txt	Sequential circuits theory and explanations (English)
2.2	docs/Ακολουθιακά-Κυκλώματα.txt	Sequential circuits theory and explanations (Greek)
3	src/	VHDL source code and testbenches
3.1	src/latch.vhd	Latch implementation
3.2	src/latch_tb.vhd	Latch testbench
3.3	src/flipflop.vhd	Flip-Flop implementation
3.4	src/flipflop_tb.vhd	Flip-Flop testbench
3.5	src/myRegister.vhd	Register implementation
3.6	src/myRegister_tb.vhd	Register testbench
3.7	src/shift4.vhd	4-bit Shift Register
3.8	src/shift4_tb.vhd	4-bit Shift Register testbench
3.9	src/shiftn.vhd	N-bit Shift Register
3.10	src/shiftn_tb.vhd	N-bit Shift Register testbench
3.11	src/upcount.vhd	Up Counter implementation
3.12	src/upcount_tb.vhd	Up Counter testbench
4	README.md	Project documentation
5	INSTALL.md	Usage instructions

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1. Implemented Circuits

1.1 Latch

A basic D-latch where the output Q follows the input D when the Enable (EN) signal is high ('1').
When EN is low ('0'), the output retains its previous value.

1.2 Flip-Flop

A standard D Flip-Flop that transfers the value of input D to output Q only on the rising edge (0 → 1 transition) of the clock signal (CLK).

1.3 Flip-Flop with Asynchronous Reset

A D Flip-Flop featuring an asynchronous active-low reset (Rstn).
When Rstn = '0', the output Q is immediately forced to '0', independent of the clock or data inputs.

1.4 4-Bit Register

A 4-bit register implemented using flip-flops with a clear (clr) input.
It supports:

• Parallel data loading
• Clearing of all bits on the rising edge of the clock

1.5 Up-Counter (0 to 3)

A small synchronous up-counter that increments its value from 0 to 3 on each rising clock edge.
A synchronous reset returns the counter to 0.

1.6 Shift Register

A 4-bit shift register with serial input (Sin).
When the Enable signal is active, bits are shifted serially through the register on each clock pulse.

1.7 Shift Register with Parallel Loading

A generic N-bit shift register (default: 8-bit) supporting:

• Serial shifting
• Parallel data loading

Parallel loading is activated when the Load signal is high, allowing all bits to be loaded simultaneously.

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2. Simulation & Verification

All circuits are verified using testbenches that stimulate:

• Clock behavior
• Reset and control signals
• Data transitions

Waveform analysis ensures correct sequential behavior and timing compliance.