README.md

Heap sort in hardware

See performance table here.

Create a new file with test values

make test-files/<file-name>.txt N=? W=?

Emit verilog RTL

make gen K=? W=? TEST_FILE=test-files/<file-name>.txt

Verilog RTL is placed in /build.

Run Xilinx Vivado synthesis for Basys3

make synth K=? W=? TEST_FILE=test-files/<file-name>.txt

Utilization and timing analysis reports are placed in /build

Program Basys3

make download K=? W=? TEST_FILE=test-files/<file-name>.txt

Run RTL tests

make rtl-test

Performance

Create performance table for different sizes and tree orders:

make performance-table