esp32: add interrupt support (vector table, timer alarm, GPIO SetInterrupt)#5510
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deadprogram wants to merge 6 commits into
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esp32: add interrupt support (vector table, timer alarm, GPIO SetInterrupt)#5510deadprogram wants to merge 6 commits into
deadprogram wants to merge 6 commits into
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Size difference with the dev branch: Binary size differenceflash ram before after diff before after diff |
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A few more things to do on this, moving back to draft. |
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| _arena_start = ABSOLUTE(.); | ||
| } >DRAM1 | ||
| _arena_end = ORIGIN(DRAM1) + LENGTH(DRAM1); | ||
| ASSERT((_arena_end - _arena_start) >= 32K, "arena region < 32K") |
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I'm curious where and how are you using the .arena section.
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…rrupt) Signed-off-by: deadprogram <ron@hybridgroup.com>
Signed-off-by: deadprogram <ron@hybridgroup.com>
Add full flash XIP support for ESP32, enabling code and read-only data to execute/load directly from flash via the MMU cache rather than consuming precious SRAM. This increases available RAM from ~328KB to effectively unlimited for code/rodata, while keeping ~121KB for the Go heap. Changes: - src/device/esp/esp32.S: Add MMU initialization in call_start_cpu0 - Call ROM bootloader mmu_init() and cache_flash_mmu_set() to map DROM/IROM - Enable flash cache via ROM Cache_Read_Enable() - Fix tinygo_scanCurrentStack to spill all register windows for GC - targets/esp32-interrupts.S: Add exception diagnostics - targets/esp32.ld: Major linker script restructure for XIP - Add DROM (4MB @ 0x3F400000) and IROM (4MB @ 0x400D0000) regions - Move .rodata to DROM, main .text to IROM (both flash-mapped) - Keep boot code, vectors, and WiFi blob IRAM sections in SRAM0 - Create WiFi arena in SRAM1 pool 7/6 (64KB @ 0x3FFF0000) - Move .bss and heap to SRAM2 (200KB @ 0x3FFAE000), avoiding ROM/MAC regions - Add _drom_flash_addr variable (patched by builder with flash offset) - targets/esp32.json: Add linker wrap flags for malloc/free and WiFi functions Signed-off-by: deadprogram <ron@hybridgroup.com>
Signed-off-by: deadprogram <ron@hybridgroup.com>
Work around an lld (LLVM 22) bug where l32r PC-relative offsets are miscalculated when auto-generated .literal.* sections are prepended to .text.* sections by the linker script. The assembler emits .literal entries for movi instructions whose constants exceed the 12-bit signed range; lld then resolves the l32r relocations with incorrect offsets, causing every l32r in the boot code to load from the wrong literal pool entry. The symptom was a TG0WDT_SYS_RESET boot loop: the watchdog disable code loaded wrong register addresses via l32r and silently wrote to the wrong peripheral registers, leaving the watchdog running. Fix by constructing PS_WOE_MASK (0x40000) with movi+slli instead of a single large-constant movi, eliminating all auto-generated .literal section entries. This is compatible with both LLVM 20 and LLVM 22. Also revert DRAM origin to 0x3FFAE000 (200K) and remove rom_phyFuns symbols that belong in a separate WiFi commit. Signed-off-by: deadprogram <ron@hybridgroup.com>
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Signed-off-by: deadprogram <ron@hybridgroup.com>
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This PR add interrupt support (vector table, timer alarm, GPIO SetInterrupt) to the esp32.
It also then hooks the IRQ up for receiving UART data.
Tested locally on my venerable
esp32-mini32board.UPDATE: added the support needed for XIP and also the linker changes for minimal espradio support.
FURTHER UPDATE: this PR turned into all the commits to get initial WiFI on ESP32 working as well.
This PR needs #5511 to correctly flash the larger programs.