From 9372bd41f75d079e9a49b5c7be62669ece1c5856 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Wed, 8 Jul 2026 15:05:24 +0200 Subject: [PATCH 1/8] first commit of vhdl rocev2 engine --- ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd | 417 +++ ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd | 787 +++++ ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd | 746 +++++ ethernet/RoCEv2/rtl/AtomicSrvConAndGen.vhd | 242 ++ ethernet/RoCEv2/rtl/BinaryArbTree.vhd | 217 ++ ethernet/RoCEv2/rtl/BinaryPipeOutArbiter.vhd | 281 ++ ethernet/RoCEv2/rtl/BinaryTreeFork.vhd | 1140 +++++++ ethernet/RoCEv2/rtl/CacheFifo.vhd | 924 ++++++ ethernet/RoCEv2/rtl/ClientArbiter.vhd | 503 +++ ethernet/RoCEv2/rtl/CntrlQp.vhd | 851 +++++ .../RoCEv2/rtl/CombineHeaderAndPayload.vhd | 244 ++ .../rtl/ConnectBramQ2PipeOutConAndGen.vhd | 166 + .../RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd | 172 + .../rtl/ConnectPipeOut2BramQConAndGen.vhd | 198 ++ .../RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd | 201 ++ ethernet/RoCEv2/rtl/ConnectionWithAction.vhd | 97 + ethernet/RoCEv2/rtl/CountCF.vhd | 250 ++ ethernet/RoCEv2/rtl/DataStream2Header.vhd | 350 +++ ethernet/RoCEv2/rtl/DmaArbiter4Qp.vhd | 329 ++ ethernet/RoCEv2/rtl/DmaReadCltArbiter.vhd | 149 + ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd | 616 ++++ ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd | 760 +++++ ethernet/RoCEv2/rtl/DmaWriteCltArbiter.vhd | 173 + ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd | 425 +++ ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd | 334 ++ .../rtl/EthMacCrcAxiStreamWrapperRecv.vhd | 127 - .../rtl/EthMacCrcAxiStreamWrapperSend.vhd | 127 - ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd | 142 - ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd | 130 - ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd | 273 -- ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd | 268 -- .../ExtractHeaderFromDataStreamPipeOut.vhd | 561 ++++ .../rtl/ExtractHeaderFromRdmaPktPipeOut.vhd | 527 ++++ ethernet/RoCEv2/rtl/Header2DataStream.vhd | 346 ++ ethernet/RoCEv2/rtl/HeaderGenRDMA.vhd | 418 +++ ethernet/RoCEv2/rtl/HeaderGenReqSQ.vhd | 465 +++ .../InputRdmaPktBufAndHeaderValidation.vhd | 1682 ++++++++++ ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd | 737 +++++ ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd | 687 ++++ ethernet/RoCEv2/rtl/MetaDataMRs.vhd | 205 ++ ethernet/RoCEv2/rtl/MetaDataPDs.vhd | 326 ++ ethernet/RoCEv2/rtl/MetaDataQPs.vhd | 461 +++ ethernet/RoCEv2/rtl/MetaDataSrv.vhd | 467 +++ .../RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd | 295 ++ .../RoCEv2/rtl/PayloadConsumerConAndGen.vhd | 764 +++++ .../RoCEv2/rtl/PayloadGeneratorConAndGen.vhd | 588 ++++ ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd | 1265 ++++++++ ethernet/RoCEv2/rtl/PermCheckCltArbiter.vhd | 175 ++ ethernet/RoCEv2/rtl/PermCheckSrv.vhd | 482 +++ ethernet/RoCEv2/rtl/PipeOutArbiter.vhd | 123 + ethernet/RoCEv2/rtl/PipeOutMux.vhd | 194 ++ ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd | 497 +++ ethernet/RoCEv2/rtl/Qp.vhd | 1523 +++++++++ .../rtl/RdmaPktMetaDataAndPayloadPipe.vhd | 142 + ethernet/RoCEv2/rtl/RecursiveSearch.vhd | 1038 ++++++ ethernet/RoCEv2/rtl/ReqGenSq.vhd | 1141 +++++++ ethernet/RoCEv2/rtl/ReqHandleRq.vhd | 2777 +++++++++++++++++ ethernet/RoCEv2/rtl/RespHandleSq.vhd | 1621 ++++++++++ ethernet/RoCEv2/rtl/RetryHandleSq.vhd | 951 ++++++ ethernet/RoCEv2/rtl/RoceConfigurator.vhd | 168 - ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd | 540 ++-- ethernet/RoCEv2/rtl/RoceMetaDataAxil.vhd | 443 +++ ethernet/RoCEv2/rtl/RocePkg.vhd | 823 +++-- ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd | 357 --- ethernet/RoCEv2/rtl/Rq.vhd | 462 +++ ethernet/RoCEv2/rtl/ScanFifoF.vhd | 504 +++ ethernet/RoCEv2/rtl/SendQ.vhd | 757 +++++ ethernet/RoCEv2/rtl/ServerArbiter.vhd | 481 +++ ethernet/RoCEv2/rtl/ServerProxy.vhd | 179 ++ ethernet/RoCEv2/rtl/SqQueuePair.vhd | 654 ++++ ethernet/RoCEv2/rtl/SqSendQ.vhd | 385 +++ ethernet/RoCEv2/rtl/TagVecSrv.vhd | 383 +++ ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd | 359 +++ ethernet/RoCEv2/rtl/TransportLayer.vhd | 1024 ++++++ ethernet/RoCEv2/rtl/WorkCompGenRq.vhd | 778 +++++ ethernet/RoCEv2/rtl/WorkCompGenSq.vhd | 692 ++++ .../rtl/WorkReqAndRecvReqDispatcher.vhd | 251 ++ python/surf/ethernet/roce/_RoceEngine.py | 50 - .../surf/ethernet/roce/_RoceMetaDataAxil.py | 650 ++++ python/surf/ethernet/roce/__init__.py | 11 +- 80 files changed, 39807 insertions(+), 2241 deletions(-) create mode 100644 ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd create mode 100644 ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd create mode 100644 ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd create mode 100644 ethernet/RoCEv2/rtl/AtomicSrvConAndGen.vhd create mode 100644 ethernet/RoCEv2/rtl/BinaryArbTree.vhd create mode 100644 ethernet/RoCEv2/rtl/BinaryPipeOutArbiter.vhd create mode 100644 ethernet/RoCEv2/rtl/BinaryTreeFork.vhd create mode 100644 ethernet/RoCEv2/rtl/CacheFifo.vhd create mode 100644 ethernet/RoCEv2/rtl/ClientArbiter.vhd create mode 100644 ethernet/RoCEv2/rtl/CntrlQp.vhd create mode 100644 ethernet/RoCEv2/rtl/CombineHeaderAndPayload.vhd create mode 100644 ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutConAndGen.vhd create mode 100644 ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd create mode 100644 ethernet/RoCEv2/rtl/ConnectPipeOut2BramQConAndGen.vhd create mode 100644 ethernet/RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd create mode 100644 ethernet/RoCEv2/rtl/ConnectionWithAction.vhd create mode 100644 ethernet/RoCEv2/rtl/CountCF.vhd create mode 100644 ethernet/RoCEv2/rtl/DataStream2Header.vhd create mode 100644 ethernet/RoCEv2/rtl/DmaArbiter4Qp.vhd create mode 100644 ethernet/RoCEv2/rtl/DmaReadCltArbiter.vhd create mode 100644 ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd create mode 100644 ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd create mode 100644 ethernet/RoCEv2/rtl/DmaWriteCltArbiter.vhd create mode 100644 ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd create mode 100644 ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd delete mode 100755 ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperRecv.vhd delete mode 100755 ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperSend.vhd delete mode 100755 ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd delete mode 100755 ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd delete mode 100755 ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd delete mode 100755 ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd create mode 100644 ethernet/RoCEv2/rtl/ExtractHeaderFromDataStreamPipeOut.vhd create mode 100644 ethernet/RoCEv2/rtl/ExtractHeaderFromRdmaPktPipeOut.vhd create mode 100644 ethernet/RoCEv2/rtl/Header2DataStream.vhd create mode 100644 ethernet/RoCEv2/rtl/HeaderGenRDMA.vhd create mode 100644 ethernet/RoCEv2/rtl/HeaderGenReqSQ.vhd create mode 100644 ethernet/RoCEv2/rtl/InputRdmaPktBufAndHeaderValidation.vhd create mode 100644 ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd create mode 100644 ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd create mode 100644 ethernet/RoCEv2/rtl/MetaDataMRs.vhd create mode 100644 ethernet/RoCEv2/rtl/MetaDataPDs.vhd create mode 100644 ethernet/RoCEv2/rtl/MetaDataQPs.vhd create mode 100644 ethernet/RoCEv2/rtl/MetaDataSrv.vhd create mode 100644 ethernet/RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd create mode 100644 ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd create mode 100644 ethernet/RoCEv2/rtl/PayloadGeneratorConAndGen.vhd create mode 100644 ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd create mode 100644 ethernet/RoCEv2/rtl/PermCheckCltArbiter.vhd create mode 100644 ethernet/RoCEv2/rtl/PermCheckSrv.vhd create mode 100644 ethernet/RoCEv2/rtl/PipeOutArbiter.vhd create mode 100644 ethernet/RoCEv2/rtl/PipeOutMux.vhd create mode 100644 ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd create mode 100644 ethernet/RoCEv2/rtl/Qp.vhd create mode 100644 ethernet/RoCEv2/rtl/RdmaPktMetaDataAndPayloadPipe.vhd create mode 100644 ethernet/RoCEv2/rtl/RecursiveSearch.vhd create mode 100644 ethernet/RoCEv2/rtl/ReqGenSq.vhd create mode 100644 ethernet/RoCEv2/rtl/ReqHandleRq.vhd create mode 100644 ethernet/RoCEv2/rtl/RespHandleSq.vhd create mode 100644 ethernet/RoCEv2/rtl/RetryHandleSq.vhd delete mode 100755 ethernet/RoCEv2/rtl/RoceConfigurator.vhd mode change 100755 => 100644 ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd create mode 100644 ethernet/RoCEv2/rtl/RoceMetaDataAxil.vhd delete mode 100755 ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd create mode 100644 ethernet/RoCEv2/rtl/Rq.vhd create mode 100644 ethernet/RoCEv2/rtl/ScanFifoF.vhd create mode 100644 ethernet/RoCEv2/rtl/SendQ.vhd create mode 100644 ethernet/RoCEv2/rtl/ServerArbiter.vhd create mode 100644 ethernet/RoCEv2/rtl/ServerProxy.vhd create mode 100644 ethernet/RoCEv2/rtl/SqQueuePair.vhd create mode 100644 ethernet/RoCEv2/rtl/SqSendQ.vhd create mode 100644 ethernet/RoCEv2/rtl/TagVecSrv.vhd create mode 100644 ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd create mode 100644 ethernet/RoCEv2/rtl/TransportLayer.vhd create mode 100644 ethernet/RoCEv2/rtl/WorkCompGenRq.vhd create mode 100644 ethernet/RoCEv2/rtl/WorkCompGenSq.vhd create mode 100644 ethernet/RoCEv2/rtl/WorkReqAndRecvReqDispatcher.vhd delete mode 100644 python/surf/ethernet/roce/_RoceEngine.py create mode 100644 python/surf/ethernet/roce/_RoceMetaDataAxil.py diff --git a/ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd b/ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd new file mode 100644 index 0000000000..a86cc11511 --- /dev/null +++ b/ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd @@ -0,0 +1,417 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Server#(AddrChunkReq, AddrChunkResp) plus a combinational isIdle() method. +-- Accepts a single AddrChunkReq (startAddr, totalLen, pmtu) into U_ReqQ and, +-- while busy, emits one AddrChunkResp per PMTU-sized chunk into U_RespQ: +-- walking the address forward by one PMTU each beat and shrinking the +-- remaining-chunk count, flagging the first and last chunk and using the +-- residue length on the final chunk when totalLen is not an exact multiple +-- of the PMTU. +-- +-- FSM states (mapped from BSV busyReg): +-- IDLE_S ('0') — waiting for a request (recvReq fires here) +-- BUSY_S ('1') — emitting chunk responses (genResp fires here) +-- +-- BSV rules implemented: +-- resetAndClear — guard clearAllI='1'; clears both FIFOs via rst, forces +-- IDLE_S and isFirstReg='0'. LEVEL-asserted. +-- recvReq — guard !clearAllI AND !busyReg (IDLE_S); implicit cond +-- reqQValid='1'. Latches the request context, computes +-- residue / pmtuLen / chunk count, advances to BUSY_S. +-- genResp — guard !clearAllI AND busyReg (BUSY_S); implicit cond +-- respQFull='0'. Emits one AddrChunkResp, decrements the +-- count, advances the address; returns to IDLE_S on the +-- last chunk. +-- +-- Mapping note (OQ-FSM-ACSCAG-01, see fsm.md §mismatch): +-- mapping.json / modules.json record fabricated rule names +-- (genChunk/lastChunk) and wrong state/ports for this entity; this file +-- and the FSM spec are authoritative. +-- +-- isSQ module parameter (OQ-FSM-ACSCAG-02, RESOLVED): functionally dead — +-- referenced only inside a fully commented-out debug rule. Per the +-- resolution the isSQI port is OMITTED from this entity. +-- +-- FIFO clear (OQ-FSM-01 carry-forward, RESOLVED in RESOLVED.md): +-- BSV reqQ.clear / respQ.clear map to asserting each Fifo's rst, OR'd with +-- the structural reset: fifoRst = rst OR clearAllI. surf.FifoSync holds +-- logically empty for the whole asserted window (level-safe); no pulse +-- generator needed. Requires GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, +-- RST_POLARITY_G='1'. +-- +-- SURF components instantiated: +-- U_ReqQ : surf.Fifo DATA_WIDTH_G=99, FWFT, sync, block RAM +-- (AddrChunkReq; source: surf/base/fifo/rtl/Fifo.vhd) +-- U_RespQ : surf.Fifo DATA_WIDTH_G=79, FWFT, sync, block RAM +-- (AddrChunkResp; source: surf/base/fifo/rtl/Fifo.vhd) +-- Block RAM FWFT cold latency is 2 cycles (DOB reg) — see tb-spec §8. +-- +-- AddrChunkReq bit layout (BSV deriving(Bits), first-field-at-MSB): +-- [98:35] startAddr[63:0] (64 bits) +-- [34:3] totalLen[31:0] (32 bits) +-- [2:0] pmtu[2:0] (3 bits) +-- +-- AddrChunkResp bit layout (BSV deriving(Bits), first-field-at-MSB): +-- [78:15] chunkAddr[63:0] (64 bits) +-- [14:2] chunkLen[12:0] (13 bits) +-- [1] isFirst +-- [0] isLast +-- +-- PMTU enum (DataTypes.bsv:407-413): IBV_MTU_256=1 .. IBV_MTU_4096=5. +-- Byte length = 2**(pmtu+7): 256, 512, 1024, 2048, 4096. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity AddrChunkSrvConAndGen is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (synchronous; LEVEL-asserted while high) + clearAllI : in sl; + -- srvPort.request : Put#(AddrChunkReq) (caller -> entity) + reqPutValid : in sl; -- caller offers a request (wr_en) + reqPutData : in slv(98 downto 0); -- AddrChunkReq packed + reqPutReady : out sl; -- entity can accept (reqQ.notFull) + -- srvPort.response : Get#(AddrChunkResp) (entity -> caller) + respGetReady : in sl; -- caller takes a response (rd_en) + respGetValid : out sl; -- response available (respQ.notEmpty) + respGetData : out slv(78 downto 0); -- AddrChunkResp packed + -- status method + isIdle : out sl); -- !busyReg AND reqQ empty AND respQ empty +end entity AddrChunkSrvConAndGen; + +architecture rtl of AddrChunkSrvConAndGen is + + -- FSM state type (maps BSV busyReg: False->IDLE_S, True->BUSY_S) + type StateType is (IDLE_S, BUSY_S); + + type RegType is record + state : StateType; -- busyReg + isFirstReg : sl; -- mkReg(False) + fullPktLenReg : slv(12 downto 0); -- mkRegU — full (non-residue) chunk length + residueReg : slv(11 downto 0); -- mkRegU — leftover bytes of final chunk + isZeroResidueReg : sl; -- mkRegU — totalLen is exact PMTU multiple + pktNumReg : slv(24 downto 0); -- mkRegU — remaining chunk count (down-counter) + chunkAddrReg : slv(63 downto 0); -- mkRegU — address of next chunk + pmtuReg : slv(2 downto 0); -- mkRegU — latched PMTU + end record RegType; + + -- mkRegU fields set to '0' in REG_INIT_C: recvReq writes every one of them + -- unconditionally on IDLE_S->BUSY_S, strictly before genResp (the only + -- reader) can fire. No correctness risk (fsm.md §State register). + constant REG_INIT_C : RegType := ( + state => IDLE_S, + isFirstReg => '0', + fullPktLenReg => (others => '0'), + residueReg => (others => '0'), + isZeroResidueReg => '0', + pktNumReg => (others => '0'), + chunkAddrReg => (others => '0'), + pmtuReg => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_ReqQ interface signals + signal reqQFull : sl; + signal reqQValid : sl; + signal reqQDout : slv(98 downto 0); + signal reqQRdEn : sl; + + -- U_RespQ interface signals + signal respQFull : sl; + signal respQValid : sl; + signal respQWrEn : sl; + signal respQDin : slv(78 downto 0); + + -- FIFO reset line: level = rst OR clearAllI (see FIFO clear note above) + signal fifoRst : sl; + +begin + + -- FIFO reset: level-sensitive clear (OQ-FSM-01 carry-forward, RESOLVED) + fifoRst <= rst or clearAllI; + + -- srvPort.request boundary wiring (pass-through; not FSM-gated) + reqPutReady <= not reqQFull; -- reqQ.notFull readiness to caller + + -- isIdle() method (combinational / Mealy): + -- !busyReg AND !reqQ.notEmpty AND !respQ.notEmpty + isIdle <= '1' when (r.state = IDLE_S and reqQValid = '0' and respQValid = '0') + else '0'; + + --------------------------------------------------------------------------- + -- U_ReqQ : surf.Fifo + -- Inbound AddrChunkReq queue (BSV mkFIFOF reqQ). wr side is the caller's + -- srvPort.request.put (pass-through); rd side is consumed by recvReq. + --------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 99, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqPutValid, -- pass-through (caller drives) + din => reqPutData, -- pass-through (caller drives) + full => reqQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => reqQRdEn, -- FSM (recvReq) + dout => reqQDout, + valid => reqQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_RespQ : surf.Fifo + -- Outbound AddrChunkResp queue (BSV mkFIFOF respQ). wr side is driven by + -- genResp; rd side is the caller's srvPort.response.get (pass-through). + --------------------------------------------------------------------------- + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 79, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => respQWrEn, -- FSM (genResp) + din => respQDin, -- FSM (genResp) + full => respQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => respGetReady, -- pass-through (caller drives) + dout => respGetData, + valid => respQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + respGetValid <= respQValid; -- pass-through to caller + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, clearAllI, reqQValid, reqQDout, respQFull) is + variable v : RegType; + -- recvReq datapath temporaries (from reqQDout, AddrChunkReq layout) + variable startAddr : slv(63 downto 0); + variable totalLen : slv(31 downto 0); + variable pmtu : slv(2 downto 0); + variable residue : slv(11 downto 0); + variable tmpPktNum : slv(24 downto 0); + variable pmtuLen : slv(12 downto 0); + variable isZeroResidue : sl; + variable totalPktNum : slv(24 downto 0); + -- genResp datapath temporaries (from r) + variable isLast : sl; + variable chunkLen : slv(12 downto 0); + variable nextChunkAddr : slv(63 downto 0); + begin + v := r; + + -- default Mealy outputs (deasserted; overridden below per transition) + reqQRdEn <= '0'; + respQWrEn <= '0'; + respQDin <= (others => '0'); + + ---------------------------------------------------------------------- + -- recvReq datapath (combinational; valid only when reqQDout holds a + -- request, but harmless to compute every cycle) + -- startAddr = reqQDout[98:35], totalLen = reqQDout[34:3], + -- pmtu = reqQDout[2:0] + -- residue = totalLen low (pmtu+7) bits, zero-extended to 12b + -- tmpPktNum = totalLen high bits, zero-extended to 25b + -- pmtuLen = 2**(pmtu+7) = chunk byte length + ---------------------------------------------------------------------- + startAddr := reqQDout(98 downto 35); + totalLen := reqQDout(34 downto 3); + pmtu := reqQDout(2 downto 0); + + case pmtu is + when "001" => -- IBV_MTU_256 (k=8) + residue := "0000" & totalLen(7 downto 0); + tmpPktNum := "0" & totalLen(31 downto 8); + pmtuLen := slv(to_unsigned(256, 13)); + when "010" => -- IBV_MTU_512 (k=9) + residue := "000" & totalLen(8 downto 0); + tmpPktNum := "00" & totalLen(31 downto 9); + pmtuLen := slv(to_unsigned(512, 13)); + when "011" => -- IBV_MTU_1024 (k=10) + residue := "00" & totalLen(9 downto 0); + tmpPktNum := "000" & totalLen(31 downto 10); + pmtuLen := slv(to_unsigned(1024, 13)); + when "100" => -- IBV_MTU_2048 (k=11) + residue := "0" & totalLen(10 downto 0); + tmpPktNum := "0000" & totalLen(31 downto 11); + pmtuLen := slv(to_unsigned(2048, 13)); + when "101" => -- IBV_MTU_4096 (k=12) + residue := totalLen(11 downto 0); + tmpPktNum := "00000" & totalLen(31 downto 12); + pmtuLen := slv(to_unsigned(4096, 13)); + when others => -- invalid PMTU (should not occur) + residue := (others => '0'); + tmpPktNum := (others => '0'); + pmtuLen := (others => '0'); + end case; + + if (unsigned(residue) = 0) then + isZeroResidue := '1'; + totalPktNum := tmpPktNum; + else + isZeroResidue := '0'; + totalPktNum := slv(unsigned(tmpPktNum) + 1); + end if; + + ---------------------------------------------------------------------- + -- genResp datapath (combinational; reads current r) + -- isLast = (pktNumReg <= 1) + -- nextChunkAddr = chunkAddrReg + pmtuLen (= addrAddPsnMultiplyPMTU, + -- psn=1; equals chunkAddrReg + 2**(pmtu+7)) + -- chunkLen = (isLast AND !isZeroResidueReg) ? residue : fullPktLen + ---------------------------------------------------------------------- + if (unsigned(r.pktNumReg) <= 1) then + isLast := '1'; + else + isLast := '0'; + end if; + + nextChunkAddr := slv(unsigned(r.chunkAddrReg) + + resize(unsigned(r.fullPktLenReg), 64)); + + if (isLast = '1' and r.isZeroResidueReg = '0') then + chunkLen := "0" & r.residueReg; -- zeroExtend(residueReg) to 13b + else + chunkLen := r.fullPktLenReg; + end if; + + ---------------------------------------------------------------------- + -- Rule scheduling: clearAllI first (resetAndClear), else case on state. + -- Guards are pairwise mutually exclusive (fsm.md §scheduling). + ---------------------------------------------------------------------- + if clearAllI = '1' then + -- resetAndClear: FIFOs cleared via fifoRst pins; force power-on state + v.state := IDLE_S; + v.isFirstReg := '0'; + + else + case r.state is + + -- --------------------------------------------------------------- + -- IDLE_S: recvReq (implicit condition reqQValid='1') + -- --------------------------------------------------------------- + when IDLE_S => + if reqQValid = '1' then + reqQRdEn <= '1'; -- reqQ.deq + v.fullPktLenReg := pmtuLen; + v.residueReg := residue; + v.isZeroResidueReg := isZeroResidue; + v.pktNumReg := totalPktNum; + v.chunkAddrReg := startAddr; + v.pmtuReg := pmtu; + v.isFirstReg := '1'; + v.state := BUSY_S; + end if; + + -- --------------------------------------------------------------- + -- BUSY_S: genResp (implicit condition respQFull='0') + -- --------------------------------------------------------------- + when BUSY_S => + -- AddrChunkResp = chunkAddr[63:0] & chunkLen[12:0] & isFirst & isLast + respQDin <= r.chunkAddrReg & chunkLen & r.isFirstReg & isLast; + if respQFull = '0' then + respQWrEn <= '1'; -- respQ.enq + v.pktNumReg := slv(unsigned(r.pktNumReg) - 1); + v.chunkAddrReg := nextChunkAddr; + v.isFirstReg := '0'; + if isLast = '1' then + v.state := IDLE_S; -- busyReg <= False + end if; + end if; + -- respQFull='1' -> whole rule stalls; all registers hold. + + end case; + end if; + + -- Synchronous reset (overrides FSM; matches BSV mkReg(False) state) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + --------------------------------------------------------------------------- + -- Simulation-only assertion (no synthesizable effect): totalLen /= 0 + -- (BSV immAssert in recvReq, fsm.md §recvReq; cf. OQ-FSM-DS2H-04 treatment). + --------------------------------------------------------------------------- + -- pragma translate_off + chk : process (clk) is + begin + if rising_edge(clk) then + if (rst = '0' and clearAllI = '0' and r.state = IDLE_S and + reqQValid = '1') then + assert unsigned(reqQDout(34 downto 3)) /= 0 + report "AddrChunkSrvConAndGen: totalLen must not be zero" + severity error; + end if; + end if; + end process chk; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd b/ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd new file mode 100644 index 0000000000..91e50ed63e --- /dev/null +++ b/ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd @@ -0,0 +1,787 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- AddrChunkSrv interface: +-- srvPort : Server#(AddrChunkReq, AddrChunkResp) +-- sgePktMetaDataPipeOut : PipeOut#(PktMetaDataSGE) +-- isIdle() : combinational status method +-- +-- This is the "Gen" variant: a 4-stage FIFO-decoupled pipeline that takes ONE +-- AddrChunkReq per SGE (already tagged isFirst/isLast by the parent +-- mkDmaReadCntrl) and explodes it into PMTU-sized address chunks, tagging each +-- emitted chunk with the original SGE's first/last flags (isOrigFirst/ +-- isOrigLast) and producing a side-channel PktMetaDataSGE stream. +-- +-- This entity does NOT iterate over scatter-gather entries — that loop lives in +-- the parent (OQ-FSM-ACSG-01). reqQ's depth-8 sizing (mkSizedFIFOF(MAX_SGE=8)) +-- is just buffering, not internal SGE iteration. +-- +-- Pipeline (all four stages decoupled; disjoint FIFO pairs, can co-fire): +-- Stage A recvReq reqQ -> calcChunkMetaDataQ +-- Stage B calcChunkMetaData calcChunkMetaDataQ -> calcPktMetaDataQ4SGE +-- Stage C genPktMetaDataSGE calcPktMetaDataQ4SGE +-- -> sgePktMetaDataOutQ + calcAddrChunkRespQ +-- Stage D genResp calcAddrChunkRespQ -> respQ (the real FSM) +-- Stages A/B/C are stateless pass-throughs; only stage D carries control state +-- (isFirstChunkReg) because it replays one calcAddrChunkRespQ entry across +-- multiple cycles, emitting one chunk response per cycle (peek; deq only on the +-- last chunk). +-- +-- Mapping note (OQ-FSM-ACSG-01, see fsm.md §mismatch): +-- mapping.json / modules.json record fabricated rules +-- (recvSglReq/genSgeChunk/lastSge) and state (sgeIdxReg/addrReg/lenReg/ +-- stateReg), miss the sgePktMetaDataPipeOut output, and list only 2 of the 6 +-- FIFOs. This file and the FSM spec are authoritative. +-- +-- isIdle() (OQ-FSM-ACSG-02): no consumer at the only instantiation site, but +-- kept anyway — purely combinational, cheap, useful for verification. +-- +-- FIFO clear (OQ-FSM-01 carry-forward, RESOLVED): BSV resetAndClear (guard +-- clearAll) calls .clear on ALL SIX FIFOs in one cycle. Modelled by asserting +-- each Fifo's rst, OR'd with the structural reset: fifoRst = rst OR clearAllI. +-- surf.FifoSync holds logically empty for the whole asserted window +-- (level-safe); no pulse generator. Requires GEN_SYNC_FIFO_G=true, +-- RST_ASYNC_G=false, RST_POLARITY_G='1'. +-- +-- SURF components instantiated (all surf.Fifo, FWFT, sync, block RAM; +-- source: surf/base/fifo/rtl/Fifo.vhd): +-- U_ReqQ DATA_WIDTH_G=101 depth 16 (AddrChunkReq; MAX_SGE buf) +-- U_RespQ DATA_WIDTH_G=81 (AddrChunkResp) +-- U_SgePktMetaDataOutQ DATA_WIDTH_G=54 (PktMetaDataSGE) +-- U_CalcChunkMetaDataQ DATA_WIDTH_G=255 (internal pipeline handoff, Stage A->B) +-- U_CalcPktMetaDataQ4SGE DATA_WIDTH_G=215 (internal pipeline handoff, Stage B->C) +-- U_CalcAddrChunkRespQ DATA_WIDTH_G=197 (internal pipeline handoff, Stage C->D) +-- Block RAM FWFT cold latency is 2 cycles (DOB reg) — see tb-spec §8. +-- +-- Struct bit layouts (BSV deriving(Bits), first-field-at-MSB, OQ-FSM-H2DS-04): +-- +-- AddrChunkReq (101 bits): +-- [100:37] startAddr[63:0] [36:5] len[31:0] [4:2] pmtu[2:0] +-- [1] isFirst [0] isLast +-- +-- AddrChunkResp (81 bits): +-- [80:17] chunkAddr[63:0] [16:4] chunkLen[12:0] [3] isFirst [2] isLast +-- [1] isOrigFirst [0] isOrigLast +-- +-- PktMetaDataSGE (54 bits): +-- [53:41] firstPktLen[12:0] [40:28] lastPktLen[12:0] +-- [27:3] sgePktNum[24:0] [2:0] pmtu[2:0] +-- +-- calcChunkMetaDataQ element (255 bits, internal): +-- [254:242] pmtuMask [241:229] addrAndLenLowPartSum [228:216] pmtuLen +-- [215:203] lenLowPart [202:190] maxFirstPktLen [189:165] truncatedPktNum +-- [164:101] pmtuAlignedStartAddr [100:0] addrChunkReq +-- +-- calcPktMetaDataQ4SGE element (TmpPktMetaDataSGE, 215 bits, internal): +-- [214:213] pktNumAddOne [212:188] truncatedPktNum [187:175] lenLowPart +-- [174:162] maxFirstPktLen [161:149] tmpLastPktLen [148:136] pmtuLen +-- [135:133] pmtu [132:69] startAddr [68:5] nextAddr [4] notFullPkt +-- [3] hasExtraPkt [2] hasResidue [1] isOrigFirst [0] isOrigLast +-- +-- calcAddrChunkRespQ element (TmpChunkRespData, 197 bits, internal): +-- [196:172] sgePktNum [171:159] firstPktLen [158:146] pmtuLen +-- [145:133] lastPktLen [132:130] pmtu [129:66] startAddr [65:2] nextAddr +-- [1] isOrigFirst [0] isOrigLast +-- +-- PMTU enum (DataTypes.bsv:407-413): IBV_MTU_256=1 .. IBV_MTU_4096=5. +-- k = log2(pmtuLen) = pmtu+7 ∈ {8,9,10,11,12}; pmtuLen = 2**k. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity AddrChunkSrvGen is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (synchronous; LEVEL-asserted while high) + clearAllI : in sl; + -- srvPort.request : Put#(AddrChunkReq) (caller -> entity) + reqPutValid : in sl; -- caller offers a request (wr_en) + reqPutData : in slv(100 downto 0); -- AddrChunkReq packed + reqPutReady : out sl; -- entity can accept (reqQ.notFull) + -- srvPort.response : Get#(AddrChunkResp) (entity -> caller) + respGetReady : in sl; -- caller takes a response (rd_en) + respGetValid : out sl; -- response available (respQ.notEmpty) + respGetData : out slv(80 downto 0); -- AddrChunkResp packed + -- sgePktMetaDataPipeOut : PipeOut#(PktMetaDataSGE) (entity -> caller) + sgePktMetaRdEn : in sl; -- caller deq + sgePktMetaValid : out sl; -- data available + sgePktMetaData : out slv(53 downto 0); -- PktMetaDataSGE packed + -- status method + isIdle : out sl); -- all six FIFOs empty +end entity AddrChunkSrvGen; + +architecture rtl of AddrChunkSrvGen is + + -- genResp control state (maps BSV isFirstChunkReg: + -- True -> NEWCHUNK_S (ready to start a fresh calcAddrChunkRespQ entry) + -- False -> CONTCHUNK_S (mid-entry, replaying further chunks)) + type StateType is (NEWCHUNK_S, CONTCHUNK_S); + + type RegType is record + state : StateType; -- isFirstChunkReg (mkReg(True)) + remainingPktNumReg : slv(24 downto 0); -- mkRegU — chunks left for in-flight entry + nextChunkAddrReg : slv(63 downto 0); -- mkRegU — address of chunk about to emit + end record RegType; + + -- isFirstChunkReg resets to '1' (NEWCHUNK_S), matching BSV mkReg(True). + -- The two mkRegU fields are set to '0': on the first-ever genResp firing, + -- state=NEWCHUNK_S forces the override branch (remaining:=sgePktNum, + -- nextChunkAddr:=nextAddr, chunkAddr:=startAddr) strictly before either is + -- read, so the reset value is never observed (fsm.md §Reset behavior). + constant REG_INIT_C : RegType := ( + state => NEWCHUNK_S, + remainingPktNumReg => (others => '0'), + nextChunkAddrReg => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- FIFO reset line: level = rst OR clearAllI (drives all six U_*Q.rst) + signal fifoRst : sl; + + -- U_ReqQ + signal reqQFull : sl; + signal reqQValid : sl; + signal reqQDout : slv(100 downto 0); + signal reqQRdEn : sl; + + -- U_RespQ + signal respQFull : sl; + signal respQValid : sl; + signal respQWrEn : sl; + signal respQDin : slv(80 downto 0); + + -- U_SgePktMetaDataOutQ + signal sgeQFull : sl; + signal sgeQValid : sl; + signal sgeQWrEn : sl; + signal sgeQDin : slv(53 downto 0); + + -- U_CalcChunkMetaDataQ (Stage A -> B, internal) + signal ccmdQFull : sl; + signal ccmdQValid : sl; + signal ccmdQDout : slv(254 downto 0); + signal ccmdQWrEn : sl; + signal ccmdQDin : slv(254 downto 0); + signal ccmdQRdEn : sl; + + -- U_CalcPktMetaDataQ4SGE (Stage B -> C, internal) + signal cpmdQFull : sl; + signal cpmdQValid : sl; + signal cpmdQDout : slv(214 downto 0); + signal cpmdQWrEn : sl; + signal cpmdQDin : slv(214 downto 0); + signal cpmdQRdEn : sl; + + -- U_CalcAddrChunkRespQ (Stage C -> D, internal) + signal cacrQFull : sl; + signal cacrQValid : sl; + signal cacrQDout : slv(196 downto 0); + signal cacrQWrEn : sl; + signal cacrQDin : slv(196 downto 0); + signal cacrQRdEn : sl; + +begin + + -- FIFO reset: level-sensitive clear (OQ-FSM-01 carry-forward, all six FIFOs) + fifoRst <= rst or clearAllI; + + -- Boundary pass-throughs (not FSM-gated) + reqPutReady <= not reqQFull; -- reqQ.notFull readiness to caller + respGetValid <= respQValid; -- respQ.notEmpty + sgePktMetaValid <= sgeQValid; -- sgePktMetaDataOutQ.notEmpty + + -- isIdle() method: !(any of the six FIFOs notEmpty) (PayloadGen.bsv:652-659) + isIdle <= '1' when (reqQValid = '0' and respQValid = '0' and ccmdQValid = '0' and + cpmdQValid = '0' and cacrQValid = '0' and sgeQValid = '0') + else '0'; + + --------------------------------------------------------------------------- + -- U_ReqQ : surf.Fifo (AddrChunkReq inbound; depth MAX_SGE=8 -> ADDR_WIDTH 4) + -- wr side = caller srvPort.request.put (pass-through); rd side = recvReq. + --------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 101, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqPutValid, -- pass-through (caller drives) + din => reqPutData, -- pass-through (caller drives) + full => reqQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => reqQRdEn, -- Stage A (recvReq) + dout => reqQDout, + valid => reqQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_CalcChunkMetaDataQ : surf.Fifo (Stage A -> Stage B, internal handoff) + --------------------------------------------------------------------------- + U_CalcChunkMetaDataQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 255, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => ccmdQWrEn, -- Stage A + din => ccmdQDin, -- Stage A + full => ccmdQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => ccmdQRdEn, -- Stage B + dout => ccmdQDout, + valid => ccmdQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_CalcPktMetaDataQ4SGE : surf.Fifo (Stage B -> Stage C, internal handoff) + --------------------------------------------------------------------------- + U_CalcPktMetaDataQ4SGE : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 215, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => cpmdQWrEn, -- Stage B + din => cpmdQDin, -- Stage B + full => cpmdQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => cpmdQRdEn, -- Stage C + dout => cpmdQDout, + valid => cpmdQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_CalcAddrChunkRespQ : surf.Fifo (Stage C -> Stage D, internal handoff) + -- Peeked (dout/valid) by genResp every firing; deq only on the last chunk. + --------------------------------------------------------------------------- + U_CalcAddrChunkRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 197, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => cacrQWrEn, -- Stage C + din => cacrQDin, -- Stage C + full => cacrQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => cacrQRdEn, -- Stage D (only on isLastChunk) + dout => cacrQDout, + valid => cacrQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_SgePktMetaDataOutQ : surf.Fifo (PktMetaDataSGE side-channel out) + -- wr side = Stage C; rd side = caller sgePktMetaDataPipeOut (pass-through). + --------------------------------------------------------------------------- + U_SgePktMetaDataOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 54, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => sgeQWrEn, -- Stage C + din => sgeQDin, -- Stage C + full => sgeQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => sgePktMetaRdEn, -- pass-through (caller drives) + dout => sgePktMetaData, -- pass-through to caller + valid => sgeQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_RespQ : surf.Fifo (AddrChunkResp outbound) + -- wr side = Stage D (genResp); rd side = caller srvPort.response.get. + --------------------------------------------------------------------------- + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 81, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => respQWrEn, -- Stage D + din => respQDin, -- Stage D + full => respQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => respGetReady, -- pass-through (caller drives) + dout => respGetData, -- pass-through to caller + valid => respQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + -- Four independent stage blocks (A/B/C stateless, D is the FSM) plus the + -- resetAndClear branch. Within !clearAllI the four stages are non-conflict + -- (disjoint FIFO pairs) and each is its own implicit-condition-gated block. + --------------------------------------------------------------------------- + comb : process (r, rst, clearAllI, + reqQValid, reqQDout, + ccmdQValid, ccmdQDout, ccmdQFull, + cpmdQValid, cpmdQDout, cpmdQFull, + cacrQValid, cacrQDout, cacrQFull, + sgeQFull, respQFull) is + variable v : RegType; + + -- Stage A (recvReq) temporaries + variable aStartAddr : slv(63 downto 0); + variable aLen : slv(31 downto 0); + variable aPmtu : slv(2 downto 0); + variable aPmtuMask : slv(12 downto 0); + variable aAddrLow : slv(12 downto 0); + variable aLenLow : slv(12 downto 0); + variable aTruncPN : slv(24 downto 0); + variable aAligned : slv(63 downto 0); + variable aPmtuLen : slv(12 downto 0); + variable aMaxFirst : slv(12 downto 0); + variable aSum : slv(12 downto 0); + + -- Stage B (calcChunkMetaData) temporaries + variable bPmtuMask : slv(12 downto 0); + variable bSum : slv(12 downto 0); + variable bPmtuLen : slv(12 downto 0); + variable bLenLow : slv(12 downto 0); + variable bMaxFirst : slv(12 downto 0); + variable bTruncPN : slv(24 downto 0); + variable bAligned : slv(63 downto 0); + variable bStartAddr : slv(63 downto 0); + variable bPmtu : slv(2 downto 0); + variable bIsFirst : sl; + variable bIsLast : sl; + variable bSecond : slv(63 downto 0); + variable bResMasked : slv(12 downto 0); + variable bTmpLast : slv(12 downto 0); + variable bInvMask : slv(12 downto 0); + variable bNotFull : sl; + variable bHasRes : sl; + variable bHasExtra : sl; + variable bAddOne : slv(1 downto 0); + + -- Stage C (genPktMetaDataSGE) temporaries + variable cAddOne : slv(1 downto 0); + variable cTruncPN : slv(24 downto 0); + variable cLenLow : slv(12 downto 0); + variable cMaxFirst : slv(12 downto 0); + variable cTmpLast : slv(12 downto 0); + variable cPmtuLen : slv(12 downto 0); + variable cPmtu : slv(2 downto 0); + variable cStartAddr : slv(63 downto 0); + variable cNextAddr : slv(63 downto 0); + variable cNotFull : sl; + variable cHasExtra : sl; + variable cHasRes : sl; + variable cOrigFirst : sl; + variable cOrigLast : sl; + variable cTotalPN : slv(24 downto 0); + variable cFirst : slv(12 downto 0); + variable cLast : slv(12 downto 0); + + -- Stage D (genResp) temporaries + variable dSgePktNum : slv(24 downto 0); + variable dFirst : slv(12 downto 0); + variable dPmtuLen : slv(12 downto 0); + variable dLast : slv(12 downto 0); + variable dStartAddr : slv(63 downto 0); + variable dNextAddr : slv(63 downto 0); + variable dOrigFirst : sl; + variable dOrigLast : sl; + variable dRemaining : slv(24 downto 0); + variable dNextChunk : slv(63 downto 0); + variable dIsLast : sl; + variable dChunkAddr : slv(63 downto 0); + variable dChunkLen : slv(12 downto 0); + variable dIsFirst : sl; + begin + v := r; + + -- Default Mealy outputs (deasserted; overridden per firing stage) + reqQRdEn <= '0'; + ccmdQWrEn <= '0'; + ccmdQDin <= (others => '0'); + ccmdQRdEn <= '0'; + cpmdQWrEn <= '0'; + cpmdQDin <= (others => '0'); + cpmdQRdEn <= '0'; + sgeQWrEn <= '0'; + sgeQDin <= (others => '0'); + cacrQWrEn <= '0'; + cacrQDin <= (others => '0'); + cacrQRdEn <= '0'; + respQWrEn <= '0'; + respQDin <= (others => '0'); + + if clearAllI = '1' then + -- resetAndClear: FIFOs flushed via fifoRst pins; force power-on state. + -- remainingPktNumReg / nextChunkAddrReg untouched (BSV never assigns + -- them here; overwritten by the next NEWCHUNK genResp before any read). + v.state := NEWCHUNK_S; + + else + ------------------------------------------------------------------- + -- Stage A : recvReq (reqQ -> calcChunkMetaDataQ) + -- impl. cond: reqQValid='1' AND calcChunkMetaDataQ not full + ------------------------------------------------------------------- + if (reqQValid = '1' and ccmdQFull = '0') then + aStartAddr := reqQDout(100 downto 37); + aLen := reqQDout(36 downto 5); + aPmtu := reqQDout(4 downto 2); + + case aPmtu is + when "001" => -- IBV_MTU_256 (k=8) + aPmtuMask := slv(to_unsigned(255, 13)); + aAddrLow := "00000" & aStartAddr(7 downto 0); + aLenLow := "00000" & aLen(7 downto 0); + aTruncPN := "0" & aLen(31 downto 8); + aAligned := aStartAddr(63 downto 8) & "00000000"; + aPmtuLen := slv(to_unsigned(256, 13)); + when "010" => -- IBV_MTU_512 (k=9) + aPmtuMask := slv(to_unsigned(511, 13)); + aAddrLow := "0000" & aStartAddr(8 downto 0); + aLenLow := "0000" & aLen(8 downto 0); + aTruncPN := "00" & aLen(31 downto 9); + aAligned := aStartAddr(63 downto 9) & "000000000"; + aPmtuLen := slv(to_unsigned(512, 13)); + when "011" => -- IBV_MTU_1024 (k=10) + aPmtuMask := slv(to_unsigned(1023, 13)); + aAddrLow := "000" & aStartAddr(9 downto 0); + aLenLow := "000" & aLen(9 downto 0); + aTruncPN := "000" & aLen(31 downto 10); + aAligned := aStartAddr(63 downto 10) & "0000000000"; + aPmtuLen := slv(to_unsigned(1024, 13)); + when "100" => -- IBV_MTU_2048 (k=11) + aPmtuMask := slv(to_unsigned(2047, 13)); + aAddrLow := "00" & aStartAddr(10 downto 0); + aLenLow := "00" & aLen(10 downto 0); + aTruncPN := "0000" & aLen(31 downto 11); + aAligned := aStartAddr(63 downto 11) & "00000000000"; + aPmtuLen := slv(to_unsigned(2048, 13)); + when "101" => -- IBV_MTU_4096 (k=12) + aPmtuMask := slv(to_unsigned(4095, 13)); + aAddrLow := "0" & aStartAddr(11 downto 0); + aLenLow := "0" & aLen(11 downto 0); + aTruncPN := "00000" & aLen(31 downto 12); + aAligned := aStartAddr(63 downto 12) & "000000000000"; + aPmtuLen := slv(to_unsigned(4096, 13)); + when others => -- invalid PMTU (should not occur) + aPmtuMask := (others => '0'); + aAddrLow := (others => '0'); + aLenLow := (others => '0'); + aTruncPN := (others => '0'); + aAligned := (others => '0'); + aPmtuLen := (others => '0'); + end case; + + aMaxFirst := slv(unsigned(aPmtuLen) - unsigned(aAddrLow)); + aSum := slv(unsigned(aAddrLow) + unsigned(aLenLow)); + + reqQRdEn <= '1'; -- reqQ.deq + ccmdQWrEn <= '1'; -- calcChunkMetaDataQ.enq + ccmdQDin <= aPmtuMask & aSum & aPmtuLen & aLenLow & aMaxFirst & + aTruncPN & aAligned & reqQDout; + end if; + + ------------------------------------------------------------------- + -- Stage B : calcChunkMetaData (calcChunkMetaDataQ -> calcPktMetaDataQ4SGE) + -- impl. cond: calcChunkMetaDataQValid='1' AND calcPktMetaDataQ4SGE not full + ------------------------------------------------------------------- + if (ccmdQValid = '1' and cpmdQFull = '0') then + bPmtuMask := ccmdQDout(254 downto 242); + bSum := ccmdQDout(241 downto 229); + bPmtuLen := ccmdQDout(228 downto 216); + bLenLow := ccmdQDout(215 downto 203); + bMaxFirst := ccmdQDout(202 downto 190); + bTruncPN := ccmdQDout(189 downto 165); + bAligned := ccmdQDout(164 downto 101); + bStartAddr := ccmdQDout(100 downto 37); -- addrChunkReq.startAddr + bPmtu := ccmdQDout(4 downto 2); -- addrChunkReq.pmtu + bIsFirst := ccmdQDout(1); -- addrChunkReq.isFirst + bIsLast := ccmdQDout(0); -- addrChunkReq.isLast + + -- secondChunkStartAddr = addrAddPsnMultiplyPMTU(aligned,1,pmtu) + -- = pmtuAlignedStartAddr + pmtuLen + bSecond := slv(unsigned(bAligned) + resize(unsigned(bPmtuLen), 64)); + + -- residue = low-k bits of addrAndLenLowPartSum (= mask AND sum); + -- tmpLastPktLen = zeroExtend(residue) (already 13-bit) + bResMasked := bPmtuMask and bSum; + bTmpLast := bResMasked; + bInvMask := not bPmtuMask; + + if (unsigned(bResMasked) = 0) then bHasRes := '0'; else bHasRes := '1'; end if; + if (unsigned(bInvMask and bSum) = 0) then bHasExtra := '0'; else bHasExtra := '1'; end if; + if (unsigned(bTruncPN) = 0) then bNotFull := '1'; else bNotFull := '0'; end if; + + -- pktNumAddOne = zeroExtend(hasResidue) + zeroExtend(hasExtraPkt) (0..2) + bAddOne := slv(unsigned'("0" & bHasRes) + unsigned'("0" & bHasExtra)); + + ccmdQRdEn <= '1'; -- calcChunkMetaDataQ.deq + cpmdQWrEn <= '1'; -- calcPktMetaDataQ4SGE.enq + cpmdQDin <= bAddOne & bTruncPN & bLenLow & bMaxFirst & bTmpLast & + bPmtuLen & bPmtu & bStartAddr & bSecond & + bNotFull & bHasExtra & bHasRes & bIsFirst & bIsLast; + end if; + + ------------------------------------------------------------------- + -- Stage C : genPktMetaDataSGE + -- (calcPktMetaDataQ4SGE -> sgePktMetaDataOutQ + calcAddrChunkRespQ) + -- impl. cond: cpmdQValid='1' AND sgePktMetaDataOutQ not full + -- AND calcAddrChunkRespQ not full + ------------------------------------------------------------------- + if (cpmdQValid = '1' and sgeQFull = '0' and cacrQFull = '0') then + cAddOne := cpmdQDout(214 downto 213); + cTruncPN := cpmdQDout(212 downto 188); + cLenLow := cpmdQDout(187 downto 175); + cMaxFirst := cpmdQDout(174 downto 162); + cTmpLast := cpmdQDout(161 downto 149); + cPmtuLen := cpmdQDout(148 downto 136); + cPmtu := cpmdQDout(135 downto 133); + cStartAddr := cpmdQDout(132 downto 69); + cNextAddr := cpmdQDout(68 downto 5); + cNotFull := cpmdQDout(4); + cHasExtra := cpmdQDout(3); + cHasRes := cpmdQDout(2); + cOrigFirst := cpmdQDout(1); + cOrigLast := cpmdQDout(0); + + cTotalPN := slv(unsigned(cTruncPN) + resize(unsigned(cAddOne), 25)); + + if (cNotFull = '1' and cHasExtra = '0') then + cFirst := cLenLow; + else + cFirst := cMaxFirst; + end if; + + if (cHasRes = '1') then + cLast := cTmpLast; + elsif (cNotFull = '1') then + cLast := cLenLow; + else + cLast := cPmtuLen; + end if; + + cpmdQRdEn <= '1'; -- calcPktMetaDataQ4SGE.deq + -- PktMetaDataSGE = firstPktLen & lastPktLen & sgePktNum & pmtu + sgeQWrEn <= '1'; + sgeQDin <= cFirst & cLast & cTotalPN & cPmtu; + -- TmpChunkRespData + cacrQWrEn <= '1'; + cacrQDin <= cTotalPN & cFirst & cPmtuLen & cLast & cPmtu & + cStartAddr & cNextAddr & cOrigFirst & cOrigLast; + end if; + + ------------------------------------------------------------------- + -- Stage D : genResp (calcAddrChunkRespQ -> respQ) — the real FSM + -- impl. cond: cacrQValid='1' AND respQ not full + -- Mealy: chunkAddr/chunkLen/isFirst read the CURRENT (pre-update) r. + ------------------------------------------------------------------- + if (cacrQValid = '1' and respQFull = '0') then + dSgePktNum := cacrQDout(196 downto 172); + dFirst := cacrQDout(171 downto 159); + dPmtuLen := cacrQDout(158 downto 146); + dLast := cacrQDout(145 downto 133); + -- pmtu (132:130) unused: addr increment uses precomputed pmtuLen + dStartAddr := cacrQDout(129 downto 66); + dNextAddr := cacrQDout(65 downto 2); + dOrigFirst := cacrQDout(1); + dOrigLast := cacrQDout(0); + + -- next-chunk address & remaining-count candidates + if (r.state = NEWCHUNK_S) then + dNextChunk := dNextAddr; -- precomputed 2nd-chunk addr + dRemaining := dSgePktNum; + else + -- addrAddPsnMultiplyPMTU(nextChunkAddrReg,1,pmtu) = +pmtuLen + dNextChunk := slv(unsigned(r.nextChunkAddrReg) + resize(unsigned(dPmtuLen), 64)); + dRemaining := r.remainingPktNumReg; + end if; + + if (unsigned(dRemaining) = 1) then dIsLast := '1'; else dIsLast := '0'; end if; + + -- response fields read the PRE-update register values (Mealy on r) + if (r.state = NEWCHUNK_S) then + dIsFirst := '1'; + dChunkAddr := dStartAddr; + dChunkLen := dFirst; + else + dIsFirst := '0'; + dChunkAddr := r.nextChunkAddrReg; + if (dIsLast = '1') then + dChunkLen := dLast; + else + dChunkLen := dPmtuLen; + end if; + end if; + + -- AddrChunkResp = chunkAddr & chunkLen & isFirst & isLast & isOrigFirst & isOrigLast + respQWrEn <= '1'; + respQDin <= dChunkAddr & dChunkLen & dIsFirst & dIsLast & dOrigFirst & dOrigLast; + + -- register / FIFO updates + if (dIsLast = '1') then + cacrQRdEn <= '1'; -- deq (done with entry) + else + v.remainingPktNumReg := slv(unsigned(dRemaining) - 1); + end if; + v.nextChunkAddrReg := dNextChunk; + if (dIsLast = '1') then + v.state := NEWCHUNK_S; -- isFirstChunkReg <= True + else + v.state := CONTCHUNK_S; -- isFirstChunkReg <= False + end if; + end if; + end if; + + -- Synchronous reset (overrides FSM; matches BSV mkReg(True) for state) + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + --------------------------------------------------------------------------- + -- Simulation-only assertion (no synthesizable effect): addrChunkReq.len /= 0 + -- (BSV immAssert in recvReq, fsm.md §recvReq; cf. OQ-FSM-DS2H-04 treatment). + --------------------------------------------------------------------------- + -- pragma translate_off + chk : process (clk) is + begin + if rising_edge(clk) then + if (rst = '0' and clearAllI = '0' and reqQValid = '1' and ccmdQFull = '0') then + assert unsigned(reqQDout(36 downto 5)) /= 0 + report "AddrChunkSrvGen: addrChunkReq.len must not be zero" + severity error; + end if; + end if; + end process chk; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd b/ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd new file mode 100644 index 0000000000..7f3b4f7aa0 --- /dev/null +++ b/ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd @@ -0,0 +1,746 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Re-segments an SGL's merged payload DataStream into PMTU-sized packets: it +-- left-shifts each packet's fragments to absorb the trailing invalid bytes of +-- the first packet's last fragment, and re-flags isFirst/isLast on packet +-- boundaries so every adjusted packet is a contiguous DataStream run. +-- +-- Structural twin of MergePayloadEachSge (same file): a 3-state stateReg +-- control FSM between a stateless input-side producer (handleMetaDataEachSGL, +-- fills U_SglAdjustedPktMetaDataQ) and a stateless output-side consumer +-- (shiftPayloadFrag, drains U_PayloadFragShiftQ -> U_PktPayloadOutQ). All +-- conventions resolved there are reused here. +-- +-- Two upstream PipeOut arguments are consumed (NOT FIFOs instantiated here): +-- adjustedTotalPayloadMetaDataPipeIn : PipeOut#(AdjustedTotalPayloadMetaData) +-- (61-bit meta word) +-- sglAllPayloadPipeIn : PipeOut#(DataStream) (290-bit flit) +-- One output PipeOut#(DataStream) is returned (read side of U_PktPayloadOutQ). +-- +-- SIX rules (fsm.md §transition table): +-- resetAndClear (guard clearAllI) — flush all 3 FIFOs, force INIT_S. +-- handleMetaDataEachSGL — state-independent producer for +-- U_SglAdjustedPktMetaDataQ. +-- adjustPayloadInit / adjustFirstOrMidPkt / adjustLastOrOnlyPkt — +-- the 3-state stateReg FSM; producer for +-- U_PayloadFragShiftQ. +-- shiftPayloadFrag — state-independent consumer of +-- U_PayloadFragShiftQ, producer for +-- U_PktPayloadOutQ. +-- The two state-independent rules can fire on the same cycle as whichever +-- state-dependent rule is active (disjoint FIFOs / registers, opposite ends). +-- +-- Mapping note (OQ-FSM-APS-01): mapping.json / modules.json `owns.state` lists +-- non-existent regs (shiftAmtReg/firstFragLenReg/lastFragLenReg) and omits +-- the 11 real mkRegU context regs; `new_ports:[]` omits the used clearAll +-- constructor parameter; SURF widths use the stale DataStream=321. This file +-- follows AdjustPayloadSegment.fsm.md, which is authoritative. +-- +-- Width / packing resolutions applied: +-- - DataStream width = 290 bits (OQ-FSM-H2DS-02 / APS-02 RESOLVED) +-- - all struct/tuple packing first-field-at-MSB +-- (OQ-FSM-H2DS-04 / APS-02 RESOLVED) +-- +-- Atomicity / stall: every adjust* rule's payloadFragShiftQ.enq is +-- unconditional in BSV, so the WHOLE rule — including the stateReg transition +-- — fails to fire when fragShiftQFull='1'. Modelled by gating EVERY register +-- update of those rules on fragShiftQFull='0' (the `fire` variable), not just +-- the FIFO write-enable. The non-prePayloadFragReg.isLast branches +-- additionally require sglAllPayloadPipeInValid='1' (they deq the payload +-- pipe). Same shape as MergePayloadEachSge (OQ-FSM-MPES-03). +-- +-- FIFO clear (OQ-FSM-01 RESOLVED): surf.Fifo has no clear port; BSV +-- FIFOF.clear is modelled by asserting the synchronous rst. All three FIFOs +-- share fifoRst = rst OR clearAllI. +-- +-- Bit layouts (BSV deriving(Bits), first-field-at-MSB): +-- DataStream (290): [289:34] data[255:0] | [33:2] byteEn[31:0] | +-- [1] isFirst | [0] isLast +-- AdjustedTotalPayloadMetaData (61): +-- [60:48] firstPktLen[12:0] | [47:40] firstPktFragNum[7:0] | +-- [39:34] firstPktLastFragValidByteNum[5:0] | +-- [33:28] origLastFragValidByteNum[5:0] | [27:3] adjustedPktNum[24:0] | +-- [2:0] pmtu[2:0] +-- sglAdjustedPktMetaDataQ Tuple8 (54): +-- [53:51] pmtu[2:0] | [50:43] firstPktFragNum[7:0] | +-- [42:18] adjustedPktNum[24:0] | +-- [17:12] firstPktLastFragValidByteNum[5:0] | +-- [11:3] firstPktLastFragValidBitNum[8:0] | [2] sglHasOnlyPkt | +-- [1] hasExtraFrag | [0] noShiftFrag +-- payloadFragShiftQ Tuple6 (628): +-- [627:338] prePayloadFrag (DataStream) | [337:48] curPayloadFrag | +-- [47:42] leftShiftValidByteNum[5:0] | [41:33] leftShiftValidBitNum[8:0] | +-- [32] shouldChangeByteEn | [31:0] firstPktLastFragByteEn[31:0] +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_PktPayloadOutQ : surf.Fifo DATA_WIDTH_G=290 (output, exposed) +-- U_SglAdjustedPktMetaDataQ : surf.Fifo DATA_WIDTH_G=54 (internal pipeline) +-- U_PayloadFragShiftQ : surf.Fifo DATA_WIDTH_G=628 (internal pipeline) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity AdjustPayloadSegment is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (BSV constructor parameter clearAll : Bool) + clearAllI : in sl; + -- Upstream: AdjustedTotalPayloadMetaData pipe (adjustedTotalPayloadMetaDataPipeIn) + adjustedMetaPipeInValid : in sl; -- .notEmpty + adjustedMetaPipeInData : in slv(60 downto 0); -- .first + adjustedMetaPipeInRdEn : out sl; -- .deq + -- Upstream: DataStream payload pipe (sglAllPayloadPipeIn argument) + sglAllPayloadPipeInValid : in sl; -- .notEmpty + sglAllPayloadPipeInData : in slv(289 downto 0); -- .first + sglAllPayloadPipeInRdEn : out sl; -- .deq + -- Downstream: returned PipeOut#(DataStream) (read side of U_PktPayloadOutQ) + pktPayloadOutValid : out sl; -- PipeOut.notEmpty + pktPayloadOutData : out slv(289 downto 0); -- PipeOut.first + pktPayloadOutRdEn : in sl); -- PipeOut.deq +end entity AdjustPayloadSegment; + +architecture rtl of AdjustPayloadSegment is + + -- Maps BSV AdjustPayloadSegmentState: + -- ADJUST_PAYLOAD_SEGMENT_INIT -> INIT_S + -- ADJUST_PAYLOAD_SEGMENT_FIRST_OR_MID_PKT -> FIRST_OR_MID_PKT_S + -- ADJUST_PAYLOAD_SEGMENT_LAST_OR_ONLY_PKT -> LAST_OR_ONLY_PKT_S + type StateType is (INIT_S, FIRST_OR_MID_PKT_S, LAST_OR_ONLY_PKT_S); + + type RegType is record + state : StateType; -- mkReg(ADJUST_PAYLOAD_SEGMENT_INIT) + prePayloadFrag : slv(289 downto 0); -- mkRegU (DataStream) + firstPktLastFragByteEn : slv(31 downto 0); -- mkRegU (ByteEn) + firstPktLastFragValidByteNum : slv(5 downto 0); -- mkRegU (ByteEnBitNum) + firstPktLastFragValidBitNum : slv(8 downto 0); -- mkRegU (BusBitNum) + isFirstPkt : sl; -- mkRegU + hasExtraFrag : sl; -- mkRegU + sglHasOnlyPkt : sl; -- mkRegU + noShiftFrag : sl; -- mkRegU + pmtuFragNum : slv(7 downto 0); -- mkRegU (PktFragNum) + pktRemainingFragNum : slv(7 downto 0); -- mkRegU (PktFragNum) + sglRemainingPktNum : slv(24 downto 0); -- mkRegU (PktNum) + end record RegType; + + -- All mkRegU fields set to '0' in REG_INIT_C: each is written by prepareNextSGL + -- (the only path out of INIT_S) before any state-dependent read, so the reset + -- value is don't-care (no correctness risk). + constant REG_INIT_C : RegType := ( + state => INIT_S, + prePayloadFrag => (others => '0'), + firstPktLastFragByteEn => (others => '0'), + firstPktLastFragValidByteNum => (others => '0'), + firstPktLastFragValidBitNum => (others => '0'), + isFirstPkt => '0', + hasExtraFrag => '0', + sglHasOnlyPkt => '0', + noShiftFrag => '0', + pmtuFragNum => (others => '0'), + pktRemainingFragNum => (others => '0'), + sglRemainingPktNum => (others => '0')); + + constant DATA_BUS_BYTE_WIDTH_C : natural := 32; -- DATA_BUS_BYTE_WIDTH + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Shared synchronous clear for all three FIFOs (rst OR clearAllI) + signal fifoRst : sl; + + -- U_SglAdjustedPktMetaDataQ control / status (internal pipeline FIFO) + signal sglMetaQWrEn : sl; + signal sglMetaQDin : slv(53 downto 0); + signal sglMetaQRdEn : sl; + signal sglMetaQDout : slv(53 downto 0); + signal sglMetaQValid : sl; + signal sglMetaQFull : sl; + + -- U_PayloadFragShiftQ control / status (internal pipeline FIFO) + signal fragShiftQWrEn : sl; + signal fragShiftQDin : slv(627 downto 0); + signal fragShiftQRdEn : sl; + signal fragShiftQDout : slv(627 downto 0); + signal fragShiftQValid : sl; + signal fragShiftQFull : sl; + + -- U_PktPayloadOutQ control / status (output queue; read side exposed) + signal pktPayloadOutQWrEn : sl; + signal pktPayloadOutQDin : slv(289 downto 0); + signal pktPayloadOutQFull : sl; + + -- genByteEn(n) (Utils.bsv:161): reverseBits((1< left-aligned mask with + -- the top n byteEn bits set. Identical to shifting an all-ones word left by + -- (32-n) (top n bits survive; n=0 -> 0, n=32 -> all ones). + function genByteEn (n : slv(5 downto 0)) return slv is + variable ones : slv(31 downto 0); + variable shiftAmt : natural; + begin + ones := (others => '1'); + shiftAmt := DATA_BUS_BYTE_WIDTH_C - to_integer(unsigned(n)); + return std_logic_vector(shift_left(unsigned(ones), shiftAmt)); + end function genByteEn; + + -- calcFragNumByPMTU(pmtu) (Utils.bsv:268): 1 << (getPmtuLogValue(pmtu) - + -- log2(DATA_BUS_BYTE_WIDTH=32)=5). PMTU enum 256/512/1024/2048/4096 -> + -- fragments/packet 8/16/32/64/128. + function calcFragNumByPMTU (pmtu : slv(2 downto 0)) return slv is + variable res : slv(7 downto 0); + begin + case pmtu is + when "001" => res := std_logic_vector(to_unsigned(8, 8)); -- IBV_MTU_256 + when "010" => res := std_logic_vector(to_unsigned(16, 8)); -- IBV_MTU_512 + when "011" => res := std_logic_vector(to_unsigned(32, 8)); -- IBV_MTU_1024 + when "100" => res := std_logic_vector(to_unsigned(64, 8)); -- IBV_MTU_2048 + when others => res := std_logic_vector(to_unsigned(128, 8)); -- IBV_MTU_4096 ("101") + end case; + return res; + end function calcFragNumByPMTU; + + -- prepareNextSGL (PayloadGen.bsv:1668): pops sglAdjustedPktMetaDataQ + the + -- payload pipe and sets up the per-SGL context registers + next stateReg. + -- Returns the next prePayloadFrag value through retFrag (the BSV function's + -- ActionValue result); the caller writes prePayloadFragReg, mirroring the BSV + -- (it does NOT write that register itself). The pops (deq) are asserted by the + -- caller, not here. + procedure prepareNextSGL ( + variable v : inout RegType; + signal metaQDout : in slv(53 downto 0); + signal payloadData : in slv(289 downto 0); + variable retFrag : out slv(289 downto 0)) is + variable pmtuV : slv(2 downto 0); + variable firstFragN : slv(7 downto 0); + variable pktNumV : slv(24 downto 0); + variable validByteN : slv(5 downto 0); + variable validBitN : slv(8 downto 0); + variable hasOnlyV : sl; + variable hasExtraV : sl; + variable noShiftV : sl; + begin + pmtuV := metaQDout(53 downto 51); + firstFragN := metaQDout(50 downto 43); + pktNumV := metaQDout(42 downto 18); + validByteN := metaQDout(17 downto 12); + validBitN := metaQDout(11 downto 3); + hasOnlyV := metaQDout(2); + hasExtraV := metaQDout(1); + noShiftV := metaQDout(0); + + v.pmtuFragNum := calcFragNumByPMTU(pmtuV); + v.pktRemainingFragNum := firstFragN; + v.sglRemainingPktNum := pktNumV; + v.firstPktLastFragValidByteNum := validByteN; + v.firstPktLastFragValidBitNum := validBitN; + v.firstPktLastFragByteEn := genByteEn(validByteN); + v.isFirstPkt := '1'; + v.hasExtraFrag := hasExtraV; + v.sglHasOnlyPkt := hasOnlyV; + v.noShiftFrag := noShiftV; + + if hasOnlyV = '1' then + v.state := LAST_OR_ONLY_PKT_S; + else + v.state := FIRST_OR_MID_PKT_S; + end if; + + retFrag := payloadData; -- curPayloadFrag (unmodified) + end procedure prepareNextSGL; + +begin + + -- FIFO reset: level-sensitive synchronous clear (OQ-FSM-01 RESOLVED). + -- resetAndClear calls .clear on all three FIFOs while clearAllI='1'. + fifoRst <= rst or clearAllI; + + --------------------------------------------------------------------------- + -- U_SglAdjustedPktMetaDataQ : surf.Fifo + -- Internal pipeline FIFO; produced by handleMetaDataEachSGL, consumed by + -- prepareNextSGL. DATA_WIDTH_G=54, FWFT, sync, distributed RAM. + --------------------------------------------------------------------------- + U_SglAdjustedPktMetaDataQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 54, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => sglMetaQWrEn, + din => sglMetaQDin, + full => sglMetaQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => sglMetaQRdEn, + dout => sglMetaQDout, + valid => sglMetaQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_PayloadFragShiftQ : surf.Fifo + -- Internal pipeline FIFO; produced by adjustFirstOrMidPkt / + -- adjustLastOrOnlyPkt, consumed by shiftPayloadFrag. + -- DATA_WIDTH_G=628, FWFT, sync, block RAM (wide word). + --------------------------------------------------------------------------- + U_PayloadFragShiftQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 628, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => fragShiftQWrEn, + din => fragShiftQDin, + full => fragShiftQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => fragShiftQRdEn, + dout => fragShiftQDout, + valid => fragShiftQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_PktPayloadOutQ : surf.Fifo + -- Output queue; its read side IS the returned PipeOut#(DataStream). + -- Produced by shiftPayloadFrag. DATA_WIDTH_G=290, FWFT, sync, block RAM. + --------------------------------------------------------------------------- + U_PktPayloadOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 290, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pktPayloadOutQWrEn, + din => pktPayloadOutQDin, + full => pktPayloadOutQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pktPayloadOutRdEn, + dout => pktPayloadOutData, + valid => pktPayloadOutValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, clearAllI, + adjustedMetaPipeInValid, adjustedMetaPipeInData, + sglAllPayloadPipeInValid, sglAllPayloadPipeInData, + sglMetaQValid, sglMetaQDout, sglMetaQFull, + fragShiftQValid, fragShiftQDout, fragShiftQFull, + pktPayloadOutQFull) is + variable v : RegType; + + -- handleMetaDataEachSGL locals + variable mFirstPktFragNum : slv(7 downto 0); + variable mValidByteNum : slv(5 downto 0); + variable mOrigValidByteNum : slv(5 downto 0); + variable mPktNum : slv(24 downto 0); + variable mPmtu : slv(2 downto 0); + variable mValidBitNum : slv(8 downto 0); + variable mHasOnly : sl; + variable mHasExtra : sl; + variable mNoShift : sl; + + -- main-FSM locals + variable preIsLast : sl; + variable isAdjLastFrag : sl; + variable isFirstPktAdjLast : sl; + variable shouldShift : sl; + variable shouldChgByteEn : sl; + variable isLastFrag : sl; + variable fire : sl; + variable curFrag : slv(289 downto 0); + variable nextFrag : slv(289 downto 0); + variable preFragWLast : slv(289 downto 0); + variable retFrag : slv(289 downto 0); + variable lsByteNum : slv(5 downto 0); + variable lsBitNum : slv(8 downto 0); + + -- shiftPayloadFrag (leftShiftAndMergeFragData) locals + variable sPreData : slv(255 downto 0); + variable sCurData : slv(255 downto 0); + variable sPreByteEn : slv(31 downto 0); + variable sCurByteEn : slv(31 downto 0); + variable sShByteNum : slv(4 downto 0); -- truncate(6->5) ShiftByteNum + variable sShBitNum : slv(7 downto 0); -- truncate(9->8) ShiftBitNum + variable byteEnCat : slv(63 downto 0); + variable dataCat : slv(511 downto 0); + variable shByteEn : slv(63 downto 0); + variable shData : slv(511 downto 0); + variable outFrag : slv(289 downto 0); + begin + v := r; + + -- default Mealy outputs (deasserted; overridden below per transition) + adjustedMetaPipeInRdEn <= '0'; + sglAllPayloadPipeInRdEn <= '0'; + sglMetaQWrEn <= '0'; + sglMetaQDin <= (others => '0'); + sglMetaQRdEn <= '0'; + fragShiftQWrEn <= '0'; + fragShiftQDin <= (others => '0'); + fragShiftQRdEn <= '0'; + pktPayloadOutQWrEn <= '0'; + pktPayloadOutQDin <= (others => '0'); + + if clearAllI = '1' then + -- resetAndClear: FIFOs flushed via fifoRst; stateReg forced to INIT_S. + -- The 11 mkRegU context registers are deliberately untouched (matches + -- BSV; rewritten by the next prepareNextSGL before any read). + v.state := INIT_S; + + else + + ------------------------------------------------------------------- + -- handleMetaDataEachSGL (state-independent producer) + -- guard: adjustedMetaPipeInValid='1' AND sglMetaQFull='0' + ------------------------------------------------------------------- + if adjustedMetaPipeInValid = '1' and sglMetaQFull = '0' then + -- AdjustedTotalPayloadMetaData slice (firstPktLen[60:48] unused) + mFirstPktFragNum := adjustedMetaPipeInData(47 downto 40); + mValidByteNum := adjustedMetaPipeInData(39 downto 34); + mOrigValidByteNum := adjustedMetaPipeInData(33 downto 28); + mPktNum := adjustedMetaPipeInData(27 downto 3); + mPmtu := adjustedMetaPipeInData(2 downto 0); + + -- calcFragBitNumAndByteNum: validBitNum = zeroExtend(validByteNum)<<3 + mValidBitNum := mValidByteNum & "000"; + + mHasOnly := ite(unsigned(mPktNum) = 1, '1', '0'); -- isOneR(adjustedPktNum) + mHasExtra := ite(unsigned(mValidByteNum) < unsigned(mOrigValidByteNum), '1', '0'); + mNoShift := ite(unsigned(mValidByteNum) = DATA_BUS_BYTE_WIDTH_C, '1', '0'); + + adjustedMetaPipeInRdEn <= '1'; + sglMetaQWrEn <= '1'; + sglMetaQDin <= mPmtu -- [53:51] + & mFirstPktFragNum -- [50:43] + & mPktNum -- [42:18] + & mValidByteNum -- [17:12] + & mValidBitNum -- [11:3] + & mHasOnly -- [2] + & mHasExtra -- [1] + & mNoShift; -- [0] + end if; + + ------------------------------------------------------------------- + -- Main 3-state FSM (adjustPayloadInit / adjustFirstOrMidPkt / + -- adjustLastOrOnlyPkt). All register reads below + -- are OLD (r) values (BSV rule semantics). + ------------------------------------------------------------------- + case r.state is + + -- ============================================================ + -- INIT_S: adjustPayloadInit + -- implicit cond: sglMetaQValid='1' AND sglAllPayloadPipeInValid='1' + -- ============================================================ + when INIT_S => + if sglMetaQValid = '1' and sglAllPayloadPipeInValid = '1' then + sglMetaQRdEn <= '1'; + sglAllPayloadPipeInRdEn <= '1'; + prepareNextSGL(v, sglMetaQDout, sglAllPayloadPipeInData, retFrag); + v.prePayloadFrag := retFrag; + end if; + + -- ============================================================ + -- FIRST_OR_MID_PKT_S: adjustFirstOrMidPkt + -- Whole rule gated on fragShiftQFull='0'; when prePayloadFrag.isLast + -- ='0' the payload pipe is also read/deq'd (needs Valid='1'). + -- ============================================================ + when FIRST_OR_MID_PKT_S => + preIsLast := r.prePayloadFrag(0); + isAdjLastFrag := ite(unsigned(r.pktRemainingFragNum) = 1, '1', '0'); -- isOneR + shouldShift := not (r.isFirstPkt or r.noShiftFrag); + curFrag := (others => '0'); -- genEmptyDataStream + shouldChgByteEn := '0'; + + fire := '0'; + if fragShiftQFull = '0' then + if preIsLast = '1' then + fire := '1'; + elsif sglAllPayloadPipeInValid = '1' then + fire := '1'; + end if; + end if; + + if fire = '1' then + if preIsLast = '0' then + curFrag := sglAllPayloadPipeInData; + isFirstPktAdjLast := r.isFirstPkt and isAdjLastFrag; + if (r.noShiftFrag = '1') or (isFirstPktAdjLast = '0') then + sglAllPayloadPipeInRdEn <= '1'; + nextFrag := curFrag; + else + -- last frag of first packet: keep it in prePayloadFragReg, + -- do NOT deq (queue head is next packet's first fragment) + nextFrag := r.prePayloadFrag; + end if; + -- nextPayloadFrag.isFirst := isAdjustedLastFrag (bit 1) + nextFrag := nextFrag(289 downto 2) & isAdjLastFrag & nextFrag(0); + v.prePayloadFrag := nextFrag; + end if; + + if isAdjLastFrag = '1' then + if r.isFirstPkt = '1' then + shouldChgByteEn := '1'; + v.isFirstPkt := '0'; + end if; + v.sglRemainingPktNum := std_logic_vector(unsigned(r.sglRemainingPktNum) - 1); + if unsigned(r.sglRemainingPktNum) = 2 then -- isTwoR + v.state := LAST_OR_ONLY_PKT_S; + else + v.pktRemainingFragNum := r.pmtuFragNum; + v.state := FIRST_OR_MID_PKT_S; + end if; + else + v.pktRemainingFragNum := std_logic_vector(unsigned(r.pktRemainingFragNum) - 1); + end if; + + -- payloadFragShiftQ.enq (first elem = OLD prePayloadFrag with + -- isLast := isAdjustedLastFrag; leftShift gated by shouldShift) + preFragWLast := r.prePayloadFrag(289 downto 1) & isAdjLastFrag; + if shouldShift = '1' then + lsByteNum := r.firstPktLastFragValidByteNum; + lsBitNum := r.firstPktLastFragValidBitNum; + else + lsByteNum := (others => '0'); + lsBitNum := (others => '0'); + end if; + fragShiftQWrEn <= '1'; + fragShiftQDin <= preFragWLast -- [627:338] + & curFrag -- [337:48] + & lsByteNum -- [47:42] + & lsBitNum -- [41:33] + & shouldChgByteEn -- [32] + & r.firstPktLastFragByteEn; -- [31:0] + end if; + + -- ============================================================ + -- LAST_OR_ONLY_PKT_S: adjustLastOrOnlyPkt + -- Whole rule gated on fragShiftQFull='0'. Branch on OLD + -- prePayloadFrag.isLast; the not-last branch deqs the payload pipe. + -- ============================================================ + when LAST_OR_ONLY_PKT_S => + preIsLast := r.prePayloadFrag(0); + shouldShift := not (r.sglHasOnlyPkt or r.noShiftFrag); + isLastFrag := preIsLast; -- = prePayloadFragReg.isLast + nextFrag := (others => '0'); -- genEmptyDataStream + shouldChgByteEn := '0'; + + fire := '0'; + if fragShiftQFull = '0' then + if preIsLast = '1' then + fire := '1'; + elsif sglAllPayloadPipeInValid = '1' then + fire := '1'; + end if; + end if; + + if fire = '1' then + if preIsLast = '1' then + if sglMetaQValid = '1' and sglAllPayloadPipeInValid = '1' then + -- start the next SGL + sglMetaQRdEn <= '1'; + sglAllPayloadPipeInRdEn <= '1'; + prepareNextSGL(v, sglMetaQDout, sglAllPayloadPipeInData, retFrag); + nextFrag := retFrag; + else + -- no next SGL yet -> wait in INIT_S (empty frag) + v.state := INIT_S; + end if; + else + sglAllPayloadPipeInRdEn <= '1'; + -- nextPayloadFrag = payload, isFirst forced 0 (bit 1) + nextFrag := sglAllPayloadPipeInData(289 downto 2) & '0' & sglAllPayloadPipeInData(0); + if (shouldShift = '1') and (r.hasExtraFrag = '0') and (nextFrag(0) = '1') then + -- no extra fragment -> finish this SGL + v.state := INIT_S; + isLastFrag := '1'; + end if; + end if; + + v.prePayloadFrag := nextFrag; + + -- payloadFragShiftQ.enq (first elem = OLD prePayloadFrag with + -- isLast := isLastFrag; shouldChangeByteEn=0, byteEn override + -- = dontCare (0) since shouldChangeByteEn is False) + preFragWLast := r.prePayloadFrag(289 downto 1) & isLastFrag; + if shouldShift = '1' then + lsByteNum := r.firstPktLastFragValidByteNum; + lsBitNum := r.firstPktLastFragValidBitNum; + else + lsByteNum := (others => '0'); + lsBitNum := (others => '0'); + end if; + fragShiftQWrEn <= '1'; + fragShiftQDin <= preFragWLast -- [627:338] + & nextFrag -- [337:48] + & lsByteNum -- [47:42] + & lsBitNum -- [41:33] + & '0' -- [32] shouldChangeByteEn + & x"00000000"; -- [31:0] invalidByteEn (dontCare) + end if; + + end case; + + ------------------------------------------------------------------- + -- shiftPayloadFrag (state-independent consumer) + -- guard: fragShiftQValid='1' AND pktPayloadOutQFull='0' + -- outPayloadFrag = leftShiftAndMergeFragData(pre, cur, + -- truncate(lsByteNum 6->5), truncate(lsBitNum 9->8)) + ------------------------------------------------------------------- + if fragShiftQValid = '1' and pktPayloadOutQFull = '0' then + -- Slice the 628-bit element + sPreData := fragShiftQDout(627 downto 372); -- prePayloadFrag.data + sPreByteEn := fragShiftQDout(371 downto 340); -- prePayloadFrag.byteEn + sCurData := fragShiftQDout(337 downto 82); -- curPayloadFrag.data + sCurByteEn := fragShiftQDout( 81 downto 50); -- curPayloadFrag.byteEn + sShByteNum := fragShiftQDout( 46 downto 42); -- truncate(leftShiftValidByteNum 6->5) + sShBitNum := fragShiftQDout( 40 downto 33); -- truncate(leftShiftValidBitNum 9->8) + + -- byteEn: truncateLSB({pre,cur} << shByteNum) -> top 32 of 64 + byteEnCat := sPreByteEn & sCurByteEn; + shByteEn := std_logic_vector(shift_left(unsigned(byteEnCat), to_integer(unsigned(sShByteNum)))); + -- data: truncateLSB({pre,cur} << shBitNum) -> top 256 of 512 + dataCat := sPreData & sCurData; + shData := std_logic_vector(shift_left(unsigned(dataCat), to_integer(unsigned(sShBitNum)))); + + -- isFirst/isLast kept from preFrag + outFrag := shData(511 downto 256) -- data [289:34] + & shByteEn(63 downto 32) -- byteEn [33:2] + & fragShiftQDout(339) -- isFirst (prePayloadFrag.isFirst) + & fragShiftQDout(338); -- isLast (prePayloadFrag.isLast) + + -- if shouldChangeByteEn: override byteEn with firstPktLastFragByteEn + if fragShiftQDout(32) = '1' then + outFrag := outFrag(289 downto 34) -- keep data + & fragShiftQDout(31 downto 0) -- byteEn := firstPktLastFragByteEn + & outFrag(1 downto 0); -- keep isFirst/isLast + end if; + + fragShiftQRdEn <= '1'; + pktPayloadOutQWrEn <= '1'; + pktPayloadOutQDin <= outFrag; + end if; + + end if; + + -- Synchronous reset (stateReg = mkReg(ADJUST_PAYLOAD_SEGMENT_INIT)) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + --------------------------------------------------------------------------- + -- Simulation-only assertions (sim-only immAssert calls, no synth effect): + -- adjustFirstOrMidPkt: when prePayloadFragReg.isLast, pktRemainingFragNum=1 + -- and sglRemainingPktNum=2. + -- adjustLastOrOnlyPkt: sglRemainingPktNum=1 whenever the rule fires. + -- shiftPayloadFrag : NOT(MSB(leftShiftValidByteNum) AND MSB(leftShiftValidBitNum)). + --------------------------------------------------------------------------- + -- pragma translate_off + check : process (clk) is + begin + if rising_edge(clk) then + if rst = '0' and clearAllI = '0' then + if (r.state = FIRST_OR_MID_PKT_S and r.prePayloadFrag(0) = '1' + and fragShiftQFull = '0') then + assert (unsigned(r.pktRemainingFragNum) = 1) + and (unsigned(r.sglRemainingPktNum) = 2) + report "AdjustPayloadSegment: pktRemainingFragNum must be 1 and " + & "sglRemainingPktNum must be 2 when prePayloadFrag.isLast in " + & "FIRST_OR_MID_PKT_S" + severity error; + end if; + if (r.state = LAST_OR_ONLY_PKT_S and fragShiftQFull = '0' + and (r.prePayloadFrag(0) = '1' or sglAllPayloadPipeInValid = '1')) then + assert unsigned(r.sglRemainingPktNum) = 1 + report "AdjustPayloadSegment: sglRemainingPktNum must be 1 in " + & "LAST_OR_ONLY_PKT_S" + severity error; + end if; + if (fragShiftQValid = '1' and pktPayloadOutQFull = '0') then + assert not (fragShiftQDout(47) = '1' and fragShiftQDout(41) = '1') + report "AdjustPayloadSegment: leftShiftValidByteNum/BitNum MSBs " + & "must not both be 1 (truncate 6->5 / 9->8 would lose a bit)" + severity error; + end if; + end if; + end if; + end process check; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/AtomicSrvConAndGen.vhd b/ethernet/RoCEv2/rtl/AtomicSrvConAndGen.vhd new file mode 100644 index 0000000000..3173c52fcd --- /dev/null +++ b/ethernet/RoCEv2/rtl/AtomicSrvConAndGen.vhd @@ -0,0 +1,242 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Implements BSV interface Server#(AtomicOpReq, AtomicOpResp) as a pair of +-- surf.Fifo instances with a single combinational transform between them +-- (BSV rule genResp). There is NO state register and NO RegType: mkAtomicSrv +-- declares no mkReg/mkRegU/mkCReg — its only state-holding elements are the two +-- FIFOs (atomicOpReqQ, atomicOpRespQ), which are SURF instances. The single +-- rule genResp has no explicit guard; it fires purely on the FIFO implicit +-- conditions (reqQ.notEmpty AND respQ.notFull). This entity is therefore a +-- structural wrapper + combinational glue (Mealy) — no two-process FSM, no +-- RegType (the only registered storage lives inside the two U_*Q FIFOs). +-- +-- cntrlStatus (OQ-FSM-ASCAG-01, non-blocking): mkAtomicSrv takes a CntrlStatus +-- constructor argument but NEVER references it (no resetAndClear rule, no +-- guard) — unlike every sibling *ConAndGen module in this file. It therefore +-- contributes NO port (mapping.json new_ports: [] is correct). The FIFOs reset +-- only via their structural rst tied to the global synchronous reset. +-- +-- !!! STUB — atomic operation is UNIMPLEMENTED (RQ-06 / OQ-FSM-ASCAG-02) !!! +-- --------------------------------------------------------------------------- +-- genResp does NOT compute a real compare-and-swap / fetch-and-add. Per the +-- BSV source comment (PayloadConAndGen.bsv:1213, "// TODO: add atomic support") +-- the rule simply ECHOES the request's own compData back as `original`: +-- +-- AtomicOpResp { initiator: req.initiator, +-- original : req.compData, -- <- STUB: should be the +-- -- pre-CAS/FA value READ +-- -- FROM MEMORY, not compData +-- sqpn : req.sqpn, +-- psn : req.psn } +-- +-- The request fields casOrFetchAdd, swapData and startAddr are present in the +-- packed request word but are NEVER referenced — confirming a genuine no-op +-- stub (no memory access of any kind occurs here). This is an INTENTIONAL, +-- RESOLVED decision (out/01-inventory/RESOLVED-round2.md RQ-06, +-- out/02-partition/RESOLVED-round4.md item 4): KEEP THE STUB IN VHDL. Do NOT +-- implement a real atomic op. This comment preserves the limitation for later +-- co-sim / hardware-correctness review. See OQ-FSM-ASCAG-02. +-- +-- Width / bit-layout trace (CLAUDE.md hard rule: trace widths, never invent) +-- -------------------------------------------------------------------------- +-- BSV deriving(Bits) packs the first field at the MSB (confirmed RESOLVED at +-- OQ-FSM-H2DS-04; project-wide convention). Field widths from DataTypes.bsv +-- 349-364, Headers.bsv 22-26: +-- DmaReqSrcType=4, ADDR=64, Long=64, QPN=24, PSN=24, Bool=1. +-- +-- AtomicOpReq = 245 bits (DataTypes.bsv:349-357): +-- | 244:241 initiator | 240 casOrFetchAdd | 239:176 startAddr | +-- | 175:112 compData | 111:48 swapData | 47:24 sqpn | 23:0 psn | +-- AtomicOpResp = 116 bits (DataTypes.bsv:359-364): +-- | 115:112 initiator | 111:48 original | 47:24 sqpn | 23:0 psn | +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_AtomicOpReqQ : surf.Fifo DATA_WIDTH_G=245 (BSV atomicOpReqQ <- mkFIFOF) +-- U_AtomicOpRespQ : surf.Fifo DATA_WIDTH_G=116 (BSV atomicOpRespQ <- mkFIFOF) +-- Both: sync, FWFT (matches BSV FIFOF.first fall-through), distributed RAM +-- (small control FIFOs), ADDR_WIDTH_G=4 (surf.Fifo minimum; BSV default depth +-- 2 maps to depth-16 — extra buffering only, functionally equivalent). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity AtomicSrvConAndGen is + generic ( + TPD_G : time := 1 ns; + -- Widths are fixed by the BSV struct layout (see header bit-layout trace); + -- the field slicing below assumes these exact values. + REQ_WIDTH_G : positive := 245; -- AtomicOpReq packed width + RESP_WIDTH_G : positive := 116); -- AtomicOpResp packed width + port ( + clk : in sl; + rst : in sl; -- active-high sync reset + -- Server.request.put(AtomicOpReq) — caller enqueues a request. + -- reqValid drives the request FIFO write enable; reqRdy = FIFO not-full. + reqValid : in sl; + reqData : in slv(REQ_WIDTH_G-1 downto 0); -- AtomicOpReq packed + reqRdy : out sl; -- = atomicOpReqQ.notFull + -- Server.response.get(AtomicOpResp) — caller dequeues a response. + -- respValid = FIFO not-empty; respRdy drives the response FIFO read enable. + respValid : out sl; -- = atomicOpRespQ.notEmpty + respData : out slv(RESP_WIDTH_G-1 downto 0); -- AtomicOpResp packed + respRdy : in sl); -- caller get() enable +end entity AtomicSrvConAndGen; + +architecture rtl of AtomicSrvConAndGen is + + -- AtomicOpReq field slices (first-field-at-MSB, OQ-FSM-H2DS-04 RESOLVED). + subtype INITIATOR_REQ_F is natural range 244 downto 241; + -- 240 casOrFetchAdd -- read but UNUSED (stub) + -- 239 downto 176 startAddr -- read but UNUSED (stub) + subtype COMPDATA_F is natural range 175 downto 112; + -- 111 downto 48 swapData -- read but UNUSED (stub) + subtype SQPN_REQ_F is natural range 47 downto 24; + subtype PSN_REQ_F is natural range 23 downto 0; + + -- U_AtomicOpReqQ interface signals (request FIFO, REQ_WIDTH_G bits) + signal reqQNotFull : sl; + signal reqQValid : sl; -- = atomicOpReqQ.notEmpty + signal reqQDout : slv(REQ_WIDTH_G-1 downto 0); + signal reqQRdEn : sl; -- atomicOpReqQ.deq + + -- U_AtomicOpRespQ interface signals (response FIFO, RESP_WIDTH_G bits) + signal respQNotFull : sl; + signal respQValid : sl; -- = atomicOpRespQ.notEmpty + signal respQDout : slv(RESP_WIDTH_G-1 downto 0); + signal respQWrEn : sl; -- atomicOpRespQ.enq + signal respQDin : slv(RESP_WIDTH_G-1 downto 0); + + -- genResp fire condition (Mealy): reqQ has a request AND respQ can accept. + signal genFire : sl; + +begin + + -- generic sanity: the field slicing is hardwired to these struct widths. + assert (REQ_WIDTH_G = 245 and RESP_WIDTH_G = 116) + report "AtomicSrvConAndGen: field slicing assumes REQ_WIDTH_G=245, " & + "RESP_WIDTH_G=116 (BSV AtomicOpReq/AtomicOpResp layout)." + severity failure; + + --------------------------------------------------------------------------- + -- request.put pass-through (NOT FSM-gated): the caller drives the request + -- FIFO write side directly; reqRdy reports the FIFO's not-full state. + --------------------------------------------------------------------------- + reqRdy <= reqQNotFull after TPD_G; + + --------------------------------------------------------------------------- + -- rule genResp (single rule; no explicit guard). Implicit conditions: + -- fire = atomicOpReqQ.notEmpty AND atomicOpRespQ.notFull + -- On firing it dequeues the request, enqueues the response, and (STUB) + -- echoes compData back as `original` — see header for the unimplemented + -- atomic-op warning (RQ-06 / OQ-FSM-ASCAG-02). + --------------------------------------------------------------------------- + genFire <= reqQValid and respQNotFull; + + reqQRdEn <= genFire after TPD_G; -- atomicOpReqQ.deq + respQWrEn <= genFire after TPD_G; -- atomicOpRespQ.enq + + -- AtomicOpResp packing (first-field-at-MSB): + -- { initiator(4) | original(64) | sqpn(24) | psn(24) } + -- STUB: original := compData (NOT a real CAS/FA result — see header). + respQDin <= reqQDout(INITIATOR_REQ_F) & + reqQDout(COMPDATA_F) & -- original <= compData (stub) + reqQDout(SQPN_REQ_F) & + reqQDout(PSN_REQ_F) after TPD_G; + + --------------------------------------------------------------------------- + -- response.get pass-through (NOT FSM-gated): the caller reads the response + -- FIFO front directly; respRdy drives the read enable. + --------------------------------------------------------------------------- + respValid <= respQValid after TPD_G; + respData <= respQDout after TPD_G; + + --------------------------------------------------------------------------- + -- U_AtomicOpReqQ : surf.Fifo + -- BSV: FIFOF#(AtomicOpReq) atomicOpReqQ <- mkFIFOF. Write side = caller's + -- request.put; read side = rule genResp. + --------------------------------------------------------------------------- + U_AtomicOpReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => REQ_WIDTH_G, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => reqValid, -- request.put enable (pass-through) + din => reqData, -- AtomicOpReq packed (pass-through) + full => open, + not_full => reqQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => reqQRdEn, -- genResp deq + dout => reqQDout, + valid => reqQValid, -- atomicOpReqQ.notEmpty + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_AtomicOpRespQ : surf.Fifo + -- BSV: FIFOF#(AtomicOpResp) atomicOpRespQ <- mkFIFOF. Write side = rule + -- genResp; read side = caller's response.get. + --------------------------------------------------------------------------- + U_AtomicOpRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => RESP_WIDTH_G, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => respQWrEn, -- genResp enq + din => respQDin, -- AtomicOpResp packed (stub) + full => open, + not_full => respQNotFull, -- genResp implicit condition + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => respRdy, -- response.get enable (pass-through) + dout => respQDout, + valid => respQValid, -- atomicOpRespQ.notEmpty + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/BinaryArbTree.vhd b/ethernet/RoCEv2/rtl/BinaryArbTree.vhd new file mode 100644 index 0000000000..f6b64be241 --- /dev/null +++ b/ethernet/RoCEv2/rtl/BinaryArbTree.vhd @@ -0,0 +1,217 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Purely structural netlist — this entity owns NO state, NO rules, and NO +-- SURF instances directly (mapping.json: rule_count=0, state_registers=[], +-- surf_instances=[]). No RegType/comb/seq two-process pair is emitted; per +-- the FSM spec this level is nothing but wiring between PORT_COUNT_G PipeOut +-- inputs, PORT_COUNT_G-1 BinaryPipeOutArbiter child instances, and 1 PipeOut +-- output. All arbitration behaviour lives in the child entity +-- (out/03-fsm/BinaryPipeOutArbiter.fsm.md / out/04-vhdl/BinaryPipeOutArbiter.vhd). +-- +-- OQ-FSM-PERMARB-01 (supersedes the OQ-HIER-01 fixed unroll): emitted GENERIC +-- over PORT_COUNT_G (any power of 2, >= 2). The tree and the leaf permutation +-- are built in generate statements: +-- * level 0 (leaves, PORT_COUNT_G/2 arbiters) pairs the physical inputs in +-- FFT bit-reverse order, per mkLeafBinaryPipeOutArbiterVec: leaf j takes +-- inputs bitRev(2j) / bitRev(2j+1), reversal over log2(PORT_COUNT_G) bits. +-- This permutation is DIFFERENT at each PORT_COUNT_G (e.g. 8 -> leaves +-- (0,4)(2,6)(1,5)(3,7); 4 -> (0,2)(1,3); 2 -> (0,1)), which is why a +-- fixed unroll cannot serve the mixed portSz=8 (ClientArbiter +-- specializations, dataStreamArb) and portSz=4 (WorkComp arbiters) uses. +-- * levels 1..log2(PORT_COUNT_G)-1 pair the previous level's outputs in +-- LINEAR order (idx, idx+1), per mkBinaryPipeOutArbiterTree's recursion. +-- Total: PORT_COUNT_G-1 arbiters in log2(PORT_COUNT_G) levels; the single +-- level-(depth-1) node is the tree apex driving the output PipeOut. +-- PORT_COUNT_G=2 degenerates to a single arbiter (matches the BSV portSz==1 +-- recursion base case returning the lone leaf unchanged). +-- +-- Ports are vectored/flattened (interface CHANGED vs the pre-2026-07-03 +-- fixed-4 emit): valid/finished/rd are slv(PORT_COUNT_G-1 downto 0); dout is +-- slv(PORT_COUNT_G*DATA_WIDTH_G-1 downto 0) with input k occupying bits +-- ((k+1)*DATA_WIDTH_G-1 downto k*DATA_WIDTH_G). +-- +-- OQ-FSM-ARBTREE-01 (RESOLVED, 2026-07-01): the child BinaryPipeOutArbiter +-- exposes an `outFinished` output (buffered head's finish predicate, +-- companion-carried through its U_OutQ FIFO), so inter-level `Finished` +-- wiring is a pure port connection — no predicate logic in this entity. +-- +-- SURF components instantiated: NONE directly. Each child arbiter +-- instantiates its own surf.Fifo (U_OutQ) internally — see +-- out/04-vhdl/BinaryPipeOutArbiter.vhd. +-- +-- NOTE: emitting does not prove equivalence — simulate this entity against +-- the BSV behaviour before trusting it. The child BinaryPipeOutArbiter must +-- pass its own Stage-5 verification before this tree's result can be trusted. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity BinaryArbTree is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + PORT_COUNT_G : positive := 8; -- number of tree inputs; any power of 2, >= 2 (OQ-FSM-PERMARB-01) + DATA_WIDTH_G : positive := 8; -- payload width = tSz of BSV anytype + MEMORY_TYPE_G : string := "distributed"; -- child output FIFO RAM style + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- child output FIFO depth = 2**ADDR + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- PORT_COUNT_G upstream PipeOut inputs (tree leaves, bit-reverse paired); + -- input k's payload is inDout((k+1)*DATA_WIDTH_G-1 downto k*DATA_WIDTH_G) + inValid : in slv(PORT_COUNT_G-1 downto 0); -- in(k).notEmpty + inDout : in slv(PORT_COUNT_G*DATA_WIDTH_G-1 downto 0); -- in(k).first, flattened + inFinished : in slv(PORT_COUNT_G-1 downto 0); -- isPipePayloadFinished(in(k).first), OQ-FSM-17 + inRd : out slv(PORT_COUNT_G-1 downto 0); -- in(k).deq strobe + -- tree PipeOut output + outNotEmpty : out sl; -- tree PipeOut.notEmpty (apex outNotEmpty) + outDout : out slv(DATA_WIDTH_G-1 downto 0); -- tree PipeOut.first (apex outDout) + outFinished : out sl; -- tree head finish predicate (apex outFinished) + outDeq : in sl); -- external dequeue of the tree output +end entity BinaryArbTree; + +architecture struct of BinaryArbTree is + + constant DEPTH_C : natural := log2(PORT_COUNT_G); -- tree levels + constant NODE_COUNT_C : natural := PORT_COUNT_G-1; -- total arbiters + constant APEX_C : natural := NODE_COUNT_C-1; -- global index of the root node + + -- Global node numbering, level-major: level 0 (leaves) has PORT_COUNT_G/2 + -- nodes at indices 0..PORT_COUNT_G/2-1, level L has PORT_COUNT_G/2**(L+1) + -- nodes starting at nodeBaseIdx(L); the single level-(DEPTH_C-1) node is + -- the apex (index APEX_C). + function nodeBaseIdx (lvl : natural) return natural is + begin + return PORT_COUNT_G - (PORT_COUNT_G/(2**lvl)); + end function nodeBaseIdx; + + -- FFT bit-reverse of a leaf input index over DEPTH_C bits + -- (mkLeafBinaryPipeOutArbiterVec: reverseBits on Bit#(TLog#(portSz))). + function bitRevIdx (idx : natural) return natural is + variable ret : natural := 0; + variable tmp : natural := idx; + begin + for i in 0 to DEPTH_C-1 loop + ret := (ret*2) + (tmp mod 2); + tmp := tmp/2; + end loop; + return ret; + end function bitRevIdx; + + type DoutArrayType is array (natural range <>) of slv(DATA_WIDTH_G-1 downto 0); + + -- Per-node output PipeOut nets (node index = global numbering above). + -- Forward: notEmpty/dout/finished driven by the node's arbiter instance. + -- Backward: deq driven by the parent node (or by outDeq for the apex). + signal nodeNotEmpty : slv(NODE_COUNT_C-1 downto 0); + signal nodeDout : DoutArrayType(NODE_COUNT_C-1 downto 0); + signal nodeFinished : slv(NODE_COUNT_C-1 downto 0); + signal nodeDeq : slv(NODE_COUNT_C-1 downto 0); + +begin + + -- Generic generate-tree is only defined for power-of-2 port counts + -- (BSV proviso Add#(TLog#(portSz), 1, TLog#(TAdd#(1, portSz)))). + assert isPowerOf2(PORT_COUNT_G) and (PORT_COUNT_G >= 2) + report "BinaryArbTree: PORT_COUNT_G must be a power of 2 and >= 2 " & + "(BSV power-of-2 proviso; OQ-FSM-PERMARB-01)" + severity failure; + + -------------------------------------------------------------------------- + -- Level 0 — leaves: PORT_COUNT_G/2 arbiters, FFT bit-reverse input pairing + -- (leaf j = arb(in(bitRev(2j)), in(bitRev(2j+1))), per + -- mkLeafBinaryPipeOutArbiterVec). + -------------------------------------------------------------------------- + GEN_LEAF : for node in 0 to (PORT_COUNT_G/2)-1 generate + constant LEFT_C : natural := bitRevIdx(2*node); + constant RIGHT_C : natural := bitRevIdx((2*node)+1); + begin + U_Arb : entity surf.BinaryPipeOutArbiter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DATA_WIDTH_G => DATA_WIDTH_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + clk => clk, + rst => rst, + pipeIn1Valid => inValid(LEFT_C), + pipeIn1Dout => inDout((LEFT_C+1)*DATA_WIDTH_G-1 downto LEFT_C*DATA_WIDTH_G), + pipeIn1Finished => inFinished(LEFT_C), + pipeIn1Rd => inRd(LEFT_C), + pipeIn2Valid => inValid(RIGHT_C), + pipeIn2Dout => inDout((RIGHT_C+1)*DATA_WIDTH_G-1 downto RIGHT_C*DATA_WIDTH_G), + pipeIn2Finished => inFinished(RIGHT_C), + pipeIn2Rd => inRd(RIGHT_C), + outNotEmpty => nodeNotEmpty(node), + outDout => nodeDout(node), + outFinished => nodeFinished(node), + outDeq => nodeDeq(node)); + end generate GEN_LEAF; + + -------------------------------------------------------------------------- + -- Levels 1..DEPTH_C-1 — linear pairing of the previous level's outputs + -- (mkBinaryPipeOutArbiterTree recursion: arb(prev(2j), prev(2j+1))). + -- Inter-level Finished wiring is a pure port connection to the children's + -- outFinished (OQ-FSM-ARBTREE-01 resolved). + -------------------------------------------------------------------------- + GEN_LVL : for lvl in 1 to DEPTH_C-1 generate + begin + GEN_NODE : for node in 0 to (PORT_COUNT_G/(2**(lvl+1)))-1 generate + constant NODE_C : natural := nodeBaseIdx(lvl) + node; + constant CH1_C : natural := nodeBaseIdx(lvl-1) + (2*node); + constant CH2_C : natural := nodeBaseIdx(lvl-1) + (2*node) + 1; + begin + U_Arb : entity surf.BinaryPipeOutArbiter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DATA_WIDTH_G => DATA_WIDTH_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + clk => clk, + rst => rst, + pipeIn1Valid => nodeNotEmpty(CH1_C), + pipeIn1Dout => nodeDout(CH1_C), + pipeIn1Finished => nodeFinished(CH1_C), + pipeIn1Rd => nodeDeq(CH1_C), + pipeIn2Valid => nodeNotEmpty(CH2_C), + pipeIn2Dout => nodeDout(CH2_C), + pipeIn2Finished => nodeFinished(CH2_C), + pipeIn2Rd => nodeDeq(CH2_C), + outNotEmpty => nodeNotEmpty(NODE_C), + outDout => nodeDout(NODE_C), + outFinished => nodeFinished(NODE_C), + outDeq => nodeDeq(NODE_C)); + end generate GEN_NODE; + end generate GEN_LVL; + + -------------------------------------------------------------------------- + -- Tree apex — the last node's PipeOut is the tree output. + -------------------------------------------------------------------------- + outNotEmpty <= nodeNotEmpty(APEX_C); + outDout <= nodeDout(APEX_C); + outFinished <= nodeFinished(APEX_C); + nodeDeq(APEX_C) <= outDeq; + +end architecture struct; diff --git a/ethernet/RoCEv2/rtl/BinaryPipeOutArbiter.vhd b/ethernet/RoCEv2/rtl/BinaryPipeOutArbiter.vhd new file mode 100644 index 0000000000..1503fb3d0f --- /dev/null +++ b/ethernet/RoCEv2/rtl/BinaryPipeOutArbiter.vhd @@ -0,0 +1,281 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Two-input PipeOut arbiter. A single BSV rule (binaryArbitrate, +-- (* fire_when_enabled *)) every cycle: +-- * picks a granted input (curGrantIdx), +-- * dequeues that input (pipeInRd), +-- * enqueues its payload into the output FIFO (U_OutQ), +-- * decides whether to re-arbitrate next cycle from the finish predicate. +-- +-- The rule fires whenever the selected input is valid AND the output FIFO has +-- room (ruleFiresEn = selectedValid AND outQNotFull). All register updates of +-- the rule are one atomic comb block — never split across cycles. +-- +-- Two architectural states, encoded by needArbitrationReg: +-- ARB_S (needArbitrationReg='1') : pick a NEW grant this cycle +-- (curGrantIdx = shouldGrantPipeIn2), +-- updating grantReg/priorityReg. +-- PASS_S (needArbitrationReg='0') : continue on the current grantReg +-- (curGrantIdx = grantReg); grant/priority +-- held. +-- needArbitrationReg is loaded from the (selected) finish predicate every +-- firing cycle: '1' -> ARB_S next, '0' -> PASS_S next. Per the FSM spec this +-- is one `if ruleFiresEn then ... end if` block with the next-state selection +-- done by `v.needArbitrationReg := selectedFinished` — NOT separate branches +-- per next state. +-- +-- shouldGrantPipeIn2 = (priorityReg AND pipeIn2Valid) +-- OR (NOT pipeIn1Valid AND pipeIn2Valid) +-- = pipeIn2Valid AND (priorityReg OR NOT pipeIn1Valid) +-- priorityReg flips to the loser each ARB cycle, giving alternating fairness; +-- reset priority is pipeIn1 ("initial grant to LSB", Arbitration.bsv:243). +-- +-- OQ-FSM-17 (RESOLVED here) — isPipePayloadFinished function parameter: +-- BSV `isPipePayloadFinished(inputPayload)` is an elaboration-time function +-- argument applied to the SELECTED payload; VHDL has no function-type ports. +-- This is a generic, reusable 2-input leaf (instantiated 3x in BinaryArbTree +-- with possibly different request/response predicates), so the payload type +-- and its finish bit are unknown here. Resolution: expose the predicate as +-- PER-CHANNEL 1-bit combinational input ports (pipeIn1Finished, +-- pipeIn2Finished) computed by the parent (where the type is known) and +-- selected internally by the same curGrantIdx mux. Muxing the per-channel +-- predicate results == applying the predicate to the muxed payload (pure +-- function), so this is exactly faithful to the BSV. See RESOLVED.md. +-- +-- OQ-FSM-ARBTREE-01 (RESOLVED here) — outFinished companion output: +-- When leaves feed a ROOT arbiter (BinaryArbTree), the root needs the finish +-- predicate of EACH leaf's OUTPUT head (predicate(U_LeftLeaf.outDout) / +-- predicate(U_RightLeaf.outDout)). The generic tree cannot recompute the +-- predicate (type/logic unknown at that level), and the parent can only wire +-- it if the leaf exports it. Resolution: carry the 1-bit finish predicate as +-- a companion THROUGH U_OutQ — the FIFO element is widened to +-- {finishedBit, payload}, the selected pipeInFinished is enqueued +-- alongside the selected payload, and the FIFO head's stored finished bit is +-- exposed as the new `outFinished` output. Because isPipePayloadFinished is a +-- pure function of the payload, the head's stored bit == predicate(outDout), +-- so leaf->root wiring becomes a pure port connection (no predicate logic in +-- the tree). Exactly faithful to BSV; extends the OQ-FSM-17 argument to the +-- buffered head. `outFinished` is only meaningful while outNotEmpty='1'. +-- +-- SURF components instantiated: +-- * U_OutQ : surf.Fifo <- BSV pipeOutQ (mkFIFOF FIFOF#(anytype)) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- The FIFO read side (dout/valid/rd_en) is the entity's PipeOut output +-- interface (first/notEmpty/deq) — driven by the downstream consumer, not +-- by this FSM. FWFT_EN_G => true so `valid` = head-present = BSV notEmpty. +-- The FIFO element width is DATA_WIDTH_G+1: bit DATA_WIDTH_G is the finished +-- companion (outFinished), bits DATA_WIDTH_G-1..0 are the payload (outDout). +-- BSV mkFIFOF is depth 2; surf.Fifo minimum ADDR_WIDTH is 4 (depth 16). +-- Functionally a buffering FIFO; depth differs and there is an inherent +-- ~1-cycle write->valid read latency vs BSV mkFIFOF (surf.Fifo sync +-- write-ptr -> read-FSM handshake) — functionally equivalent, NOT +-- cycle-accurate. MEMORY_TYPE_G defaults to "distributed" (1-cycle read +-- branch); set "block" for wide payloads at the cost of a DOB_REG stage. +-- +-- NOTE: emitting does not prove equivalence — simulate this entity (cocotb) +-- against the BSV behaviour before trusting it. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity BinaryPipeOutArbiter is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + DATA_WIDTH_G : positive := 8; -- payload width = tSz of BSV anytype + MEMORY_TYPE_G : string := "distributed"; -- output FIFO RAM style + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- output FIFO depth = 2**ADDR (BSV mkFIFOF depth 2; SURF min 4) + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- pipeIn1 (PipeOut#) input, preferred at reset ("initial grant to LSB") + pipeIn1Valid : in sl; -- pipeIn1.notEmpty + pipeIn1Dout : in slv(DATA_WIDTH_G-1 downto 0); -- pipeIn1.first + pipeIn1Finished : in sl; -- isPipePayloadFinished(pipeIn1.first) (OQ-FSM-17) + pipeIn1Rd : out sl; -- pipeIn1.deq strobe + -- pipeIn2 (PipeOut#) input + pipeIn2Valid : in sl; -- pipeIn2.notEmpty + pipeIn2Dout : in slv(DATA_WIDTH_G-1 downto 0); -- pipeIn2.first + pipeIn2Finished : in sl; -- isPipePayloadFinished(pipeIn2.first) (OQ-FSM-17) + pipeIn2Rd : out sl; -- pipeIn2.deq strobe + -- PipeOut output interface (read side of U_OutQ; driven by downstream) + outNotEmpty : out sl; -- PipeOut.notEmpty (U_OutQ.valid) + outDout : out slv(DATA_WIDTH_G-1 downto 0); -- PipeOut.first (U_OutQ.dout payload) + outFinished : out sl; -- isPipePayloadFinished(outDout), buffered head bit (OQ-FSM-ARBTREE-01) + outDeq : in sl); -- PipeOut.deq (U_OutQ.rd_en) +end BinaryPipeOutArbiter; + +architecture rtl of BinaryPipeOutArbiter is + + -- All registered state (BSV: three mkReg). The two architectural states + -- ARB_S/PASS_S are encoded by needArbitrationReg; grantReg/priorityReg are + -- auxiliary registers persisting across arbitration decisions. + type RegType is record + needArbitrationReg : sl; -- '1'=ARB_S (re-arbitrate), '0'=PASS_S + priorityReg : sl; -- '0'=pipeIn1 preferred, '1'=pipeIn2 + grantReg : sl; -- last grant: '0'=pipeIn1, '1'=pipeIn2 + end record RegType; + + constant REG_INIT_C : RegType := ( + needArbitrationReg => '1', -- BSV mkReg(True) -> start in ARB_S + priorityReg => '0', -- BSV mkReg(False) -> pipeIn1 preferred + grantReg => '0'); -- BSV mkReg(False) -> default to pipeIn1 + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_OutQ element width = payload + 1-bit finished companion (OQ-FSM-ARBTREE-01). + -- Layout: bit DATA_WIDTH_G = finished, bits DATA_WIDTH_G-1..0 = payload. + constant FIFO_WIDTH_C : positive := DATA_WIDTH_G + 1; + + -- U_OutQ (surf.Fifo) handshake/status + signal outQNotFull : sl; -- not_full : back-pressure (room to enqueue) + signal outQValid : sl; -- valid : head present (= PipeOut.notEmpty) + signal outQDout : slv(FIFO_WIDTH_C-1 downto 0); -- dout {finished, payload} + signal outQWrEn : sl; -- wr_en : enqueue strobe (Mealy, comb) + signal outQDin : slv(FIFO_WIDTH_C-1 downto 0); -- din {selectedFinished, selectedData} (comb) + +begin + + -------------------------------------------------------------------------- + -- BSV pipeOutQ (mkFIFOF FIFOF#(anytype)) -> surf.Fifo + -- Write side driven by the FSM (outQWrEn/outQDin). Read side is the + -- entity's PipeOut output interface, driven by the downstream consumer + -- (outDeq). FWFT: valid = head-present = BSV notEmpty. + -------------------------------------------------------------------------- + U_OutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, -- single clock (wr_clk = rd_clk) + FWFT_EN_G => true, -- valid = head present = BSV notEmpty + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => FIFO_WIDTH_C, -- payload + finished companion bit + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => outQWrEn, + din => outQDin, + not_full => outQNotFull, + rd_clk => clk, + rd_en => outDeq, + dout => outQDout, + valid => outQValid); + + -- PipeOut output interface (downstream reads U_OutQ directly). The head word + -- unpacks into {finished, payload} (OQ-FSM-ARBTREE-01). + outNotEmpty <= outQValid; + outDout <= outQDout(DATA_WIDTH_G-1 downto 0); + outFinished <= outQDout(DATA_WIDTH_G); + + -------------------------------------------------------------------------- + -- Combinatorial : single rule binaryArbitrate (one atomic action block). + -- See BinaryPipeOutArbiter.fsm.md transition table. + -------------------------------------------------------------------------- + comb : process (r, rst, pipeIn1Valid, pipeIn1Dout, pipeIn1Finished, + pipeIn2Valid, pipeIn2Dout, pipeIn2Finished, outQNotFull) is + variable v : RegType; + variable shouldGrantPipeIn2 : sl; + variable curGrantIdx : sl; + variable selectedData : slv(DATA_WIDTH_G-1 downto 0); + variable selectedValid : sl; + variable selectedFinished : sl; + variable ruleFiresEn : sl; + begin + -- Latch the current state + v := r; + + -- Default Mealy strobes (no rule firing). These are signals/ports, so + -- driven with <= ; the last assignment in this process wins. + outQWrEn <= '0'; + outQDin <= (others => '0'); + pipeIn1Rd <= '0'; + pipeIn2Rd <= '0'; + + -- shouldGrantPipeIn2 = pipeIn2Valid AND (priorityReg OR NOT pipeIn1Valid) + shouldGrantPipeIn2 := (r.priorityReg and pipeIn2Valid) or + ((not pipeIn1Valid) and pipeIn2Valid); + + -- Current grant index: re-arbitrated in ARB_S, held in PASS_S. + if (r.needArbitrationReg = '1') then -- ARB_S + curGrantIdx := shouldGrantPipeIn2; + else -- PASS_S + curGrantIdx := r.grantReg; + end if; + + -- Mux the selected input channel by curGrantIdx. Selecting the finish + -- predicate per channel == isPipePayloadFinished(selectedData) (OQ-FSM-17). + if (curGrantIdx = '0') then + selectedData := pipeIn1Dout; + selectedValid := pipeIn1Valid; + selectedFinished := pipeIn1Finished; + else + selectedData := pipeIn2Dout; + selectedValid := pipeIn2Valid; + selectedFinished := pipeIn2Finished; + end if; + + -- Implicit rule condition: selected input valid AND output FIFO has room. + ruleFiresEn := selectedValid and outQNotFull; + + -- Atomic rule body (single block; next-state from selectedFinished). + if (ruleFiresEn = '1') then + -- ARB_S re-arbitration updates the auxiliary grant/priority registers; + -- PASS_S holds them (BSV: grant/priority written only under needArbitration). + if (r.needArbitrationReg = '1') then + v.grantReg := shouldGrantPipeIn2; + v.priorityReg := not shouldGrantPipeIn2; + end if; + + -- Next-state select: '1' -> ARB_S, '0' -> PASS_S + v.needArbitrationReg := selectedFinished; + + -- Enqueue selected payload + its finished companion, and dequeue the + -- granted input. Storing selectedFinished with the payload lets the + -- FIFO head expose outFinished == predicate(outDout) (OQ-FSM-ARBTREE-01). + outQWrEn <= '1'; + outQDin <= selectedFinished & selectedData; + pipeIn1Rd <= not curGrantIdx; -- '1' when curGrantIdx = '0' + pipeIn2Rd <= curGrantIdx; -- '1' when curGrantIdx = '1' + end if; + + -- Synchronous Reset + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + end process comb; + + -------------------------------------------------------------------------- + -- Sequential + -------------------------------------------------------------------------- + seq : process (clk, rst) is + begin + if (RST_ASYNC_G) and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/BinaryTreeFork.vhd b/ethernet/RoCEv2/rtl/BinaryTreeFork.vhd new file mode 100644 index 0000000000..2f1f39c1b4 --- /dev/null +++ b/ethernet/RoCEv2/rtl/BinaryTreeFork.vhd @@ -0,0 +1,1140 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Duplicates one incoming item to all VSZ_G output pipes through a binary +-- tree of doublers. This file contains four design units corresponding to +-- the four levels needed for VSZ_G=16: +-- +-- BinaryTreeFork_L0 (base case, 2 outputs, 2 FIFOs) +-- BinaryTreeFork_L1 (level 1, 4 outputs, 4 FIFOs + U_SubFork:L0) +-- BinaryTreeFork_L2 (level 2, 8 outputs, 8 FIFOs + U_SubFork:L1) +-- BinaryTreeFork (top / L3, 16 outputs, 16 FIFOs + U_SubFork:L2) +-- +-- VHDL does not support recursive entity instantiation; layered entities +-- replace the BSV recursive self-instantiation (OQ-FSM-BTF-02 resolved: +-- layered-entities option chosen). +-- BinaryTreeFork is the public name expected by CacheFifo. +-- +-- clearAll semantics (OQ-FSM-BTF-04, resolved via OQ-FSM-06 RESOLVED.md): +-- forkQRst = rstNorm OR clearAll (level-sensitive; SURF FifoSync safe). +-- No pulse generator needed. +-- +-- Interface (OQ-FSM-BTF-01 resolved): +-- mapping.json listed Server#(req,resp); actual interface is +-- Vector#(vSz, PipeOut#(anytype)). Port list follows fsm.md. +-- +-- Concrete DATA_W_G values (OQ-FSM-BTF-03 partial): +-- readCacheQ instantiation: DATA_W_G = 176 (ReadCacheItem) +-- atomicCacheQ instantiation: DATA_W_G = TBD (RdmaOpCode width unresolved) +-- +-- SURF components (30 total): +-- surf.Fifo GEN_SYNC_FIFO_G=true, FWFT_EN_G=true, RST_POLARITY_G='1' +-- source: surf/base/fifo/rtl/Fifo.vhd +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + + +-- =========================================================================== +-- BinaryTreeFork_L0 (base case, VSZ_G = 2) +-- BSV rules: dupPipeIn, discardInput, resetAndClear[0..1] +-- =========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library surf; +use surf.StdRtlPkg.all; + +entity BinaryTreeFork_L0 is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + DATA_W_G : positive := 176; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "distributed"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + clearAll : in sl; + -- Upstream PipeIn + pipeInValid : in sl; + pipeInDout : in slv(DATA_W_G-1 downto 0); + pipeInRdEn : out sl; + -- Output pipe 0 (resultVec[0]) + pipeOut0Valid : out sl; + pipeOut0Dout : out slv(DATA_W_G-1 downto 0); + pipeOut0RdEn : in sl; + -- Output pipe 1 (resultVec[1]) + pipeOut1Valid : out sl; + pipeOut1Dout : out slv(DATA_W_G-1 downto 0); + pipeOut1RdEn : in sl); +end entity BinaryTreeFork_L0; + +architecture rtl of BinaryTreeFork_L0 is + + -- No live registered state; one dummy field keeps RegType non-empty. + type RegType is record + dummy : sl; + end record RegType; + constant REG_INIT_C : RegType := (dummy => '0'); + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rstNorm : sl; + signal forkQRst : sl; + signal forkQ0WrEn : sl; + signal forkQ1WrEn : sl; + signal forkQ0NotFull : sl; + signal forkQ1NotFull : sl; + signal forkQ0Valid : sl; + signal forkQ0Dout : slv(DATA_W_G-1 downto 0); + signal forkQ1Valid : sl; + signal forkQ1Dout : slv(DATA_W_G-1 downto 0); + +begin + + rstNorm <= rst when (RST_POLARITY_G = '1') else not rst; + forkQRst <= rstNorm or clearAll; + + -- U_ForkQ_0 : resultVec[0] + U_ForkQ_0 : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => DATA_W_G, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => forkQRst, + wr_clk => clk, + wr_en => forkQ0WrEn, + din => pipeInDout, + not_full => forkQ0NotFull, + rd_clk => clk, + rd_en => pipeOut0RdEn, + dout => forkQ0Dout, + valid => forkQ0Valid); + + -- U_ForkQ_1 : resultVec[1] + U_ForkQ_1 : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => DATA_W_G, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => forkQRst, + wr_clk => clk, + wr_en => forkQ1WrEn, + din => pipeInDout, + not_full => forkQ1NotFull, + rd_clk => clk, + rd_en => pipeOut1RdEn, + dout => forkQ1Dout, + valid => forkQ1Valid); + + pipeOut0Valid <= forkQ0Valid; + pipeOut0Dout <= forkQ0Dout; + pipeOut1Valid <= forkQ1Valid; + pipeOut1Dout <= forkQ1Dout; + + -- Combinatorial: dupPipeIn + discardInput + comb : process(r, rst, clearAll, pipeInValid, + forkQ0NotFull, forkQ1NotFull) is + variable v : RegType; + variable rdEnV : sl; + variable fq0WrV : sl; + variable fq1WrV : sl; + begin + v := r; + rdEnV := '0'; + fq0WrV := '0'; + fq1WrV := '0'; + + if clearAll = '1' then + -- discardInput: drain upstream while FIFOs are being cleared + rdEnV := pipeInValid; + else + -- dupPipeIn: atomically dequeue from pipeIn, enqueue to both FIFOs + if pipeInValid = '1' and forkQ0NotFull = '1' and forkQ1NotFull = '1' then + rdEnV := '1'; + fq0WrV := '1'; + fq1WrV := '1'; + end if; + end if; + + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + pipeInRdEn <= rdEnV; + forkQ0WrEn <= fq0WrV; + forkQ1WrEn <= fq1WrV; + end process comb; + + seq : process(clk, rst) is + begin + if RST_ASYNC_G and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; + + +-- =========================================================================== +-- BinaryTreeFork_L1 (level 1, VSZ_G = 4) +-- BSV rules: dupPipeOut[0..1], resetAndClear[0..3] +-- =========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library surf; +use surf.StdRtlPkg.all; + +entity BinaryTreeFork_L1 is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + DATA_W_G : positive := 176; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "distributed"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + clearAll : in sl; + pipeInValid : in sl; + pipeInDout : in slv(DATA_W_G-1 downto 0); + pipeInRdEn : out sl; + pipeOut0Valid : out sl; + pipeOut0Dout : out slv(DATA_W_G-1 downto 0); + pipeOut0RdEn : in sl; + pipeOut1Valid : out sl; + pipeOut1Dout : out slv(DATA_W_G-1 downto 0); + pipeOut1RdEn : in sl; + pipeOut2Valid : out sl; + pipeOut2Dout : out slv(DATA_W_G-1 downto 0); + pipeOut2RdEn : in sl; + pipeOut3Valid : out sl; + pipeOut3Dout : out slv(DATA_W_G-1 downto 0); + pipeOut3RdEn : in sl); +end entity BinaryTreeFork_L1; + +architecture rtl of BinaryTreeFork_L1 is + + type RegType is record + dummy : sl; + end record RegType; + constant REG_INIT_C : RegType := (dummy => '0'); + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rstNorm : sl; + signal forkQRst : sl; + -- Sub-fork (L0) interface + signal sfPipeInRdEn : sl; + signal sf0Valid : sl; + signal sf0Dout : slv(DATA_W_G-1 downto 0); + signal sf0RdEn : sl; + signal sf1Valid : sl; + signal sf1Dout : slv(DATA_W_G-1 downto 0); + signal sf1RdEn : sl; + -- ForkQ control / feedback + signal forkQ0WrEn : sl; + signal forkQ1WrEn : sl; + signal forkQ2WrEn : sl; + signal forkQ3WrEn : sl; + signal forkQ0NotFull : sl; + signal forkQ1NotFull : sl; + signal forkQ2NotFull : sl; + signal forkQ3NotFull : sl; + signal forkQ0Valid : sl; + signal forkQ0Dout : slv(DATA_W_G-1 downto 0); + signal forkQ1Valid : sl; + signal forkQ1Dout : slv(DATA_W_G-1 downto 0); + signal forkQ2Valid : sl; + signal forkQ2Dout : slv(DATA_W_G-1 downto 0); + signal forkQ3Valid : sl; + signal forkQ3Dout : slv(DATA_W_G-1 downto 0); + +begin + + rstNorm <= rst when (RST_POLARITY_G = '1') else not rst; + forkQRst <= rstNorm or clearAll; + pipeInRdEn <= sfPipeInRdEn; + + -- U_SubFork : halfSzFork (VSZ_G/2 = 2 outputs) + U_SubFork : entity surf.BinaryTreeFork_L0 + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DATA_W_G => DATA_W_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + clearAll => clearAll, + pipeInValid => pipeInValid, + pipeInDout => pipeInDout, + pipeInRdEn => sfPipeInRdEn, + pipeOut0Valid => sf0Valid, + pipeOut0Dout => sf0Dout, + pipeOut0RdEn => sf0RdEn, + pipeOut1Valid => sf1Valid, + pipeOut1Dout => sf1Dout, + pipeOut1RdEn => sf1RdEn); + + -- resultVec[0] ← halfSzPipeOutVec[0] + U_ForkQ_0 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ0WrEn, din=>sf0Dout, + not_full=>forkQ0NotFull, rd_clk=>clk, rd_en=>pipeOut0RdEn, + dout=>forkQ0Dout, valid=>forkQ0Valid); + + -- resultVec[1] ← halfSzPipeOutVec[0] + U_ForkQ_1 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ1WrEn, din=>sf0Dout, + not_full=>forkQ1NotFull, rd_clk=>clk, rd_en=>pipeOut1RdEn, + dout=>forkQ1Dout, valid=>forkQ1Valid); + + -- resultVec[2] ← halfSzPipeOutVec[1] + U_ForkQ_2 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ2WrEn, din=>sf1Dout, + not_full=>forkQ2NotFull, rd_clk=>clk, rd_en=>pipeOut2RdEn, + dout=>forkQ2Dout, valid=>forkQ2Valid); + + -- resultVec[3] ← halfSzPipeOutVec[1] + U_ForkQ_3 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ3WrEn, din=>sf1Dout, + not_full=>forkQ3NotFull, rd_clk=>clk, rd_en=>pipeOut3RdEn, + dout=>forkQ3Dout, valid=>forkQ3Valid); + + pipeOut0Valid <= forkQ0Valid; pipeOut0Dout <= forkQ0Dout; + pipeOut1Valid <= forkQ1Valid; pipeOut1Dout <= forkQ1Dout; + pipeOut2Valid <= forkQ2Valid; pipeOut2Dout <= forkQ2Dout; + pipeOut3Valid <= forkQ3Valid; pipeOut3Dout <= forkQ3Dout; + + -- Combinatorial: dupPipeOut[0..1] + comb : process(r, rst, clearAll, + sf0Valid, sf1Valid, + forkQ0NotFull, forkQ1NotFull, + forkQ2NotFull, forkQ3NotFull) is + variable v : RegType; + variable fq0WrV : sl; + variable fq1WrV : sl; + variable fq2WrV : sl; + variable fq3WrV : sl; + variable sf0RdV : sl; + variable sf1RdV : sl; + begin + v := r; + fq0WrV := '0'; fq1WrV := '0'; + fq2WrV := '0'; fq3WrV := '0'; + sf0RdV := '0'; sf1RdV := '0'; + + if clearAll = '0' then + -- dupPipeOut[0]: halfSzPipeOutVec[0] → resultVec[0], resultVec[1] + if sf0Valid = '1' and forkQ0NotFull = '1' and forkQ1NotFull = '1' then + sf0RdV := '1'; + fq0WrV := '1'; + fq1WrV := '1'; + end if; + -- dupPipeOut[1]: halfSzPipeOutVec[1] → resultVec[2], resultVec[3] + if sf1Valid = '1' and forkQ2NotFull = '1' and forkQ3NotFull = '1' then + sf1RdV := '1'; + fq2WrV := '1'; + fq3WrV := '1'; + end if; + end if; + + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + forkQ0WrEn <= fq0WrV; forkQ1WrEn <= fq1WrV; + forkQ2WrEn <= fq2WrV; forkQ3WrEn <= fq3WrV; + sf0RdEn <= sf0RdV; sf1RdEn <= sf1RdV; + end process comb; + + seq : process(clk, rst) is + begin + if RST_ASYNC_G and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; + + +-- =========================================================================== +-- BinaryTreeFork_L2 (level 2, VSZ_G = 8) +-- BSV rules: dupPipeOut[0..3], resetAndClear[0..7] +-- =========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library surf; +use surf.StdRtlPkg.all; + +entity BinaryTreeFork_L2 is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + DATA_W_G : positive := 176; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "distributed"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + clearAll : in sl; + pipeInValid : in sl; + pipeInDout : in slv(DATA_W_G-1 downto 0); + pipeInRdEn : out sl; + pipeOut0Valid : out sl; + pipeOut0Dout : out slv(DATA_W_G-1 downto 0); + pipeOut0RdEn : in sl; + pipeOut1Valid : out sl; + pipeOut1Dout : out slv(DATA_W_G-1 downto 0); + pipeOut1RdEn : in sl; + pipeOut2Valid : out sl; + pipeOut2Dout : out slv(DATA_W_G-1 downto 0); + pipeOut2RdEn : in sl; + pipeOut3Valid : out sl; + pipeOut3Dout : out slv(DATA_W_G-1 downto 0); + pipeOut3RdEn : in sl; + pipeOut4Valid : out sl; + pipeOut4Dout : out slv(DATA_W_G-1 downto 0); + pipeOut4RdEn : in sl; + pipeOut5Valid : out sl; + pipeOut5Dout : out slv(DATA_W_G-1 downto 0); + pipeOut5RdEn : in sl; + pipeOut6Valid : out sl; + pipeOut6Dout : out slv(DATA_W_G-1 downto 0); + pipeOut6RdEn : in sl; + pipeOut7Valid : out sl; + pipeOut7Dout : out slv(DATA_W_G-1 downto 0); + pipeOut7RdEn : in sl); +end entity BinaryTreeFork_L2; + +architecture rtl of BinaryTreeFork_L2 is + + type RegType is record + dummy : sl; + end record RegType; + constant REG_INIT_C : RegType := (dummy => '0'); + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rstNorm : sl; + signal forkQRst : sl; + -- Sub-fork (L1) interface — 4 outputs + signal sfPipeInRdEn : sl; + signal sf0Valid : sl; + signal sf0Dout : slv(DATA_W_G-1 downto 0); + signal sf0RdEn : sl; + signal sf1Valid : sl; + signal sf1Dout : slv(DATA_W_G-1 downto 0); + signal sf1RdEn : sl; + signal sf2Valid : sl; + signal sf2Dout : slv(DATA_W_G-1 downto 0); + signal sf2RdEn : sl; + signal sf3Valid : sl; + signal sf3Dout : slv(DATA_W_G-1 downto 0); + signal sf3RdEn : sl; + -- ForkQ control / feedback + signal forkQ0WrEn : sl; + signal forkQ1WrEn : sl; + signal forkQ2WrEn : sl; + signal forkQ3WrEn : sl; + signal forkQ4WrEn : sl; + signal forkQ5WrEn : sl; + signal forkQ6WrEn : sl; + signal forkQ7WrEn : sl; + signal forkQ0NotFull : sl; + signal forkQ1NotFull : sl; + signal forkQ2NotFull : sl; + signal forkQ3NotFull : sl; + signal forkQ4NotFull : sl; + signal forkQ5NotFull : sl; + signal forkQ6NotFull : sl; + signal forkQ7NotFull : sl; + signal forkQ0Valid : sl; + signal forkQ0Dout : slv(DATA_W_G-1 downto 0); + signal forkQ1Valid : sl; + signal forkQ1Dout : slv(DATA_W_G-1 downto 0); + signal forkQ2Valid : sl; + signal forkQ2Dout : slv(DATA_W_G-1 downto 0); + signal forkQ3Valid : sl; + signal forkQ3Dout : slv(DATA_W_G-1 downto 0); + signal forkQ4Valid : sl; + signal forkQ4Dout : slv(DATA_W_G-1 downto 0); + signal forkQ5Valid : sl; + signal forkQ5Dout : slv(DATA_W_G-1 downto 0); + signal forkQ6Valid : sl; + signal forkQ6Dout : slv(DATA_W_G-1 downto 0); + signal forkQ7Valid : sl; + signal forkQ7Dout : slv(DATA_W_G-1 downto 0); + +begin + + rstNorm <= rst when (RST_POLARITY_G = '1') else not rst; + forkQRst <= rstNorm or clearAll; + pipeInRdEn <= sfPipeInRdEn; + + -- U_SubFork : halfSzFork (VSZ_G/2 = 4 outputs) + U_SubFork : entity surf.BinaryTreeFork_L1 + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DATA_W_G => DATA_W_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + clearAll => clearAll, + pipeInValid => pipeInValid, + pipeInDout => pipeInDout, + pipeInRdEn => sfPipeInRdEn, + pipeOut0Valid => sf0Valid, + pipeOut0Dout => sf0Dout, + pipeOut0RdEn => sf0RdEn, + pipeOut1Valid => sf1Valid, + pipeOut1Dout => sf1Dout, + pipeOut1RdEn => sf1RdEn, + pipeOut2Valid => sf2Valid, + pipeOut2Dout => sf2Dout, + pipeOut2RdEn => sf2RdEn, + pipeOut3Valid => sf3Valid, + pipeOut3Dout => sf3Dout, + pipeOut3RdEn => sf3RdEn); + + U_ForkQ_0 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ0WrEn, din=>sf0Dout, + not_full=>forkQ0NotFull, rd_clk=>clk, rd_en=>pipeOut0RdEn, + dout=>forkQ0Dout, valid=>forkQ0Valid); + + U_ForkQ_1 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ1WrEn, din=>sf0Dout, + not_full=>forkQ1NotFull, rd_clk=>clk, rd_en=>pipeOut1RdEn, + dout=>forkQ1Dout, valid=>forkQ1Valid); + + U_ForkQ_2 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ2WrEn, din=>sf1Dout, + not_full=>forkQ2NotFull, rd_clk=>clk, rd_en=>pipeOut2RdEn, + dout=>forkQ2Dout, valid=>forkQ2Valid); + + U_ForkQ_3 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ3WrEn, din=>sf1Dout, + not_full=>forkQ3NotFull, rd_clk=>clk, rd_en=>pipeOut3RdEn, + dout=>forkQ3Dout, valid=>forkQ3Valid); + + U_ForkQ_4 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ4WrEn, din=>sf2Dout, + not_full=>forkQ4NotFull, rd_clk=>clk, rd_en=>pipeOut4RdEn, + dout=>forkQ4Dout, valid=>forkQ4Valid); + + U_ForkQ_5 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ5WrEn, din=>sf2Dout, + not_full=>forkQ5NotFull, rd_clk=>clk, rd_en=>pipeOut5RdEn, + dout=>forkQ5Dout, valid=>forkQ5Valid); + + U_ForkQ_6 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ6WrEn, din=>sf3Dout, + not_full=>forkQ6NotFull, rd_clk=>clk, rd_en=>pipeOut6RdEn, + dout=>forkQ6Dout, valid=>forkQ6Valid); + + U_ForkQ_7 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ7WrEn, din=>sf3Dout, + not_full=>forkQ7NotFull, rd_clk=>clk, rd_en=>pipeOut7RdEn, + dout=>forkQ7Dout, valid=>forkQ7Valid); + + pipeOut0Valid <= forkQ0Valid; pipeOut0Dout <= forkQ0Dout; + pipeOut1Valid <= forkQ1Valid; pipeOut1Dout <= forkQ1Dout; + pipeOut2Valid <= forkQ2Valid; pipeOut2Dout <= forkQ2Dout; + pipeOut3Valid <= forkQ3Valid; pipeOut3Dout <= forkQ3Dout; + pipeOut4Valid <= forkQ4Valid; pipeOut4Dout <= forkQ4Dout; + pipeOut5Valid <= forkQ5Valid; pipeOut5Dout <= forkQ5Dout; + pipeOut6Valid <= forkQ6Valid; pipeOut6Dout <= forkQ6Dout; + pipeOut7Valid <= forkQ7Valid; pipeOut7Dout <= forkQ7Dout; + + -- Combinatorial: dupPipeOut[0..3] + comb : process(r, rst, clearAll, + sf0Valid, sf1Valid, sf2Valid, sf3Valid, + forkQ0NotFull, forkQ1NotFull, + forkQ2NotFull, forkQ3NotFull, + forkQ4NotFull, forkQ5NotFull, + forkQ6NotFull, forkQ7NotFull) is + variable v : RegType; + variable fq0WrV : sl; variable fq1WrV : sl; + variable fq2WrV : sl; variable fq3WrV : sl; + variable fq4WrV : sl; variable fq5WrV : sl; + variable fq6WrV : sl; variable fq7WrV : sl; + variable sf0RdV : sl; variable sf1RdV : sl; + variable sf2RdV : sl; variable sf3RdV : sl; + begin + v := r; + fq0WrV := '0'; fq1WrV := '0'; fq2WrV := '0'; fq3WrV := '0'; + fq4WrV := '0'; fq5WrV := '0'; fq6WrV := '0'; fq7WrV := '0'; + sf0RdV := '0'; sf1RdV := '0'; sf2RdV := '0'; sf3RdV := '0'; + + if clearAll = '0' then + if sf0Valid='1' and forkQ0NotFull='1' and forkQ1NotFull='1' then + sf0RdV:='1'; fq0WrV:='1'; fq1WrV:='1'; + end if; + if sf1Valid='1' and forkQ2NotFull='1' and forkQ3NotFull='1' then + sf1RdV:='1'; fq2WrV:='1'; fq3WrV:='1'; + end if; + if sf2Valid='1' and forkQ4NotFull='1' and forkQ5NotFull='1' then + sf2RdV:='1'; fq4WrV:='1'; fq5WrV:='1'; + end if; + if sf3Valid='1' and forkQ6NotFull='1' and forkQ7NotFull='1' then + sf3RdV:='1'; fq6WrV:='1'; fq7WrV:='1'; + end if; + end if; + + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + forkQ0WrEn <= fq0WrV; forkQ1WrEn <= fq1WrV; + forkQ2WrEn <= fq2WrV; forkQ3WrEn <= fq3WrV; + forkQ4WrEn <= fq4WrV; forkQ5WrEn <= fq5WrV; + forkQ6WrEn <= fq6WrV; forkQ7WrEn <= fq7WrV; + sf0RdEn <= sf0RdV; sf1RdEn <= sf1RdV; + sf2RdEn <= sf2RdV; sf3RdEn <= sf3RdV; + end process comb; + + seq : process(clk, rst) is + begin + if RST_ASYNC_G and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; + + +-- =========================================================================== +-- BinaryTreeFork (top / level 3, VSZ_G = 16) +-- BSV rules: dupPipeOut[0..7], resetAndClear[0..15] +-- Public entity name consumed by CacheFifo. +-- =========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library surf; +use surf.StdRtlPkg.all; + +entity BinaryTreeFork is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + DATA_W_G : positive := 176; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "distributed"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + clearAll : in sl; + pipeInValid : in sl; + pipeInDout : in slv(DATA_W_G-1 downto 0); + pipeInRdEn : out sl; + pipeOut0Valid : out sl; + pipeOut0Dout : out slv(DATA_W_G-1 downto 0); + pipeOut0RdEn : in sl; + pipeOut1Valid : out sl; + pipeOut1Dout : out slv(DATA_W_G-1 downto 0); + pipeOut1RdEn : in sl; + pipeOut2Valid : out sl; + pipeOut2Dout : out slv(DATA_W_G-1 downto 0); + pipeOut2RdEn : in sl; + pipeOut3Valid : out sl; + pipeOut3Dout : out slv(DATA_W_G-1 downto 0); + pipeOut3RdEn : in sl; + pipeOut4Valid : out sl; + pipeOut4Dout : out slv(DATA_W_G-1 downto 0); + pipeOut4RdEn : in sl; + pipeOut5Valid : out sl; + pipeOut5Dout : out slv(DATA_W_G-1 downto 0); + pipeOut5RdEn : in sl; + pipeOut6Valid : out sl; + pipeOut6Dout : out slv(DATA_W_G-1 downto 0); + pipeOut6RdEn : in sl; + pipeOut7Valid : out sl; + pipeOut7Dout : out slv(DATA_W_G-1 downto 0); + pipeOut7RdEn : in sl; + pipeOut8Valid : out sl; + pipeOut8Dout : out slv(DATA_W_G-1 downto 0); + pipeOut8RdEn : in sl; + pipeOut9Valid : out sl; + pipeOut9Dout : out slv(DATA_W_G-1 downto 0); + pipeOut9RdEn : in sl; + pipeOut10Valid : out sl; + pipeOut10Dout : out slv(DATA_W_G-1 downto 0); + pipeOut10RdEn : in sl; + pipeOut11Valid : out sl; + pipeOut11Dout : out slv(DATA_W_G-1 downto 0); + pipeOut11RdEn : in sl; + pipeOut12Valid : out sl; + pipeOut12Dout : out slv(DATA_W_G-1 downto 0); + pipeOut12RdEn : in sl; + pipeOut13Valid : out sl; + pipeOut13Dout : out slv(DATA_W_G-1 downto 0); + pipeOut13RdEn : in sl; + pipeOut14Valid : out sl; + pipeOut14Dout : out slv(DATA_W_G-1 downto 0); + pipeOut14RdEn : in sl; + pipeOut15Valid : out sl; + pipeOut15Dout : out slv(DATA_W_G-1 downto 0); + pipeOut15RdEn : in sl); +end entity BinaryTreeFork; + +architecture rtl of BinaryTreeFork is + + type RegType is record + dummy : sl; + end record RegType; + constant REG_INIT_C : RegType := (dummy => '0'); + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rstNorm : sl; + signal forkQRst : sl; + -- Sub-fork (L2) interface — 8 outputs + signal sfPipeInRdEn : sl; + signal sf0Valid : sl; + signal sf0Dout : slv(DATA_W_G-1 downto 0); + signal sf0RdEn : sl; + signal sf1Valid : sl; + signal sf1Dout : slv(DATA_W_G-1 downto 0); + signal sf1RdEn : sl; + signal sf2Valid : sl; + signal sf2Dout : slv(DATA_W_G-1 downto 0); + signal sf2RdEn : sl; + signal sf3Valid : sl; + signal sf3Dout : slv(DATA_W_G-1 downto 0); + signal sf3RdEn : sl; + signal sf4Valid : sl; + signal sf4Dout : slv(DATA_W_G-1 downto 0); + signal sf4RdEn : sl; + signal sf5Valid : sl; + signal sf5Dout : slv(DATA_W_G-1 downto 0); + signal sf5RdEn : sl; + signal sf6Valid : sl; + signal sf6Dout : slv(DATA_W_G-1 downto 0); + signal sf6RdEn : sl; + signal sf7Valid : sl; + signal sf7Dout : slv(DATA_W_G-1 downto 0); + signal sf7RdEn : sl; + -- ForkQ write enables + signal forkQ0WrEn : sl; + signal forkQ1WrEn : sl; + signal forkQ2WrEn : sl; + signal forkQ3WrEn : sl; + signal forkQ4WrEn : sl; + signal forkQ5WrEn : sl; + signal forkQ6WrEn : sl; + signal forkQ7WrEn : sl; + signal forkQ8WrEn : sl; + signal forkQ9WrEn : sl; + signal forkQ10WrEn : sl; + signal forkQ11WrEn : sl; + signal forkQ12WrEn : sl; + signal forkQ13WrEn : sl; + signal forkQ14WrEn : sl; + signal forkQ15WrEn : sl; + -- ForkQ not_full feedback + signal forkQ0NotFull : sl; + signal forkQ1NotFull : sl; + signal forkQ2NotFull : sl; + signal forkQ3NotFull : sl; + signal forkQ4NotFull : sl; + signal forkQ5NotFull : sl; + signal forkQ6NotFull : sl; + signal forkQ7NotFull : sl; + signal forkQ8NotFull : sl; + signal forkQ9NotFull : sl; + signal forkQ10NotFull : sl; + signal forkQ11NotFull : sl; + signal forkQ12NotFull : sl; + signal forkQ13NotFull : sl; + signal forkQ14NotFull : sl; + signal forkQ15NotFull : sl; + -- ForkQ valid / dout + signal forkQ0Valid : sl; signal forkQ0Dout : slv(DATA_W_G-1 downto 0); + signal forkQ1Valid : sl; signal forkQ1Dout : slv(DATA_W_G-1 downto 0); + signal forkQ2Valid : sl; signal forkQ2Dout : slv(DATA_W_G-1 downto 0); + signal forkQ3Valid : sl; signal forkQ3Dout : slv(DATA_W_G-1 downto 0); + signal forkQ4Valid : sl; signal forkQ4Dout : slv(DATA_W_G-1 downto 0); + signal forkQ5Valid : sl; signal forkQ5Dout : slv(DATA_W_G-1 downto 0); + signal forkQ6Valid : sl; signal forkQ6Dout : slv(DATA_W_G-1 downto 0); + signal forkQ7Valid : sl; signal forkQ7Dout : slv(DATA_W_G-1 downto 0); + signal forkQ8Valid : sl; signal forkQ8Dout : slv(DATA_W_G-1 downto 0); + signal forkQ9Valid : sl; signal forkQ9Dout : slv(DATA_W_G-1 downto 0); + signal forkQ10Valid : sl; signal forkQ10Dout : slv(DATA_W_G-1 downto 0); + signal forkQ11Valid : sl; signal forkQ11Dout : slv(DATA_W_G-1 downto 0); + signal forkQ12Valid : sl; signal forkQ12Dout : slv(DATA_W_G-1 downto 0); + signal forkQ13Valid : sl; signal forkQ13Dout : slv(DATA_W_G-1 downto 0); + signal forkQ14Valid : sl; signal forkQ14Dout : slv(DATA_W_G-1 downto 0); + signal forkQ15Valid : sl; signal forkQ15Dout : slv(DATA_W_G-1 downto 0); + +begin + + rstNorm <= rst when (RST_POLARITY_G = '1') else not rst; + forkQRst <= rstNorm or clearAll; + pipeInRdEn <= sfPipeInRdEn; + + -- U_SubFork : halfSzFork (VSZ_G/2 = 8 outputs) + U_SubFork : entity surf.BinaryTreeFork_L2 + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DATA_W_G => DATA_W_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + clearAll => clearAll, + pipeInValid => pipeInValid, + pipeInDout => pipeInDout, + pipeInRdEn => sfPipeInRdEn, + pipeOut0Valid => sf0Valid, pipeOut0Dout => sf0Dout, pipeOut0RdEn => sf0RdEn, + pipeOut1Valid => sf1Valid, pipeOut1Dout => sf1Dout, pipeOut1RdEn => sf1RdEn, + pipeOut2Valid => sf2Valid, pipeOut2Dout => sf2Dout, pipeOut2RdEn => sf2RdEn, + pipeOut3Valid => sf3Valid, pipeOut3Dout => sf3Dout, pipeOut3RdEn => sf3RdEn, + pipeOut4Valid => sf4Valid, pipeOut4Dout => sf4Dout, pipeOut4RdEn => sf4RdEn, + pipeOut5Valid => sf5Valid, pipeOut5Dout => sf5Dout, pipeOut5RdEn => sf5RdEn, + pipeOut6Valid => sf6Valid, pipeOut6Dout => sf6Dout, pipeOut6RdEn => sf6RdEn, + pipeOut7Valid => sf7Valid, pipeOut7Dout => sf7Dout, pipeOut7RdEn => sf7RdEn); + + U_ForkQ_0 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ0WrEn, din=>sf0Dout, + not_full=>forkQ0NotFull, rd_clk=>clk, rd_en=>pipeOut0RdEn, + dout=>forkQ0Dout, valid=>forkQ0Valid); + + U_ForkQ_1 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ1WrEn, din=>sf0Dout, + not_full=>forkQ1NotFull, rd_clk=>clk, rd_en=>pipeOut1RdEn, + dout=>forkQ1Dout, valid=>forkQ1Valid); + + U_ForkQ_2 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ2WrEn, din=>sf1Dout, + not_full=>forkQ2NotFull, rd_clk=>clk, rd_en=>pipeOut2RdEn, + dout=>forkQ2Dout, valid=>forkQ2Valid); + + U_ForkQ_3 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ3WrEn, din=>sf1Dout, + not_full=>forkQ3NotFull, rd_clk=>clk, rd_en=>pipeOut3RdEn, + dout=>forkQ3Dout, valid=>forkQ3Valid); + + U_ForkQ_4 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ4WrEn, din=>sf2Dout, + not_full=>forkQ4NotFull, rd_clk=>clk, rd_en=>pipeOut4RdEn, + dout=>forkQ4Dout, valid=>forkQ4Valid); + + U_ForkQ_5 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ5WrEn, din=>sf2Dout, + not_full=>forkQ5NotFull, rd_clk=>clk, rd_en=>pipeOut5RdEn, + dout=>forkQ5Dout, valid=>forkQ5Valid); + + U_ForkQ_6 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ6WrEn, din=>sf3Dout, + not_full=>forkQ6NotFull, rd_clk=>clk, rd_en=>pipeOut6RdEn, + dout=>forkQ6Dout, valid=>forkQ6Valid); + + U_ForkQ_7 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ7WrEn, din=>sf3Dout, + not_full=>forkQ7NotFull, rd_clk=>clk, rd_en=>pipeOut7RdEn, + dout=>forkQ7Dout, valid=>forkQ7Valid); + + U_ForkQ_8 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ8WrEn, din=>sf4Dout, + not_full=>forkQ8NotFull, rd_clk=>clk, rd_en=>pipeOut8RdEn, + dout=>forkQ8Dout, valid=>forkQ8Valid); + + U_ForkQ_9 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ9WrEn, din=>sf4Dout, + not_full=>forkQ9NotFull, rd_clk=>clk, rd_en=>pipeOut9RdEn, + dout=>forkQ9Dout, valid=>forkQ9Valid); + + U_ForkQ_10 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ10WrEn, din=>sf5Dout, + not_full=>forkQ10NotFull, rd_clk=>clk, rd_en=>pipeOut10RdEn, + dout=>forkQ10Dout, valid=>forkQ10Valid); + + U_ForkQ_11 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ11WrEn, din=>sf5Dout, + not_full=>forkQ11NotFull, rd_clk=>clk, rd_en=>pipeOut11RdEn, + dout=>forkQ11Dout, valid=>forkQ11Valid); + + U_ForkQ_12 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ12WrEn, din=>sf6Dout, + not_full=>forkQ12NotFull, rd_clk=>clk, rd_en=>pipeOut12RdEn, + dout=>forkQ12Dout, valid=>forkQ12Valid); + + U_ForkQ_13 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ13WrEn, din=>sf6Dout, + not_full=>forkQ13NotFull, rd_clk=>clk, rd_en=>pipeOut13RdEn, + dout=>forkQ13Dout, valid=>forkQ13Valid); + + U_ForkQ_14 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ14WrEn, din=>sf7Dout, + not_full=>forkQ14NotFull, rd_clk=>clk, rd_en=>pipeOut14RdEn, + dout=>forkQ14Dout, valid=>forkQ14Valid); + + U_ForkQ_15 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>DATA_W_G, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>forkQRst, wr_clk=>clk, wr_en=>forkQ15WrEn, din=>sf7Dout, + not_full=>forkQ15NotFull, rd_clk=>clk, rd_en=>pipeOut15RdEn, + dout=>forkQ15Dout, valid=>forkQ15Valid); + + pipeOut0Valid <= forkQ0Valid; pipeOut0Dout <= forkQ0Dout; + pipeOut1Valid <= forkQ1Valid; pipeOut1Dout <= forkQ1Dout; + pipeOut2Valid <= forkQ2Valid; pipeOut2Dout <= forkQ2Dout; + pipeOut3Valid <= forkQ3Valid; pipeOut3Dout <= forkQ3Dout; + pipeOut4Valid <= forkQ4Valid; pipeOut4Dout <= forkQ4Dout; + pipeOut5Valid <= forkQ5Valid; pipeOut5Dout <= forkQ5Dout; + pipeOut6Valid <= forkQ6Valid; pipeOut6Dout <= forkQ6Dout; + pipeOut7Valid <= forkQ7Valid; pipeOut7Dout <= forkQ7Dout; + pipeOut8Valid <= forkQ8Valid; pipeOut8Dout <= forkQ8Dout; + pipeOut9Valid <= forkQ9Valid; pipeOut9Dout <= forkQ9Dout; + pipeOut10Valid <= forkQ10Valid; pipeOut10Dout <= forkQ10Dout; + pipeOut11Valid <= forkQ11Valid; pipeOut11Dout <= forkQ11Dout; + pipeOut12Valid <= forkQ12Valid; pipeOut12Dout <= forkQ12Dout; + pipeOut13Valid <= forkQ13Valid; pipeOut13Dout <= forkQ13Dout; + pipeOut14Valid <= forkQ14Valid; pipeOut14Dout <= forkQ14Dout; + pipeOut15Valid <= forkQ15Valid; pipeOut15Dout <= forkQ15Dout; + + -- Combinatorial: dupPipeOut[0..7] + comb : process(r, rst, clearAll, + sf0Valid, sf1Valid, sf2Valid, sf3Valid, + sf4Valid, sf5Valid, sf6Valid, sf7Valid, + forkQ0NotFull, forkQ1NotFull, + forkQ2NotFull, forkQ3NotFull, + forkQ4NotFull, forkQ5NotFull, + forkQ6NotFull, forkQ7NotFull, + forkQ8NotFull, forkQ9NotFull, + forkQ10NotFull, forkQ11NotFull, + forkQ12NotFull, forkQ13NotFull, + forkQ14NotFull, forkQ15NotFull) is + variable v : RegType; + variable fq0WrV : sl; variable fq1WrV : sl; + variable fq2WrV : sl; variable fq3WrV : sl; + variable fq4WrV : sl; variable fq5WrV : sl; + variable fq6WrV : sl; variable fq7WrV : sl; + variable fq8WrV : sl; variable fq9WrV : sl; + variable fq10WrV : sl; variable fq11WrV : sl; + variable fq12WrV : sl; variable fq13WrV : sl; + variable fq14WrV : sl; variable fq15WrV : sl; + variable sf0RdV : sl; variable sf1RdV : sl; + variable sf2RdV : sl; variable sf3RdV : sl; + variable sf4RdV : sl; variable sf5RdV : sl; + variable sf6RdV : sl; variable sf7RdV : sl; + begin + v := r; + fq0WrV := '0'; fq1WrV := '0'; fq2WrV := '0'; fq3WrV := '0'; + fq4WrV := '0'; fq5WrV := '0'; fq6WrV := '0'; fq7WrV := '0'; + fq8WrV := '0'; fq9WrV := '0'; fq10WrV := '0'; fq11WrV := '0'; + fq12WrV := '0'; fq13WrV := '0'; fq14WrV := '0'; fq15WrV := '0'; + sf0RdV := '0'; sf1RdV := '0'; sf2RdV := '0'; sf3RdV := '0'; + sf4RdV := '0'; sf5RdV := '0'; sf6RdV := '0'; sf7RdV := '0'; + + if clearAll = '0' then + if sf0Valid='1' and forkQ0NotFull='1' and forkQ1NotFull='1' then + sf0RdV:='1'; fq0WrV:='1'; fq1WrV:='1'; + end if; + if sf1Valid='1' and forkQ2NotFull='1' and forkQ3NotFull='1' then + sf1RdV:='1'; fq2WrV:='1'; fq3WrV:='1'; + end if; + if sf2Valid='1' and forkQ4NotFull='1' and forkQ5NotFull='1' then + sf2RdV:='1'; fq4WrV:='1'; fq5WrV:='1'; + end if; + if sf3Valid='1' and forkQ6NotFull='1' and forkQ7NotFull='1' then + sf3RdV:='1'; fq6WrV:='1'; fq7WrV:='1'; + end if; + if sf4Valid='1' and forkQ8NotFull='1' and forkQ9NotFull='1' then + sf4RdV:='1'; fq8WrV:='1'; fq9WrV:='1'; + end if; + if sf5Valid='1' and forkQ10NotFull='1' and forkQ11NotFull='1' then + sf5RdV:='1'; fq10WrV:='1'; fq11WrV:='1'; + end if; + if sf6Valid='1' and forkQ12NotFull='1' and forkQ13NotFull='1' then + sf6RdV:='1'; fq12WrV:='1'; fq13WrV:='1'; + end if; + if sf7Valid='1' and forkQ14NotFull='1' and forkQ15NotFull='1' then + sf7RdV:='1'; fq14WrV:='1'; fq15WrV:='1'; + end if; + end if; + + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + forkQ0WrEn <= fq0WrV; forkQ1WrEn <= fq1WrV; + forkQ2WrEn <= fq2WrV; forkQ3WrEn <= fq3WrV; + forkQ4WrEn <= fq4WrV; forkQ5WrEn <= fq5WrV; + forkQ6WrEn <= fq6WrV; forkQ7WrEn <= fq7WrV; + forkQ8WrEn <= fq8WrV; forkQ9WrEn <= fq9WrV; + forkQ10WrEn <= fq10WrV; forkQ11WrEn <= fq11WrV; + forkQ12WrEn <= fq12WrV; forkQ13WrEn <= fq13WrV; + forkQ14WrEn <= fq14WrV; forkQ15WrEn <= fq15WrV; + sf0RdEn <= sf0RdV; sf1RdEn <= sf1RdV; + sf2RdEn <= sf2RdV; sf3RdEn <= sf3RdV; + sf4RdEn <= sf4RdV; sf5RdEn <= sf5RdV; + sf6RdEn <= sf6RdV; sf7RdEn <= sf7RdV; + end process comb; + + seq : process(clk, rst) is + begin + if RST_ASYNC_G and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/CacheFifo.vhd b/ethernet/RoCEv2/rtl/CacheFifo.vhd new file mode 100644 index 0000000000..575c914fef --- /dev/null +++ b/ethernet/RoCEv2/rtl/CacheFifo.vhd @@ -0,0 +1,924 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- DESIGN NOTE - two specialised entities (OQ-FSM-CF-01, RESOLVED) +-- mkCacheFIFO is parameterised over THREE combinational stage functions and +-- the stored item type. It is instantiated twice (DupReadAtomicCache.bsv:719- +-- 724) with structurally different functions/types. VHDL has no function +-- generics, so per the resolved OQ-FSM-CF-01 this file emits TWO concrete +-- entities, each inlining its own three stage functions: +-- * CacheFifoRead <- readCacheQ (ReadCacheItem, item width 176) +-- * CacheFifoAtomic <- atomicCacheQ (AtomicCacheItem, item width 317) +-- The FSM/pipeline structure (CacheFifo.fsm.md) is identical for both. +-- +-- WIDTHS (OQ-FSM-CF-02 / OQ-FSM-CF-03, RESOLVED): +-- readCacheQ : item=176 searchData=359 cmpResult=235 searchResult=177 +-- atomicCacheQ : item=317 searchData=638 cmpResult=325 searchResult=318 +-- (searchData = 1 tag + searchType; cmpResult/searchResult = Maybe = 1 tag + value.) +-- +-- CLEAR (OQ-FSM-CF-04 / OQ-FSM-01 / OQ-FSM-06 family, RESOLVED): +-- surf.Fifo has no clear port; FIFOF.clear is modelled by a level assertion of +-- the synchronous rst (sync FifoSync re-applies REG_INIT_C every held cycle). +-- fifosRst <= rst or clearActive drives every local FIFO; the BinaryTreeFork / +-- RecursiveSearch children receive clearActive on their own clearAll port. +-- +-- CReg(2) clearReg: clear() writes port[0]; clearAll reads+clears port[1] the SAME +-- cycle (fire_when_enabled), so the registered value never persists -> the clear +-- is a pure 1-cycle level pulse == clear() this cycle. Hence clearActive = clearEn +-- and no clearReg register is carried (differs from TagVecSrv's OQ-FSM-03, where +-- method/rule use different CReg ports). +-- +-- FIDELITY NOTE: BSV cmpHalfAddr (DupReadAtomicCache.bsv:192-202) has a source +-- bug - its low-half compare reads addrB twice, so addrLowPartMatch is always +-- True. Reproduced faithfully in CacheFifoAtomic.f_secondAtomic (constant '1'). +-- +-- DEPTH NOTE: BSV mkFIFOF default depth is 2; the intermediate FIFOs here are +-- over-provisioned to depth 2**FIFO_ADDR_WIDTH_G (default 16) to match the +-- sibling BinaryTreeFork/RecursiveSearch entities. Depth does not affect +-- functional correctness under ready/valid flow control. +-- +-- dataVec is BSV mkRegU (no reset); REG_INIT_C clears it to 0 (safe - read only +-- when the matching tagVec bit is set; OQ-FSM-04 reasoning). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- CacheFifoRead : readCacheQ specialisation (ReadCacheItem, 176-bit items) +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity CacheFifoRead is + generic ( + TPD_G : time := 1 ns; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "block"); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous + pmtu : in slv(2 downto 0); -- PMTU enum (1..5); feeds firstStageFunc + -- push (insert) method : enq ReadCacheItem + pushEn : in sl; + pushData : in slv(175 downto 0); + pushReady : out sl; -- = insertQ.not_full + -- clear method + clearEn : in sl; + -- searchReq method : enq ReadCacheItem to search for + searchReqEn : in sl; + searchReqData : in slv(175 downto 0); + searchReqReady : out sl; -- = searchReqQ.not_full + -- searchResp method : Maybe#(ReadCacheItem) result (valid tag = MSB) + searchRespValid : out sl; + searchRespData : out slv(176 downto 0); + searchRespRdEn : in sl); +end entity CacheFifoRead; + +architecture rtl of CacheFifoRead is + + constant QSZ_C : positive := 16; -- MAX_QP_RD_ATOM + constant CNT_W_C : positive := 4; -- TLog(QSZ) + constant ITEM_W_C : positive := 176; -- ReadCacheItem + constant SEARCH_W_C : positive := 358; -- Tuple6 searchType + constant CMP_W_C : positive := 234; -- Tuple4 cmpResultType + constant SD_W_C : positive := 1 + SEARCH_W_C; -- 359 : Tuple2(Bool, searchType) + constant CR_W_C : positive := 1 + CMP_W_C; -- 235 : Maybe(cmpResultType) + constant SR_W_C : positive := 1 + ITEM_W_C; -- 177 : Maybe(anytype) + + -- Array signal types (one element per lane) + type SlVecType is array (0 to QSZ_C-1) of sl; + type ItemArray is array (0 to QSZ_C-1) of slv(ITEM_W_C-1 downto 0); + type SdArray is array (0 to QSZ_C-1) of slv(SD_W_C-1 downto 0); + type CrArray is array (0 to QSZ_C-1) of slv(CR_W_C-1 downto 0); + type SrArray is array (0 to QSZ_C-1) of slv(SR_W_C-1 downto 0); + + -- psnInRangeExclusive (Utils.bsv:386) ; PSN width 24, msb = bit 23 + function f_psnInRange (psn, psnStart, psnEnd : slv(23 downto 0)) return sl is + variable psnGtStart, psnLtEnd, result : sl; + begin + psnGtStart := toSl(unsigned(psnStart) < unsigned(psn)); + psnLtEnd := toSl(unsigned(psn) < unsigned(psnEnd)); + if (psnStart(23) = psnEnd(23)) then + result := psnGtStart and psnLtEnd; -- no wrap + else + result := (psnGtStart and toSl(psnStart(23) = psn(23))) or + (psnLtEnd and toSl(psn(23) = psnEnd(23))); -- wrapped + end if; + return result; + end function; + + -- firstStageFunc = buildDupReadSearchData(pmtu) (DupReadAtomicCache.bsv:552) + -- item4Search = dup (incoming), itemInQ = orig (stored) + -- ReadCacheItem layout: startPSN[175:152] endPSN[151:128] reth[127:0] + -- reth: va[127:64] rkey[63:32] dlen[31:0] + function f_firstRead (item4Search, itemInQ : slv(ITEM_W_C-1 downto 0); + pmtuI : slv(2 downto 0)) return slv is + variable psnStartExact, psnEndExact, keyMatch : sl; + begin + psnStartExact := toSl(item4Search(175 downto 152) = itemInQ(175 downto 152)); + psnEndExact := toSl(item4Search(151 downto 128) = itemInQ(151 downto 128)); + keyMatch := toSl(item4Search(63 downto 32) = itemInQ(63 downto 32)); + -- Tuple6(pmtu, psnStartExact, psnEndExact, keyMatch, dup, orig) + return pmtuI & psnStartExact & psnEndExact & keyMatch & item4Search & itemInQ; + end function; + + -- secondStageFunc = compareReadCacheItem (DupReadAtomicCache.bsv:576) + -- incl. computeReadEndAddrAndCompare (bsv:17-122) specialised by pmtu shift + function f_secondRead (searchData : slv(SEARCH_W_C-1 downto 0)) return slv is + variable pmtuV : slv(2 downto 0); + variable psnStartExact, psnEndExact, keyMatch : sl; + variable dup, orig : slv(ITEM_W_C-1 downto 0); + variable dupStartPSN, dupEndPSN : slv(23 downto 0); + variable origStartPSN, origEndPSN : slv(23 downto 0); + variable dupVaHigh, oVaHigh, dupVaLow, oVaLow : slv(31 downto 0); + variable dupDlen, origDlen : slv(31 downto 0); + variable addrHighHalfMatch, addrLowHalfMatch : sl; + variable readLenMatch, psnStartRange, psnEndRange: sl; + variable dupLastPkt, origLastPkt : slv(24 downto 0); + variable s : integer range 8 to 12; + variable cmpParts : slv(7 downto 0); + begin + pmtuV := searchData(357 downto 355); + psnStartExact := searchData(354); + psnEndExact := searchData(353); + keyMatch := searchData(352); + dup := searchData(351 downto 176); + orig := searchData(175 downto 0); + + dupStartPSN := dup(175 downto 152); dupEndPSN := dup(151 downto 128); + origStartPSN := orig(175 downto 152); origEndPSN := orig(151 downto 128); + dupVaHigh := dup(127 downto 96); dupVaLow := dup(95 downto 64); dupDlen := dup(31 downto 0); + oVaHigh := orig(127 downto 96); oVaLow := orig(95 downto 64); origDlen := orig(31 downto 0); + + addrHighHalfMatch := toSl(dupVaHigh = oVaHigh); + + -- shift = log2(pmtu payload size) : 256->8 512->9 1024->10 2048->11 4096->12 + case pmtuV is + when "001" => s := 8; + when "010" => s := 9; + when "011" => s := 10; + when "100" => s := 11; + when "101" => s := 12; + when others => s := 8; + end case; + + addrLowHalfMatch := toSl(dupVaLow(s-1 downto 0) = oVaLow(s-1 downto 0)) and + toSl(dupDlen(s-1 downto 0) = origDlen(s-1 downto 0)); + readLenMatch := toSl(unsigned(origDlen(31 downto s)) >= unsigned(dupDlen(31 downto s))); + dupLastPkt := slv(resize(unsigned(dupVaLow(31 downto s)) + unsigned(dupDlen(31 downto s)), 25)); + origLastPkt := slv(resize(unsigned(oVaLow(31 downto s)) + unsigned(origDlen(31 downto s)), 25)); + + psnStartRange := f_psnInRange(dupStartPSN, origStartPSN, origEndPSN); + psnEndRange := f_psnInRange(dupEndPSN, origStartPSN, origEndPSN); + + -- DupReadCmpParts (8 Bools, first-field-at-MSB) + cmpParts := addrHighHalfMatch & addrLowHalfMatch & keyMatch & + psnStartExact & psnStartRange & psnEndExact & psnEndRange & readLenMatch; + -- Tuple4(DupReadCmpParts, dupLastPkt, origLastPkt, origReadCacheItem) + return cmpParts & dupLastPkt & origLastPkt & orig; + end function; + + -- thirdStageFunc = checkReadCacheItemCmpResult (DupReadAtomicCache.bsv:617) + function f_thirdRead (cmpResult : slv(CMP_W_C-1 downto 0)) return slv is + variable cmpParts : slv(7 downto 0); + variable dupLastPkt, origLast : slv(24 downto 0); + variable orig : slv(ITEM_W_C-1 downto 0); + variable addrLenMatch, psnMatch, matchAll : sl; + begin + cmpParts := cmpResult(233 downto 226); + dupLastPkt := cmpResult(225 downto 201); + origLast := cmpResult(200 downto 176); + orig := cmpResult(175 downto 0); + addrLenMatch := cmpParts(7) and cmpParts(6) and cmpParts(0) and toSl(dupLastPkt = origLast); + psnMatch := (cmpParts(4) or cmpParts(3)) and (cmpParts(2) or cmpParts(1)); + matchAll := addrLenMatch and cmpParts(5) and psnMatch; -- cmpParts(5)=keyMatch + -- Maybe(ReadCacheItem): valid tag = MSB + return matchAll & orig; + end function; + + type RegType is record + dataVec : ItemArray; + tagVec : SlVecType; + enqPtrReg : slv(CNT_W_C-1 downto 0); + end record RegType; + + constant REG_INIT_C : RegType := ( + dataVec => (others => (others => '0')), -- mkRegU; init 0 (don't-care, gated by tagVec) + tagVec => (others => '0'), + enqPtrReg => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal clearActive : sl; + signal fifosRst : sl; + + -- insertQ + signal insertNotFull, insertValid, insertRdEn : sl; + signal insertDout : slv(ITEM_W_C-1 downto 0); + -- searchReqQ + signal searchReqNotFull, searchReqValid, forkPipeInRdEn : sl; + signal searchReqDout : slv(ITEM_W_C-1 downto 0); + -- BinaryTreeFork outputs (per lane) + signal forkValid : SlVecType; + signal forkDout : ItemArray; + signal forkRdEn : SlVecType; + -- searchDataVec FIFOs + signal sdWrEn, sdNotFull, sdRdEn, sdValid : SlVecType; + signal sdDin, sdDout : SdArray; + -- cmpResultVec FIFOs + signal crWrEn, crNotFull, crRdEn, crValid : SlVecType; + signal crDin, crDout : CrArray; + -- searchResultVec FIFOs + signal srWrEn, srNotFull, srRdEn, srValid : SlVecType; + signal srDin, srDout : SrArray; + +begin + + clearActive <= clearEn; -- CReg pulse reduces to combinational clear + fifosRst <= rst or clearActive; -- BSV FIFOF.clear modelled as level rst + pushReady <= insertNotFull; + searchReqReady <= searchReqNotFull; + + ---------------------------------------------------------------------------- + -- Source FIFOs + ---------------------------------------------------------------------------- + U_InsertQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => ITEM_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => pushEn, + din => pushData, + not_full => insertNotFull, + rd_clk => clk, + rd_en => insertRdEn, + dout => insertDout, + valid => insertValid); + + U_SearchReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => ITEM_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => searchReqEn, + din => searchReqData, + not_full => searchReqNotFull, + rd_clk => clk, + rd_en => forkPipeInRdEn, + dout => searchReqDout, + valid => searchReqValid); + + ---------------------------------------------------------------------------- + -- BinaryTreeFork : broadcast searchReq stream to QSZ lanes + ---------------------------------------------------------------------------- + U_SearchReqFork : entity surf.BinaryTreeFork + generic map ( + TPD_G => TPD_G, + DATA_W_G => ITEM_W_C, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + clearAll => clearActive, + pipeInValid => searchReqValid, + pipeInDout => searchReqDout, + pipeInRdEn => forkPipeInRdEn, + pipeOut0Valid => forkValid(0), pipeOut0Dout => forkDout(0), pipeOut0RdEn => forkRdEn(0), + pipeOut1Valid => forkValid(1), pipeOut1Dout => forkDout(1), pipeOut1RdEn => forkRdEn(1), + pipeOut2Valid => forkValid(2), pipeOut2Dout => forkDout(2), pipeOut2RdEn => forkRdEn(2), + pipeOut3Valid => forkValid(3), pipeOut3Dout => forkDout(3), pipeOut3RdEn => forkRdEn(3), + pipeOut4Valid => forkValid(4), pipeOut4Dout => forkDout(4), pipeOut4RdEn => forkRdEn(4), + pipeOut5Valid => forkValid(5), pipeOut5Dout => forkDout(5), pipeOut5RdEn => forkRdEn(5), + pipeOut6Valid => forkValid(6), pipeOut6Dout => forkDout(6), pipeOut6RdEn => forkRdEn(6), + pipeOut7Valid => forkValid(7), pipeOut7Dout => forkDout(7), pipeOut7RdEn => forkRdEn(7), + pipeOut8Valid => forkValid(8), pipeOut8Dout => forkDout(8), pipeOut8RdEn => forkRdEn(8), + pipeOut9Valid => forkValid(9), pipeOut9Dout => forkDout(9), pipeOut9RdEn => forkRdEn(9), + pipeOut10Valid => forkValid(10), pipeOut10Dout => forkDout(10), pipeOut10RdEn => forkRdEn(10), + pipeOut11Valid => forkValid(11), pipeOut11Dout => forkDout(11), pipeOut11RdEn => forkRdEn(11), + pipeOut12Valid => forkValid(12), pipeOut12Dout => forkDout(12), pipeOut12RdEn => forkRdEn(12), + pipeOut13Valid => forkValid(13), pipeOut13Dout => forkDout(13), pipeOut13RdEn => forkRdEn(13), + pipeOut14Valid => forkValid(14), pipeOut14Dout => forkDout(14), pipeOut14RdEn => forkRdEn(14), + pipeOut15Valid => forkValid(15), pipeOut15Dout => forkDout(15), pipeOut15RdEn => forkRdEn(15)); + + ---------------------------------------------------------------------------- + -- Per-lane pipeline FIFOs (searchData / cmpResult / searchResult) + ---------------------------------------------------------------------------- + GEN_LANE : for i in 0 to QSZ_C-1 generate + + U_SearchDataQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => SD_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => sdWrEn(i), + din => sdDin(i), + not_full => sdNotFull(i), + rd_clk => clk, + rd_en => sdRdEn(i), + dout => sdDout(i), + valid => sdValid(i)); + + U_CmpResultQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => CR_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => crWrEn(i), + din => crDin(i), + not_full => crNotFull(i), + rd_clk => clk, + rd_en => crRdEn(i), + dout => crDout(i), + valid => crValid(i)); + + U_SearchResultQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => SR_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => srWrEn(i), + din => srDin(i), + not_full => srNotFull(i), + rd_clk => clk, + rd_en => srRdEn(i), + dout => srDout(i), + valid => srValid(i)); + + end generate GEN_LANE; + + ---------------------------------------------------------------------------- + -- RecursiveSearch : reduce QSZ Maybe lanes to one left-priority winner + ---------------------------------------------------------------------------- + U_SearchResult : entity surf.RecursiveSearch + generic map ( + TPD_G => TPD_G, + ITEM_W_G => ITEM_W_C, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + clearAll => clearActive, + inputVec_0_valid => srValid(0), inputVec_0_dout => srDout(0), inputVec_0_rdEn => srRdEn(0), + inputVec_1_valid => srValid(1), inputVec_1_dout => srDout(1), inputVec_1_rdEn => srRdEn(1), + inputVec_2_valid => srValid(2), inputVec_2_dout => srDout(2), inputVec_2_rdEn => srRdEn(2), + inputVec_3_valid => srValid(3), inputVec_3_dout => srDout(3), inputVec_3_rdEn => srRdEn(3), + inputVec_4_valid => srValid(4), inputVec_4_dout => srDout(4), inputVec_4_rdEn => srRdEn(4), + inputVec_5_valid => srValid(5), inputVec_5_dout => srDout(5), inputVec_5_rdEn => srRdEn(5), + inputVec_6_valid => srValid(6), inputVec_6_dout => srDout(6), inputVec_6_rdEn => srRdEn(6), + inputVec_7_valid => srValid(7), inputVec_7_dout => srDout(7), inputVec_7_rdEn => srRdEn(7), + inputVec_8_valid => srValid(8), inputVec_8_dout => srDout(8), inputVec_8_rdEn => srRdEn(8), + inputVec_9_valid => srValid(9), inputVec_9_dout => srDout(9), inputVec_9_rdEn => srRdEn(9), + inputVec_10_valid => srValid(10), inputVec_10_dout => srDout(10), inputVec_10_rdEn => srRdEn(10), + inputVec_11_valid => srValid(11), inputVec_11_dout => srDout(11), inputVec_11_rdEn => srRdEn(11), + inputVec_12_valid => srValid(12), inputVec_12_dout => srDout(12), inputVec_12_rdEn => srRdEn(12), + inputVec_13_valid => srValid(13), inputVec_13_dout => srDout(13), inputVec_13_rdEn => srRdEn(13), + inputVec_14_valid => srValid(14), inputVec_14_dout => srDout(14), inputVec_14_rdEn => srRdEn(14), + inputVec_15_valid => srValid(15), inputVec_15_dout => srDout(15), inputVec_15_rdEn => srRdEn(15), + resultValid => searchRespValid, + resultDout => searchRespData, + resultRdEn => searchRespRdEn); + + ---------------------------------------------------------------------------- + -- Two-process FSM + ---------------------------------------------------------------------------- + comb : process (r, rst, clearEn, pmtu, insertValid, insertDout, + forkValid, forkDout, sdValid, sdDout, sdNotFull, + crValid, crDout, crNotFull, srNotFull) is + variable v : RegType; + variable enqIdx : integer range 0 to QSZ_C-1; + variable tagV : sl; + variable sDataV : slv(SEARCH_W_C-1 downto 0); + variable validBit : sl; + begin + v := r; + + -- default FIFO drives + insertRdEn <= '0'; + forkRdEn <= (others => '0'); + sdWrEn <= (others => '0'); sdRdEn <= (others => '0'); + crWrEn <= (others => '0'); crRdEn <= (others => '0'); + srWrEn <= (others => '0'); -- srRdEn is driven by U_SearchResult (RecursiveSearch); + -- the comb must NOT also drive it (would be a 2nd driver -> 'X'). + sdDin <= (others => (others => '0')); + crDin <= (others => (others => '0')); + srDin <= (others => (others => '0')); + + if (clearEn = '0') then + -- search pipeline : QSZ independent lanes (conflict-free) + for i in 0 to QSZ_C-1 loop + -- firstSearchStage[i] + if (forkValid(i) = '1') and (sdNotFull(i) = '1') then + sdDin(i) <= r.tagVec(i) & f_firstRead(forkDout(i), r.dataVec(i), pmtu); + sdWrEn(i) <= '1'; + forkRdEn(i) <= '1'; + end if; + -- secondSearchStage[i] + if (sdValid(i) = '1') and (crNotFull(i) = '1') then + tagV := sdDout(i)(SD_W_C-1); + sDataV := sdDout(i)(SD_W_C-2 downto 0); + crDin(i) <= tagV & f_secondRead(sDataV); -- Maybe: valid = tag + crWrEn(i) <= '1'; + sdRdEn(i) <= '1'; + end if; + -- thirdSearchStage[i] + if (crValid(i) = '1') and (srNotFull(i) = '1') then + validBit := crDout(i)(CR_W_C-1); + if (validBit = '1') then + srDin(i) <= f_thirdRead(crDout(i)(CR_W_C-2 downto 0)); + else + srDin(i) <= (others => '0'); -- Invalid + end if; + srWrEn(i) <= '1'; + crRdEn(i) <= '1'; + end if; + end loop; + + -- insert : circular overwrite ring (no full check) + if (insertValid = '1') then + enqIdx := to_integer(unsigned(r.enqPtrReg)); + v.dataVec(enqIdx) := insertDout; + v.tagVec(enqIdx) := '1'; + v.enqPtrReg := slv(unsigned(r.enqPtrReg) + 1); + insertRdEn <= '1'; + end if; + + else + -- clearAll : clear tags + ptr ; all FIFOs cleared via fifosRst (level) + v.tagVec := (others => '0'); + v.enqPtrReg := (others => '0'); + -- dataVec left unchanged (only tags cleared) + end if; + + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; + +------------------------------------------------------------------------------- +-- CacheFifoAtomic : atomicCacheQ specialisation (AtomicCacheItem, 317-bit items) +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity CacheFifoAtomic is + generic ( + TPD_G : time := 1 ns; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "block"); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous + -- push (insert) method : enq AtomicCacheItem + pushEn : in sl; + pushData : in slv(316 downto 0); + pushReady : out sl; + -- clear method + clearEn : in sl; + -- searchReq method + searchReqEn : in sl; + searchReqData : in slv(316 downto 0); + searchReqReady : out sl; + -- searchResp method : Maybe#(AtomicCacheItem) (valid tag = MSB) + searchRespValid : out sl; + searchRespData : out slv(317 downto 0); + searchRespRdEn : in sl); +end entity CacheFifoAtomic; + +architecture rtl of CacheFifoAtomic is + + constant QSZ_C : positive := 16; + constant CNT_W_C : positive := 4; + constant ITEM_W_C : positive := 317; -- AtomicCacheItem + constant SEARCH_W_C : positive := 637; -- Tuple5 searchType + constant CMP_W_C : positive := 324; -- Tuple2 cmpResultType + constant SD_W_C : positive := 1 + SEARCH_W_C; -- 638 + constant CR_W_C : positive := 1 + CMP_W_C; -- 325 + constant SR_W_C : positive := 1 + ITEM_W_C; -- 318 + + constant COMPARE_SWAP_C : slv(4 downto 0) := "10011"; -- RdmaOpCode 5'h13 + + type SlVecType is array (0 to QSZ_C-1) of sl; + type ItemArray is array (0 to QSZ_C-1) of slv(ITEM_W_C-1 downto 0); + type SdArray is array (0 to QSZ_C-1) of slv(SD_W_C-1 downto 0); + type CrArray is array (0 to QSZ_C-1) of slv(CR_W_C-1 downto 0); + type SrArray is array (0 to QSZ_C-1) of slv(SR_W_C-1 downto 0); + + -- AtomicCacheItem layout: atomicPSN[316:293] atomicOpCode[292:288] + -- atomicEth[287:64] (va[287:224] rkey[223:192] swap[191:128] comp[127:64]) + -- atomicAckEth[63:0] + + -- firstStageFunc = buildAtomicSearchData (DupReadAtomicCache.bsv:646) + function f_firstAtomic (item4Search, itemInQ : slv(ITEM_W_C-1 downto 0)) return slv is + variable keyMatch, opCodeMatch, psnMatch : sl; + begin + keyMatch := toSl(item4Search(223 downto 192) = itemInQ(223 downto 192)); -- atomicEth.rkey + opCodeMatch := toSl(item4Search(292 downto 288) = itemInQ(292 downto 288)); -- atomicOpCode + psnMatch := toSl(item4Search(316 downto 293) = itemInQ(316 downto 293)); -- atomicPSN + -- Tuple5(keyMatch, opCodeMatch, psnMatch, dup, orig) + return keyMatch & opCodeMatch & psnMatch & item4Search & itemInQ; + end function; + + -- secondStageFunc = compareAtomicCacheItem (DupReadAtomicCache.bsv:662) + function f_secondAtomic (searchData : slv(SEARCH_W_C-1 downto 0)) return slv is + variable keyMatch, opCodeMatch, psnMatch : sl; + variable dup, orig : slv(ITEM_W_C-1 downto 0); + variable dupVa, origVa : slv(63 downto 0); + variable addrHighPartMatch, addrLowPartMatch : sl; + variable swapMatch, compMatch : sl; + variable cmpParts : slv(6 downto 0); + begin + keyMatch := searchData(636); + opCodeMatch := searchData(635); + psnMatch := searchData(634); + dup := searchData(633 downto 317); + orig := searchData(316 downto 0); + + dupVa := dup(287 downto 224); -- atomicEth.va + origVa := orig(287 downto 224); + + -- cmpHalfAddr(dupVa, origVa) : HALF_ADDR_WIDTH=32 + addrHighPartMatch := toSl(dupVa(63 downto 32) = origVa(63 downto 32)); + -- FIDELITY: BSV cmpHalfAddr reads addrB for both low halves -> always True + addrLowPartMatch := '1'; + + swapMatch := toSl(dup(191 downto 128) = orig(191 downto 128)); -- atomicEth.swap + compMatch := toSl(dup(127 downto 64) = orig(127 downto 64)); -- atomicEth.comp + + -- DupAtomicCmpParts (7 Bools, first-field-at-MSB) + cmpParts := addrHighPartMatch & addrLowPartMatch & compMatch & + keyMatch & opCodeMatch & psnMatch & swapMatch; + -- Tuple2(DupAtomicCmpParts, origAtomicCacheItem) + return cmpParts & orig; + end function; + + -- thirdStageFunc = checkAtomicCacheItemCmpResult (DupReadAtomicCache.bsv:697) + function f_thirdAtomic (cmpResult : slv(CMP_W_C-1 downto 0)) return slv is + variable cmpParts : slv(6 downto 0); + variable orig : slv(ITEM_W_C-1 downto 0); + variable origOpCode : slv(4 downto 0); + variable payloadMatch, allMatch : sl; + begin + cmpParts := cmpResult(323 downto 317); + orig := cmpResult(316 downto 0); + origOpCode := orig(292 downto 288); + -- cmpParts: addrHighPartMatch(6) addrLowPartMatch(5) compMatch(4) + -- keyMatch(3) opCodeMatch(2) psnMatch(1) swapMatch(0) + payloadMatch := ite(origOpCode = COMPARE_SWAP_C, + cmpParts(0) and cmpParts(4), -- swap && comp + cmpParts(0)); -- swap + allMatch := cmpParts(6) and cmpParts(5) and cmpParts(3) and + payloadMatch and cmpParts(2) and cmpParts(1); + -- Maybe(AtomicCacheItem): valid tag = MSB + return allMatch & orig; + end function; + + type RegType is record + dataVec : ItemArray; + tagVec : SlVecType; + enqPtrReg : slv(CNT_W_C-1 downto 0); + end record RegType; + + constant REG_INIT_C : RegType := ( + dataVec => (others => (others => '0')), -- mkRegU; init 0 (don't-care, gated by tagVec) + tagVec => (others => '0'), + enqPtrReg => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal clearActive : sl; + signal fifosRst : sl; + + signal insertNotFull, insertValid, insertRdEn : sl; + signal insertDout : slv(ITEM_W_C-1 downto 0); + signal searchReqNotFull, searchReqValid, forkPipeInRdEn : sl; + signal searchReqDout : slv(ITEM_W_C-1 downto 0); + signal forkValid : SlVecType; + signal forkDout : ItemArray; + signal forkRdEn : SlVecType; + signal sdWrEn, sdNotFull, sdRdEn, sdValid : SlVecType; + signal sdDin, sdDout : SdArray; + signal crWrEn, crNotFull, crRdEn, crValid : SlVecType; + signal crDin, crDout : CrArray; + signal srWrEn, srNotFull, srRdEn, srValid : SlVecType; + signal srDin, srDout : SrArray; + +begin + + clearActive <= clearEn; + fifosRst <= rst or clearActive; + pushReady <= insertNotFull; + searchReqReady <= searchReqNotFull; + + U_InsertQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => ITEM_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => pushEn, + din => pushData, + not_full => insertNotFull, + rd_clk => clk, + rd_en => insertRdEn, + dout => insertDout, + valid => insertValid); + + U_SearchReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => ITEM_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => searchReqEn, + din => searchReqData, + not_full => searchReqNotFull, + rd_clk => clk, + rd_en => forkPipeInRdEn, + dout => searchReqDout, + valid => searchReqValid); + + U_SearchReqFork : entity surf.BinaryTreeFork + generic map ( + TPD_G => TPD_G, + DATA_W_G => ITEM_W_C, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + clearAll => clearActive, + pipeInValid => searchReqValid, + pipeInDout => searchReqDout, + pipeInRdEn => forkPipeInRdEn, + pipeOut0Valid => forkValid(0), pipeOut0Dout => forkDout(0), pipeOut0RdEn => forkRdEn(0), + pipeOut1Valid => forkValid(1), pipeOut1Dout => forkDout(1), pipeOut1RdEn => forkRdEn(1), + pipeOut2Valid => forkValid(2), pipeOut2Dout => forkDout(2), pipeOut2RdEn => forkRdEn(2), + pipeOut3Valid => forkValid(3), pipeOut3Dout => forkDout(3), pipeOut3RdEn => forkRdEn(3), + pipeOut4Valid => forkValid(4), pipeOut4Dout => forkDout(4), pipeOut4RdEn => forkRdEn(4), + pipeOut5Valid => forkValid(5), pipeOut5Dout => forkDout(5), pipeOut5RdEn => forkRdEn(5), + pipeOut6Valid => forkValid(6), pipeOut6Dout => forkDout(6), pipeOut6RdEn => forkRdEn(6), + pipeOut7Valid => forkValid(7), pipeOut7Dout => forkDout(7), pipeOut7RdEn => forkRdEn(7), + pipeOut8Valid => forkValid(8), pipeOut8Dout => forkDout(8), pipeOut8RdEn => forkRdEn(8), + pipeOut9Valid => forkValid(9), pipeOut9Dout => forkDout(9), pipeOut9RdEn => forkRdEn(9), + pipeOut10Valid => forkValid(10), pipeOut10Dout => forkDout(10), pipeOut10RdEn => forkRdEn(10), + pipeOut11Valid => forkValid(11), pipeOut11Dout => forkDout(11), pipeOut11RdEn => forkRdEn(11), + pipeOut12Valid => forkValid(12), pipeOut12Dout => forkDout(12), pipeOut12RdEn => forkRdEn(12), + pipeOut13Valid => forkValid(13), pipeOut13Dout => forkDout(13), pipeOut13RdEn => forkRdEn(13), + pipeOut14Valid => forkValid(14), pipeOut14Dout => forkDout(14), pipeOut14RdEn => forkRdEn(14), + pipeOut15Valid => forkValid(15), pipeOut15Dout => forkDout(15), pipeOut15RdEn => forkRdEn(15)); + + GEN_LANE : for i in 0 to QSZ_C-1 generate + + U_SearchDataQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => SD_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => sdWrEn(i), + din => sdDin(i), + not_full => sdNotFull(i), + rd_clk => clk, + rd_en => sdRdEn(i), + dout => sdDout(i), + valid => sdValid(i)); + + U_CmpResultQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => CR_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => crWrEn(i), + din => crDin(i), + not_full => crNotFull(i), + rd_clk => clk, + rd_en => crRdEn(i), + dout => crDout(i), + valid => crValid(i)); + + U_SearchResultQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => SR_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => fifosRst, + wr_clk => clk, + wr_en => srWrEn(i), + din => srDin(i), + not_full => srNotFull(i), + rd_clk => clk, + rd_en => srRdEn(i), + dout => srDout(i), + valid => srValid(i)); + + end generate GEN_LANE; + + U_SearchResult : entity surf.RecursiveSearch + generic map ( + TPD_G => TPD_G, + ITEM_W_G => ITEM_W_C, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + clearAll => clearActive, + inputVec_0_valid => srValid(0), inputVec_0_dout => srDout(0), inputVec_0_rdEn => srRdEn(0), + inputVec_1_valid => srValid(1), inputVec_1_dout => srDout(1), inputVec_1_rdEn => srRdEn(1), + inputVec_2_valid => srValid(2), inputVec_2_dout => srDout(2), inputVec_2_rdEn => srRdEn(2), + inputVec_3_valid => srValid(3), inputVec_3_dout => srDout(3), inputVec_3_rdEn => srRdEn(3), + inputVec_4_valid => srValid(4), inputVec_4_dout => srDout(4), inputVec_4_rdEn => srRdEn(4), + inputVec_5_valid => srValid(5), inputVec_5_dout => srDout(5), inputVec_5_rdEn => srRdEn(5), + inputVec_6_valid => srValid(6), inputVec_6_dout => srDout(6), inputVec_6_rdEn => srRdEn(6), + inputVec_7_valid => srValid(7), inputVec_7_dout => srDout(7), inputVec_7_rdEn => srRdEn(7), + inputVec_8_valid => srValid(8), inputVec_8_dout => srDout(8), inputVec_8_rdEn => srRdEn(8), + inputVec_9_valid => srValid(9), inputVec_9_dout => srDout(9), inputVec_9_rdEn => srRdEn(9), + inputVec_10_valid => srValid(10), inputVec_10_dout => srDout(10), inputVec_10_rdEn => srRdEn(10), + inputVec_11_valid => srValid(11), inputVec_11_dout => srDout(11), inputVec_11_rdEn => srRdEn(11), + inputVec_12_valid => srValid(12), inputVec_12_dout => srDout(12), inputVec_12_rdEn => srRdEn(12), + inputVec_13_valid => srValid(13), inputVec_13_dout => srDout(13), inputVec_13_rdEn => srRdEn(13), + inputVec_14_valid => srValid(14), inputVec_14_dout => srDout(14), inputVec_14_rdEn => srRdEn(14), + inputVec_15_valid => srValid(15), inputVec_15_dout => srDout(15), inputVec_15_rdEn => srRdEn(15), + resultValid => searchRespValid, + resultDout => searchRespData, + resultRdEn => searchRespRdEn); + + comb : process (r, rst, clearEn, insertValid, insertDout, + forkValid, forkDout, sdValid, sdDout, sdNotFull, + crValid, crDout, crNotFull, srNotFull) is + variable v : RegType; + variable enqIdx : integer range 0 to QSZ_C-1; + variable tagV : sl; + variable sDataV : slv(SEARCH_W_C-1 downto 0); + variable validBit : sl; + begin + v := r; + + insertRdEn <= '0'; + forkRdEn <= (others => '0'); + sdWrEn <= (others => '0'); sdRdEn <= (others => '0'); + crWrEn <= (others => '0'); crRdEn <= (others => '0'); + srWrEn <= (others => '0'); -- srRdEn is driven by U_SearchResult (RecursiveSearch); + -- the comb must NOT also drive it (would be a 2nd driver -> 'X'). + sdDin <= (others => (others => '0')); + crDin <= (others => (others => '0')); + srDin <= (others => (others => '0')); + + if (clearEn = '0') then + for i in 0 to QSZ_C-1 loop + if (forkValid(i) = '1') and (sdNotFull(i) = '1') then + sdDin(i) <= r.tagVec(i) & f_firstAtomic(forkDout(i), r.dataVec(i)); + sdWrEn(i) <= '1'; + forkRdEn(i) <= '1'; + end if; + if (sdValid(i) = '1') and (crNotFull(i) = '1') then + tagV := sdDout(i)(SD_W_C-1); + sDataV := sdDout(i)(SD_W_C-2 downto 0); + crDin(i) <= tagV & f_secondAtomic(sDataV); + crWrEn(i) <= '1'; + sdRdEn(i) <= '1'; + end if; + if (crValid(i) = '1') and (srNotFull(i) = '1') then + validBit := crDout(i)(CR_W_C-1); + if (validBit = '1') then + srDin(i) <= f_thirdAtomic(crDout(i)(CR_W_C-2 downto 0)); + else + srDin(i) <= (others => '0'); + end if; + srWrEn(i) <= '1'; + crRdEn(i) <= '1'; + end if; + end loop; + + if (insertValid = '1') then + enqIdx := to_integer(unsigned(r.enqPtrReg)); + v.dataVec(enqIdx) := insertDout; + v.tagVec(enqIdx) := '1'; + v.enqPtrReg := slv(unsigned(r.enqPtrReg) + 1); + insertRdEn <= '1'; + end if; + + else + v.tagVec := (others => '0'); + v.enqPtrReg := (others => '0'); + end if; + + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ClientArbiter.vhd b/ethernet/RoCEv2/rtl/ClientArbiter.vhd new file mode 100644 index 0000000000..c204b0f455 --- /dev/null +++ b/ethernet/RoCEv2/rtl/ClientArbiter.vhd @@ -0,0 +1,503 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Dual of mkServerArbiter. Multiplexes PORT_COUNT_G upstream *client* request +-- streams onto ONE downstream client face, tagging each request with its +-- origin port index so the matching response is routed back to that port. +-- ClientArbiter is the MASTER of each clientVec[k]: it *gets* requests from +-- client k and *puts* responses to client k. The single returned Client +-- (toGPClient(reqQ, respQ)) is the shared downstream resource this arbiter +-- feeds. +-- +-- BSV owns ONE register (shouldSaveGrantIdxReg), PORT_COUNT_G+2 rules +-- (extractReq[k] ×portSz, issueArbitratedReq, dispatchResponse), four FIFO +-- groups (inputReqWithIdxVec[k], reqQ, respQ, preGrantIdxQ) and the arbitration +-- tree (mkLeafBinaryPipeOutArbiterVec -> mkBinaryPipeOutArbiterTree). This is a +-- 1-flag flow-control wrapper around the arbitration tree — no multi-state +-- enum; shouldSaveGrantIdxReg is a burst-boundary flag ('1' => next issued +-- request starts a new burst -> record its grant index in preGrantIdxQ). +-- +-- OQ-FSM-CLTARB-01 (RESOLVED — inventory/partition mis-model this entity): +-- ClientArbiter.fsm.md (built from source) is AUTHORITATIVE: the child is +-- the arbitration tree = PipeOutArbiter (NOT ServerArbiter), and the owned +-- FSM/FIFOs are emitted here. +-- +-- OQ-FSM-PERMARB-01 (RESOLVED — generic re-emit, supersedes the fixed-4 emit): +-- every concrete specialization (mkPermCheckCltArbiter, mkDmaReadCltArbiter, +-- mkDmaWriteCltArbiter, instantiated in TransportLayer.bsv over +-- qpPermCheckSrvVec / qpDmaReadCltVec / qpDmaWriteCltVec) uses +-- portSz = TMul#(2, MAX_QP) = 8 (one RQ-side + one SQ-side client per QP), +-- NOT MAX_QP = 4 as the inventory previously claimed. This entity is +-- therefore emitted GENERIC over PORT_COUNT_G (any power of 2, >= 2; +-- derived IDX_WIDTH_C = log2(PORT_COUNT_G)) with vectored/flattened +-- per-client ports built by generate statements, and the wrappers +-- instantiate it with PORT_COUNT_G => 2*MAX_QP_G = 8 (idxW = 3, full +-- 8-input tree: 4 leaf + 2 mid + 1 top BinaryPipeOutArbiters, 3 levels). +-- The power-of-2 proviso and the FFT bit-reverse leaf permutation live in +-- the child tree (BinaryArbTree, via PipeOutArbiter); a matching local +-- assert below fails elaboration early with a ClientArbiter-specific +-- message. +-- +-- OQ-FSM-17 (predicate handling) — cltReqFinished / outRespFinished input +-- ports: BSV isReqFinished / isRespFinished are elaboration-time function +-- arguments; VHDL has no function-type ports, so the parent (where the concrete +-- type is known) computes them and feeds them as 1-bit combinational inputs. +-- Concrete values are trivial (PermCheck req+resp both constant True -> tie '1'; +-- DmaRead isRespFinished = resp.dataStream.isLast; DmaWrite isReqFinished = +-- req.dataStream.isLast). Because each predicate is a PURE function of its +-- payload, the bit is sampled at ENQUEUE and carried as a companion THROUGH the +-- relevant FIFO (same established resolution as ServerArbiter): +-- * REQUEST predicate cltReqFinished(k) -> stored top bit of U_InReqQ(k) +-- element {finished, idx, req}; the arbiter's per-channel inFinished(k) +-- input reads that stored bit, and its outFinished companion == +-- isReqFinished of the arbitrated request, which drives +-- shouldSaveGrantIdxReg. +-- * RESPONSE predicate outRespFinished -> stored top bit of U_RespQ element +-- {finished, resp}; dispatchResponse reads it as respFinished (release the +-- grant index only at response-burst end). +-- +-- Payload layout (BSV pack(tuple2(reqIdx, inputReq)) = {reqIdx, inputReq}, +-- reqIdx in the HIGH bits): +-- arbiter payload width = IDX_WIDTH_C + REQ_WIDTH_G (= REQIDX_WIDTH_C) +-- inputReq = arbDout(REQ_WIDTH_G-1 downto 0) +-- reqIdx = arbDout(REQIDX_WIDTH_C-1 downto REQ_WIDTH_G) +-- In extractReq[k], din = {cltReqFinished(k), idx=const k, req slice k}, idx +-- in the HIGH-of-payload bits (below the finished companion), req in the low +-- bits. Per-client flattened buses: client k's request payload is +-- cltReqData((k+1)*REQ_WIDTH_G-1 downto k*REQ_WIDTH_G), and likewise for +-- cltRespData with RESP_WIDTH_G. +-- +-- Rules & scheduling (ClientArbiter.fsm.md): +-- * extractReq[k] (×PORT_COUNT_G) — mutually independent (disjoint ports); +-- each is pure combinational interface wiring: on cltReqValid(k) & room, +-- get client k's request and enqueue {finished,k,req} into U_InReqQ(k). +-- Emitted as a generate of continuous assignments. +-- * issueArbitratedReq vs dispatchResponse — disjoint registers, different +-- ports of preGrantIdxQ (issue -> enq, dispatch -> first/deq); conflict-free, +-- both may fire the same cycle. Emitted as two independent `if ...FiresEn` +-- blocks, no priority. +-- issueArbitratedReq guard : arbNotEmpty AND U_ReqQ.notFull +-- AND ((NOT shouldSave) OR preGrantNotFull) +-- -- preGrantIdxQ.enq is CONDITIONAL on shouldSaveGrantIdxReg, so the +-- rule may fire when the flag is '0' even if preGrantIdxQ is full +-- (BSV conditional-method implicit condition). MUST NOT gate issue +-- unconditionally on notFull. +-- dispatchResponse guard : preGrantNotEmpty AND U_RespQ.notEmpty +-- AND cltRespReady(preGrantIdx) +-- -- the response put targets clientVec[preGrantIdx], so the readiness +-- term is the SELECTED client's cltRespReady bit (indexed by +-- preGrantIdx), NOT all-ports-ready. +-- +-- Mealy: all strobes/data are combinational functions of FIFO/handshake status, +-- arbDout and r.shouldSaveGrantIdxReg. Only shouldSaveGrantIdxReg is registered. +-- Data persistence lives in the surf.Fifo instances, not FSM regs. +-- +-- Child entity instantiated: +-- * U_ReqArb : work.PipeOutArbiter (generic vectored tree = BinaryArbTree, +-- PORT_COUNT_G forwarded; PORT_COUNT_G-1 BinaryPipeOutArbiters) +-- source: out/04-vhdl/PipeOutArbiter.vhd +-- +-- SURF components instantiated (all BSV mkFIFOF -> surf.Fifo): +-- * GEN_PORT(k).U_InReqQ : surf.Fifo <- inputReqWithIdxVec[k] ({finished,idx,req}) +-- * U_ReqQ : surf.Fifo <- reqQ (reqType, downstream) +-- * U_RespQ : surf.Fifo <- respQ ({finished,resp}) +-- * U_PreGrantQ : surf.Fifo <- preGrantIdxQ (Bit#(idxW)) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- FWFT_EN_G => true so `valid` = head-present = BSV notEmpty. BSV mkFIFOF is +-- depth 2; surf.Fifo minimum ADDR_WIDTH is 4 (depth 16). Functionally a +-- buffering FIFO; depth differs and there is an inherent ~1-cycle write->valid +-- read latency vs BSV mkFIFOF — functionally equivalent, NOT cycle-accurate. +-- +-- NOTE: emitting does not prove equivalence — simulate this entity against +-- the BSV behaviour before trusting it. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ClientArbiter is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + PORT_COUNT_G : positive := 8; -- upstream client ports; any power of 2, >= 2 (OQ-FSM-PERMARB-01); concrete BSV use = 2*MAX_QP = 8 + REQ_WIDTH_G : positive := 8; -- Bits#(reqType) + RESP_WIDTH_G : positive := 8; -- Bits#(respType) + MEMORY_TYPE_G : string := "distributed"; -- FIFO RAM style + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- FIFO depth = 2**ADDR (BSV mkFIFOF depth 2; SURF min 4) + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- Per-port upstream client faces (clientVec[k], k = 0..PORT_COUNT_G-1; + -- arbiter is master). Client k's payload slice is + -- ((k+1)*WIDTH-1 downto k*WIDTH) of the flattened data buses. + cltReqValid : in slv(PORT_COUNT_G-1 downto 0); -- client k request available (request.get implicit cond) + cltReqData : in slv(PORT_COUNT_G*REQ_WIDTH_G-1 downto 0); -- client k request payload, flattened + cltReqFinished : in slv(PORT_COUNT_G-1 downto 0); -- isReqFinished(cltReqData slice k) (OQ-FSM-17), sampled at enqueue + cltReqGet : out slv(PORT_COUNT_G-1 downto 0); -- ClientArbiter takes client k's request (request.get fired) + cltRespValid : out slv(PORT_COUNT_G-1 downto 0); -- ClientArbiter drives a response to client k (response.put fired; one-hot on preGrantIdx) + cltRespData : out slv(PORT_COUNT_G*RESP_WIDTH_G-1 downto 0); -- response payload (respQ.first broadcast to every slice; cltRespValid selects the port) + cltRespReady : in slv(PORT_COUNT_G-1 downto 0); -- client k can accept a response (response.put ready) + -- Downstream shared Client face (toGPClient(reqQ, respQ)) + outReqValid : out sl; -- request.first valid (U_ReqQ notEmpty) + outReqData : out slv(REQ_WIDTH_G-1 downto 0); -- request.first (U_ReqQ dout) + outReqRd : in sl; -- downstream request.get (U_ReqQ deq) + outRespValid : in sl; -- downstream response.put fired + outRespData : in slv(RESP_WIDTH_G-1 downto 0); -- response payload from downstream + outRespFinished : in sl; -- isRespFinished(outRespData) (OQ-FSM-17), sampled at enqueue + outRespReady : out sl); -- response can accept a put (U_RespQ notFull) +end entity ClientArbiter; + +architecture rtl of ClientArbiter is + + -- idxW = TLog#(PORT_COUNT_G); for the concrete PORT_COUNT_G=8 -> 3 + -- (OQ-FSM-PERMARB-01). + constant IDX_WIDTH_C : positive := log2(PORT_COUNT_G); + -- Arbiter payload = {reqIdx, inputReq} (reqIdx in the HIGH bits). + constant REQIDX_WIDTH_C : positive := IDX_WIDTH_C + REQ_WIDTH_G; + -- Per-port input FIFO element = {finished, idx, req}. + constant INREQ_WIDTH_C : positive := 1 + REQIDX_WIDTH_C; + -- Downstream response FIFO element = {finished, resp}. + constant RESPQ_WIDTH_C : positive := 1 + RESP_WIDTH_G; + + -- Only registered state (BSV mkReg(True)). Burst-boundary flag, not a state + -- selector: '1' => next issued request starts a new burst (record its grant + -- index in preGrantIdxQ); '0' => mid-burst continuation (index already saved). + type RegType is record + shouldSaveGrantIdxReg : sl; + end record RegType; + + constant REG_INIT_C : RegType := ( + shouldSaveGrantIdxReg => '1'); -- BSV mkReg(True) + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- GEN_PORT(k).U_InReqQ (surf.Fifo, element {finished,idx,req}) status/handshake. + type InReqDoutArrayType is array (natural range <>) of slv(INREQ_WIDTH_C-1 downto 0); + signal inReqQNotFull : slv(PORT_COUNT_G-1 downto 0); + signal inReqQValid : slv(PORT_COUNT_G-1 downto 0); + signal inReqQDout : InReqDoutArrayType(PORT_COUNT_G-1 downto 0); + signal inReqQWrEn : slv(PORT_COUNT_G-1 downto 0); + signal inReqQDin : InReqDoutArrayType(PORT_COUNT_G-1 downto 0); + signal inReqQRd : slv(PORT_COUNT_G-1 downto 0); + + -- U_ReqArb (PipeOutArbiter) vectored inputs (flattened) + arbitrated PipeOut + -- output. + signal arbInDout : slv(PORT_COUNT_G*REQIDX_WIDTH_C-1 downto 0); + signal arbInFinished : slv(PORT_COUNT_G-1 downto 0); + signal arbNotEmpty : sl; + signal arbDout : slv(REQIDX_WIDTH_C-1 downto 0); -- {reqIdx, inputReq} + signal arbFinished : sl; -- isReqFinished(inputReq), buffered head bit + signal arbDeq : sl; + + -- U_ReqQ (surf.Fifo, element reqType) — downstream request queue. + signal reqQNotFull : sl; + signal reqQNotEmpty : sl; + signal reqQDout : slv(REQ_WIDTH_G-1 downto 0); + signal reqQWrEn : sl; + signal reqQDin : slv(REQ_WIDTH_G-1 downto 0); + signal reqQRd : sl; + + -- U_RespQ (surf.Fifo, element {finished,resp}) — downstream response queue. + signal respQNotFull : sl; + signal respQNotEmpty : sl; + signal respQDout : slv(RESPQ_WIDTH_C-1 downto 0); + signal respQWrEn : sl; + signal respQDin : slv(RESPQ_WIDTH_C-1 downto 0); + signal respQRd : sl; + + -- U_PreGrantQ (surf.Fifo, element Bit#(idxW)) status/handshake. + signal preGrantNotFull : sl; + signal preGrantNotEmpty : sl; + signal preGrantDout : slv(IDX_WIDTH_C-1 downto 0); + signal preGrantWrEn : sl; + signal preGrantDin : slv(IDX_WIDTH_C-1 downto 0); + signal preGrantRdEn : sl; + +begin + + -- BSV power-of-2 proviso (OQ-FSM-PERMARB-01). The child tree + -- (PipeOutArbiter -> BinaryArbTree) carries the same guard; this local copy + -- names the offending entity when a wrapper mis-parameterizes. + assert isPowerOf2(PORT_COUNT_G) and (PORT_COUNT_G >= 2) + report "ClientArbiter: PORT_COUNT_G must be a power of 2 and >= 2 " & + "(BSV arbitration-tree proviso; OQ-FSM-PERMARB-01)" + severity failure; + + -------------------------------------------------------------------------- + -- Per-port request input FIFOs (BSV inputReqWithIdxVec[k] = mkFIFOF) and + -- rule extractReq[k] : pure interface wiring of clientVec[k].request.get. + -- On cltReqValid(k) & not_full: get client k's request (cltReqGet(k) + -- strobe) and enqueue {cltReqFinished(k), idx=const k, req slice k}. Read + -- side feeds the arbiter's input channel k. + -------------------------------------------------------------------------- + GEN_PORT : for k in 0 to PORT_COUNT_G-1 generate + + U_InReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => INREQ_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => inReqQWrEn(k), + din => inReqQDin(k), + not_full => inReqQNotFull(k), + rd_clk => clk, + rd_en => inReqQRd(k), + dout => inReqQDout(k), + valid => inReqQValid(k)); + + -- rule extractReq[k]: independent, pure combinational interface wiring. + -- Element = {finished, idx=const k, req}; idx in the HIGH-of-payload bits + -- (below the finished companion), req in the low bits. + cltReqGet(k) <= cltReqValid(k) and inReqQNotFull(k); + inReqQWrEn(k) <= cltReqValid(k) and inReqQNotFull(k); + inReqQDin(k) <= cltReqFinished(k) & toSlv(k, IDX_WIDTH_C) & + cltReqData((k+1)*REQ_WIDTH_G-1 downto k*REQ_WIDTH_G); + + -- Arbiter input channel k <- U_InReqQ(k) head; the stored finished + -- companion (top element bit) is the per-channel finish predicate + -- (OQ-FSM-17). + arbInDout((k+1)*REQIDX_WIDTH_C-1 downto k*REQIDX_WIDTH_C) <= + inReqQDout(k)(REQIDX_WIDTH_C-1 downto 0); + arbInFinished(k) <= inReqQDout(k)(REQIDX_WIDTH_C); + + -- Response payload broadcast (cltRespValid selects the port). + cltRespData((k+1)*RESP_WIDTH_G-1 downto k*RESP_WIDTH_G) <= + respQDout(RESP_WIDTH_G-1 downto 0); + + end generate GEN_PORT; + + -------------------------------------------------------------------------- + -- U_ReqArb : generic arbitration tree (mkLeafBinaryPipeOutArbiterVec + + -- mkBinaryPipeOutArbiterTree = PipeOutArbiter -> BinaryArbTree, + -- PORT_COUNT_G-1 BinaryPipeOutArbiters, bit-reversed leaf pairing). Its + -- PORT_COUNT_G PipeOut inputs are the input request FIFO heads; its + -- outFinished companion = isReqFinished(inputReq) drives + -- shouldSaveGrantIdxReg. + -------------------------------------------------------------------------- + U_ReqArb : entity surf.PipeOutArbiter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PORT_COUNT_G => PORT_COUNT_G, + DATA_WIDTH_G => REQIDX_WIDTH_C, -- payload = {idx, req} + MEMORY_TYPE_G => MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + clk => clk, + rst => rst, + inValid => inReqQValid, + inDout => arbInDout, + inFinished => arbInFinished, + inRd => inReqQRd, + outNotEmpty => arbNotEmpty, + outDout => arbDout, + outFinished => arbFinished, + outDeq => arbDeq); + + -------------------------------------------------------------------------- + -- U_ReqQ : BSV reqQ (mkFIFOF reqType). Written by issueArbitratedReq; read + -- side = pure interface wiring of the downstream Client request (toGet). + -------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => REQ_WIDTH_G, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => reqQWrEn, + din => reqQDin, + not_full => reqQNotFull, + rd_clk => clk, + rd_en => reqQRd, + dout => reqQDout, + valid => reqQNotEmpty); + + -- Downstream request face (toGet(reqQ)): expose FIFO head; deq on request.get. + outReqValid <= reqQNotEmpty; + outReqData <= reqQDout; + reqQRd <= outReqRd; + + -------------------------------------------------------------------------- + -- U_RespQ : BSV respQ (mkFIFOF respType). Write side = pure interface wiring + -- of the downstream Client response (toPut): on outRespValid & not_full, + -- enqueue {outRespFinished, outRespData}. Read side feeds dispatchResponse. + -- The finished companion is sampled at enqueue (OQ-FSM-17). + -------------------------------------------------------------------------- + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => RESPQ_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => respQWrEn, + din => respQDin, + not_full => respQNotFull, + rd_clk => clk, + rd_en => respQRd, + dout => respQDout, + valid => respQNotEmpty); + + -- Downstream response face (toPut(respQ)): accept a put when not_full. + outRespReady <= respQNotFull; + respQWrEn <= outRespValid and respQNotFull; + respQDin <= outRespFinished & outRespData; + + -------------------------------------------------------------------------- + -- U_PreGrantQ : BSV preGrantIdxQ (mkFIFOF Bit#(idxW)). Written by + -- issueArbitratedReq (conditional on shouldSaveGrantIdxReg), read by + -- dispatchResponse (first each cycle; deq only at response-burst end). + -------------------------------------------------------------------------- + U_PreGrantQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => IDX_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => preGrantWrEn, + din => preGrantDin, + not_full => preGrantNotFull, + rd_clk => clk, + rd_en => preGrantRdEn, + dout => preGrantDout, + valid => preGrantNotEmpty); + + -------------------------------------------------------------------------- + -- Combinatorial : the always-enabled BSV rules issueArbitratedReq and + -- dispatchResponse. Conflict-free -> two independent `if ...FiresEn` blocks. + -- (extractReq[k] are emitted above inside GEN_PORT as continuous + -- assignments.) See ClientArbiter.fsm.md transition table. + -------------------------------------------------------------------------- + comb : process (r, rst, arbNotEmpty, arbDout, arbFinished, reqQNotFull, + preGrantNotEmpty, preGrantNotFull, preGrantDout, + respQNotEmpty, respQDout, cltRespReady) is + variable v : RegType; + variable inputReq : slv(REQ_WIDTH_G-1 downto 0); + variable reqIdx : slv(IDX_WIDTH_C-1 downto 0); + variable issueFiresEn : sl; + variable respFinished : sl; + variable preGrantIdx : natural range 0 to PORT_COUNT_G-1; + variable selRespReady : sl; + variable dispatchFiresEn : sl; + begin + -- Latch current state + v := r; + + -- Default Mealy outputs / strobes (no rule firing). + arbDeq <= '0'; + reqQWrEn <= '0'; + reqQDin <= (others => '0'); + preGrantWrEn <= '0'; + preGrantDin <= (others => '0'); + preGrantRdEn <= '0'; + respQRd <= '0'; + cltRespValid <= (others => '0'); + + ---------------------------------------------------------------------- + -- rule issueArbitratedReq + -- {reqIdx, inputReq} = arbDout; reqIdx in the HIGH bits. + -- enq to preGrantIdxQ is CONDITIONAL on shouldSaveGrantIdxReg, so the + -- rule may fire when the flag is '0' even if preGrantIdxQ is full. + ---------------------------------------------------------------------- + inputReq := arbDout(REQ_WIDTH_G-1 downto 0); + reqIdx := arbDout(REQIDX_WIDTH_C-1 downto REQ_WIDTH_G); + + issueFiresEn := arbNotEmpty and reqQNotFull and + ((not r.shouldSaveGrantIdxReg) or preGrantNotFull); + + if (issueFiresEn = '1') then + arbDeq <= '1'; -- dequeue arbitrated request + reqQWrEn <= '1'; -- reqQ.enq(inputReq) (downstream) + reqQDin <= inputReq; + preGrantWrEn <= r.shouldSaveGrantIdxReg; -- conditional preGrantIdxQ.enq + preGrantDin <= reqIdx; + -- next burst-start = this request was the last of its burst + v.shouldSaveGrantIdxReg := arbFinished; -- = isReqFinished(inputReq) + end if; + + ---------------------------------------------------------------------- + -- rule dispatchResponse + -- route respQ.first to clientVec[preGrantIdx].response.put; release the + -- grant index only at response-burst end (respFinished). Readiness term + -- is the SELECTED client's cltRespReady bit (indexed by preGrantIdx). + -- (Response DATA is broadcast to every port slice inside GEN_PORT; + -- cltRespValid selects the port.) + ---------------------------------------------------------------------- + respFinished := respQDout(RESP_WIDTH_G); -- stored finished companion + preGrantIdx := to_integer(unsigned(preGrantDout)); + selRespReady := cltRespReady(preGrantIdx); -- cltRespReady(preGrantIdx) + + dispatchFiresEn := preGrantNotEmpty and respQNotEmpty and selRespReady; + + if (dispatchFiresEn = '1') then + respQRd <= '1'; -- deq respQ + preGrantRdEn <= respFinished; -- deq preGrantIdxQ at burst end + cltRespValid(preGrantIdx) <= '1'; -- response.put to selected client + end if; + + -- Synchronous reset + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + end process comb; + + -------------------------------------------------------------------------- + -- Sequential + -------------------------------------------------------------------------- + seq : process (clk, rst) is + begin + if (RST_ASYNC_G) and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/CntrlQp.vhd b/ethernet/RoCEv2/rtl/CntrlQp.vhd new file mode 100644 index 0000000000..eede1aab14 --- /dev/null +++ b/ethernet/RoCEv2/rtl/CntrlQp.vhd @@ -0,0 +1,851 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Purpose: Per-QueuePair IB modify-state controller. The single control FSM is +-- the QP state machine (stateReg/StateQP). Seven mutually-exclusive +-- on* rules service one request from reqQ, emit a response into respQ, +-- latch QP attributes and propose a next state; rule canonicalize is +-- the single point that commits stateReg (with a setStateErr override). +-- +-- SURF components instantiated (read from /home/fmarini/sink/surf/base/fifo/rtl/Fifo.vhd): +-- U_ReqQ : surf.Fifo (reqQ, ReqQP = 301 bits) +-- U_RespQ : surf.Fifo (respQ, RespQP = 274 bits) +-- U_RestoreQ : surf.Fifo (restoreQ, {RdmaOpCode,PSN} = 29 bits) +-- +-- Struct bit packing: BSV deriving(Bits) packs the FIRST field at the MSBs +-- (the project-wide convention confirmed in OQ-FSM-16 / RESOLVED.md, already +-- shipped in ConnectionWithAction.vhd). All field-position constants below +-- follow that rule. Widths are all traced from DataTypes.bsv/Headers.bsv/ +-- Settings.bsv (CLAUDE.md: never invent widths). +-- +-- Deferred-decision carry-forwards applied: +-- * OQ-FSM-CntrlQP-01 : RegType field list/widths taken from the FSM spec, +-- NOT mapping.json owns.state (stale/abbreviated). +-- * OQ-FSM-CntrlQP-02 : immFail (DESTROY in non-ERR / default) is a sim-only +-- fatal -> emitted as translate_off asserts; in synth +-- the request is consumed and the rule's response is +-- enqueued, no state transition. +-- * OQ-FSM-CntrlQP-03 : ~26 mkRegU/mkCRegU fields have no BSV reset; per the +-- spec they are written-before-read, initialised to 0 +-- in REG_INIT_C (safe). errFlushDone init '0'. +-- * OQ-FSM-01/06 : BSV FIFOF.clear modelled by pulsing the (sync) Fifo +-- rst; only restoreQ is cleared (RESET_S scrub, level). +-- reqQ/respQ are never cleared (BSV clear was disabled). +-- +-- Port modelling: ReqQP/RespQP cross the entity boundary as packed slv words +-- (the parent packs/unpacks); restorePort and the ~50 status/getter/setter +-- methods are exploded into explicit ports. All inited-guarded methods share +-- one inited_o ready output (their BSV implicit RDY == inited); setter writes +-- are gated internally by inited so an out-of-state assert is ignored. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity CntrlQp is + generic ( + TPD_G : time := 1 ns); + port ( + -- Clock and synchronous active-high reset + clk : in sl; + rst : in sl; + + -- srvPort = toGPServer(reqQ, respQ): request.put (in) / response.get (out) + srvReqValid : in sl; -- request.put valid + srvReqData : in slv(300 downto 0); -- ReqQP packed + srvReqReady : out sl; -- = reqQ.not_full + srvRespValid : out sl; -- = respQ.valid + srvRespData : out slv(273 downto 0); -- RespQP packed + srvRespReady : in sl; -- response.get rdEn + + -- restorePort = restorePreReqOpCodeAndEPSN(preOpCode, psn) -> restoreQ.enq + restoreValid : in sl; + restorePreOpCode : in slv(4 downto 0); -- RdmaOpCode + restoreEpsn : in slv(23 downto 0); -- PSN + restoreReady : out sl; -- = restoreQ.not_full + + -- Error-state control methods (guarded by inited) + setStateErr : in sl; -- setStateErr() + errFlushDoneIn : in sl; -- errFlushDone() + + -- Shared ready: every inited-guarded getter/setter is valid when '1' + inited : out sl; + + ---------------------------------------------------------------------------- + -- CntrlCommStatus (comm) status decodes of stateReg (Moore) + ---------------------------------------------------------------------------- + isCreate : out sl; + isErr : out sl; + isInit : out sl; + isNonErr : out sl; + isReset : out sl; + isRTR : out sl; + isRTS : out sl; + isSQD : out sl; + isUnknown : out sl; + isRTR2RTS : out sl; + isStableRTS : out sl; + + -- CntrlCommStatus getters (valid when inited, except where noted) + getAccessFlags : out slv(7 downto 0); -- FlagsType#(MemAccessTypeFlag) + getMaxRnrCnt : out slv(2 downto 0); -- RetryCnt + getMaxRetryCnt : out slv(2 downto 0); -- RetryCnt + getMaxTimeOut : out slv(4 downto 0); -- TimeOutTimer + getMinRnrTimer : out slv(4 downto 0); -- RnrTimer + getPendingWorkReqNum : out slv(7 downto 0); -- PendingReqCnt + getPendingRecvReqNum : out slv(7 downto 0); + getPendingReadAtomicReqNum : out slv(7 downto 0); + getPendingDestReadAtomicReqNum : out slv(7 downto 0); + getSigAll : out sl; + getSQPN : out slv(23 downto 0); -- QPN + getDQPN : out slv(23 downto 0); + getPKEY : out slv(15 downto 0); -- PKEY + getQKEY : out slv(31 downto 0); -- QKEY + getPMTU : out slv(2 downto 0); -- PMTU + + -- statusSQ / statusRQ: getTypeQP differs per context (sq vs rq) + getTypeSq : out slv(3 downto 0); -- TypeQP (statusSQ) + getTypeRq : out slv(3 downto 0); -- TypeQP (statusRQ) + + ---------------------------------------------------------------------------- + -- ContextSQ + ---------------------------------------------------------------------------- + getNPSN : out slv(23 downto 0); -- PSN + setNPSNen : in sl; + setNPSN : in slv(23 downto 0); + + ---------------------------------------------------------------------------- + -- ContextRQ getters/setters + ---------------------------------------------------------------------------- + getPermCheckReq : out slv(266 downto 0); -- PermCheckReq (opaque) + setPermCheckReqEn : in sl; + setPermCheckReq : in slv(266 downto 0); + getTotalDmaWriteLen : out slv(31 downto 0); -- Length + setTotalDmaWriteLenEn : in sl; + setTotalDmaWriteLen : in slv(31 downto 0); + getRemainingDmaWriteLen : out slv(31 downto 0); + setRemainingDmaWriteLenEn : in sl; + setRemainingDmaWriteLen : in slv(31 downto 0); + getNextDmaWriteAddr : out slv(63 downto 0); -- ADDR + setNextDmaWriteAddrEn : in sl; + setNextDmaWriteAddr : in slv(63 downto 0); + getSendWriteReqPktNum : out slv(24 downto 0); -- PktNum + setSendWriteReqPktNumEn : in sl; + setSendWriteReqPktNum : in slv(24 downto 0); + getPreReqOpCode : out slv(4 downto 0); -- RdmaOpCode + setPreReqOpCodeEn : in sl; + setPreReqOpCode : in slv(4 downto 0); + getEpoch : out sl; -- Epoch (no inited guard) + incEpochEn : in sl; + getMSN : out slv(23 downto 0); -- MSN + setMSNen : in sl; + setMSN : in slv(23 downto 0); + getIsRespPktNumZero : out sl; + getRespPktNum : out slv(24 downto 0); -- PktNum + setRespPktNumEn : in sl; + setRespPktNum : in slv(24 downto 0); + getCurRespPSN : out slv(23 downto 0); -- PSN + setCurRespPSNen : in sl; + setCurRespPSN : in slv(23 downto 0); + getEPSN : out slv(23 downto 0); -- PSN + setEPSNen : in sl; + setEPSN : in slv(23 downto 0)); +end entity CntrlQp; + +architecture rtl of CntrlQp is + + --------------------------------------------------------------------------- + -- Width constants (traced from BSV types) + --------------------------------------------------------------------------- + constant REQ_WIDTH_C : positive := 301; -- ReqQP + constant RESP_WIDTH_C : positive := 274; -- RespQP + constant PERM_WIDTH_C : positive := 267; -- PermCheckReq (opaque scratch) + + --------------------------------------------------------------------------- + -- StateQP encoding (4 bits, BSV enum declaration order) + --------------------------------------------------------------------------- + subtype StateType is slv(3 downto 0); + constant RESET_S : StateType := x"0"; -- IBV_QPS_RESET + constant INIT_S : StateType := x"1"; -- IBV_QPS_INIT + constant RTR_S : StateType := x"2"; -- IBV_QPS_RTR + constant RTS_S : StateType := x"3"; -- IBV_QPS_RTS + constant SQD_S : StateType := x"4"; -- IBV_QPS_SQD + constant SQE_S : StateType := x"5"; -- IBV_QPS_SQE (dead/decode-only) + constant ERR_S : StateType := x"6"; -- IBV_QPS_ERR + constant UNKNOWN_S : StateType := x"7"; -- IBV_QPS_UNKNOWN + constant CREATE_S : StateType := x"8"; -- IBV_QPS_CREATE + + -- QpReqType encoding (2 bits, BSV enum declaration order) + constant REQ_QP_CREATE_C : slv(1 downto 0) := "00"; + constant REQ_QP_DESTROY_C : slv(1 downto 0) := "01"; + constant REQ_QP_MODIFY_C : slv(1 downto 0) := "10"; + constant REQ_QP_QUERY_C : slv(1 downto 0) := "11"; + + -- TypeQP encoding (4 bits, explicit BSV values) -- only XRC values used here + constant IBV_QPT_XRC_SEND_C : slv(3 downto 0) := x"9"; -- 9 + constant IBV_QPT_XRC_RECV_C : slv(3 downto 0) := x"A"; -- 10 + + -- RdmaOpCode SEND_ONLY = 5'h04 (preReqOpCode reset) + constant SEND_ONLY_C : slv(4 downto 0) := "00100"; + + -- MAX_QP_WR = 32 (pendingWorkReqNum/pendingRecvReqNum reset) + constant MAX_QP_WR_C : slv(7 downto 0) := toSlv(32, 8); + + --------------------------------------------------------------------------- + -- containFlags(mask, required) == (mask and required) = required + -- QpAttrMaskFlag is FlagsType#(...) = 26 bits; enum values are bit weights. + -- IBV_QP_STATE=bit0 ACCESS_FLAGS=bit3 PKEY_INDEX=bit4 PATH_MTU=bit8 + -- TIMEOUT=bit9 RETRY_CNT=bit10 RNR_RETRY=bit11 RQ_PSN=bit12 + -- MAX_QP_RD_ATOMIC=bit13 MIN_RNR_TIMER=bit15 SQ_PSN=bit16 + -- MAX_DEST_RD_ATOMIC=bit17 DEST_QPN=bit20 + --------------------------------------------------------------------------- + constant MASK_RESET2INIT_C : slv(25 downto 0) := toSlv(25, 26); -- bits 0,3,4 + constant MASK_INIT2RTR_C : slv(25 downto 0) := toSlv(1216769, 26); -- bits 0,8,12,15,17,20 + constant MASK_RTR2RTS_C : slv(25 downto 0) := toSlv(77313, 26); -- bits 0,9,10,11,13,16 + constant MASK_ONLYSTATE_C : slv(25 downto 0) := toSlv(1, 26); -- bit 0 + + --------------------------------------------------------------------------- + -- ReqQP packed-field absolute ranges (301-bit word, first field at MSB) + -- qpReqType[300:299] pdHandler[298:267] qpn[266:243] qpAttrMask[242:217] + -- qpAttr[216:5] qpInitAttr[4:0] + -- AttrQP (base offset 5) fields used by the FSM (absolute bit ranges): + -- qpState[216:213] pmtu[208:206] qkey[205:174] rqPSN[173:150] + -- sqPSN[149:126] dqpn[125:102] qpAccessFlags[101:94] pkeyIndex[53:38] + -- maxReadAtomic[36:29] maxDestReadAtomic[28:21] minRnrTimer[20:16] + -- timeout[15:11] retryCnt[10:8] rnrRetry[7:5] + -- QpInitAttr (base offset 0): qpType[4:1] sqSigAll[0] + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- RegType : all FSM state + QP attribute latches + ContextRQ scratch. + -- Per OQ-FSM-CntrlQP-01/02: nextState and setStateErr are CReg intra-cycle + -- forwarding signals (cleared every cycle by canonicalize) -> modelled as + -- comb variables, NOT registered fields. + --------------------------------------------------------------------------- + type RegType is record + -- control state + state : StateType; + preState : StateType; + errFlushDone : sl; + -- QP attribute latches + sqpn : slv(23 downto 0); + dqpn : slv(23 downto 0); + sqType : slv(3 downto 0); + rqType : slv(3 downto 0); + sqSigAll : sl; + qpAccessFlags : slv(7 downto 0); + pkey : slv(15 downto 0); + qkey : slv(31 downto 0); + pmtu : slv(2 downto 0); + epsn : slv(23 downto 0); -- epsnReg (CReg: port0 onINIT/setEPSN, port1 restore) + npsn : slv(23 downto 0); + maxTimeOut : slv(4 downto 0); + maxRetryCnt : slv(2 downto 0); + maxRnrCnt : slv(2 downto 0); + minRnrTimer : slv(4 downto 0); + pendingReadAtomicReqNum : slv(7 downto 0); + pendingDestReadAtomicReqNum : slv(7 downto 0); + pendingWorkReqNum : slv(7 downto 0); + pendingRecvReqNum : slv(7 downto 0); + preReqOpCode : slv(4 downto 0); -- CReg: port0 scrub/set, port1 restore + epoch : sl; + msn : slv(23 downto 0); + -- ContextRQ scratch (method-only) + permCheckReq : slv(266 downto 0); + totalDmaWriteLen : slv(31 downto 0); + remainingDmaWriteLen: slv(31 downto 0); + nextDmaWriteAddr : slv(63 downto 0); + sendWriteReqPktNum : slv(24 downto 0); + respPktNum : slv(24 downto 0); + isRespPktNumZero : sl; + curRespPsn : slv(23 downto 0); + end record RegType; + + -- mkRegU/mkCRegU fields initialised to 0 per OQ-FSM-CntrlQP-03 (safe: all + -- written-before-read). Reset values from BSV mkReg(...) where present. + constant REG_INIT_C : RegType := ( + state => RESET_S, -- mkReg(IBV_QPS_RESET) + preState => UNKNOWN_S, -- mkReg(IBV_QPS_UNKNOWN) + errFlushDone => '0', -- mkRegU + sqpn => (others => '0'), + dqpn => (others => '0'), + sqType => (others => '0'), + rqType => (others => '0'), + sqSigAll => '0', + qpAccessFlags => (others => '0'), + pkey => (others => '0'), + qkey => (others => '0'), + pmtu => (others => '0'), + epsn => (others => '0'), + npsn => (others => '0'), + maxTimeOut => (others => '0'), + maxRetryCnt => (others => '0'), + maxRnrCnt => (others => '0'), + minRnrTimer => (others => '0'), + pendingReadAtomicReqNum => (others => '0'), + pendingDestReadAtomicReqNum => (others => '0'), + pendingWorkReqNum => MAX_QP_WR_C, -- mkReg(MAX_QP_WR) + pendingRecvReqNum => MAX_QP_WR_C, -- mkReg(MAX_QP_WR) + preReqOpCode => SEND_ONLY_C, -- mkCReg(2, SEND_ONLY) + epoch => '0', -- mkReg(0) + msn => (others => '0'), -- mkReg(0) + permCheckReq => (others => '0'), + totalDmaWriteLen => (others => '0'), + remainingDmaWriteLen=> (others => '0'), + nextDmaWriteAddr => (others => '0'), + sendWriteReqPktNum => (others => '0'), + respPktNum => (others => '0'), + isRespPktNumZero => '0', + curRespPsn => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- inited (combinational decode of r.state), used as method RDY and guard + signal initedInt : sl; + + -- U_ReqQ + signal reqQNotFull : sl; + signal reqQValid : sl; + signal reqQDout : slv(300 downto 0); + signal reqQRdEn : sl; + -- U_RespQ + signal respQNotFull : sl; + signal respQValid : sl; + signal respQDin : slv(273 downto 0); + signal respQWrEn : sl; + -- U_RestoreQ + signal restoreQNotFull : sl; + signal restoreQValid : sl; + signal restoreQDout : slv(28 downto 0); + signal restoreQRdEn : sl; + signal restoreQRst : sl; -- global rst OR RESET_S clear (level) + + signal rstActiveHigh : sl; + +begin + + --------------------------------------------------------------------------- + -- inited = (state /= RESET) and (state /= UNKNOWN) + --------------------------------------------------------------------------- + initedInt <= '1' when (r.state /= RESET_S and r.state /= UNKNOWN_S) else '0'; + rstActiveHigh <= rst; -- RST_POLARITY_G = '1' (active-high) + + -- restoreQ.clear (resetAndClear, fire_when_enabled while state=RESET) is + -- modelled as a level rst pulse (OQ-FSM-01/06). reqQ/respQ never cleared. + restoreQRst <= rstActiveHigh or ite(r.state = RESET_S, '1', '0'); + + --------------------------------------------------------------------------- + -- U_ReqQ : reqQ (ReqQP, 301 bits). FWFT so valid/dout == BSV !empty/first. + --------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + SYNTH_MODE_G => "inferred", + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => REQ_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rstActiveHigh, + wr_clk => clk, + wr_en => srvReqValid, -- parent gates externally on srvReqReady + din => srvReqData, + not_full => reqQNotFull, + rd_clk => clk, + rd_en => reqQRdEn, + dout => reqQDout, + valid => reqQValid); + + --------------------------------------------------------------------------- + -- U_RespQ : respQ (RespQP, 274 bits) + --------------------------------------------------------------------------- + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + SYNTH_MODE_G => "inferred", + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => RESP_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rstActiveHigh, + wr_clk => clk, + wr_en => respQWrEn, + din => respQDin, + not_full => respQNotFull, + rd_clk => clk, + rd_en => srvRespReady, -- parent gates externally on srvRespValid + dout => srvRespData, + valid => respQValid); + + --------------------------------------------------------------------------- + -- U_RestoreQ : restoreQ (Tuple2#(RdmaOpCode,PSN) = 29 bits) + -- din = preOpCode(5) & psn(24); dout(28:24)=preOpCode, dout(23:0)=psn. + -- rst carries the RESET_S clear pulse (OQ-FSM-01). + --------------------------------------------------------------------------- + U_RestoreQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + SYNTH_MODE_G => "inferred", + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 29, + ADDR_WIDTH_G => 4) + port map ( + rst => restoreQRst, + wr_clk => clk, + wr_en => restoreValid, -- parent gates externally on restoreReady + din => restorePreOpCode & restoreEpsn, + not_full => restoreQNotFull, + rd_clk => clk, + rd_en => restoreQRdEn, + dout => restoreQDout, + valid => restoreQValid); + + --------------------------------------------------------------------------- + -- Combinatorial process: all on*/canonicalize/restore/updatePreState/ + -- resetAndClear logic + method writes. One atomic BSV rule = one v-block. + --------------------------------------------------------------------------- + comb : process (r, rst, initedInt, + reqQValid, reqQDout, reqQNotFull, + respQNotFull, respQValid, + restoreQValid, restoreQDout, restoreQNotFull, + srvReqValid, srvRespReady, + setStateErr, errFlushDoneIn, + setNPSNen, setNPSN, setPermCheckReqEn, setPermCheckReq, + setTotalDmaWriteLenEn, setTotalDmaWriteLen, + setRemainingDmaWriteLenEn, setRemainingDmaWriteLen, + setNextDmaWriteAddrEn, setNextDmaWriteAddr, + setSendWriteReqPktNumEn, setSendWriteReqPktNum, + setPreReqOpCodeEn, setPreReqOpCode, incEpochEn, + setMSNen, setMSN, setRespPktNumEn, setRespPktNum, + setCurRespPSNen, setCurRespPSN, setEPSNen, setEPSN) is + variable v : RegType; + variable nextStateVld : sl; + variable nextStateData : StateType; + variable setStateErrV : sl; + variable fireV : sl; + variable successV : sl; + variable reqType : slv(1 downto 0); + variable reqQpState : StateType; + variable reqQpType : slv(3 downto 0); + variable reqMask : slv(25 downto 0); + variable vResp : slv(273 downto 0); + begin + v := r; + + -- CReg intra-cycle forwarding signals (default: no proposal / no error) + nextStateVld := '0'; + nextStateData := r.state; + setStateErrV := '0'; + + -- FIFO drive defaults + reqQRdEn <= '0'; + respQWrEn <= '0'; + restoreQRdEn <= '0'; + + -- Request field views (ReqQP packed) + reqType := reqQDout(300 downto 299); + reqQpState := reqQDout(216 downto 213); -- qpAttr.qpState (target state) + reqQpType := reqQDout(4 downto 1); -- qpInitAttr.qpType + reqMask := reqQDout(242 downto 217); -- qpAttrMask + + -- Response default = echo request (qpn / pdHandler / qpAttr / qpInitAttr) + vResp := (others => '0'); + vResp(272 downto 249) := reqQDout(266 downto 243); -- qpn + vResp(248 downto 217) := reqQDout(298 downto 267); -- pdHandler + vResp(216 downto 5) := reqQDout(216 downto 5); -- qpAttr (echo) + vResp(4 downto 0) := reqQDout(4 downto 0); -- qpInitAttr + successV := '1'; + + ------------------------------------------------------------------------ + -- ContextSQ/ContextRQ setter methods (CReg/Reg port0 writes), gated by + -- inited (BSV implicit RDY). Applied before the state case so that the + -- on* rule latches and restore (port1) take precedence in their states. + ------------------------------------------------------------------------ + if (initedInt = '1') then + if (setNPSNen = '1') then v.npsn := setNPSN; end if; + if (setPermCheckReqEn = '1') then v.permCheckReq := setPermCheckReq; end if; + if (setTotalDmaWriteLenEn = '1') then v.totalDmaWriteLen := setTotalDmaWriteLen; end if; + if (setRemainingDmaWriteLenEn = '1') then v.remainingDmaWriteLen := setRemainingDmaWriteLen; end if; + if (setNextDmaWriteAddrEn = '1') then v.nextDmaWriteAddr := setNextDmaWriteAddr; end if; + if (setSendWriteReqPktNumEn = '1') then v.sendWriteReqPktNum := setSendWriteReqPktNum; end if; + if (setPreReqOpCodeEn = '1') then v.preReqOpCode := setPreReqOpCode; end if; -- port0 + if (incEpochEn = '1') then v.epoch := not r.epoch; end if; + if (setMSNen = '1') then v.msn := setMSN; end if; + if (setCurRespPSNen = '1') then v.curRespPsn := setCurRespPSN; end if; + if (setEPSNen = '1') then v.epsn := setEPSN; end if; -- port0 + if (setRespPktNumEn = '1') then + v.respPktNum := setRespPktNum; + v.isRespPktNumZero := ite(unsigned(setRespPktNum) = 0, '1', '0'); + end if; + end if; + + ------------------------------------------------------------------------ + -- setStateErr() / errFlushDone() methods (both guarded by inited). + -- They share errFlushDoneReg, so they cannot both apply same cycle: + -- setStateErr takes priority (it forces the error transition). + ------------------------------------------------------------------------ + if (initedInt = '1' and setStateErr = '1') then + setStateErrV := '1'; -- setStateErrReg[0] <= True (consumed by canonicalize) + v.errFlushDone := '0'; -- errFlushDoneReg <= False + elsif (initedInt = '1' and errFlushDoneIn = '1' + and r.state = ERR_S and r.errFlushDone = '0') then + v.errFlushDone := '1'; + end if; + + ------------------------------------------------------------------------ + -- rule updatePreState (fire_when_enabled, unconditional) + ------------------------------------------------------------------------ + v.preState := r.state; + + ------------------------------------------------------------------------ + -- on* rules (mutually exclusive by state) + resetAndClear scrub. + -- A rule fires iff reqQ has data and respQ can accept (implicit conds); + -- onERR additionally requires errFlushDone. fireV => deq req + enq resp. + ------------------------------------------------------------------------ + case r.state is + ---------------------------------------------------------------------- + when RESET_S => + -- rule resetAndClear (every cycle in RESET): re-apply defaults + + -- pulse restoreQ clear (restoreQRst level, driven concurrently). + v.pendingWorkReqNum := MAX_QP_WR_C; + v.pendingRecvReqNum := MAX_QP_WR_C; + v.preReqOpCode := SEND_ONLY_C; + v.epoch := '0'; + v.msn := (others => '0'); + + -- rule onReset + fireV := reqQValid and respQNotFull; + successV := ite(reqType = REQ_QP_CREATE_C, '1', '0'); + if (fireV = '1') then + v.sqpn := reqQDout(266 downto 243); -- qpn + v.sqType := ite(reqQpType = IBV_QPT_XRC_RECV_C, IBV_QPT_XRC_SEND_C, reqQpType); + v.rqType := ite(reqQpType = IBV_QPT_XRC_SEND_C, IBV_QPT_XRC_RECV_C, reqQpType); + v.sqSigAll := reqQDout(0); -- qpInitAttr.sqSigAll + if (successV = '1') then + nextStateVld := '1'; + nextStateData := CREATE_S; -- tagged Valid IBV_QPS_CREATE + end if; + vResp(273) := successV; + end if; + + ---------------------------------------------------------------------- + when CREATE_S => + fireV := reqQValid and respQNotFull; + if (fireV = '1') then + case reqType is + when REQ_QP_MODIFY_C => + successV := ite((reqQpState = INIT_S) and + ((reqMask and MASK_RESET2INIT_C) = MASK_RESET2INIT_C), + '1', '0'); + if (successV = '1') then + nextStateVld := '1'; + nextStateData := reqQpState; + end if; + v.qpAccessFlags := reqQDout(101 downto 94); -- always (success or not) + v.pkey := reqQDout(53 downto 38); + when REQ_QP_QUERY_C => + vResp(212 downto 209) := r.state; -- curQpState + when others => -- DESTROY / default: immFail (sim-only) + null; + end case; + vResp(273) := successV; + end if; + + ---------------------------------------------------------------------- + when INIT_S => + fireV := reqQValid and respQNotFull; + if (fireV = '1') then + case reqType is + when REQ_QP_MODIFY_C => + successV := ite((reqQpState = RTR_S) and + ((reqMask and MASK_INIT2RTR_C) = MASK_INIT2RTR_C), + '1', '0'); + if (successV = '1') then + nextStateVld := '1'; + nextStateData := reqQpState; + end if; + v.pmtu := reqQDout(208 downto 206); + v.dqpn := reqQDout(125 downto 102); + v.epsn := reqQDout(173 downto 150); -- epsn[0] <= rqPSN + v.pendingDestReadAtomicReqNum := reqQDout(28 downto 21); + v.minRnrTimer := reqQDout(20 downto 16); + when REQ_QP_QUERY_C => + vResp(212 downto 209) := r.state; -- curQpState + vResp(101 downto 94) := r.qpAccessFlags; + vResp(53 downto 38) := r.pkey; -- pkeyIndex + when others => + null; + end case; + vResp(273) := successV; + end if; + + ---------------------------------------------------------------------- + when RTR_S => + fireV := reqQValid and respQNotFull; + if (fireV = '1') then + case reqType is + when REQ_QP_MODIFY_C => + successV := ite( + ((reqQpState = ERR_S) and ((reqMask and MASK_ONLYSTATE_C) = MASK_ONLYSTATE_C)) or + ((reqQpState = RTS_S) and ((reqMask and MASK_RTR2RTS_C) = MASK_RTR2RTS_C)), + '1', '0'); + if (successV = '1') then + nextStateVld := '1'; + nextStateData := reqQpState; + end if; + v.npsn := reqQDout(149 downto 126); -- sqPSN + v.maxTimeOut := reqQDout(15 downto 11); -- timeout + v.maxRetryCnt := reqQDout(10 downto 8); -- retryCnt + v.maxRnrCnt := reqQDout(7 downto 5); -- rnrRetry + v.pendingReadAtomicReqNum := reqQDout(36 downto 29); -- maxReadAtomic + when REQ_QP_QUERY_C => + vResp(212 downto 209) := r.state; + vResp(101 downto 94) := r.qpAccessFlags; + vResp(53 downto 38) := r.pkey; + when others => + null; + end case; + vResp(273) := successV; + end if; + + ---------------------------------------------------------------------- + when RTS_S => + fireV := reqQValid and respQNotFull; + if (fireV = '1') then + case reqType is + when REQ_QP_MODIFY_C => + successV := ite( + ((reqQpState = SQD_S) or (reqQpState = ERR_S)) and + ((reqMask and MASK_ONLYSTATE_C) = MASK_ONLYSTATE_C), + '1', '0'); + if (successV = '1') then + nextStateVld := '1'; + nextStateData := reqQpState; + end if; + when REQ_QP_QUERY_C => + vResp(212 downto 209) := r.state; -- curQpState + vResp(101 downto 94) := r.qpAccessFlags; + vResp(53 downto 38) := r.pkey; + vResp(149 downto 126) := r.npsn; -- sqPSN + vResp(15 downto 11) := r.maxTimeOut; -- timeout + vResp(10 downto 8) := r.maxRetryCnt; -- retryCnt + vResp(7 downto 5) := r.maxRnrCnt; -- rnrRetry + vResp(36 downto 29) := r.pendingReadAtomicReqNum; -- maxReadAtomic + when others => + null; + end case; + vResp(273) := successV; + end if; + + ---------------------------------------------------------------------- + when SQD_S => + fireV := reqQValid and respQNotFull; + if (fireV = '1') then + case reqType is + when REQ_QP_MODIFY_C => + successV := ite( + ((reqQpState = ERR_S) or (reqQpState = RTS_S)) and + ((reqMask and MASK_ONLYSTATE_C) = MASK_ONLYSTATE_C), + '1', '0'); + if (successV = '1') then + nextStateVld := '1'; + nextStateData := reqQpState; + end if; + when REQ_QP_QUERY_C => + vResp(212 downto 209) := r.state; + vResp(101 downto 94) := r.qpAccessFlags; + vResp(53 downto 38) := r.pkey; + vResp(149 downto 126) := r.npsn; + vResp(15 downto 11) := r.maxTimeOut; + vResp(10 downto 8) := r.maxRetryCnt; + vResp(7 downto 5) := r.maxRnrCnt; + vResp(36 downto 29) := r.pendingReadAtomicReqNum; + when others => + null; + end case; + vResp(273) := successV; + end if; + + ---------------------------------------------------------------------- + when ERR_S => + -- onERR also requires errFlushDone + fireV := reqQValid and respQNotFull and r.errFlushDone; + if (fireV = '1') then + case reqType is + when REQ_QP_DESTROY_C => + nextStateVld := '1'; + nextStateData := RESET_S; -- DESTROY legal only from ERR + when REQ_QP_MODIFY_C => + successV := ite((reqQpState = RESET_S) and + ((reqMask and MASK_ONLYSTATE_C) = MASK_ONLYSTATE_C), + '1', '0'); + if (successV = '1') then + nextStateVld := '1'; + nextStateData := reqQpState; -- RESET + end if; + when REQ_QP_QUERY_C => + vResp(212 downto 209) := r.state; -- curQpState + when others => + null; + end case; + vResp(273) := successV; + end if; + + when others => -- SQE/UNKNOWN: no active rule + null; + end case; + + -- Drive FIFO enables from the firing rule + reqQRdEn <= fireV; + respQWrEn <= fireV; + respQDin <= vResp; + + ------------------------------------------------------------------------ + -- rule restore (RTR/RTS/SQD, when restoreQ has data) — independent of + -- reqQ. Writes preReqOpCode[1]/epsn[1] (port1) -> OVERRIDES same-cycle + -- port0 (setPreReqOpCode/setEPSN) writes applied above. + ------------------------------------------------------------------------ + if ((r.state = RTR_S or r.state = RTS_S or r.state = SQD_S) + and restoreQValid = '1') then + restoreQRdEn <= '1'; + v.preReqOpCode := restoreQDout(28 downto 24); -- preOpCode + v.epsn := restoreQDout(23 downto 0); -- psn + end if; + + ------------------------------------------------------------------------ + -- rule canonicalize (fire_when_enabled): single state commit. + -- priority: setStateErr (force ERR) > nextState proposal > hold. + ------------------------------------------------------------------------ + if (nextStateVld = '1') then + v.state := nextStateData; + end if; + if (setStateErrV = '1') then + v.state := ERR_S; + end if; + + ------------------------------------------------------------------------ + -- Synchronous reset + ------------------------------------------------------------------------ + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + + ------------------------------------------------------------------------ + -- Outputs + ------------------------------------------------------------------------ + srvReqReady <= reqQNotFull; + srvRespValid <= respQValid; + restoreReady <= restoreQNotFull; + inited <= initedInt; + + -- CntrlCommStatus decodes (Moore, from r.state / r.preState) + isCreate <= ite(r.state = CREATE_S, '1', '0'); + isErr <= ite(r.state = ERR_S, '1', '0'); + isInit <= ite(r.state = INIT_S, '1', '0'); + isNonErr <= ite(r.state = RTR_S or r.state = RTS_S or r.state = SQD_S, '1', '0'); + isReset <= ite(r.state = RESET_S, '1', '0'); + isRTR <= ite(r.state = RTR_S, '1', '0'); + isRTS <= ite(r.state = RTS_S, '1', '0'); + isSQD <= ite(r.state = SQD_S, '1', '0'); + isUnknown <= ite(r.state = UNKNOWN_S, '1', '0'); + isRTR2RTS <= ite(r.preState = RTR_S and r.state = RTS_S, '1', '0'); + isStableRTS <= ite(r.preState = RTS_S and r.state = RTS_S, '1', '0'); + + -- Attribute getters (Moore) + getAccessFlags <= r.qpAccessFlags; + getMaxRnrCnt <= r.maxRnrCnt; + getMaxRetryCnt <= r.maxRetryCnt; + getMaxTimeOut <= r.maxTimeOut; + getMinRnrTimer <= r.minRnrTimer; + getPendingWorkReqNum <= r.pendingWorkReqNum; + getPendingRecvReqNum <= r.pendingRecvReqNum; + getPendingReadAtomicReqNum <= r.pendingReadAtomicReqNum; + getPendingDestReadAtomicReqNum <= r.pendingDestReadAtomicReqNum; + getSigAll <= r.sqSigAll; + getSQPN <= r.sqpn; + getDQPN <= r.dqpn; + getPKEY <= r.pkey; + getQKEY <= r.qkey; + getPMTU <= r.pmtu; + getTypeSq <= r.sqType; + getTypeRq <= r.rqType; + + -- ContextSQ / ContextRQ getters (Moore) + getNPSN <= r.npsn; + getPermCheckReq <= r.permCheckReq; + getTotalDmaWriteLen <= r.totalDmaWriteLen; + getRemainingDmaWriteLen <= r.remainingDmaWriteLen; + getNextDmaWriteAddr <= r.nextDmaWriteAddr; + getSendWriteReqPktNum <= r.sendWriteReqPktNum; + getPreReqOpCode <= r.preReqOpCode; -- preReqOpCodeReg[0] + getEpoch <= r.epoch; + getMSN <= r.msn; + getIsRespPktNumZero <= r.isRespPktNumZero; + getRespPktNum <= r.respPktNum; + getCurRespPSN <= r.curRespPsn; + getEPSN <= r.epsn; -- epsnReg[0] + + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process: r <= rin on rising edge. + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + --------------------------------------------------------------------------- + -- Simulation-only invariant checks (OQ-FSM-CntrlQP-02): immFail asserts. + -- DESTROY is legal only from ERR_S; any other reqType decodes to default. + --------------------------------------------------------------------------- + -- pragma translate_off + check : process (clk) is + begin + if rising_edge(clk) then + if (rst = '0' and reqQValid = '1' and respQNotFull = '1') then + if ((r.state = CREATE_S or r.state = INIT_S or r.state = RTR_S or + r.state = RTS_S or r.state = SQD_S) + and reqQDout(300 downto 299) = REQ_QP_DESTROY_C) then + assert false + report "CntrlQp: REQ_QP_DESTROY illegal outside ERR_S (immFail @ mkCntrlQP)" + severity failure; + end if; + end if; + if (rst = '0' and setStateErr = '1' and initedInt = '1') then + assert (r.state /= UNKNOWN_S and r.state /= RESET_S) + report "CntrlQp: setStateErr while state is UNKNOWN/RESET (immAssert @ canonicalize)" + severity failure; + end if; + end if; + end process check; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/CombineHeaderAndPayload.vhd b/ethernet/RoCEv2/rtl/CombineHeaderAndPayload.vhd new file mode 100644 index 0000000000..357189c742 --- /dev/null +++ b/ethernet/RoCEv2/rtl/CombineHeaderAndPayload.vhd @@ -0,0 +1,244 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- STRUCTURAL packet-stream merger. Owns no datapath transformation. It chains +-- two child entities and drains their merged RDMA DataStream into one output +-- FIFO, popping one psnPipeIn entry per completed packet (per isLast): +-- +-- headerPipeIn ──> U_Header2DataStream ──(headerDataStream + headerMetaData)──┐ +-- v +-- payloadPipeIn ───────────────────────────────> U_PrependHeader2PipeOut ──(rdmaDataStream) +-- │ +-- connect handshake (this entity) │ +-- v +-- U_OutputQ : surf.Fifo +-- │ +-- toPipeOut(outputQ) = output +-- +-- The single BSV `rule connect` comes from mkConnectionWithAction +-- (Utils.bsv:1782): get rdmaDataStreamPipeOut, put into outputQ, and run +-- deqActionFunc (ExtractAndPrependPipeOut.bsv:735), which pops psnPipeIn only +-- when the transferred fragment is isLast. Modeled here as a pure combinational +-- FIFO handshake — there is NO local RegType (single perpetual CONNECT state). +-- +-- Partition / spec notes applied: +-- * OQ-FSM-CHP-01: mapping.json wrongly records rules=[]/surf_instances=[]. +-- The BSV has `outputQ <- mkFIFOF` (-> U_OutputQ : surf.Fifo, 290 b) and the +-- implied connect rule. Both are emitted (FSM spec is authoritative). +-- * OQ-FSM-CHP-02: the commented-out `rule connect` (lines 700-733) with the +-- BTH-extract / PSN-compare assertion is DEAD CODE. `psnPipeIn` is drained +-- (notEmpty + deq) but its VALUE is never used; `bthReg` (mkRegU in +-- mkConnectionWithAction) is dead and NOT emitted. No PSN check is added — +-- that would be NEW behavior. +-- +-- Width / packing (BSV deriving(Bits), first-field-at-MSB; OQ-FSM-H2DS-02/04): +-- DataStream (290): [289:34] data[255:0] | [33:2] byteEn[31:0] | +-- [1] isFirst | [0] isLast +-- HeaderRDMA = 593 b ; HeaderMetaData = 17 b ; PSN = 24 b. +-- +-- FIFO clear (OQ-FSM-01 family RESOLVED): surf.Fifo has no clear port; the +-- FSM spec's "U_OutputQ clears on cntrlStatus.comm.isReset" is realized by +-- asserting the synchronous FIFO reset: outputQRst = rst OR clearAllI. (Note: +-- the BSV mkFIFOF itself resets only on the module's implicit/global reset; +-- the OR with clearAllI follows the Stage-3 spec decision and the project-wide +-- soft-clear convention so the whole pipeline flushes coordinated.) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity CombineHeaderAndPayload is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset + RST_ASYNC_G : boolean := false); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + + -- Soft clear (cntrlStatus.comm.isReset); fanned to both children + outputQ + clearAllI : in sl; + + -- headerPipeIn : PipeOut#(HeaderRDMA) (593 b) -> U_Header2DataStream + headerPipeInValid : in sl; -- .notEmpty + headerPipeInData : in slv(592 downto 0); -- .first (HeaderRDMA) + headerPipeInRdEn : out sl; -- .deq + + -- payloadPipeIn : DataStreamPipeOut (290 b) -> U_PrependHeader2PipeOut + payloadPipeInValid : in sl; -- .notEmpty + payloadPipeInData : in slv(289 downto 0); -- .first (DataStream) + payloadPipeInRdEn : out sl; -- .deq + + -- psnPipeIn : PipeOut#(PSN) (24 b). VALUE UNUSED (OQ-FSM-CHP-02); only the + -- notEmpty/deq handshake is used — one pop per completed (isLast) packet. + psnPipeInValid : in sl; -- .notEmpty + psnPipeInData : in slv(23 downto 0); -- .first (PSN) — unused + psnPipeInRdEn : out sl; -- .deq (only on isLast) + + -- Output : toPipeOut(outputQ) : DataStreamPipeOut (290 b) + dataStreamOutValid : out sl; -- PipeOut.notEmpty + dataStreamOutData : out slv(289 downto 0); -- PipeOut.first + dataStreamOutRdEn : in sl); -- PipeOut.deq +end entity CombineHeaderAndPayload; + +architecture rtl of CombineHeaderAndPayload is + + -- DataStream layout + constant DS_WIDTH_C : integer := 290; + constant DS_ISLAST_C : integer := 0; -- DataStream.isLast bit index + + -- Reset / clear plumbing + signal rstActiveHigh : sl; + signal outputQRst : sl; -- rst OR clearAllI (soft clear) + + -- U_Header2DataStream -> U_PrependHeader2PipeOut interconnect + signal hdrDsValid : sl; -- headerDataStream.notEmpty + signal hdrDsData : slv(DS_WIDTH_C-1 downto 0);-- headerDataStream.first + signal hdrDsRdEn : sl; -- headerDataStream.deq + signal hdrMetaValid : sl; -- headerMetaData.notEmpty + signal hdrMetaData : slv(16 downto 0); -- headerMetaData.first + signal hdrMetaRdEn : sl; -- headerMetaData.deq + + -- U_PrependHeader2PipeOut output (rdmaDataStreamPipeOut) + signal rdmaOutValid : sl; -- .notEmpty + signal rdmaOutData : slv(DS_WIDTH_C-1 downto 0);-- .first + signal rdmaOutRdEn : sl; -- .deq (connect-rule pop) + + -- U_OutputQ (surf.Fifo) write side + signal outputQFull : sl; + signal outputQWrEn : sl; + signal outputQDin : slv(DS_WIDTH_C-1 downto 0); + + -- connect-rule combinational signals + signal isLast : sl; + signal transferFire : sl; + +begin + + ----------------------------------------------------------------------------- + -- Reset normalisation + soft clear + ----------------------------------------------------------------------------- + rstActiveHigh <= rst when RST_POLARITY_G = '1' else not rst; + outputQRst <= rstActiveHigh or clearAllI; + + ----------------------------------------------------------------------------- + -- U_Header2DataStream : HeaderRDMA pipe -> (headerDataStream + headerMetaData) + -- (BSV: mkHeader2DataStream(cntrlStatus.comm.isReset, headerPipeIn)) + ----------------------------------------------------------------------------- + U_Header2DataStream : entity surf.Header2DataStream + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rstActiveHigh, + clearAllI => clearAllI, + -- headerPipeIn (top-level) + hdrPipeInValid => headerPipeInValid, + hdrPipeInData => headerPipeInData, + hdrPipeInRdEn => headerPipeInRdEn, + -- headerDataStream -> U_PrependHeader2PipeOut.headerPipeIn + hdrDataStreamValid => hdrDsValid, + hdrDataStreamDout => hdrDsData, + hdrDataStreamRdEn => hdrDsRdEn, + -- headerMetaData -> U_PrependHeader2PipeOut.headerMetaPipeIn + hdrMetaDataValid => hdrMetaValid, + hdrMetaDataDout => hdrMetaData, + hdrMetaDataRdEn => hdrMetaRdEn); + + ----------------------------------------------------------------------------- + -- U_PrependHeader2PipeOut : merge header DataStream + payload -> RDMA stream + -- (BSV: mkPrependHeader2PipeOut(isReset, headerDataStream, headerMetaData, + -- payloadPipeIn)) + ----------------------------------------------------------------------------- + U_PrependHeader2PipeOut : entity surf.PrependHeader2PipeOut + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rstActiveHigh, + clearAllI => clearAllI, + -- headerMetaPipeIn <- U_Header2DataStream.headerMetaData + headerMetaPipeInValid => hdrMetaValid, + headerMetaPipeInData => hdrMetaData, + headerMetaPipeInRdEn => hdrMetaRdEn, + -- headerPipeIn <- U_Header2DataStream.headerDataStream + headerPipeInValid => hdrDsValid, + headerPipeInData => hdrDsData, + headerPipeInRdEn => hdrDsRdEn, + -- dataPipeIn <- payloadPipeIn (top-level) + dataPipeInValid => payloadPipeInValid, + dataPipeInData => payloadPipeInData, + dataPipeInRdEn => payloadPipeInRdEn, + -- dataStreamOut = rdmaDataStreamPipeOut (drained by connect handshake) + dataStreamOutValid => rdmaOutValid, + dataStreamOutData => rdmaOutData, + dataStreamOutRdEn => rdmaOutRdEn); + + ----------------------------------------------------------------------------- + -- U_OutputQ : surf.Fifo (BSV: outputQ <- mkFIFOF, element DataStream = 290 b) + -- FWFT first/deq PipeOut semantics; sync; soft-cleared via outputQRst. + -- Read side IS the module's toPipeOut(outputQ) output interface. + ----------------------------------------------------------------------------- + U_OutputQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', -- outputQRst is active-high + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => outputQRst, + wr_clk => clk, + wr_en => outputQWrEn, + din => outputQDin, + full => outputQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => dataStreamOutRdEn, -- downstream deq (output port) + dout => dataStreamOutData, -- output port + valid => dataStreamOutValid, -- output port + underflow => open, + rd_data_count => open, + prog_empty => open, + almost_empty => open, + empty => open); + + ----------------------------------------------------------------------------- + -- connect rule (combinational FIFO handshake; no RegType — CONNECT_S only) + -- fire = rdmaOut.notEmpty AND outputQ.notFull AND (!isLast OR psn.notEmpty) + -- on fire: outputQ.enq(rdmaOut.first); rdmaOut.deq; if isLast: psn.deq + -- BSV mkConnectionWithAction: the connectAction (psnPipeIn.deq, gated by + -- isLast) contributes its implicit notEmpty condition to the rule only when + -- isLast — hence the (!isLast OR psnPipeInValid) term (FSM spec guard note). + ----------------------------------------------------------------------------- + isLast <= rdmaOutData(DS_ISLAST_C); + transferFire <= rdmaOutValid and (not outputQFull) and + ((not isLast) or psnPipeInValid); + + outputQWrEn <= transferFire; + outputQDin <= rdmaOutData; + rdmaOutRdEn <= transferFire; -- pop the merged RDMA stream + psnPipeInRdEn <= transferFire and isLast; -- one pop per completed packet + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutConAndGen.vhd b/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutConAndGen.vhd new file mode 100644 index 0000000000..f78945ff23 --- /dev/null +++ b/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutConAndGen.vhd @@ -0,0 +1,166 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Skid / output-register stage. Pulls fragments out of an upstream FIFO +-- (bramQ, a module argument — exposed here as a Get/dequeue handshake on +-- ports, NOT instantiated) into a small internal skid FIFO (postBramQ), and +-- re-exposes that internal FIFO as a PipeOut. +-- +-- There is NO explicit state register and NO data-dependent control flow: +-- per the FSM spec (§State register / §Output style) the only "machine" is the +-- implicit mkConnection transfer rule, gated solely by the two FIFOs' +-- full/empty flags. This entity is therefore emitted as a *pure structural +-- wrapper* — one surf.Fifo plus combinational glue — with NO two-process FSM +-- and NO RegType (the only registered storage lives inside U_PostBramQ). +-- +-- BramPipe interface (3 live methods restored per OQ-FSM-CB-2; mapping.json +-- listed only pipeOutPort): +-- pipeOut : PipeOut#(DataStream) -> first/deq/notEmpty handshake ports +-- clear() : Action -> clearEnI (synchronous flush of postBramQ) +-- notEmpty : Bool -> notEmpty output +-- +-- Two independent, conflict-free handshakes through the one FIFO: +-- * Upstream enqueue (mkConnection rl_connect, line 521): +-- fire = bramQNotEmpty AND postBramQNotFull +-- -> bramQDeq, postBramQWrEn, postBramQDin = bramQDout +-- * Downstream dequeue (toPipeOut, line 523): +-- postBramQRdEn = pipeOutDeq +-- They may both occur in the same cycle (opposite ends of a FIFO). +-- +-- clear() mapping (OQ-FSM-CB-3, resolved via OQ-FSM-01 in +-- out/03-fsm/RESOLVED.md): +-- surf.Fifo has no dedicated clear port; BSV postBramQ.clear is modelled by +-- asserting the Fifo rst, OR'd with the structural reset: +-- fifoRst <= rst or clearEnI +-- surf.FifoSync (GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, RST_POLARITY_G='1') +-- holds the FIFO logically empty for the whole asserted window (level-safe; +-- no pulse generator). The upstream enqueue (bramQDeq / postBramQWrEn) is +-- SUPPRESSED while clearEnI='1' (fsm.md §Conflicts/scheduling) so a fragment +-- is not dequeued from the upstream bramQ only to be discarded by the flush. +-- +-- Width (OQ-FSM-CB-1 + project-wide OQ-FSM-H2DS-02, RESOLVED): +-- DataStream = data(256)+byteEn(32)+isFirst(1)+isLast(1) = 290 bits. +-- The FSM spec / mapping.json carry the stale inventory value 321; per the +-- OQ-FSM-H2DS-02 resolution ("apply consistently at emit") and OQ-FSM-CPG-1 +-- ("backfill the ConAndGen siblings"), this entity uses DATA_WIDTH_G=290. +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, block RAM +-- (BSV postBramQ <- mkFIFOF). ADDR_WIDTH_G=4 (surf.Fifo min; +-- the BSV 2-deep skid maps to depth-16 — extra buffering only, +-- functionally equivalent for a skid stage). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ConnectBramQ2PipeOutConAndGen is + generic ( + TPD_G : time := 1 ns; + DATA_W_G : positive := 290); -- DataStream width (OQ-FSM-H2DS-02) + port ( + clk : in sl; + rst : in sl; -- active-high sync reset + -- clear() method (Action): synchronous flush of the internal skid FIFO + clearEnI : in sl; + -- Upstream bramQ : Get#(DataStream) handshake (bramQ is a module argument) + bramQNotEmpty : in sl; -- bramQ.notEmpty (first valid) + bramQDout : in slv(DATA_W_G-1 downto 0); -- bramQ.first + bramQDeq : out sl; -- dequeue upstream bramQ + -- pipeOut : PipeOut#(DataStream) (downstream consumer) + pipeOutDeq : in sl; -- consumer dequeues pipeOut + pipeOutFirst : out slv(DATA_W_G-1 downto 0); -- pipeOut.first + pipeOutNotEmpty : out sl; -- pipeOut.notEmpty + -- notEmpty() method result (parent payloadNotEmpty) + notEmpty : out sl); +end entity ConnectBramQ2PipeOutConAndGen; + +architecture rtl of ConnectBramQ2PipeOutConAndGen is + + -- U_PostBramQ interface signals (DataStream, DATA_W_G bits) + signal postBramQNotFull : sl; + signal postBramQValid : sl; -- = postBramQ.notEmpty (FWFT) + signal postBramQDout : slv(DATA_W_G-1 downto 0); + signal postBramQWrEn : sl; + signal postBramQRdEn : sl; + + -- Upstream->skid enqueue fire condition (Mealy, gated against flush) + signal enqFire : sl; + + -- FIFO reset line: level = rst OR clearEnI (BSV postBramQ.clear) + signal fifoRst : sl; + +begin + + -- FIFO clear (OQ-FSM-CB-3 / OQ-FSM-01, RESOLVED): level-sensitive flush. + fifoRst <= rst or clearEnI; + + -- Upstream enqueue handshake (mkConnection rl_connect): fire when the + -- upstream has a fragment and the skid FIFO can accept it. Suppressed during + -- a clear flush so we do not dequeue bramQ into a FIFO being emptied. + enqFire <= bramQNotEmpty and postBramQNotFull and (not clearEnI); + + bramQDeq <= enqFire; -- dequeue upstream bramQ (Get side) + postBramQWrEn <= enqFire; -- enqueue into skid FIFO + + -- Downstream dequeue handshake (toPipeOut): decoupled, every-cycle strobe. + postBramQRdEn <= pipeOutDeq; + + -- pipeOut method wiring (pure combinational re-export of the skid FIFO front) + pipeOutFirst <= postBramQDout; + pipeOutNotEmpty <= postBramQValid; + + -- notEmpty() method: upstream has data AND skid FIFO has data + notEmpty <= bramQNotEmpty and postBramQValid; + + --------------------------------------------------------------------------- + -- U_PostBramQ : surf.Fifo + -- Internal skid FIFO (BSV postBramQ <- mkFIFOF). Write side = upstream + -- enqueue (enqFire / bramQDout); read side = downstream pipeOut dequeue. + --------------------------------------------------------------------------- + U_PostBramQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DATA_W_G, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => postBramQWrEn, + din => bramQDout, -- pass-through of upstream head + full => open, + not_full => postBramQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => postBramQRdEn, + dout => postBramQDout, + valid => postBramQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd b/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd new file mode 100644 index 0000000000..b77286963f --- /dev/null +++ b/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd @@ -0,0 +1,172 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Byte-for-byte twin of ConnectBramQ2PipeOutConAndGen (the two copies exist +-- only because mkConnectBramQ2PipeOut is defined once per BSV file; the bodies +-- are identical). This entity mirrors that one; only the source/instantiation +-- line references and OQ ids differ (OQ-FSM-CBG-1/-2/-3 vs CB-1/-2/-3). +-- +-- Skid / output-register stage. Pulls fragments out of an upstream FIFO +-- (bramQ, a module argument — exposed here as a Get/dequeue handshake on +-- ports, NOT instantiated) into a small internal skid FIFO (postBramQ), and +-- re-exposes that internal FIFO as a PipeOut. +-- +-- There is NO explicit state register and NO data-dependent control flow: +-- per the FSM spec (§State register / §Output style) the only "machine" is the +-- implicit mkConnection transfer rule, gated solely by the two FIFOs' +-- full/empty flags. This entity is therefore emitted as a *pure structural +-- wrapper* — one surf.Fifo plus combinational glue — with NO two-process FSM +-- and NO RegType (the only registered storage lives inside U_PostBramQ). +-- +-- BramPipe interface (3 live methods restored per OQ-FSM-CBG-2; mapping.json +-- listed only pipeOutPort): +-- pipeOut : PipeOut#(DataStream) -> first/deq/notEmpty handshake ports +-- clear() : Action -> clearEnI (synchronous flush of postBramQ) +-- notEmpty : Bool -> notEmpty output +-- (pipeOut->lines 2128/2631, clear->line 2148, notEmpty->line 2632.) +-- +-- Two independent, conflict-free handshakes through the one FIFO: +-- * Upstream enqueue (mkConnection rl_connect, line 1971): +-- fire = bramQNotEmpty AND postBramQNotFull +-- -> bramQDeq, postBramQWrEn, postBramQDin = bramQDout +-- * Downstream dequeue (toPipeOut, line 1973): +-- postBramQRdEn = pipeOutDeq +-- They may both occur in the same cycle (opposite ends of a FIFO). +-- +-- clear() mapping (OQ-FSM-CBG-3, resolved via OQ-FSM-01 in +-- out/03-fsm/RESOLVED.md): +-- surf.Fifo has no dedicated clear port; BSV postBramQ.clear is modelled by +-- asserting the Fifo rst, OR'd with the structural reset: +-- fifoRst <= rst or clearEnI +-- surf.FifoSync (GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, RST_POLARITY_G='1') +-- holds the FIFO logically empty for the whole asserted window (level-safe; +-- no pulse generator). The upstream enqueue (bramQDeq / postBramQWrEn) is +-- SUPPRESSED while clearEnI='1' (fsm.md §Conflicts/scheduling) so a fragment +-- is not dequeued from the upstream bramQ only to be discarded by the flush. +-- +-- Width (OQ-FSM-CBG-1 + project-wide OQ-FSM-H2DS-02, RESOLVED): +-- DataStream = data(256)+byteEn(32)+isFirst(1)+isLast(1) = 290 bits. +-- The FSM spec / mapping.json carry the stale inventory value 321; per the +-- OQ-FSM-H2DS-02 resolution ("apply consistently at emit") and OQ-FSM-CPG-1 +-- ("backfill the siblings"), this entity uses DATA_W_G=290. +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, block RAM +-- (BSV postBramQ <- mkFIFOF). ADDR_WIDTH_G=4 (surf.Fifo min; +-- the BSV 2-deep skid maps to depth-16 — extra buffering only, +-- functionally equivalent for a skid stage). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ConnectBramQ2PipeOutGen is + generic ( + TPD_G : time := 1 ns; + DATA_W_G : positive := 290); -- DataStream width (OQ-FSM-H2DS-02) + port ( + clk : in sl; + rst : in sl; -- active-high sync reset + -- clear() method (Action): synchronous flush of the internal skid FIFO + clearEnI : in sl; + -- Upstream bramQ : Get#(DataStream) handshake (bramQ is a module argument) + bramQNotEmpty : in sl; -- bramQ.notEmpty (first valid) + bramQDout : in slv(DATA_W_G-1 downto 0); -- bramQ.first + bramQDeq : out sl; -- dequeue upstream bramQ + -- pipeOut : PipeOut#(DataStream) (downstream consumer) + pipeOutDeq : in sl; -- consumer dequeues pipeOut + pipeOutFirst : out slv(DATA_W_G-1 downto 0); -- pipeOut.first + pipeOutNotEmpty : out sl; -- pipeOut.notEmpty + -- notEmpty() method result (parent payloadNotEmpty) + notEmpty : out sl); +end entity ConnectBramQ2PipeOutGen; + +architecture rtl of ConnectBramQ2PipeOutGen is + + -- U_PostBramQ interface signals (DataStream, DATA_W_G bits) + signal postBramQNotFull : sl; + signal postBramQValid : sl; -- = postBramQ.notEmpty (FWFT) + signal postBramQDout : slv(DATA_W_G-1 downto 0); + signal postBramQWrEn : sl; + signal postBramQRdEn : sl; + + -- Upstream->skid enqueue fire condition (Mealy, gated against flush) + signal enqFire : sl; + + -- FIFO reset line: level = rst OR clearEnI (BSV postBramQ.clear) + signal fifoRst : sl; + +begin + + -- FIFO clear (OQ-FSM-CBG-3 / OQ-FSM-01, RESOLVED): level-sensitive flush. + fifoRst <= rst or clearEnI; + + -- Upstream enqueue handshake (mkConnection rl_connect): fire when the + -- upstream has a fragment and the skid FIFO can accept it. Suppressed during + -- a clear flush so we do not dequeue bramQ into a FIFO being emptied. + enqFire <= bramQNotEmpty and postBramQNotFull and (not clearEnI); + + bramQDeq <= enqFire; -- dequeue upstream bramQ (Get side) + postBramQWrEn <= enqFire; -- enqueue into skid FIFO + + -- Downstream dequeue handshake (toPipeOut): decoupled, every-cycle strobe. + postBramQRdEn <= pipeOutDeq; + + -- pipeOut method wiring (pure combinational re-export of the skid FIFO front) + pipeOutFirst <= postBramQDout; + pipeOutNotEmpty <= postBramQValid; + + -- notEmpty() method: upstream has data AND skid FIFO has data + notEmpty <= bramQNotEmpty and postBramQValid; + + --------------------------------------------------------------------------- + -- U_PostBramQ : surf.Fifo + -- Internal skid FIFO (BSV postBramQ <- mkFIFOF). Write side = upstream + -- enqueue (enqFire / bramQDout); read side = downstream pipeOut dequeue. + --------------------------------------------------------------------------- + U_PostBramQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DATA_W_G, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => postBramQWrEn, + din => bramQDout, -- pass-through of upstream head + full => open, + not_full => postBramQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => postBramQRdEn, + dout => postBramQDout, + valid => postBramQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQConAndGen.vhd b/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQConAndGen.vhd new file mode 100644 index 0000000000..fb02e0858f --- /dev/null +++ b/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQConAndGen.vhd @@ -0,0 +1,198 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Two-stage forwarding / skid wrapper around an externally-owned BRAM FIFO. +-- It (1) pushes fragments from the upstream pipeIn into the external bramQ, and +-- (2) pulls them out of bramQ into a small internal skid FIFO (postBramQ) which +-- it re-exposes as a PipeOut. +-- +-- Difference vs. the sibling ConnectBramQ2PipeOutConAndGen: that adapter has a +-- SINGLE mkConnection (bramQ -> postBramQ). This one has TWO — it also performs +-- the upstream pipeIn -> bramQ enqueue, so this entity drives BOTH the put and +-- the get ports of the external bramQ. +-- +-- There is NO explicit state register and NO data-dependent control flow: per +-- the FSM spec (§State register / §Output style) the only "machines" are the two +-- implicit mkConnection transfer rules, each gated solely by the relevant FIFOs' +-- full/empty flags. This entity is therefore emitted as a *pure structural +-- wrapper* — one surf.Fifo plus combinational glue — with NO two-process FSM and +-- NO RegType (the only registered storage local to this entity lives inside +-- U_PostBramQ; bramQ is registered storage in the parent). +-- +-- BramPipe interface (3 live methods + the pipeIn input arg, restored per +-- OQ-FSM-CP-1 / OQ-FSM-CP-2; mapping.json listed only "pipeInPort"): +-- pipeIn : PipeOut#(DataStream) -> input handshake (notEmpty/first in, deq out) +-- pipeOut : PipeOut#(DataStream) -> first/deq/notEmpty handshake ports +-- clear() : Action -> clearEnI (synchronous flush of postBramQ) +-- notEmpty : Bool -> notEmpty output +-- bramQ (parent-owned) is exposed as a put+get handshake (wrEn/din/notFull and +-- deq/first/notEmpty). +-- +-- Three independent, conflict-free handshakes (fsm.md §Transition table): +-- * Stage 1 — pipeIn -> bramQ enqueue (mkConnection rl_in2bram, line 535): +-- fire1 = pipeInNotEmpty AND bramQNotFull +-- -> pipeInDeq, bramQWrEn, bramQDin = pipeInFirst +-- * Stage 2 — bramQ -> postBramQ skid (mkConnection rl_bram2skid, line 536): +-- fire2 = bramQNotEmpty AND postBramQNotFull (suppressed during flush) +-- -> bramQDeq, postBramQWrEn, postBramQDin = bramQFirst +-- * Downstream — pipeOut dequeue (toPipeOut, line 538): +-- postBramQRdEn = pipeOutDeq +-- They touch distinct FIFO ports and may all occur in the same cycle. +-- +-- clear() mapping (OQ-FSM-CP-3, resolved via OQ-FSM-01 in +-- out/03-fsm/RESOLVED.md): +-- surf.Fifo has no dedicated clear port; BSV postBramQ.clear is modelled by +-- asserting the Fifo rst, OR'd with the structural reset: +-- fifoRst <= rst or clearEnI +-- surf.FifoSync (GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, RST_POLARITY_G='1') +-- holds the FIFO logically empty for the whole asserted window (level-safe; no +-- pulse generator). clear() flushes ONLY postBramQ (BSV clear method, lines +-- 539-541); the external bramQ is cleared separately by the parent +-- (payloadBufQ.clear, line 790). The stage-2 skid enqueue +-- (bramQDeq / postBramQWrEn) is SUPPRESSED while clearEnI='1' so a fragment is +-- not dequeued from bramQ only to be discarded by the flush. The stage-1 +-- pipeIn -> bramQ enqueue is NOT suppressed (it does not touch postBramQ). +-- +-- Width (OQ-FSM-CP-1 + project-wide OQ-FSM-H2DS-02, RESOLVED): +-- DataStream = data(256)+byteEn(32)+isFirst(1)+isLast(1) = 290 bits. +-- The FSM spec / mapping.json carry the stale inventory value 321; per the +-- OQ-FSM-H2DS-02 resolution ("apply consistently at emit") and OQ-FSM-CPG-1 +-- ("backfill the ConAndGen siblings"), this entity uses DATA_W_G=290. +-- +-- SURF components instantiated (source: +-- surf-catalogue-prj/surf/base/fifo/rtl/Fifo.vhd): +-- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, block RAM +-- (BSV postBramQ <- mkFIFOF). ADDR_WIDTH_G=4 (surf.Fifo min; +-- the BSV 2-deep skid maps to depth-16 — extra buffering only, +-- functionally equivalent for a skid stage). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ConnectPipeOut2BramQConAndGen is + generic ( + TPD_G : time := 1 ns; + DATA_W_G : positive := 290); -- DataStream width (OQ-FSM-H2DS-02) + port ( + clk : in sl; + rst : in sl; -- active-high sync reset + -- clear() method (Action): synchronous flush of the internal skid FIFO only + clearEnI : in sl; + -- pipeIn : PipeOut#(DataStream) input arg (upstream DataStreamPipeOut) + pipeInNotEmpty : in sl; -- pipeIn.notEmpty (first valid) + pipeInFirst : in slv(DATA_W_G-1 downto 0); -- pipeIn.first + pipeInDeq : out sl; -- dequeue upstream pipeIn + -- bramQ : parent-owned BRAM buffer (put + get handshake; NOT instantiated) + bramQNotFull : in sl; -- bramQ.notFull (can enqueue) + bramQWrEn : out sl; -- enqueue into bramQ + bramQDin : out slv(DATA_W_G-1 downto 0); -- bramQ enqueue data + bramQNotEmpty : in sl; -- bramQ.notEmpty (first valid) + bramQFirst : in slv(DATA_W_G-1 downto 0); -- bramQ.first + bramQDeq : out sl; -- dequeue bramQ + -- pipeOut : PipeOut#(DataStream) (downstream consumer) + pipeOutDeq : in sl; -- consumer dequeues pipeOut + pipeOutFirst : out slv(DATA_W_G-1 downto 0); -- pipeOut.first + pipeOutNotEmpty : out sl; -- pipeOut.notEmpty + -- notEmpty() method result (parent BramPipe) + notEmpty : out sl); +end entity ConnectPipeOut2BramQConAndGen; + +architecture rtl of ConnectPipeOut2BramQConAndGen is + + -- U_PostBramQ interface signals (DataStream, DATA_W_G bits) + signal postBramQNotFull : sl; + signal postBramQValid : sl; -- = postBramQ.notEmpty (FWFT) + signal postBramQDout : slv(DATA_W_G-1 downto 0); + signal postBramQWrEn : sl; + signal postBramQRdEn : sl; + + -- Stage-1 (pipeIn -> bramQ) and stage-2 (bramQ -> postBramQ) fire conditions + signal fire1 : sl; -- upstream enqueue (Mealy) + signal fire2 : sl; -- skid enqueue (Mealy, gated) + + -- FIFO reset line: level = rst OR clearEnI (BSV postBramQ.clear) + signal fifoRst : sl; + +begin + + -- FIFO clear (OQ-FSM-CP-3 / OQ-FSM-01, RESOLVED): level-sensitive flush of the + -- internal skid FIFO only. + fifoRst <= rst or clearEnI; + + -- Stage 1: pipeIn -> bramQ enqueue (mkConnection rl_in2bram). Fire when the + -- upstream has a fragment and the external bramQ can accept it. NOT suppressed + -- by clear (clear flushes postBramQ, not bramQ). + fire1 <= pipeInNotEmpty and bramQNotFull; + pipeInDeq <= fire1; -- dequeue upstream pipeIn (Get side) + bramQWrEn <= fire1; -- enqueue into external bramQ (Put side) + bramQDin <= pipeInFirst; -- pass-through of upstream head + + -- Stage 2: bramQ -> postBramQ skid enqueue (mkConnection rl_bram2skid). Fire + -- when bramQ has a fragment and the skid FIFO can accept it. Suppressed during + -- a clear flush so we do not dequeue bramQ into a FIFO being emptied. + fire2 <= bramQNotEmpty and postBramQNotFull and (not clearEnI); + bramQDeq <= fire2; -- dequeue external bramQ (Get side) + postBramQWrEn <= fire2; -- enqueue into skid FIFO + + -- Downstream dequeue handshake (toPipeOut): decoupled, every-cycle strobe. + postBramQRdEn <= pipeOutDeq; + + -- pipeOut method wiring (pure combinational re-export of the skid FIFO front) + pipeOutFirst <= postBramQDout; + pipeOutNotEmpty <= postBramQValid; + + -- notEmpty() method: external bramQ has data AND skid FIFO has data + notEmpty <= bramQNotEmpty and postBramQValid; + + --------------------------------------------------------------------------- + -- U_PostBramQ : surf.Fifo + -- Internal skid FIFO (BSV postBramQ <- mkFIFOF). Write side = stage-2 skid + -- enqueue (fire2 / bramQFirst); read side = downstream pipeOut dequeue. + --------------------------------------------------------------------------- + U_PostBramQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DATA_W_G, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => postBramQWrEn, + din => bramQFirst, -- pass-through of bramQ head + full => open, + not_full => postBramQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => postBramQRdEn, + dout => postBramQDout, + valid => postBramQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd b/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd new file mode 100644 index 0000000000..5751746b82 --- /dev/null +++ b/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd @@ -0,0 +1,201 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Two-stage forwarding / skid wrapper around an externally-owned BRAM FIFO. +-- It (1) pushes fragments from the upstream pipeIn into the external bramQ, and +-- (2) pulls them out of bramQ into a small internal skid FIFO (postBramQ) which +-- it re-exposes as a PipeOut. +-- +-- Identical in structure to ConnectPipeOut2BramQConAndGen: that adapter has +-- the same two mkConnection rules (pipeIn -> bramQ enqueue, bramQ -> +-- postBramQ skid), driving both the put and the get ports of the external +-- bramQ. Only the (absent) instantiation context and the data width differ +-- (see below). +-- +-- There is NO explicit state register and NO data-dependent control flow: per +-- the FSM spec (§State register / §Output style) the only "machines" are the two +-- implicit mkConnection transfer rules, each gated solely by the relevant FIFOs' +-- full/empty flags. This entity is therefore emitted as a *pure structural +-- wrapper* — one surf.Fifo plus combinational glue — with NO two-process FSM and +-- NO RegType (the only registered storage local to this entity lives inside +-- U_PostBramQ; bramQ is registered storage outside this entity's scope). +-- +-- BramPipe interface (3 live methods + the pipeIn input arg, restored per +-- OQ-FSM-CPG-1 / OQ-FSM-CPG-2; mapping.json listed only "pipeInPort"): +-- pipeIn : PipeOut#(anytype) -> input handshake (notEmpty/first in, deq out) +-- pipeOut : PipeOut#(anytype) -> first/deq/notEmpty handshake ports +-- clear() : Action -> clearEnI (synchronous flush of postBramQ) +-- notEmpty : Bool -> notEmpty output +-- bramQ (module argument, no in-scope owner) is exposed as a put+get handshake +-- (wrEn/din/notFull and deq/first/notEmpty). +-- +-- Three independent, conflict-free handshakes (fsm.md §Transition table): +-- * Stage 1 — pipeIn -> bramQ enqueue (mkConnection rl_in2bram, line 1985): +-- fire1 = pipeInNotEmpty AND bramQNotFull +-- -> pipeInDeq, bramQWrEn, bramQDin = pipeInFirst +-- * Stage 2 — bramQ -> postBramQ skid (mkConnection rl_bram2skid, line 1986): +-- fire2 = bramQNotEmpty AND postBramQNotFull (suppressed during flush) +-- -> bramQDeq, postBramQWrEn, postBramQDin = bramQFirst +-- * Downstream — pipeOut dequeue (toPipeOut, line 1988): +-- postBramQRdEn = pipeOutDeq +-- They touch distinct FIFO ports and may all occur in the same cycle. +-- +-- clear() mapping (OQ-FSM-CPG-3, resolved via OQ-FSM-01 in +-- out/03-fsm/RESOLVED.md): +-- surf.Fifo has no dedicated clear port; BSV postBramQ.clear is modelled by +-- asserting the Fifo rst, OR'd with the structural reset: +-- fifoRst <= rst or clearEnI +-- surf.FifoSync (GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, RST_POLARITY_G='1') +-- holds the FIFO logically empty for the whole asserted window (level-safe; no +-- pulse generator). clear() flushes ONLY postBramQ (BSV clear method, lines +-- 1989-1991); the external bramQ has no in-scope owner to clear it (it would +-- be cleared by whatever owns it). The stage-2 skid enqueue +-- (bramQDeq / postBramQWrEn) is SUPPRESSED while clearEnI='1' so a fragment is +-- not dequeued from bramQ only to be discarded by the flush. The stage-1 +-- pipeIn -> bramQ enqueue is NOT suppressed (it does not touch postBramQ). +-- +-- Width (OQ-FSM-CPG-1, per the project-wide OQ-FSM-H2DS-02 resolution): +-- DataStream = data(256)+byteEn(32)+isFirst(1)+isLast(1) = 290 bits. +-- This entity has no concrete instantiation site to trace a width from (see +-- dead-code note above); per construction parity with its three siblings, +-- which all carry DataStream through this exact adapter shape, DATA_W_G +-- defaults to 290 — the RESOLVED DataStream width, not the stale 321 the +-- three sibling .vhd/specs still carry (pre-dates the OQ-FSM-H2DS-02 fix). +-- +-- SURF components instantiated (source: +-- surf-catalogue-prj/surf/base/fifo/rtl/Fifo.vhd): +-- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, block RAM +-- (BSV postBramQ <- mkFIFOF). ADDR_WIDTH_G=4 (surf.Fifo min; +-- the BSV 2-deep skid maps to depth-16 — extra buffering only, +-- functionally equivalent for a skid stage). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ConnectPipeOut2BramQGen is + generic ( + TPD_G : time := 1 ns; + DATA_W_G : positive := 290); -- DataStream width (OQ-FSM-CPG-1 / OQ-FSM-H2DS-02) + port ( + clk : in sl; + rst : in sl; -- active-high sync reset + -- clear() method (Action): synchronous flush of the internal skid FIFO only + clearEnI : in sl; + -- pipeIn : PipeOut#(anytype) input arg (upstream PipeOut, no in-scope owner) + pipeInNotEmpty : in sl; -- pipeIn.notEmpty (first valid) + pipeInFirst : in slv(DATA_W_G-1 downto 0); -- pipeIn.first + pipeInDeq : out sl; -- dequeue upstream pipeIn + -- bramQ : external BRAM buffer (put + get handshake; NOT instantiated, no in-scope owner) + bramQNotFull : in sl; -- bramQ.notFull (can enqueue) + bramQWrEn : out sl; -- enqueue into bramQ + bramQDin : out slv(DATA_W_G-1 downto 0); -- bramQ enqueue data + bramQNotEmpty : in sl; -- bramQ.notEmpty (first valid) + bramQFirst : in slv(DATA_W_G-1 downto 0); -- bramQ.first + bramQDeq : out sl; -- dequeue bramQ + -- pipeOut : PipeOut#(anytype) (downstream consumer) + pipeOutDeq : in sl; -- consumer dequeues pipeOut + pipeOutFirst : out slv(DATA_W_G-1 downto 0); -- pipeOut.first + pipeOutNotEmpty : out sl; -- pipeOut.notEmpty + -- notEmpty() method result (BramPipe) + notEmpty : out sl); +end entity ConnectPipeOut2BramQGen; + +architecture rtl of ConnectPipeOut2BramQGen is + + -- U_PostBramQ interface signals (DataStream, DATA_W_G bits) + signal postBramQNotFull : sl; + signal postBramQValid : sl; -- = postBramQ.notEmpty (FWFT) + signal postBramQDout : slv(DATA_W_G-1 downto 0); + signal postBramQWrEn : sl; + signal postBramQRdEn : sl; + + -- Stage-1 (pipeIn -> bramQ) and stage-2 (bramQ -> postBramQ) fire conditions + signal fire1 : sl; -- upstream enqueue (Mealy) + signal fire2 : sl; -- skid enqueue (Mealy, gated) + + -- FIFO reset line: level = rst OR clearEnI (BSV postBramQ.clear) + signal fifoRst : sl; + +begin + + -- FIFO clear (OQ-FSM-CPG-3 / OQ-FSM-01, RESOLVED): level-sensitive flush of the + -- internal skid FIFO only. + fifoRst <= rst or clearEnI; + + -- Stage 1: pipeIn -> bramQ enqueue (mkConnection rl_in2bram). Fire when the + -- upstream has a fragment and the external bramQ can accept it. NOT suppressed + -- by clear (clear flushes postBramQ, not bramQ). + fire1 <= pipeInNotEmpty and bramQNotFull; + pipeInDeq <= fire1; -- dequeue upstream pipeIn (Get side) + bramQWrEn <= fire1; -- enqueue into external bramQ (Put side) + bramQDin <= pipeInFirst; -- pass-through of upstream head + + -- Stage 2: bramQ -> postBramQ skid enqueue (mkConnection rl_bram2skid). Fire + -- when bramQ has a fragment and the skid FIFO can accept it. Suppressed during + -- a clear flush so we do not dequeue bramQ into a FIFO being emptied. + fire2 <= bramQNotEmpty and postBramQNotFull and (not clearEnI); + bramQDeq <= fire2; -- dequeue external bramQ (Get side) + postBramQWrEn <= fire2; -- enqueue into skid FIFO + + -- Downstream dequeue handshake (toPipeOut): decoupled, every-cycle strobe. + postBramQRdEn <= pipeOutDeq; + + -- pipeOut method wiring (pure combinational re-export of the skid FIFO front) + pipeOutFirst <= postBramQDout; + pipeOutNotEmpty <= postBramQValid; + + -- notEmpty() method: external bramQ has data AND skid FIFO has data + notEmpty <= bramQNotEmpty and postBramQValid; + + --------------------------------------------------------------------------- + -- U_PostBramQ : surf.Fifo + -- Internal skid FIFO (BSV postBramQ <- mkFIFOF). Write side = stage-2 skid + -- enqueue (fire2 / bramQFirst); read side = downstream pipeOut dequeue. + --------------------------------------------------------------------------- + U_PostBramQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DATA_W_G, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => postBramQWrEn, + din => bramQFirst, -- pass-through of bramQ head + full => open, + not_full => postBramQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => postBramQRdEn, + dout => postBramQDout, + valid => postBramQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ConnectionWithAction.vhd b/ethernet/RoCEv2/rtl/ConnectionWithAction.vhd new file mode 100644 index 0000000000..060cd5eea1 --- /dev/null +++ b/ethernet/RoCEv2/rtl/ConnectionWithAction.vhd @@ -0,0 +1,97 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Behaviour +-- --------- +-- A purely combinational hand-shaken wire-through. The BSV `connect` rule fires +-- whenever upstream has data (getIn.notEmpty) AND downstream can accept it +-- (putOut.notFull); on firing it forwards the datum and dequeues upstream. The +-- module has NO state register driving control flow, so this entity is emitted +-- as a combinational block (no two-process FSM, no clk/rst): there is genuinely +-- no hardware to clock. +-- * bthReg (BSV mkRegU, Reg#(BTH), 96 bits) is DEAD CODE — never read or +-- written in the module body. It is intentionally NOT emitted. See +-- OQ-FSM-15 (RESOLVED-DESIGN-NOTE). +-- +-- connectAction (OQ-FSM-16, resolved: hardwire) +-- -------------------------------------------- +-- The BSV `connectAction` is a function-valued elaboration parameter; VHDL has +-- no function-type ports. At the single instantiation site the action is: +-- function Action deqActionFunc(DataStream dataStream); +-- action if (dataStream.isLast) psnPipeIn.deq; endaction +-- endfunction +-- It is hardwired here as a 1-bit output strobe `psnDeqEn`, asserted when the +-- rule fires AND the forwarded datum's isLast bit is set. The parent +-- (CombineHeaderAndPayload) wires psnDeqEn to its PSN-queue dequeue/read enable. +-- +-- Width / bit-layout trace (CLAUDE.md hard rule: trace widths, never invent) +-- -------------------------------------------------------------------------- +-- DataStream (src-bsv/DataTypes.bsv:183-188) deriving(Bits) packs the first +-- field in the MSBs and the last field in the LSBs: +-- { DATA data; ByteEn byteEn; Bool isFirst; Bool isLast } +-- DATA = Bit#(DATA_BUS_WIDTH) = 256 (Settings.bsv:10) +-- ByteEn = Bit#(DATA_BUS_BYTE_WIDTH) = 32 (TDiv 256/8) +-- isFirst = 1, isLast = 1 +-- => total = 290 bits ; isLast = bit 0 (LSB), isFirst = bit 1. +-- NOTE: the FSM spec stated 321 bits; that is incorrect — 290 is the traced +-- value. isLast at LSB is independent of DATA_W_G (always the last packed field). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ConnectionWithAction is + generic ( + TPD_G : time := 1 ns; + -- Width of the streamed datum (DataStream = 290 bits at the in-scope site). + DATA_W_G : positive := 290); + port ( + -- Upstream source (BSV getIn : Get#(anytype)) + dataIn : in slv(DATA_W_G-1 downto 0); -- getIn.first + upstreamValid : in sl; -- getIn.notEmpty + deqUpstream : out sl; -- getIn.get (dequeue ack) + -- Downstream sink (BSV putOut : Put#(anytype)) + dataOut : out slv(DATA_W_G-1 downto 0); -- putOut.put data + dataOutValid : out sl; -- putOut.put enable + downstreamReady : in sl; -- putOut.notFull + -- Hardwired connectAction strobe (OQ-FSM-16): psnPipeIn.deq when isLast + psnDeqEn : out sl); +end entity ConnectionWithAction; + +architecture rtl of ConnectionWithAction is + + -- isLast occupies bit 0 of the packed DataStream (last struct field -> LSB). + constant ISLAST_BIT_C : natural := 0; + + -- Rule `connect` fires iff upstream has data and downstream can accept it. + signal fire : sl; + +begin + + -- conflict_free single rule: fire = getIn.notEmpty AND putOut.notFull + fire <= upstreamValid and downstreamReady; + + -- putOut.put(data): forward the datum; zeroed when idle (matches spec row 2). + dataOut <= dataIn after TPD_G when fire = '1' else + (others => '0') after TPD_G; + dataOutValid <= fire after TPD_G; + + -- getIn.get: dequeue upstream on the same cycle the datum is forwarded. + deqUpstream <= fire after TPD_G; + + -- connectAction(data): psnPipeIn.deq when forwarded datum's isLast is set. + psnDeqEn <= (fire and dataIn(ISLAST_BIT_C)) after TPD_G; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/CountCF.vhd b/ethernet/RoCEv2/rtl/CountCF.vhd new file mode 100644 index 0000000000..5f5753361f --- /dev/null +++ b/ethernet/RoCEv2/rtl/CountCF.vhd @@ -0,0 +1,250 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Conflict-free up/down counter. incrOne()/decrOne() each enqueue a "tick" +-- into a small FIFO; every cycle the counter applies the net delta +-- (+1 / -1 / 0) of whichever ticks are pending, and _write() overrides the +-- count and atomically clears both FIFOs. +-- +-- There is no enumerated control FSM (single implied state OPER_S). The only +-- true registered state is cntReg. The BSV CReg(2) scratch registers +-- (writeReg/incrReg/decrReg) are pure intra-cycle forwarding signals and +-- collapse to combinational logic here — see OQ-FSM-02. +-- +-- SURF components instantiated: +-- * U_IncrQ : surf.Fifo <- BSV incrQ (mkFIFOF FIFOF#(Bool), 1-bit) +-- * U_DecrQ : surf.Fifo <- BSV decrQ (mkFIFOF FIFOF#(Bool), 1-bit) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- +-- BSV FIFOF.clear has NO equivalent SURF Fifo flush port (OQ-FSM-01, +-- RESOLVED). It is modelled by pulsing the synchronous Fifo rst for one cycle +-- on BOTH FIFOs in parallel (fifoRst = global rst OR clrStrobe), with +-- GEN_SYNC_FIFO_G => true, RST_ASYNC_G => false, RST_POLARITY_G => '1'. On the +-- clock edge the FifoSync FSM restores REG_INIT_C, zeroing the pointers in one +-- cycle — the BSV single-cycle, two-queue atomic clear. +-- +-- Clear-vs-enq ordering (OQ-FSM-01 open follow-up): BSV mkFIFOF schedules +-- clear AFTER enq, so when _write fires in the same cycle as incrOne/decrOne +-- the queue ends EMPTY (the enq is discarded). Here wr_en is left ungated: +-- when fifoRst asserts, FifoSync's synchronous reset dominates the concurrent +-- wr_en, dropping the write and emptying the FIFO — matching BSV. (Confirm in +-- cocotb.) +-- +-- NOTE: emitting does not prove equivalence — simulate this entity (cocotb) +-- before trusting it. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity CountCF is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_ASYNC_G : boolean := false; + WIDTH_G : positive := 8; -- count width = tSz of BSV anytype + RESET_VAL_G : slv := "00000000"; -- BSV mkCountCF 'resetVal' parameter (length must = WIDTH_G) + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- tick FIFO depth = 2**ADDR (BSV mkFIFOF depth 2; SURF min 4) + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- incrOne() method : enq a +1 tick (ready = incrQ not full) + incrOneEn : in sl; + incrOneRdy : out sl; + -- decrOne() method : enq a -1 tick (ready = decrQ not full) + decrOneEn : in sl; + decrOneRdy : out sl; + -- _write() method : override count and clear both tick FIFOs + writeEn : in sl; + writeVal : in slv(WIDTH_G-1 downto 0); + -- _read() method : current count (Moore, registered) + cntOut : out slv(WIDTH_G-1 downto 0)); +end CountCF; + +architecture rtl of CountCF is + + -- Only true registered state is the count (BSV cntReg <- mkReg(resetVal)). + type RegType is record + cntReg : slv(WIDTH_G-1 downto 0); + end record RegType; + + constant REG_INIT_C : RegType := ( + cntReg => RESET_VAL_G); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Tick FIFO payload is a constant 'True' (BSV enq(True)); only presence matters. + constant TICK_DIN_C : slv(0 downto 0) := "1"; + + -- SURF Fifo handshake/status (FWFT: valid = head present = BSV notEmpty) + signal incrValid : sl; + signal decrValid : sl; + signal incrNotFull : sl; + signal decrNotFull : sl; + signal incrDout : slv(0 downto 0); + signal decrDout : slv(0 downto 0); + + -- Mealy combinational outputs (BSV rule firing this cycle) + signal incrRdEn : sl; -- U_IncrQ.rd_en (increment rule deq) + signal decrRdEn : sl; -- U_DecrQ.rd_en (decrement rule deq) + + -- Atomic clear of both FIFOs (BSV write rule: incrQ.clear; decrQ.clear) + signal clrStrobe : sl; -- 1-cycle pulse when _write fires + signal rstActiveHigh : sl; -- global rst normalised to active high + signal fifoRst : sl; -- driven into both Fifo rst ports + +begin + + -- Elaboration sanity check: the reset value must be WIDTH_G bits wide. + assert (RESET_VAL_G'length = WIDTH_G) + report "CountCF: RESET_VAL_G length must equal WIDTH_G" severity failure; + + -- Method-readiness (implicit conditions) exposed as explicit ready outputs. + incrOneRdy <= incrNotFull; -- incrOne implicit cond: incrQ not full + decrOneRdy <= decrNotFull; -- decrOne implicit cond: decrQ not full + + -------------------------------------------------------------------------- + -- Atomic clear strobe (OQ-FSM-01): _write fires same-cycle as the BSV CReg + -- writeReg forwards _write -> write rule. fifoRst pulses both FIFOs' rst. + -------------------------------------------------------------------------- + clrStrobe <= writeEn; + rstActiveHigh <= rst when (RST_POLARITY_G = '1') else not rst; + fifoRst <= rstActiveHigh or clrStrobe; + + -------------------------------------------------------------------------- + -- BSV incrQ (mkFIFOF FIFOF#(Bool)) -> surf.Fifo + -- wr_en <- incrOneEn (incrOne method enq True); ungated so a same-cycle + -- clear (fifoRst) dominates the write, matching BSV clear-after-enq. + -------------------------------------------------------------------------- + U_IncrQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', -- clear strobe is active high (OQ-FSM-01) + RST_ASYNC_G => false, -- synchronous one-cycle clear (OQ-FSM-01) + GEN_SYNC_FIFO_G => true, -- must stay sync for one-cycle clear (OQ-FSM-01) + FWFT_EN_G => true, -- valid = head present = BSV notEmpty + MEMORY_TYPE_G => "distributed", -- LUTRAM read path (FifoRdFsm 1-cycle + -- branch). BRAM ("block") adds a DOB_REG + -- stage -> 2-cycle RAM read, inflating + -- enq->valid by one extra cycle. Distributed + -- is the correct primitive for a depth-2, + -- 1-bit tick FIFO and removes that stage. + -- NOTE: even distributed leaves a ~1-cycle + -- read-latency gap vs BSV mkFIFOF, inherent + -- to surf.Fifo's sync write-ptr -> read-FSM + -- handshake. Functionally equivalent; NOT + -- cycle-accurate to BSV. (OQ-FSM-03) + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => incrOneEn, + din => TICK_DIN_C, + not_full => incrNotFull, + rd_clk => clk, + rd_en => incrRdEn, + dout => incrDout, + valid => incrValid); + + -------------------------------------------------------------------------- + -- BSV decrQ (mkFIFOF FIFOF#(Bool)) -> surf.Fifo + -------------------------------------------------------------------------- + U_DecrQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", -- LUTRAM: 1-cycle read latency (see U_IncrQ) + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => decrOneEn, + din => TICK_DIN_C, + not_full => decrNotFull, + rd_clk => clk, + rd_en => decrRdEn, + dout => decrDout, + valid => decrValid); + + -------------------------------------------------------------------------- + -- Combinatorial : per-cycle priority action table (single state OPER_S). + -- priority: write > (net incr/decr delta). See CountCF.fsm.md. + -------------------------------------------------------------------------- + comb : process (decrValid, incrValid, r, rst, writeEn, writeVal) is + variable v : RegType; + variable incrDeqV : sl; + variable decrDeqV : sl; + begin + -- Latch the current value + v := r; + + -- Default Mealy strobes + incrDeqV := '0'; + decrDeqV := '0'; + + -- increment/decrement rules: gated off while _write fires (writeReg valid). + -- Each deqs its own FIFO independently when that FIFO is non-empty. + if (writeEn = '0') then + incrDeqV := incrValid; + decrDeqV := decrValid; + end if; + + -- cntReg update: write wins; otherwise apply the net +1/-1/0 delta. + if (writeEn = '1') then + v.cntReg := writeVal; + elsif (incrValid = '1') and (decrValid = '0') then + v.cntReg := slv(unsigned(r.cntReg) + 1); + elsif (incrValid = '0') and (decrValid = '1') then + v.cntReg := slv(unsigned(r.cntReg) - 1); + else + v.cntReg := r.cntReg; -- both ticks (net 0) or neither + end if; + + -- Synchronous Reset + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + -- Mealy outputs (combinational FIFO deq strobes) + incrRdEn <= incrDeqV; + decrRdEn <= decrDeqV; + + -- Moore output + cntOut <= r.cntReg; + end process comb; + + -------------------------------------------------------------------------- + -- Sequential + -------------------------------------------------------------------------- + seq : process (clk, rst) is + begin + if (RST_ASYNC_G) and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/DataStream2Header.vhd b/ethernet/RoCEv2/rtl/DataStream2Header.vhd new file mode 100644 index 0000000000..0463c9073b --- /dev/null +++ b/ethernet/RoCEv2/rtl/DataStream2Header.vhd @@ -0,0 +1,350 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Structural inverse of Header2DataStream. Re-accumulates a sequence of +-- 256-bit DataStream flits back into a single packed 593-bit HeaderRDMA word +-- and enqueues it into U_HeaderOutQ, which is exposed as the returned +-- PipeOut#(HeaderRDMA) interface (headerOutQValid/Dout/RdEn). +-- +-- Two input pipes are consumed (both opaque PipeOut arguments at the BSV call +-- site — NOT FIFOs instantiated here): +-- dataPipeIn : DataStreamPipeOut (290-bit DataStream flits) +-- headerMetaDataPipeIn : PipeOut#(HeaderMetaData) (17-bit meta word) +-- +-- FSM states (mapped from BSV busyReg : Reg#(Bool) <- mkReg(False)): +-- IDLE_S ('0') — waiting to pop the HeaderMetaData for the next header +-- BUSY_S ('1') — accumulating DataStream flits until isLast +-- +-- BSV rules implemented: +-- popHeaderMetaData (guard !busyReg) — IDLE_S row: latch HeaderMetaData, +-- deq headerMetaDataPipeIn, go BUSY_S. +-- accumulate (guard busyReg) — BUSY_S rows: shift each DataStream +-- fragment into the header accumulator; on isLast, +-- left-align and enqueue the completed HeaderRDMA. +-- +-- Mapping note (OQ-FSM-DS2H-01, see fsm.md §mismatch): +-- mapping.json / inventory describe an unrelated header/payload-split shape +-- (two outputs, payloadQ, rule `extract`). They are WRONG for this entity; +-- this file follows DataStream2Header.fsm.md, which is authoritative. +-- +-- Width / packing resolutions applied: +-- - DataStream width = 290 bits (OQ-FSM-H2DS-02 RESOLVED) +-- - HeaderRDMA / HeaderMetaData packing is first-field-at-MSB +-- (OQ-FSM-H2DS-04 / DS2H-05 RESOLVED) +-- - hdrInvalidFragBitNumReg / hdrInvalidFragByteNumReg ELIMINATED +-- (OQ-FSM-DS2H-02 RESOLVED): the final isLast left-shift is specialized +-- into the FSM per the HEADER_MAX_FRAG_NUM=2 invariant, mirroring +-- Header2DataStream's prepend side — no runtime barrel shifter, no +-- HeaderBitNum-width register. The shift amount (0 or 256 b) is fully +-- determined by which completing row fires: +-- row 3 (1-frag header, isFirst=isLast=1) → shift 256 → frag to high half +-- row 4 (2nd of 2-frag header, isLast=1) → shift 0 → already aligned +-- +-- Reset convention (judgment call, see report): +-- The fsm.md Inputs table notes "rst_n async active-low". This file uses +-- active-high SYNCHRONOUS rst to stay consistent with the sibling +-- Header2DataStream and with the surf.Fifo config used project-wide +-- (RST_POLARITY_G='1', RST_ASYNC_G=false). busyReg is mkReg(False) → +-- synchronous reset, matching this choice. There is NO software clear in +-- this module (no resetAndClear rule), so no clearAllI port exists. +-- +-- SURF components instantiated: +-- U_HeaderOutQ : surf.Fifo +-- DATA_WIDTH_G=593, FWFT, sync, block RAM (wide word; 2-cycle cold +-- latency, DOB reg) — source: surf/base/fifo/rtl/Fifo.vhd +-- +-- Scheduling / atomicity (fsm.md §scheduling): +-- accumulate's headerOutQ.enq is conditional (isLast branch) but BSV +-- all-or-nothing rule firing means the WHOLE rule (incl. dataPipeIn.deq) +-- does not fire when isLast='1' AND headerOutQFull='1'. Modelled here by +-- gating dataPipeInRdEn AND every register update of the completing rows on +-- headerOutQFull='0' — NOT merely gating headerOutQWrEn (would deq and lose +-- the fragment while the output FIFO is full). +-- +-- DataStream bit layout (BSV deriving(Bits), first-field-at-MSB): +-- [289:34] data[255:0] (256 bits) +-- [33:2] byteEn[31:0] (32 bits) +-- [1] isFirst +-- [0] isLast +-- +-- HeaderRDMA bit layout (BSV deriving(Bits), first-field-at-MSB): +-- [592:81] headerData[511:0] (512 bits) +-- [80:17] headerByteEn[63:0] (64 bits) +-- [16:10] headerLen[6:0] +-- [9:8] headerFragNum[1:0] (OVERWRITTEN with running count on enqueue) +-- [7:2] lastFragValidByteNum[5:0] +-- [1] hasPayload +-- [0] isEmptyHeader +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity DataStream2Header is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Upstream: DataStream pipe (dataPipeIn, 290 b per beat) + dataPipeInValid : in sl; -- dataPipeIn.notEmpty + dataPipeInData : in slv(289 downto 0); -- dataPipeIn.first + dataPipeInRdEn : out sl; -- dataPipeIn.deq + -- Upstream: HeaderMetaData pipe (headerMetaDataPipeIn, 17 b) + hdrMetaDataPipeInValid : in sl; -- headerMetaDataPipeIn.notEmpty + hdrMetaDataPipeInData : in slv(16 downto 0); -- headerMetaDataPipeIn.first + hdrMetaDataPipeInRdEn : out sl; -- headerMetaDataPipeIn.deq + -- Downstream: returned PipeOut#(HeaderRDMA) (read side of U_HeaderOutQ) + headerOutQValid : out sl; -- PipeOut.notEmpty + headerOutQDout : out slv(592 downto 0); -- PipeOut.first + headerOutQRdEn : in sl); -- PipeOut.deq +end entity DataStream2Header; + +architecture rtl of DataStream2Header is + + -- FSM state type (maps BSV busyReg: False→IDLE_S, True→BUSY_S) + type StateType is (IDLE_S, BUSY_S); + + type RegType is record + state : StateType; + rdmaHdrData : slv(511 downto 0); -- mkRegU — accumulating headerData + rdmaHdrByteEn : slv(63 downto 0); -- mkRegU — accumulating headerByteEn + rdmaHdrFragNum : slv(1 downto 0); -- mkRegU — running accumulated frag count + hdrMetaDataReg : slv(16 downto 0); -- mkRegU — latched HeaderMetaData + end record RegType; + + -- mkRegU fields set to '0' in REG_INIT_C: every one is written in IDLE_S / + -- the first BUSY_S fire before being read on completion (no correctness risk). + constant REG_INIT_C : RegType := ( + state => IDLE_S, + rdmaHdrData => (others => '0'), + rdmaHdrByteEn => (others => '0'), + rdmaHdrFragNum => (others => '0'), + hdrMetaDataReg => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_HeaderOutQ control signals (internal; driven by comb process) + signal headerOutQFull : sl; + signal headerOutQWrEn : sl; + signal headerOutQDin : slv(592 downto 0); + + -- Zero-padding constants for the left-align (isLast) shift specialization + constant ZERO_256_C : slv(255 downto 0) := (others => '0'); + constant ZERO_32_C : slv(31 downto 0) := (others => '0'); + +begin + + --------------------------------------------------------------------------- + -- U_HeaderOutQ : surf.Fifo + -- Holds completed HeaderRDMA words; its read side IS the returned + -- PipeOut#(HeaderRDMA) interface. DATA_WIDTH_G=593, FWFT, sync, block RAM. + -- rst wired directly (no software clear in this module). + --------------------------------------------------------------------------- + U_HeaderOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 593, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => headerOutQWrEn, + din => headerOutQDin, + full => headerOutQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => headerOutQRdEn, + dout => headerOutQDout, + valid => headerOutQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, + dataPipeInValid, dataPipeInData, + hdrMetaDataPipeInValid, hdrMetaDataPipeInData, + headerOutQFull) is + variable v : RegType; + variable fragData : slv(255 downto 0); + variable fragByteEn : slv(31 downto 0); + variable fragIsFirst : sl; + variable fragIsLast : sl; + begin + v := r; + + -- default Mealy outputs (deasserted; overridden below per transition) + dataPipeInRdEn <= '0'; + hdrMetaDataPipeInRdEn <= '0'; + headerOutQWrEn <= '0'; + headerOutQDin <= (others => '0'); + + -- DataStream field aliases (see bit layout in header) + fragData := dataPipeInData(289 downto 34); + fragByteEn := dataPipeInData(33 downto 2); + fragIsFirst := dataPipeInData(1); + fragIsLast := dataPipeInData(0); + + case r.state is + + -- --------------------------------------------------------------- + -- IDLE_S: popHeaderMetaData (guard !busyReg) + -- Latch the HeaderMetaData for the header about to arrive, deq the + -- meta pipe, advance to BUSY_S. Touches neither dataPipeIn nor + -- headerOutQ. hdrInvalidFrag* precompute is eliminated (DS2H-02). + -- --------------------------------------------------------------- + when IDLE_S => + if hdrMetaDataPipeInValid = '1' then + hdrMetaDataPipeInRdEn <= '1'; + v.hdrMetaDataReg := hdrMetaDataPipeInData; + v.state := BUSY_S; + end if; + + -- --------------------------------------------------------------- + -- BUSY_S: accumulate (guard busyReg) + -- Base guard for all rows: dataPipeInValid='1'. + -- --------------------------------------------------------------- + when BUSY_S => + if dataPipeInValid = '1' then + + -- Row 1: isFirst='1', isLast='0' — first of a 2-fragment header. + -- zeroExtend: fragment lands in the LOW half; stay BUSY_S. + if fragIsFirst = '1' and fragIsLast = '0' then + v.rdmaHdrData := ZERO_256_C & fragData; + v.rdmaHdrByteEn := ZERO_32_C & fragByteEn; + v.rdmaHdrFragNum := "01"; + dataPipeInRdEn <= '1'; + + -- Row 3: isFirst='1', isLast='1' — 1-fragment header, completes. + -- isLast shift = 256 b (1 invalid frag) specialized as slice + + -- zero-pad: frag moves to the HIGH (left-aligned) half. + -- Gated on !headerOutQFull (all-or-nothing, see header). + elsif fragIsFirst = '1' and fragIsLast = '1' then + if headerOutQFull = '0' then + headerOutQWrEn <= '1'; + headerOutQDin <= (fragData & ZERO_256_C) -- headerData [592:81] + & (fragByteEn & ZERO_32_C) -- headerByteEn [80:17] + & r.hdrMetaDataReg(16 downto 10) -- headerLen [16:10] + & "01" -- headerFragNum [9:8] = running count + & r.hdrMetaDataReg(7 downto 0); -- lastFragValidByteNum/hasPayload/isEmptyHeader [7:0] + dataPipeInRdEn <= '1'; + v.state := IDLE_S; + end if; + + -- Row 4: isFirst='0', isLast='1' — 2nd of a 2-fragment header, + -- completes. isLast shift = 0 (no invalid frag): the + -- shift-in accumulator already left-aligns it. + -- Gated on !headerOutQFull. + elsif fragIsFirst = '0' and fragIsLast = '1' then + if headerOutQFull = '0' then + headerOutQWrEn <= '1'; + headerOutQDin <= (r.rdmaHdrData(255 downto 0) & fragData) -- headerData [592:81] + & (r.rdmaHdrByteEn(31 downto 0) & fragByteEn) -- headerByteEn [80:17] + & r.hdrMetaDataReg(16 downto 10) -- headerLen [16:10] + & slv(unsigned(r.rdmaHdrFragNum) + 1) -- headerFragNum [9:8] = "10" + & r.hdrMetaDataReg(7 downto 0); -- [7:0] + dataPipeInRdEn <= '1'; + v.state := IDLE_S; + end if; + + -- Row 5: isFirst='0', isLast='0' — STRUCTURALLY UNREACHABLE under + -- HEADER_MAX_FRAG_NUM=2 / DATA_BUS_WIDTH=256 (OQ-FSM-DS2H-03). + -- Implemented for source fidelity (the BSV else arm): shift-in + -- accumulate, stay BUSY_S. Dead in the current build. + else + v.rdmaHdrData := r.rdmaHdrData(255 downto 0) & fragData; + v.rdmaHdrByteEn := r.rdmaHdrByteEn(31 downto 0) & fragByteEn; + v.rdmaHdrFragNum := slv(unsigned(r.rdmaHdrFragNum) + 1); + dataPipeInRdEn <= '1'; + end if; + + end if; + + end case; + + -- Synchronous reset (matches BSV mkReg(False) for busyReg) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + --------------------------------------------------------------------------- + -- Simulation-only assertions (OQ-FSM-DS2H-04): BSV immAssert calls have no + -- synthesizable effect. Emitted under translate_off for Stage 5 value. + --------------------------------------------------------------------------- + -- pragma translate_off + check : process (clk) is + begin + if rising_edge(clk) then + if rst = '0' then + -- popHeaderMetaData immAssert: headerLen (meta[16:10]) must be /= 0 + if (r.state = IDLE_S and hdrMetaDataPipeInValid = '1') then + assert hdrMetaDataPipeInData(16 downto 10) /= "0000000" + report "DataStream2Header: headerLen must be non-zero" + severity error; + end if; + -- accumulate immAsserts (completing fire): running headerFragNum must + -- equal the expected value latched in hdrMetaDataReg(9:8), and + -- genByteEn(headerLastFragValidByteNum) must equal fragByteEn. + -- TODO(OQ-FSM-DS2H-04): the genByteEn(...) == fragByteEn check needs + -- the BSV genByteEn helper; left as a TODO rather than an incorrect + -- assertion. The fragNum-match check is asserted below. + if (r.state = BUSY_S and dataPipeInValid = '1' + and dataPipeInData(0) = '1' and headerOutQFull = '0') then + if dataPipeInData(1) = '1' then -- 1-frag header (row 3) + assert r.hdrMetaDataReg(9 downto 8) = "01" + report "DataStream2Header: 1-frag header fragNum mismatch" + severity error; + else -- 2-frag header (row 4) + assert r.hdrMetaDataReg(9 downto 8) = slv(unsigned(r.rdmaHdrFragNum) + 1) + report "DataStream2Header: 2-frag header fragNum mismatch" + severity error; + end if; + end if; + end if; + end if; + end process check; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/DmaArbiter4Qp.vhd b/ethernet/RoCEv2/rtl/DmaArbiter4Qp.vhd new file mode 100644 index 0000000000..92c4826dcf --- /dev/null +++ b/ethernet/RoCEv2/rtl/DmaArbiter4Qp.vhd @@ -0,0 +1,329 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Pure structural interconnect. `mkDmaArbiter4QP` owns NO registered state, +-- NO rules and NO FIFOs of its own; it composes two proxy+arbiter pairs (one +-- per DMA direction) and routes their faces to the module boundary: +-- +-- read path : {dmaReadSrv4RQ , dmaReadSrv4SQ } --> U_DmaReadArb +-- --(downstream srv)--> U_DmaReadProxy --> dmaReadClt +-- write path : {dmaWriteSrv4RQ, dmaWriteSrv4SQ} --> U_DmaWriteArb +-- --(downstream srv)--> U_DmaWriteProxy --> dmaWriteClt +-- +-- Each direction is 2 upstream Servers (RQ = port 0, SQ = port 1) arbitrated +-- onto one downstream Server (the proxy's srvPort); the proxy's cltPort is the +-- aggregated Client toward the external DMA subsystem. All FIFO/RAM state +-- lives inside the children; this container only wires and computes the four +-- arbiter "finished" predicates (OQ-FSM-17 resolution). +-- +-- Because there is no state to translate, this architecture is emitted as pure +-- structural VHDL (four component instances + port maps + a handful of +-- concurrent glue assignments) rather than the SURF two-process comb/seq +-- template. There is no RegType / REG_INIT_C — mkDmaArbiter4QP has zero +-- mkReg/mkRegU/mkCReg fields (FSM spec §"State register": NONE). Same +-- convention as the sibling structural container SqQueuePair.vhd +-- (OQ-EMIT-SQQP-01). +-- +-- Child entity instances (each separately emitted): +-- U_DmaReadArb : work.ServerArbiter (PORT_COUNT_G=2) <- dmaReadSrvVec +-- U_DmaReadProxy : work.ServerProxy <- dmaReadProxy +-- U_DmaWriteArb : work.ServerArbiter (PORT_COUNT_G=2) <- dmaWriteSrvVec +-- U_DmaWriteProxy : work.ServerProxy <- dmaWriteProxy +-- +-- SURF components instantiated DIRECTLY by this entity: NONE. Every surf.Fifo +-- used by the DMA arbitration lives inside a child entity. +-- +-- Struct widths (traced from DataTypes.bsv; confirmed against DmaReadCntrlGen.vhd +-- lines 134/141 where DmaReadReq=176 and DmaReadResp=383 are used): +-- DmaReadReq = 176 = DmaReqSrcType(4)+QPN(24)+WorkReqID(64)+ADDR(64) +-- +PktLen(13)+IndexMR(7) +-- DmaReadResp = 383 = DmaReqSrcType(4)+QPN(24)+WorkReqID(64)+Bool(1) +-- +DataStream(290) +-- DmaWriteReq = 419 = DmaWriteMetaData(129)+DataStream(290) +-- [meta = DmaReqSrcType(4)+QPN(24)+ADDR(64)+PktLen(13)+PSN(24)] +-- DmaWriteResp = 53 = DmaReqSrcType(4)+QPN(24)+PSN(24)+Bool(1) +-- DataStream = 290 = DATA(256)+ByteEn(32)+isFirst(1)+isLast(1) +-- +-- Arbiter "finished" predicates (OQ-FSM-17: the parent, where the concrete type +-- is known, computes them and feeds them to the child as 1-bit inputs). BSV +-- packs the first struct field into the MSBs, so `dataStream` (last field) sits +-- in the low bits and `isLast` (last field of DataStream) is bit 0 of the whole +-- payload (confirmed: DmaReadCntrlGen.vhd uses dmaRespIn(0) as dataStream.isLast): +-- U_DmaReadArb .reqKFinished = isDmaReadReqLastFrag(req) = True -> tie '1' +-- U_DmaReadArb .srvRespFinished= isDmaReadRespLastFrag(rsp)= rsp.ds.isLast-> bit 0 +-- U_DmaWriteArb.reqKFinished = isDmaWriteReqLastFrag(req) = req.ds.isLast-> bit 0 +-- U_DmaWriteArb.srvRespFinished= isDmaWriteRespLastFrag(rsp)= True -> tie '1' +-- The two per-port request predicates are sampled at enqueue (companion carried +-- through the arbiter's input FIFO), so they are pure functions of the incoming +-- request data on that port — extracted here as bit 0 of the port's reqData. +-- +-- ServerProxy caveat: it hard-codes active-HIGH synchronous reset internally +-- (RST_POLARITY_G='1', RST_ASYNC_G=false in its surf.Fifo instances) and has no +-- reset-polarity generic; the shared rst is forwarded as-is. Keep the parent's +-- RST_POLARITY_G='1'/RST_ASYNC_G=false defaults for a consistent reset domain. +-- +-- Open questions (out/04-vhdl/OPEN_QUESTIONS.md): OQ-EMIT-DMAARB-01. +-- +-- NOTE: emitting does not prove equivalence — simulate this entity (cocotb) +-- against the BSV behaviour before trusting it. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; + +entity DmaArbiter4Qp is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active-HIGH reset + RST_ASYNC_G : boolean := false; + DMA_READ_REQ_WIDTH_G : positive := 176; -- Bits#(DmaReadReq) + DMA_READ_RESP_WIDTH_G : positive := 383; -- Bits#(DmaReadResp) + DMA_WRITE_REQ_WIDTH_G : positive := 419; -- Bits#(DmaWriteReq) + DMA_WRITE_RESP_WIDTH_G : positive := 53); -- Bits#(DmaWriteResp) + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; -- FPGA async/sync reset + + ----------------------------------------------------------------------- + -- dmaReadClt : aggregated Client toward external DMA (= dmaReadProxy.cltPort) + ----------------------------------------------------------------------- + dmaReadCltReqValid : out sl; -- request (put) + dmaReadCltReqData : out slv(DMA_READ_REQ_WIDTH_G-1 downto 0); -- DmaReadReq + dmaReadCltReqReady : in sl; + dmaReadCltRespValid : in sl; -- response (get) + dmaReadCltRespData : in slv(DMA_READ_RESP_WIDTH_G-1 downto 0); -- DmaReadResp + dmaReadCltRespReady : out sl; + + ----------------------------------------------------------------------- + -- dmaWriteClt : aggregated Client toward external DMA (= dmaWriteProxy.cltPort) + ----------------------------------------------------------------------- + dmaWriteCltReqValid : out sl; -- request (put) + dmaWriteCltReqData : out slv(DMA_WRITE_REQ_WIDTH_G-1 downto 0); -- DmaWriteReq + dmaWriteCltReqReady : in sl; + dmaWriteCltRespValid : in sl; -- response (get) + dmaWriteCltRespData : in slv(DMA_WRITE_RESP_WIDTH_G-1 downto 0); -- DmaWriteResp + dmaWriteCltRespReady : out sl; + + ----------------------------------------------------------------------- + -- dmaReadSrv4RQ : Server for the RQ engine (U_DmaReadArb port 0) + ----------------------------------------------------------------------- + dmaReadSrv4RqReqValid : in sl; -- request (put) + dmaReadSrv4RqReqData : in slv(DMA_READ_REQ_WIDTH_G-1 downto 0); -- DmaReadReq + dmaReadSrv4RqReqReady : out sl; + dmaReadSrv4RqRespValid : out sl; -- response (get) + dmaReadSrv4RqRespData : out slv(DMA_READ_RESP_WIDTH_G-1 downto 0); -- DmaReadResp + dmaReadSrv4RqRespReady : in sl; + + ----------------------------------------------------------------------- + -- dmaWriteSrv4RQ : Server for the RQ engine (U_DmaWriteArb port 0) + ----------------------------------------------------------------------- + dmaWriteSrv4RqReqValid : in sl; -- request (put) + dmaWriteSrv4RqReqData : in slv(DMA_WRITE_REQ_WIDTH_G-1 downto 0); -- DmaWriteReq + dmaWriteSrv4RqReqReady : out sl; + dmaWriteSrv4RqRespValid : out sl; -- response (get) + dmaWriteSrv4RqRespData : out slv(DMA_WRITE_RESP_WIDTH_G-1 downto 0); -- DmaWriteResp + dmaWriteSrv4RqRespReady : in sl; + + ----------------------------------------------------------------------- + -- dmaReadSrv4SQ : Server for the SQ engine (U_DmaReadArb port 1) + ----------------------------------------------------------------------- + dmaReadSrv4SqReqValid : in sl; -- request (put) + dmaReadSrv4SqReqData : in slv(DMA_READ_REQ_WIDTH_G-1 downto 0); -- DmaReadReq + dmaReadSrv4SqReqReady : out sl; + dmaReadSrv4SqRespValid : out sl; -- response (get) + dmaReadSrv4SqRespData : out slv(DMA_READ_RESP_WIDTH_G-1 downto 0); -- DmaReadResp + dmaReadSrv4SqRespReady : in sl; + + ----------------------------------------------------------------------- + -- dmaWriteSrv4SQ : Server for the SQ engine (U_DmaWriteArb port 1) + ----------------------------------------------------------------------- + dmaWriteSrv4SqReqValid : in sl; -- request (put) + dmaWriteSrv4SqReqData : in slv(DMA_WRITE_REQ_WIDTH_G-1 downto 0); -- DmaWriteReq + dmaWriteSrv4SqReqReady : out sl; + dmaWriteSrv4SqRespValid : out sl; -- response (get) + dmaWriteSrv4SqRespData : out slv(DMA_WRITE_RESP_WIDTH_G-1 downto 0); -- DmaWriteResp + dmaWriteSrv4SqRespReady : in sl); +end entity DmaArbiter4Qp; + +architecture rtl of DmaArbiter4Qp is + + ----------------------------------------------------------------------------- + -- Downstream srv <-> proxy srvPort nets (read direction) + ----------------------------------------------------------------------------- + signal rdArbReqValid : sl; -- arb.srvReq -> proxy.srvReq + signal rdArbReqData : slv(DMA_READ_REQ_WIDTH_G-1 downto 0); + signal rdProxyReqReady : sl; -- proxy.srvReqReady -> arb + signal rdProxyRespValid : sl; -- proxy.srvResp -> arb.srvResp + signal rdProxyRespData : slv(DMA_READ_RESP_WIDTH_G-1 downto 0); + signal rdArbRespRd : sl; -- arb.srvRespRd -> proxy.srvRespReady + signal rdSrvRespFinished : sl; -- isDmaReadRespLastFrag = resp.dataStream.isLast + + ----------------------------------------------------------------------------- + -- Downstream srv <-> proxy srvPort nets (write direction) + ----------------------------------------------------------------------------- + signal wrArbReqValid : sl; + signal wrArbReqData : slv(DMA_WRITE_REQ_WIDTH_G-1 downto 0); + signal wrProxyReqReady : sl; + signal wrProxyRespValid : sl; + signal wrProxyRespData : slv(DMA_WRITE_RESP_WIDTH_G-1 downto 0); + signal wrArbRespRd : sl; + +begin + + ----------------------------------------------------------------------------- + -- Non-constant "finished" predicates (OQ-FSM-17). isLast = bit 0 of the + -- struct-packed payload (dataStream is the low field; isLast its low bit). + ----------------------------------------------------------------------------- + rdSrvRespFinished <= rdProxyRespData(0); -- DmaReadResp.dataStream.isLast + + ----------------------------------------------------------------------------- + -- READ direction + ----------------------------------------------------------------------------- + -- U_DmaReadArb : dmaReadSrvVec <- mkServerArbiter(dmaReadProxy.srvPort, ...) + -- Two upstream Server faces (RQ=port0, SQ=port1) arbitrated onto the read + -- proxy's srvPort. Both request predicates tie '1' (isDmaReadReqLastFrag + -- = True); the response predicate is resp.dataStream.isLast. + U_DmaReadArb : entity surf.ServerArbiter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PORT_COUNT_G => 2, + REQ_WIDTH_G => DMA_READ_REQ_WIDTH_G, + RESP_WIDTH_G => DMA_READ_RESP_WIDTH_G, + MEMORY_TYPE_G => "distributed", + FIFO_ADDR_WIDTH_G => 4) + port map ( + clk => clk, + rst => rst, + -- port 0 = RQ + req0Valid => dmaReadSrv4RqReqValid, + req0Data => dmaReadSrv4RqReqData, + req0Finished => '1', -- isDmaReadReqLastFrag = True + req0Ready => dmaReadSrv4RqReqReady, + resp0Valid => dmaReadSrv4RqRespValid, + resp0Data => dmaReadSrv4RqRespData, + resp0Rd => dmaReadSrv4RqRespReady, + -- port 1 = SQ + req1Valid => dmaReadSrv4SqReqValid, + req1Data => dmaReadSrv4SqReqData, + req1Finished => '1', -- isDmaReadReqLastFrag = True + req1Ready => dmaReadSrv4SqReqReady, + resp1Valid => dmaReadSrv4SqRespValid, + resp1Data => dmaReadSrv4SqRespData, + resp1Rd => dmaReadSrv4SqRespReady, + -- downstream shared srv <-> U_DmaReadProxy.srvPort + srvReqValid => rdArbReqValid, + srvReqData => rdArbReqData, + srvReqReady => rdProxyReqReady, + srvRespValid => rdProxyRespValid, + srvRespData => rdProxyRespData, + srvRespFinished => rdSrvRespFinished, + srvRespRd => rdArbRespRd); + + -- U_DmaReadProxy : dmaReadProxy <- mkServerProxy + -- srvPort <-> read arbiter's downstream srv; cltPort -> external dmaReadClt. + U_DmaReadProxy : entity surf.ServerProxy + generic map ( + TPD_G => TPD_G, + REQ_WIDTH_G => DMA_READ_REQ_WIDTH_G, + RESP_WIDTH_G => DMA_READ_RESP_WIDTH_G) + port map ( + clk => clk, + rst => rst, + -- srvPort <-> U_DmaReadArb downstream srv + srvReqValid => rdArbReqValid, + srvReqData => rdArbReqData, + srvReqReady => rdProxyReqReady, + srvRespValid => rdProxyRespValid, + srvRespData => rdProxyRespData, + srvRespReady => rdArbRespRd, + -- cltPort -> dmaReadClt boundary + cltReqValid => dmaReadCltReqValid, + cltReqData => dmaReadCltReqData, + cltReqReady => dmaReadCltReqReady, + cltRespValid => dmaReadCltRespValid, + cltRespData => dmaReadCltRespData, + cltRespReady => dmaReadCltRespReady); + + ----------------------------------------------------------------------------- + -- WRITE direction + ----------------------------------------------------------------------------- + -- U_DmaWriteArb : dmaWriteSrvVec <- mkServerArbiter(dmaWriteProxy.srvPort, ...) + -- Request predicate = req.dataStream.isLast (bit 0 of each port's reqData); + -- response predicate ties '1' (isDmaWriteRespLastFrag = True). + U_DmaWriteArb : entity surf.ServerArbiter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PORT_COUNT_G => 2, + REQ_WIDTH_G => DMA_WRITE_REQ_WIDTH_G, + RESP_WIDTH_G => DMA_WRITE_RESP_WIDTH_G, + MEMORY_TYPE_G => "distributed", + FIFO_ADDR_WIDTH_G => 4) + port map ( + clk => clk, + rst => rst, + -- port 0 = RQ + req0Valid => dmaWriteSrv4RqReqValid, + req0Data => dmaWriteSrv4RqReqData, + req0Finished => dmaWriteSrv4RqReqData(0), -- isDmaWriteReqLastFrag = req.dataStream.isLast + req0Ready => dmaWriteSrv4RqReqReady, + resp0Valid => dmaWriteSrv4RqRespValid, + resp0Data => dmaWriteSrv4RqRespData, + resp0Rd => dmaWriteSrv4RqRespReady, + -- port 1 = SQ + req1Valid => dmaWriteSrv4SqReqValid, + req1Data => dmaWriteSrv4SqReqData, + req1Finished => dmaWriteSrv4SqReqData(0), -- isDmaWriteReqLastFrag = req.dataStream.isLast + req1Ready => dmaWriteSrv4SqReqReady, + resp1Valid => dmaWriteSrv4SqRespValid, + resp1Data => dmaWriteSrv4SqRespData, + resp1Rd => dmaWriteSrv4SqRespReady, + -- downstream shared srv <-> U_DmaWriteProxy.srvPort + srvReqValid => wrArbReqValid, + srvReqData => wrArbReqData, + srvReqReady => wrProxyReqReady, + srvRespValid => wrProxyRespValid, + srvRespData => wrProxyRespData, + srvRespFinished => '1', -- isDmaWriteRespLastFrag = True + srvRespRd => wrArbRespRd); + + -- U_DmaWriteProxy : dmaWriteProxy <- mkServerProxy + U_DmaWriteProxy : entity surf.ServerProxy + generic map ( + TPD_G => TPD_G, + REQ_WIDTH_G => DMA_WRITE_REQ_WIDTH_G, + RESP_WIDTH_G => DMA_WRITE_RESP_WIDTH_G) + port map ( + clk => clk, + rst => rst, + -- srvPort <-> U_DmaWriteArb downstream srv + srvReqValid => wrArbReqValid, + srvReqData => wrArbReqData, + srvReqReady => wrProxyReqReady, + srvRespValid => wrProxyRespValid, + srvRespData => wrProxyRespData, + srvRespReady => wrArbRespRd, + -- cltPort -> dmaWriteClt boundary + cltReqValid => dmaWriteCltReqValid, + cltReqData => dmaWriteCltReqData, + cltReqReady => dmaWriteCltReqReady, + cltRespValid => dmaWriteCltRespValid, + cltRespData => dmaWriteCltRespData, + cltRespReady => dmaWriteCltRespReady); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/DmaReadCltArbiter.vhd b/ethernet/RoCEv2/rtl/DmaReadCltArbiter.vhd new file mode 100644 index 0000000000..5d999e80e4 --- /dev/null +++ b/ethernet/RoCEv2/rtl/DmaReadCltArbiter.vhd @@ -0,0 +1,149 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Thin STRUCTURAL specialization of mkClientArbiter — owns 0 rules, +-- 0 state registers, 0 SURF instances (matches the partition entry). Its +-- entire contribution over a bare ClientArbiter is: +-- +-- 1. Type specialization: reqType = DmaReadReq (176b), respType = +-- DmaReadResp (383b). These fix the child's REQ_WIDTH_G / RESP_WIDTH_G. +-- +-- 2. Resolution of the two BSV `function Bool` module parameters +-- (isReqFinished / isRespFinished — OQ-FSM-17). BSV realizes these as +-- elaboration-time functions; VHDL has no function-type ports, so this +-- wrapper (where the concrete DmaRead type is known) computes each +-- predicate and feeds it as a 1-bit combinational input to the child: +-- * isDmaReadReqLastFrag(req) = True +-- -> child cltReqFinished tied to all-'1' (every request is a +-- single-fragment burst; the child re-arms shouldSaveGrantIdxReg +-- on every issued request). +-- * isDmaReadRespLastFrag(resp) = resp.dataStream.isLast +-- -> child outRespFinished = outRespData(0). BSV struct-pack places +-- the first field in the MSBs, so `dataStream` (last field of +-- DmaReadResp) sits in the low bits, and `isLast` (last field of +-- DataStream) is bit 0 (LSB) of the packed DmaReadResp. Confirmed +-- against DmaReadCntrlGen.vhd (dataStream.isLast = dmaRespIn(0)). +-- +-- All other ports connect one-to-one between this entity boundary and the +-- child U_Arb. There is no owned RegType, no FSM, no sequential process — +-- the generated VHDL is a single child instantiation plus predicate wiring. +-- All arbitration state / FIFOs live in the child ClientArbiter; see +-- out/04-vhdl/ClientArbiter.vhd. +-- +-- Sizing (DmaReadCltArbiter.fsm.md §Elaboration facts, OQ-FSM-PERMARB-01, +-- CLOSED 2026-07-04): +-- portSz = TMul#(2, MAX_QP) = 8. dmaReadCltVec is +-- Vector#(TMul#(2,MAX_QP), DmaReadClt) (each QP contributes one RQ-side and +-- one SQ-side DmaRead client). This wrapper carries a MAX_QP_G generic and +-- drives the child PORT_COUNT_G => 2*MAX_QP_G (= 8 at MAX_QP_G=4, idxW=3: +-- full 8-input arbitration tree). The child ClientArbiter is emitted generic +-- over PORT_COUNT_G and Stage-5 verified at PORT_COUNT_G=8. +-- +-- Per-client flattened buses (inherited from ClientArbiter): client k's +-- request payload slice is cltReqData((k+1)*REQ_WIDTH_G-1 downto k*REQ_WIDTH_G) +-- and likewise cltRespData with RESP_WIDTH_G, k = 0 .. 2*MAX_QP_G-1. +-- +-- Child entity instantiated: +-- * U_Arb : work.ClientArbiter (owns the arbitration FSM + all FIFOs) +-- source: out/04-vhdl/ClientArbiter.vhd +-- SURF components instantiated directly: NONE (all owned by the child). +-- +-- NOTE: emitting does not prove equivalence — simulate this entity (cocotb) +-- against the BSV behaviour before trusting it. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity DmaReadCltArbiter is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + MAX_QP_G : positive := 4; -- BSV MAX_QP; child PORT_COUNT = 2*MAX_QP + REQ_WIDTH_G : positive := 176; -- Bits#(DmaReadReq) (fixed by type; do not change) + RESP_WIDTH_G : positive := 383; -- Bits#(DmaReadResp) (fixed by type; do not change) + MEMORY_TYPE_G : string := "distributed"; -- child FIFO RAM style + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- child FIFO depth = 2**ADDR + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- Per-port upstream DmaRead client faces (dmaReadCltVec[k], + -- k = 0 .. 2*MAX_QP_G-1; arbiter is master). Client k's payload slice is + -- ((k+1)*WIDTH-1 downto k*WIDTH) of the flattened data buses. + cltReqValid : in slv(2*MAX_QP_G-1 downto 0); -- client k DmaReadReq available (request.get implicit cond) + cltReqData : in slv(2*MAX_QP_G*REQ_WIDTH_G-1 downto 0); -- client k DmaReadReq payload, flattened + cltReqGet : out slv(2*MAX_QP_G-1 downto 0); -- arbiter takes client k's request (request.get fired) + cltRespValid : out slv(2*MAX_QP_G-1 downto 0); -- arbiter drives a DmaReadResp to client k (one-hot on grant) + cltRespData : out slv(2*MAX_QP_G*RESP_WIDTH_G-1 downto 0); -- DmaReadResp payload (broadcast; cltRespValid selects the port) + cltRespReady : in slv(2*MAX_QP_G-1 downto 0); -- client k can accept a response (response.put ready) + -- Downstream shared DmaRead Client face (returned arbitratedClient) + outReqValid : out sl; -- arbitrated DmaReadReq valid to DMA + outReqData : out slv(REQ_WIDTH_G-1 downto 0); -- arbitrated DmaReadReq + outReqRd : in sl; -- DMA dequeues the request (request.get) + outRespValid : in sl; -- DMA presents a DmaReadResp (response.put fired) + outRespData : in slv(RESP_WIDTH_G-1 downto 0); -- DmaReadResp payload from DMA + outRespReady : out sl); -- arbiter can accept a response (response.put ready) +end entity DmaReadCltArbiter; + +architecture rtl of DmaReadCltArbiter is + + -- Resolved OQ-FSM-17 request predicate: isDmaReadReqLastFrag = True for every + -- port, so the child's per-channel finish input is a constant all-'1' bus. + signal reqFinishedAll : slv(2*MAX_QP_G-1 downto 0); + +begin + + -- isDmaReadReqLastFrag(req) = True -> every request is single-fragment. + reqFinishedAll <= (others => '1'); + + -------------------------------------------------------------------------- + -- U_Arb : the actual DmaRead client arbiter (ClientArbiter) — owns the FSM + -- register (shouldSaveGrantIdxReg), the arbitration tree, and all FIFOs. + -- PORT_COUNT_G => 2*MAX_QP_G (= 8 at MAX_QP_G=4). Predicate inputs resolved + -- by this wrapper; all other ports pass straight through. + -------------------------------------------------------------------------- + U_Arb : entity surf.ClientArbiter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PORT_COUNT_G => 2*MAX_QP_G, + REQ_WIDTH_G => REQ_WIDTH_G, + RESP_WIDTH_G => RESP_WIDTH_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + clk => clk, + rst => rst, + -- Per-port upstream client faces (pass-through) + cltReqValid => cltReqValid, + cltReqData => cltReqData, + cltReqFinished => reqFinishedAll, -- OQ-FSM-17: isDmaReadReqLastFrag = True + cltReqGet => cltReqGet, + cltRespValid => cltRespValid, + cltRespData => cltRespData, + cltRespReady => cltRespReady, + -- Downstream shared client face (pass-through) + outReqValid => outReqValid, + outReqData => outReqData, + outReqRd => outReqRd, + outRespValid => outRespValid, + outRespData => outRespData, + outRespFinished => outRespData(0), -- OQ-FSM-17: resp.dataStream.isLast = RESP LSB + outRespReady => outRespReady); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd b/ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd new file mode 100644 index 0000000000..4297f4a3cb --- /dev/null +++ b/ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd @@ -0,0 +1,616 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Read-side analogue of DmaWriteCntrl with an embedded address-chunker child +-- server. It splits each incoming DmaReadCntrlReq into PMTU-sized chunks (via +-- U_AddrChunkSrv), issues one external DmaReadReq per chunk, and re-assembles +-- the streamed DmaReadResp fragments into DmaReadCntrlResps that carry the +-- *original* request's first/last flags. Cancel / graceful-stop support +-- mirrors DmaWriteCntrl. +-- +-- There is NO explicit state-enum register: control is two CReg booleans plus +-- the four FIFO occupancies. The implied control sub-FSM over +-- {cancel, gracefulStop} (fsm.md §State register): +-- RUN_S = {cancel=0} — recvReq/issueDmaReq/recvDmaResp active +-- CANCELLING_S = {cancel=1,grStop=0} — recvReq/issueDmaReq blocked; recvDmaResp +-- keeps draining; await respQ + pendingRead empty +-- STOPPED_S = {cancel=1,grStop=1} — quiesced; isIdle() true +-- {cancel=0,gracefulStop=1} is unreachable. Emitted as two boolean RegType +-- fields, not an enum. +-- +-- The entity is a Server to its caller (srvPort: request Put / response Get, +-- wired through U_ReqQ/U_RespQ) and a Client of the external Server dmaReadSrv +-- (request Put dmaReqOut / response Get dmaRespIn). +-- +-- BSV rules implemented (fsm.md §Transition table): +-- resetAndClear (R0) — guard clearAll='1' (LEVEL); clears all four FIFOs via +-- rst, forces cancel/gracefulStop to '0'. Dominates all +-- other rules (every other guards !clearAll). +-- recvReq (R1) — RUN_S (!cancel); deq U_ReqQ -> enq the whole 198-bit +-- request into U_PendingDmaCntrlReqQ AND push an +-- AddrChunkReq (startAddr,totalLen,pmtu) into the child. +-- issueDmaReq (R2) — RUN_S (!cancel); get one AddrChunkResp from the child, +-- Put one DmaReadReq to dmaReadSrv, enq a token (the +-- DmaReadReq + chunk first/last) into U_PendingDmaReadReqQ. +-- On addrChunkResp.isLast, retire (deq) the matching +-- U_PendingDmaCntrlReqQ entry (per-original-request cadence). +-- recvDmaResp (R3) — cancel-INDEPENDENT; get one DmaReadResp from dmaReadSrv, +-- AND its stream first/last with the chunk's first/last +-- (isOrigFirst/isOrigLast), enq the 385-bit +-- DmaReadCntrlResp into U_RespQ. On dataStream.isLast, +-- retire (deq) one U_PendingDmaReadReqQ token +-- (per-DMA-fragment cadence). This is how the pending-read +-- queue empties so R4 can latch even while cancelling. +-- setGracefulStop(R4)— CANCELLING_S (cancel && !gracefulStop); latches +-- gracefulStop:='1' once BOTH U_RespQ and +-- U_PendingDmaReadReqQ are empty (no in-flight responses). +-- dmaCntrl.cancel()(M0)— Action pulse cancelEn -> cancel:='1' (CReg port0, +-- same-cycle forwarded into the R1/R2/R4 guards) and +-- re-arms gracefulStop:='0' (port0). +-- dmaCntrl.isIdle() — Moore output = r.gracefulStop (CReg port0 read of the +-- REGISTERED value). +-- +-- IMPORTANT — the two pending-FIFO deq conditions are DISTINCT (fsm.md §Notes): +-- U_PendingDmaCntrlReqQ : deq per ORIGINAL request -> if addrChunkResp.isLast +-- (childRespQDout(0)) in R2. +-- U_PendingDmaReadReqQ : deq per DMA FRAGMENT -> if dataStream.isLast +-- (dmaRespIn(0)) in R3. +-- +-- CReg semantics (fsm.md §CReg semantics) — each mkCReg(2,False) is ONE RegType +-- field, writes applied in port order so reads see the forwarded value: +-- cancel : v:=r; port0 (cancelEn) sets '1' BEFORE R1/R2/R4 read v.cancel +-- (same-cycle cancel); port1 (clearAll) clears '0' last (dominates). +-- gracefulStop : port0 read (isIdle) uses r.gracefulStop (pre-update, Moore); +-- port0 write (cancelEn) re-arms '0'; R4 then sets '1'; +-- port1 (clearAll) clears '0' last (dominates). +-- Net: clearAll->0; else setGracefulStop->1; else cancelEn->0; else hold. +-- +-- Mealy (combinational) request paths (fsm.md §Output style) — MUST NOT be +-- registered (would insert a spurious cycle): +-- dmaReqOut = composed DmaReadReq (initiator/sqpn/wrID from the pending- +-- cntrl front + chunkAddr/chunkLen from the child front), +-- gated by dmaReqValid (R2). +-- childReqPutData = AddrChunkReq (reqQ front startAddr/totalLen/pmtu), gated by +-- childReqPutWrEn (R1). +-- U_RespQ.din = DmaReadResp & isOrigFirst & isOrigLast, computed in R3 and +-- then registered INSIDE the Fifo. +-- +-- FIFO clear (OQ-FSM-01 carry-forward, RESOLVED in out/03-fsm/RESOLVED.md): +-- BSV reqQ/respQ/pendingDmaCntrlReqQ/pendingDmaReadReqQ .clear map to asserting +-- each Fifo's rst, OR'd with the structural reset: fifoRst = rst OR clearAll. +-- surf.FifoSync holds logically empty for the whole asserted window (level-safe; +-- no pulse generator). Requires GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, +-- RST_POLARITY_G='1'. All four FIFOs share fifoRst so the BSV single-cycle +-- simultaneous clear is preserved. The child clears via its own clearAllI. +-- +-- Open-question carry-forwards (see out/04-vhdl/OPEN_QUESTIONS.md and +-- out/03-fsm/DmaReadCntrlConAndGen.fsm.md §Open issues): +-- OQ-FSM-DRCCAG-01 — Stage-1/2 records (mapping.json/modules.json) are wrong +-- for this entity (fabricated issueReq/recvResp/cancelFlush/ +-- pendingCntReg; two FIFOs + the child missing). This file +-- follows the FSM spec / LIVE BSV source: FOUR surf.Fifo +-- instances + one U_AddrChunkSrv child. +-- OQ-FSM-DRCCAG-02 — clearAll, isSQ and the dmaReadSrv Server-client handshake +-- are real top-level ports (RESOLVED; enumerated below). +-- isSQ is retained for interface fidelity only — the child +-- AddrChunkSrvConAndGen dropped its isSQI port +-- (OQ-FSM-ACSCAG-02), so isSQ has NO internal sink here. +-- OQ-EMIT-08 — R4 quiescence guard reads respQ-empty AND pendingRead-empty; +-- FWFT cold latency caveat — verify in Stage 5. See +-- out/04-vhdl/OPEN_QUESTIONS.md. +-- +-- Bit layouts (BSV deriving(Bits), first-field-at-MSB; fsm.md §Bit layouts, +-- OQ-FSM-H2DS-04 / OQ-FSM-DRCCAG-03): +-- +-- DmaReadCntrlReq (198b) — U_ReqQ / U_PendingDmaCntrlReqQ element: +-- [197:194] initiator(4) [193:170] sqpn(24) [169:106] wrID(64) +-- [105:42] startAddr(64) [41:10] len(32) [9:3] mrIdx(7) +-- [2:0] pmtu(3) +-- DmaReadReq (176b) — dmaReqOut / U_PendingDmaReadReqQ.dmaReadReq part: +-- [175:172] initiator(4) [171:148] sqpn(24) [147:84] wrID(64) +-- [83:20] startAddr(64) [19:7] len(13,PktLen) [6:0] mrIdx(7) +-- DmaReadResp (383b) — dmaRespIn: +-- [382:379] initiator(4) [378:355] sqpn(24) [354:291] wrID(64) +-- [290] isRespErr [289:34] data(256) [33:2] byteEn(32) [1] isFirst [0] isLast +-- DmaReadCntrlResp (385b) — U_RespQ element: +-- [384:2] dmaReadResp(383) [1] isOrigFirst [0] isOrigLast +-- Tuple3#(DmaReadReq,Bool,Bool) (178b) — U_PendingDmaReadReqQ element: +-- [177:2] dmaReadReq(176) [1] isFirstDmaReqChunk [0] isLastDmaReqChunk +-- AddrChunkReq (99b) — childReqPutData: +-- [98:35] startAddr(64) [34:3] totalLen(32) [2:0] pmtu(3) +-- AddrChunkResp (79b) — childRespQDout: +-- [78:15] chunkAddr(64) [14:2] chunkLen(13) [1] isFirst [0] isLast +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_ReqQ : surf.Fifo DATA_WIDTH_G=198, FWFT, sync, block RAM +-- (DmaReadCntrlReq; BSV mkFIFOF reqQ) +-- U_RespQ : surf.Fifo DATA_WIDTH_G=385, FWFT, sync, block RAM +-- (DmaReadCntrlResp; BSV mkFIFOF respQ) +-- U_PendingDmaCntrlReqQ : surf.Fifo DATA_WIDTH_G=198, FWFT, sync, block RAM +-- (DmaReadCntrlReq; BSV mkFIFOF pendingDmaCntrlReqQ) +-- U_PendingDmaReadReqQ : surf.Fifo DATA_WIDTH_G=178, FWFT, sync, distributed RAM +-- (Tuple3; BSV mkFIFOF pendingDmaReadReqQ). Distributed +-- RAM chosen so its enq->notEmpty tracks the BSV timing +-- that R4's quiescence guard relies on, mirroring the +-- DmaWriteCntrl U_HasPendQ rationale. See OQ-EMIT-08. +-- Child entity instantiated: +-- U_AddrChunkSrv : AddrChunkSrvConAndGen (out/04-vhdl/AddrChunkSrvConAndGen.vhd) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity DmaReadCntrlConAndGen is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (cntrlStatus.comm.isReset; synchronous, LEVEL-asserted) + clearAll : in sl; + -- cntrlStatus.isSQ : forwarded to the child only in BSV, but the child + -- (AddrChunkSrvConAndGen) dropped its isSQI port (OQ-FSM-ACSCAG-02), so this + -- input has NO internal sink. Retained for interface fidelity per + -- OQ-FSM-DRCCAG-02. + isSQ : in sl; + -- dmaCntrl.cancel() method (Action pulse): request graceful cancel + cancelEn : in sl; + -- srvPort.request : Put#(DmaReadCntrlReq) (caller -> entity, enq to reqQ) + reqInValid : in sl; -- caller offers a request (wr_en) + reqInData : in slv(197 downto 0); -- DmaReadCntrlReq packed + reqInReady : out sl; -- entity can accept (reqQ.notFull) + -- srvPort.response : Get#(DmaReadCntrlResp) (entity -> caller, deq from respQ) + respOutReady : in sl; -- caller takes a response (rd_en) + respOutValid : out sl; -- response available (respQ.notEmpty) + respOutData : out slv(384 downto 0); -- DmaReadCntrlResp packed + -- dmaReadSrv.request : Put#(DmaReadReq) (entity -> external server, CLIENT) + dmaReqValid : out sl; -- entity offers a request (Mealy) + dmaReqOut : out slv(175 downto 0); -- DmaReadReq packed (Mealy) + dmaReqReady : in sl; -- external server can accept + -- dmaReadSrv.response : Get#(DmaReadResp) (external server -> entity, CLIENT) + dmaRespValid : in sl; -- external server offers a response + dmaRespIn : in slv(382 downto 0); -- DmaReadResp packed + dmaRespReady : out sl; -- entity takes the response (get/pop) + -- dmaCntrl.isIdle() method result (Moore, registered) + isIdle : out sl); +end entity DmaReadCntrlConAndGen; + +architecture rtl of DmaReadCntrlConAndGen is + + -- Control sub-FSM state lives in two boolean fields (mkCReg(2,False) each). + -- Documented implied states: RUN_S/CANCELLING_S/STOPPED_S (fsm.md §State). + type RegType is record + cancel : sl; -- cancelReg[2] <- mkCReg(2,False) + gracefulStop : sl; -- gracefulStopReg[2] <- mkCReg(2,False) + end record RegType; + + constant REG_INIT_C : RegType := ( + cancel => '0', + gracefulStop => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_ReqQ interface signals (DmaReadCntrlReq, 198b) + signal reqQNotFull : sl; + signal reqQValid : sl; -- = reqQ.notEmpty (FWFT data valid) + signal reqQDout : slv(197 downto 0); + signal reqQRdEn : sl; + + -- U_RespQ interface signals (DmaReadCntrlResp, 385b) + signal respQNotFull : sl; + signal respQValid : sl; -- = respQ.notEmpty + signal respQWrEn : sl; + signal respQDin : slv(384 downto 0); + + -- U_PendingDmaCntrlReqQ interface signals (DmaReadCntrlReq, 198b) + signal pendCntrlNotFull : sl; + signal pendCntrlValid : sl; -- = notEmpty + signal pendCntrlWrEn : sl; + signal pendCntrlDin : slv(197 downto 0); + signal pendCntrlRdEn : sl; + signal pendCntrlDout : slv(197 downto 0); + + -- U_PendingDmaReadReqQ interface signals (Tuple3, 178b) + signal pendReadNotFull : sl; + signal pendReadValid : sl; -- = notEmpty (R4 quiescence guard) + signal pendReadWrEn : sl; + signal pendReadDin : slv(177 downto 0); + signal pendReadRdEn : sl; + signal pendReadDout : slv(177 downto 0); + + -- U_AddrChunkSrv child interface signals + signal childReqPutWrEn : sl; -- FSM (recvReq) -> child request.put + signal childReqPutDin : slv(98 downto 0); + signal childReqPutReady : sl; -- child reqQ.notFull (R1 implicit cond) + signal childRespGetRdEn : sl; -- FSM (issueDmaReq) -> child response.get + signal childRespQValid : sl; -- child respQ.notEmpty (R2 implicit cond) + signal childRespQDout : slv(78 downto 0); + + -- FIFO reset line: level = rst OR clearAll (atomic 4-FIFO clear) + signal fifoRst : sl; + +begin + + -- FIFO reset: level-sensitive clear (OQ-FSM-01 carry-forward, RESOLVED) + fifoRst <= rst or clearAll; + + -- srvPort boundary wiring (pass-through; not FSM-gated) + reqInReady <= reqQNotFull; -- reqQ.notFull readiness to caller + respOutValid <= respQValid; -- respQ.notEmpty to caller + + -- isIdle() method (Moore): registered gracefulStop (CReg port0 read of the + -- REGISTERED value). Drive from r, NOT v. + isIdle <= r.gracefulStop; + + --------------------------------------------------------------------------- + -- U_ReqQ : surf.Fifo + -- Inbound DmaReadCntrlReq queue (BSV mkFIFOF reqQ). wr side = caller's + -- srvPort.request.put (pass-through); rd side = FSM (recvReq deq). + --------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 198, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqInValid, -- pass-through (caller drives) + din => reqInData, -- pass-through (caller drives) + full => open, + not_full => reqQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => reqQRdEn, -- FSM (recvReq) + dout => reqQDout, + valid => reqQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_RespQ : surf.Fifo + -- Outbound DmaReadCntrlResp queue (BSV mkFIFOF respQ). wr side = FSM + -- (recvDmaResp enq); rd side = caller's srvPort.response.get (pass-through). + --------------------------------------------------------------------------- + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 385, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => respQWrEn, -- FSM (recvDmaResp) + din => respQDin, -- FSM (recvDmaResp) + full => open, + not_full => respQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => respOutReady, -- pass-through (caller drives) + dout => respOutData, + valid => respQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_PendingDmaCntrlReqQ : surf.Fifo + -- Holds the whole 198-bit original request while its chunks are issued. + -- wr = FSM (recvReq); rd = FSM (issueDmaReq, deq per ORIGINAL request, i.e. + -- on the LAST addr chunk). Only notFull/notEmpty + dout consumed. + --------------------------------------------------------------------------- + U_PendingDmaCntrlReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 198, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pendCntrlWrEn, -- FSM (recvReq) + din => pendCntrlDin, -- FSM (recvReq) = reqQDout + full => open, + not_full => pendCntrlNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pendCntrlRdEn, -- FSM (issueDmaReq, per original req) + dout => pendCntrlDout, + valid => pendCntrlValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_PendingDmaReadReqQ : surf.Fifo + -- One token per issued DMA-read chunk (DmaReadReq + chunk first/last). + -- wr = FSM (issueDmaReq); rd = FSM (recvDmaResp, deq per DMA FRAGMENT, i.e. + -- on dataStream.isLast). R4's graceful-stop guard reads its notEmpty, so + -- distributed RAM is used (enq->notEmpty timing fidelity; see OQ-EMIT-08, + -- mirrors DmaWriteCntrl U_HasPendQ). + --------------------------------------------------------------------------- + U_PendingDmaReadReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 178, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pendReadWrEn, -- FSM (issueDmaReq) + din => pendReadDin, -- FSM (issueDmaReq) + full => open, + not_full => pendReadNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pendReadRdEn, -- FSM (recvDmaResp, per DMA fragment) + dout => pendReadDout, + valid => pendReadValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_AddrChunkSrv : AddrChunkSrvConAndGen (child entity, not SURF) + -- BSV: addrChunkSrv <- mkAddrChunkSrv(clearAll, cntrlStatus.isSQ). + -- The child has its own clearAllI (internal clear) and does NOT expose an + -- isSQI port (OQ-FSM-ACSCAG-02), so the parent's isSQ is not wired here. + -- Treated as a Server pair: parent drives request.put / response.get. + --------------------------------------------------------------------------- + U_AddrChunkSrv : entity surf.AddrChunkSrvConAndGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAllI => clearAll, + reqPutValid => childReqPutWrEn, + reqPutData => childReqPutDin, + reqPutReady => childReqPutReady, + respGetReady => childRespGetRdEn, + respGetValid => childRespQValid, + respGetData => childRespQDout, + isIdle => open); -- parent does not read child isIdle + + --------------------------------------------------------------------------- + -- Combinatorial process + -- Emit order (fsm.md §Conflicts/scheduling §Suggested comb order): + -- 1) cancel() port0 (cancelEn) forwarded into v.cancel / v.gracefulStop + -- 2) recvDmaResp (R3) — cancel-independent + -- 3) R1/R2/R4 evaluated off v.cancel and v.gracefulStop + FIFO/child flags + -- 4) setGracefulStop is part of (3); resetAndClear (R0) port1 writes last + --------------------------------------------------------------------------- + comb : process (r, rst, clearAll, cancelEn, + reqQValid, reqQDout, + respQNotFull, respQValid, + pendCntrlNotFull, pendCntrlValid, pendCntrlDout, + pendReadNotFull, pendReadValid, pendReadDout, + childReqPutReady, childRespQValid, childRespQDout, + dmaReqReady, dmaRespValid, dmaRespIn) is + variable v : RegType; + -- recvReq (R1) datapath off U_ReqQ front (DmaReadCntrlReq layout) + variable startAddr : slv(63 downto 0); + variable totalLen : slv(31 downto 0); + variable pmtu : slv(2 downto 0); + variable chunkReqData : slv(98 downto 0); -- AddrChunkReq to child + -- issueDmaReq (R2) datapath off pending-cntrl front + child resp front + variable initiator : slv(3 downto 0); + variable sqpn : slv(23 downto 0); + variable wrID : slv(63 downto 0); + variable mrIdx : slv(6 downto 0); + variable chunkAddr : slv(63 downto 0); + variable chunkLen : slv(12 downto 0); + variable chunkIsFirst : sl; + variable chunkIsLast : sl; + variable dmaReadReq : slv(175 downto 0); -- DmaReadReq to dmaReadSrv + -- recvDmaResp (R3) datapath + variable isOrigFirst : sl; + variable isOrigLast : sl; + begin + v := r; + + ---------------------------------------------------------------------- + -- Combinational datapath extraction (harmless to compute every cycle; + -- only committed under the corresponding rule guard below). + ---------------------------------------------------------------------- + -- recvReq (R1): AddrChunkReq = startAddr(64) & totalLen(32) & pmtu(3) + startAddr := reqQDout(105 downto 42); + totalLen := reqQDout(41 downto 10); + pmtu := reqQDout(2 downto 0); + chunkReqData := startAddr & totalLen & pmtu; + + -- issueDmaReq (R2): compose DmaReadReq from the pending-cntrl front and + -- the child's AddrChunkResp front. + initiator := pendCntrlDout(197 downto 194); + sqpn := pendCntrlDout(193 downto 170); + wrID := pendCntrlDout(169 downto 106); + mrIdx := pendCntrlDout(9 downto 3); + chunkAddr := childRespQDout(78 downto 15); + chunkLen := childRespQDout(14 downto 2); + chunkIsFirst := childRespQDout(1); + chunkIsLast := childRespQDout(0); + -- DmaReadReq = initiator & sqpn & wrID & startAddr(=chunkAddr) & len(=chunkLen) & mrIdx + dmaReadReq := initiator & sqpn & wrID & chunkAddr & chunkLen & mrIdx; + + -- recvDmaResp (R3): AND the response stream first/last with the chunk's + -- first/last so the re-assembled stream reports the ORIGINAL boundaries. + isOrigFirst := dmaRespIn(1) and pendReadDout(1); + isOrigLast := dmaRespIn(0) and pendReadDout(0); + + ---------------------------------------------------------------------- + -- Default Mealy outputs / SURF & child drives (deasserted / front data). + -- The "din"/"out" defaults carry the combinational front so the Mealy + -- paths are correct whenever their enable is asserted below. + ---------------------------------------------------------------------- + reqQRdEn <= '0'; + respQWrEn <= '0'; + respQDin <= dmaRespIn & isOrigFirst & isOrigLast; -- 383+1+1=385 + pendCntrlWrEn <= '0'; + pendCntrlDin <= reqQDout; -- enq whole 198-bit request (R1) + pendCntrlRdEn <= '0'; + pendReadWrEn <= '0'; + pendReadDin <= dmaReadReq & chunkIsFirst & chunkIsLast; -- 176+1+1=178 + pendReadRdEn <= '0'; + dmaReqValid <= '0'; + dmaReqOut <= dmaReadReq; -- Mealy front; gated by dmaReqValid + dmaRespReady <= '0'; + childReqPutWrEn <= '0'; + childReqPutDin <= chunkReqData; -- Mealy front; gated by childReqPutWrEn + childRespGetRdEn <= '0'; + + ---------------------------------------------------------------------- + -- (1) CReg cancel() port0: dmaCntrl.cancel() method (cancelEn). + -- Forwarded into the R1/R2/R4 guards this same cycle (same-cycle + -- cancel); also re-arms gracefulStop to '0' (port0 write). + ---------------------------------------------------------------------- + if cancelEn = '1' then + v.cancel := '1'; + v.gracefulStop := '0'; + end if; + + ---------------------------------------------------------------------- + -- (2) recvDmaResp (R3): cancel-INDEPENDENT. Get one DmaReadResp -> + -- enq the 385-bit DmaReadCntrlResp into U_RespQ; on the LAST DMA + -- fragment retire (deq) one pending-read token. This drains + -- U_PendingDmaReadReqQ so R4 can eventually latch while cancelling. + ---------------------------------------------------------------------- + if (clearAll = '0' and dmaRespValid = '1' and pendReadValid = '1' and + respQNotFull = '1') then + dmaRespReady <= '1'; -- get external server response + respQWrEn <= '1'; -- enq U_RespQ (respQDin set above) + if dmaRespIn(0) = '1' then -- dataStream.isLast -> retire token + pendReadRdEn <= '1'; -- deq U_PendingDmaReadReqQ (per fragment) + end if; + end if; + + ---------------------------------------------------------------------- + -- (3) Forwarding path on {cancel, gracefulStop} (all guard !clearAll). + -- R1/R2 (RUN_S, !cancel) are mutually exclusive with R4 + -- (CANCELLING_S, cancel) on v.cancel. + ---------------------------------------------------------------------- + if clearAll = '0' then + if v.cancel = '0' then + -- R1 recvReq: deq U_ReqQ; enq the whole request into the pending- + -- cntrl queue; push an AddrChunkReq into the child. Implicit + -- conds: reqQ has data, pending-cntrl has room, child can accept. + if (reqQValid = '1' and pendCntrlNotFull = '1' and + childReqPutReady = '1') then + reqQRdEn <= '1'; -- deq U_ReqQ + pendCntrlWrEn <= '1'; -- enq U_PendingDmaCntrlReqQ (din=reqQDout) + childReqPutWrEn <= '1'; -- child request.put (din=chunkReqData) + end if; + + -- R2 issueDmaReq: get one AddrChunkResp from the child, Put one + -- DmaReadReq to dmaReadSrv, enq a pending-read token. On the LAST + -- chunk of the request, retire the pending-cntrl entry. Implicit + -- conds: child has a resp, pending-cntrl has a head, server ready, + -- pending-read has room. + if (childRespQValid = '1' and pendCntrlValid = '1' and + dmaReqReady = '1' and pendReadNotFull = '1') then + childRespGetRdEn <= '1'; -- get child response + dmaReqValid <= '1'; -- Put external request (dmaReqOut set above) + pendReadWrEn <= '1'; -- enq U_PendingDmaReadReqQ (din set above) + if chunkIsLast = '1' then -- addrChunkResp.isLast -> request done + pendCntrlRdEn <= '1'; -- deq U_PendingDmaCntrlReqQ (per original req) + end if; + end if; + + else + -- cancel = '1' (CANCELLING_S / STOPPED_S). R1/R2 blocked. + -- R4 setGracefulStop: latch once both the response queue and the + -- pending-read queue have drained (no in-flight responses). Reads + -- v.gracefulStop (post-port0; cancel() may have re-armed it to '0'). + if (v.gracefulStop = '0' and respQValid = '0' and + pendReadValid = '0') then + v.gracefulStop := '1'; + end if; + end if; + end if; + + ---------------------------------------------------------------------- + -- (4) resetAndClear (R0) port1 writes: clearAll dominates all rules and + -- forces both control bits to '0' (FIFOs cleared via fifoRst pins; + -- the child clears via its own clearAllI). + ---------------------------------------------------------------------- + if clearAll = '1' then + v.cancel := '0'; + v.gracefulStop := '0'; + end if; + + -- Synchronous reset (matches BSV mkCReg(_,False) reset) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd b/ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd new file mode 100644 index 0000000000..ebb03eea64 --- /dev/null +++ b/ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd @@ -0,0 +1,760 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- SGL-aware read controller for the SQ payload generator. Each incoming +-- DmaReadCntrlReq (1163b) carries a full scatter-gather list (MAX_SGE=8 SGEs). +-- * recvReq (R1) walks the SGL one SGE per cycle (sglIdxReg), emitting a +-- per-SGE MergedMetaDataSGE side stream +-- (U_SgeMergedMetaDataOutQ) and pushing each SGE+PMTU +-- into the chunker pipeline (U_PendingScatterGatherElemQ). +-- It deqs U_ReqQ ONLY on the SGL's last SGE (sge.isLast), +-- and enqs the per-SGL {sqpn,wrID} into +-- U_PendingDmaCntrlReqQ ONLY on the first SGE +-- (sge.isFirst). +-- * issueChunkReq(R2) pops one SGE, pushes an AddrChunkReq into the child +-- U_AddrChunkSrv, and stashes the SGE's lkey in +-- U_PendingLKeyQ. +-- * issueDmaReq (R3) pops one AddrChunkResp from the child, composes one +-- external DmaReadReq (one per PMTU chunk), and tokenises +-- the SGL-level first/last flags into U_PendingDmaReadReqQ. +-- * recvDmaResp (R4) re-assembles the streamed DmaReadResp fragments into +-- DmaReadCntrlResps that carry the *SGL-level* first/last +-- flags, into U_RespQ. +-- Cancel / graceful-stop mirrors DmaReadCntrlConAndGen and DmaWriteCntrl. +-- +-- There is NO explicit state-enum register. Two control axes coexist: +-- (1) the {cancel, gracefulStop} CReg sub-FSM (two boolean RegType fields): +-- RUN_S = {cancel=0} — R1/R2/R3/R4 active +-- CANCELLING_S = {cancel=1,grStop=0} — R1/R2/R3 blocked; R4 keeps +-- draining; await respQ + +-- pendingDmaReadReqQ empty +-- STOPPED_S = {cancel=1,grStop=1} — quiesced; isIdle() true +-- {cancel=0,gracefulStop=1} is unreachable. +-- (2) sglIdxReg (3b) — the SGL-walk index inside recvReq (counter-as-state). +-- +-- The four pipeline rules carry (* conflict_free *) (PayloadGen.bsv:730-733) +-- and touch DISJOINT FIFO enq/deq pairs, so all four may fire the SAME cycle +-- (a 4-stage pipeline). Each is emitted as an independent if-block in comb. +-- +-- Boundaries: +-- * Server to its caller (srvPort: request Put / response Get, wired through +-- U_ReqQ / U_RespQ). +-- * Client of the external Server dmaReadSrv (request Put dmaReqOut / +-- response Get dmaRespIn). +-- * Two PipeOut outputs: sgeMergedMetaDataPipeOut (8b, from the parent +-- U_SgeMergedMetaDataOutQ) and sgePktMetaDataPipeOut (54b, re-exported +-- DIRECTLY from the child U_AddrChunkSrv — no parent FIFO, no FSM logic). +-- +-- THREE distinct "last" conditions (fsm.md §Notes; do NOT conflate): +-- addrChunkResp.isLast (last CHUNK of an SGE) -> deq U_PendingLKeyQ +-- isLastDmaReqChunk (= isLast AND isOrigLast SGE) -> deq U_PendingDmaCntrlReqQ +-- dmaResp.dataStream.isLast (last FRAGMENT of a DMA resp)-> deq U_PendingDmaReadReqQ +-- +-- CReg semantics (fsm.md §CReg semantics) — each mkCReg(2,False) is ONE RegType +-- field, writes applied in port order so reads see the forwarded value: +-- cancel : v:=r; port0 (cancelEn) sets '1' BEFORE R1/R2/R3/R5 read +-- v.cancel (same-cycle cancel); port1 (clearAll) clears '0' +-- last (dominates). +-- gracefulStop : port0 read (isIdle) uses r.gracefulStop (pre-update, Moore); +-- port0 write (cancelEn) re-arms '0'; R5 then sets '1'; +-- port1 (clearAll) clears '0' last (dominates). +-- Net: clearAll->0; else setGracefulStop->1; else cancelEn->0; +-- else hold. +-- +-- Mealy (combinational) request paths (fsm.md §Output style) — MUST NOT be +-- registered: +-- dmaReqOut = composed DmaReadReq (sqpn/wrID from the pending-cntrl +-- front, chunkAddr/chunkLen from the child resp front, +-- mrIdx from the pending-lkey front), gated by dmaReqValid +-- (R3). +-- childReqPutDin = AddrChunkReq off the pending-SGE front, gated by +-- childReqPutWrEn (R2). +-- U_RespQ.din = DmaReadResp & isFirstFragInSGL & isLastFragInSGL, +-- computed in R4 and then registered INSIDE the Fifo. +-- +-- sglIdxReg / totalLenReg / sgeNumReg (fsm.md §State register): +-- sglIdxReg is genuine state (selects the SGE, paces the U_ReqQ deq). +-- totalLenReg/sgeNumReg are DEAD for synthesis (totalLenReg feeds only a +-- sim-only immAssert / commented-out enq; sgeNumReg is never read). Kept +-- in RegType for source fidelity per OQ-FSM-DRCG-04; a synth tool may prune +-- them. +-- +-- FIFO clear (OQ-FSM-01 carry-forward, RESOLVED in out/03-fsm/RESOLVED.md): +-- BSV resetAndClear .clear of all seven FIFOs maps to asserting each Fifo's +-- rst, OR'd with the structural reset: fifoRst = rst OR clearAll. Requires +-- GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, RST_POLARITY_G='1'. All seven +-- share fifoRst so the BSV single-cycle simultaneous clear is preserved. The +-- child clears via its own clearAllI (= clearAll). +-- +-- Open-question carry-forwards (out/04-vhdl/OPEN_QUESTIONS.md and +-- out/03-fsm/DmaReadCntrlGen.fsm.md §Open issues): +-- OQ-FSM-DRCG-01 — mapping.json/modules.json are WRONG for this entity +-- (fabricated issueReq/recvResp/cancelFlush rules; five FIFOs +-- and three registers + the child + two PipeOut outputs +-- missing). This file follows the FSM spec / LIVE BSV: SEVEN +-- surf.Fifo + one U_AddrChunkSrv child. +-- OQ-FSM-DRCG-02 — new_ports=[] is incomplete: clearAll, the dmaReadSrv +-- Server-client handshake, and BOTH PipeOut output groups are +-- real top-level ports (enumerated below). +-- OQ-FSM-DRCG-03 — Vector packing direction for sgl[sglIdx]: element 0 at the +-- MSB of the 1040b sgl region (project-wide first-element-at- +-- MSB convention, shared with OQ-FSM-H2DS-04). Correctness +-- needs only producer/consumer agreement; both sides are this +-- pipeline. +-- OQ-FSM-DRCG-04 — totalLenReg/sgeNumReg dead for synthesis (kept for +-- fidelity). +-- +-- Bit layouts (BSV deriving(Bits), first-field-at-MSB; fsm.md §Bit layouts): +-- +-- DmaReadCntrlReq (1163b) — U_ReqQ element: +-- [1162:123] sgl (Vector#(8,SGE), element 0 at MSB; SGE i at +-- (1162-130*i) downto (1033-130*i)) +-- [122:91] totalLen(32) [90:67] sqpn(24) [66:3] wrID(64) [2:0] pmtu(3) +-- ScatterGatherElem (130b) — selected sgl[sglIdx] slice, bits within the SGE: +-- [129:66] laddr(64) [65:34] len(32) [33:2] lkey(32) [1] isFirst [0] isLast +-- MergedMetaDataSGE (8b) — U_SgeMergedMetaDataOutQ element: +-- [7:2] lastFragValidByteNum(6) [1] isFirst [0] isLast +-- Tuple2#(SGE,PMTU) (133b) — U_PendingScatterGatherElemQ element: +-- [132:3] sge(130) [2:0] pmtu(3) +-- Tuple2#(QPN,WorkReqID) (88b) — U_PendingDmaCntrlReqQ element: +-- [87:64] sqpn(24) [63:0] wrID(64) +-- AddrChunkReq (101b, Gen) — childReqPutDin: +-- [100:37] startAddr(64) [36:5] len(32) [4:2] pmtu(3) [1] isFirst [0] isLast +-- AddrChunkResp (81b, Gen) — childRespQDout: +-- [80:17] chunkAddr(64) [16:4] chunkLen(13) [3] isFirst [2] isLast +-- [1] isOrigFirst [0] isOrigLast +-- DmaReadReq (176b) — dmaReqOut: +-- [175:172] initiator(4) [171:148] sqpn(24) [147:84] wrID(64) +-- [83:20] startAddr(64) [19:7] len(13,PktLen) [6:0] mrIdx(7) +-- DmaReadResp (383b) — dmaRespIn: +-- [382:379] initiator(4) [378:355] sqpn(24) [354:291] wrID(64) +-- [290] isRespErr [289:34] data(256) [33:2] byteEn(32) [1] isFirst [0] isLast +-- DmaReadCntrlResp (385b) — U_RespQ element: +-- [384:2] dmaReadResp(383) [1] isFirstFragInSGL [0] isLastFragInSGL +-- Tuple2#(Bool,Bool) (2b) — U_PendingDmaReadReqQ element: +-- [1] isFirstDmaReqChunk [0] isLastDmaReqChunk +-- +-- calcLastFragValidByteNum(len) (Utils.bsv:165-180) -> 6b: +-- residue := len(4:0); +-- (residue=0 AND len(31:5)/=0) ? 32 : ('0' & residue) +-- key2IndexMR(lkey) (Utils.bsv:416, truncateLSB) -> 7b: mrIdx := lkey(31:25) +-- DMA_SRC_SQ_RD = enum index 5 of DmaReqSrcType (DataTypes.bsv:302-314, +-- commented members excluded) => 4-bit "0101". +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_ReqQ : surf.Fifo DATA_WIDTH_G=1163 (DmaReadCntrlReq) +-- U_RespQ : surf.Fifo DATA_WIDTH_G=385 (DmaReadCntrlResp) +-- U_SgeMergedMetaDataOutQ : surf.Fifo DATA_WIDTH_G=8 (MergedMetaDataSGE) +-- U_PendingScatterGatherElemQ : surf.Fifo DATA_WIDTH_G=133 (Tuple2#(SGE,PMTU)) +-- U_PendingLKeyQ : surf.Fifo DATA_WIDTH_G=32 (LKEY) +-- U_PendingDmaCntrlReqQ : surf.Fifo DATA_WIDTH_G=88 (Tuple2#(QPN,WRID)) +-- U_PendingDmaReadReqQ : surf.Fifo DATA_WIDTH_G=2 (Tuple2#(Bool,Bool)) +-- Child entity instantiated: +-- U_AddrChunkSrv : AddrChunkSrvGen (out/04-vhdl/AddrChunkSrvGen.vhd) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity DmaReadCntrlGen is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (module parameter clearAll; synchronous, LEVEL-asserted) + clearAll : in sl; + -- dmaCntrl.cancel() method (Action pulse): request graceful cancel + cancelEn : in sl; + -- srvPort.request : Put#(DmaReadCntrlReq) (caller -> entity, enq to reqQ) + reqInValid : in sl; -- caller offers a request (wr_en) + reqInData : in slv(1162 downto 0); -- DmaReadCntrlReq packed + reqInReady : out sl; -- entity can accept (reqQ.notFull) + -- srvPort.response : Get#(DmaReadCntrlResp) (entity -> caller, deq from respQ) + respOutReady : in sl; -- caller takes a response (rd_en) + respOutValid : out sl; -- response available (respQ.notEmpty) + respOutData : out slv(384 downto 0); -- DmaReadCntrlResp packed + -- sgeMergedMetaDataPipeOut : PipeOut#(MergedMetaDataSGE) (entity -> caller) + sgeMergedRdEn : in sl; -- caller deq + sgeMergedValid : out sl; -- data available (notEmpty) + sgeMergedData : out slv(7 downto 0); -- MergedMetaDataSGE packed + -- sgePktMetaDataPipeOut : PipeOut#(PktMetaDataSGE) (re-exported from child) + sgePktMetaRdEn : in sl; -- caller deq -> child + sgePktMetaValid : out sl; -- child respQ.notEmpty + sgePktMetaData : out slv(53 downto 0); -- PktMetaDataSGE packed (child) + -- dmaReadSrv.request : Put#(DmaReadReq) (entity -> external server, CLIENT) + dmaReqValid : out sl; -- entity offers a request (Mealy) + dmaReqOut : out slv(175 downto 0); -- DmaReadReq packed (Mealy) + dmaReqReady : in sl; -- external server can accept + -- dmaReadSrv.response : Get#(DmaReadResp) (external server -> entity, CLIENT) + dmaRespValid : in sl; -- external server offers a response + dmaRespIn : in slv(382 downto 0); -- DmaReadResp packed + dmaRespReady : out sl; -- entity takes the response (get/pop) + -- dmaCntrl.isIdle() method result (Moore, registered) + isIdle : out sl); +end entity DmaReadCntrlGen; + +architecture rtl of DmaReadCntrlGen is + + -- DmaReqSrcType enum index 5 (DataTypes.bsv:302-314, commented members excluded) + constant DMA_SRC_SQ_RD_C : slv(3 downto 0) := "0101"; + + -- Control sub-FSM state: two CReg booleans + the SGL-walk index. The two + -- accumulators are dead for synthesis (OQ-FSM-DRCG-04) but kept for fidelity. + type RegType is record + cancel : sl; -- cancelReg[2] <- mkCReg(2,False) + gracefulStop : sl; -- gracefulStopReg[2] <- mkCReg(2,False) + sglIdxReg : slv(2 downto 0); -- mkReg(0) : IdxSGL, SGL-walk index + totalLenReg : slv(31 downto 0); -- mkRegU : Length accumulator (dead) + sgeNumReg : slv(3 downto 0); -- mkRegU : NumSGE accumulator (dead) + end record RegType; + + constant REG_INIT_C : RegType := ( + cancel => '0', + gracefulStop => '0', + sglIdxReg => (others => '0'), + totalLenReg => (others => '0'), + sgeNumReg => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_ReqQ (DmaReadCntrlReq, 1163b) + signal reqQValid : sl; -- = reqQ.notEmpty (FWFT data valid) + signal reqQDout : slv(1162 downto 0); + signal reqQRdEn : sl; + + -- U_RespQ (DmaReadCntrlResp, 385b) + signal respQNotFull : sl; + signal respQValid : sl; -- = respQ.notEmpty (R5 quiescence guard) + signal respQWrEn : sl; + signal respQDin : slv(384 downto 0); + + -- U_SgeMergedMetaDataOutQ (MergedMetaDataSGE, 8b) + signal sgeMergedNotFull : sl; + signal sgeMergedWrEn : sl; + signal sgeMergedDin : slv(7 downto 0); + + -- U_PendingScatterGatherElemQ (Tuple2#(SGE,PMTU), 133b) + signal pscElemNotFull : sl; + signal pscElemValid : sl; -- = notEmpty + signal pscElemWrEn : sl; + signal pscElemDin : slv(132 downto 0); + signal pscElemRdEn : sl; + signal pscElemDout : slv(132 downto 0); + + -- U_PendingLKeyQ (LKEY, 32b) + signal lkeyNotFull : sl; + signal lkeyValid : sl; -- = notEmpty + signal lkeyWrEn : sl; + signal lkeyDin : slv(31 downto 0); + signal lkeyRdEn : sl; + signal lkeyDout : slv(31 downto 0); + + -- U_PendingDmaCntrlReqQ (Tuple2#(QPN,WorkReqID), 88b) + signal pendCntrlNotFull : sl; + signal pendCntrlValid : sl; -- = notEmpty + signal pendCntrlWrEn : sl; + signal pendCntrlDin : slv(87 downto 0); + signal pendCntrlRdEn : sl; + signal pendCntrlDout : slv(87 downto 0); + + -- U_PendingDmaReadReqQ (Tuple2#(Bool,Bool), 2b) + signal pendReadNotFull : sl; + signal pendReadValid : sl; -- = notEmpty (R5 quiescence guard) + signal pendReadWrEn : sl; + signal pendReadDin : slv(1 downto 0); + signal pendReadRdEn : sl; + signal pendReadDout : slv(1 downto 0); + + -- U_AddrChunkSrv child interface + signal childReqPutWrEn : sl; -- FSM (issueChunkReq) -> child request.put + signal childReqPutDin : slv(100 downto 0); + signal childReqPutReady : sl; -- child reqQ.notFull (R2 implicit cond) + signal childRespGetRdEn : sl; -- FSM (issueDmaReq) -> child response.get + signal childRespQValid : sl; -- child respQ.notEmpty (R3 implicit cond) + signal childRespQDout : slv(80 downto 0); + + -- FIFO reset line: level = rst OR clearAll (atomic 7-FIFO clear) + signal fifoRst : sl; + +begin + + -- FIFO reset: level-sensitive clear (OQ-FSM-01 carry-forward, RESOLVED) + fifoRst <= rst or clearAll; + + -- srvPort response valid pass-through (also used by R5 quiescence guard) + respOutValid <= respQValid; + + -- isIdle() method (Moore): registered gracefulStop (CReg port0 read of the + -- REGISTERED value). Drive from r, NOT v. + isIdle <= r.gracefulStop; + + --------------------------------------------------------------------------- + -- U_ReqQ : surf.Fifo + -- Inbound DmaReadCntrlReq queue (BSV mkFIFOF reqQ). wr side = caller's + -- srvPort.request.put (pass-through); rd side = FSM (recvReq deq on the + -- SGL's last SGE only). + --------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1163, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqInValid, -- pass-through (caller drives) + din => reqInData, -- pass-through (caller drives) + not_full => reqInReady, -- pass-through to caller + rd_clk => clk, + rd_en => reqQRdEn, -- FSM (recvReq, on sge.isLast) + dout => reqQDout, + valid => reqQValid); + + --------------------------------------------------------------------------- + -- U_RespQ : surf.Fifo + -- Outbound DmaReadCntrlResp queue (BSV mkFIFOF respQ). wr = FSM + -- (recvDmaResp enq); rd = caller's srvPort.response.get (pass-through). + --------------------------------------------------------------------------- + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 385, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => respQWrEn, -- FSM (recvDmaResp) + din => respQDin, -- FSM (recvDmaResp) + not_full => respQNotFull, + rd_clk => clk, + rd_en => respOutReady, -- pass-through (caller drives) + dout => respOutData, + valid => respQValid); + + --------------------------------------------------------------------------- + -- U_SgeMergedMetaDataOutQ : surf.Fifo + -- Per-SGE MergedMetaDataSGE side stream (BSV mkSizedFIFOF(MAX_SGE)). + -- wr = FSM (recvReq, every SGE); rd = caller (sgeMergedMetaDataPipeOut). + -- ADDR_WIDTH_G=4 (capacity 15 >= MAX_SGE=8). + --------------------------------------------------------------------------- + U_SgeMergedMetaDataOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 8, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => sgeMergedWrEn, -- FSM (recvReq) + din => sgeMergedDin, -- FSM (recvReq) + not_full => sgeMergedNotFull, + rd_clk => clk, + rd_en => sgeMergedRdEn, -- pass-through (caller drives) + dout => sgeMergedData, + valid => sgeMergedValid); + + --------------------------------------------------------------------------- + -- U_PendingScatterGatherElemQ : surf.Fifo + -- SGE+PMTU staged for the chunker (BSV mkSizedFIFOF(MAX_SGE)). + -- wr = FSM (recvReq, every SGE); rd = FSM (issueChunkReq). + -- ADDR_WIDTH_G=4 (capacity 15 >= MAX_SGE=8). + --------------------------------------------------------------------------- + U_PendingScatterGatherElemQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 133, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pscElemWrEn, -- FSM (recvReq) + din => pscElemDin, -- FSM (recvReq) + not_full => pscElemNotFull, + rd_clk => clk, + rd_en => pscElemRdEn, -- FSM (issueChunkReq) + dout => pscElemDout, + valid => pscElemValid); + + --------------------------------------------------------------------------- + -- U_PendingLKeyQ : surf.Fifo + -- Per-SGE lkey held until its chunks are issued (BSV mkFIFOF). + -- wr = FSM (issueChunkReq); rd = FSM (issueDmaReq, on addrChunkResp.isLast). + --------------------------------------------------------------------------- + U_PendingLKeyQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 32, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => lkeyWrEn, -- FSM (issueChunkReq) + din => lkeyDin, -- FSM (issueChunkReq) + not_full => lkeyNotFull, + rd_clk => clk, + rd_en => lkeyRdEn, -- FSM (issueDmaReq, on chunk.isLast) + dout => lkeyDout, + valid => lkeyValid); + + --------------------------------------------------------------------------- + -- U_PendingDmaCntrlReqQ : surf.Fifo + -- Per-SGL {sqpn,wrID} (BSV mkFIFOF). wr = FSM (recvReq, only on + -- sge.isFirst); rd = FSM (issueDmaReq, only on isLastDmaReqChunk). + --------------------------------------------------------------------------- + U_PendingDmaCntrlReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 88, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pendCntrlWrEn, -- FSM (recvReq, on sge.isFirst) + din => pendCntrlDin, -- FSM (recvReq) + not_full => pendCntrlNotFull, + rd_clk => clk, + rd_en => pendCntrlRdEn, -- FSM (issueDmaReq, on isLastDmaReqChunk) + dout => pendCntrlDout, + valid => pendCntrlValid); + + --------------------------------------------------------------------------- + -- U_PendingDmaReadReqQ : surf.Fifo + -- One token per issued DMA-read chunk: {isFirstDmaReqChunk, + -- isLastDmaReqChunk} (BSV mkFIFOF). wr = FSM (issueDmaReq); rd = FSM + -- (recvDmaResp, on dataStream.isLast). R5's graceful-stop guard reads its + -- notEmpty, so distributed RAM is used for enq->notEmpty timing fidelity + -- (mirrors the DmaReadCntrlConAndGen/DmaWriteCntrl rationale; OQ-EMIT-08). + --------------------------------------------------------------------------- + U_PendingDmaReadReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 2, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pendReadWrEn, -- FSM (issueDmaReq) + din => pendReadDin, -- FSM (issueDmaReq) + not_full => pendReadNotFull, + rd_clk => clk, + rd_en => pendReadRdEn, -- FSM (recvDmaResp, on dataStream.isLast) + dout => pendReadDout, + valid => pendReadValid); + + --------------------------------------------------------------------------- + -- U_AddrChunkSrv : AddrChunkSrvGen (child entity, not SURF) + -- BSV: addrChunkSrv <- mkAddrChunkSrv(clearAll). Server pair: parent drives + -- request.put / response.get. Its sgePktMetaDataPipeOut is RE-EXPORTED + -- directly as the parent's sgePktMetaDataPipeOut (no parent FIFO/logic). + -- The child's isIdle is not read by this parent (left open). + --------------------------------------------------------------------------- + U_AddrChunkSrv : entity surf.AddrChunkSrvGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAllI => clearAll, + reqPutValid => childReqPutWrEn, + reqPutData => childReqPutDin, + reqPutReady => childReqPutReady, + respGetReady => childRespGetRdEn, + respGetValid => childRespQValid, + respGetData => childRespQDout, + sgePktMetaRdEn => sgePktMetaRdEn, -- re-export: caller deq -> child + sgePktMetaValid => sgePktMetaValid, -- re-export: child -> caller + sgePktMetaData => sgePktMetaData, -- re-export: child -> caller + isIdle => open); -- parent does not read child isIdle + + --------------------------------------------------------------------------- + -- Combinatorial process + -- Emit order (fsm.md §Conflicts/scheduling §Suggested comb order): + -- 1) cancel() port0 (cancelEn) forwarded into v.cancel / v.gracefulStop + -- 2) recvDmaResp (R4) — cancel-independent + -- 3) if !cancel: R1/R2/R3 (independent CF blocks); else: R5 setGracefulStop + -- 4) resetAndClear (R0) port1 writes last (clearAll dominates) + --------------------------------------------------------------------------- + comb : process (r, rst, clearAll, cancelEn, + reqQValid, reqQDout, + respQNotFull, respQValid, + sgeMergedNotFull, + pscElemNotFull, pscElemValid, pscElemDout, + lkeyNotFull, lkeyValid, lkeyDout, + pendCntrlNotFull, pendCntrlValid, pendCntrlDout, + pendReadNotFull, pendReadValid, pendReadDout, + childReqPutReady, childRespQValid, childRespQDout, + dmaReqReady, dmaRespValid, dmaRespIn) is + variable v : RegType; + -- recvReq (R1) datapath off U_ReqQ front (DmaReadCntrlReq layout) + variable sglIdxInt : integer range 0 to 7; + variable sgeHi : integer range 252 to 1162; + variable sge : slv(129 downto 0); -- selected sgl[sglIdx] + variable sgeLen : slv(31 downto 0); + variable mergedByte : slv(5 downto 0); -- calcLastFragValidByteNum + variable sqpnR1 : slv(23 downto 0); + variable wrIDR1 : slv(63 downto 0); + -- issueChunkReq (R2) datapath off U_PendingScatterGatherElemQ front + variable sge2 : slv(129 downto 0); + variable pmtu2 : slv(2 downto 0); + -- issueDmaReq (R3) datapath off child resp / lkey / pending-cntrl fronts + variable chunkAddr : slv(63 downto 0); + variable chunkLen : slv(12 downto 0); + variable mrIdx : slv(6 downto 0); + variable curSqpn : slv(23 downto 0); + variable curWrID : slv(63 downto 0); + variable dmaReadReqV : slv(175 downto 0); + variable isFirstChunk : sl; -- isFirstDmaReqChunk + variable isLastChunk : sl; -- isLastDmaReqChunk + -- recvDmaResp (R4) datapath + variable isFirstFrag : sl; -- isFirstFragInSGL + variable isLastFrag : sl; -- isLastFragInSGL + begin + v := r; + + ---------------------------------------------------------------------- + -- Combinational datapath extraction (harmless every cycle; committed + -- only under the corresponding rule guard below). + ---------------------------------------------------------------------- + -- R1: select sgl[sglIdx] (element 0 at MSB; OQ-FSM-DRCG-03). sgl occupies + -- reqQDout(1162:123); SGE i at (1162-130*i) downto (1033-130*i). + sglIdxInt := to_integer(unsigned(r.sglIdxReg)); + sgeHi := 1162 - 130 * sglIdxInt; + sge := reqQDout(sgeHi downto sgeHi - 129); + sgeLen := sge(65 downto 34); + -- calcLastFragValidByteNum(sge.len): residue=len(4:0); + -- (residue=0 AND len(31:5)/=0) ? 32 : ('0' & residue) + if (sgeLen(4 downto 0) = "00000") and (unsigned(sgeLen(31 downto 5)) /= 0) then + mergedByte := "100000"; -- 32 + else + mergedByte := '0' & sgeLen(4 downto 0); + end if; + sqpnR1 := reqQDout(90 downto 67); + wrIDR1 := reqQDout(66 downto 3); + + -- R2: {sge,pmtu} off the pending-SGE front (133b = sge(132:3) & pmtu(2:0)) + sge2 := pscElemDout(132 downto 3); + pmtu2 := pscElemDout(2 downto 0); + + -- R3: compose DmaReadReq from child resp / lkey / pending-cntrl fronts. + chunkAddr := childRespQDout(80 downto 17); + chunkLen := childRespQDout(16 downto 4); + mrIdx := lkeyDout(31 downto 25); -- key2IndexMR (truncateLSB) + curSqpn := pendCntrlDout(87 downto 64); + curWrID := pendCntrlDout(63 downto 0); + -- DmaReadReq = initiator & sqpn & wrID & startAddr(=chunkAddr) & len(=chunkLen) & mrIdx + dmaReadReqV := DMA_SRC_SQ_RD_C & curSqpn & curWrID & chunkAddr & chunkLen & mrIdx; + -- isFirstDmaReqChunk = chunk.isFirst AND chunk.isOrigFirst + -- isLastDmaReqChunk = chunk.isLast AND chunk.isOrigLast + isFirstChunk := childRespQDout(3) and childRespQDout(1); + isLastChunk := childRespQDout(2) and childRespQDout(0); + + -- R4: AND the response stream first/last with the chunk SGL-level first/last + isFirstFrag := dmaRespIn(1) and pendReadDout(1); + isLastFrag := dmaRespIn(0) and pendReadDout(0); + + ---------------------------------------------------------------------- + -- Default Mealy outputs / SURF & child drives (deasserted; din/out carry + -- the combinational front so the Mealy paths are correct when enabled). + ---------------------------------------------------------------------- + reqQRdEn <= '0'; + respQWrEn <= '0'; + respQDin <= dmaRespIn & isFirstFrag & isLastFrag; -- 383+1+1=385 + sgeMergedWrEn <= '0'; + sgeMergedDin <= mergedByte & sge(1) & sge(0); -- 6+1+1=8 + pscElemWrEn <= '0'; + pscElemDin <= sge & reqQDout(2 downto 0); -- sge(130) & pmtu(3) (R1 front) + pscElemRdEn <= '0'; + lkeyWrEn <= '0'; + lkeyDin <= sge2(33 downto 2); -- sge.lkey (R2 front) + lkeyRdEn <= '0'; + pendCntrlWrEn <= '0'; + pendCntrlDin <= sqpnR1 & wrIDR1; -- {sqpn,wrID} (R1 front) + pendCntrlRdEn <= '0'; + pendReadWrEn <= '0'; + pendReadDin <= isFirstChunk & isLastChunk; -- 2b (R3 front) + pendReadRdEn <= '0'; + dmaReqValid <= '0'; + dmaReqOut <= dmaReadReqV; -- Mealy front; gated by dmaReqValid + dmaRespReady <= '0'; + childReqPutWrEn <= '0'; + -- AddrChunkReq = laddr(64) & len(32) & pmtu(3) & isFirst(1) & isLast(1) (R2 front) + childReqPutDin <= sge2(129 downto 66) & sge2(65 downto 34) & pmtu2 & + sge2(1) & sge2(0); + childRespGetRdEn <= '0'; + + ---------------------------------------------------------------------- + -- (1) CReg cancel() port0: dmaCntrl.cancel() method (cancelEn). + -- Forwarded into the R1/R2/R3/R5 guards this same cycle; also re-arms + -- gracefulStop to '0' (port0 write). + ---------------------------------------------------------------------- + if cancelEn = '1' then + v.cancel := '1'; + v.gracefulStop := '0'; + end if; + + ---------------------------------------------------------------------- + -- (2) recvDmaResp (R4): cancel-INDEPENDENT. Get one DmaReadResp -> enq the + -- 385-bit DmaReadCntrlResp into U_RespQ; on the LAST DMA fragment + -- retire (deq) one pending-read token. This drains + -- U_PendingDmaReadReqQ so R5 can eventually latch while cancelling. + ---------------------------------------------------------------------- + if (clearAll = '0' and dmaRespValid = '1' and pendReadValid = '1' and + respQNotFull = '1') then + dmaRespReady <= '1'; -- get external server response + respQWrEn <= '1'; -- enq U_RespQ (respQDin set above) + if dmaRespIn(0) = '1' then -- dataStream.isLast -> retire token + pendReadRdEn <= '1'; -- deq U_PendingDmaReadReqQ (per fragment) + end if; + end if; + + ---------------------------------------------------------------------- + -- (3) Pipeline rules on {cancel}. R1/R2/R3 (RUN_S, !cancel) are mutually + -- exclusive with R5 (CANCELLING_S, cancel) on v.cancel. All guard + -- !clearAll. R1/R2/R3 are conflict_free over disjoint FIFO pairs. + ---------------------------------------------------------------------- + if clearAll = '0' then + if v.cancel = '0' then + + -- R1 recvReq: walk the SGL. Always emit one MergedMetaDataSGE and + -- one pending-SGE entry; deq U_ReqQ only on the SGL's last SGE; + -- enq {sqpn,wrID} only on the first SGE. Implicit conds: reqQ has + -- data, both always-written queues have room, and (only when + -- sge.isFirst) the pending-cntrl queue has room. + if (reqQValid = '1' and sgeMergedNotFull = '1' and pscElemNotFull = '1' and + (sge(1) = '0' or pendCntrlNotFull = '1')) then + sgeMergedWrEn <= '1'; -- enq MergedMetaDataSGE (din set above) + pscElemWrEn <= '1'; -- enq {sge,pmtu} (din set below) + if sge(1) = '1' then -- sge.isFirst + v.totalLenReg := sgeLen; + v.sgeNumReg := "0001"; + pendCntrlWrEn <= '1'; -- enq {sqpn,wrID} (din set above) + else + v.totalLenReg := slv(unsigned(r.totalLenReg) + unsigned(sgeLen)); + v.sgeNumReg := slv(unsigned(r.sgeNumReg) + 1); + end if; + if sge(0) = '1' then -- sge.isLast -> SGL complete + reqQRdEn <= '1'; -- deq U_ReqQ + v.sglIdxReg := "000"; + else + v.sglIdxReg := slv(unsigned(r.sglIdxReg) + 1); + end if; + end if; + + -- R2 issueChunkReq: pop one SGE, push an AddrChunkReq into the child, + -- stash its lkey. Implicit conds: pending-SGE has data, child can + -- accept, lkey queue has room. + if (pscElemValid = '1' and childReqPutReady = '1' and lkeyNotFull = '1') then + pscElemRdEn <= '1'; -- deq U_PendingScatterGatherElemQ + childReqPutWrEn <= '1'; -- child request.put (din set above) + lkeyWrEn <= '1'; -- enq U_PendingLKeyQ (din set above) + end if; + + -- R3 issueDmaReq: pop one AddrChunkResp, Put one DmaReadReq to + -- dmaReadSrv, tokenise SGL-level first/last. On the last CHUNK of + -- an SGE retire the lkey; on the original-last chunk retire the + -- pending-cntrl entry. Implicit conds: child has a resp, lkey and + -- pending-cntrl have heads, server ready, pending-read has room. + if (childRespQValid = '1' and lkeyValid = '1' and pendCntrlValid = '1' and + dmaReqReady = '1' and pendReadNotFull = '1') then + childRespGetRdEn <= '1'; -- get child response + dmaReqValid <= '1'; -- Put external request (dmaReqOut set above) + pendReadWrEn <= '1'; -- enq U_PendingDmaReadReqQ (din set above) + if childRespQDout(2) = '1' then -- addrChunkResp.isLast (chunk-last) + lkeyRdEn <= '1'; -- deq U_PendingLKeyQ + end if; + if isLastChunk = '1' then -- isLastDmaReqChunk (original-last) + pendCntrlRdEn <= '1'; -- deq U_PendingDmaCntrlReqQ + end if; + end if; + + else + -- cancel = '1' (CANCELLING_S / STOPPED_S). R1/R2/R3 blocked. + -- R5 setGracefulStop: latch once BOTH the response queue and the + -- pending-read queue have drained. Reads v.gracefulStop (post-port0; + -- cancel() may have re-armed it to '0'). + if (v.gracefulStop = '0' and respQValid = '0' and pendReadValid = '0') then + v.gracefulStop := '1'; + end if; + end if; + end if; + + ---------------------------------------------------------------------- + -- (4) resetAndClear (R0) port1 writes: clearAll dominates all rules and + -- forces the control bits + SGL index to their power-on values (FIFOs + -- cleared via fifoRst pins; the child clears via its own clearAllI). + ---------------------------------------------------------------------- + if clearAll = '1' then + v.cancel := '0'; + v.gracefulStop := '0'; + v.sglIdxReg := "000"; + end if; + + -- Synchronous reset (matches BSV mkReg/mkCReg reset values) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/DmaWriteCltArbiter.vhd b/ethernet/RoCEv2/rtl/DmaWriteCltArbiter.vhd new file mode 100644 index 0000000000..6246dd0a48 --- /dev/null +++ b/ethernet/RoCEv2/rtl/DmaWriteCltArbiter.vhd @@ -0,0 +1,173 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Thin STRUCTURAL specialization of mkClientArbiter — owns 0 rules, +-- 0 state registers, 0 SURF instances (matches the partition entry). The exact +-- mirror of DmaReadCltArbiter with the two finish-predicates SWAPPED. Its +-- entire contribution over a bare ClientArbiter is: +-- +-- 1. Type specialization: reqType = DmaWriteReq (419b), respType = +-- DmaWriteResp (53b). These fix the child's REQ_WIDTH_G / RESP_WIDTH_G. +-- * DmaWriteReq = metaData(DmaWriteMetaData 129) + dataStream(DataStream +-- 290) = 419. DmaWriteMetaData = initiator(4)+sqpn(24)+startAddr(64)+ +-- len(13)+psn(24) = 129. DataStream = data(256)+byteEn(32)+isFirst(1)+ +-- isLast(1) = 290. +-- * DmaWriteResp = initiator(4)+sqpn(24)+psn(24)+isRespErr(1) = 53 +-- (no dataStream — every response is single-fragment). +-- +-- 2. Resolution of the two BSV `function Bool` module parameters +-- (isReqFinished / isRespFinished — OQ-FSM-17). BSV realizes these as +-- elaboration-time functions; VHDL has no function-type ports, so this +-- wrapper (where the concrete DmaWrite type is known) computes each +-- predicate and feeds it as a 1-bit combinational input to the child. +-- DmaWrite is the OPPOSITE of DmaRead — writes carry the multi-fragment +-- *request* payload, reads carry the multi-fragment *response* payload: +-- * isDmaWriteReqLastFrag(req) = req.dataStream.isLast +-- -> child cltReqFinished(k) = LSB of client k's request slice. +-- BSV struct-pack places the first field in the MSBs, so +-- `dataStream` (last field of DmaWriteReq) sits in the low bits, +-- and `isLast` (last field of DataStream) is bit 0 (LSB) of the +-- packed DmaWriteReq = cltReqData(k*REQ_WIDTH_G). This is a +-- per-port tap (each client's own request LSB), driven through the +-- generate below. +-- * isDmaWriteRespLastFrag(resp) = True +-- -> child outRespFinished tied to '1' (every response is a +-- single-fragment burst; the child releases its preGrantIdxQ entry +-- on every dispatched response). +-- +-- All other ports connect one-to-one between this entity boundary and the +-- child U_Arb. There is no owned RegType, no FSM, no sequential process — +-- the generated VHDL is a single child instantiation plus predicate wiring. +-- All arbitration state / FIFOs live in the child ClientArbiter; see +-- out/04-vhdl/ClientArbiter.vhd. +-- +-- Sizing (DmaWriteCltArbiter.fsm.md §Elaboration facts, OQ-FSM-PERMARB-01, +-- CLOSED 2026-07-04): +-- portSz = TMul#(2, MAX_QP) = 8. dmaWriteCltVec is +-- Vector#(TMul#(2,MAX_QP), DmaWriteClt) (each QP contributes one RQ-side and +-- one SQ-side DmaWrite client). This wrapper carries a MAX_QP_G generic and +-- drives the child PORT_COUNT_G => 2*MAX_QP_G (= 8 at MAX_QP_G=4, idxW=3: +-- full 8-input arbitration tree). The child ClientArbiter is emitted generic +-- over PORT_COUNT_G and Stage-5 verified at PORT_COUNT_G=8. +-- +-- Per-client flattened buses (inherited from ClientArbiter): client k's +-- request payload slice is cltReqData((k+1)*REQ_WIDTH_G-1 downto k*REQ_WIDTH_G) +-- and likewise cltRespData with RESP_WIDTH_G, k = 0 .. 2*MAX_QP_G-1. +-- +-- Child entity instantiated: +-- * U_Arb : work.ClientArbiter (owns the arbitration FSM + all FIFOs) +-- source: out/04-vhdl/ClientArbiter.vhd +-- SURF components instantiated directly: NONE (all owned by the child). +-- +-- NOTE: emitting does not prove equivalence — simulate this entity (cocotb) +-- against the BSV behaviour before trusting it. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity DmaWriteCltArbiter is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + MAX_QP_G : positive := 4; -- BSV MAX_QP; child PORT_COUNT = 2*MAX_QP + REQ_WIDTH_G : positive := 419; -- Bits#(DmaWriteReq) (fixed by type; do not change) + RESP_WIDTH_G : positive := 53; -- Bits#(DmaWriteResp) (fixed by type; do not change) + MEMORY_TYPE_G : string := "distributed"; -- child FIFO RAM style + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- child FIFO depth = 2**ADDR + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- Per-port upstream DmaWrite client faces (dmaWriteCltVec[k], + -- k = 0 .. 2*MAX_QP_G-1; arbiter is master). Client k's payload slice is + -- ((k+1)*WIDTH-1 downto k*WIDTH) of the flattened data buses. + cltReqValid : in slv(2*MAX_QP_G-1 downto 0); -- client k DmaWriteReq available (request.get implicit cond) + cltReqData : in slv(2*MAX_QP_G*REQ_WIDTH_G-1 downto 0); -- client k DmaWriteReq payload, flattened + cltReqGet : out slv(2*MAX_QP_G-1 downto 0); -- arbiter takes client k's request (request.get fired) + cltRespValid : out slv(2*MAX_QP_G-1 downto 0); -- arbiter drives a DmaWriteResp to client k (one-hot on grant) + cltRespData : out slv(2*MAX_QP_G*RESP_WIDTH_G-1 downto 0); -- DmaWriteResp payload (broadcast; cltRespValid selects the port) + cltRespReady : in slv(2*MAX_QP_G-1 downto 0); -- client k can accept a response (response.put ready) + -- Downstream shared DmaWrite Client face (returned arbitratedClient) + outReqValid : out sl; -- arbitrated DmaWriteReq valid to DMA + outReqData : out slv(REQ_WIDTH_G-1 downto 0); -- arbitrated DmaWriteReq + outReqRd : in sl; -- DMA dequeues the request (request.get) + outRespValid : in sl; -- DMA presents a DmaWriteResp (response.put fired) + outRespData : in slv(RESP_WIDTH_G-1 downto 0); -- DmaWriteResp payload from DMA + outRespReady : out sl); -- arbiter can accept a response (response.put ready) +end entity DmaWriteCltArbiter; + +architecture rtl of DmaWriteCltArbiter is + + -- Resolved OQ-FSM-17 request predicate: isDmaWriteReqLastFrag(req) = + -- req.dataStream.isLast = bit 0 (LSB) of client k's packed DmaWriteReq. This + -- is a PER-PORT tap (unlike DmaRead, whose request predicate is constant '1'); + -- each channel's finish input is the LSB of its own request slice. + signal reqFinishedAll : slv(2*MAX_QP_G-1 downto 0); + + -- Resolved OQ-FSM-17 response predicate: isDmaWriteRespLastFrag = True, so the + -- child's downstream finish input is a constant '1' (every response is a + -- single-fragment burst). + signal respFinished : sl; + +begin + + -- isDmaWriteReqLastFrag(req) = req.dataStream.isLast = LSB of each request + -- slice. cltReqData(k*REQ_WIDTH_G) is bit 0 of client k's DmaWriteReq. + GEN_REQ_FINISHED : for k in 0 to 2*MAX_QP_G-1 generate + reqFinishedAll(k) <= cltReqData(k*REQ_WIDTH_G); + end generate GEN_REQ_FINISHED; + + -- isDmaWriteRespLastFrag(resp) = True -> every response is single-fragment. + respFinished <= '1'; + + -------------------------------------------------------------------------- + -- U_Arb : the actual DmaWrite client arbiter (ClientArbiter) — owns the FSM + -- register (shouldSaveGrantIdxReg), the arbitration tree, and all FIFOs. + -- PORT_COUNT_G => 2*MAX_QP_G (= 8 at MAX_QP_G=4). Predicate inputs resolved + -- by this wrapper; all other ports pass straight through. + -------------------------------------------------------------------------- + U_Arb : entity surf.ClientArbiter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PORT_COUNT_G => 2*MAX_QP_G, + REQ_WIDTH_G => REQ_WIDTH_G, + RESP_WIDTH_G => RESP_WIDTH_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + clk => clk, + rst => rst, + -- Per-port upstream client faces (pass-through) + cltReqValid => cltReqValid, + cltReqData => cltReqData, + cltReqFinished => reqFinishedAll, -- OQ-FSM-17: isDmaWriteReqLastFrag = req.dataStream.isLast = REQ LSB per port + cltReqGet => cltReqGet, + cltRespValid => cltRespValid, + cltRespData => cltRespData, + cltRespReady => cltRespReady, + -- Downstream shared client face (pass-through) + outReqValid => outReqValid, + outReqData => outReqData, + outReqRd => outReqRd, + outRespValid => outRespValid, + outRespData => outRespData, + outRespFinished => respFinished, -- OQ-FSM-17: isDmaWriteRespLastFrag = True (tie '1') + outRespReady => outRespReady); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd b/ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd new file mode 100644 index 0000000000..7a1a84195d --- /dev/null +++ b/ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd @@ -0,0 +1,425 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Thin DMA-write request/response shuttle with cancel / graceful-stop +-- support. Almost pure dataflow (FIFO <-> external Server passthrough) plus +-- a 2-bit control sub-FSM over {cancel, gracefulStop}: +-- RUN_S = {cancel=0} — normal forwarding (issueReq/recvResp) +-- CANCELLING_S = {cancel=1,grStop=0} — drain non-first frags, await resp +-- STOPPED_S = {cancel=1,grStop=1} — quiesced; isIdle() true +-- {cancel=0,gracefulStop=1} is unreachable. The control bits are NOT an +-- explicit state enum in the live module — they are emitted as two boolean +-- RegType fields (per fsm.md §State register). +-- +-- The entity is a Server to its caller (srvPort: request Put / response Get) +-- and a Client of an external Server dmaWriteSrv (request Put / response Get). +-- +-- BSV rules implemented: +-- resetAndClear (R0) — guard clearAllI='1' (LEVEL); clears all three FIFOs +-- via rst, forces cancel/gracefulStop to '0'. Dominates +-- every other rule (all guard !clearAllI). +-- issueReq (R1) — RUN_S (!cancel); deq reqQ -> Put dmaWriteSrv request; +-- on a first-fragment also enq a hasPendingReqQ token. +-- Blocks if a first-fragment cannot enq its token. +-- recvResp (R2) — cancel-INDEPENDENT; Get dmaWriteSrv response -> enq +-- respQ and retire one hasPendingReqQ token. This is +-- how hasPendingReqQ empties so R4 can latch. +-- gracefulStopReq(R3)— CANCELLING_S (cancel && !gracefulStop); drains only +-- NON-first fragments (deq reqQ -> Put request). On a +-- first-fragment it is a genuine no-op spin (reads +-- reqQ.first only) — nothing emitted. +-- setGracefulStop(R4)— CANCELLING_S; latches gracefulStop:='1' once +-- hasPendingReqQ is empty (no requests awaiting a resp). +-- Conflict-free with R3 — both may fire the same cycle. +-- dmaCntrl.cancel() (M0) — Action pulse cancelEn -> cancel:='1' (CReg port0, +-- same-cycle forwarded into the R1/R3/R4 guards). +-- dmaCntrl.isIdle() — Moore output = r.gracefulStop (CReg port0 read of the +-- REGISTERED value). +-- +-- CReg semantics (fsm.md §CReg semantics) — each mkCReg(2) is ONE RegType +-- field, writes applied in port order so reads see the forwarded value: +-- cancel : v:=r; port0 (cancelEn) sets '1' BEFORE the rule guards read +-- v.cancel (same-cycle cancel); port1 (clearAllI) clears '0' +-- last (dominates). +-- gracefulStop : port0 read (isIdle) uses r.gracefulStop (pre-update, Moore); +-- rule guards read v.gracefulStop (= r.gracefulStop, no port0 +-- writer); setGracefulStop sets '1', clearAllI clears '0'. +-- +-- Request drive to dmaWriteSrv (dmaReqOut/dmaReqValid) is COMBINATIONAL +-- (Mealy): dmaReqOut is reqQ.dout (FIFO front) and dmaReqValid is the R1/R3 +-- fire condition. It is a deq->put passthrough in one rule and MUST NOT be +-- registered (fsm.md §Output style). +-- +-- FIFO clear (OQ-FSM-01 carry-forward, RESOLVED in out/03-fsm/RESOLVED.md): +-- BSV reqQ.clear / respQ.clear / hasPendingReqQ.clear map to asserting each +-- Fifo's rst, OR'd with the structural reset: fifoRst = rst OR clearAllI. +-- surf.FifoSync holds logically empty for the whole asserted window +-- (level-safe; no pulse generator). Requires GEN_SYNC_FIFO_G=true, +-- RST_ASYNC_G=false, RST_POLARITY_G='1'. All three FIFOs share fifoRst so +-- the BSV single-cycle simultaneous clear is preserved. +-- +-- Open-question carry-forwards (see out/03-fsm/OPEN_QUESTIONS.md): +-- OQ-FSM-DWC-01 — Stage-1/2 records describe a stale DEAD variant +-- (PayloadConAndGen.bsv:434-508, inside /* */); this file +-- emits the LIVE body only. +-- OQ-FSM-DWC-02 — third FIFO hasPendingReqQ (omitted from mapping.json) IS +-- emitted here as U_HasPendQ. +-- OQ-FSM-DWC-03 — dmaWriteSrv / cntrlStatus.comm.isReset are external ports +-- (mapping.new_ports=[] is incomplete); enumerated below. +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_ReqQ : surf.Fifo DATA_WIDTH_G=419, FWFT, sync, block RAM +-- (DmaWriteReq; BSV mkFIFOF reqQ) +-- U_RespQ : surf.Fifo DATA_WIDTH_G=53, FWFT, sync, block RAM +-- (DmaWriteResp; BSV mkFIFOF respQ) +-- U_HasPendQ : surf.Fifo DATA_WIDTH_G=1, FWFT, sync, distributed RAM +-- (Bool token; BSV mkFIFOF hasPendingReqQ) +-- Block-RAM FWFT cold latency is 2 cycles (DOB reg); the 1-bit token queue +-- uses distributed RAM (1-cycle FWFT) so its notEmpty tracks the BSV +-- enq->notEmpty timing the R4 guard relies on — see tb-spec §8. +-- +-- DmaWriteReq bit layout (419b; BSV deriving(Bits), first-field-at-MSB): +-- [418:290] metaData : DmaWriteMetaData (129b) +-- [418:415] initiator (DmaReqSrcType, 4b) +-- [414:391] sqpn (QPN, 24b) +-- [390:327] startAddr (ADDR, 64b) +-- [326:314] len (PktLen, 13b) +-- [313:290] psn (PSN, 24b) +-- [289:0] dataStream : DataStream (290b) +-- [289:34] data (DATA, 256b) +-- [33:2] byteEn (ByteEn, 32b) +-- [1] isFirst <-- reqFirst +-- [0] isLast +-- +-- DmaWriteResp bit layout (53b; first-field-at-MSB): +-- [52:49] initiator (4b) [48:25] sqpn (24b) [24:1] psn (24b) [0] isRespErr +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity DmaWriteCntrl is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (cntrlStatus.comm.isReset; synchronous, LEVEL-asserted) + clearAllI : in sl; + -- dmaCntrl.cancel() method (Action pulse): request graceful cancel + cancelEn : in sl; + -- srvPort.request : Put#(DmaWriteReq) (caller -> entity, enq to reqQ) + reqInValid : in sl; -- caller offers a request (wr_en) + reqInData : in slv(418 downto 0); -- DmaWriteReq packed + reqInReady : out sl; -- entity can accept (reqQ.notFull) + -- srvPort.response : Get#(DmaWriteResp) (entity -> caller, deq from respQ) + respOutReady : in sl; -- caller takes a response (rd_en) + respOutValid : out sl; -- response available (respQ.notEmpty) + respOutData : out slv(52 downto 0); -- DmaWriteResp packed + -- dmaWriteSrv.request : Put#(DmaWriteReq) (entity -> external server) + dmaReqValid : out sl; -- entity offers a request (Mealy) + dmaReqOut : out slv(418 downto 0); -- DmaWriteReq packed = reqQ.dout + dmaReqReady : in sl; -- external server can accept + -- dmaWriteSrv.response : Get#(DmaWriteResp) (external server -> entity) + dmaRespValid : in sl; -- external server offers a response + dmaRespIn : in slv(52 downto 0); -- DmaWriteResp packed + dmaRespReady : out sl; -- entity takes the response (get/pop) + -- dmaCntrl.isIdle() method result (Moore, registered) + isIdle : out sl); +end entity DmaWriteCntrl; + +architecture rtl of DmaWriteCntrl is + + -- Control sub-FSM state lives in two boolean fields (mkCReg(2,False) each). + -- Documented implied states: RUN_S/CANCELLING_S/STOPPED_S (fsm.md §State). + type RegType is record + cancel : sl; -- cancelReg[2] <- mkCReg(2,False) + gracefulStop : sl; -- gracefulStopReg[2] <- mkCReg(2,False) + end record RegType; + + constant REG_INIT_C : RegType := ( + cancel => '0', + gracefulStop => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_ReqQ interface signals (DmaWriteReq, 419b) + signal reqQNotFull : sl; + signal reqQValid : sl; -- = reqQ.notEmpty (FWFT data valid) + signal reqQDout : slv(418 downto 0); + signal reqQRdEn : sl; + + -- U_RespQ interface signals (DmaWriteResp, 53b) + signal respQNotFull : sl; + signal respQValid : sl; + signal respQWrEn : sl; + signal respQDin : slv(52 downto 0); + + -- U_HasPendQ interface signals (Bool token, 1b) + signal hasPendNotFull : sl; + signal hasPendValid : sl; -- = hasPendingReqQ.notEmpty + signal hasPendWrEn : sl; + signal hasPendDin : slv(0 downto 0); + signal hasPendRdEn : sl; + + -- FIFO reset line: level = rst OR clearAllI (atomic 3-FIFO clear) + signal fifoRst : sl; + +begin + + -- FIFO reset: level-sensitive clear (OQ-FSM-01 carry-forward, RESOLVED) + fifoRst <= rst or clearAllI; + + -- srvPort boundary wiring (pass-through; not FSM-gated) + reqInReady <= reqQNotFull; -- reqQ.notFull readiness to caller + respOutValid <= respQValid; -- respQ.notEmpty to caller + + -- isIdle() method (Moore): registered gracefulStop (CReg port0 read, no port0 + -- writer => the pre-update value). Drive from r, NOT v. + isIdle <= r.gracefulStop; + + --------------------------------------------------------------------------- + -- U_ReqQ : surf.Fifo + -- Inbound DmaWriteReq queue (BSV mkFIFOF reqQ). wr side = caller's + -- srvPort.request.put (pass-through); rd side = FSM (issueReq / + -- gracefulStopReq deq). + --------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 419, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqInValid, -- pass-through (caller drives) + din => reqInData, -- pass-through (caller drives) + full => open, + not_full => reqQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => reqQRdEn, -- FSM (issueReq / gracefulStopReq) + dout => reqQDout, + valid => reqQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_RespQ : surf.Fifo + -- Outbound DmaWriteResp queue (BSV mkFIFOF respQ). wr side = FSM + -- (recvResp enq); rd side = caller's srvPort.response.get (pass-through). + --------------------------------------------------------------------------- + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 53, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => respQWrEn, -- FSM (recvResp) + din => respQDin, -- FSM (recvResp) + full => open, + not_full => respQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => respOutReady, -- pass-through (caller drives) + dout => respOutData, + valid => respQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_HasPendQ : surf.Fifo + -- 1-bit token queue (BSV mkFIFOF hasPendingReqQ). Enqueued by issueReq on + -- each first-fragment request, dequeued by recvResp per DMA-write response. + -- Only its notEmpty flag is consumed (setGracefulStop guard); dout unused. + -- Distributed RAM => 1-cycle FWFT, matching BSV enq->notEmpty timing. + --------------------------------------------------------------------------- + U_HasPendQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => hasPendWrEn, -- FSM (issueReq, first-fragment) + din => hasPendDin, -- FSM (constant "1") + full => open, + not_full => hasPendNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => hasPendRdEn, -- FSM (recvResp) + dout => open, -- value never read (only notEmpty) + valid => hasPendValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + -- Emit order (fsm.md §Conflicts/scheduling): + -- 1) cancel() port0 (cancelEn) forwarded into v.cancel + -- 2) recvResp (R2) — cancel-independent + -- 3) R1/R3/R4 evaluated off v.cancel and r.gracefulStop + SURF flags + -- 4) setGracefulStop / resetAndClear port1 writes + --------------------------------------------------------------------------- + comb : process (r, rst, clearAllI, cancelEn, reqQValid, reqQDout, dmaReqReady, + dmaRespValid, dmaRespIn, respQNotFull, hasPendValid, + hasPendNotFull) is + variable v : RegType; + variable reqFirst : sl; + begin + v := r; + + -- default Mealy outputs / SURF drives (deasserted) + reqQRdEn <= '0'; + respQWrEn <= '0'; + respQDin <= (others => '0'); + hasPendWrEn <= '0'; + hasPendDin <= (others => '0'); + hasPendRdEn <= '0'; + dmaReqValid <= '0'; + dmaReqOut <= reqQDout; -- Mealy front: reqQ.dout, gated by dmaReqValid + dmaRespReady <= '0'; + + -- reqQ.first.dataStream.isFirst (DmaWriteReq bit 1) + reqFirst := reqQDout(1); + + ---------------------------------------------------------------------- + -- (1) CReg cancel port0: dmaCntrl.cancel() method. Forwarded into the + -- R1/R3/R4 guards this same cycle (same-cycle cancel). + ---------------------------------------------------------------------- + if cancelEn = '1' then + v.cancel := '1'; + end if; + + ---------------------------------------------------------------------- + -- (2) recvResp (R2): cancel-INDEPENDENT. Get dmaWriteSrv response -> + -- enq respQ and retire one hasPendingReqQ token. + ---------------------------------------------------------------------- + if (clearAllI = '0' and dmaRespValid = '1' and respQNotFull = '1' and + hasPendValid = '1') then + dmaRespReady <= '1'; -- get/pop external server response + respQWrEn <= '1'; -- enq respQ + respQDin <= dmaRespIn; + hasPendRdEn <= '1'; -- deq hasPendingReqQ token + end if; + + ---------------------------------------------------------------------- + -- (3) Forwarding path on {cancel, gracefulStop} (all guard !clearAllI). + -- R1 (RUN_S, !cancel) vs R3/R4 (CANCELLING_S, cancel) are mutually + -- exclusive on v.cancel. + ---------------------------------------------------------------------- + if clearAllI = '0' then + if v.cancel = '0' then + -- R1 issueReq: deq reqQ -> Put request; first-fragment also enqs a + -- hasPendingReqQ token (rule blocks if that token cannot enq). + if (reqQValid = '1' and dmaReqReady = '1' and + (reqFirst = '0' or hasPendNotFull = '1')) then + reqQRdEn <= '1'; -- deq reqQ + dmaReqValid <= '1'; -- Put (dmaReqOut already = reqQDout) + if reqFirst = '1' then + hasPendWrEn <= '1'; + hasPendDin <= "1"; -- enq token + end if; + end if; + + else + -- cancel = '1' + if r.gracefulStop = '0' then + -- R3 gracefulStopReq: drain only NON-first fragments. A first + -- fragment is a no-op spin (reads reqQ.first only) -> emit + -- nothing; hold until R4 latches gracefulStop. + if (reqQValid = '1' and reqFirst = '0' and dmaReqReady = '1') then + reqQRdEn <= '1'; -- deq reqQ + dmaReqValid <= '1'; -- Put (dmaReqOut already = reqQDout) + end if; + + -- R4 setGracefulStop: latch once hasPendingReqQ is empty. + -- Conflict-free with R3 (may fire the same cycle). + if hasPendValid = '0' then + v.gracefulStop := '1'; + end if; + end if; + end if; + end if; + + ---------------------------------------------------------------------- + -- (4) resetAndClear (R0) port1 writes: clearAllI dominates all rules and + -- forces both control bits to '0' (FIFOs cleared via fifoRst pins). + ---------------------------------------------------------------------- + if clearAllI = '1' then + v.cancel := '0'; + v.gracefulStop := '0'; + end if; + + -- Synchronous reset (matches BSV mkCReg(_,False) reset) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd b/ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd new file mode 100644 index 0000000000..7045374151 --- /dev/null +++ b/ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd @@ -0,0 +1,334 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- DESIGN NOTE - STATELESS WRAPPER (OQ-FSM-DRAC-02) +-- mkDupReadAtomicCache owns NO mkReg/mkRegU/mkCReg and no counter; its only +-- sequential control is the single rule postProcessDupReadResp, which is a +-- one-stage combinational stream-join registered only through the dupReadRespQ +-- FIFO. There is therefore no RegType / REG_INIT_C / r-rin pair and no seq +-- process for this entity: all state lives inside the two surf.Fifo instances +-- and the two CacheFifo children. The two-process FSM template does not apply +-- to a stateless join. (mapping.json wrongly records rules=[], surf_instances=[]; +-- the .fsm.md is authoritative - OQ-FSM-DRAC-02.) +-- +-- STRUCTURE +-- * U_ReadCacheQ : CacheFifoRead (readCacheQ, ReadCacheItem 176 b) - takes pmtu +-- * U_AtomicCacheQ : CacheFifoAtomic (atomicCacheQ, AtomicCacheItem 317 b) +-- * U_DupReadReqQ : surf.Fifo (dupReadReqQ, ReadCacheItem 176 b, FWFT) +-- * U_DupReadRespQ : surf.Fifo (dupReadRespQ, Maybe#(Tuple3) 242 b, FWFT) +-- +-- WIDTHS (traced; see CacheFifo.vhd header / RESOLVED.md OQ-FSM-CF-02/03) +-- ReadCacheItem = startPSN(24)+endPSN(24)+RETH(128) = 176 +-- RETH = va(64)+rkey(32)+dlen(32) ; va = reth[127:64] +-- AtomicCacheItem = 317 +-- readCacheQ searchResp = Maybe#(ReadCacheItem) = 1+176 = 177 (tag = bit 176) +-- atomicCacheQ searchResp = Maybe#(AtomicCacheItem) = 1+317 = 318 (tag = bit 317) +-- Tuple3(ReadCacheItem, ADDR, DupReadReqStartState) = 176+64+1 = 241 +-- dupReadRespQ word = Maybe#(Tuple3) = 1+241 = 242 (tag = bit 241) +-- DupReadReqStartState : FROM_FIRST=0, FROM_MIDDLE=1 (1 bit) +-- PMTU enum (3 b) encoding: 256="001" 512="010" 1024="011" 2048="100" 4096="101" +-- (matches CacheFifoRead.f_secondRead / DataTypes.bsv:407-413) +-- +-- ATOMICITY (OQ-FSM-DRAC-04) +-- searchReadReq fires TWO enqueues atomically: U_ReadCacheQ.searchReq AND +-- U_DupReadReqQ.enq. Both are gated on the AND of (searchReq-ready AND +-- dupReadReqQ.not_full) so neither commits without the other; otherwise the +-- rule's 1:1 join (child searchResp <-> dupReadReqQ.first) would desync. +-- +-- CLEAR (OQ-FSM-DRAC-03) +-- clear() asserts cacheIfc.clear on BOTH children only; it does NOT flush +-- dupReadReqQ / dupReadRespQ. Faithfully reproduced: clearEn is wired ONLY to +-- the children's clearEn; the two own FIFOs see the global rst alone. +-- +-- MEALY NOTE +-- readResp is computed combinationally (compareDupReadAddr / getVerifiedDupReadAddr +-- are pure) and registered only by the U_DupReadRespQ enqueue. searchAtomicResp +-- is a pure combinational passthrough of U_AtomicCacheQ's search response. +-- +-- VERIFY: this entity has not been simulated. Run Stage 5 (cocotb/VHDL TB) before +-- trusting it. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity DupReadAtomicCache is + generic ( + TPD_G : time := 1 ns; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; -- children + own FIFO depth = 2**N + MEM_TYPE_G : string := "block"); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous + pmtu : in slv(2 downto 0); -- PMTU enum (feeds read-cache compare) + -- insertRead method : push ReadCacheItem into readCacheQ + insertReadEn : in sl; + insertReadData : in slv(175 downto 0); + insertReadReady : out sl; -- = U_ReadCacheQ.pushReady + -- searchReadReq method : enq into readCacheQ.searchReq AND dupReadReqQ (atomic) + searchReadReqEn : in sl; + searchReadReqData : in slv(175 downto 0); + searchReadReqReady : out sl; -- = readCacheQ.searchReqReady AND dupReadReqQ.not_full + -- searchReadResp method : Maybe#(Tuple3(ReadCacheItem, ADDR, StartState)) + searchReadRespValid : out sl; + searchReadRespData : out slv(241 downto 0); + searchReadRespRdEn : in sl; + -- insertAtomic method : push AtomicCacheItem into atomicCacheQ + insertAtomicEn : in sl; + insertAtomicData : in slv(316 downto 0); + insertAtomicReady : out sl; -- = U_AtomicCacheQ.pushReady + -- searchAtomicReq method : enq into atomicCacheQ.searchReq + searchAtomicReqEn : in sl; + searchAtomicReqData : in slv(316 downto 0); + searchAtomicReqReady : out sl; -- = U_AtomicCacheQ.searchReqReady + -- searchAtomicResp method : Maybe#(AtomicCacheItem) (direct passthrough) + searchAtomicRespValid : out sl; + searchAtomicRespData : out slv(317 downto 0); + searchAtomicRespRdEn : in sl; + -- clear method : clears the two children's caches only (NOT dup*Q) + clearEn : in sl); +end entity DupReadAtomicCache; + +architecture rtl of DupReadAtomicCache is + + constant READ_ITEM_W_C : positive := 176; -- ReadCacheItem + constant ATOMIC_ITEM_W_C : positive := 317; -- AtomicCacheItem + constant READ_SEARCH_RESP_W_C : positive := 177; -- Maybe#(ReadCacheItem) (tag = bit 176) + constant READ_RESP_W_C : positive := 242; -- Maybe#(Tuple3) (tag = bit 241) + constant SR_TAG_C : natural := 176; -- Maybe-valid tag index in readCacheQ searchResp + + -- compareDupReadAddr (DupReadAtomicCache.bsv:134-188) : compares the upper bits + -- (above the PMTU shift) of the LOW 32-bit half of va. dupVaLow/origVaLow are + -- reth.va[31:0]. Returns True when dAddrLowHalf[31:s] = oAddrLowHalf[31:s]. + function f_cmpDupReadAddr (dupVaLow, origVaLow : slv(31 downto 0); + pmtuI : slv(2 downto 0)) return sl is + variable s : integer range 8 to 12; + begin + case pmtuI is + when "001" => s := 8; -- IBV_MTU_256 : 8 = log2(256) + when "010" => s := 9; -- IBV_MTU_512 : 9 = log2(512) + when "011" => s := 10; -- IBV_MTU_1024 : 10 = log2(1024) + when "100" => s := 11; -- IBV_MTU_2048 : 11 = log2(2048) + when "101" => s := 12; -- IBV_MTU_4096 : 12 = log2(4096) + when others => s := 8; + end case; + return toSl(dupVaLow(31 downto s) = origVaLow(31 downto s)); + end function; + + -- read-cache child (readCacheQ) + signal readPushReady : sl; + signal readSearchReqEn : sl; + signal readSearchReqReady : sl; + signal readSearchRespValid : sl; + signal readSearchRespData : slv(READ_SEARCH_RESP_W_C-1 downto 0); + signal readSearchRespRdEn : sl; + + -- atomic-cache child (atomicCacheQ) + signal atomicPushReady : sl; + signal atomicSearchReqReady : sl; + signal atomicSearchRespValid : sl; + signal atomicSearchRespData : slv(ATOMIC_ITEM_W_C downto 0); -- 318 b Maybe + + -- dupReadReqQ (own FIFO) + signal dupReqWrEn : sl; + signal dupReqNotFull : sl; + signal dupReqRdEn : sl; + signal dupReqDout : slv(READ_ITEM_W_C-1 downto 0); + signal dupReqValid : sl; + + -- dupReadRespQ (own FIFO) + signal dupRespWrEn : sl; + signal dupRespDin : slv(READ_RESP_W_C-1 downto 0); + signal dupRespNotFull : sl; + signal dupRespDout : slv(READ_RESP_W_C-1 downto 0); + signal dupRespValid : sl; + + -- atomic dual-enqueue gate for searchReadReq + signal searchReqCombReady : sl; + signal searchReqDoEnq : sl; + +begin + + ---------------------------------------------------------------------------- + -- Method-level wiring (combinational handshakes, no state) + ---------------------------------------------------------------------------- + -- insertRead : straight push (readiness exposed; wr_en ungated like CacheFifo) + insertReadReady <= readPushReady; + + -- searchReadReq : TWO atomic enqueues, gated on the AND of both readinesses + searchReqCombReady <= readSearchReqReady and dupReqNotFull; + searchReqDoEnq <= searchReadReqEn and searchReqCombReady; + searchReadReqReady <= searchReqCombReady; + readSearchReqEn <= searchReqDoEnq; -- to U_ReadCacheQ.searchReq + dupReqWrEn <= searchReqDoEnq; -- to U_DupReadReqQ.enq + + -- searchReadResp : FWFT output of dupReadRespQ + searchReadRespValid <= dupRespValid; + searchReadRespData <= dupRespDout; + -- (dupReadRespQ rd_en driven directly from searchReadRespRdEn in the port map) + + -- insertAtomic : straight push + insertAtomicReady <= atomicPushReady; + + -- searchAtomicReq : single enqueue + searchAtomicReqReady <= atomicSearchReqReady; + + -- searchAtomicResp : pure passthrough of atomicCacheQ search response + searchAtomicRespValid <= atomicSearchRespValid; + searchAtomicRespData <= atomicSearchRespData; + -- (U_AtomicCacheQ.searchRespRdEn driven directly from searchAtomicRespRdEn) + + ---------------------------------------------------------------------------- + -- Child entities (CacheFifo specialisations, NOT SURF, NOT state) + ---------------------------------------------------------------------------- + U_ReadCacheQ : entity surf.CacheFifoRead + generic map ( + TPD_G => TPD_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + pmtu => pmtu, + pushEn => insertReadEn, + pushData => insertReadData, + pushReady => readPushReady, + clearEn => clearEn, -- DRAC-03: only children are cleared + searchReqEn => readSearchReqEn, + searchReqData => searchReadReqData, + searchReqReady => readSearchReqReady, + searchRespValid => readSearchRespValid, + searchRespData => readSearchRespData, + searchRespRdEn => readSearchRespRdEn); + + U_AtomicCacheQ : entity surf.CacheFifoAtomic + generic map ( + TPD_G => TPD_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + pushEn => insertAtomicEn, + pushData => insertAtomicData, + pushReady => atomicPushReady, + clearEn => clearEn, -- DRAC-03: only children are cleared + searchReqEn => searchAtomicReqEn, + searchReqData => searchAtomicReqData, + searchReqReady => atomicSearchReqReady, + searchRespValid => atomicSearchRespValid, + searchRespData => atomicSearchRespData, + searchRespRdEn => searchAtomicRespRdEn); -- passthrough get + + ---------------------------------------------------------------------------- + -- Own FIFOs (surf.Fifo ; FWFT sync ; NOT flushed by clear() - DRAC-03) + ---------------------------------------------------------------------------- + U_DupReadReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => READ_ITEM_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => rst, -- global rst only (not clearEn) + wr_clk => clk, + wr_en => dupReqWrEn, + din => searchReadReqData, -- same item enqueued to readCacheQ.searchReq + not_full => dupReqNotFull, + rd_clk => clk, + rd_en => dupReqRdEn, + dout => dupReqDout, + valid => dupReqValid); + + U_DupReadRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => READ_RESP_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => rst, -- global rst only (not clearEn) + wr_clk => clk, + wr_en => dupRespWrEn, + din => dupRespDin, + not_full => dupRespNotFull, + rd_clk => clk, + rd_en => searchReadRespRdEn, -- searchReadResp deq + dout => dupRespDout, + valid => dupRespValid); + + ---------------------------------------------------------------------------- + -- rule postProcessDupReadResp : combinational 1:1 stream-join + -- guard : dupReadReqQ.notEmpty AND readCacheQ.searchResp valid AND + -- dupReadRespQ.not_full + -- on fire (atomic) : deq dupReadReqQ ; get readCacheQ.searchResp ; + -- enq readResp into dupReadRespQ + ---------------------------------------------------------------------------- + join_comb : process (dupReqValid, dupReqDout, readSearchRespValid, + readSearchRespData, dupRespNotFull, pmtu) is + variable fire : sl; + variable searchValid : sl; + variable orig : slv(READ_ITEM_W_C-1 downto 0); + variable matchV : sl; + variable vaddr : slv(63 downto 0); + variable startState : sl; + variable readResp : slv(READ_RESP_W_C-1 downto 0); + begin + -- defaults : no enqueue / dequeue + dupReqRdEn <= '0'; + readSearchRespRdEn <= '0'; + dupRespWrEn <= '0'; + dupRespDin <= (others => '0'); + + fire := dupReqValid and readSearchRespValid and dupRespNotFull; + + -- compute readResp (Mealy combinational; registered only by the enq below) + searchValid := readSearchRespData(SR_TAG_C); -- Maybe tag (MSB) + orig := readSearchRespData(READ_ITEM_W_C-1 downto 0); + + -- compareDupReadAddr(pmtu, dupReth, origReth) : low-half va, bits [95:64] + matchV := f_cmpDupReadAddr(dupReqDout(95 downto 64), orig(95 downto 64), pmtu); + + -- getVerifiedDupReadAddr = { origReth.va[63:32] , dupReth.va[31:0] } + -- origReth.va[63:32] = orig[127:96] ; dupReth.va[31:0] = dupReqDout[95:64] + vaddr := orig(127 downto 96) & dupReqDout(95 downto 64); + + -- match -> FROM_FIRST(0) ; mismatch -> FROM_MIDDLE(1) + startState := not matchV; + + if (searchValid = '1') then + -- Maybe Valid : tag=1, Tuple3(origReadCacheItem, vaddr, startState) + readResp := '1' & orig & vaddr & startState; + else + readResp := (others => '0'); -- tagged Invalid + end if; + + if (fire = '1') then + dupReqRdEn <= '1'; -- deq dupReadReqQ + readSearchRespRdEn <= '1'; -- get readCacheQ.searchResp + dupRespWrEn <= '1'; -- enq dupReadRespQ + dupRespDin <= readResp; + end if; + end process join_comb; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperRecv.vhd b/ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperRecv.vhd deleted file mode 100755 index 499b192116..0000000000 --- a/ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperRecv.vhd +++ /dev/null @@ -1,127 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Wrapper on mkCrcRawAxiStreamCustomRecv.v -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiStreamPkg.all; - -entity EthMacCrcAxiStreamWrapperRecv is - generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'); -- '1' for active HIGH reset, '0' for active LOW reset - port ( - -- Clock and Reset - ethClk : in sl; - ethRst : in sl; - -- Slave ports - sAxisMaster : in AxiStreamMasterType; - sAxisSlave : out AxiStreamSlaveType; - -- Master ports - mAxisMaster : out AxiStreamMasterType; - mAxisSlave : in AxiStreamSlaveType); -end EthMacCrcAxiStreamWrapperRecv; - -architecture rtl of EthMacCrcAxiStreamWrapperRecv is - - component mkCrcRawAxiStreamCustomRecv - port ( - CLK : in std_logic; - RST_N : in std_logic; - s_axis_tvalid : in std_logic; - s_axis_tdata : in std_logic_vector(255 downto 0); - s_axis_tkeep : in std_logic_vector(31 downto 0); - s_axis_tlast : in std_logic; - s_axis_tuser : in std_logic; - s_axis_tready : out std_logic; - m_crc_stream_data : out std_logic_vector(31 downto 0); - m_crc_stream_valid : out std_logic; - m_crc_stream_ready : in std_logic); - end component; - - -- BlueRdma - signal blueRstN : sl; - signal bluetValidSlave : sl; - signal bluetDataSlave : slv(255 downto 0); - signal bluetKeepSlave : slv(31 downto 0); - signal bluetUserSlave : sl; - signal bluetLastSlave : sl; - signal bluetReadySlave : sl; - signal bluetDataMaster : slv(31 downto 0); - signal bluetValidMaster : sl; - signal bluetReadyMaster : sl; - -begin - - blueRstN <= not ethRst when (RST_POLARITY_G = '1') else ethRst; - - ----------------------------------------------------------------------------- - -- IP integrator - ----------------------------------------------------------------------------- - MasterAxiStreamIpIntegrator_1 : entity surf.MasterAxiStreamIpIntegrator - generic map ( - TUSER_WIDTH => 1, - TDATA_NUM_BYTES => 32) - port map ( - M_AXIS_ACLK => ethClk, - M_AXIS_ARESETN => blueRstN, - M_AXIS_TVALID => bluetValidSlave, - M_AXIS_TDATA => bluetDataSlave, - M_AXIS_TKEEP => bluetKeepSlave, - M_AXIS_TLAST => bluetLastSlave, - M_AXIS_TUSER(0) => bluetUserSlave, - M_AXIS_TREADY => bluetReadySlave, - axisClk => open, - axisRst => open, - axisMaster => sAxisMaster, - axisSlave => sAxisSlave); - - SlaveAxiStreamIpIntegrator_1 : entity surf.SlaveAxiStreamIpIntegrator - generic map ( - HAS_TLAST => 1, - HAS_TKEEP => 1, - TDATA_NUM_BYTES => 4) - port map ( - S_AXIS_ACLK => ethClk, - S_AXIS_ARESETN => blueRstN, - S_AXIS_TVALID => bluetValidMaster, - S_AXIS_TDATA => bluetDataMaster, - S_AXIS_TKEEP => x"F", - S_AXIS_TLAST => '1', - S_AXIS_TREADY => bluetReadyMaster, - axisClk => open, - axisRst => open, - axisMaster => mAxisMaster, - axisSlave => mAxisSlave); - - ----------------------------------------------------------------------------- - -- CRC calculator - ----------------------------------------------------------------------------- - mkCrcRawAxiStreamCustomRecv_1 : mkCrcRawAxiStreamCustomRecv - port map ( - CLK => ethClk, - RST_N => blueRstN, - s_axis_tvalid => bluetValidSlave, - s_axis_tdata => bluetDataSlave, - s_axis_tkeep => bluetKeepSlave, - s_axis_tlast => bluetLastSlave, - s_axis_tuser => bluetUserSlave, - s_axis_tready => bluetReadySlave, - m_crc_stream_data => bluetDataMaster, - m_crc_stream_valid => bluetValidMaster, - m_crc_stream_ready => bluetReadyMaster); - -end rtl; diff --git a/ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperSend.vhd b/ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperSend.vhd deleted file mode 100755 index 475f9db8d7..0000000000 --- a/ethernet/RoCEv2/rtl/EthMacCrcAxiStreamWrapperSend.vhd +++ /dev/null @@ -1,127 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Wrapper on mkCrcRawAxiStreamCustomSend.v -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiStreamPkg.all; - -entity EthMacCrcAxiStreamWrapperSend is - generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'); -- '1' for active HIGH reset, '0' for active LOW reset - port ( - -- Clock and Reset - ethClk : in sl; - ethRst : in sl; - -- Slave ports - sAxisMaster : in AxiStreamMasterType; - sAxisSlave : out AxiStreamSlaveType; - -- Master ports - mAxisMaster : out AxiStreamMasterType; - mAxisSlave : in AxiStreamSlaveType); -end EthMacCrcAxiStreamWrapperSend; - -architecture rtl of EthMacCrcAxiStreamWrapperSend is - - component mkCrcRawAxiStreamCustomSend - port ( - CLK : in std_logic; - RST_N : in std_logic; - s_axis_tvalid : in std_logic; - s_axis_tdata : in std_logic_vector(255 downto 0); - s_axis_tkeep : in std_logic_vector(31 downto 0); - s_axis_tlast : in std_logic; - s_axis_tuser : in std_logic; - s_axis_tready : out std_logic; - m_crc_stream_data : out std_logic_vector(31 downto 0); - m_crc_stream_valid : out std_logic; - m_crc_stream_ready : in std_logic); - end component; - - -- BlueRdma - signal blueRstN : sl; - signal bluetValidSlave : sl; - signal bluetDataSlave : slv(255 downto 0); - signal bluetKeepSlave : slv(31 downto 0); - signal bluetUserSlave : sl; - signal bluetLastSlave : sl; - signal bluetReadySlave : sl; - signal bluetDataMaster : slv(31 downto 0); - signal bluetValidMaster : sl; - signal bluetReadyMaster : sl; - -begin - - blueRstN <= not ethRst when (RST_POLARITY_G = '1') else ethRst; - - ----------------------------------------------------------------------------- - -- IP integrator - ----------------------------------------------------------------------------- - MasterAxiStreamIpIntegrator_1 : entity surf.MasterAxiStreamIpIntegrator - generic map ( - TUSER_WIDTH => 1, - TDATA_NUM_BYTES => 32) - port map ( - M_AXIS_ACLK => ethClk, - M_AXIS_ARESETN => blueRstN, - M_AXIS_TVALID => bluetValidSlave, - M_AXIS_TDATA => bluetDataSlave, - M_AXIS_TKEEP => bluetKeepSlave, - M_AXIS_TLAST => bluetLastSlave, - M_AXIS_TUSER(0) => bluetUserSlave, - M_AXIS_TREADY => bluetReadySlave, - axisClk => open, - axisRst => open, - axisMaster => sAxisMaster, - axisSlave => sAxisSlave); - - SlaveAxiStreamIpIntegrator_1 : entity surf.SlaveAxiStreamIpIntegrator - generic map ( - HAS_TLAST => 1, - HAS_TKEEP => 1, - TDATA_NUM_BYTES => 4) - port map ( - S_AXIS_ACLK => ethClk, - S_AXIS_ARESETN => blueRstN, - S_AXIS_TVALID => bluetValidMaster, - S_AXIS_TDATA => bluetDataMaster, - S_AXIS_TKEEP => x"F", - S_AXIS_TLAST => '1', - S_AXIS_TREADY => bluetReadyMaster, - axisClk => open, - axisRst => open, - axisMaster => mAxisMaster, - axisSlave => mAxisSlave); - - ----------------------------------------------------------------------------- - -- CRC calculator - ----------------------------------------------------------------------------- - EthMacCrcAxiStreamWrapperSend_1 : mkCrcRawAxiStreamCustomSend - port map ( - CLK => ethClk, - RST_N => blueRstN, - s_axis_tvalid => bluetValidSlave, - s_axis_tdata => bluetDataSlave, - s_axis_tkeep => bluetKeepSlave, - s_axis_tlast => bluetLastSlave, - s_axis_tuser => bluetUserSlave, - s_axis_tready => bluetReadySlave, - m_crc_stream_data => bluetDataMaster, - m_crc_stream_valid => bluetValidMaster, - m_crc_stream_ready => bluetReadyMaster); - -end rtl; diff --git a/ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd b/ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd deleted file mode 100755 index 9b1897bcad..0000000000 --- a/ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd +++ /dev/null @@ -1,142 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Prepares the AXI stream for the ICRC insertion -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library surf; -use surf.AxiStreamPkg.all; -use surf.StdRtlPkg.all; -use surf.EthMacPkg.all; - -entity EthMacPrepareForICrc is - generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset - RST_ASYNC_G : boolean := false; - PIPE_STAGES_G : natural := 0); - port ( - -- Clock and Reset - ethClk : in sl; - ethRst : in sl; - -- Slave ports - sAxisMaster : in AxiStreamMasterType; - sAxisSlave : out AxiStreamSlaveType; - -- Master ports - mAxisMaster : out AxiStreamMasterType; - mAxisSlave : in AxiStreamSlaveType); -end entity EthMacPrepareForICrc; - -architecture rtl of EthMacPrepareForICrc is - - type RegType is record - cnt : natural range 0 to 3; - obMaster : AxiStreamMasterType; - ibSlave : AxiStreamSlaveType; - end record RegType; - - constant REG_INIT_C : RegType := ( - cnt => 0, - obMaster => AXI_STREAM_MASTER_INIT_C, - ibSlave => AXI_STREAM_SLAVE_INIT_C); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - -begin - - comb : process (ethRst, mAxisSlave, r, sAxisMaster) is - variable v : RegType; - begin - -- Latch the current value - v := r; - - -- AXI Stream flow control - v.ibSlave.tReady := '0'; - if mAxisSlave.tReady = '1' then - v.obMaster.tValid := '0'; - end if; - - -- Check for moving data condition - if (sAxisMaster.tValid = '1') and (v.obMaster.tValid = '0') then - - -- Accept the transaction - v.ibSlave.tReady := '1'; - - -- Move the data - v.obMaster := sAxisMaster; - - -- Case on the counter - case r.cnt is - when 0 => - -- reset output data - v.obMaster.tData(v.obMaster.tData'length-1 downto 80) := (others => '0'); - -- ignore MAC header - v.obMaster.tData(63 downto 0) := (others => '1'); - -- Get Version and Header length - v.obMaster.tData(71 downto 64) := sAxisMaster.tData(119 downto 112); - -- ignore Type of Service - v.obMaster.tData(79 downto 72) := (others => '1'); - -- adjust tKeep - v.obMaster.tKeep(v.obMaster.tKeep'length-1 downto 10) := (others => '0'); - v.obMaster.tKeep(9 downto 0) := (others => '1'); - when 1 => - -- ignore TTL - v.obMaster.tData(55 downto 48) := (others => '1'); - -- ignore ip checksum - v.obMaster.tData(79 downto 64) := (others => '1'); - when 2 => - -- ignore prot checksum - v.obMaster.tData(79 downto 64) := (others => '1'); - -- ignore BTH fecn, becn and resv6 - v.obMaster.tData(119 downto 112) := (others => '1'); - when others => - null; - end case; - - -- Increment the counter - if sAxisMaster.tLast = '1' then - v.cnt := 0; - elsif (r.cnt /= 3) then - v.cnt := v.cnt + 1; - end if; - - end if; - - -- Outputs - sAxisSlave <= v.ibSlave; - mAxisMaster <= r.obMaster; - - -- Reset - if (RST_ASYNC_G = false and ethRst = RST_POLARITY_G) then - v := REG_INIT_C; - end if; - - -- Register the variable for next clock cycle - rin <= v; - - end process comb; - - seq : process (ethClk, ethRst) is - begin - if (RST_ASYNC_G and ethRst = RST_POLARITY_G) then - r <= REG_INIT_C after TPD_G; - elsif rising_edge(ethClk) then - r <= rin after TPD_G; - end if; - end process seq; - -end rtl; diff --git a/ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd b/ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd deleted file mode 100755 index d11655aa53..0000000000 --- a/ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd +++ /dev/null @@ -1,130 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Checks the RX RoCEv2 iCRC value -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_misc.all; - -library surf; -use surf.AxiStreamPkg.all; -use surf.StdRtlPkg.all; -use surf.EthMacPkg.all; - -entity EthMacRxCheckICrc is - generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset - RST_ASYNC_G : boolean := false); - port ( - -- Clock and Reset - ethClk : in sl; - ethRst : in sl; - -- Slave ports - sAxisMaster : in AxiStreamMasterType; - sAxisSlave : out AxiStreamSlaveType; - sAxisCrcCheckMaster : in AxiStreamMasterType; - sAxisCrcCheckSlave : out AxiStreamSlaveType; - -- Master ports - mAxisMaster : out AxiStreamMasterType; - mAxisSlave : in AxiStreamSlaveType); -end entity EthMacRxCheckICrc; - -architecture rtl of EthMacRxCheckICrc is - - type RegType is record - gotCrc : sl; - ibSlave : AxiStreamSlaveType; - ibCrcSlave : AxiStreamSlaveType; - obMaster : AxiStreamMasterType; - end record RegType; - - constant REG_INIT_C : RegType := ( - gotCrc => '0', - ibSlave => AXI_STREAM_SLAVE_INIT_C, - ibCrcSlave => AXI_STREAM_SLAVE_INIT_C, - obMaster => axiStreamMasterInit(EMAC_AXIS_CONFIG_C)); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - -begin - - comb : process (ethRst, mAxisSlave, r, sAxisCrcCheckMaster, sAxisMaster) is - variable v : RegType; - variable ibM : AxiStreamMasterType; - variable ibCrcM : AxiStreamMasterType; - begin - -- Latch the current value - v := r; - - -- AXI Stream flow control - v.ibSlave.tReady := '0'; - v.ibCrcSlave.tReady := '0'; - if (mAxisSlave.tReady = '1') then - v.obMaster.tValid := '0'; - end if; - - -- Check if we are ready to move data - if v.obMaster.tValid = '0' then - -- Get inbound data - ibM := sAxisMaster; - ibCrcM := sAxisCrcCheckMaster; - - if ibM.tValid = '1' and (ibCrcM.tValid = '1' or r.gotCrc = '1') then - -- Enable tReady on main - v.ibSlave.tReady := '1'; - -- Enable tReady on CRC only for a single transaction - if r.gotCrc = '0' then - v.ibCrcSlave.tReady := '1'; - v.gotCrc := '1'; - end if; - if ibM.tLast = '1' then - v.gotCrc := '0'; - end if; - v.obMaster := ibM; - if or_reduce(ibCrcM.tData(31 downto 0)) = '0' then - v.obMaster.tUser(2) := '0'; - else - v.obMaster.tUser(2) := '1'; - end if; - end if; - end if; - - -- Outputs - sAxisSlave <= v.ibSlave; - sAxisCrcCheckSlave <= v.ibCrcSlave; - mAxisMaster <= r.obMaster; - - -- Reset - if (RST_ASYNC_G = false and ethRst = RST_POLARITY_G) then - v := REG_INIT_C; - end if; - - -- Register the variable for next clock cycle - rin <= v; - - end process comb; - - seq : process (ethClk, ethRst) is - begin - if (RST_ASYNC_G and ethRst = RST_POLARITY_G) then - r <= REG_INIT_C after TPD_G; - elsif rising_edge(ethClk) then - r <= rin after TPD_G; - end if; - end process seq; - -end rtl; diff --git a/ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd b/ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd deleted file mode 100755 index b42fbe291a..0000000000 --- a/ethernet/RoCEv2/rtl/EthMacRxRoCEv2.vhd +++ /dev/null @@ -1,273 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: RoCEv2 Protocol Wrapper for RX path -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library surf; -use surf.AxiStreamPkg.all; -use surf.StdRtlPkg.all; -use surf.EthMacPkg.all; - -entity EthMacRxRoCEv2 is - generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'); -- '1' for active HIGH reset, '0' for active LOW reset - port ( - -- Clock and Reset - ethClk : in sl; - ethRst : in sl; - -- Checksum Interface - obCsumMaster : in AxiStreamMasterType; - -- Bypass Interface - ibBypassMaster : out AxiStreamMasterType); -end EthMacRxRoCEv2; - -architecture mapping of EthMacRxRoCEv2 is - - constant ROCE_CRC32_AXI_CONFIG_C : AxiStreamConfigType := ( - TSTRB_EN_C => false, - TDATA_BYTES_C => 32, - TDEST_BITS_C => 8, - TID_BITS_C => 0, - TKEEP_MODE_C => TKEEP_COMP_C, - TUSER_BITS_C => 4, - TUSER_MODE_C => TUSER_FIRST_LAST_C); - - signal csumDmMasters : AxiStreamMasterArray(1 downto 0); - signal csumDmSlaves : AxiStreamSlaveArray(1 downto 0); - - signal csumMastersRoCE : AxiStreamMasterArray(1 downto 0); - signal csumSlavesRoCE : AxiStreamSlaveArray(1 downto 0); - - signal csumMasterDly : AxiStreamMasterType; - signal csumSlaveDly : AxiStreamSlaveType; - - signal axisMasterNoTrail : AxiStreamMasterType; - signal axisSlaveNoTrail : AxiStreamSlaveType; - - signal csumiCrcMaster : AxiStreamMasterType; - signal csumiCrcSlave : AxiStreamSlaveType; - - signal readyForiCrcMaster : AxiStreamMasterType; - signal readyForiCrcSlave : AxiStreamSlaveType; - - signal crcStreamMaster : AxiStreamMasterType; - signal crcStreamSlave : AxiStreamSlaveType; - - signal roceCheckedMaster : AxiStreamMasterType; - signal roceCheckedSlave : AxiStreamSlaveType; - - signal roceMaster : AxiStreamMasterType; - signal roceCtrl : AxiStreamCtrlType; - - signal roceMasters : AxiStreamMasterArray(1 downto 0); - signal roceSlaves : AxiStreamSlaveArray(1 downto 0); - -begin - - ---------------------------------------------------------------------------- - -- RoCE iCRC check - ---------------------------------------------------------------------------- - U_DeMux : entity surf.AxiStreamDeMux - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - NUM_MASTERS_G => 2, - MODE_G => "INDEXED", - TDEST_HIGH_G => 1, - TDEST_LOW_G => 0) - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMaster => obCsumMaster, - sAxisSlave => open, - mAxisMasters => csumDmMasters, - mAxisSlaves => csumDmSlaves); - - -- double the stream - U_Repeater : entity surf.AxiStreamRepeater - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - NUM_MASTERS_G => 2) - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMaster => csumDmMasters(1), - sAxisSlave => csumDmSlaves(1), - mAxisMasters => csumMastersRoCE, - mAxisSlaves => csumSlavesRoCE); - - -- FIFO the second stream to wait for iCrc - U_FifoV2 : entity surf.AxiStreamFifoV2 - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - GEN_SYNC_FIFO_G => true, - FIFO_ADDR_WIDTH_G => 5, - SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - sAxisClk => ethClk, - sAxisRst => ethRst, - sAxisMaster => csumMastersRoCE(1), - sAxisSlave => csumSlavesRoCE(1), - mAxisClk => ethClk, - mAxisRst => ethRst, - mAxisMaster => csumMasterDly, - mAxisSlave => csumSlaveDly); - - U_TrailerRemove : entity surf.AxiStreamTrailerRemove - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMaster => csumMasterDly, - sAxisSlave => csumSlaveDly, - mAxisMaster => axisMasterNoTrail, - mAxisSlave => axisSlaveNoTrail); - - U_iCrc : entity surf.EthMacPrepareForICrc - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G) - port map ( - ethClk => ethClk, - ethRst => ethRst, - sAxisMaster => csumMastersRoCE(0), - sAxisSlave => csumSlavesRoCE(0), - mAxisMaster => csumiCrcMaster, - mAxisSlave => csumiCrcSlave); - - U_Compact : entity surf.AxiStreamCompact - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => ROCE_CRC32_AXI_CONFIG_C) - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMaster => csumiCrcMaster, - sAxisSlave => csumiCrcSlave, - mAxisMaster => readyForiCrcMaster, - mAxisSlave => readyForiCrcSlave); - - U_iCrcIn : entity surf.EthMacCrcAxiStreamWrapperRecv - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G) - port map ( - ethClk => ethClk, - ethRst => ethRst, - sAxisMaster => readyForiCrcMaster, - sAxisSlave => readyForiCrcSlave, - mAxisMaster => crcStreamMaster, - mAxisSlave => crcStreamSlave); - - U_CheckICrc : entity surf.EthMacRxCheckICrc - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G) - port map ( - ethClk => ethClk, - ethRst => ethRst, - sAxisMaster => axisMasterNoTrail, - sAxisSlave => axisSlaveNoTrail, - sAxisCrcCheckMaster => crcStreamMaster, - sAxisCrcCheckSlave => crcStreamSlave, - mAxisMaster => roceCheckedMaster, - mAxisSlave => roceCheckedSlave); - - U_Flush : entity surf.AxiStreamFlush - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - AXIS_CONFIG_G => EMAC_AXIS_CONFIG_C, - SSI_EN_G => true) - port map ( - axisClk => ethClk, - axisRst => ethRst, - flushEn => roceCheckedMaster.tUser(2), - sAxisMaster => roceCheckedMaster, - sAxisSlave => roceCheckedSlave, - mAxisMaster => roceMaster, - mAxisCtrl => roceCtrl); - - -------------------- - -- Packetizer FIFOs - -------------------- - U_FifoPacketizer_Roce : entity surf.AxiStreamFifoV2 - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - VALID_THOLD_G => 0, - GEN_SYNC_FIFO_G => true, - SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - sAxisClk => ethClk, - sAxisRst => ethRst, - sAxisMaster => RoceMaster, - sAxisCtrl => RoceCtrl, - mAxisClk => ethClk, - mAxisRst => ethRst, - mAxisMaster => RoceMasters(1), - mAxisSlave => RoceSlaves(1)); - - U_FifoPacketizer_Udp : entity surf.AxiStreamFifoV2 - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - VALID_THOLD_G => 0, - GEN_SYNC_FIFO_G => true, - SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - sAxisClk => ethClk, - sAxisRst => ethRst, - sAxisMaster => csumDmMasters(0), - sAxisSlave => csumDmSlaves(0), - mAxisClk => ethClk, - mAxisRst => ethRst, - mAxisMaster => roceMasters(0), - mAxisSlave => roceSlaves(0)); - - ----------------------- - -- RoCE - Normal MUX - ----------------------- - AxiStreamMux_1 : entity surf.AxiStreamMux - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - NUM_SLAVES_G => 2, - ILEAVE_EN_G => true, - ILEAVE_ON_NOTVALID_G => true, - MODE_G => "PASSTHROUGH", - TID_MODE_G => "PASSTHROUGH") - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMasters => roceMasters, - sAxisSlaves => roceSlaves, - mAxisMaster => ibBypassMaster, - mAxisSlave => AXI_STREAM_SLAVE_FORCE_C); - -end mapping; diff --git a/ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd b/ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd deleted file mode 100755 index 0f61e75206..0000000000 --- a/ethernet/RoCEv2/rtl/EthMacTxRoCEv2.vhd +++ /dev/null @@ -1,268 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: RoCEv2 Protocol Wrapper for TX path -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_arith.all; -use ieee.std_logic_unsigned.all; - -library surf; -use surf.AxiStreamPkg.all; -use surf.StdRtlPkg.all; -use surf.EthMacPkg.all; - -entity EthMacTxRoCEv2 is - generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'); -- '1' for active HIGH reset, '0' for active LOW reset - port ( - -- Clock and Reset - ethClk : in sl; - ethRst : in sl; - -- Checksum Interface - obCsumMaster : in AxiStreamMasterType; - obCsumSlave : out AxiStreamSlaveType; - -- Pause Interface - ibPauseMaster : out AxiStreamMasterType; - ibPauseSlave : in AxiStreamSlaveType); -end EthMacTxRoCEv2; - -architecture mapping of EthMacTxRoCEv2 is - - constant ROCE_CRC32CALC_AXI_CONFIG_C : AxiStreamConfigType := ( - TSTRB_EN_C => false, - TDATA_BYTES_C => 32, - TDEST_BITS_C => 0, - TID_BITS_C => 0, - TKEEP_MODE_C => TKEEP_COMP_C, - TUSER_BITS_C => 2, - TUSER_MODE_C => TUSER_FIRST_LAST_C); - - constant ROCE_CRC32_AXI_CONFIG_C : AxiStreamConfigType := ( - TSTRB_EN_C => false, - TDATA_BYTES_C => 4, - TDEST_BITS_C => 0, - TID_BITS_C => 0, - TKEEP_MODE_C => TKEEP_COMP_C, - TUSER_BITS_C => 2, - TUSER_MODE_C => TUSER_FIRST_LAST_C); - - signal csumDmMasters : AxiStreamMasterArray(1 downto 0); - signal csumDmSlaves : AxiStreamSlaveArray(1 downto 0); - - signal csumMastersRoCE : AxiStreamMasterArray(1 downto 0); - signal csumSlavesRoCE : AxiStreamSlaveArray(1 downto 0); - - signal csumMasterDly : AxiStreamMasterType; - signal csumSlaveDly : AxiStreamSlaveType; - - signal csumiCrcMaster : AxiStreamMasterType; - signal csumiCrcSlave : AxiStreamSlaveType; - - signal readyForiCrcMaster : AxiStreamMasterType; - signal readyForiCrcSlave : AxiStreamSlaveType; - - signal crcStreamMaster : AxiStreamMasterType; - signal crcStreamSlave : AxiStreamSlaveType; - - signal roceStreamMaster : AxiStreamMasterType; - signal roceStreamSlave : AxiStreamSlaveType; - - signal roceFixMaster : AxiStreamMasterType; - signal roceFixSlave : AxiStreamSlaveType; - - signal roceMasters : AxiStreamMasterArray(1 downto 0); - signal roceSlaves : AxiStreamSlaveArray(1 downto 0); - -begin - - ---------------------------------------------------------------------------- - -- RoCE iCRC calculation - ---------------------------------------------------------------------------- - U_DeMux : entity surf.AxiStreamDeMux - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - NUM_MASTERS_G => 2, - MODE_G => "INDEXED", - TDEST_HIGH_G => 1, - TDEST_LOW_G => 0) - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMaster => obCsumMaster, - sAxisSlave => obCsumSlave, - mAxisMasters => csumDmMasters, - mAxisSlaves => csumDmSlaves); - - -- double the stream - U_Repeater : entity surf.AxiStreamRepeater - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - NUM_MASTERS_G => 2) - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMaster => csumDmMasters(1), - sAxisSlave => csumDmSlaves(1), - mAxisMasters => csumMastersRoCE, - mAxisSlaves => csumSlavesRoCE); - - U_FifoV2 : entity surf.AxiStreamFifoV2 - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - GEN_SYNC_FIFO_G => true, - FIFO_ADDR_WIDTH_G => 5, - SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - sAxisClk => ethClk, - sAxisRst => ethRst, - sAxisMaster => csumMastersRoCE(1), - sAxisSlave => csumSlavesRoCE(1), - mAxisClk => ethClk, - mAxisRst => ethRst, - mAxisMaster => csumMasterDly, - mAxisSlave => csumSlaveDly); - - U_iCrc : entity surf.EthMacPrepareForICrc - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G) - port map ( - ethClk => ethClk, - ethRst => ethRst, - sAxisMaster => csumMastersRoCE(0), - sAxisSlave => csumSlavesRoCE(0), - mAxisMaster => csumiCrcMaster, - mAxisSlave => csumiCrcSlave); - - U_Compact : entity surf.AxiStreamCompact - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => ROCE_CRC32CALC_AXI_CONFIG_C) - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMaster => csumiCrcMaster, - sAxisSlave => csumiCrcSlave, - mAxisMaster => readyForiCrcMaster, - mAxisSlave => readyForiCrcSlave); - - CrcAxiStreamWrapperSend_1 : entity surf.EthMacCrcAxiStreamWrapperSend - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G) - port map ( - ethClk => ethClk, - ethRst => ethRst, - sAxisMaster => readyForiCrcMaster, - sAxisSlave => readyForiCrcSlave, - mAxisMaster => crcStreamMaster, - mAxisSlave => crcStreamSlave); - - U_TrailerAppend : entity surf.AxiStreamTrailerAppend - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - TRAILER_AXI_CONFIG_G => ROCE_CRC32_AXI_CONFIG_C, - MASTER_SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMaster => csumMasterDly, - sAxisSlave => csumSlaveDly, - sAxisTrailerMaster => crcStreamMaster, - sAxisTrailerSlave => crcStreamSlave, - mAxisMaster => roceStreamMaster, - mAxisSlave => roceStreamSlave); - - U_Compact_1 : entity surf.AxiStreamCompact - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMaster => roceStreamMaster, - sAxisSlave => roceStreamSlave, - mAxisMaster => roceFixMaster, - mAxisSlave => roceFixSlave); - - -------------------- - -- Packetizer FIFOs - -------------------- - U_FifoPacketizer_Roce : entity surf.AxiStreamFifoV2 - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - VALID_THOLD_G => 0, - GEN_SYNC_FIFO_G => true, - SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - sAxisClk => ethClk, - sAxisRst => ethRst, - sAxisMaster => RoceFixMaster, - sAxisSlave => RoceFixSlave, - mAxisClk => ethClk, - mAxisRst => ethRst, - mAxisMaster => roceMasters(1), - mAxisSlave => roceSlaves(1)); - - U_FifoPacketizer_Udp : entity surf.AxiStreamFifoV2 - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - VALID_THOLD_G => 0, - GEN_SYNC_FIFO_G => true, - SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, - MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) - port map ( - sAxisClk => ethClk, - sAxisRst => ethRst, - sAxisMaster => csumDmMasters(0), - sAxisSlave => csumDmSlaves(0), - mAxisClk => ethClk, - mAxisRst => ethRst, - mAxisMaster => roceMasters(0), - mAxisSlave => roceSlaves(0)); - - ----------------------- - -- RoCE - Normal MUX - ----------------------- - AxiStreamMux_1 : entity surf.AxiStreamMux - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - NUM_SLAVES_G => 2, - ILEAVE_EN_G => true, - ILEAVE_ON_NOTVALID_G => true, - MODE_G => "PASSTHROUGH", - TID_MODE_G => "PASSTHROUGH") - port map ( - axisClk => ethClk, - axisRst => ethRst, - sAxisMasters => roceMasters, - sAxisSlaves => roceSlaves, - mAxisMaster => ibPauseMaster, - mAxisSlave => ibPauseSlave); - -end mapping; diff --git a/ethernet/RoCEv2/rtl/ExtractHeaderFromDataStreamPipeOut.vhd b/ethernet/RoCEv2/rtl/ExtractHeaderFromDataStreamPipeOut.vhd new file mode 100644 index 0000000000..85adf8730c --- /dev/null +++ b/ethernet/RoCEv2/rtl/ExtractHeaderFromDataStreamPipeOut.vhd @@ -0,0 +1,561 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Inverse of PrependHeader2PipeOut. Splits one incoming left-aligned +-- DataStream (header bytes immediately followed by payload bytes, described +-- by a HeaderMetaData token) into two separate output streams: +-- * header — the header fragments, last fragment trimmed to the header's +-- valid byte count; +-- * payload — the payload bytes that followed the header, re-left-aligned +-- by de-shifting the header's trailing partial fragment back +-- out and concatenating across fragment boundaries, emitting an +-- extra trailing fragment when the de-shift overflows a word. +-- If a header carries no payload (or the input ran out before any payload +-- byte), an empty DataStream {0,0,isFirst,isLast} is pushed to `payload` to +-- keep header and payload aligned 1:1. +-- +-- 4-stage FSM (BSV stageReg : ExtractOrPrependHeaderStage): +-- HEADER_META_DATA_POP_S — latch HeaderMetaData + first data frag +-- HEADER_OUTPUT_S — emit header frags to U_HeaderDataStreamOutQ +-- DATA_OUTPUT_S — emit de-shifted payload frags +-- EXTRA_LAST_FRAG_OUTPUT_S — emit trailing payload frag from leftover bits +-- +-- BSV rules implemented (mutually exclusive on stageReg → single case): +-- popHeaderMetaData → HEADER_META_DATA_POP_S +-- outputHeader → HEADER_OUTPUT_S +-- outputData → DATA_OUTPUT_S +-- extraLastFrag → EXTRA_LAST_FRAG_OUTPUT_S +-- +-- Mapping note (OQ-FSM-EHDSPO-01): +-- mapping.json/modules.json are STALE for this entity (owns.rules=[], +-- surf_instances=[], and a bogus DataStream2Header child). The BSV source +-- is authoritative: no child modules, two output FIFOs, 12 registers. +-- This file follows the BSV source + fsm.md, not mapping.json. +-- +-- Width notes: +-- DataStream = 290 b (data 256 + byteEn 32 + isFirst 1 + isLast 1) +-- (OQ-FSM-EHDSPO-02 / OQ-FSM-H2DS-02 RESOLVED — NOT 321). +-- HeaderMetaData = 17 b (headerLen 7 + headerFragNum 2 + +-- lastFragValidByteNum 6 + hasPayload 1 + isEmptyHeader 1). +-- The fsm.md "42b" is an error; confirmed 17 b against +-- DataTypes.bsv and the sibling Header2DataStream entity. +-- Only headerFragNum and lastFragValidByteNum are read functionally here. +-- +-- Bit packing (BSV deriving(Bits), first-field-at-MSB; OQ-FSM-EHDSPO-03 / +-- OQ-FSM-H2DS-04 RESOLVED): +-- DataStream: +-- [289:34] data[255:0] (256 b) +-- [33:2] byteEn[31:0] (32 b) -- left-aligned mask (MSB = first byte) +-- [1] isFirst +-- [0] isLast +-- HeaderMetaData: +-- [16:10] headerLen[6:0] (sim-only assert; unused in RTL) +-- [9:8] headerFragNum[1:0] +-- [7:2] lastFragValidByteNum[5:0] +-- [1] hasPayload (unused here) +-- [0] isEmptyHeader (unused here) +-- +-- Helper semantics (faithful to BSV — read the source, not the fsm.md prose): +-- genByteEn(n) = reverseBits((1< '0'); + begin + n := to_integer(unsigned(validByteNum)); + for i in 0 to 31 loop + if i >= (32 - n) then + ret(i) := '1'; + end if; + end loop; + return ret; + end function genByteEn; + + -- isZeroByteEn(b) = isZero({msb(b), lsb(b)}): only the MSB and LSB are tested + function isZeroByteEn (be : slv) return boolean is + begin + return (be(be'high) = '0') and (be(be'low) = '0'); + end function isZeroByteEn; + + --------------------------------------------------------------------------- + -- FSM state (BSV stageReg : ExtractOrPrependHeaderStage) + --------------------------------------------------------------------------- + type StateType is ( + HEADER_META_DATA_POP_S, + HEADER_OUTPUT_S, + DATA_OUTPUT_S, + EXTRA_LAST_FRAG_OUTPUT_S); + + type RegType is record + stageReg : StateType; + -- mkRegU context registers (no architectural reset; written before read) + preDataStreamReg : slv(289 downto 0); -- previous frag (de-shift high half) + curDataStreamReg : slv(289 downto 0); -- current frag (low half / header frag) + headerFragNum : slv(1 downto 0); -- remaining header frags (decremented) + headerLastFragByteEn : slv(31 downto 0); -- byteEn mask for header last frag + headerLastFragInvalidBitNum : slv(8 downto 0); -- (32-validByteNum)<<3 + headerLastFragInvalidByteNum : slv(5 downto 0); -- 32-validByteNum + headerLastFragValidBitNum : slv(8 downto 0); -- validByteNum<<3 + headerLastFragValidByteNum : slv(5 downto 0); -- header last-frag valid byte count + isFirstDataFrag : sl; -- payload-out isFirst flag + isHeaderLastFrag : sl; -- current frag is the last header frag + shiftedCurDataFragByteEn : slv(31 downto 0); -- curFrag.byteEn << validByteNum + end record RegType; + + -- stageReg: mkReg(HEADER_META_DATA_POP) → reset value. + -- All other fields: mkRegU → no real reset; set to '0' (written before read on + -- every live path; OQ-FSM-04 / OQ-FSM-PH2PO precedent). + constant REG_INIT_C : RegType := ( + stageReg => HEADER_META_DATA_POP_S, + preDataStreamReg => (others => '0'), + curDataStreamReg => (others => '0'), + headerFragNum => (others => '0'), + headerLastFragByteEn => (others => '0'), + headerLastFragInvalidBitNum => (others => '0'), + headerLastFragInvalidByteNum => (others => '0'), + headerLastFragValidBitNum => (others => '0'), + headerLastFragValidByteNum => (others => '0'), + isFirstDataFrag => '0', + isHeaderLastFrag => '0', + shiftedCurDataFragByteEn => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Output-FIFO control signals (driven by comb process) + signal headerOutQNotFull : sl; + signal headerOutQWrEn : sl; + signal headerOutQDin : slv(289 downto 0); + signal payloadOutQNotFull : sl; + signal payloadOutQWrEn : sl; + signal payloadOutQDin : slv(289 downto 0); + + -- Internal copies of the deq output ports (driven from the comb process) + signal dataPipeInRdEn_i : sl; + signal hdrMetaPipeInRdEn_i : sl; + +begin + + dataPipeInRdEn <= dataPipeInRdEn_i; + hdrMetaPipeInRdEn <= hdrMetaPipeInRdEn_i; + + --------------------------------------------------------------------------- + -- U_HeaderDataStreamOutQ : surf.Fifo + -- BSV: headerDataStreamOutQ <- mkFIFOF; read side = `header` PipeOut. + -- DATA_WIDTH_G=290, FWFT (first = combinational dout/valid), sync, block. + --------------------------------------------------------------------------- + U_HeaderDataStreamOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => headerOutQWrEn, + din => headerOutQDin, + not_full => headerOutQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => headerRdEn, + dout => headerData, + valid => headerValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_PayloadDataStreamOutQ : surf.Fifo + -- BSV: payloadDataStreamOutQ <- mkFIFOF; read side = `payload` PipeOut. + -- DATA_WIDTH_G=290, FWFT, sync, block. + --------------------------------------------------------------------------- + U_PayloadDataStreamOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => payloadOutQWrEn, + din => payloadOutQDin, + not_full => payloadOutQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => payloadRdEn, + dout => payloadData, + valid => payloadValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process (two-process FSM) + --------------------------------------------------------------------------- + comb : process (r, rst, + dataPipeInValid, dataPipeInData, + hdrMetaPipeInValid, hdrMetaPipeInData, + headerOutQNotFull, payloadOutQNotFull) is + variable v : RegType; + + -- popHeaderMetaData scratch + variable hmdFragNum : slv(1 downto 0); + variable vByte : slv(5 downto 0); + variable invByte : slv(5 downto 0); + variable validBit : slv(8 downto 0); + variable invalidBit : slv(8 downto 0); + variable firstByteEn : slv(31 downto 0); + + -- outputHeader scratch + variable cur : slv(289 downto 0); + variable curIsLast : sl; + variable hasDataAfter : boolean; + variable nextByteEn : slv(31 downto 0); + + -- outputData scratch + variable noExtraLast : boolean; + variable concatData : slv(511 downto 0); + variable concatByteEn : slv(63 downto 0); + variable shData : slv(511 downto 0); + variable shByteEn : slv(63 downto 0); + variable payIsLast : sl; + + -- extraLastFrag scratch + variable lsData : slv(255 downto 0); + variable lsByteEn : slv(31 downto 0); + + -- shared fire gate + variable canFire : boolean; + begin + v := r; + + -- Default Mealy outputs (deasserted; overridden per fired transition) + headerOutQWrEn <= '0'; + headerOutQDin <= (others => '0'); + payloadOutQWrEn <= '0'; + payloadOutQDin <= (others => '0'); + dataPipeInRdEn_i <= '0'; + hdrMetaPipeInRdEn_i <= '0'; + + case r.stageReg is + + ----------------------------------------------------------------- + -- popHeaderMetaData : POP -> HOUT + -- Needs both upstream pipes ready (it deqs both); no enq → no + -- notFull gate. + ----------------------------------------------------------------- + when HEADER_META_DATA_POP_S => + canFire := (hdrMetaPipeInValid = '1') and (dataPipeInValid = '1'); + if canFire then + hmdFragNum := hdrMetaPipeInData(9 downto 8); -- headerFragNum + vByte := hdrMetaPipeInData(7 downto 2); -- lastFragValidByteNum + + -- calcFragBitNumAndByteNum(vByte) + validBit := slv(shift_left(resize(unsigned(vByte), 9), 3)); + invByte := slv(to_unsigned(DATA_BUS_BYTE_WIDTH_C, 6) - unsigned(vByte)); + invalidBit := slv(shift_left(resize(unsigned(invByte), 9), 3)); + + v.headerLastFragValidByteNum := vByte; + v.headerLastFragValidBitNum := validBit; + v.headerLastFragInvalidByteNum := invByte; + v.headerLastFragInvalidBitNum := invalidBit; + v.headerLastFragByteEn := genByteEn(vByte); + + -- isHeaderLastFrag uses the ORIGINAL fragNum; store fragNum-1 + v.isHeaderLastFrag := toSl(hmdFragNum = "01"); + v.headerFragNum := slv(unsigned(hmdFragNum) - 1); + + -- latch first data frag; precompute payload-after-header detector + v.curDataStreamReg := dataPipeInData; + firstByteEn := dataPipeInData(DsByteEnRange); + v.shiftedCurDataFragByteEn := + slv(shift_left(unsigned(firstByteEn), to_integer(unsigned(vByte)))); + + -- deq both upstream pipes + hdrMetaPipeInRdEn_i <= '1'; + dataPipeInRdEn_i <= '1'; + + v.stageReg := HEADER_OUTPUT_S; + end if; + + ----------------------------------------------------------------- + -- outputHeader : HOUT + -- Always enq header. cur.isLast branch may enq payload (empty pad); + -- !cur.isLast branch deqs dataPipeIn. + ----------------------------------------------------------------- + when HEADER_OUTPUT_S => + cur := r.curDataStreamReg; + curIsLast := cur(DS_ISLAST_C); + -- hasDataFragAfterHeader = !isZeroByteEn(shifted) && isHeaderLastFrag + hasDataAfter := (not isZeroByteEn(r.shiftedCurDataFragByteEn)) + and (r.isHeaderLastFrag = '1'); + + if curIsLast = '1' then + -- gate: header enq always; payload enq only when !hasDataAfter + if hasDataAfter then + canFire := (headerOutQNotFull = '1'); + else + canFire := (headerOutQNotFull = '1') and (payloadOutQNotFull = '1'); + end if; + + if canFire then + v.preDataStreamReg := cur; + + -- header out frag: keep data/isFirst, trim byteEn, force isLast=1 + if hasDataAfter then + nextByteEn := r.headerLastFragByteEn; + else + nextByteEn := cur(DsByteEnRange); + end if; + headerOutQWrEn <= '1'; + headerOutQDin <= cur(DsDataRange) & nextByteEn & cur(DS_ISFIRST_C) & '1'; + + v.isFirstDataFrag := toSl(hasDataAfter); + + if hasDataAfter then + -- hasDataAfter implies isHeaderLastFrag, so this is EXTRA + if r.isHeaderLastFrag = '1' then + v.stageReg := EXTRA_LAST_FRAG_OUTPUT_S; + else + v.stageReg := DATA_OUTPUT_S; + end if; + else + -- no payload: push empty pad frag to keep header/payload 1:1 + payloadOutQWrEn <= '1'; + payloadOutQDin <= (others => '0'); -- data=0, byteEn=0 + payloadOutQDin(DS_ISFIRST_C) <= '1'; + payloadOutQDin(DS_ISLAST_C) <= '1'; + v.stageReg := HEADER_META_DATA_POP_S; + end if; + end if; + + else -- not cur.isLast : more header/data frags follow + canFire := (headerOutQNotFull = '1') and (dataPipeInValid = '1'); + if canFire then + v.preDataStreamReg := cur; + + -- advance to next frag + v.curDataStreamReg := dataPipeInData; + nextByteEn := dataPipeInData(DsByteEnRange); + v.shiftedCurDataFragByteEn := + slv(shift_left(unsigned(nextByteEn), + to_integer(unsigned(r.headerLastFragValidByteNum)))); + dataPipeInRdEn_i <= '1'; + + if r.isHeaderLastFrag = '1' then + -- finish header: trim byteEn, force isLast=1, go to DATA + headerOutQWrEn <= '1'; + headerOutQDin <= cur(DsDataRange) & r.headerLastFragByteEn + & cur(DS_ISFIRST_C) & '1'; + v.isFirstDataFrag := '1'; + v.stageReg := DATA_OUTPUT_S; + else + -- mid-header full frag (isLast stays 0); decrement fragNum + headerOutQWrEn <= '1'; + headerOutQDin <= cur; -- full frag unchanged + v.isHeaderLastFrag := toSl(r.headerFragNum = "01"); + v.headerFragNum := slv(unsigned(r.headerFragNum) - 1); + -- stageReg stays HEADER_OUTPUT_S + end if; + end if; + end if; + + ----------------------------------------------------------------- + -- outputData : DOUT + -- Always enq payload (de-shifted). !cur.isLast also deqs dataPipeIn. + ----------------------------------------------------------------- + when DATA_OUTPUT_S => + cur := r.curDataStreamReg; + curIsLast := cur(DS_ISLAST_C); + if curIsLast = '1' then + canFire := (payloadOutQNotFull = '1'); + else + canFire := (payloadOutQNotFull = '1') and (dataPipeInValid = '1'); + end if; + + if canFire then + noExtraLast := isZeroByteEn(r.shiftedCurDataFragByteEn); + + -- {pre, cur} with pre as MSB, then >> invalid count, truncate to low half + concatData := r.preDataStreamReg(DsDataRange) & r.curDataStreamReg(DsDataRange); + concatByteEn := r.preDataStreamReg(DsByteEnRange) & r.curDataStreamReg(DsByteEnRange); + shData := slv(shift_right(unsigned(concatData), + to_integer(unsigned(r.headerLastFragInvalidBitNum)))); + shByteEn := slv(shift_right(unsigned(concatByteEn), + to_integer(unsigned(r.headerLastFragInvalidByteNum)))); + + -- isLast = cur.isLast && noExtraLast ; isFirst = OLD r.isFirstDataFrag + if (curIsLast = '1') and noExtraLast then + payIsLast := '1'; + else + payIsLast := '0'; + end if; + payloadOutQWrEn <= '1'; + payloadOutQDin <= shData(255 downto 0) & shByteEn(31 downto 0) + & r.isFirstDataFrag & payIsLast; + + v.preDataStreamReg := cur; + v.isFirstDataFrag := '0'; + + if curIsLast = '1' then + if noExtraLast then + v.stageReg := HEADER_META_DATA_POP_S; + else + v.stageReg := EXTRA_LAST_FRAG_OUTPUT_S; + end if; + else + v.curDataStreamReg := dataPipeInData; + nextByteEn := dataPipeInData(DsByteEnRange); + v.shiftedCurDataFragByteEn := + slv(shift_left(unsigned(nextByteEn), + to_integer(unsigned(r.headerLastFragValidByteNum)))); + dataPipeInRdEn_i <= '1'; + end if; + end if; + + ----------------------------------------------------------------- + -- extraLastFrag : EXTRA -> POP + -- Emit the trailing payload frag from the leftover (left-shifted) + -- bits of preDataStreamReg. Enq payload only. + ----------------------------------------------------------------- + when EXTRA_LAST_FRAG_OUTPUT_S => + canFire := (payloadOutQNotFull = '1'); + if canFire then + lsData := slv(shift_left(unsigned(r.preDataStreamReg(DsDataRange)), + to_integer(unsigned(r.headerLastFragValidBitNum)))); + lsByteEn := slv(shift_left(unsigned(r.preDataStreamReg(DsByteEnRange)), + to_integer(unsigned(r.headerLastFragValidByteNum)))); + payloadOutQWrEn <= '1'; + payloadOutQDin <= lsData & lsByteEn & r.isFirstDataFrag & '1'; + + v.isFirstDataFrag := '0'; + v.stageReg := HEADER_META_DATA_POP_S; + end if; + + end case; + + -- Synchronous reset (matches BSV mkReg(HEADER_META_DATA_POP) for stageReg) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ExtractHeaderFromRdmaPktPipeOut.vhd b/ethernet/RoCEv2/rtl/ExtractHeaderFromRdmaPktPipeOut.vhd new file mode 100644 index 0000000000..8b89d17636 --- /dev/null +++ b/ethernet/RoCEv2/rtl/ExtractHeaderFromRdmaPktPipeOut.vhd @@ -0,0 +1,527 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Thin front-end splitter / fan-out wrapper around the child +-- ExtractHeaderFromDataStreamPipeOut. Takes ONE incoming RDMA-packet +-- DataStream pipe (rdmaPktPipeIn, header bytes left-aligned at the front of +-- the first fragment) and: +-- 1. forwards every fragment verbatim into U_DataInQ; +-- 2. on the FIRST fragment only, decodes the BTH {transType, rdmaOpCode} +-- field, looks up the header byte length + has-payload flag, builds a +-- 17-bit HeaderMetaData token and pushes it into U_HeaderMetaDataInQ; +-- 3. fans the metadata token out 2 ways (U_Fork, replicate-with-join): +-- copy[0] → child U_ExtractDS.headerMetaDataPipeIn (unbuffered) +-- copy[1] → U_HeaderMetaDataBuf → exposed headerMetaData PipeOut +-- 4. instantiates the child extractor U_ExtractDS, fed by U_DataInQ and +-- fork copy[0]; its header/payload outputs pass straight through to this +-- module's interface. +-- +-- ALL header/payload byte-splitting is done by the CHILD entity. This module +-- does NOT touch payload data; it only routes fragments + emits the metadata +-- token (it is mkForkAndBufferRight on the metadata stream + the opcode decode). +-- +-- Mapping note (OQ-FSM-EHRPPO-01): mapping.json/modules.json are STALE for this +-- entity (owns.rules=["extract"]→actual "extractHeader"; a bogus single "outQ" +-- Fifo; interface PipeOut#(RdmaHeader)→actual +-- HeaderAndMetaDataAndPayloadSeperateDataStreamPipeOut). The BSV source + +-- fsm.md are authoritative; this file follows them, not mapping.json. +-- +-- Width notes (traced from DataTypes.bsv / Headers.bsv / Settings.bsv): +-- DataStream = 290 b (data 256 + byteEn 32 + isFirst 1 + isLast 1) +-- HeaderMetaData = 17 b (headerLen 7 + headerFragNum 2 + +-- lastFragValidByteNum 6 + hasPayload 1 + isEmptyHeader 1) +-- DATA_BUS_WIDTH = 256, DATA_BUS_BYTE_WIDTH = 32 (5-bit byte index) +-- TransType = 3 b (data[255:253] of first frag) +-- RdmaOpCode = 5 b (data[252:248] of first frag) +-- +-- Bit packing (BSV deriving(Bits), first-field-at-MSB; project-wide +-- OQ-FSM-H2DS-04): +-- DataStream: [289:34]=data [33:2]=byteEn [1]=isFirst [0]=isLast +-- HeaderMetaData: [16:10]=headerLen [9:8]=headerFragNum +-- [7:2]=lastFragValidByteNum [1]=hasPayload [0]=isEmptyHeader +-- +-- Decode datapath (faithful to Utils.bsv / Headers.bsv, isFirst path only): +-- extractTranTypeAndRdmaOpCode : transType = data[255:253], +-- rdmaOpCode = data[252:248] (Utils.bsv:840) +-- rdmaOpCodeHasPayload(opcode) : LUT on the 5-bit opcode (Headers.bsv:407) +-- calcHeaderLenByTransTypeAndRdmaOpCode(transType, opcode) : +-- ROM keyed on the 8-bit {transType, opcode} (Headers.bsv:286) +-- (BTH=12 + optional XRCETH=4/RETH=16/AETH=4/IMM_DT=4/IETH=4/DETH=8/ +-- ATOMIC_ETH=28/ATOMIC_ACK_ETH=8/CNP_PAYLOAD=16; default 0) +-- genHeaderMetaData(headerLen, hasPayload) (Utils.bsv:303) +-- headerFragNum = headerLen[6:5] + (headerLen[4:0]/=0 ? 1 : 0) +-- lastFragValidByteNum = (residue==0 && headerLen[6:5]/=0) ? 32 +-- : zeroExt(residue) +-- isEmptyHeader = '0' (constant) +-- The BSV immAssert(!isZero(headerLen)) is simulation-only and is NOT +-- emitted (synthesis drops it); an unknown opcode yields headerLen=0. +-- +-- SURF components instantiated (read at emit from the .vhd source): +-- U_DataInQ : surf.Fifo (DATA_WIDTH_G=290, FWFT, sync, block) +-- source: surf/base/fifo/rtl/Fifo.vhd (BSV: dataInQ <- mkFIFOF; +-- read side owned by the child U_ExtractDS.dataPipeIn) +-- U_HeaderMetaDataInQ : surf.Fifo (DATA_WIDTH_G=17, FWFT, sync, dist) +-- source: surf/base/fifo/rtl/Fifo.vhd (BSV: headerMetaDataInQ <- mkFIFOF; +-- read side owned by U_Fork) +-- U_HeaderMetaDataBuf : surf.Fifo (DATA_WIDTH_G=17, FWFT, sync, dist) +-- source: surf/base/fifo/rtl/Fifo.vhd (BSV: mkBuffer = mkPipelineFIFOF, +-- 1-deep; emitted as a depth-16 Fifo — SURF ADDR_WIDTH_G min is 4. Extra +-- buffering is behaviour-preserving for the notFull/notEmpty handshake; +-- OQ-EMIT-EHRPPO-02.) +-- Hand-rolled (no stock SURF entity — OQ-FSM-EHRPPO-02 / OQ-EMIT-EHRPPO-01): +-- U_Fork : the 2-way mkForkVector replicate-with-join is NOT a catalog +-- component (the SURF replicate entity AxiStreamSplitter is AXI-Stream-only; +-- this metadata path uses plain valid/data/rdEn PipeOut ports). It is the +-- ONLY state in this module: a 2-bit "taken" register (r.forkTaken) so the +-- source HeaderMetaDataInQ is dequeued only once BOTH consumers (child + +-- buffer) have accepted the token. +-- Child entity: +-- U_ExtractDS : work.ExtractHeaderFromDataStreamPipeOut +-- spec: out/03-fsm/ExtractHeaderFromDataStreamPipeOut.fsm.md +-- +-- Scheduling fidelity (fsm.md §Conflicts): the metadata-FIFO readiness gates the +-- single extractHeader rule ONLY on the isFirst path (the enq sits inside +-- `if (isFirst)`). The data path must NOT stall on U_HeaderMetaDataInQ fullness +-- for non-first fragments: +-- deqEn = inValid && dataInQ.notFull && (isFirst -> hdrMetaInQ.notFull) +-- All rule actions are one atomic BSV firing → one block of combinational enables. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ExtractHeaderFromRdmaPktPipeOut is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Upstream: one RDMA packet DataStream pipe (module arg rdmaPktPipeIn) + rdmaPktPipeInValid : in sl; -- rdmaPktPipeIn.notEmpty + rdmaPktPipeInData : in slv(289 downto 0); -- rdmaPktPipeIn.first (DataStream) + rdmaPktPipeInRdEn : out sl; -- rdmaPktPipeIn.deq + -- Downstream: header DataStream (headerAndMetaData.headerDataStream = child.header) + headerDataStreamValid : out sl; -- header.notEmpty + headerDataStreamData : out slv(289 downto 0); -- header.first (DataStream) + headerDataStreamRdEn : in sl; -- header.deq + -- Downstream: header metadata token (headerAndMetaData.headerMetaData = buffer) + headerMetaDataValid : out sl; -- headerMetaData.notEmpty + headerMetaDataData : out slv(16 downto 0); -- headerMetaData.first (HeaderMetaData) + headerMetaDataRdEn : in sl; -- headerMetaData.deq + -- Downstream: payload DataStream (payload = child.payload) + payloadValid : out sl; -- payload.notEmpty + payloadData : out slv(289 downto 0); -- payload.first (DataStream) + payloadRdEn : in sl); -- payload.deq +end entity ExtractHeaderFromRdmaPktPipeOut; + +architecture rtl of ExtractHeaderFromRdmaPktPipeOut is + + --------------------------------------------------------------------------- + -- Widths / DataStream field slicing (290-bit packed layout) + --------------------------------------------------------------------------- + constant DS_WIDTH_C : natural := 290; + constant HMD_WIDTH_C : natural := 17; + constant DATA_BUS_BYTE_WIDTH_C : natural := 32; -- DATA_BUS_WIDTH/8 + + subtype DsDataRange is natural range 289 downto 34; -- 256 b + constant DS_ISFIRST_C : natural := 1; + + --------------------------------------------------------------------------- + -- Header-component byte widths (Headers.bsv SizeOf comments, verified) + --------------------------------------------------------------------------- + constant BTH_BYTE_C : natural := 12; + constant AETH_BYTE_C : natural := 4; + constant RETH_BYTE_C : natural := 16; + constant ATOMIC_ETH_BYTE_C : natural := 28; + constant ATOMIC_ACK_ETH_BYTE_C : natural := 8; + constant IMM_DT_BYTE_C : natural := 4; + constant IETH_BYTE_C : natural := 4; + constant DETH_BYTE_C : natural := 8; + constant XRCETH_BYTE_C : natural := 4; + constant CNP_PAYLOAD_BYTE_C : natural := 16; + + --------------------------------------------------------------------------- + -- BSV decode helpers (faithful to Headers.bsv / Utils.bsv) + --------------------------------------------------------------------------- + -- rdmaOpCodeHasPayload : LUT on the 5-bit RdmaOpCode (Headers.bsv:407) + function rdmaOpCodeHasPayload (opcode : slv(4 downto 0)) return sl is + begin + case opcode is + when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | -- SEND_FIRST..ONLY_WITH_IMMEDIATE + "00110" | "00111" | "01000" | "01001" | "01010" | "01011" | -- RDMA_WRITE_FIRST..ONLY_WITH_IMMEDIATE + "01101" | "01110" | "01111" | "10000" | -- RDMA_READ_RESPONSE_FIRST..ONLY + "10110" | "10111" => -- SEND_{LAST,ONLY}_WITH_INVALIDATE + return '1'; + when others => + return '0'; + end case; + end function rdmaOpCodeHasPayload; + + -- calcHeaderLenByTransTypeAndRdmaOpCode : ROM keyed on {transType(3),opcode(5)} + -- (Headers.bsv:286-344; the active, non-commented variant). Returns 7-bit + -- header byte length; unknown keys → 0 (BSV default). + function calcHeaderLen (key : slv(7 downto 0)) return slv is + variable n : natural := 0; + begin + case key is + -- RC requests / responses + when x"00" | x"01" | x"02" | x"04" | x"07" | x"08" | x"0e" => + n := BTH_BYTE_C; -- 12 + when x"03" | x"05" | x"09" | x"0d" | x"0f" | x"10" | x"11" | x"16" | x"17" => + n := BTH_BYTE_C + AETH_BYTE_C; -- 16 (also =BTH+IMM_DT/IETH) + when x"06" | x"0a" | x"0c" => + n := BTH_BYTE_C + RETH_BYTE_C; -- 28 + when x"0b" => + n := BTH_BYTE_C + RETH_BYTE_C + IMM_DT_BYTE_C; -- 32 + when x"12" => + n := BTH_BYTE_C + AETH_BYTE_C + ATOMIC_ACK_ETH_BYTE_C; -- 24 + when x"13" | x"14" => + n := BTH_BYTE_C + ATOMIC_ETH_BYTE_C; -- 40 + -- RC/XRC responses sharing AETH-based lengths + when x"ad" | x"af" | x"b0" | x"b1" => + n := BTH_BYTE_C + AETH_BYTE_C; -- 16 + when x"ae" => + n := BTH_BYTE_C; -- 12 + when x"b2" => + n := BTH_BYTE_C + AETH_BYTE_C + ATOMIC_ACK_ETH_BYTE_C; -- 24 + -- XRC requests (BTH + XRCETH + ...) + when x"a0" | x"a1" | x"a2" | x"a4" | x"a7" | x"a8" => + n := BTH_BYTE_C + XRCETH_BYTE_C; -- 16 + when x"a3" | x"a5" | x"a9" | x"b6" | x"b7" => + n := BTH_BYTE_C + XRCETH_BYTE_C + IMM_DT_BYTE_C; -- 20 (IMM_DT/IETH both 4) + when x"a6" | x"aa" | x"ac" => + n := BTH_BYTE_C + XRCETH_BYTE_C + RETH_BYTE_C; -- 32 + when x"ab" => + n := BTH_BYTE_C + XRCETH_BYTE_C + RETH_BYTE_C + IMM_DT_BYTE_C; -- 36 + when x"b3" | x"b4" => + n := BTH_BYTE_C + XRCETH_BYTE_C + ATOMIC_ETH_BYTE_C; -- 44 + -- UD requests (BTH + DETH + ...) + when x"64" => + n := BTH_BYTE_C + DETH_BYTE_C; -- 20 + when x"65" => + n := BTH_BYTE_C + DETH_BYTE_C + IMM_DT_BYTE_C; -- 24 + -- CNP notification + when x"81" => + n := BTH_BYTE_C + CNP_PAYLOAD_BYTE_C; -- 28 + when others => + n := 0; + end case; + return slv(to_unsigned(n, 7)); + end function calcHeaderLen; + + -- genHeaderMetaData(headerLen, hasPayload) → packed 17-bit HeaderMetaData + -- (Utils.bsv:303 + calcHeaderFragNumAndLastFragValidByeNum, Utils.bsv:284) + function genHeaderMetaData (headerLen : slv(6 downto 0); hasPayload : sl) return slv is + variable residue : unsigned(4 downto 0); + variable truncLen : unsigned(1 downto 0); + variable fragNum : unsigned(1 downto 0); + variable lastVbn : unsigned(5 downto 0); + begin + residue := unsigned(headerLen(4 downto 0)); + truncLen := unsigned(headerLen(6 downto 5)); + if residue /= 0 then + fragNum := truncLen + 1; + else + fragNum := truncLen; + end if; + if (residue = 0) and (truncLen /= 0) then + lastVbn := to_unsigned(DATA_BUS_BYTE_WIDTH_C, 6); -- 32 + else + lastVbn := resize(residue, 6); + end if; + -- [16:10]headerLen [9:8]headerFragNum [7:2]lastFragValidByteNum [1]hasPayload [0]isEmptyHeader + return headerLen & slv(fragNum) & slv(lastVbn) & hasPayload & '0'; + end function genHeaderMetaData; + + --------------------------------------------------------------------------- + -- FSM state : ONLY the U_Fork replicate-with-join "taken" flags. + -- forkTaken(0) = child copy already consumed ; forkTaken(1) = buffer copy. + --------------------------------------------------------------------------- + type RegType is record + forkTaken : slv(1 downto 0); + end record RegType; + + constant REG_INIT_C : RegType := ( + forkTaken => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- rdmaPktPipeIn deq (driven by comb; out port cannot be read back) + signal rdmaPktPipeInRdEn_i : sl; + + -- U_DataInQ (290 b) + signal dataInQWrEn : sl; + signal dataInQDin : slv(DS_WIDTH_C-1 downto 0); + signal dataInQNotFull: sl; + signal dataInQValid : sl; + signal dataInQDout : slv(DS_WIDTH_C-1 downto 0); + signal dataInQRdEn : sl; -- owned by child U_ExtractDS + + -- U_HeaderMetaDataInQ (17 b) — fork source + signal hmdInQWrEn : sl; + signal hmdInQDin : slv(HMD_WIDTH_C-1 downto 0); + signal hmdInQNotFull : sl; + signal hmdInQValid : sl; + signal hmdInQDout : slv(HMD_WIDTH_C-1 downto 0); + signal hmdInQRdEn : sl; -- driven by comb (fork join deq) + + -- U_Fork outputs + signal fork0Valid : sl; -- comb → child.hdrMetaPipeInValid + signal childHdrMetaRdEn : sl; -- child.hdrMetaPipeInRdEn → comb + + -- U_HeaderMetaDataBuf (17 b) — copy[1] buffer + signal bufWrEn : sl; + signal bufNotFull : sl; + +begin + + rdmaPktPipeInRdEn <= rdmaPktPipeInRdEn_i; + -- U_DataInQ din is the input fragment verbatim (gated by dataInQWrEn) + dataInQDin <= rdmaPktPipeInData; + + --------------------------------------------------------------------------- + -- U_DataInQ : surf.Fifo (BSV: dataInQ <- mkFIFOF) + -- Write side driven by extractHeader; read side feeds child U_ExtractDS. + --------------------------------------------------------------------------- + U_DataInQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => dataInQWrEn, + din => dataInQDin, + not_full => dataInQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => dataInQRdEn, + dout => dataInQDout, + valid => dataInQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_HeaderMetaDataInQ : surf.Fifo (BSV: headerMetaDataInQ <- mkFIFOF) + -- Write side driven by extractHeader (isFirst path); read side = U_Fork. + --------------------------------------------------------------------------- + U_HeaderMetaDataInQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => HMD_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => hmdInQWrEn, + din => hmdInQDin, + not_full => hmdInQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => hmdInQRdEn, + dout => hmdInQDout, + valid => hmdInQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_HeaderMetaDataBuf : surf.Fifo (BSV: mkBuffer = mkPipelineFIFOF, 1-deep) + -- Consumes fork copy[1]; read side = exposed headerMetaData PipeOut. + -- Emitted depth 16 (SURF ADDR_WIDTH_G min 4); see OQ-EMIT-EHRPPO-02. + --------------------------------------------------------------------------- + U_HeaderMetaDataBuf : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => HMD_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => bufWrEn, + din => hmdInQDout, -- fork copy[1] payload = source token + not_full => bufNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => headerMetaDataRdEn, + dout => headerMetaDataData, + valid => headerMetaDataValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_ExtractDS : child entity ExtractHeaderFromDataStreamPipeOut + -- dataPipeIn ← U_DataInQ (read side owned here) + -- headerMetaDataPipeIn ← U_Fork copy[0] (unbuffered) + -- header / payload → this module's interface (pass-through) + --------------------------------------------------------------------------- + U_ExtractDS : entity surf.ExtractHeaderFromDataStreamPipeOut + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + dataPipeInValid => dataInQValid, + dataPipeInData => dataInQDout, + dataPipeInRdEn => dataInQRdEn, + hdrMetaPipeInValid => fork0Valid, + hdrMetaPipeInData => hmdInQDout, -- fork copy[0] payload = source token + hdrMetaPipeInRdEn => childHdrMetaRdEn, + headerValid => headerDataStreamValid, + headerData => headerDataStreamData, + headerRdEn => headerDataStreamRdEn, + payloadValid => payloadValid, + payloadData => payloadData, + payloadRdEn => payloadRdEn); + + --------------------------------------------------------------------------- + -- Combinatorial process (two-process FSM) + -- * extractHeader rule (Mealy routing + first-frag decode) + -- * U_Fork 2-way replicate-with-join (the only registered state) + --------------------------------------------------------------------------- + comb : process (r, rst, + rdmaPktPipeInValid, rdmaPktPipeInData, + dataInQNotFull, hmdInQNotFull, hmdInQValid, hmdInQDout, + childHdrMetaRdEn, bufNotFull) is + variable v : RegType; + variable isFirst : sl; + variable ruleFires : boolean; + variable data : slv(255 downto 0); + variable transType : slv(2 downto 0); + variable rdmaOpCode : slv(4 downto 0); + variable hasPayload : sl; + variable headerLen : slv(6 downto 0); + -- fork join + variable take0 : sl; + variable take1 : sl; + variable newTaken0 : sl; + variable newTaken1 : sl; + begin + v := r; + + -- Default Mealy outputs (deasserted) + rdmaPktPipeInRdEn_i <= '0'; + dataInQWrEn <= '0'; + hmdInQWrEn <= '0'; + hmdInQDin <= (others => '0'); + hmdInQRdEn <= '0'; + fork0Valid <= '0'; + bufWrEn <= '0'; + + ---------------------------------------------------------------------- + -- extractHeader rule (single implied PASS_S state) + -- ruleFires = inValid && dataInQ.notFull && (isFirst -> hdrMetaInQ.notFull) + ---------------------------------------------------------------------- + isFirst := rdmaPktPipeInData(DS_ISFIRST_C); + ruleFires := (rdmaPktPipeInValid = '1') and (dataInQNotFull = '1') + and ((isFirst = '0') or (hmdInQNotFull = '1')); + + if ruleFires then + rdmaPktPipeInRdEn_i <= '1'; -- rdmaPktPipeIn.deq + dataInQWrEn <= '1'; -- dataInQ.enq(frag) (din wired above) + + if isFirst = '1' then + data := rdmaPktPipeInData(DsDataRange); + transType := data(255 downto 253); + rdmaOpCode := data(252 downto 248); + hasPayload := rdmaOpCodeHasPayload(rdmaOpCode); + headerLen := calcHeaderLen(transType & rdmaOpCode); + hmdInQWrEn <= '1'; -- headerMetaDataInQ.enq(token) + hmdInQDin <= genHeaderMetaData(headerLen, hasPayload); + end if; + end if; + + ---------------------------------------------------------------------- + -- U_Fork : replicate U_HeaderMetaDataInQ head to two consumers, joined. + -- copy[0] → child U_ExtractDS ; copy[1] → U_HeaderMetaDataBuf. + -- Source is dequeued only once BOTH copies have been accepted. + ---------------------------------------------------------------------- + fork0Valid <= hmdInQValid and (not r.forkTaken(0)); + bufWrEn <= (hmdInQValid and (not r.forkTaken(1))) and bufNotFull; + + take0 := (hmdInQValid and (not r.forkTaken(0))) and childHdrMetaRdEn; + take1 := (hmdInQValid and (not r.forkTaken(1))) and bufNotFull; + + newTaken0 := r.forkTaken(0) or take0; + newTaken1 := r.forkTaken(1) or take1; + + if (newTaken0 = '1') and (newTaken1 = '1') then + hmdInQRdEn <= '1'; -- both consumed → deq source + v.forkTaken := (others => '0'); + else + v.forkTaken(0) := newTaken0; + v.forkTaken(1) := newTaken1; + end if; + + -- Synchronous reset (fork join state only) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/Header2DataStream.vhd b/ethernet/RoCEv2/rtl/Header2DataStream.vhd new file mode 100644 index 0000000000..a6ac4c2073 --- /dev/null +++ b/ethernet/RoCEv2/rtl/Header2DataStream.vhd @@ -0,0 +1,346 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Accepts a packed HeaderRDMA word from an upstream pipe (headerPipeIn) +-- and serialises it into at most two 256-bit DataStream flits, writing them +-- into U_HdrDataStreamQ. Simultaneously pushes a 17-bit HeaderMetaData +-- word into U_HdrMetaDataQ. +-- +-- FSM states (mapped from BSV headerValidReg): +-- IDLE_S ('0') — waiting for a new header +-- BUSY_S ('1') — emitting the second flit of a 2-fragment header +-- +-- BSV rules implemented: +-- resetAndClear — no_implicit_conditions; fires every cycle while +-- clearAllI='1'; clears both FIFOs via rst, sets IDLE_S. +-- outputHeader — base guard: !clearAllI AND hdrPipeInValid='1'; +-- IDLE_S handles the three IDLE sub-cases; BUSY_S emits +-- the second (last) flit. +-- +-- Mapping note (OQ-FSM-H2DS-01, see fsm.md §mismatch): +-- mapping.json records one output FIFO and wrong port/state names; this +-- file is authoritative. DataStream width = 290 bits (OQ-FSM-H2DS-02, +-- RESOLVED). HeaderRDMA packing is first-field-at-MSB (OQ-FSM-H2DS-04, +-- RESOLVED). +-- +-- SURF components instantiated: +-- U_HdrDataStreamQ : surf.Fifo +-- DATA_WIDTH_G=290, FWFT, sync, block RAM (2-cycle cold latency, DOB reg) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- U_HdrMetaDataQ : surf.Fifo +-- DATA_WIDTH_G=17, FWFT, sync, distributed RAM (1-cycle cold latency) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- +-- FIFO clear (OQ-FSM-H2DS-03, resolved via OQ-FSM-06 in RESOLVED.md): +-- hdrDataStreamQRst / hdrMetaDataQRst are driven as levels: +-- fifoRst = rst OR clearAllI +-- surf.FifoSync holds logically empty for the entire asserted window; +-- no pulse generator is needed. +-- +-- Scheduling note (fsm.md §scheduling): +-- hdrPipeInValid is required in BOTH IDLE_S and BUSY_S because the BSV +-- source reads headerPipeIn.first unconditionally in the BUSY branch +-- (peek-ahead). The FSM stalls in BUSY_S until the next header arrives. +-- +-- DataStream bit layout (BSV deriving(Bits), first-field-at-MSB): +-- [289:34] data[255:0] (256 bits) +-- [33:2] byteEn[31:0] (32 bits) +-- [1] isFirst +-- [0] isLast +-- +-- HeaderRDMA bit layout (BSV deriving(Bits), first-field-at-MSB): +-- [592:81] headerData[511:0] (512 bits) +-- [80:17] headerByteEn[63:0] (64 bits) +-- [16:10] headerLen[6:0] +-- [9:8] headerFragNum[1:0] +-- [7:2] lastFragValidByteNum[5:0] +-- [1] hasPayload +-- [0] isEmptyHeader +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity Header2DataStream is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (synchronous; fires every cycle while asserted) + clearAllI : in sl; + -- Upstream: packed HeaderRDMA pipe (headerPipeIn) + hdrPipeInValid : in sl; -- headerPipeIn.notEmpty + hdrPipeInData : in slv(592 downto 0); -- headerPipeIn.first + hdrPipeInRdEn : out sl; -- headerPipeIn.deq (asserted on isLast) + -- Downstream: headerDataStream (DataStream, 290 b per beat) + hdrDataStreamValid : out sl; -- headerDataStream.notEmpty + hdrDataStreamDout : out slv(289 downto 0); -- headerDataStream.first + hdrDataStreamRdEn : in sl; -- headerDataStream.deq + -- Downstream: headerMetaData (HeaderMetaData, 17 b, one per header) + hdrMetaDataValid : out sl; -- headerMetaData.notEmpty + hdrMetaDataDout : out slv(16 downto 0); -- headerMetaData.first + hdrMetaDataRdEn : in sl); -- headerMetaData.deq +end entity Header2DataStream; + +architecture rtl of Header2DataStream is + + -- FSM state type (maps BSV headerValidReg: False→IDLE_S, True→BUSY_S) + type StateType is (IDLE_S, BUSY_S); + + type RegType is record + state : StateType; + rdmaHdrData : slv(511 downto 0); -- mkRegU — left-aligned remaining header data + rdmaHdrByEn : slv(63 downto 0); -- mkRegU — left-aligned remaining byte enables + fragCnt : slv(1 downto 0); -- mkRegU — remaining fragment count + end record RegType; + + -- mkRegU fields set to '0' in REG_INIT_C (written before read; no correctness risk) + constant REG_INIT_C : RegType := ( + state => IDLE_S, + rdmaHdrData => (others => '0'), + rdmaHdrByEn => (others => '0'), + fragCnt => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- FIFO control signals (internal; driven by comb process) + signal hdrDataStreamQFull : sl; + signal hdrDataStreamQWrEn : sl; + signal hdrDataStreamQDin : slv(289 downto 0); + signal hdrMetaDataQFull : sl; + signal hdrMetaDataQWrEn : sl; + signal hdrMetaDataQDin : slv(16 downto 0); + + -- FIFO reset lines: level = rst OR clearAllI (see FIFO clear note above) + signal hdrDataStreamQRst : sl; + signal hdrMetaDataQRst : sl; + + -- Internal copy of hdrPipeInRdEn (avoids driving output port from process) + signal hdrPipeInRdEn_i : sl; + + -- Zero-padding constants for the left-shift operation + constant ZERO_256_C : slv(255 downto 0) := (others => '0'); + constant ZERO_32_C : slv(31 downto 0) := (others => '0'); + +begin + + -- FIFO reset: level-sensitive clear (OQ-FSM-H2DS-03 / OQ-FSM-06 RESOLVED) + hdrDataStreamQRst <= rst or clearAllI; + hdrMetaDataQRst <= rst or clearAllI; + hdrPipeInRdEn <= hdrPipeInRdEn_i; + + --------------------------------------------------------------------------- + -- U_HdrDataStreamQ : surf.Fifo + -- Carries DataStream flits to the headerDataStream output interface. + -- DATA_WIDTH_G=290 (256+32+1+1), FWFT, sync, block RAM. + --------------------------------------------------------------------------- + U_HdrDataStreamQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 290, + ADDR_WIDTH_G => 4) + port map ( + rst => hdrDataStreamQRst, + wr_clk => clk, + wr_en => hdrDataStreamQWrEn, + din => hdrDataStreamQDin, + full => hdrDataStreamQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => hdrDataStreamRdEn, + dout => hdrDataStreamDout, + valid => hdrDataStreamValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_HdrMetaDataQ : surf.Fifo + -- Carries HeaderMetaData words to the headerMetaData output interface. + -- DATA_WIDTH_G=17 (7+2+6+1+1), FWFT, sync, distributed RAM. + --------------------------------------------------------------------------- + U_HdrMetaDataQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 17, + ADDR_WIDTH_G => 4) + port map ( + rst => hdrMetaDataQRst, + wr_clk => clk, + wr_en => hdrMetaDataQWrEn, + din => hdrMetaDataQDin, + full => hdrMetaDataQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => hdrMetaDataRdEn, + dout => hdrMetaDataDout, + valid => hdrMetaDataValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, clearAllI, + hdrPipeInValid, hdrPipeInData, + hdrDataStreamQFull, hdrMetaDataQFull) is + variable v : RegType; + begin + v := r; + + -- default Mealy outputs (deasserted; overridden below per transition) + hdrPipeInRdEn_i <= '0'; + hdrDataStreamQWrEn <= '0'; + hdrDataStreamQDin <= (others => '0'); + hdrMetaDataQWrEn <= '0'; + hdrMetaDataQDin <= (others => '0'); + + -- resetAndClear (no_implicit_conditions, fire_when_enabled): + -- fires every cycle while clearAllI='1'; FIFOs cleared via rst pins; + -- stateReg forced to IDLE_S. Mutually exclusive with outputHeader. + if clearAllI = '1' then + v.state := IDLE_S; + + -- outputHeader (conflict_free): + -- base guard = !clearAllI AND hdrPipeInValid='1' + -- hdrPipeInValid required in BOTH states (BSV peek-ahead scheduling; + -- see fsm.md §scheduling note). + elsif hdrPipeInValid = '1' then + + case r.state is + + -- --------------------------------------------------------------- + -- IDLE_S: examine incoming HeaderRDMA word; three sub-cases + -- --------------------------------------------------------------- + when IDLE_S => + + -- Sub-case A: 2-fragment header (fragNum=2), not empty + -- → emit first DataStream flit (isFirst='1', isLast='0'), + -- store second fragment in RegType, advance to BUSY_S. + -- No deq of headerPipeIn yet (more flits to come). + if hdrMetaDataQFull = '0' and hdrDataStreamQFull = '0' + and hdrPipeInData(0) = '0' -- isEmptyHeader=false + and hdrPipeInData(9 downto 8) = "10" -- headerFragNum=2 + then + hdrMetaDataQWrEn <= '1'; + hdrMetaDataQDin <= hdrPipeInData(16 downto 0); + hdrDataStreamQWrEn <= '1'; + -- data[289:34]=hdrData_msb, byteEn[33:2]=hdrByEn_msb, + -- isFirst[1]='1', isLast[0]='0' + hdrDataStreamQDin <= hdrPipeInData(592 downto 337) -- 256 b + & hdrPipeInData(80 downto 49) -- 32 b + & '1' & '0'; -- 2 b + -- Shift headerData/headerByteEn left by DATA_BUS_WIDTH (256 b) + -- using truncate: keep lower half, zero-pad the vacated upper half + v.rdmaHdrData := hdrPipeInData(336 downto 81) & ZERO_256_C; + v.rdmaHdrByEn := hdrPipeInData(48 downto 17) & ZERO_32_C; + v.fragCnt := "01"; -- fragNum(2) - 1 = 1 + v.state := BUSY_S; + -- hdrPipeInRdEn stays '0' + + -- Sub-case B: 1-fragment header (fragNum=1), not empty + -- → emit single DataStream flit (isFirst='1', isLast='1'), + -- deq headerPipeIn, stay in IDLE_S. + elsif hdrMetaDataQFull = '0' and hdrDataStreamQFull = '0' + and hdrPipeInData(0) = '0' -- isEmptyHeader=false + and hdrPipeInData(9 downto 8) = "01" -- headerFragNum=1 + then + hdrMetaDataQWrEn <= '1'; + hdrMetaDataQDin <= hdrPipeInData(16 downto 0); + hdrDataStreamQWrEn <= '1'; + hdrDataStreamQDin <= hdrPipeInData(592 downto 337) + & hdrPipeInData(80 downto 49) + & '1' & '1'; + hdrPipeInRdEn_i <= '1'; + + -- Sub-case C: empty header (isEmptyHeader=1) + -- → push HeaderMetaData only; no DataStream flit; + -- deq headerPipeIn, stay in IDLE_S. + elsif hdrMetaDataQFull = '0' + and hdrPipeInData(0) = '1' -- isEmptyHeader=true + then + hdrMetaDataQWrEn <= '1'; + hdrMetaDataQDin <= hdrPipeInData(16 downto 0); + hdrPipeInRdEn_i <= '1'; + end if; + + -- --------------------------------------------------------------- + -- BUSY_S: emit second (last) DataStream flit from RegType + -- Structural invariant: HEADER_MAX_FRAG_NUM=2 → fragCnt always 1 + -- here, so isLast='1' unconditionally; BUSY_S exits in one cycle. + -- --------------------------------------------------------------- + when BUSY_S => + if hdrDataStreamQFull = '0' then + hdrDataStreamQWrEn <= '1'; + -- data[289:34]=MSB 256b of saved data, + -- byteEn[33:2]=MSB 32b of saved byteEn, + -- isFirst[1]='0', isLast[0]='1' + hdrDataStreamQDin <= r.rdmaHdrData(511 downto 256) + & r.rdmaHdrByEn(63 downto 32) + & '0' & '1'; + hdrPipeInRdEn_i <= '1'; + v.state := IDLE_S; + end if; + + end case; + end if; + + -- Synchronous reset (overrides FSM; matches BSV mkReg(False) for stateReg) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/HeaderGenRDMA.vhd b/ethernet/RoCEv2/rtl/HeaderGenRDMA.vhd new file mode 100644 index 0000000000..a3e2dd8bb7 --- /dev/null +++ b/ethernet/RoCEv2/rtl/HeaderGenRDMA.vhd @@ -0,0 +1,418 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- PURELY COMBINATIONAL (Mealy) datapath — no clock, no reset, no state, no +-- SURF instances. Reproduces +-- genHeaderRDMA( genFirstOrOnlyPktHeader(...) | genMiddleOrLastPktHeader(...) ) +-- for the NON-raw path. Given the WQE-derived header fields and the per-packet +-- control (HeaderGenInfo), it emits the 593-bit packed HeaderRDMA word consumed +-- by pktHeaderQ / Header2DataStream, plus headerValid (the Maybe tag). +-- +-- Packing is first-field-at-MSB; the header is left-aligned in headerData +-- (zeroExtendLSB), canonical order: bth . xrceth? . middle? . tail? +-- middle in {RETH, DETH, AtomicEth}, tail in {LETH, ImmDt, IETH}. +-- +-- Header struct byte widths (Headers.bsv): BTH 12, XRCETH 4, DETH 8, RETH 16, +-- LETH 16, AtomicEth 28, ImmDt 4, IETH 4. +-- +-- HeaderRDMA output bit layout (matches Header2DataStream input [592:0]): +-- [592:81] headerData(512) | [80:17] headerByteEn(64) | [16:10] headerLen(7) | +-- [9:8] headerFragNum(2) | [7:2] lastFragValidByteNum(6) | [1] hasPayload | +-- [0] isEmptyHeader(=0) +-- +-- headerValid='0' means the (opcode,qpType) combination is unsupported (Maybe +-- Invalid); the caller (SendQ.genPktHeader) must deq pendingHeaderQ WITHOUT enq. +-- +-- Assumption (guaranteed by mkSendQ.recvWQE immAsserts, fsm.md): the Maybe fields +-- the packers unwrap (srqn/qkey/swap/comp/immDtOrInvRKey) are Valid whenever the +-- selected arm uses them, so their raw data ports are used directly. +-- +-- OQ-FSM-HGR-01 (NON-BLOCKING): BTH.pkey is dontCareValue in BSV source; emitted +-- as 0. If PKEY is ever populated upstream, add a pkey input port. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity HeaderGenRDMA is + generic ( + TPD_G : time := 1 ns); -- unused (no registers); kept for SURF consistency + port ( + -- Control (from HeaderGenInfo) + isFirstOrOnly : in sl; -- '1' first/only header, '0' middle/last + isOnlyOrLast : in sl; -- isOnlyReqPkt / isLastReqPkt + qpType : in slv(3 downto 0); -- TypeQP + opcode : in slv(3 downto 0); -- WorkReqOpCode + solicited : in sl; + ackReq : in sl; + psn : in slv(23 downto 0); + padCnt : in slv(1 downto 0); + remoteAddr : in slv(63 downto 0); -- RETH.va + wqeRaddr : in slv(63 downto 0); -- AtomicEth.va (wqe.raddr) + dlen : in slv(31 downto 0); -- RETH/LETH.dlen (Length) + hasPayloadIn : in sl; + -- WQE-derived header fields + dqpn : in slv(23 downto 0); -- BTH.dqpn + sqpn : in slv(23 downto 0); -- DETH.sqpn + srqn : in slv(23 downto 0); -- XRCETH.srqn (unwrapped) + qkey : in slv(31 downto 0); -- DETH.qkey (unwrapped) + rkey : in slv(31 downto 0); -- RETH/AtomicEth.rkey + sgeLaddr : in slv(63 downto 0); -- LETH.va + sgeLkey : in slv(31 downto 0); -- LETH.lkey + swapData : in slv(63 downto 0); -- AtomicEth.swap + compData : in slv(63 downto 0); -- AtomicEth.comp + immData : in slv(31 downto 0); -- ImmDt.data / IETH.rkey + -- Outputs + headerValid : out sl; -- Maybe#(PktHeaderInfo) tag + pktHeaderRdma : out slv(592 downto 0)); +end entity HeaderGenRDMA; + +architecture rtl of HeaderGenRDMA is + + -- TypeQP encoding (4 bits, explicit BSV values; DataTypes.bsv:388) + constant QPT_RC_C : slv(3 downto 0) := x"2"; + constant QPT_UC_C : slv(3 downto 0) := x"3"; + constant QPT_UD_C : slv(3 downto 0) := x"4"; + constant QPT_RAW_C : slv(3 downto 0) := x"8"; + constant QPT_XRC_SEND_C : slv(3 downto 0) := x"9"; + constant QPT_XRC_RECV_C : slv(3 downto 0) := x"A"; + + -- WorkReqOpCode encoding (4 bits; DataTypes.bsv:510) + constant WR_RDMA_WRITE_C : slv(3 downto 0) := x"0"; + constant WR_RDMA_WRITE_WITH_IMM_C : slv(3 downto 0) := x"1"; + constant WR_SEND_C : slv(3 downto 0) := x"2"; + constant WR_SEND_WITH_IMM_C : slv(3 downto 0) := x"3"; + constant WR_RDMA_READ_C : slv(3 downto 0) := x"4"; + constant WR_ATOMIC_CMP_AND_SWP_C : slv(3 downto 0) := x"5"; + constant WR_ATOMIC_FETCH_ADD_C : slv(3 downto 0) := x"6"; + constant WR_SEND_WITH_INV_C : slv(3 downto 0) := x"9"; + constant WR_RDMA_READ_RESP_C : slv(3 downto 0) := x"C"; + + -- TransType encoding (3 bits; Headers.bsv:96) + constant TRANS_RC_C : slv(2 downto 0) := "000"; + constant TRANS_UC_C : slv(2 downto 0) := "001"; + constant TRANS_UD_C : slv(2 downto 0) := "011"; + constant TRANS_XRC_C : slv(2 downto 0) := "101"; + + -- RdmaOpCode encoding (5 bits; Headers.bsv:125) [hex value in comment] + constant OP_SEND_FIRST_C : slv(4 downto 0) := "00000"; -- 0x00 + constant OP_SEND_MIDDLE_C : slv(4 downto 0) := "00001"; -- 0x01 + constant OP_SEND_LAST_C : slv(4 downto 0) := "00010"; -- 0x02 + constant OP_SEND_LAST_IMM_C : slv(4 downto 0) := "00011"; -- 0x03 + constant OP_SEND_ONLY_C : slv(4 downto 0) := "00100"; -- 0x04 + constant OP_SEND_ONLY_IMM_C : slv(4 downto 0) := "00101"; -- 0x05 + constant OP_WRITE_FIRST_C : slv(4 downto 0) := "00110"; -- 0x06 + constant OP_WRITE_MIDDLE_C : slv(4 downto 0) := "00111"; -- 0x07 + constant OP_WRITE_LAST_C : slv(4 downto 0) := "01000"; -- 0x08 + constant OP_WRITE_LAST_IMM_C : slv(4 downto 0) := "01001"; -- 0x09 + constant OP_WRITE_ONLY_C : slv(4 downto 0) := "01010"; -- 0x0a + constant OP_WRITE_ONLY_IMM_C : slv(4 downto 0) := "01011"; -- 0x0b + constant OP_READ_REQUEST_C : slv(4 downto 0) := "01100"; -- 0x0c + constant OP_READ_RESP_FIRST_C : slv(4 downto 0) := "01101"; -- 0x0d + constant OP_READ_RESP_LAST_C : slv(4 downto 0) := "01111"; -- 0x0f + constant OP_READ_RESP_ONLY_C : slv(4 downto 0) := "10000"; -- 0x10 + constant OP_COMPARE_SWAP_C : slv(4 downto 0) := "10011"; -- 0x13 + constant OP_FETCH_ADD_C : slv(4 downto 0) := "10100"; -- 0x14 + constant OP_SEND_LAST_INV_C : slv(4 downto 0) := "10110"; -- 0x16 + constant OP_SEND_ONLY_INV_C : slv(4 downto 0) := "10111"; -- 0x17 + + -- Extension-header slot selectors + type MiddleType is (MID_NONE, MID_RETH, MID_DETH, MID_ATOMIC); + type TailType is (TAIL_NONE, TAIL_LETH, TAIL_IMM, TAIL_IETH); + +begin + + comb : process (isFirstOrOnly, isOnlyOrLast, qpType, opcode, solicited, ackReq, + psn, padCnt, remoteAddr, wqeRaddr, dlen, hasPayloadIn, dqpn, + sqpn, srqn, qkey, rkey, sgeLaddr, sgeLkey, swapData, compData, + immData) is + variable trans : slv(2 downto 0); + variable transValid : sl; + variable opc5 : slv(4 downto 0); + variable solicE : sl; + variable ackReqE : sl; + variable bthBits : slv(95 downto 0); + variable rethBits : slv(127 downto 0); + variable lethBits : slv(127 downto 0); + variable atomicBits : slv(223 downto 0); + variable xrcethBits : slv(31 downto 0); + variable dethBits : slv(63 downto 0); + variable immOrIeth : slv(31 downto 0); + variable useXrceth : sl; + variable midSel : MiddleType; + variable tailSel : TailType; + variable armValid : sl; + variable incTail : sl; -- immDt / ieth appended only on only/last + variable hasPl : sl; + variable isReadAtom : sl; + variable slvHeader : slv(511 downto 0); + variable hlen : integer range 0 to 63; + variable hlenSlv : slv(6 downto 0); + variable byteEn : slv(63 downto 0); + variable fragNum : slv(1 downto 0); + variable lastValid : slv(5 downto 0); + variable residue : slv(4 downto 0); + variable pos : integer range 0 to 512; + begin + + ----------------------------------------------------------------------- + -- 1. TransType = qpType2TransType(qpType) (Utils.bsv:741) + ----------------------------------------------------------------------- + transValid := '1'; + case qpType is + when QPT_RC_C => trans := TRANS_RC_C; + when QPT_UC_C => trans := TRANS_UC_C; + when QPT_UD_C => trans := TRANS_UD_C; + when QPT_XRC_SEND_C | QPT_XRC_RECV_C => trans := TRANS_XRC_C; + when others => trans := (others => '0'); transValid := '0'; + end case; + + ----------------------------------------------------------------------- + -- 2. RdmaOpCode = gen{FirstOrOnly|MiddleOrLast}RdmaOpCode (SendQ.bsv:49-74) + ----------------------------------------------------------------------- + opc5 := (others => '0'); + incTail := isOnlyOrLast; + if (isFirstOrOnly = '1') then + case opcode is + when WR_RDMA_WRITE_C => opc5 := ite(isOnlyOrLast = '1', OP_WRITE_ONLY_C, OP_WRITE_FIRST_C); + when WR_RDMA_WRITE_WITH_IMM_C => opc5 := ite(isOnlyOrLast = '1', OP_WRITE_ONLY_IMM_C, OP_WRITE_FIRST_C); + when WR_SEND_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_ONLY_C, OP_SEND_FIRST_C); + when WR_SEND_WITH_IMM_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_ONLY_IMM_C, OP_SEND_FIRST_C); + when WR_SEND_WITH_INV_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_ONLY_INV_C, OP_SEND_FIRST_C); + when WR_RDMA_READ_RESP_C => opc5 := ite(isOnlyOrLast = '1', OP_READ_RESP_ONLY_C, OP_READ_RESP_FIRST_C); + when WR_RDMA_READ_C => opc5 := OP_READ_REQUEST_C; + when WR_ATOMIC_CMP_AND_SWP_C => opc5 := OP_COMPARE_SWAP_C; + when WR_ATOMIC_FETCH_ADD_C => opc5 := OP_FETCH_ADD_C; + when others => opc5 := (others => '0'); + end case; + else + case opcode is + when WR_RDMA_WRITE_C => opc5 := ite(isOnlyOrLast = '1', OP_WRITE_LAST_C, OP_WRITE_MIDDLE_C); + when WR_RDMA_WRITE_WITH_IMM_C => opc5 := ite(isOnlyOrLast = '1', OP_WRITE_LAST_IMM_C, OP_WRITE_MIDDLE_C); + when WR_SEND_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_LAST_C, OP_SEND_MIDDLE_C); + when WR_SEND_WITH_IMM_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_LAST_IMM_C, OP_SEND_MIDDLE_C); + when WR_SEND_WITH_INV_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_LAST_INV_C, OP_SEND_MIDDLE_C); + when WR_RDMA_READ_RESP_C => opc5 := ite(isOnlyOrLast = '1', OP_READ_RESP_LAST_C, OP_READ_RESP_FIRST_C); + when others => opc5 := (others => '0'); + end case; + end if; + + ----------------------------------------------------------------------- + -- 3. BTH assembly (first-field-at-MSB, 96 bits; Headers.bsv:153-168) + -- pkey = dontCareValue -> 0 (OQ-FSM-HGR-01) + ----------------------------------------------------------------------- + solicE := isOnlyOrLast and solicited; + ackReqE := isOnlyOrLast and ackReq; + bthBits := trans -- [95:93] trans + & opc5 -- [92:88] opcode + & solicE -- [87] solicited + & '0' -- [86] migReq + & padCnt -- [85:84] padCnt + & "0000" -- [83:80] tver + & x"0000" -- [79:64] pkey (dontCare -> 0) + & '0' -- [63] fecn + & '0' -- [62] becn + & "000000" -- [61:56] resv6 + & dqpn -- [55:32] dqpn + & ackReqE -- [31] ackReq + & "0000000" -- [30:24] resv7 + & psn; -- [23:0] psn + + ----------------------------------------------------------------------- + -- 4. Extension sub-headers (first-field-at-MSB) + ----------------------------------------------------------------------- + rethBits := remoteAddr & rkey & dlen; -- RETH 128 + lethBits := sgeLaddr & sgeLkey & dlen; -- LETH 128 + atomicBits := wqeRaddr & rkey & swapData & compData; -- Atomic 224 + xrcethBits := x"00" & srqn; -- XRCETH 32 + dethBits := qkey & x"00" & sqpn; -- DETH 64 + immOrIeth := immData; -- ImmDt / IETH 32 + + ----------------------------------------------------------------------- + -- 5. Slot selection per (opcode, qpType) (SendQ.bsv:216-374 / 417-533) + ----------------------------------------------------------------------- + useXrceth := '0'; + midSel := MID_NONE; + tailSel := TAIL_NONE; + armValid := '0'; + isReadAtom := '0'; + + case opcode is + when WR_RDMA_WRITE_C => + case qpType is + when QPT_RC_C | QPT_UC_C => midSel := MID_RETH; armValid := '1'; + when QPT_XRC_SEND_C => useXrceth := '1'; midSel := MID_RETH; armValid := '1'; + when others => null; + end case; + + when WR_RDMA_WRITE_WITH_IMM_C => + case qpType is + when QPT_RC_C | QPT_UC_C => + midSel := MID_RETH; + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when QPT_XRC_SEND_C => + useXrceth := '1'; midSel := MID_RETH; + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when others => null; + end case; + + when WR_SEND_C => + case qpType is + when QPT_RC_C | QPT_UC_C => armValid := '1'; -- bth only + when QPT_UD_C => midSel := MID_DETH; armValid := '1'; + when QPT_XRC_SEND_C => useXrceth := '1'; armValid := '1'; + when others => null; + end case; + + when WR_SEND_WITH_IMM_C => + case qpType is + when QPT_RC_C | QPT_UC_C => + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when QPT_UD_C => + midSel := MID_DETH; tailSel := TAIL_IMM; armValid := '1'; -- UD always only-pkt + when QPT_XRC_SEND_C => + useXrceth := '1'; + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when others => null; + end case; + + when WR_SEND_WITH_INV_C => + case qpType is + when QPT_RC_C => + if (incTail = '1') then tailSel := TAIL_IETH; end if; + armValid := '1'; + when QPT_XRC_SEND_C => + useXrceth := '1'; + if (incTail = '1') then tailSel := TAIL_IETH; end if; + armValid := '1'; + when others => null; + end case; + + when WR_RDMA_READ_C => -- first/only only + if (isFirstOrOnly = '1') then + isReadAtom := '1'; + case qpType is + when QPT_RC_C => midSel := MID_RETH; tailSel := TAIL_LETH; armValid := '1'; + when QPT_XRC_SEND_C => useXrceth := '1'; midSel := MID_RETH; tailSel := TAIL_LETH; armValid := '1'; + when others => null; + end case; + end if; + + when WR_ATOMIC_CMP_AND_SWP_C | WR_ATOMIC_FETCH_ADD_C => -- first/only only + if (isFirstOrOnly = '1') then + isReadAtom := '1'; + case qpType is + when QPT_RC_C => midSel := MID_ATOMIC; armValid := '1'; + when QPT_XRC_SEND_C => useXrceth := '1'; midSel := MID_ATOMIC; armValid := '1'; + when others => null; + end case; + end if; + + when WR_RDMA_READ_RESP_C => + case qpType is + when QPT_RC_C | QPT_XRC_SEND_C | QPT_XRC_RECV_C => + midSel := MID_RETH; armValid := '1'; + when others => null; + end case; + + when others => null; + end case; + + ----------------------------------------------------------------------- + -- 6. Effective hasPayload (SendQ.bsv per-case) + ----------------------------------------------------------------------- + if (isFirstOrOnly = '0') then + hasPl := '1'; -- middle/last always has payload + elsif (isReadAtom = '1') then + hasPl := '0'; -- read/atomic requests carry no payload + else + hasPl := hasPayloadIn; + end if; + + ----------------------------------------------------------------------- + -- 7. Assemble headerData (left-aligned, zeroExtendLSB) + headerLen + ----------------------------------------------------------------------- + slvHeader := (others => '0'); + slvHeader(511 downto 416) := bthBits; + hlen := 12; + pos := 416; + if (useXrceth = '1') then + slvHeader(pos-1 downto pos-32) := xrcethBits; + pos := pos - 32; + hlen := hlen + 4; + end if; + case midSel is + when MID_RETH => + slvHeader(pos-1 downto pos-128) := rethBits; pos := pos - 128; hlen := hlen + 16; + when MID_DETH => + slvHeader(pos-1 downto pos-64) := dethBits; pos := pos - 64; hlen := hlen + 8; + when MID_ATOMIC => + slvHeader(pos-1 downto pos-224) := atomicBits; pos := pos - 224; hlen := hlen + 28; + when MID_NONE => null; + end case; + case tailSel is + when TAIL_LETH => + slvHeader(pos-1 downto pos-128) := lethBits; hlen := hlen + 16; + when TAIL_IMM => + slvHeader(pos-1 downto pos-32) := immOrIeth; hlen := hlen + 4; + when TAIL_IETH => + slvHeader(pos-1 downto pos-32) := immOrIeth; hlen := hlen + 4; + when TAIL_NONE => null; + end case; + hlenSlv := toSlv(hlen, 7); + + ----------------------------------------------------------------------- + -- 8. genHeaderRDMA: byteEn + metaData (Utils.bsv:165-345) + ----------------------------------------------------------------------- + -- byteEn = reverseBits((1< '0'); + end if; + + ----------------------------------------------------------------------- + -- 9. Drive outputs + ----------------------------------------------------------------------- + headerValid <= transValid and armValid; + pktHeaderRdma <= slvHeader & byteEn & hlenSlv & fragNum & lastValid & hasPl & '0'; + + end process comb; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/HeaderGenReqSQ.vhd b/ethernet/RoCEv2/rtl/HeaderGenReqSQ.vhd new file mode 100644 index 0000000000..840e9c944b --- /dev/null +++ b/ethernet/RoCEv2/rtl/HeaderGenReqSQ.vhd @@ -0,0 +1,465 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- PURELY COMBINATIONAL (Mealy) datapath — no clock, no reset, no state, no SURF +-- instances. Reproduces the SQ request-header packers +-- genFirstOrOnlyReqHeader(...) (isFirstOrOnly = '1') +-- genMiddleOrLastReqHeader(...) (isFirstOrOnly = '0') +-- which each return Maybe#(Tuple3#(HeaderData, HeaderByteNum, Bool)). This entity +-- emits that tuple as three ports (headerData/headerByteNum/hasPayload) plus the +-- Maybe tag (headerValid). The caller (ReqGenSq.prepareReqHeaderGen, R8) enqueues +-- {headerData, headerByteNum, hasPayload} into pendingReqHeaderQ when headerValid; +-- the subsequent genHeaderRDMA (R9) turns headerData+headerByteNum into the packed +-- HeaderRDMA (byteEn + metaData) — that step stays in the integrator, matching the +-- BSV structure (this leaf = the two gen*ReqHeader functions ONLY). +-- +-- Packing is first-field-at-MSB; the header is left-aligned in headerData +-- (zeroExtendLSB), canonical order: bth . xrceth? . mid? . tail? +-- mid in {RETH, DETH, AtomicEth}, tail in {ImmDt, IETH}. (NO LETH on the +-- request path — RDMA_READ requests carry RETH only.) +-- +-- Header struct byte widths (Headers.bsv): BTH 12, XRCETH 4, DETH 8, RETH 16, +-- AtomicEth 28, ImmDt 4, IETH 4. HeaderData = 512 b, HeaderByteNum = 7 b. +-- +-- headerValid='0' means the (opcode,qpType) combination is unsupported (Maybe +-- Invalid) — the caller must deq WITHOUT enq (genReqHeader R9 skips the enq). +-- +-- Differences vs the SendQ HeaderGenRDMA leaf (same struct packing, different +-- selection): (1) BTH.solicited = wr.solicited is UNGATED here; (2) BTH.pkey is a +-- real input (cntrlStatus.comm.getPKEY), not dontCare; (3) dqpn = (qpType=UD) ? +-- wr.dqpn : comm.getDQPN; (4) middle/last supports only RC and XRC_SEND (no UC, no +-- UD); (5) RDMA_READ/ATOMIC are first/only-only and carry no payload. +-- +-- Maybe-field assumption (mirrors HeaderGenRDMA / guaranteed by ReqGenSq.recvWorkReq +-- immAsserts): srqn/qkey/swap/comp/immDt/rkey2Inv/dqpn(UD) are Valid whenever the +-- selected arm uses them, so their raw data ports are consumed directly. +-- +-- OQ-EMIT-HGRSQ-01 (NON-BLOCKING): genMiddleOrLastReqHeader has NO IBV_QPT_UC arm +-- for RDMA_WRITE (BSV source), so a multi-packet UC RDMA_WRITE middle/last yields +-- headerValid='0'. Reproduced faithfully; flagged in case it is a source quirk. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity HeaderGenReqSQ is + generic ( + TPD_G : time := 1 ns); -- unused (no registers); kept for SURF consistency + port ( + -- Per-packet control (from ReqPktHeaderInfo / countReqPkt) + isFirstOrOnly : in sl; -- '1' genFirstOrOnlyReqHeader, '0' genMiddleOrLastReqHeader + isOnlyOrLast : in sl; -- isOnlyReqPkt (first) / isLastReqPkt (middle/last) + psn : in slv(23 downto 0); -- BTH.psn (curPSN) + -- cntrlStatus fields + qpType : in slv(3 downto 0); -- getTypeQP + pkey : in slv(15 downto 0); -- comm.getPKEY -> BTH.pkey + sigAll : in sl; -- comm.getSigAll + commDqpn : in slv(23 downto 0); -- comm.getDQPN (RC/UC/XRC dest QPN) + sqpn : in slv(23 downto 0); -- comm.getSQPN -> DETH.sqpn + -- WorkReq-derived fields + opcode : in slv(3 downto 0); -- WorkReqOpCode + solicited : in sl; -- wr.solicited (ungated) + sendSignaled : in sl; -- wr.flags contains IBV_SEND_SIGNALED (workReqHasAckReq) + len : in slv(31 downto 0); -- wr.len (Length) -> RETH.dlen, calcPadCnt, hasPayload + raddr : in slv(63 downto 0); -- wr.raddr -> RETH.va / AtomicEth.va + rkey : in slv(31 downto 0); -- wr.rkey -> RETH.rkey / AtomicEth.rkey + wrDqpn : in slv(23 downto 0); -- wr.dqpn unwrapped (UD dest QPN) + srqn : in slv(23 downto 0); -- wr.srqn unwrapped -> XRCETH.srqn + qkey : in slv(31 downto 0); -- wr.qkey unwrapped -> DETH.qkey + swapData : in slv(63 downto 0); -- wr.swap unwrapped -> AtomicEth.swap + compData : in slv(63 downto 0); -- wr.comp unwrapped -> AtomicEth.comp + immDtData : in slv(31 downto 0); -- wr.immDt unwrapped -> ImmDt.data + invRkey : in slv(31 downto 0); -- wr.rkey2Inv unwrapped -> IETH.rkey + -- Outputs (the Maybe#(Tuple3#(HeaderData, HeaderByteNum, Bool))) + headerValid : out sl; -- Maybe tag + headerData : out slv(511 downto 0); -- HeaderData (left-aligned) + headerByteNum : out slv(6 downto 0); -- HeaderByteNum (byte length) + hasPayload : out sl); -- the tuple's Bool +end entity HeaderGenReqSQ; + +architecture rtl of HeaderGenReqSQ is + + -- TypeQP encoding (4 bits; DataTypes.bsv:388) + constant QPT_RC_C : slv(3 downto 0) := x"2"; + constant QPT_UC_C : slv(3 downto 0) := x"3"; + constant QPT_UD_C : slv(3 downto 0) := x"4"; + constant QPT_XRC_SEND_C : slv(3 downto 0) := x"9"; + constant QPT_XRC_RECV_C : slv(3 downto 0) := x"A"; + + -- WorkReqOpCode encoding (4 bits; DataTypes.bsv:490-510) + constant WR_RDMA_WRITE_C : slv(3 downto 0) := x"0"; + constant WR_RDMA_WRITE_WITH_IMM_C : slv(3 downto 0) := x"1"; + constant WR_SEND_C : slv(3 downto 0) := x"2"; + constant WR_SEND_WITH_IMM_C : slv(3 downto 0) := x"3"; + constant WR_RDMA_READ_C : slv(3 downto 0) := x"4"; + constant WR_ATOMIC_CMP_AND_SWP_C : slv(3 downto 0) := x"5"; + constant WR_ATOMIC_FETCH_ADD_C : slv(3 downto 0) := x"6"; + constant WR_SEND_WITH_INV_C : slv(3 downto 0) := x"9"; + + -- TransType encoding (3 bits; Headers.bsv:96) + constant TRANS_RC_C : slv(2 downto 0) := "000"; + constant TRANS_UC_C : slv(2 downto 0) := "001"; + constant TRANS_UD_C : slv(2 downto 0) := "011"; + constant TRANS_XRC_C : slv(2 downto 0) := "101"; + + -- RdmaOpCode encoding (5 bits; Headers.bsv:125) + constant OP_SEND_FIRST_C : slv(4 downto 0) := "00000"; -- 0x00 + constant OP_SEND_MIDDLE_C : slv(4 downto 0) := "00001"; -- 0x01 + constant OP_SEND_LAST_C : slv(4 downto 0) := "00010"; -- 0x02 + constant OP_SEND_LAST_IMM_C : slv(4 downto 0) := "00011"; -- 0x03 + constant OP_SEND_ONLY_C : slv(4 downto 0) := "00100"; -- 0x04 + constant OP_SEND_ONLY_IMM_C : slv(4 downto 0) := "00101"; -- 0x05 + constant OP_WRITE_FIRST_C : slv(4 downto 0) := "00110"; -- 0x06 + constant OP_WRITE_MIDDLE_C : slv(4 downto 0) := "00111"; -- 0x07 + constant OP_WRITE_LAST_C : slv(4 downto 0) := "01000"; -- 0x08 + constant OP_WRITE_LAST_IMM_C : slv(4 downto 0) := "01001"; -- 0x09 + constant OP_WRITE_ONLY_C : slv(4 downto 0) := "01010"; -- 0x0a + constant OP_WRITE_ONLY_IMM_C : slv(4 downto 0) := "01011"; -- 0x0b + constant OP_READ_REQUEST_C : slv(4 downto 0) := "01100"; -- 0x0c + constant OP_COMPARE_SWAP_C : slv(4 downto 0) := "10011"; -- 0x13 + constant OP_FETCH_ADD_C : slv(4 downto 0) := "10100"; -- 0x14 + constant OP_SEND_LAST_INV_C : slv(4 downto 0) := "10110"; -- 0x16 + constant OP_SEND_ONLY_INV_C : slv(4 downto 0) := "10111"; -- 0x17 + + -- Extension-header slot selectors (request path: no LETH) + type MiddleType is (MID_NONE, MID_RETH, MID_DETH, MID_ATOMIC); + type TailType is (TAIL_NONE, TAIL_IMM, TAIL_IETH); + +begin + + comb : process (isFirstOrOnly, isOnlyOrLast, psn, qpType, pkey, sigAll, + commDqpn, sqpn, opcode, solicited, sendSignaled, len, raddr, + rkey, wrDqpn, srqn, qkey, swapData, compData, immDtData, invRkey) is + variable trans : slv(2 downto 0); + variable transValid : sl; + variable opc5 : slv(4 downto 0); + variable opcValid : sl; + variable dqpnSel : slv(23 downto 0); + variable isReadAtom : sl; + variable lenNonZero : sl; + variable incTail : sl; + variable padRaw : unsigned(3 downto 0); + variable padCnt : slv(1 downto 0); + variable padGate : sl; + variable padEff : slv(1 downto 0); + variable ackReq : sl; + variable bthBits : slv(95 downto 0); + variable rethBits : slv(127 downto 0); + variable atomicBits : slv(223 downto 0); + variable xrcethBits : slv(31 downto 0); + variable dethBits : slv(63 downto 0); + variable immBits : slv(31 downto 0); + variable iethBits : slv(31 downto 0); + variable useXrceth : sl; + variable midSel : MiddleType; + variable tailSel : TailType; + variable armValid : sl; + variable hasPl : sl; + variable slvHeader : slv(511 downto 0); + variable hlen : integer range 0 to 63; + variable pos : integer range 0 to 512; + begin + + ----------------------------------------------------------------------- + -- 1. TransType = qpType2TransType(qpType) (Utils.bsv:741) + ----------------------------------------------------------------------- + transValid := '1'; + case qpType is + when QPT_RC_C => trans := TRANS_RC_C; + when QPT_UC_C => trans := TRANS_UC_C; + when QPT_UD_C => trans := TRANS_UD_C; + when QPT_XRC_SEND_C | QPT_XRC_RECV_C => trans := TRANS_XRC_C; + when others => trans := (others => '0'); transValid := '0'; + end case; + + ----------------------------------------------------------------------- + -- 2. RdmaOpCode = gen{FirstOrOnly|MiddleOrLast}ReqRdmaOpCode (ReqGenSQ.bsv:24-47) + ----------------------------------------------------------------------- + opc5 := (others => '0'); + opcValid := '1'; + if (isFirstOrOnly = '1') then + case opcode is + when WR_RDMA_WRITE_C => opc5 := ite(isOnlyOrLast = '1', OP_WRITE_ONLY_C, OP_WRITE_FIRST_C); + when WR_RDMA_WRITE_WITH_IMM_C => opc5 := ite(isOnlyOrLast = '1', OP_WRITE_ONLY_IMM_C, OP_WRITE_FIRST_C); + when WR_SEND_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_ONLY_C, OP_SEND_FIRST_C); + when WR_SEND_WITH_IMM_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_ONLY_IMM_C, OP_SEND_FIRST_C); + when WR_SEND_WITH_INV_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_ONLY_INV_C, OP_SEND_FIRST_C); + when WR_RDMA_READ_C => opc5 := OP_READ_REQUEST_C; + when WR_ATOMIC_CMP_AND_SWP_C => opc5 := OP_COMPARE_SWAP_C; + when WR_ATOMIC_FETCH_ADD_C => opc5 := OP_FETCH_ADD_C; + when others => opc5 := (others => '0'); opcValid := '0'; + end case; + else + case opcode is + when WR_RDMA_WRITE_C => opc5 := ite(isOnlyOrLast = '1', OP_WRITE_LAST_C, OP_WRITE_MIDDLE_C); + when WR_RDMA_WRITE_WITH_IMM_C => opc5 := ite(isOnlyOrLast = '1', OP_WRITE_LAST_IMM_C, OP_WRITE_MIDDLE_C); + when WR_SEND_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_LAST_C, OP_SEND_MIDDLE_C); + when WR_SEND_WITH_IMM_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_LAST_IMM_C, OP_SEND_MIDDLE_C); + when WR_SEND_WITH_INV_C => opc5 := ite(isOnlyOrLast = '1', OP_SEND_LAST_INV_C, OP_SEND_MIDDLE_C); + when others => opc5 := (others => '0'); opcValid := '0'; + end case; + end if; + + ----------------------------------------------------------------------- + -- 3. dqpn = getMaybeDestQpnSQ : UD -> wr.dqpn ; RC/UC/XRC_SEND -> comm.getDQPN + ----------------------------------------------------------------------- + dqpnSel := ite(qpType = QPT_UD_C, wrDqpn, commDqpn); + + -- isReadOrAtomicWorkReq(opcode) ; workReqHasPayload uses !isZero(len) + case opcode is + when WR_RDMA_READ_C | WR_ATOMIC_CMP_AND_SWP_C | WR_ATOMIC_FETCH_ADD_C => + isReadAtom := '1'; + when others => + isReadAtom := '0'; + end case; + lenNonZero := toSl(unsigned(len) /= 0); + incTail := isOnlyOrLast; + + ----------------------------------------------------------------------- + -- 4. padCnt = calcPadCnt(len) = (1< isOnly && !readAtomic ; middle/last -> isLast + ----------------------------------------------------------------------- + padRaw := to_unsigned(4, 4) - resize(unsigned(len(1 downto 0)), 4); + padCnt := slv(padRaw(1 downto 0)); + if (isFirstOrOnly = '1') then + padGate := isOnlyOrLast and (not isReadAtom); + else + padGate := isOnlyOrLast; + end if; + padEff := ite(padGate = '1', padCnt, "00"); + + -- ackReq = getSigAll || (isOnlyOrLast && workReqRequireAck) + -- workReqRequireAck = workReqHasAckReq(signaled) || isReadOrAtomic + ackReq := sigAll or (isOnlyOrLast and (sendSignaled or isReadAtom)); + + ----------------------------------------------------------------------- + -- 5. BTH assembly (first-field-at-MSB, 96 bits; Headers.bsv:153-168) + -- solicited UNGATED; pkey is a real input. + ----------------------------------------------------------------------- + bthBits := trans -- [95:93] trans + & opc5 -- [92:88] opcode + & solicited -- [87] solicited (ungated) + & '0' -- [86] migReq + & padEff -- [85:84] padCnt + & "0000" -- [83:80] tver + & pkey -- [79:64] pkey + & '0' -- [63] fecn + & '0' -- [62] becn + & "000000" -- [61:56] resv6 + & dqpnSel -- [55:32] dqpn + & ackReq -- [31] ackReq + & "0000000" -- [30:24] resv7 + & psn; -- [23:0] psn + + ----------------------------------------------------------------------- + -- 6. Extension sub-headers (first-field-at-MSB) + ----------------------------------------------------------------------- + rethBits := raddr & rkey & len; -- RETH 128 (va,rkey,dlen) + atomicBits := raddr & rkey & swapData & compData; -- Atomic 224 (va,rkey,swap,comp) + xrcethBits := x"00" & srqn; -- XRCETH 32 (rsvd,srqn) + dethBits := qkey & x"00" & sqpn; -- DETH 64 (qkey,rsvd,sqpn) + immBits := immDtData; -- ImmDt 32 (data) + iethBits := invRkey; -- IETH 32 (rkey) + + ----------------------------------------------------------------------- + -- 7. Slot selection per (isFirstOrOnly, opcode, qpType) (ReqGenSQ.bsv:159-306 / 347-448) + ----------------------------------------------------------------------- + useXrceth := '0'; + midSel := MID_NONE; + tailSel := TAIL_NONE; + armValid := '0'; + + if (isFirstOrOnly = '1') then + -- genFirstOrOnlyReqHeader + case opcode is + when WR_RDMA_WRITE_C => + case qpType is + when QPT_RC_C | QPT_UC_C => midSel := MID_RETH; armValid := '1'; + when QPT_XRC_SEND_C => useXrceth := '1'; midSel := MID_RETH; armValid := '1'; + when others => null; + end case; + + when WR_RDMA_WRITE_WITH_IMM_C => + case qpType is + when QPT_RC_C | QPT_UC_C => + midSel := MID_RETH; + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when QPT_XRC_SEND_C => + useXrceth := '1'; midSel := MID_RETH; + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when others => null; + end case; + + when WR_SEND_C => + case qpType is + when QPT_RC_C | QPT_UC_C => armValid := '1'; -- bth only + when QPT_UD_C => midSel := MID_DETH; armValid := '1'; + when QPT_XRC_SEND_C => useXrceth := '1'; armValid := '1'; + when others => null; + end case; + + when WR_SEND_WITH_IMM_C => + case qpType is + when QPT_RC_C | QPT_UC_C => + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when QPT_UD_C => + midSel := MID_DETH; tailSel := TAIL_IMM; armValid := '1'; -- UD always only + when QPT_XRC_SEND_C => + useXrceth := '1'; + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when others => null; + end case; + + when WR_SEND_WITH_INV_C => + case qpType is + when QPT_RC_C => + if (incTail = '1') then tailSel := TAIL_IETH; end if; + armValid := '1'; + when QPT_XRC_SEND_C => + useXrceth := '1'; + if (incTail = '1') then tailSel := TAIL_IETH; end if; + armValid := '1'; + when others => null; + end case; + + when WR_RDMA_READ_C => + case qpType is + when QPT_RC_C => midSel := MID_RETH; armValid := '1'; + when QPT_XRC_SEND_C => useXrceth := '1'; midSel := MID_RETH; armValid := '1'; + when others => null; + end case; + + when WR_ATOMIC_CMP_AND_SWP_C | WR_ATOMIC_FETCH_ADD_C => + case qpType is + when QPT_RC_C => midSel := MID_ATOMIC; armValid := '1'; + when QPT_XRC_SEND_C => useXrceth := '1'; midSel := MID_ATOMIC; armValid := '1'; + when others => null; + end case; + + when others => null; + end case; + + else + -- genMiddleOrLastReqHeader (RC / XRC_SEND only; no UC, no UD; hasPayload=True) + case opcode is + when WR_RDMA_WRITE_C => + case qpType is + when QPT_RC_C => armValid := '1'; -- bth only + when QPT_XRC_SEND_C => useXrceth := '1'; armValid := '1'; + when others => null; + end case; + + when WR_RDMA_WRITE_WITH_IMM_C => + case qpType is + when QPT_RC_C => + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when QPT_XRC_SEND_C => + useXrceth := '1'; + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when others => null; + end case; + + when WR_SEND_C => + case qpType is + when QPT_RC_C => armValid := '1'; + when QPT_XRC_SEND_C => useXrceth := '1'; armValid := '1'; + when others => null; + end case; + + when WR_SEND_WITH_IMM_C => + case qpType is + when QPT_RC_C => + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when QPT_XRC_SEND_C => + useXrceth := '1'; + if (incTail = '1') then tailSel := TAIL_IMM; end if; + armValid := '1'; + when others => null; + end case; + + when WR_SEND_WITH_INV_C => + case qpType is + when QPT_RC_C => + if (incTail = '1') then tailSel := TAIL_IETH; end if; + armValid := '1'; + when QPT_XRC_SEND_C => + useXrceth := '1'; + if (incTail = '1') then tailSel := TAIL_IETH; end if; + armValid := '1'; + when others => null; + end case; + + when others => null; + end case; + end if; + + ----------------------------------------------------------------------- + -- 8. hasPayload : middle/last -> True ; first/only -> workReqHasPayload + -- (= !(isZero(len) || isReadOrAtomic)); read/atomic arms -> False + ----------------------------------------------------------------------- + if (isFirstOrOnly = '0') then + hasPl := '1'; + else + hasPl := (not isReadAtom) and lenNonZero; + end if; + + ----------------------------------------------------------------------- + -- 9. Assemble headerData (left-aligned, zeroExtendLSB) + headerByteNum + ----------------------------------------------------------------------- + slvHeader := (others => '0'); + slvHeader(511 downto 416) := bthBits; + hlen := 12; + pos := 416; + if (useXrceth = '1') then + slvHeader(pos-1 downto pos-32) := xrcethBits; + pos := pos - 32; + hlen := hlen + 4; + end if; + case midSel is + when MID_RETH => + slvHeader(pos-1 downto pos-128) := rethBits; pos := pos - 128; hlen := hlen + 16; + when MID_DETH => + slvHeader(pos-1 downto pos-64) := dethBits; pos := pos - 64; hlen := hlen + 8; + when MID_ATOMIC => + slvHeader(pos-1 downto pos-224) := atomicBits; pos := pos - 224; hlen := hlen + 28; + when MID_NONE => null; + end case; + case tailSel is + when TAIL_IMM => + slvHeader(pos-1 downto pos-32) := immBits; hlen := hlen + 4; + when TAIL_IETH => + slvHeader(pos-1 downto pos-32) := iethBits; hlen := hlen + 4; + when TAIL_NONE => null; + end case; + + ----------------------------------------------------------------------- + -- 10. Drive outputs + ----------------------------------------------------------------------- + headerValid <= transValid and opcValid and armValid; + headerData <= slvHeader; + headerByteNum <= toSlv(hlen, 7); + hasPayload <= hasPl; + + end process comb; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/InputRdmaPktBufAndHeaderValidation.vhd b/ethernet/RoCEv2/rtl/InputRdmaPktBufAndHeaderValidation.vhd new file mode 100644 index 0000000000..8c7103f734 --- /dev/null +++ b/ethernet/RoCEv2/rtl/InputRdmaPktBufAndHeaderValidation.vhd @@ -0,0 +1,1682 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- 12-stage concurrent dataflow pipeline. Each BSV rule is one stage; stages +-- are joined by FIFO pairs — one rdmaHeader*Q carrying the per-packet header +-- tuple (advanced once per packet, on isFirst/isLast), one payload*Q carrying +-- each DataStream fragment (advanced once per fragment). All 12 stage rules +-- are BSV `conflict_free`: emitted as independent `if (guard) then ...` blocks +-- in the comb process — NO elsif precedence between stages. Every stage's +-- guard is "input FIFO(s) notEmpty AND output FIFO(s) notFull" (conditional +-- FIFO writes contribute their notFull only on the path that writes them — +-- BSV conditional implicit conditions). +-- +-- Genuine sequential control (only two pieces): +-- 1. pktBufState (2-state FSM, PRE_CHECK_FRAG_S / DISCARD_FRAG_S) — +-- owned by preCheckHeader (→ DISCARD) and discardInvalidFrag (→ PRE_CHECK); +-- drains the payload fragments of a packet whose header failed pre-check. +-- 2. Per-packet accumulator regs (isValidPkt, bthPadCnt, pktFragNum, pktLen, +-- pktValid): set on isFirst, carried across mid frags, consumed on isLast. +-- All BSV mkRegU (no reset) — given defined REG_INIT_C=0 here (re-armed on +-- each packet's isFirst fragment; see "Reset behaviour" below). +-- +-- RESOLVED open questions applied: +-- - OQ-FSM-IRPB-01: Stage-1 inventory / Stage-2 mapping.json rows for this +-- entity describe a DIFFERENT module (wrong rules/FIFOs/state/children). +-- The .fsm.md (derived from BSV source, authoritative per CLAUDE.md) is the +-- sole basis for this emit. mapping.json was NOT consulted for structure. +-- - OQ-FSM-IRPB-02 (user-confirmed 2026-07-01; REVISED after Stage-5 TC-08): +-- recvPktFrag and discardInvalidFrag both deq the single payloadPipeIn in +-- BSV under `conflict_free`. The first emit gated recvPktFrag on +-- PRE_CHECK_FRAG_S; that RACED at the PRE_CHECK→DISCARD boundary — on the +-- cycle preCheckHeader set DISCARD, r.pktBufState was still PRE_CHECK, so +-- recvPktFrag also fired and pulled the fragment after isFirst into +-- payloadRecvQ before the gate engaged, desynchronizing the header/payload +-- queues and DROPPING valid packets that followed a discarded multi-frag +-- packet (Stage-5 TC-08 fail). FIX: recvPktFrag is the SOLE payloadPipeIn +-- consumer and ALWAYS runs (matches the fsm.md "recvPktFrag keeps +-- running"); the invalid-fragment drain is moved off payloadPipeIn onto +-- payloadRecvQ, so discardInvalidFrag drains payloadRecvQ (downstream of +-- recvPktFrag) while in DISCARD_FRAG_S. No two rules ever deq +-- payloadPipeIn → the race is eliminated and every fragment of an invalid +-- multi-fragment packet is dropped in order (f0 by preCheckHeader, the +-- rest by discardInvalidFrag), with subsequent packets processed cleanly. +-- - OQ-FSM-IRPB-03: qpMetaData (MetaDataQPs) combinational lookups modelled +-- as explicit request/response ports (CntrlQp method-explosion precedent): +-- getPD(dqpn) → getPdQpn out; getPdMaybeValid + getPdHandler in +-- getQueuePairByQPN(dqpn)→ getQpQpn out; sq*/rq* CntrlStatus fields in +-- (only the subset validateHeader + the pmtu read touch). Request qpns are +-- driven combinationally from the pipeline FIFO heads; the provider +-- mkMetaDataQPs / parent TransportLayer must match this contract at emit. +-- - OQ-FSM-H2DS-02: DataStream = 290 bits. OQ-FSM-H2DS-04: BSV deriving(Bits) +-- is first-field-at-MSB (all struct/tuple slicing below follows it). +-- +-- Widths traced (Headers.bsv / DataTypes.bsv / Settings.bsv): +-- HeaderRDMA 593, DataStream 290, BTH 96, AETH 32, DETH 64, XRCETH 32, +-- QPN/PSN 24, QKEY/HandlerPD 32, PAD 2, PktFragNum 8, PktLen 13, +-- ByteEnBitNum 6, TransType 3, RdmaOpCode 5, PMTU 3, TypeQP 4, +-- IndexQP log2(MAX_QP_G) (getIndexQP = truncateLSB(qpn): top log2(MAX_QP_G) +-- bits of the 24-bit QPN, i.e. qpn(23 downto 24-log2(MAX_QP_G)); +-- 2 bits at the default MAX_QP_G=4), PktVeriStatus 1. +-- RdmaPktMetaData 649, HeaderValidateInfo 94, ValidHeaderInfo 65, +-- PktLenCheckInfo 710. +-- +-- Bit layouts (first-field-at-MSB): +-- DataStream(290) : [289:34]data [33:2]byteEn [1]isFirst [0]isLast +-- HeaderRDMA(593) : [592:81]headerData(512) [80:17]headerByteEn(64) +-- [16:10]headerLen [9:8]headerFragNum +-- [7:2]lastFragValidByteNum [1]hasPayload [0]isEmptyHeader +-- BTH(96) : [95:93]trans [92:88]opcode [87]solicited [86]migReq +-- [85:84]padCnt [83:80]tver [79:64]pkey [63]fecn [62]becn +-- [61:56]resv6 [55:32]dqpn [31]ackReq [30:24]resv7 [23:0]psn +-- (bth = headerData top 96 = rdmaHeader[592:497]) +-- AETH(32) rel. : [31]rsvd [30:29]code [28:24]value [23:0]msn +-- (aeth = headerData[415:384] = rdmaHeader[496:465]; +-- aethCode = rdmaHeader[495:494], aethValue = rdmaHeader[493:489]) +-- DETH.qkey = rdmaHeader[496:465] XRCETH.srqn = rdmaHeader[488:465] +-- +-- SURF components instantiated (all surf.Fifo, FWFT + sync + RST_POLARITY_G='1', +-- RST_ASYNC_G=false — source surf/base/fifo/rtl/Fifo.vhd): +-- 18 internal scalar pipeline FIFOs (U_RdmaHeaderRecvQ … U_PayloadOutputQ), +-- 5 output FIFO vectors x MAX_QP_G (U_CnpOutVec, U_ReqPayloadOutVec, +-- U_ReqPktMetaDataOutVec, U_RespPayloadOutVec, U_RespPktMetaDataOutVec), +-- U_PayloadPipeIn (BSV mkBuffer = mkPipelineFIFOF, 1-deep skid on the payload +-- input; precedent ExtractHeaderFromRdmaPktPipeOut U_HeaderMetaDataBuf). +-- Child entity (NOT SURF): +-- U_RdmaHeaderPipeOut : entity surf.DataStream2Header +-- (BSV mkDataStream2Header) — re-accumulates HeaderRDMA per packet from the +-- header DataStream + HeaderMetaData input pipes. +-- +-- Reset behaviour: pktBufState → PRE_CHECK_FRAG_S (BSV mkReg). Accumulators are +-- BSV mkRegU (no reset) — set to 0 in REG_INIT_C; functionally re-armed on each +-- packet's isFirst fragment. All surf.Fifo reset via rst (empty). +-- +-- NOTE: emitting does not prove equivalence. This entity MUST be simulated +-- (Stage 5) before it is trusted. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity InputRdmaPktBufAndHeaderValidation is + generic ( + TPD_G : time := 1 ns; + MAX_QP_G : positive := 4; -- any power of 2, >= 2 (IndexQP = log2(MAX_QP_G) bits) + EN_TX_G : boolean := true; -- false = no requester: skip resp-stream output FIFOs + EN_RX_G : boolean := true); -- false = no responder: skip req-stream output FIFOs + -- (skipped direction: notFull tied '1' => packets drop here) + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + + -- Input: payload DataStream pipe (pipeIn.payload) → U_PayloadPipeIn buffer + payloadPipeInValid : in sl; + payloadPipeInData : in slv(289 downto 0); + payloadPipeInRdEn : out sl; + + -- Input: header DataStream pipe (pipeIn.headerAndMetaData.headerDataStream) + -- → child U_RdmaHeaderPipeOut.dataPipeIn + headerDataStreamValid : in sl; + headerDataStreamData : in slv(289 downto 0); + headerDataStreamRdEn : out sl; + + -- Input: header metadata pipe (pipeIn.headerAndMetaData.headerMetaData) + -- → child U_RdmaHeaderPipeOut.hdrMetaDataPipeIn + headerMetaDataValid : in sl; + headerMetaDataData : in slv(16 downto 0); + headerMetaDataRdEn : out sl; + + -- qpMetaData combinational lookup: getPD(dqpn) (prepareValidation) + getPdQpn : out slv(23 downto 0); + getPdMaybeValid : in sl; + getPdHandler : in slv(31 downto 0); + + -- qpMetaData combinational lookup: getQueuePairByQPN(dqpn) (checkMetaDataQP) + getQpQpn : out slv(23 downto 0); + sqTypeQP : in slv(3 downto 0); + sqIsERR : in sl; + sqIsRTS : in sl; + sqIsNonErr : in sl; + sqQKEY : in slv(31 downto 0); + sqPMTU : in slv(2 downto 0); + rqTypeQP : in slv(3 downto 0); + rqIsERR : in sl; + rqIsRTS : in sl; + rqIsNonErr : in sl; + rqQKEY : in slv(31 downto 0); + + -- Output vectors (x MAX_QP_G), flattened. Each PipeOut: Valid out/Dout out/RdEn in + reqPktMetaDataValid : out slv(MAX_QP_G-1 downto 0); + reqPktMetaDataDout : out slv(MAX_QP_G*649-1 downto 0); + reqPktMetaDataRdEn : in slv(MAX_QP_G-1 downto 0); + reqPayloadValid : out slv(MAX_QP_G-1 downto 0); + reqPayloadDout : out slv(MAX_QP_G*290-1 downto 0); + reqPayloadRdEn : in slv(MAX_QP_G-1 downto 0); + respPktMetaDataValid : out slv(MAX_QP_G-1 downto 0); + respPktMetaDataDout : out slv(MAX_QP_G*649-1 downto 0); + respPktMetaDataRdEn : in slv(MAX_QP_G-1 downto 0); + respPayloadValid : out slv(MAX_QP_G-1 downto 0); + respPayloadDout : out slv(MAX_QP_G*290-1 downto 0); + respPayloadRdEn : in slv(MAX_QP_G-1 downto 0); + cnpValid : out slv(MAX_QP_G-1 downto 0); + cnpDout : out slv(MAX_QP_G*96-1 downto 0); + cnpRdEn : in slv(MAX_QP_G-1 downto 0)); +end entity InputRdmaPktBufAndHeaderValidation; + +architecture rtl of InputRdmaPktBufAndHeaderValidation is + + --------------------------------------------------------------------------- + -- Width constants + --------------------------------------------------------------------------- + constant HDR_W_C : integer := 593; -- HeaderRDMA + constant DS_W_C : integer := 290; -- DataStream + constant BTH_W_C : integer := 96; -- BTH + constant HVI_W_C : integer := 94; -- HeaderValidateInfo + constant VHI_W_C : integer := 65; -- ValidHeaderInfo + constant PLCI_W_C : integer := 710; -- PktLenCheckInfo + constant META_W_C : integer := 649; -- RdmaPktMetaData + constant ADDR_W_C : integer := 4; -- FIFO depth 2**4 = 16 (mkFIFOF skid) + constant QP_IDX_W_C : positive := log2(MAX_QP_G); -- IndexQP = TLog#(MAX_QP) (2 at MAX_QP_G=4) + constant BYTEEN_ONES_C : slv(31 downto 0) := (others => '1'); -- isAllOnesR(byteEn) + + -- Tuple / element widths + constant RECV_W_C : integer := HDR_W_C + BTH_W_C + 3; -- 692 rdmaHeaderRecvQ + constant PRECHK_W_C : integer := HDR_W_C + BTH_W_C; -- 689 rdmaHeaderPreCheckQ + constant VALID_W_C : integer := HDR_W_C + BTH_W_C + HVI_W_C; -- 783 rdmaHeaderValidationQ + constant FILT_W_C : integer := HDR_W_C + BTH_W_C + VHI_W_C; -- 754 filter/fragLen/pktLenCalc header Qs + constant PLC_W_C : integer := DS_W_C + 6 + 6 + 2; -- 304 payloadPktLenCalcQ + constant PCHK4_W_C : integer := PLCI_W_C + 3; -- 713 rdmaHeaderPktLenCheckQ + constant PL3_W_C : integer := DS_W_C + QP_IDX_W_C + 1; -- 293 @MAX_QP_G=4; payload {frag,qpIndex,isRespPkt} + constant HDROUT_W_C : integer := META_W_C + QP_IDX_W_C + 1; -- 652 @MAX_QP_G=4; rdmaHeaderOutputQ {meta,qpIndex,isRespPkt} + + --------------------------------------------------------------------------- + -- RdmaOpCode (5-bit) constants + --------------------------------------------------------------------------- + constant SEND_FIRST_C : slv(4 downto 0) := "00000"; + constant SEND_MIDDLE_C : slv(4 downto 0) := "00001"; + constant SEND_LAST_C : slv(4 downto 0) := "00010"; + constant SEND_LAST_WITH_IMMEDIATE_C : slv(4 downto 0) := "00011"; + constant SEND_ONLY_C : slv(4 downto 0) := "00100"; + constant SEND_ONLY_WITH_IMMEDIATE_C : slv(4 downto 0) := "00101"; + constant RDMA_WRITE_FIRST_C : slv(4 downto 0) := "00110"; + constant RDMA_WRITE_MIDDLE_C : slv(4 downto 0) := "00111"; + constant RDMA_WRITE_LAST_C : slv(4 downto 0) := "01000"; + constant RDMA_WRITE_LAST_WITH_IMMEDIATE_C : slv(4 downto 0) := "01001"; + constant RDMA_WRITE_ONLY_C : slv(4 downto 0) := "01010"; + constant RDMA_WRITE_ONLY_WITH_IMMEDIATE_C : slv(4 downto 0) := "01011"; + constant RDMA_READ_REQUEST_C : slv(4 downto 0) := "01100"; + constant RDMA_READ_RESPONSE_FIRST_C : slv(4 downto 0) := "01101"; + constant RDMA_READ_RESPONSE_MIDDLE_C : slv(4 downto 0) := "01110"; + constant RDMA_READ_RESPONSE_LAST_C : slv(4 downto 0) := "01111"; + constant RDMA_READ_RESPONSE_ONLY_C : slv(4 downto 0) := "10000"; + constant ACKNOWLEDGE_C : slv(4 downto 0) := "10001"; + constant ATOMIC_ACKNOWLEDGE_C : slv(4 downto 0) := "10010"; + constant COMPARE_SWAP_C : slv(4 downto 0) := "10011"; + constant FETCH_ADD_C : slv(4 downto 0) := "10100"; + constant SEND_LAST_WITH_INVALIDATE_C : slv(4 downto 0) := "10110"; + constant SEND_ONLY_WITH_INVALIDATE_C : slv(4 downto 0) := "10111"; + + -- TransType (3-bit) + constant TRANS_TYPE_RC_C : slv(2 downto 0) := "000"; + constant TRANS_TYPE_UC_C : slv(2 downto 0) := "001"; + constant TRANS_TYPE_UD_C : slv(2 downto 0) := "011"; + constant TRANS_TYPE_CNP_C : slv(2 downto 0) := "100"; + constant TRANS_TYPE_XRC_C : slv(2 downto 0) := "101"; + + -- TypeQP (4-bit, deriving(Bits) integer encodings) + constant IBV_QPT_RC_C : slv(3 downto 0) := x"2"; + constant IBV_QPT_UC_C : slv(3 downto 0) := x"3"; + constant IBV_QPT_UD_C : slv(3 downto 0) := x"4"; + constant IBV_QPT_XRC_SEND_C : slv(3 downto 0) := x"9"; + constant IBV_QPT_XRC_RECV_C : slv(3 downto 0) := x"A"; + + -- PMTU (3-bit) + constant IBV_MTU_256_C : slv(2 downto 0) := "001"; + constant IBV_MTU_512_C : slv(2 downto 0) := "010"; + constant IBV_MTU_1024_C : slv(2 downto 0) := "011"; + constant IBV_MTU_2048_C : slv(2 downto 0) := "100"; + constant IBV_MTU_4096_C : slv(2 downto 0) := "101"; + + -- AETH code (2-bit) / NAK value (5-bit) + constant AETH_CODE_ACK_C : slv(1 downto 0) := "00"; + constant AETH_CODE_RNR_C : slv(1 downto 0) := "01"; + constant AETH_CODE_NAK_C : slv(1 downto 0) := "11"; + constant AETH_NAK_SEQ_ERR_C : slv(4 downto 0) := "00000"; + constant AETH_NAK_INV_REQ_C : slv(4 downto 0) := "00001"; + constant AETH_NAK_RMT_ACC_C : slv(4 downto 0) := "00010"; + constant AETH_NAK_RMT_OP_C : slv(4 downto 0) := "00011"; + constant AETH_NAK_INV_RD_C : slv(4 downto 0) := "00100"; + + -- {trans,opcode} congestion-notification marker (ROCE_CNP = 8'h81) + constant ROCE_CNP_C : slv(7 downto 0) := x"81"; + + -- PktVeriStatus (1-bit): PKT_ST_VALID=0, PKT_ST_LEN_ERR=1 + constant PKT_ST_VALID_C : sl := '0'; + constant PKT_ST_LEN_ERR_C : sl := '1'; + + --------------------------------------------------------------------------- + -- Helper functions (faithful to Utils.bsv / Headers.bsv / InputPktHandle.bsv) + --------------------------------------------------------------------------- + type FragByteNumType is record + valid : sl; + num : slv(5 downto 0); -- ByteEnBitNum + end record; + + function isFirstOp (op : slv(4 downto 0)) return boolean is + begin + case op is + when SEND_FIRST_C | RDMA_WRITE_FIRST_C | RDMA_READ_RESPONSE_FIRST_C => return true; + when others => return false; + end case; + end function; + + function isMiddleOp (op : slv(4 downto 0)) return boolean is + begin + case op is + when SEND_MIDDLE_C | RDMA_WRITE_MIDDLE_C | RDMA_READ_RESPONSE_MIDDLE_C => return true; + when others => return false; + end case; + end function; + + function isLastOp (op : slv(4 downto 0)) return boolean is + begin + case op is + when SEND_LAST_C | SEND_LAST_WITH_IMMEDIATE_C | SEND_LAST_WITH_INVALIDATE_C | + RDMA_WRITE_LAST_C | RDMA_WRITE_LAST_WITH_IMMEDIATE_C | + RDMA_READ_RESPONSE_LAST_C => return true; + when others => return false; + end case; + end function; + + function isOnlyOp (op : slv(4 downto 0)) return boolean is + begin + case op is + when SEND_ONLY_C | SEND_ONLY_WITH_IMMEDIATE_C | SEND_ONLY_WITH_INVALIDATE_C | + RDMA_WRITE_ONLY_C | RDMA_WRITE_ONLY_WITH_IMMEDIATE_C | + RDMA_READ_REQUEST_C | COMPARE_SWAP_C | FETCH_ADD_C | + RDMA_READ_RESPONSE_ONLY_C | ACKNOWLEDGE_C | ATOMIC_ACKNOWLEDGE_C => return true; + when others => return false; + end case; + end function; + + function isFirstOrMidOp (op : slv(4 downto 0)) return boolean is + begin return isFirstOp(op) or isMiddleOp(op); end function; + + function isLastOrOnlyOp (op : slv(4 downto 0)) return boolean is + begin return isLastOp(op) or isOnlyOp(op); end function; + + function isRdmaRespOp (op : slv(4 downto 0)) return boolean is + begin + case op is + when RDMA_READ_RESPONSE_FIRST_C | RDMA_READ_RESPONSE_MIDDLE_C | + RDMA_READ_RESPONSE_LAST_C | RDMA_READ_RESPONSE_ONLY_C | + ACKNOWLEDGE_C | ATOMIC_ACKNOWLEDGE_C => return true; + when others => return false; + end case; + end function; + + -- checkZeroFields4BTH: tver, fecn, becn, resv6, resv7 all zero (migReq NOT checked) + function checkZeroFields4BTH (bth : slv(95 downto 0)) return boolean is + begin + return (bth(83 downto 80) = "0000") -- tver + and (bth(63) = '0') -- fecn + and (bth(62) = '0') -- becn + and (bth(61 downto 56) = "000000") -- resv6 + and (bth(30 downto 24) = "0000000"); -- resv7 + end function; + + -- padCntCheckReqHeader(bth): opcode/padCnt LUT + function padCntCheckReqHeader (op : slv(4 downto 0); padCnt : slv(1 downto 0)) return boolean is + variable zeroPad : boolean; + begin + zeroPad := (padCnt = "00"); + case op is + when SEND_FIRST_C | SEND_MIDDLE_C => return zeroPad; + when SEND_LAST_C | SEND_ONLY_C | + SEND_LAST_WITH_IMMEDIATE_C | SEND_ONLY_WITH_IMMEDIATE_C | + SEND_LAST_WITH_INVALIDATE_C | SEND_ONLY_WITH_INVALIDATE_C => return true; + when RDMA_WRITE_FIRST_C | RDMA_WRITE_MIDDLE_C => return zeroPad; + when RDMA_WRITE_LAST_C | RDMA_WRITE_ONLY_C | + RDMA_WRITE_LAST_WITH_IMMEDIATE_C | RDMA_WRITE_ONLY_WITH_IMMEDIATE_C => return true; + when RDMA_READ_REQUEST_C | COMPARE_SWAP_C | FETCH_ADD_C => return zeroPad; + when others => return false; + end case; + end function; + + -- padCntCheckRespHeader(bth, aeth): opcode + AETH code/value LUT + function padCntCheckRespHeader (op : slv(4 downto 0); + padCnt : slv(1 downto 0); + aethCode : slv(1 downto 0); + aethVal : slv(4 downto 0)) return boolean is + variable zeroPad : boolean; + begin + zeroPad := (padCnt = "00"); + case op is + when RDMA_READ_RESPONSE_MIDDLE_C => + return zeroPad; + when RDMA_READ_RESPONSE_LAST_C | RDMA_READ_RESPONSE_ONLY_C => + return (aethCode = AETH_CODE_ACK_C); + when RDMA_READ_RESPONSE_FIRST_C | ATOMIC_ACKNOWLEDGE_C => + return (aethCode = AETH_CODE_ACK_C) and zeroPad; + when ACKNOWLEDGE_C => + if (aethCode = AETH_CODE_ACK_C) or (aethCode = AETH_CODE_RNR_C) then + return zeroPad; + elsif (aethCode = AETH_CODE_NAK_C) then + case aethVal is + when AETH_NAK_SEQ_ERR_C | AETH_NAK_INV_REQ_C | AETH_NAK_RMT_ACC_C | + AETH_NAK_RMT_OP_C | AETH_NAK_INV_RD_C => return zeroPad; + when others => return false; + end case; + else + return false; -- AETH_CODE_RSVD / others + end if; + when others => return false; + end case; + end function; + + -- isCongestionNotificationPkt(bth) = {trans,opcode} == ROCE_CNP + function isCnp (trans : slv(2 downto 0); op : slv(4 downto 0)) return boolean is + begin + return ((trans & op) = ROCE_CNP_C); + end function; + + -- transTypeMatchQpType(tt, qpt, isRecvSide) + function transTypeMatchQpType (tt : slv(2 downto 0); qpt : slv(3 downto 0); + isRecvSide : sl) return boolean is + begin + case tt is + when TRANS_TYPE_CNP_C => return true; + when TRANS_TYPE_RC_C => return (qpt = IBV_QPT_RC_C); + when TRANS_TYPE_UC_C => return (qpt = IBV_QPT_UC_C); + when TRANS_TYPE_UD_C => return (qpt = IBV_QPT_UD_C); + when TRANS_TYPE_XRC_C => + return ((isRecvSide = '0') and (qpt = IBV_QPT_XRC_RECV_C)) + or ((isRecvSide = '1') and (qpt = IBV_QPT_XRC_SEND_C)); + when others => return false; + end case; + end function; + + -- validateHeader(transType, qkey, cntrlStatus, isRespPkt) + function validateHeader (transType : slv(2 downto 0); + qkey : slv(31 downto 0); + qpType : slv(3 downto 0); + statusIsERR, statusIsRTS, statusIsNonErr : sl; + statusQKEY : slv(31 downto 0); + isRespPkt : sl) return boolean is + variable transTypeMatch, qpStateMatch, qKeyMatch : boolean; + begin + transTypeMatch := transTypeMatchQpType(transType, qpType, isRespPkt); + if statusIsERR = '1' then + qpStateMatch := true; + elsif isRespPkt = '1' then + qpStateMatch := (statusIsRTS = '1'); + else + qpStateMatch := (statusIsNonErr = '1'); + end if; + if transType = TRANS_TYPE_UD_C then + qKeyMatch := (qkey = statusQKEY); + else + qKeyMatch := true; + end if; + return transTypeMatch and qpStateMatch and qKeyMatch; + end function; + + -- calcFragByteNumFromByteEn(byteEn): reverse, find idx in {0,4,..,32} where + -- reversed == (1< '0'); + for k in 0 to 8 loop -- idx = k*4 = 0,4,...,32 (step FRAG_MIN_VALID_BYTE_NUM=4) + idx := k * 4; + m := shift_left(to_unsigned(1, 33), idx) - 1; -- idx ones (idx=0 → 0) + cmp := slv(m(31 downto 0)); + if rev = cmp then + res.valid := '1'; + res.num := slv(to_unsigned(idx, 6)); + end if; + end loop; + return res; + end function; + + -- isZeroByteEn(byteEn) = isZero({msb,lsb}) (only MSB and LSB tested, per source) + function isZeroByteEn (byteEn : slv(31 downto 0)) return boolean is + begin + return (byteEn(31) = '0') and (byteEn(0) = '0'); + end function; + + -- pktLenEqPMTU: pktLen == 2**log2(pmtu) (clear bit idx, rest must be zero) + function pktLenEqPMTU (pktLen : slv(12 downto 0); pmtu : slv(2 downto 0)) return boolean is + variable tmp : slv(12 downto 0); + variable idx : integer; + begin + case pmtu is + when IBV_MTU_256_C => idx := 8; + when IBV_MTU_512_C => idx := 9; + when IBV_MTU_1024_C => idx := 10; + when IBV_MTU_2048_C => idx := 11; + when others => idx := 12; -- IBV_MTU_4096 + end case; + tmp := pktLen; + tmp(idx) := '0'; + return (unsigned(tmp) = 0); + end function; + + -- pktLenGtPMTU: pktLen(idx)='1' AND lower idx bits nonzero + function pktLenGtPMTU (pktLen : slv(12 downto 0); pmtu : slv(2 downto 0)) return boolean is + begin + case pmtu is + when IBV_MTU_256_C => return (pktLen(8) = '1') and (unsigned(pktLen(7 downto 0)) /= 0); + when IBV_MTU_512_C => return (pktLen(9) = '1') and (unsigned(pktLen(8 downto 0)) /= 0); + when IBV_MTU_1024_C => return (pktLen(10) = '1') and (unsigned(pktLen(9 downto 0)) /= 0); + when IBV_MTU_2048_C => return (pktLen(11) = '1') and (unsigned(pktLen(10 downto 0)) /= 0); + when others => return (pktLen(12) = '1') and (unsigned(pktLen(11 downto 0)) /= 0); + end case; + end function; + + -- pktLenAddBusByteWidth: {(pktLen[12:5]+1), pktLen[4:0]} + function pktLenAddBusByteWidth (pktLen : slv(12 downto 0)) return slv is + variable r : slv(12 downto 0); + begin + r(12 downto 5) := slv(unsigned(pktLen(12 downto 5)) + 1); + r(4 downto 0) := pktLen(4 downto 0); + return r; + end function; + + -- pktLenAddFragLen: fragLen==32 ? addBusByteWidth : {pktLen[12:5], fragLen[4:0]} + function pktLenAddFragLen (pktLen : slv(12 downto 0); fragLen : slv(5 downto 0)) return slv is + variable tmp : slv(5 downto 0); + begin + tmp := fragLen; + tmp(5) := '0'; + if unsigned(tmp) = 0 then -- fragLenEqBusByteWidth (fragLen == 32) + return pktLenAddBusByteWidth(pktLen); + else + return pktLen(12 downto 5) & fragLen(4 downto 0); + end if; + end function; + + --------------------------------------------------------------------------- + -- Control-FSM state + accumulators (RegType) + --------------------------------------------------------------------------- + type RdmaPktBufStateType is (PRE_CHECK_FRAG_S, DISCARD_FRAG_S); + + type RegType is record + pktBufState : RdmaPktBufStateType; -- mkReg(PRE_CHECK_FRAG_S) + isValidPkt : sl; -- mkRegU (0 in init) + bthPadCnt : slv(1 downto 0); -- mkRegU + pktFragNum : slv(7 downto 0); -- mkRegU + pktLen : slv(12 downto 0); -- mkRegU + pktValid : sl; -- mkRegU + end record RegType; + + constant REG_INIT_C : RegType := ( + pktBufState => PRE_CHECK_FRAG_S, + isValidPkt => '0', + bthPadCnt => (others => '0'), + pktFragNum => (others => '0'), + pktLen => (others => '0'), + pktValid => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + --------------------------------------------------------------------------- + -- FIFO / child interconnect signals + --------------------------------------------------------------------------- + -- U_PayloadPipeIn (mkBuffer skid on payload input) + signal payloadBufWrEn : sl; + signal payloadBufNotFull: sl; + signal payloadBufValid : sl; + signal payloadBufDout : slv(DS_W_C-1 downto 0); + signal payloadBufRdEn : sl; + + -- U_RdmaHeaderPipeOut (child DataStream2Header) output = rdmaHeaderPipeOut + signal rdmaHdrValid : sl; + signal rdmaHdrDout : slv(HDR_W_C-1 downto 0); + signal rdmaHdrRdEn : sl; + + -- 18 internal pipeline FIFOs: {Din,WrEn,NotFull,Valid,Dout,RdEn} + signal rdmaHeaderRecvQDin : slv(RECV_W_C-1 downto 0); + signal rdmaHeaderRecvQWrEn, rdmaHeaderRecvQNotFull, rdmaHeaderRecvQValid, rdmaHeaderRecvQRdEn : sl; + signal rdmaHeaderRecvQDout : slv(RECV_W_C-1 downto 0); + + signal payloadRecvQDin : slv(DS_W_C-1 downto 0); + signal payloadRecvQWrEn, payloadRecvQNotFull, payloadRecvQValid, payloadRecvQRdEn : sl; + signal payloadRecvQDout : slv(DS_W_C-1 downto 0); + + signal rdmaHeaderPreCheckQDin : slv(PRECHK_W_C-1 downto 0); + signal rdmaHeaderPreCheckQWrEn, rdmaHeaderPreCheckQNotFull, rdmaHeaderPreCheckQValid, rdmaHeaderPreCheckQRdEn : sl; + signal rdmaHeaderPreCheckQDout : slv(PRECHK_W_C-1 downto 0); + + signal payloadPreCheckQDin : slv(DS_W_C-1 downto 0); + signal payloadPreCheckQWrEn, payloadPreCheckQNotFull, payloadPreCheckQValid, payloadPreCheckQRdEn : sl; + signal payloadPreCheckQDout : slv(DS_W_C-1 downto 0); + + signal rdmaHeaderValidationQDin : slv(VALID_W_C-1 downto 0); + signal rdmaHeaderValidationQWrEn, rdmaHeaderValidationQNotFull, rdmaHeaderValidationQValid, rdmaHeaderValidationQRdEn : sl; + signal rdmaHeaderValidationQDout : slv(VALID_W_C-1 downto 0); + + signal payloadValidationQDin : slv(DS_W_C-1 downto 0); + signal payloadValidationQWrEn, payloadValidationQNotFull, payloadValidationQValid, payloadValidationQRdEn : sl; + signal payloadValidationQDout : slv(DS_W_C-1 downto 0); + + signal rdmaHeaderFilterQDin : slv(FILT_W_C-1 downto 0); + signal rdmaHeaderFilterQWrEn, rdmaHeaderFilterQNotFull, rdmaHeaderFilterQValid, rdmaHeaderFilterQRdEn : sl; + signal rdmaHeaderFilterQDout : slv(FILT_W_C-1 downto 0); + + signal payloadFilterQDin : slv(DS_W_C-1 downto 0); + signal payloadFilterQWrEn, payloadFilterQNotFull, payloadFilterQValid, payloadFilterQRdEn : sl; + signal payloadFilterQDout : slv(DS_W_C-1 downto 0); + + signal rdmaHeaderFragLenCalcQDin : slv(FILT_W_C-1 downto 0); + signal rdmaHeaderFragLenCalcQWrEn, rdmaHeaderFragLenCalcQNotFull, rdmaHeaderFragLenCalcQValid, rdmaHeaderFragLenCalcQRdEn : sl; + signal rdmaHeaderFragLenCalcQDout : slv(FILT_W_C-1 downto 0); + + signal payloadFragLenCalcQDin : slv(DS_W_C-1 downto 0); + signal payloadFragLenCalcQWrEn, payloadFragLenCalcQNotFull, payloadFragLenCalcQValid, payloadFragLenCalcQRdEn : sl; + signal payloadFragLenCalcQDout : slv(DS_W_C-1 downto 0); + + signal rdmaHeaderPktLenCalcQDin : slv(FILT_W_C-1 downto 0); + signal rdmaHeaderPktLenCalcQWrEn, rdmaHeaderPktLenCalcQNotFull, rdmaHeaderPktLenCalcQValid, rdmaHeaderPktLenCalcQRdEn : sl; + signal rdmaHeaderPktLenCalcQDout : slv(FILT_W_C-1 downto 0); + + signal payloadPktLenCalcQDin : slv(PLC_W_C-1 downto 0); + signal payloadPktLenCalcQWrEn, payloadPktLenCalcQNotFull, payloadPktLenCalcQValid, payloadPktLenCalcQRdEn : sl; + signal payloadPktLenCalcQDout : slv(PLC_W_C-1 downto 0); + + signal rdmaHeaderPktLenPreCheckQDin : slv(PLCI_W_C-1 downto 0); + signal rdmaHeaderPktLenPreCheckQWrEn, rdmaHeaderPktLenPreCheckQNotFull, rdmaHeaderPktLenPreCheckQValid, rdmaHeaderPktLenPreCheckQRdEn : sl; + signal rdmaHeaderPktLenPreCheckQDout : slv(PLCI_W_C-1 downto 0); + + signal payloadPktLenPreCheckQDin : slv(PL3_W_C-1 downto 0); + signal payloadPktLenPreCheckQWrEn, payloadPktLenPreCheckQNotFull, payloadPktLenPreCheckQValid, payloadPktLenPreCheckQRdEn : sl; + signal payloadPktLenPreCheckQDout : slv(PL3_W_C-1 downto 0); + + signal rdmaHeaderPktLenCheckQDin : slv(PCHK4_W_C-1 downto 0); + signal rdmaHeaderPktLenCheckQWrEn, rdmaHeaderPktLenCheckQNotFull, rdmaHeaderPktLenCheckQValid, rdmaHeaderPktLenCheckQRdEn : sl; + signal rdmaHeaderPktLenCheckQDout : slv(PCHK4_W_C-1 downto 0); + + signal payloadPktLenCheckQDin : slv(PL3_W_C-1 downto 0); + signal payloadPktLenCheckQWrEn, payloadPktLenCheckQNotFull, payloadPktLenCheckQValid, payloadPktLenCheckQRdEn : sl; + signal payloadPktLenCheckQDout : slv(PL3_W_C-1 downto 0); + + signal rdmaHeaderOutputQDin : slv(HDROUT_W_C-1 downto 0); + signal rdmaHeaderOutputQWrEn, rdmaHeaderOutputQNotFull, rdmaHeaderOutputQValid, rdmaHeaderOutputQRdEn : sl; + signal rdmaHeaderOutputQDout : slv(HDROUT_W_C-1 downto 0); + + signal payloadOutputQDin : slv(PL3_W_C-1 downto 0); + signal payloadOutputQWrEn, payloadOutputQNotFull, payloadOutputQValid, payloadOutputQRdEn : sl; + signal payloadOutputQDout : slv(PL3_W_C-1 downto 0); + + --------------------------------------------------------------------------- + -- Output FIFO vectors (internal arrays; flattened to ports in the generate) + --------------------------------------------------------------------------- + type MetaArray is array (natural range <>) of slv(META_W_C-1 downto 0); + type DsArray is array (natural range <>) of slv(DS_W_C-1 downto 0); + type BthArray is array (natural range <>) of slv(BTH_W_C-1 downto 0); + + signal cnpDinA, cnpDoutA : BthArray(0 to MAX_QP_G-1); + signal cnpWrEnA, cnpNotFullA, cnpValidA : slv(MAX_QP_G-1 downto 0); + + signal reqPayloadDinA, reqPayloadDoutA : DsArray(0 to MAX_QP_G-1); + signal reqPayloadWrEnA, reqPayloadNotFullA, reqPayloadValidA : slv(MAX_QP_G-1 downto 0); + signal respPayloadDinA, respPayloadDoutA : DsArray(0 to MAX_QP_G-1); + signal respPayloadWrEnA, respPayloadNotFullA, respPayloadValidA : slv(MAX_QP_G-1 downto 0); + + signal reqMetaDinA, reqMetaDoutA : MetaArray(0 to MAX_QP_G-1); + signal reqMetaWrEnA, reqMetaNotFullA, reqMetaValidA : slv(MAX_QP_G-1 downto 0); + signal respMetaDinA, respMetaDoutA : MetaArray(0 to MAX_QP_G-1); + signal respMetaWrEnA, respMetaNotFullA, respMetaValidA : slv(MAX_QP_G-1 downto 0); + +begin + + assert isPowerOf2(MAX_QP_G) + report "InputRdmaPktBufAndHeaderValidation: MAX_QP_G must be a power of 2, >= 1 " & + "(getIndexQP = truncateLSB of the 24-bit QPN to log2(MAX_QP_G) bits; " & + "at MAX_QP_G=1 the index is forced to 0, MetaData.bsv:349)." + severity failure; + + --------------------------------------------------------------------------- + -- U_PayloadPipeIn : surf.Fifo (BSV mkBuffer(pipeIn.payload) = mkPipelineFIFOF) + -- Write side fed by the payload input pipe; read side (payloadBuf*) consumed + -- by recvPktFrag / discardInvalidFrag. + --------------------------------------------------------------------------- + payloadBufWrEn <= payloadPipeInValid and payloadBufNotFull; + payloadPipeInRdEn <= payloadPipeInValid and payloadBufNotFull; + + U_PayloadPipeIn : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => DS_W_C, + ADDR_WIDTH_G => ADDR_W_C) + port map ( + rst => rst, wr_clk => clk, wr_en => payloadBufWrEn, din => payloadPipeInData, + not_full => payloadBufNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadBufRdEn, dout => payloadBufDout, + valid => payloadBufValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_RdmaHeaderPipeOut : entity surf.DataStream2Header (child, mkDataStream2Header) + -- Consumes the header DataStream + HeaderMetaData input pipes; emits a + -- 593-bit HeaderRDMA per packet (rdmaHdr*), consumed by recvPktFrag. + --------------------------------------------------------------------------- + U_RdmaHeaderPipeOut : entity surf.DataStream2Header + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, rst => rst, + dataPipeInValid => headerDataStreamValid, + dataPipeInData => headerDataStreamData, + dataPipeInRdEn => headerDataStreamRdEn, + hdrMetaDataPipeInValid => headerMetaDataValid, + hdrMetaDataPipeInData => headerMetaDataData, + hdrMetaDataPipeInRdEn => headerMetaDataRdEn, + headerOutQValid => rdmaHdrValid, + headerOutQDout => rdmaHdrDout, + headerOutQRdEn => rdmaHdrRdEn); + + --------------------------------------------------------------------------- + -- 18 internal pipeline FIFOs (all surf.Fifo, FWFT, sync) + --------------------------------------------------------------------------- + U_RdmaHeaderRecvQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => RECV_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderRecvQWrEn, din => rdmaHeaderRecvQDin, + not_full => rdmaHeaderRecvQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rdmaHeaderRecvQRdEn, dout => rdmaHeaderRecvQDout, + valid => rdmaHeaderRecvQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadRecvQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => payloadRecvQWrEn, din => payloadRecvQDin, + not_full => payloadRecvQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadRecvQRdEn, dout => payloadRecvQDout, + valid => payloadRecvQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_RdmaHeaderPreCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PRECHK_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderPreCheckQWrEn, din => rdmaHeaderPreCheckQDin, + not_full => rdmaHeaderPreCheckQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rdmaHeaderPreCheckQRdEn, dout => rdmaHeaderPreCheckQDout, + valid => rdmaHeaderPreCheckQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadPreCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => payloadPreCheckQWrEn, din => payloadPreCheckQDin, + not_full => payloadPreCheckQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadPreCheckQRdEn, dout => payloadPreCheckQDout, + valid => payloadPreCheckQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_RdmaHeaderValidationQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => VALID_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderValidationQWrEn, din => rdmaHeaderValidationQDin, + not_full => rdmaHeaderValidationQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rdmaHeaderValidationQRdEn, dout => rdmaHeaderValidationQDout, + valid => rdmaHeaderValidationQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadValidationQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => payloadValidationQWrEn, din => payloadValidationQDin, + not_full => payloadValidationQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadValidationQRdEn, dout => payloadValidationQDout, + valid => payloadValidationQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_RdmaHeaderFilterQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => FILT_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderFilterQWrEn, din => rdmaHeaderFilterQDin, + not_full => rdmaHeaderFilterQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rdmaHeaderFilterQRdEn, dout => rdmaHeaderFilterQDout, + valid => rdmaHeaderFilterQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadFilterQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => payloadFilterQWrEn, din => payloadFilterQDin, + not_full => payloadFilterQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadFilterQRdEn, dout => payloadFilterQDout, + valid => payloadFilterQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_RdmaHeaderFragLenCalcQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => FILT_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderFragLenCalcQWrEn, din => rdmaHeaderFragLenCalcQDin, + not_full => rdmaHeaderFragLenCalcQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rdmaHeaderFragLenCalcQRdEn, dout => rdmaHeaderFragLenCalcQDout, + valid => rdmaHeaderFragLenCalcQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadFragLenCalcQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => payloadFragLenCalcQWrEn, din => payloadFragLenCalcQDin, + not_full => payloadFragLenCalcQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadFragLenCalcQRdEn, dout => payloadFragLenCalcQDout, + valid => payloadFragLenCalcQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_RdmaHeaderPktLenCalcQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => FILT_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderPktLenCalcQWrEn, din => rdmaHeaderPktLenCalcQDin, + not_full => rdmaHeaderPktLenCalcQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rdmaHeaderPktLenCalcQRdEn, dout => rdmaHeaderPktLenCalcQDout, + valid => rdmaHeaderPktLenCalcQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadPktLenCalcQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PLC_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => payloadPktLenCalcQWrEn, din => payloadPktLenCalcQDin, + not_full => payloadPktLenCalcQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadPktLenCalcQRdEn, dout => payloadPktLenCalcQDout, + valid => payloadPktLenCalcQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_RdmaHeaderPktLenPreCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PLCI_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderPktLenPreCheckQWrEn, din => rdmaHeaderPktLenPreCheckQDin, + not_full => rdmaHeaderPktLenPreCheckQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rdmaHeaderPktLenPreCheckQRdEn, dout => rdmaHeaderPktLenPreCheckQDout, + valid => rdmaHeaderPktLenPreCheckQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadPktLenPreCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PL3_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => payloadPktLenPreCheckQWrEn, din => payloadPktLenPreCheckQDin, + not_full => payloadPktLenPreCheckQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadPktLenPreCheckQRdEn, dout => payloadPktLenPreCheckQDout, + valid => payloadPktLenPreCheckQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_RdmaHeaderPktLenCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PCHK4_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderPktLenCheckQWrEn, din => rdmaHeaderPktLenCheckQDin, + not_full => rdmaHeaderPktLenCheckQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rdmaHeaderPktLenCheckQRdEn, dout => rdmaHeaderPktLenCheckQDout, + valid => rdmaHeaderPktLenCheckQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadPktLenCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PL3_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => payloadPktLenCheckQWrEn, din => payloadPktLenCheckQDin, + not_full => payloadPktLenCheckQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadPktLenCheckQRdEn, dout => payloadPktLenCheckQDout, + valid => payloadPktLenCheckQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_RdmaHeaderOutputQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => HDROUT_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderOutputQWrEn, din => rdmaHeaderOutputQDin, + not_full => rdmaHeaderOutputQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rdmaHeaderOutputQRdEn, dout => rdmaHeaderOutputQDout, + valid => rdmaHeaderOutputQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadOutputQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PL3_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => payloadOutputQWrEn, din => payloadOutputQDin, + not_full => payloadOutputQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadOutputQRdEn, dout => payloadOutputQDout, + valid => payloadOutputQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + --------------------------------------------------------------------------- + -- Output FIFO vectors (x MAX_QP_G): 5 groups, one surf.Fifo per QP index. + -- Read side is the entity's returned PipeOut vector (flattened ports). + --------------------------------------------------------------------------- + GEN_OUT_VEC : for i in 0 to MAX_QP_G-1 generate + -- flatten read side to the entity ports + cnpValid(i) <= cnpValidA(i); + cnpDout((i+1)*96-1 downto i*96) <= cnpDoutA(i); + + reqPayloadValid(i) <= reqPayloadValidA(i); + reqPayloadDout((i+1)*290-1 downto i*290) <= reqPayloadDoutA(i); + respPayloadValid(i) <= respPayloadValidA(i); + respPayloadDout((i+1)*290-1 downto i*290) <= respPayloadDoutA(i); + reqPktMetaDataValid(i) <= reqMetaValidA(i); + reqPktMetaDataDout((i+1)*649-1 downto i*649) <= reqMetaDoutA(i); + respPktMetaDataValid(i) <= respMetaValidA(i); + respPktMetaDataDout((i+1)*649-1 downto i*649) <= respMetaDoutA(i); + + U_CnpOutVec : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => BTH_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => cnpWrEnA(i), din => cnpDinA(i), + not_full => cnpNotFullA(i), full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => cnpRdEn(i), dout => cnpDoutA(i), + valid => cnpValidA(i), underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + -- Req-stream (-> responder/RQ) output FIFOs: pruned when EN_RX_G=false. + -- notFull tied '1' makes the output stages fire-and-drop request packets + -- here (authoritative drain for the disabled responder). + GEN_NO_REQ_FIFOS : if not EN_RX_G generate + reqPayloadNotFullA(i) <= '1'; + reqPayloadValidA(i) <= '0'; + reqPayloadDoutA(i) <= (others => '0'); + reqMetaNotFullA(i) <= '1'; + reqMetaValidA(i) <= '0'; + reqMetaDoutA(i) <= (others => '0'); + end generate GEN_NO_REQ_FIFOS; + + GEN_REQ_FIFOS : if EN_RX_G generate + U_ReqPayloadOutVec : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => reqPayloadWrEnA(i), din => reqPayloadDinA(i), + not_full => reqPayloadNotFullA(i), full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => reqPayloadRdEn(i), dout => reqPayloadDoutA(i), + valid => reqPayloadValidA(i), underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_ReqPktMetaDataOutVec : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => META_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => reqMetaWrEnA(i), din => reqMetaDinA(i), + not_full => reqMetaNotFullA(i), full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => reqPktMetaDataRdEn(i), dout => reqMetaDoutA(i), + valid => reqMetaValidA(i), underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + end generate GEN_REQ_FIFOS; + + -- Resp-stream (-> requester/SQ) output FIFOs: pruned when EN_TX_G=false + -- (a pure responder never sees ACK/read-response packets addressed to it; + -- any that arrive drop here). + GEN_NO_RESP_FIFOS : if not EN_TX_G generate + respPayloadNotFullA(i) <= '1'; + respPayloadValidA(i) <= '0'; + respPayloadDoutA(i) <= (others => '0'); + respMetaNotFullA(i) <= '1'; + respMetaValidA(i) <= '0'; + respMetaDoutA(i) <= (others => '0'); + end generate GEN_NO_RESP_FIFOS; + + GEN_RESP_FIFOS : if EN_TX_G generate + U_RespPayloadOutVec : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => respPayloadWrEnA(i), din => respPayloadDinA(i), + not_full => respPayloadNotFullA(i), full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => respPayloadRdEn(i), dout => respPayloadDoutA(i), + valid => respPayloadValidA(i), underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_RespPktMetaDataOutVec : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => META_W_C, ADDR_WIDTH_G => ADDR_W_C) + port map (rst => rst, wr_clk => clk, wr_en => respMetaWrEnA(i), din => respMetaDinA(i), + not_full => respMetaNotFullA(i), full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => respPktMetaDataRdEn(i), dout => respMetaDoutA(i), + valid => respMetaValidA(i), underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + end generate GEN_RESP_FIFOS; + end generate GEN_OUT_VEC; + + --------------------------------------------------------------------------- + -- Combinatorial process — 12 concurrent stage rules (no elsif precedence), + -- pktBufState control FSM, per-packet accumulators. + --------------------------------------------------------------------------- + comb : process (all) is + variable v : RegType; + + -- shared per-rule temporaries + variable frag : slv(DS_W_C-1 downto 0); + variable isFirst : sl; + variable isLast : sl; + variable canFire : boolean; + + -- recvPktFrag + variable rHdr : slv(HDR_W_C-1 downto 0); + variable rBth : slv(BTH_W_C-1 downto 0); + variable aethCode : slv(1 downto 0); + variable aethVal : slv(4 downto 0); + variable bthChk : sl; + variable hdrChk : sl; + variable nonPayOk : sl; + + -- prepareValidation + variable pcHdr : slv(HDR_W_C-1 downto 0); + variable pcBth : slv(BTH_W_C-1 downto 0); + variable pcTrans : slv(2 downto 0); + variable pcOp : slv(4 downto 0); + variable pcIsCnp : boolean; + variable pcIsResp : boolean; + variable pcRespOrCnp: boolean; + variable pcDqpn : slv(23 downto 0); + variable pcQkey : slv(31 downto 0); + variable pcSrqn : slv(23 downto 0); + variable hvi : slv(HVI_W_C-1 downto 0); + + -- checkMetaDataQP + variable vHdr : slv(HDR_W_C-1 downto 0); + variable vBth : slv(BTH_W_C-1 downto 0); + variable vHvi : slv(HVI_W_C-1 downto 0); + variable vIsCnp : sl; + variable vIsResp : sl; + variable vResp : sl; -- isRespPkt || isCNP + variable vMaybe : sl; + variable vDqpn : slv(23 downto 0); + variable vQkey : slv(31 downto 0); + variable selTypeQP : slv(3 downto 0); + variable selERR, selRTS, selNonErr : sl; + variable selQKEY : slv(31 downto 0); + variable isValidHdr : sl; + variable pdHandler : slv(31 downto 0); + variable vhInfo : slv(VHI_W_C-1 downto 0); + + -- discardInvalidHeaderPkt + variable fHdr : slv(HDR_W_C-1 downto 0); + variable fBth : slv(BTH_W_C-1 downto 0); + variable fVhi : slv(VHI_W_C-1 downto 0); + variable fIsValidHdr: sl; + variable fIsCnp : sl; + variable isValidEff : sl; + variable cnpIdx : integer range 0 to MAX_QP_G-1; + variable needFrag, needCnp, needPay : boolean; + variable fragOk, cnpOk, payOk : boolean; + + -- calcFraglen + variable clHdr : slv(HDR_W_C-1 downto 0); + variable clBth : slv(BTH_W_C-1 downto 0); + variable clVhi : slv(VHI_W_C-1 downto 0); + variable clPadCnt : slv(1 downto 0); + variable fbn : FragByteNumType; + variable fragLen : slv(5 downto 0); + variable fragLenNoPad : slv(5 downto 0); + variable byteEnNZ : sl; + variable byteEnAll : sl; + + -- calcPktLen + variable pHdr : slv(HDR_W_C-1 downto 0); + variable pBth : slv(BTH_W_C-1 downto 0); + variable pVhi : slv(VHI_W_C-1 downto 0); + variable pFrag : slv(DS_W_C-1 downto 0); + variable pFragLen : slv(5 downto 0); + variable pFragLenNoPad : slv(5 downto 0); + variable pByteEnNZ : sl; + variable pByteEnAll : sl; + variable pIsFirst, pIsLast : sl; + variable pIsRespPkt, pIsLastPkt, pIsFirstOrMid, pIsLastOrOnly : sl; + variable pQpIdx : integer range 0 to MAX_QP_G-1; + variable newPktLen : slv(12 downto 0); + variable newFragNum : slv(7 downto 0); + variable newValid : sl; + variable plci : slv(PLCI_W_C-1 downto 0); + + -- preCheckPktLen + variable preFrag : slv(DS_W_C-1 downto 0); + variable preQpIdx : slv(QP_IDX_W_C-1 downto 0); + variable preIsResp : sl; + variable preIsLast : sl; + variable prePlci : slv(PLCI_W_C-1 downto 0); + variable isZeroLen : sl; + variable isEqPMTU : sl; + variable isGtPMTU : sl; + + -- checkPktLen + variable ckFrag : slv(DS_W_C-1 downto 0); + variable ckQpIdx : slv(QP_IDX_W_C-1 downto 0); + variable ckIsResp : sl; + variable ckIsLast : sl; + variable ckPlci : slv(PLCI_W_C-1 downto 0); + variable ckZeroLen : sl; + variable ckEqPMTU : sl; + variable ckGtPMTU : sl; + variable ckValid : sl; + variable ckStatus : sl; + variable meta : slv(META_W_C-1 downto 0); + + -- output stages + variable oQpIdx : integer range 0 to MAX_QP_G-1; + variable oIsResp : sl; + begin + v := r; + + -- default all comb-driven controls (no latches) + rdmaHdrRdEn <= '0'; + payloadBufRdEn <= '0'; + + rdmaHeaderRecvQWrEn <= '0'; rdmaHeaderRecvQRdEn <= '0'; rdmaHeaderRecvQDin <= (others => '0'); + payloadRecvQWrEn <= '0'; payloadRecvQRdEn <= '0'; payloadRecvQDin <= (others => '0'); + rdmaHeaderPreCheckQWrEn <= '0'; rdmaHeaderPreCheckQRdEn <= '0'; rdmaHeaderPreCheckQDin <= (others => '0'); + payloadPreCheckQWrEn <= '0'; payloadPreCheckQRdEn <= '0'; payloadPreCheckQDin <= (others => '0'); + rdmaHeaderValidationQWrEn <= '0'; rdmaHeaderValidationQRdEn <= '0'; rdmaHeaderValidationQDin <= (others => '0'); + payloadValidationQWrEn <= '0'; payloadValidationQRdEn <= '0'; payloadValidationQDin <= (others => '0'); + rdmaHeaderFilterQWrEn <= '0'; rdmaHeaderFilterQRdEn <= '0'; rdmaHeaderFilterQDin <= (others => '0'); + payloadFilterQWrEn <= '0'; payloadFilterQRdEn <= '0'; payloadFilterQDin <= (others => '0'); + rdmaHeaderFragLenCalcQWrEn <= '0'; rdmaHeaderFragLenCalcQRdEn <= '0'; rdmaHeaderFragLenCalcQDin <= (others => '0'); + payloadFragLenCalcQWrEn <= '0'; payloadFragLenCalcQRdEn <= '0'; payloadFragLenCalcQDin <= (others => '0'); + rdmaHeaderPktLenCalcQWrEn <= '0'; rdmaHeaderPktLenCalcQRdEn <= '0'; rdmaHeaderPktLenCalcQDin <= (others => '0'); + payloadPktLenCalcQWrEn <= '0'; payloadPktLenCalcQRdEn <= '0'; payloadPktLenCalcQDin <= (others => '0'); + rdmaHeaderPktLenPreCheckQWrEn <= '0'; rdmaHeaderPktLenPreCheckQRdEn <= '0'; rdmaHeaderPktLenPreCheckQDin <= (others => '0'); + payloadPktLenPreCheckQWrEn <= '0'; payloadPktLenPreCheckQRdEn <= '0'; payloadPktLenPreCheckQDin <= (others => '0'); + rdmaHeaderPktLenCheckQWrEn <= '0'; rdmaHeaderPktLenCheckQRdEn <= '0'; rdmaHeaderPktLenCheckQDin <= (others => '0'); + payloadPktLenCheckQWrEn <= '0'; payloadPktLenCheckQRdEn <= '0'; payloadPktLenCheckQDin <= (others => '0'); + rdmaHeaderOutputQWrEn <= '0'; rdmaHeaderOutputQRdEn <= '0'; rdmaHeaderOutputQDin <= (others => '0'); + payloadOutputQWrEn <= '0'; payloadOutputQRdEn <= '0'; payloadOutputQDin <= (others => '0'); + + for i in 0 to MAX_QP_G-1 loop + cnpWrEnA(i) <= '0'; cnpDinA(i) <= (others => '0'); + reqPayloadWrEnA(i) <= '0'; reqPayloadDinA(i) <= (others => '0'); + respPayloadWrEnA(i) <= '0'; respPayloadDinA(i) <= (others => '0'); + reqMetaWrEnA(i) <= '0'; reqMetaDinA(i) <= (others => '0'); + respMetaWrEnA(i) <= '0'; respMetaDinA(i) <= (others => '0'); + end loop; + + -------------------------------------------------------------------- + -- qpMetaData combinational lookup requests (driven from FIFO heads) + -------------------------------------------------------------------- + -- getPD(dqpn) : dqpn computed from rdmaHeaderPreCheckQ head (prepareValidation) + pcHdr := rdmaHeaderPreCheckQDout(PRECHK_W_C-1 downto BTH_W_C); + pcBth := rdmaHeaderPreCheckQDout(BTH_W_C-1 downto 0); + pcTrans:= pcBth(95 downto 93); + pcOp := pcBth(92 downto 88); + pcIsCnp := isCnp(pcTrans, pcOp); + pcIsResp := isRdmaRespOp(pcOp); + pcRespOrCnp := pcIsResp or pcIsCnp; + pcSrqn := pcHdr(488 downto 465); -- xrceth.srqn + pcQkey := pcHdr(496 downto 465); -- deth.qkey + if (pcTrans = TRANS_TYPE_XRC_C) and (not pcRespOrCnp) then + pcDqpn := pcSrqn; + else + pcDqpn := pcBth(55 downto 32); -- bth.dqpn + end if; + getPdQpn <= pcDqpn; + + -- getQueuePairByQPN(dqpn) : dqpn from rdmaHeaderValidationQ head (checkMetaDataQP) + getQpQpn <= rdmaHeaderValidationQDout(60 downto 37); -- headerValidateInfo.dqpn + + -------------------------------------------------------------------- + -- Rule 1: recvPktFrag (table B row1) + -- SOLE consumer of payloadPipeIn; ALWAYS runs (fsm.md "keeps running"). + -- Invalid multi-fragment packets are drained downstream from payloadRecvQ + -- by discardInvalidFrag, NOT from payloadPipeIn (OQ-FSM-IRPB-02 fix — see + -- the file header). No pktBufState gate here: only one rule ever deqs + -- payloadPipeIn, so the PRE_CHECK→DISCARD race cannot occur. + -------------------------------------------------------------------- + frag := payloadBufDout; + isFirst := payloadBufDout(1); + isLast := payloadBufDout(0); + rHdr := rdmaHdrDout; + rBth := rHdr(592 downto 497); -- extractBTH(headerData) + aethCode:= rHdr(495 downto 494); + aethVal := rHdr(493 downto 489); + bthChk := ite(checkZeroFields4BTH(rBth), '1', '0'); + hdrChk := ite(padCntCheckReqHeader(rBth(92 downto 88), rBth(85 downto 84)) + or padCntCheckRespHeader(rBth(92 downto 88), rBth(85 downto 84), aethCode, aethVal), + '1', '0'); + -- nonPayloadHeaderShouldHaveNoPayload + if rHdr(1) = '1' then -- headerMetaData.hasPayload + nonPayOk := '1'; + elsif (isFirst = '1' and isLast = '1' and isZeroByteEn(frag(33 downto 2))) then + nonPayOk := '1'; + else + nonPayOk := '0'; + end if; + + -- canFire: buffer notEmpty AND payloadRecvQ notFull; on isFirst also header + -- pipe notEmpty AND rdmaHeaderRecvQ notFull. + canFire := (payloadBufValid = '1') and (payloadRecvQNotFull = '1'); + if isFirst = '1' then + canFire := canFire and (rdmaHdrValid = '1') and (rdmaHeaderRecvQNotFull = '1'); + end if; + if canFire then + payloadBufRdEn <= '1'; + payloadRecvQWrEn <= '1'; + payloadRecvQDin <= frag; + if isFirst = '1' then + rdmaHdrRdEn <= '1'; + rdmaHeaderRecvQWrEn <= '1'; + rdmaHeaderRecvQDin <= rHdr & rBth & bthChk & hdrChk & nonPayOk; + end if; + end if; + + -------------------------------------------------------------------- + -- Rule 2: preCheckHeader (table A rows 1-4; writes pktBufState → DISCARD) + -- guard pktBufState = PRE_CHECK_FRAG_S + -------------------------------------------------------------------- + if r.pktBufState = PRE_CHECK_FRAG_S then + frag := payloadRecvQDout; + isFirst := payloadRecvQDout(1); + isLast := payloadRecvQDout(0); + if isFirst = '1' then + -- needs rdmaHeaderRecvQ head; header-valid → forward, else discard + rHdr := rdmaHeaderRecvQDout(RECV_W_C-1 downto RECV_W_C-HDR_W_C); -- [691:99] + rBth := rdmaHeaderRecvQDout(98 downto 3); + bthChk := rdmaHeaderRecvQDout(2); + hdrChk := rdmaHeaderRecvQDout(1); + nonPayOk := rdmaHeaderRecvQDout(0); + if (bthChk = '1' and hdrChk = '1' and nonPayOk = '1') then + -- valid header: forward to preCheck queues (needs both notFull) + canFire := (payloadRecvQValid = '1') and (rdmaHeaderRecvQValid = '1') + and (rdmaHeaderPreCheckQNotFull = '1') and (payloadPreCheckQNotFull = '1'); + if canFire then + payloadRecvQRdEn <= '1'; + rdmaHeaderRecvQRdEn <= '1'; + rdmaHeaderPreCheckQWrEn <= '1'; + rdmaHeaderPreCheckQDin <= rHdr & rBth; + payloadPreCheckQWrEn <= '1'; + payloadPreCheckQDin <= frag; + end if; + else + -- invalid header: drop header+frag; multi-frag → enter DISCARD + canFire := (payloadRecvQValid = '1') and (rdmaHeaderRecvQValid = '1'); + if canFire then + payloadRecvQRdEn <= '1'; + rdmaHeaderRecvQRdEn <= '1'; + if isLast = '0' then + v.pktBufState := DISCARD_FRAG_S; + end if; + end if; + end if; + else + -- non-first fragment: forward payload only + canFire := (payloadRecvQValid = '1') and (payloadPreCheckQNotFull = '1'); + if canFire then + payloadRecvQRdEn <= '1'; + payloadPreCheckQWrEn <= '1'; + payloadPreCheckQDin <= frag; + end if; + end if; + end if; + + -------------------------------------------------------------------- + -- Rule 3: discardInvalidFrag (table A rows 5-6) + -- guard pktBufState = DISCARD_FRAG_S. Drains the invalid packet's + -- remaining fragments from payloadRecvQ (recvPktFrag already moved them + -- off payloadPipeIn). Mutually exclusive with preCheckHeader, which + -- reads payloadRecvQ only in PRE_CHECK_FRAG_S → a single payloadRecvQ + -- reader per state. OQ-FSM-IRPB-02 fix (was draining payloadPipeIn and + -- racing recvPktFrag on it). + -------------------------------------------------------------------- + if r.pktBufState = DISCARD_FRAG_S then + if payloadRecvQValid = '1' then + payloadRecvQRdEn <= '1'; -- drop fragment + if payloadRecvQDout(0) = '1' then -- isLast + v.pktBufState := PRE_CHECK_FRAG_S; + end if; + end if; + end if; + + -------------------------------------------------------------------- + -- Rule 4: prepareValidation (table B row2) + -------------------------------------------------------------------- + frag := payloadPreCheckQDout; + isFirst := payloadPreCheckQDout(1); + if isFirst = '1' then + canFire := (payloadPreCheckQValid = '1') and (rdmaHeaderPreCheckQValid = '1') + and (rdmaHeaderValidationQNotFull = '1') and (payloadValidationQNotFull = '1'); + if canFire then + -- headerValidateInfo built from pcHdr/pcBth (computed above for getPD) + hvi := (getPdMaybeValid & getPdHandler) -- maybePdHandler [93:61] + & pcDqpn -- dqpn [60:37] + & pcQkey -- qkeyDETH [36:5] + & ite(pcIsCnp, '1', '0') -- isCNP [4] + & ite(pcIsResp, '1', '0') -- isRespPkt [3] + & ite(isLastOp(pcOp), '1', '0') -- isLastPkt [2] + & ite(isFirstOrMidOp(pcOp), '1', '0') -- isFirstOrMidPkt [1] + & ite(isLastOrOnlyOp(pcOp), '1', '0');-- isLastOrOnlyPkt [0] + payloadPreCheckQRdEn <= '1'; + rdmaHeaderPreCheckQRdEn <= '1'; + rdmaHeaderValidationQWrEn <= '1'; + rdmaHeaderValidationQDin <= pcHdr & pcBth & hvi; + payloadValidationQWrEn <= '1'; + payloadValidationQDin <= frag; + end if; + else + canFire := (payloadPreCheckQValid = '1') and (payloadValidationQNotFull = '1'); + if canFire then + payloadPreCheckQRdEn <= '1'; + payloadValidationQWrEn <= '1'; + payloadValidationQDin <= frag; + end if; + end if; + + -------------------------------------------------------------------- + -- Rule 5: checkMetaDataQP (table B row3) + -------------------------------------------------------------------- + frag := payloadValidationQDout; + isFirst := payloadValidationQDout(1); + vHdr := rdmaHeaderValidationQDout(VALID_W_C-1 downto VALID_W_C-HDR_W_C); -- [782:190] + vBth := rdmaHeaderValidationQDout(189 downto 94); + vHvi := rdmaHeaderValidationQDout(93 downto 0); + vMaybe := vHvi(93); + pdHandler := vHvi(92 downto 61); + vDqpn := vHvi(60 downto 37); + vQkey := vHvi(36 downto 5); + vIsCnp := vHvi(4); + vIsResp:= vHvi(3); + vResp := vIsResp or vIsCnp; + if vResp = '1' then + selTypeQP := sqTypeQP; selERR := sqIsERR; selRTS := sqIsRTS; + selNonErr := sqIsNonErr; selQKEY := sqQKEY; + else + selTypeQP := rqTypeQP; selERR := rqIsERR; selRTS := rqIsRTS; + selNonErr := rqIsNonErr; selQKEY := rqQKEY; + end if; + if vMaybe = '1' then + isValidHdr := ite(validateHeader(vBth(95 downto 93), vQkey, selTypeQP, + selERR, selRTS, selNonErr, selQKEY, vResp), '1', '0'); + else + isValidHdr := '0'; + pdHandler := (others => '0'); -- dontCareValue + end if; + if isFirst = '1' then + canFire := (payloadValidationQValid = '1') and (rdmaHeaderValidationQValid = '1') + and (rdmaHeaderFilterQNotFull = '1') and (payloadFilterQNotFull = '1'); + if canFire then + vhInfo := pdHandler -- pdHandler [64:33] + & vDqpn -- dqpn [32:9] + & sqPMTU -- pmtu (always from SQ) [8:6] + & isValidHdr -- isValidHeader [5] + & vIsCnp -- isCNP [4] + & vIsResp -- isRespPkt [3] + & vHvi(2) -- isLastPkt [2] + & vHvi(1) -- isFirstOrMidPkt [1] + & vHvi(0); -- isLastOrOnlyPkt [0] + payloadValidationQRdEn <= '1'; + rdmaHeaderValidationQRdEn <= '1'; + rdmaHeaderFilterQWrEn <= '1'; + rdmaHeaderFilterQDin <= vHdr & vBth & vhInfo; + payloadFilterQWrEn <= '1'; + payloadFilterQDin <= frag; + end if; + else + canFire := (payloadValidationQValid = '1') and (payloadFilterQNotFull = '1'); + if canFire then + payloadValidationQRdEn <= '1'; + payloadFilterQWrEn <= '1'; + payloadFilterQDin <= frag; + end if; + end if; + + -------------------------------------------------------------------- + -- Rule 6: discardInvalidHeaderPkt (table B row4; writes isValidPktReg; CNP fork) + -------------------------------------------------------------------- + frag := payloadFilterQDout; + isFirst := payloadFilterQDout(1); + fHdr := rdmaHeaderFilterQDout(FILT_W_C-1 downto FILT_W_C-HDR_W_C); -- [753:161] + fBth := rdmaHeaderFilterQDout(160 downto 65); + fVhi := rdmaHeaderFilterQDout(64 downto 0); + fIsValidHdr := fVhi(5); + fIsCnp := fVhi(4); + cnpIdx := ite(MAX_QP_G > 1, to_integer(unsigned(fBth(55 downto 56-QP_IDX_W_C))), 0); -- getIndexQP(bth.dqpn): dqpn=[55:32], top log2(MAX_QP_G) bits; constant 0 at MAX_QP_G=1 + if isFirst = '1' then + isValidEff := fIsValidHdr and (not fIsCnp); + else + isValidEff := r.isValidPkt; + end if; + needFrag := (isFirst = '1') and (fIsValidHdr = '1') and (fIsCnp = '0'); + needCnp := (isFirst = '1') and (fIsValidHdr = '1') and (fIsCnp = '1'); + needPay := (isValidEff = '1'); + fragOk := (not needFrag) or (rdmaHeaderFragLenCalcQNotFull = '1'); + cnpOk := (not needCnp) or (cnpNotFullA(cnpIdx) = '1'); + payOk := (not needPay) or (payloadFragLenCalcQNotFull = '1'); + canFire := (payloadFilterQValid = '1') and fragOk and cnpOk and payOk; + if isFirst = '1' then + canFire := canFire and (rdmaHeaderFilterQValid = '1'); + end if; + if canFire then + payloadFilterQRdEn <= '1'; + if isFirst = '1' then + rdmaHeaderFilterQRdEn <= '1'; + v.isValidPkt := isValidEff; + if needFrag then + rdmaHeaderFragLenCalcQWrEn <= '1'; + rdmaHeaderFragLenCalcQDin <= fHdr & fBth & fVhi; + elsif needCnp then + cnpWrEnA(cnpIdx) <= '1'; + cnpDinA(cnpIdx) <= fBth; + end if; + end if; + if needPay then + payloadFragLenCalcQWrEn <= '1'; + payloadFragLenCalcQDin <= frag; + end if; + end if; + + -------------------------------------------------------------------- + -- Rule 7: calcFraglen (table B row5; writes bthPadCntReg) + -------------------------------------------------------------------- + frag := payloadFragLenCalcQDout; + isFirst := payloadFragLenCalcQDout(1); + clHdr := rdmaHeaderFragLenCalcQDout(FILT_W_C-1 downto FILT_W_C-HDR_W_C); + clBth := rdmaHeaderFragLenCalcQDout(160 downto 65); + clVhi := rdmaHeaderFragLenCalcQDout(64 downto 0); + if isFirst = '1' then + clPadCnt := clBth(85 downto 84); + else + clPadCnt := r.bthPadCnt; + end if; + fbn := calcFragByteNum(frag(33 downto 2)); + fragLen := fbn.num; + byteEnNZ := ite(not isZeroByteEn(frag(33 downto 2)), '1', '0'); + byteEnAll := ite(frag(33 downto 2) = BYTEEN_ONES_C, '1', '0'); + fragLenNoPad := slv(unsigned(fragLen) - resize(unsigned(clPadCnt), 6)); -- fragLen - zeroExt(bthPadCnt) + canFire := (payloadFragLenCalcQValid = '1') and (payloadPktLenCalcQNotFull = '1'); + if isFirst = '1' then + canFire := canFire and (rdmaHeaderFragLenCalcQValid = '1') and (rdmaHeaderPktLenCalcQNotFull = '1'); + end if; + if canFire then + payloadFragLenCalcQRdEn <= '1'; + if isFirst = '1' then + rdmaHeaderFragLenCalcQRdEn <= '1'; + v.bthPadCnt := clPadCnt; + rdmaHeaderPktLenCalcQWrEn <= '1'; + rdmaHeaderPktLenCalcQDin <= clHdr & clBth & clVhi; + end if; + payloadPktLenCalcQWrEn <= '1'; + payloadPktLenCalcQDin <= frag & fragLen & fragLenNoPad & byteEnNZ & byteEnAll; + end if; + + -------------------------------------------------------------------- + -- Rule 8: calcPktLen (table B row6 + datapath sub-table) + -- reads rdmaHeaderPktLenCalcQ head every fire; deq only on isLast. + -------------------------------------------------------------------- + pFrag := payloadPktLenCalcQDout(PLC_W_C-1 downto PLC_W_C-DS_W_C); -- [303:14] + pFragLen := payloadPktLenCalcQDout(13 downto 8); + pFragLenNoPad := payloadPktLenCalcQDout(7 downto 2); + pByteEnNZ := payloadPktLenCalcQDout(1); + pByteEnAll := payloadPktLenCalcQDout(0); + pIsFirst := pFrag(1); + pIsLast := pFrag(0); + pHdr := rdmaHeaderPktLenCalcQDout(FILT_W_C-1 downto FILT_W_C-HDR_W_C); + pBth := rdmaHeaderPktLenCalcQDout(160 downto 65); + pVhi := rdmaHeaderPktLenCalcQDout(64 downto 0); + pIsRespPkt := pVhi(3); + pIsLastPkt := pVhi(2); + pIsFirstOrMid := pVhi(1); + pIsLastOrOnly := pVhi(0); + pQpIdx := ite(MAX_QP_G > 1, to_integer(unsigned(pVhi(32 downto 33-QP_IDX_W_C))), 0); -- getIndexQP(vhi.dqpn): dqpn=[32:9], top log2(MAX_QP_G) bits; constant 0 at MAX_QP_G=1 + -- {isFirst,isLast} case + if (pIsFirst = '1') and (pIsLast = '1') then + newPktLen := slv(resize(unsigned(pFragLenNoPad), 13)); + newFragNum := slv(to_unsigned(1, 8)); + if pIsFirstOrMid = '1' then + newValid := '0'; + elsif pIsLastPkt = '1' then + newValid := pByteEnNZ; + else + newValid := '1'; + end if; + elsif (pIsFirst = '1') and (pIsLast = '0') then + newPktLen := slv(to_unsigned(32, 13)); -- DATA_BUS_BYTE_WIDTH + newFragNum := slv(to_unsigned(1, 8)); + newValid := pByteEnAll; + elsif (pIsFirst = '0') and (pIsLast = '1') then + newPktLen := pktLenAddFragLen(r.pktLen, pFragLenNoPad); + newFragNum := slv(unsigned(r.pktFragNum) + 1); + newValid := r.pktValid; + else + newPktLen := pktLenAddBusByteWidth(r.pktLen); + newFragNum := slv(unsigned(r.pktFragNum) + 1); + newValid := r.pktValid and pByteEnAll; + end if; + canFire := (payloadPktLenCalcQValid = '1') and (rdmaHeaderPktLenCalcQValid = '1') + and (payloadPktLenPreCheckQNotFull = '1'); + if pIsLast = '1' then + canFire := canFire and (rdmaHeaderPktLenPreCheckQNotFull = '1'); + end if; + if canFire then + payloadPktLenCalcQRdEn <= '1'; + v.pktLen := newPktLen; + v.pktValid := newValid; + v.pktFragNum := newFragNum; + if pIsLast = '1' then + rdmaHeaderPktLenCalcQRdEn <= '1'; + plci := pBth(95 downto 93) -- trans + & pBth(92 downto 88) -- opcode + & pBth(85 downto 84) -- padCnt + & pBth(23 downto 0) -- psn + & pVhi(32 downto 9) -- dqpn + & pHdr -- rdmaHeader + & pVhi(64 downto 33) -- pdHandler + & newFragNum -- pktFragNum + & newPktLen -- pktLen + & pVhi(8 downto 6) -- pmtu + & newValid -- pktValid + & pIsFirstOrMid -- isFirstOrMidPkt + & pIsLastOrOnly; -- isLastOrOnlyPkt + rdmaHeaderPktLenPreCheckQWrEn <= '1'; + rdmaHeaderPktLenPreCheckQDin <= plci; + end if; + payloadPktLenPreCheckQWrEn <= '1'; + -- qpIdx field: constant 0 at MAX_QP_G=1 (getIndexQP of a 0-bit index) + payloadPktLenPreCheckQDin <= pFrag & ite(MAX_QP_G > 1, pVhi(32 downto 33-QP_IDX_W_C), "0") & pIsRespPkt; + end if; + + -------------------------------------------------------------------- + -- Rule 9: preCheckPktLen (table B row7) + -------------------------------------------------------------------- + preFrag := payloadPktLenPreCheckQDout(PL3_W_C-1 downto QP_IDX_W_C+1); + preQpIdx := payloadPktLenPreCheckQDout(QP_IDX_W_C downto 1); + preIsResp:= payloadPktLenPreCheckQDout(0); + preIsLast:= preFrag(0); + prePlci := rdmaHeaderPktLenPreCheckQDout; + isZeroLen := ite(unsigned(prePlci(18 downto 6)) = 0, '1', '0'); -- isZeroR(pktLen) + isEqPMTU := ite(pktLenEqPMTU(prePlci(18 downto 6), prePlci(5 downto 3)), '1', '0'); + isGtPMTU := ite(pktLenGtPMTU(prePlci(18 downto 6), prePlci(5 downto 3)), '1', '0'); + canFire := (payloadPktLenPreCheckQValid = '1') and (payloadPktLenCheckQNotFull = '1'); + if preIsLast = '1' then + canFire := canFire and (rdmaHeaderPktLenPreCheckQValid = '1') and (rdmaHeaderPktLenCheckQNotFull = '1'); + end if; + if canFire then + payloadPktLenPreCheckQRdEn <= '1'; + if preIsLast = '1' then + rdmaHeaderPktLenPreCheckQRdEn <= '1'; + rdmaHeaderPktLenCheckQWrEn <= '1'; + rdmaHeaderPktLenCheckQDin <= prePlci & isZeroLen & isEqPMTU & isGtPMTU; + end if; + payloadPktLenCheckQWrEn <= '1'; + payloadPktLenCheckQDin <= preFrag & preQpIdx & preIsResp; + end if; + + -------------------------------------------------------------------- + -- Rule 10: checkPktLen (table B row8; builds RdmaPktMetaData, PMTU verdict) + -------------------------------------------------------------------- + ckFrag := payloadPktLenCheckQDout(PL3_W_C-1 downto QP_IDX_W_C+1); + ckQpIdx := payloadPktLenCheckQDout(QP_IDX_W_C downto 1); + ckIsResp:= payloadPktLenCheckQDout(0); + ckIsLast:= ckFrag(0); + ckPlci := rdmaHeaderPktLenCheckQDout(PCHK4_W_C-1 downto 3); + ckZeroLen := rdmaHeaderPktLenCheckQDout(2); + ckEqPMTU := rdmaHeaderPktLenCheckQDout(1); + ckGtPMTU := rdmaHeaderPktLenCheckQDout(0); + -- pktValid recompute (only meaningful when plci.pktValid; else stays false) + if ckPlci(2) = '1' then + ckValid := ite(((ckPlci(1) = '1') and (ckEqPMTU = '1')) + or ((ckPlci(0) = '1') and (ckGtPMTU = '0')), '1', '0'); + else + ckValid := '0'; + end if; + ckStatus := ite(ckValid = '1', PKT_ST_VALID_C, PKT_ST_LEN_ERR_C); + -- RdmaPktMetaData + meta := ckPlci(18 downto 6) -- pktPayloadLen (pktLen) + & ite(ckZeroLen = '1', slv(to_unsigned(0, 8)), ckPlci(26 downto 19)) -- pktFragNum + & ckZeroLen -- isZeroPayloadLen + & ckPlci(651 downto 59) -- pktHeader (rdmaHeader) + & ckPlci(58 downto 27) -- pdHandler + & ckValid -- pktValid + & ckStatus; -- pktStatus + if ckIsLast = '1' then + -- enq rdmaHeaderOutputQ always; enq payloadOutputQ only if !isZeroPayloadLen + canFire := (payloadPktLenCheckQValid = '1') and (rdmaHeaderPktLenCheckQValid = '1') + and (rdmaHeaderOutputQNotFull = '1'); + if ckZeroLen = '0' then + canFire := canFire and (payloadOutputQNotFull = '1'); + end if; + if canFire then + payloadPktLenCheckQRdEn <= '1'; + rdmaHeaderPktLenCheckQRdEn<= '1'; + rdmaHeaderOutputQWrEn <= '1'; + rdmaHeaderOutputQDin <= meta & ckQpIdx & ckIsResp; + if ckZeroLen = '0' then + payloadOutputQWrEn <= '1'; + payloadOutputQDin <= ckFrag & ckQpIdx & ckIsResp; + end if; + end if; + else + canFire := (payloadPktLenCheckQValid = '1') and (payloadOutputQNotFull = '1'); + if canFire then + payloadPktLenCheckQRdEn <= '1'; + payloadOutputQWrEn <= '1'; + payloadOutputQDin <= ckFrag & ckQpIdx & ckIsResp; + end if; + end if; + + -------------------------------------------------------------------- + -- Rule 11: outputPayload (table B row9) + -------------------------------------------------------------------- + oQpIdx := to_integer(unsigned(payloadOutputQDout(QP_IDX_W_C downto 1))); + oIsResp := payloadOutputQDout(0); + if payloadOutputQValid = '1' then + if oIsResp = '1' then + if respPayloadNotFullA(oQpIdx) = '1' then + payloadOutputQRdEn <= '1'; + respPayloadWrEnA(oQpIdx) <= '1'; + respPayloadDinA(oQpIdx) <= payloadOutputQDout(PL3_W_C-1 downto QP_IDX_W_C+1); + end if; + else + if reqPayloadNotFullA(oQpIdx) = '1' then + payloadOutputQRdEn <= '1'; + reqPayloadWrEnA(oQpIdx) <= '1'; + reqPayloadDinA(oQpIdx) <= payloadOutputQDout(PL3_W_C-1 downto QP_IDX_W_C+1); + end if; + end if; + end if; + + -------------------------------------------------------------------- + -- Rule 12: outputHeaderMetaData (table B row10) + -------------------------------------------------------------------- + oQpIdx := to_integer(unsigned(rdmaHeaderOutputQDout(QP_IDX_W_C downto 1))); + oIsResp := rdmaHeaderOutputQDout(0); + if rdmaHeaderOutputQValid = '1' then + if oIsResp = '1' then + if respMetaNotFullA(oQpIdx) = '1' then + rdmaHeaderOutputQRdEn <= '1'; + respMetaWrEnA(oQpIdx) <= '1'; + respMetaDinA(oQpIdx) <= rdmaHeaderOutputQDout(HDROUT_W_C-1 downto QP_IDX_W_C+1); + end if; + else + if reqMetaNotFullA(oQpIdx) = '1' then + rdmaHeaderOutputQRdEn <= '1'; + reqMetaWrEnA(oQpIdx) <= '1'; + reqMetaDinA(oQpIdx) <= rdmaHeaderOutputQDout(HDROUT_W_C-1 downto QP_IDX_W_C+1); + end if; + end if; + end if; + + -- synchronous reset + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd b/ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd new file mode 100644 index 0000000000..7a919b1783 --- /dev/null +++ b/ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd @@ -0,0 +1,737 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Cross-SGE byte-shift merge. The byte stream of each SGE (scatter/gather +-- element) within one SGL is generally not bus-width aligned at its last +-- fragment. This module concatenates the partial last fragment of one SGE +-- with the first fragment(s) of the next SGE so the emitted DataStream is +-- densely packed across SGE boundaries, re-marking isFirst/isLast at SGL +-- granularity. 3-stage feed-forward pipeline: +-- Stage A handleMetaDataEachSGE — turns per-SGE MergedMetaDataSGE into a +-- TmpMergedMetaDataSGE, accumulating cross-SGE misalignment +-- (preInvalid*Reg). State-independent producer for +-- U_MergedMetaDataQ4EachSGE. +-- Stage B stateReg control FSM (mergePayloadInit / mergeFirstOrMidSGE / +-- mergeLastOrOnlySGE) — consumes payload fragments + Stage-A +-- metadata, computes the merged fragment and per-fragment left +-- shift amounts; producer for U_PayloadFragShiftQ. +-- Stage C shiftPayloadFrag — applies the barrel left-shift+merge and emits +-- the final DataStream. State-independent consumer of +-- U_PayloadFragShiftQ; producer for U_PktPayloadOutQ. +-- The two state-independent rules (A, C) may fire on the same cycle as +-- whichever Stage-B rule is active (disjoint registers / FIFO ports). +-- +-- Two upstream PipeOut arguments are CONSUMED (NOT FIFOs instantiated here): +-- sgeMergedMetaDataPipeIn : PipeOut#(MergedMetaDataSGE) (8-bit meta word) +-- sgeMergedPayloadPipeIn : PipeOut#(DataStream) (290-bit payload). +-- This pipe is the OUTPUT of the SIBLING MergePayloadEachSge entity wired +-- by the parent (OQ-FSM-MPAS-01) — it is NOT a submodule of this entity. +-- One output PipeOut#(DataStream) is returned (read side of U_PktPayloadOutQ). +-- +-- Mapping note (OQ-FSM-MPAS-01): mapping.json / modules.json are entirely +-- wrong for this entity (fabricated single rule `crossMerge`, nonexistent +-- `crossQ`/`carryReg`, a bogus MergePayloadEachSge child instance). This +-- file follows MergePayloadAllSge.fsm.md, which is authoritative. +-- +-- DEVIATION-MPAS-01 (deliberate fix of a latent upstream BSV bug): +-- preprocessNextSGL holds the payload flit (empty prePayloadFrag, no deq) +-- for ANY non-only single-flit first SGE, whereas BSV holds only when the +-- flit is partial (hasLessFrag=1). The literal BSV dequeues a FULL-width +-- single-flit first SGE at INIT, desynchronising the SGE bookkeeping by one +-- SGE and deadlocking at end-of-SGL (terminal fragment held with isLast +-- stripped). Upstream blue-rdma has the identical code and its tests never +-- cover this input. Details in MergePayloadAllSge.result.md (TC-09/TC-10). +-- +-- Width / packing resolutions applied: +-- - DataStream width = 290 bits (OQ-FSM-H2DS-02 / MPAS-02 RESOLVED) +-- - all struct/tuple packing first-field-at-MSB +-- (OQ-FSM-H2DS-04 / MPAS-02 RESOLVED) +-- +-- Atomicity / stall (OQ-FSM-MPAS-04): +-- - mergeLastOrOnlySGE's final payloadFragShiftQ.enq is UNCONDITIONAL in +-- BSV, so a full U_PayloadFragShiftQ stalls the WHOLE rule — including the +-- stateReg transition and prePayloadFragReg/deq. Modelled by gating EVERY +-- register update of that rule on fragShiftQFull='0' (branch B also needs +-- sgeMergedPayloadPipeInValid='1'). +-- - mergeFirstOrMidSGE's enq is nested under `if (shouldOutput)`. Per the +-- RESOLVED OQ-FSM-MPAS-04(a) decision the overall rule enable is +-- `(shouldOutput='1') ? fragShiftQNotFull : '1'`; ALL effects (payload +-- deq, prePayloadFragReg, preprocessNextSGE state/reg writes) key off this +-- single enable — gating only the enq would be a partial-fire bug. +-- +-- FIFO clear (OQ-FSM-MPAS-03 RESOLVED): surf.Fifo has no clear port; BSV +-- FIFOF.clear is modelled by asserting the synchronous rst. All three FIFOs +-- share fifoRst = rst OR clearAllI (level-safe with FifoSync). +-- +-- Bit layouts (BSV deriving(Bits), first-field-at-MSB): +-- DataStream (290): [289:34] data[255:0] | [33:2] byteEn[31:0] | +-- [1] isFirst | [0] isLast +-- MergedMetaDataSGE (8): [7:2] lastFragValidByteNum[5:0] | +-- [1] isFirst | [0] isLast +-- TmpMergedMetaDataSGE (34): +-- [33:28] lastFragInvalidByteNum[5:0] | [27:19] lastFragInvalidBitNum[8:0] | +-- [18:13] curInvalidByteNum[5:0] | [12:4] curInvalidBitNum[8:0] | +-- [3] isOnlySGE | [2] sgeIsFirst | [1] sgeIsLast | [0] hasLessFrag +-- payloadFragShiftQ Tuple4 (595): +-- [594:305] prePayloadFrag (DataStream) | [304:15] curPayloadFrag | +-- [14:9] leftShiftInvalidByteNum[5:0] | [8:0] leftShiftInvalidBitNum[8:0] +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_PktPayloadOutQ : surf.Fifo DATA_WIDTH_G=290 (output queue, exposed) +-- U_MergedMetaDataQ4EachSGE : surf.Fifo DATA_WIDTH_G=34 (internal pipeline) +-- U_PayloadFragShiftQ : surf.Fifo DATA_WIDTH_G=595 (internal pipeline) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity MergePayloadAllSge is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (BSV constructor parameter clearAll : Bool) + clearAllI : in sl; + -- Upstream: MergedMetaDataSGE pipe (sgeMergedMetaDataPipeIn argument) + sgeMergedMetaDataPipeInValid : in sl; -- sgeMergedMetaDataPipeIn.notEmpty + sgeMergedMetaDataPipeInData : in slv(7 downto 0); -- sgeMergedMetaDataPipeIn.first + sgeMergedMetaDataPipeInRdEn : out sl; -- sgeMergedMetaDataPipeIn.deq + -- Upstream: DataStream payload pipe (sgeMergedPayloadPipeIn argument, + -- driven by the sibling MergePayloadEachSge entity) + sgeMergedPayloadPipeInValid : in sl; -- sgeMergedPayloadPipeIn.notEmpty + sgeMergedPayloadPipeInData : in slv(289 downto 0);-- sgeMergedPayloadPipeIn.first + sgeMergedPayloadPipeInRdEn : out sl; -- sgeMergedPayloadPipeIn.deq + -- Downstream: returned PipeOut#(DataStream) (read side of U_PktPayloadOutQ) + pktPayloadOutValid : out sl; -- PipeOut.notEmpty + pktPayloadOutData : out slv(289 downto 0);-- PipeOut.first + pktPayloadOutRdEn : in sl); -- PipeOut.deq +end entity MergePayloadAllSge; + +architecture rtl of MergePayloadAllSge is + + -- Maps BSV MergePayloadStateAllSGE: + -- MERGE_SGL_PAYLOAD_INIT -> INIT_S + -- MERGE_SGL_PAYLOAD_FIRST_OR_MID_SGE -> FIRST_OR_MID_SGE_S + -- MERGE_SGL_PAYLOAD_LAST_OR_ONLY_SGE -> LAST_OR_ONLY_SGE_S + type StateType is (INIT_S, FIRST_OR_MID_SGE_S, LAST_OR_ONLY_SGE_S); + + type RegType is record + state : StateType; -- mkReg(MERGE_SGL_PAYLOAD_INIT) + -- Stage-B context registers (all mkRegU) + prePayloadFrag : slv(289 downto 0); -- mkRegU (DataStream) + lastFragInvalidByteNum : slv(5 downto 0); -- mkRegU (ByteEnBitNum) + lastFragInvalidBitNum : slv(8 downto 0); -- mkRegU (BusBitNum) + curInvalidByteNum : slv(5 downto 0); -- mkRegU (ByteEnBitNum) + curInvalidBitNum : slv(8 downto 0); -- mkRegU (BusBitNum) + isFirstFrag : sl; -- mkRegU + sgeIsOnly : sl; -- mkRegU + sgeIsLast : sl; -- mkRegU (DEAD: written, never read; kept for source fidelity, OQ-FSM-MPAS-04b) + hasLessFrag : sl; -- mkRegU + -- Stage-A cross-SGE accumulator (mkRegU) + preInvalidByteNum : slv(5 downto 0); -- mkRegU (ByteEnBitNum) + preInvalidBitNum : slv(8 downto 0); -- mkRegU (BusBitNum) + end record RegType; + + -- All mkRegU fields set to '0' in REG_INIT_C: each is written by its + -- preprocess*/Stage-A producer before any consumer reads it (pipeline + -- ordering guarantees write-before-read; preInvalid* is read only on + -- !sgeIsFirst, which follows a sgeIsFirst write). Reset value is don't-care. + constant REG_INIT_C : RegType := ( + state => INIT_S, + prePayloadFrag => (others => '0'), + lastFragInvalidByteNum => (others => '0'), + lastFragInvalidBitNum => (others => '0'), + curInvalidByteNum => (others => '0'), + curInvalidBitNum => (others => '0'), + isFirstFrag => '0', + sgeIsOnly => '0', + sgeIsLast => '0', + hasLessFrag => '0', + preInvalidByteNum => (others => '0'), + preInvalidBitNum => (others => '0')); + + constant DATA_BUS_BYTE_WIDTH_C : natural := 32; -- DATA_BUS_BYTE_WIDTH + constant DATA_BUS_WIDTH_C : natural := 256; -- DATA_BUS_WIDTH + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Shared synchronous clear for all three FIFOs (rst OR clearAllI) + signal fifoRst : sl; + + -- U_MergedMetaDataQ4EachSGE control / status (internal pipeline FIFO) + signal metaQWrEn : sl; + signal metaQDin : slv(33 downto 0); + signal metaQRdEn : sl; + signal metaQDout : slv(33 downto 0); + signal metaQValid : sl; + signal metaQFull : sl; + + -- U_PayloadFragShiftQ control / status (internal pipeline FIFO) + signal fragShiftQWrEn : sl; + signal fragShiftQDin : slv(594 downto 0); + signal fragShiftQRdEn : sl; + signal fragShiftQDout : slv(594 downto 0); + signal fragShiftQValid : sl; + signal fragShiftQFull : sl; + + -- U_PktPayloadOutQ control / status (output queue; read side exposed) + signal pktPayloadOutQWrEn : sl; + signal pktPayloadOutQDin : slv(289 downto 0); + signal pktPayloadOutQFull : sl; + + -- preprocessNextSGL (PayloadGen.bsv:1300): pops mergedMetaDataQ4EachSGE + -- (deq asserted by caller) and conditionally the payload pipe, sets the + -- per-SGE context registers + next stateReg, and returns the next + -- prePayloadFrag value via retFrag (the caller writes prePayloadFragReg). + -- deqPayload reports whether the payload pipe must be dequeued this cycle. + procedure preprocessNextSGL ( + variable v : inout RegType; + signal mDout : in slv(33 downto 0); + signal payloadData : in slv(289 downto 0); + variable retFrag : out slv(289 downto 0); + variable deqPayload : out sl) is + variable lastInvByte : slv(5 downto 0); + variable lastInvBit : slv(8 downto 0); + variable isOnlySGEIn : sl; + variable sgeIsLastIn : sl; + variable curIsLast : sl; + variable nextHasLess : sl; + begin + lastInvByte := mDout(33 downto 28); + lastInvBit := mDout(27 downto 19); + -- mDout(18:13) curInvalidByteNum / mDout(12:4) curInvalidBitNum unused + -- here; mDout(0) hasLessFrag deliberately unused (DEVIATION-MPAS-01) + isOnlySGEIn := mDout(3); + sgeIsLastIn := mDout(1); + curIsLast := payloadData(0); + + v.sgeIsOnly := isOnlySGEIn; + v.sgeIsLast := sgeIsLastIn; + v.isFirstFrag := '1'; + + -- If this SGE is a single fragment (and not the only SGE of the SGL), + -- hold an empty prePayloadFrag and wait for the first fragment of the + -- next SGE to merge. BSV additionally requires hasLessFrag=1 here + -- (partial last fragment); that is a latent upstream bug for a FULL-width + -- single-flit first SGE (hasLessFrag=0): the flit would be dequeued now, + -- making every later meta pop lag one SGE behind, so mergeFirstOrMidSGE + -- eventually strips isLast off the SGL's true terminal fragment and + -- mergeLastOrOnlySGE then waits forever for payload that never comes + -- (deadlock; SqSendQ TC-03). Holding for ANY non-only single-flit SGE + -- keeps the invariant "the meta pop happens on the SGE's own last flit"; + -- the mergeFirstOrMidSGE shift by lastFragInvalid* (=0 when full-width) + -- reconstructs the held flit exactly, so partial-SGE behaviour is + -- unchanged. See DEVIATION-MPAS-01 in MergePayloadAllSge.result.md. + if (isOnlySGEIn = '0') and (curIsLast = '1') then + retFrag := (others => '0'); -- genEmptyDataStream + deqPayload := '0'; -- no payload deq + nextHasLess := '1'; + else + retFrag := payloadData; -- unmodified + deqPayload := '1'; + nextHasLess := '0'; + end if; + + v.hasLessFrag := nextHasLess; + v.lastFragInvalidByteNum := lastInvByte; + v.lastFragInvalidBitNum := lastInvBit; + if nextHasLess = '1' then + v.curInvalidByteNum := std_logic_vector(to_unsigned(DATA_BUS_BYTE_WIDTH_C, 6)); -- 32 + v.curInvalidBitNum := std_logic_vector(to_unsigned(DATA_BUS_WIDTH_C, 9)); -- 256 + else + v.curInvalidByteNum := (others => '0'); + v.curInvalidBitNum := (others => '0'); + end if; + + -- nextState = {sgeIsFirst,sgeIsLast} in {11,01}->LAST ; {10,00}->FIRST + -- (depends only on sgeIsLast) + if sgeIsLastIn = '1' then + v.state := LAST_OR_ONLY_SGE_S; + else + v.state := FIRST_OR_MID_SGE_S; + end if; + end procedure preprocessNextSGL; + + -- preprocessNextSGE (PayloadGen.bsv:1373): pops mergedMetaDataQ4EachSGE (deq + -- asserted by caller) and loads the next-SGE context registers + stateReg. + -- No payload deq, no returned fragment. + procedure preprocessNextSGE ( + variable v : inout RegType; + signal mDout : in slv(33 downto 0)) is + variable lastInvByte : slv(5 downto 0); + variable lastInvBit : slv(8 downto 0); + variable curInvByte : slv(5 downto 0); + variable curInvBit : slv(8 downto 0); + variable sgeIsLastIn : sl; + variable hasLessIn : sl; + begin + lastInvByte := mDout(33 downto 28); + lastInvBit := mDout(27 downto 19); + curInvByte := mDout(18 downto 13); + curInvBit := mDout(12 downto 4); + sgeIsLastIn := mDout(1); + hasLessIn := mDout(0); + + v.sgeIsLast := sgeIsLastIn; + v.hasLessFrag := hasLessIn; + v.lastFragInvalidByteNum := lastInvByte; + v.lastFragInvalidBitNum := lastInvBit; + v.curInvalidByteNum := curInvByte; + v.curInvalidBitNum := curInvBit; + + if sgeIsLastIn = '1' then + v.state := LAST_OR_ONLY_SGE_S; + else + v.state := FIRST_OR_MID_SGE_S; + end if; + end procedure preprocessNextSGE; + +begin + + -- FIFO reset: level-sensitive synchronous clear (OQ-FSM-MPAS-03 RESOLVED). + -- resetAndClear calls .clear on all three FIFOs while clearAllI='1'. + fifoRst <= rst or clearAllI; + + --------------------------------------------------------------------------- + -- U_MergedMetaDataQ4EachSGE : surf.Fifo + -- Internal pipeline FIFO; produced by handleMetaDataEachSGE (Stage A), + -- consumed by preprocessNextSGL/SGE (Stage B). DATA_WIDTH_G=34, FWFT, + -- sync, distributed RAM. + --------------------------------------------------------------------------- + U_MergedMetaDataQ4EachSGE : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 34, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => metaQWrEn, + din => metaQDin, + full => metaQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => metaQRdEn, + dout => metaQDout, + valid => metaQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_PayloadFragShiftQ : surf.Fifo + -- Internal pipeline FIFO; produced by mergeFirstOrMidSGE / + -- mergeLastOrOnlySGE (Stage B), consumed by shiftPayloadFrag (Stage C). + -- DATA_WIDTH_G=595, FWFT, sync, block RAM (wide word). + --------------------------------------------------------------------------- + U_PayloadFragShiftQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 595, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => fragShiftQWrEn, + din => fragShiftQDin, + full => fragShiftQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => fragShiftQRdEn, + dout => fragShiftQDout, + valid => fragShiftQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_PktPayloadOutQ : surf.Fifo + -- Output queue; its read side IS the returned PipeOut#(DataStream). + -- Produced by shiftPayloadFrag (Stage C). DATA_WIDTH_G=290, FWFT, sync, + -- block RAM. + --------------------------------------------------------------------------- + U_PktPayloadOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 290, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pktPayloadOutQWrEn, + din => pktPayloadOutQDin, + full => pktPayloadOutQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pktPayloadOutRdEn, + dout => pktPayloadOutData, + valid => pktPayloadOutValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, clearAllI, + sgeMergedMetaDataPipeInValid, sgeMergedMetaDataPipeInData, + sgeMergedPayloadPipeInValid, sgeMergedPayloadPipeInData, + metaQValid, metaQDout, metaQFull, + fragShiftQValid, fragShiftQDout, fragShiftQFull, + pktPayloadOutQFull) is + variable v : RegType; + + -- Stage A (handleMetaDataEachSGE) locals + variable lastFragValidByteNum : slv(5 downto 0); + variable aIsFirst : sl; + variable aIsLast : sl; + variable aIsOnly : sl; + variable aLastInvByte : slv(5 downto 0); + variable aLastInvBit : slv(8 downto 0); + variable aHasLessFrag : sl; + variable aCurInvByte : slv(5 downto 0); + variable aCurInvBit : slv(8 downto 0); + variable aPreInvByte : slv(5 downto 0); + variable aPreInvBit : slv(8 downto 0); + variable aSumInvByte : slv(5 downto 0); + variable aSumInvBit : slv(8 downto 0); + + -- Stage B (control FSM) locals + variable curIsLast : sl; + variable shouldOutput : sl; + variable ruleFire : sl; + variable preIsLast : sl; + variable isLastFrag : sl; + variable nextPre : slv(289 downto 0); + variable nextFrag : slv(289 downto 0); + variable retFrag : slv(289 downto 0); + variable deqPayload : sl; + variable outPre : slv(289 downto 0); + variable bByteEnCat : slv(63 downto 0); + variable bDataCat : slv(511 downto 0); + variable bShByteEn : slv(63 downto 0); + variable bShData : slv(511 downto 0); + + -- Stage C (shiftPayloadFrag / leftShiftAndMergeFragData) locals + variable cPreData : slv(255 downto 0); + variable cCurData : slv(255 downto 0); + variable cPreByteEn : slv(31 downto 0); + variable cCurByteEn : slv(31 downto 0); + variable cShByteNum : slv(4 downto 0); -- truncate(6->5) ShiftByteNum + variable cShBitNum : slv(7 downto 0); -- truncate(9->8) ShiftBitNum + variable cByteEnCat : slv(63 downto 0); + variable cDataCat : slv(511 downto 0); + variable cShByteEn : slv(63 downto 0); + variable cShData : slv(511 downto 0); + variable cOutFrag : slv(289 downto 0); + begin + v := r; + + -- default Mealy outputs (deasserted; overridden below per transition) + sgeMergedMetaDataPipeInRdEn <= '0'; + sgeMergedPayloadPipeInRdEn <= '0'; + metaQWrEn <= '0'; + metaQDin <= (others => '0'); + metaQRdEn <= '0'; + fragShiftQWrEn <= '0'; + fragShiftQDin <= (others => '0'); + fragShiftQRdEn <= '0'; + pktPayloadOutQWrEn <= '0'; + pktPayloadOutQDin <= (others => '0'); + + if clearAllI = '1' then + -- resetAndClear: FIFOs flushed via fifoRst; stateReg forced to INIT_S. + -- The mkRegU context registers are deliberately untouched (matches BSV; + -- they are rewritten by the next preprocess* before any read). + v.state := INIT_S; + + else + + ------------------------------------------------------------------- + -- Stage A : handleMetaDataEachSGE (state-independent producer) + -- guard: sgeMergedMetaDataPipeInValid='1' AND metaQFull='0' + ------------------------------------------------------------------- + if sgeMergedMetaDataPipeInValid = '1' and metaQFull = '0' then + lastFragValidByteNum := sgeMergedMetaDataPipeInData(7 downto 2); + aIsFirst := sgeMergedMetaDataPipeInData(1); + aIsLast := sgeMergedMetaDataPipeInData(0); + aIsOnly := aIsFirst and aIsLast; + + -- calcFragBitNumAndByteNum(lastFragValidByteNum): + -- invalidByteNum = 32 - valid ; invalidBitNum = invalidByteNum<<3 + aLastInvByte := std_logic_vector(to_unsigned(DATA_BUS_BYTE_WIDTH_C, 6) - unsigned(lastFragValidByteNum)); + aLastInvBit := aLastInvByte & "000"; + + -- hasLessFrag / cur / pre defaults (sgeIsFirst path) + aHasLessFrag := ite(unsigned(lastFragValidByteNum) < DATA_BUS_BYTE_WIDTH_C, '1', '0'); + aCurInvByte := (others => '0'); + aCurInvBit := (others => '0'); + aPreInvByte := aLastInvByte; + aPreInvBit := aLastInvBit; + + if aIsFirst = '0' then + -- accumulate cross-SGE misalignment from preInvalid*Reg (OLD) + aHasLessFrag := ite(unsigned(r.preInvalidByteNum) >= unsigned(lastFragValidByteNum), '1', '0'); + aSumInvByte := std_logic_vector(unsigned(r.preInvalidByteNum) + unsigned(aLastInvByte)); + aSumInvBit := std_logic_vector(unsigned(r.preInvalidBitNum) + unsigned(aLastInvBit)); + aCurInvByte := r.preInvalidByteNum; + aCurInvBit := r.preInvalidBitNum; + aPreInvByte := '0' & aSumInvByte(4 downto 0); -- AND busByteNumMask (0x1F) + aPreInvBit := '0' & aSumInvBit(7 downto 0); -- AND busBitNumMask (0xFF) + end if; + + v.preInvalidByteNum := aPreInvByte; + v.preInvalidBitNum := aPreInvBit; + + sgeMergedMetaDataPipeInRdEn <= '1'; + metaQWrEn <= '1'; + metaQDin <= aLastInvByte -- [33:28] + & aLastInvBit -- [27:19] + & aCurInvByte -- [18:13] + & aCurInvBit -- [12:4] + & aIsOnly -- [3] + & aIsFirst -- [2] + & aIsLast -- [1] + & aHasLessFrag; -- [0] + end if; + + ------------------------------------------------------------------- + -- Stage B : control FSM + -- (mergePayloadInit / mergeFirstOrMidSGE / mergeLastOrOnlySGE) + -- All register reads below use OLD (r) values (BSV semantics). + ------------------------------------------------------------------- + case r.state is + + -- ============================================================ + -- INIT_S : mergePayloadInit (preprocessNextSGL) + -- implicit cond: metaQValid='1' AND sgeMergedPayloadPipeInValid='1' + -- ============================================================ + when INIT_S => + if metaQValid = '1' and sgeMergedPayloadPipeInValid = '1' then + metaQRdEn <= '1'; + preprocessNextSGL(v, metaQDout, sgeMergedPayloadPipeInData, retFrag, deqPayload); + if deqPayload = '1' then + sgeMergedPayloadPipeInRdEn <= '1'; + end if; + v.prePayloadFrag := retFrag; + end if; + + -- ============================================================ + -- FIRST_OR_MID_SGE_S : mergeFirstOrMidSGE (+preprocessNextSGE) + -- Overall enable (OQ-FSM-MPAS-04a RESOLVED): + -- sgePayloadValid AND (curIsLast='0' OR metaQValid) + -- AND (shouldOutput='0' OR fragShiftQNotFull) + -- ============================================================ + when FIRST_OR_MID_SGE_S => + curIsLast := sgeMergedPayloadPipeInData(0); + if curIsLast = '1' then + shouldOutput := not r.hasLessFrag; + else + shouldOutput := '1'; + end if; + + ruleFire := '0'; + if sgeMergedPayloadPipeInValid = '1' + and (curIsLast = '0' or metaQValid = '1') + and (shouldOutput = '0' or fragShiftQFull = '0') then + ruleFire := '1'; + end if; + + if ruleFire = '1' then + sgeMergedPayloadPipeInRdEn <= '1'; + + if curIsLast = '1' then + -- preprocessNextSGE advances state + loads next-SGE regs + metaQRdEn <= '1'; + preprocessNextSGE(v, metaQDout); + + -- nextPrePayloadFrag = curPayloadFrag, isLast:=0, byteEn/data + -- = truncate({pre,cur} >> lastFragInvalid*Reg[OLD]) (low bits) + bByteEnCat := r.prePayloadFrag(33 downto 2) & sgeMergedPayloadPipeInData(33 downto 2); + bShByteEn := std_logic_vector(shift_right(unsigned(bByteEnCat), to_integer(unsigned(r.lastFragInvalidByteNum)))); + bDataCat := r.prePayloadFrag(289 downto 34) & sgeMergedPayloadPipeInData(289 downto 34); + bShData := std_logic_vector(shift_right(unsigned(bDataCat), to_integer(unsigned(r.lastFragInvalidBitNum)))); + + nextPre := bShData(255 downto 0) -- data [289:34] + & bShByteEn(31 downto 0) -- byteEn [33:2] + & sgeMergedPayloadPipeInData(1) -- isFirst (kept from cur) + & '0'; -- isLast := 0 + else + nextPre := sgeMergedPayloadPipeInData; -- unmodified, stay + end if; + v.prePayloadFrag := nextPre; + + if shouldOutput = '1' then + v.isFirstFrag := '0'; + -- enq first elem = prePayloadFragReg[OLD] with + -- isFirst:=isFirstFragReg[OLD], isLast:=0 + outPre := r.prePayloadFrag(289 downto 2) & r.isFirstFrag & '0'; + fragShiftQWrEn <= '1'; + fragShiftQDin <= outPre -- [594:305] + & sgeMergedPayloadPipeInData -- [304:15] curPayloadFrag (raw) + & r.curInvalidByteNum -- [14:9] + & r.curInvalidBitNum; -- [8:0] + end if; + end if; + + -- ============================================================ + -- LAST_OR_ONLY_SGE_S : mergeLastOrOnlySGE + -- Whole-rule gate (enq unconditional, OQ-FSM-MPAS-04a): + -- fragShiftQNotFull AND (preIsLast='1' OR sgePayloadValid) + -- ============================================================ + when LAST_OR_ONLY_SGE_S => + preIsLast := r.prePayloadFrag(0); + + ruleFire := '0'; + if fragShiftQFull = '0' + and (preIsLast = '1' or sgeMergedPayloadPipeInValid = '1') then + ruleFire := '1'; + end if; + + if ruleFire = '1' then + isLastFrag := preIsLast; -- isLastFrag = prePayloadFragReg.isLast + nextFrag := (others => '0'); -- genEmptyDataStream default + + if preIsLast = '1' then + -- Branch A + if metaQValid = '1' and sgeMergedPayloadPipeInValid = '1' then + -- A1: start the next SGE (also of next SGL) + metaQRdEn <= '1'; + preprocessNextSGL(v, metaQDout, sgeMergedPayloadPipeInData, retFrag, deqPayload); + if deqPayload = '1' then + sgeMergedPayloadPipeInRdEn <= '1'; + end if; + nextFrag := retFrag; + else + -- A2: no next SGE yet -> wait in INIT_S (empty frag) + v.state := INIT_S; + end if; + else + -- Branch B: needs sgePayloadPipeInValid (deqs it) + sgeMergedPayloadPipeInRdEn <= '1'; + nextFrag := sgeMergedPayloadPipeInData(289 downto 2) & '0' & sgeMergedPayloadPipeInData(0); -- isFirst:=0 + if r.sgeIsOnly = '0' and r.hasLessFrag = '1' and nextFrag(0) = '1' then + -- B1: one less fragment -> finish this SGE + v.state := INIT_S; + isLastFrag := '1'; + end if; + -- B2: isLastFrag stays preIsLast (= 0 in branch B) + end if; + + v.prePayloadFrag := nextFrag; + -- enq first elem = prePayloadFragReg[OLD] with isLast:=isLastFrag + outPre := r.prePayloadFrag(289 downto 1) & isLastFrag; + fragShiftQWrEn <= '1'; + fragShiftQDin <= outPre -- [594:305] + & nextFrag -- [304:15] + & r.curInvalidByteNum -- [14:9] + & r.curInvalidBitNum; -- [8:0] + end if; + + end case; + + ------------------------------------------------------------------- + -- Stage C : shiftPayloadFrag (state-independent consumer) + -- guard: fragShiftQValid='1' AND pktPayloadOutQFull='0' + -- outPayloadFrag = leftShiftAndMergeFragData(pre, cur, + -- truncate(lsByteNum), truncate(lsBitNum)) + ------------------------------------------------------------------- + if fragShiftQValid = '1' and pktPayloadOutQFull = '0' then + -- Slice the 595-bit element + cPreData := fragShiftQDout(594 downto 339); -- prePayloadFrag.data + cPreByteEn := fragShiftQDout(338 downto 307); -- prePayloadFrag.byteEn + cCurData := fragShiftQDout(304 downto 49); -- curPayloadFrag.data + cCurByteEn := fragShiftQDout( 48 downto 17); -- curPayloadFrag.byteEn + cShByteNum := fragShiftQDout(13 downto 9); -- truncate(leftShiftInvByteNum 6->5) + cShBitNum := fragShiftQDout( 7 downto 0); -- truncate(leftShiftInvBitNum 9->8) + + -- byteEn: truncateLSB({pre,cur} << shByteNum) -> top 32 of 64 + cByteEnCat := cPreByteEn & cCurByteEn; + cShByteEn := std_logic_vector(shift_left(unsigned(cByteEnCat), to_integer(unsigned(cShByteNum)))); + -- data: truncateLSB({pre,cur} << shBitNum) -> top 256 of 512 + cDataCat := cPreData & cCurData; + cShData := std_logic_vector(shift_left(unsigned(cDataCat), to_integer(unsigned(cShBitNum)))); + + -- isFirst/isLast kept from preFrag + cOutFrag := cShData(511 downto 256) -- data [289:34] + & cShByteEn(63 downto 32) -- byteEn [33:2] + & fragShiftQDout(306) -- isFirst (prePayloadFrag.isFirst) + & fragShiftQDout(305); -- isLast (prePayloadFrag.isLast) + + fragShiftQRdEn <= '1'; + pktPayloadOutQWrEn <= '1'; + pktPayloadOutQDin <= cOutFrag; + end if; + + end if; + + -- Synchronous reset (stateReg = mkReg(MERGE_SGL_PAYLOAD_INIT)) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd b/ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd new file mode 100644 index 0000000000..baa0a54fe9 --- /dev/null +++ b/ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd @@ -0,0 +1,687 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Merges the raw payload DataStream of one Scatter/Gather Element (SGE) across +-- packet boundaries: it drops the trailing invalid bytes of each packet's last +-- fragment and shifts the next packet's first fragment up to fill them, so the +-- SGE's payload becomes a single gap-free DataStream sequence. +-- +-- Two upstream PipeOut arguments are consumed (NOT FIFOs instantiated here): +-- sgePktMetaDataPipeIn : PipeOut#(PktMetaDataSGE) (54-bit meta word) +-- sgePayloadPipeIn : PipeOut#(DataStream) (290-bit payload flit) +-- One output PipeOut#(DataStream) is returned (read side of U_PktPayloadOutQ). +-- +-- FOUR rule groups (fsm.md §transition table): +-- resetAndClear (guard clearAllI) — flush all 3 FIFOs, force INIT_S. +-- handleEachPktMetaData4SGE — state-independent producer for +-- U_SgeCurPktMetaDataQ. +-- mergePayloadInit / mergeFirstOrMidPktSGE / mergeLastOrOnlyPktSGE — +-- the 3-state stateReg FSM; producer for +-- U_PayloadFragShiftQ. +-- shiftPayloadFrag — state-independent consumer of +-- U_PayloadFragShiftQ, producer for +-- U_PktPayloadOutQ. +-- The two state-independent rules can fire on the same cycle as whichever +-- state-dependent rule is active (disjoint FIFOs / registers). +-- +-- Mapping note (OQ-FSM-MPES-01): mapping.json / modules.json are entirely +-- wrong for this entity (fabricated single rule `merge`, nonexistent +-- `shiftReg`/`mergeQ`, missing 2 of 3 FIFOs and 5 of 6 rules). This file +-- follows MergePayloadEachSge.fsm.md, which is authoritative. +-- +-- Width / packing resolutions applied: +-- - DataStream width = 290 bits (OQ-FSM-H2DS-02 / MPES-02 RESOLVED) +-- - all struct/tuple packing first-field-at-MSB +-- (OQ-FSM-H2DS-04 / MPES-04 RESOLVED) +-- +-- Atomicity / stall (OQ-FSM-MPES-03): mergeLastOrOnlyPktSGE's final +-- payloadFragShiftQ.enq is unconditional in BSV, so the WHOLE rule — +-- including the stateReg transition decided by branches A/B — fails to fire +-- when payloadFragShiftQFull='1'. Modelled here by gating EVERY register +-- update of that rule (state, prePayloadFrag, …) on fragShiftQFull='0', not +-- merely the FIFO write-enable. Branch B additionally requires +-- sgePayloadPipeInValid='1' (it deqs the payload pipe unconditionally). +-- +-- FIFO clear (OQ-FSM-01 RESOLVED): surf.Fifo has no clear port; BSV +-- FIFOF.clear is modelled by asserting the synchronous rst. All three +-- FIFOs share fifoRst = rst OR clearAllI (level-safe with FifoSync). +-- +-- Bit layouts (BSV deriving(Bits), first-field-at-MSB): +-- DataStream (290): [289:34] data[255:0] | [33:2] byteEn[31:0] | +-- [1] isFirst | [0] isLast +-- PktMetaDataSGE (54): [53:41] firstPktLen[12:0] | [40:28] lastPktLen[12:0] | +-- [27:3] sgePktNum[24:0] | [2:0] pmtu[2:0] +-- sgeCurPktMetaDataQ Tuple6 (43): +-- [42:37] firstPktLastFragInvalidByteNum[5:0] | +-- [36:28] firstPktLastFragInvalidBitNum[8:0] | +-- [27:3] sgePktNum[24:0] | [2] sgeHasJustTwoPkts | +-- [1] sgeHasOnlyPkt | [0] hasExtraFrag +-- payloadFragShiftQ Tuple4 (595): +-- [594:305] prePayloadFrag (DataStream) | [304:15] curPayloadFrag | +-- [14:9] leftShiftInvalidByteNum[5:0] | [8:0] leftShiftInvalidBitNum[8:0] +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_PktPayloadOutQ : surf.Fifo DATA_WIDTH_G=290 (output queue, exposed) +-- U_SgeCurPktMetaDataQ : surf.Fifo DATA_WIDTH_G=43 (internal pipeline) +-- U_PayloadFragShiftQ : surf.Fifo DATA_WIDTH_G=595 (internal pipeline) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity MergePayloadEachSge is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (BSV constructor parameter clearAll : Bool) + clearAllI : in sl; + -- Upstream: PktMetaDataSGE pipe (sgePktMetaDataPipeIn argument) + sgePktMetaDataPipeInValid : in sl; -- sgePktMetaDataPipeIn.notEmpty + sgePktMetaDataPipeInData : in slv(53 downto 0);-- sgePktMetaDataPipeIn.first + sgePktMetaDataPipeInRdEn : out sl; -- sgePktMetaDataPipeIn.deq + -- Upstream: DataStream payload pipe (sgePayloadPipeIn argument) + sgePayloadPipeInValid : in sl; -- sgePayloadPipeIn.notEmpty + sgePayloadPipeInData : in slv(289 downto 0);-- sgePayloadPipeIn.first + sgePayloadPipeInRdEn : out sl; -- sgePayloadPipeIn.deq + -- Downstream: returned PipeOut#(DataStream) (read side of U_PktPayloadOutQ) + pktPayloadOutValid : out sl; -- PipeOut.notEmpty + pktPayloadOutData : out slv(289 downto 0);-- PipeOut.first + pktPayloadOutRdEn : in sl); -- PipeOut.deq +end entity MergePayloadEachSge; + +architecture rtl of MergePayloadEachSge is + + -- Maps BSV MergePayloadStateEachSGE: + -- MERGE_SGE_PAYLOAD_INIT -> INIT_S + -- MERGE_SGE_PAYLOAD_FIRST_OR_MID_PKT -> FIRST_OR_MID_PKT_S + -- MERGE_SGE_PAYLOAD_LAST_OR_ONLY_PKT -> LAST_OR_ONLY_PKT_S + type StateType is (INIT_S, FIRST_OR_MID_PKT_S, LAST_OR_ONLY_PKT_S); + + type RegType is record + state : StateType; -- mkReg(MERGE_SGE_PAYLOAD_INIT) + sgeFirstPktLastFragInvByteNum : slv(5 downto 0); -- mkRegU (ByteEnBitNum) + sgeFirstPktLastFragInvBitNum : slv(8 downto 0); -- mkRegU (BusBitNum) + sgeHasOnlyPkt : sl; -- mkRegU + hasExtraFrag : sl; -- mkRegU + isFirstFrag : sl; -- mkRegU + isFirstPkt : sl; -- mkRegU + remainingPktNum : slv(24 downto 0); -- mkRegU (PktNum) + prePayloadFrag : slv(289 downto 0);-- mkRegU (DataStream) + end record RegType; + + -- All mkRegU fields set to '0' in REG_INIT_C: each is written by + -- prepareNextSGE (the only path out of INIT_S) before any state-dependent + -- read, so the reset value is don't-care (no correctness risk). + constant REG_INIT_C : RegType := ( + state => INIT_S, + sgeFirstPktLastFragInvByteNum => (others => '0'), + sgeFirstPktLastFragInvBitNum => (others => '0'), + sgeHasOnlyPkt => '0', + hasExtraFrag => '0', + isFirstFrag => '0', + isFirstPkt => '0', + remainingPktNum => (others => '0'), + prePayloadFrag => (others => '0')); + + constant DATA_BUS_BYTE_WIDTH_C : natural := 32; -- DATA_BUS_BYTE_WIDTH + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Shared synchronous clear for all three FIFOs (rst OR clearAllI) + signal fifoRst : sl; + + -- U_SgeCurPktMetaDataQ control / status (internal pipeline FIFO) + signal sgeCurMetaQWrEn : sl; + signal sgeCurMetaQDin : slv(42 downto 0); + signal sgeCurMetaQRdEn : sl; + signal sgeCurMetaQDout : slv(42 downto 0); + signal sgeCurMetaQValid : sl; + signal sgeCurMetaQFull : sl; + + -- U_PayloadFragShiftQ control / status (internal pipeline FIFO) + signal fragShiftQWrEn : sl; + signal fragShiftQDin : slv(594 downto 0); + signal fragShiftQRdEn : sl; + signal fragShiftQDout : slv(594 downto 0); + signal fragShiftQValid : sl; + signal fragShiftQFull : sl; + + -- U_PktPayloadOutQ control / status (output queue; read side exposed) + signal pktPayloadOutQWrEn : sl; + signal pktPayloadOutQDin : slv(289 downto 0); + signal pktPayloadOutQFull : sl; + + -- calcLastFragValidByteNum(len) (Utils.bsv:165): residue = len(4:0); if the + -- residue is zero but len is a non-zero multiple of 32, the last fragment is + -- "full" (32 valid bytes), else the residue is the valid byte count. + function calcLastFragValidByteNum (len : slv(12 downto 0)) return slv is + variable residue : slv(4 downto 0); + variable result : slv(5 downto 0); + begin + residue := len(4 downto 0); + if (residue = "00000") and (len /= "0000000000000") then + result := std_logic_vector(to_unsigned(DATA_BUS_BYTE_WIDTH_C, 6)); -- 32 + else + result := '0' & residue; -- zero-extend 5->6 + end if; + return result; + end function calcLastFragValidByteNum; + + -- prepareNextSGE (PayloadGen.bsv:994): pops sgeCurPktMetaDataQ + the payload + -- pipe and sets up the per-SGE context registers + next stateReg. Returns + -- the next prePayloadFrag value through retFrag (the BSV function's + -- ActionValue result); the caller writes prePayloadFragReg, mirroring the BSV + -- (it does NOT write the register itself). The pops (deq) are asserted by the + -- caller, not here. + procedure prepareNextSGE ( + variable v : inout RegType; + signal metaQDout : in slv(42 downto 0); + signal payloadData : in slv(289 downto 0); + variable retFrag : out slv(289 downto 0)) is + variable invByteNumIn : slv(5 downto 0); + variable invBitNumIn : slv(8 downto 0); + variable pktNumIn : slv(24 downto 0); + variable hasJustTwoIn : sl; + variable hasOnlyIn : sl; + variable curIsLast : sl; + variable shiftedFrag : slv(289 downto 0); + begin + invByteNumIn := metaQDout(42 downto 37); + invBitNumIn := metaQDout(36 downto 28); + pktNumIn := metaQDout(27 downto 3); + hasJustTwoIn := metaQDout(2); + hasOnlyIn := metaQDout(1); + curIsLast := payloadData(0); + + -- Single-fragment first-packet shift: drop the invalid trailing bytes of + -- the first packet's last fragment. isLast forced to 0, isFirst kept. + shiftedFrag := + std_logic_vector(shift_right(unsigned(payloadData(289 downto 34)), to_integer(unsigned(invBitNumIn)))) -- data >> invBitNum + & std_logic_vector(shift_right(unsigned(payloadData(33 downto 2)), to_integer(unsigned(invByteNumIn)))) -- byteEn >> invByteNum + & payloadData(1) -- isFirst (unchanged) + & '0'; -- isLast := 0 + + -- Common register updates for every branch + v.sgeHasOnlyPkt := hasOnlyIn; + v.hasExtraFrag := metaQDout(0); + v.sgeFirstPktLastFragInvByteNum := invByteNumIn; + v.sgeFirstPktLastFragInvBitNum := invBitNumIn; + v.isFirstFrag := '1'; + + if hasOnlyIn = '1' then -- P1: only one packet in SGE + v.state := LAST_OR_ONLY_PKT_S; + v.remainingPktNum := (others => '0'); + v.isFirstPkt := '1'; + retFrag := payloadData; -- unmodified + elsif curIsLast = '1' then -- single-fragment first packet + retFrag := shiftedFrag; + v.isFirstPkt := '0'; + if hasJustTwoIn = '1' then -- P2: exactly two packets + v.state := LAST_OR_ONLY_PKT_S; + v.remainingPktNum := (others => '0'); + else -- P3: more than two packets + v.state := FIRST_OR_MID_PKT_S; + v.remainingPktNum := std_logic_vector(unsigned(pktNumIn) - 2); + end if; + else -- P4: multi-fragment first packet + v.state := FIRST_OR_MID_PKT_S; + v.remainingPktNum := std_logic_vector(unsigned(pktNumIn) - 1); + v.isFirstPkt := '1'; + retFrag := payloadData; -- unmodified + end if; + end procedure prepareNextSGE; + +begin + + -- FIFO reset: level-sensitive synchronous clear (OQ-FSM-01 RESOLVED). + -- resetAndClear calls .clear on all three FIFOs while clearAllI='1'. + fifoRst <= rst or clearAllI; + + --------------------------------------------------------------------------- + -- U_SgeCurPktMetaDataQ : surf.Fifo + -- Internal pipeline FIFO; produced by handleEachPktMetaData4SGE, consumed + -- by prepareNextSGE. DATA_WIDTH_G=43, FWFT, sync, distributed RAM. + --------------------------------------------------------------------------- + U_SgeCurPktMetaDataQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 43, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => sgeCurMetaQWrEn, + din => sgeCurMetaQDin, + full => sgeCurMetaQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => sgeCurMetaQRdEn, + dout => sgeCurMetaQDout, + valid => sgeCurMetaQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_PayloadFragShiftQ : surf.Fifo + -- Internal pipeline FIFO; produced by mergeFirstOrMidPktSGE / + -- mergeLastOrOnlyPktSGE, consumed by shiftPayloadFrag. + -- DATA_WIDTH_G=595, FWFT, sync, block RAM (wide word). + --------------------------------------------------------------------------- + U_PayloadFragShiftQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 595, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => fragShiftQWrEn, + din => fragShiftQDin, + full => fragShiftQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => fragShiftQRdEn, + dout => fragShiftQDout, + valid => fragShiftQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_PktPayloadOutQ : surf.Fifo + -- Output queue; its read side IS the returned PipeOut#(DataStream). + -- Produced by shiftPayloadFrag. DATA_WIDTH_G=290, FWFT, sync, block RAM. + --------------------------------------------------------------------------- + U_PktPayloadOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 290, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pktPayloadOutQWrEn, + din => pktPayloadOutQDin, + full => pktPayloadOutQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pktPayloadOutRdEn, + dout => pktPayloadOutData, + valid => pktPayloadOutValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, clearAllI, + sgePktMetaDataPipeInValid, sgePktMetaDataPipeInData, + sgePayloadPipeInValid, sgePayloadPipeInData, + sgeCurMetaQValid, sgeCurMetaQDout, sgeCurMetaQFull, + fragShiftQValid, fragShiftQDout, fragShiftQFull, + pktPayloadOutQFull) is + variable v : RegType; + + -- handleEachPktMetaData4SGE locals + variable firstPktLen : slv(12 downto 0); + variable lastPktLen : slv(12 downto 0); + variable metaPktNum : slv(24 downto 0); + variable firstValid : slv(5 downto 0); + variable lastValid : slv(5 downto 0); + variable firstInvByte : slv(5 downto 0); + variable firstInvBit : slv(8 downto 0); + variable hasJustTwoPkts : sl; + variable metaHasOnlyPkt : sl; + variable metaHasExtra : sl; + + -- main-FSM locals + variable retFrag : slv(289 downto 0); + variable nextFrag : slv(289 downto 0); + variable nextPre : slv(289 downto 0); + variable preFragWIsFirst : slv(289 downto 0); + variable preFragWIsLast : slv(289 downto 0); + variable curIsLast : sl; + variable preIsLast : sl; + variable isLastFrag : sl; + variable fire : sl; + variable lsByteNum : slv(5 downto 0); + variable lsBitNum : slv(8 downto 0); + + -- shiftPayloadFrag (leftShiftAndMergeFragData) locals + variable sPreData : slv(255 downto 0); + variable sCurData : slv(255 downto 0); + variable sPreByteEn : slv(31 downto 0); + variable sCurByteEn : slv(31 downto 0); + variable sShByteNum : slv(4 downto 0); -- truncate(6->5) ShiftByteNum + variable sShBitNum : slv(7 downto 0); -- truncate(9->8) ShiftBitNum + variable byteEnCat : slv(63 downto 0); + variable dataCat : slv(511 downto 0); + variable shByteEn : slv(63 downto 0); + variable shData : slv(511 downto 0); + variable outFrag : slv(289 downto 0); + begin + v := r; + + -- default Mealy outputs (deasserted; overridden below per transition) + sgePktMetaDataPipeInRdEn <= '0'; + sgePayloadPipeInRdEn <= '0'; + sgeCurMetaQWrEn <= '0'; + sgeCurMetaQDin <= (others => '0'); + sgeCurMetaQRdEn <= '0'; + fragShiftQWrEn <= '0'; + fragShiftQDin <= (others => '0'); + fragShiftQRdEn <= '0'; + pktPayloadOutQWrEn <= '0'; + pktPayloadOutQDin <= (others => '0'); + + if clearAllI = '1' then + -- resetAndClear: FIFOs flushed via fifoRst; stateReg forced to INIT_S. + -- The 8 mkRegU context registers are deliberately untouched (matches + -- BSV; they are rewritten by the next prepareNextSGE before any read). + v.state := INIT_S; + + else + + ------------------------------------------------------------------- + -- handleEachPktMetaData4SGE (state-independent producer) + -- guard: sgePktMetaDataPipeInValid='1' AND sgeCurMetaQFull='0' + ------------------------------------------------------------------- + if sgePktMetaDataPipeInValid = '1' and sgeCurMetaQFull = '0' then + firstPktLen := sgePktMetaDataPipeInData(53 downto 41); + lastPktLen := sgePktMetaDataPipeInData(40 downto 28); + metaPktNum := sgePktMetaDataPipeInData(27 downto 3); + + firstValid := calcLastFragValidByteNum(firstPktLen); + lastValid := calcLastFragValidByteNum(lastPktLen); + + -- calcFragBitNumAndByteNum(firstValid): invalidByteNum = 32 - valid, + -- invalidBitNum = invalidByteNum << 3. + firstInvByte := std_logic_vector(to_unsigned(DATA_BUS_BYTE_WIDTH_C, 6) - unsigned(firstValid)); + firstInvBit := firstInvByte & "000"; + + hasJustTwoPkts := ite(unsigned(metaPktNum) = 2, '1', '0'); + metaHasOnlyPkt := ite(unsigned(metaPktNum) <= 1, '1', '0'); + metaHasExtra := ite(unsigned(lastValid) > unsigned(firstInvByte), '1', '0'); + + sgePktMetaDataPipeInRdEn <= '1'; + sgeCurMetaQWrEn <= '1'; + sgeCurMetaQDin <= firstInvByte -- [42:37] + & firstInvBit -- [36:28] + & metaPktNum -- [27:3] + & hasJustTwoPkts -- [2] + & metaHasOnlyPkt -- [1] + & metaHasExtra; -- [0] + end if; + + ------------------------------------------------------------------- + -- Main 3-state FSM (mergePayloadInit / mergeFirstOrMidPktSGE / + -- mergeLastOrOnlyPktSGE) + ------------------------------------------------------------------- + case r.state is + + -- ============================================================ + -- INIT_S: mergePayloadInit + -- implicit cond: sgeCurMetaQValid='1' AND sgePayloadPipeInValid='1' + -- ============================================================ + when INIT_S => + if sgeCurMetaQValid = '1' and sgePayloadPipeInValid = '1' then + sgeCurMetaQRdEn <= '1'; + sgePayloadPipeInRdEn <= '1'; + prepareNextSGE(v, sgeCurMetaQDout, sgePayloadPipeInData, retFrag); + v.prePayloadFrag := retFrag; + end if; + + -- ============================================================ + -- FIRST_OR_MID_PKT_S: mergeFirstOrMidPktSGE + -- implicit cond: sgePayloadPipeInValid='1' AND fragShiftQFull='0' + -- All register reads below are OLD (r) values (BSV semantics). + -- ============================================================ + when FIRST_OR_MID_PKT_S => + if sgePayloadPipeInValid = '1' and fragShiftQFull = '0' then + sgePayloadPipeInRdEn <= '1'; + curIsLast := sgePayloadPipeInData(0); + + -- nextPrePayloadFrag computation (BSV lines 1109-1126) + if curIsLast = '0' then + nextPre := sgePayloadPipeInData; -- unmodified, stay + else + if r.isFirstPkt = '1' then + -- first packet's last fragment: drop invalid trailing + -- bytes (right shift), force isLast=0; isFirstPkt -> 0 + v.isFirstPkt := '0'; + nextPre := + std_logic_vector(shift_right(unsigned(sgePayloadPipeInData(289 downto 34)), to_integer(unsigned(r.sgeFirstPktLastFragInvBitNum)))) + & std_logic_vector(shift_right(unsigned(sgePayloadPipeInData(33 downto 2)), to_integer(unsigned(r.sgeFirstPktLastFragInvByteNum)))) + & sgePayloadPipeInData(1) + & '0'; + else + nextPre := sgePayloadPipeInData(289 downto 1) & '0'; -- isLast := 0 only + end if; + if unsigned(r.remainingPktNum) <= 1 then + v.state := LAST_OR_ONLY_PKT_S; + end if; + v.remainingPktNum := std_logic_vector(unsigned(r.remainingPktNum) - 1); + end if; + v.prePayloadFrag := nextPre; + + -- payloadFragShiftQ.enq (BSV lines 1137-1151) + -- first elem = prePayloadFragReg[old] with isFirst:=isFirstFragReg[old] + -- second elem = curPayloadFrag (raw, unmodified) + -- leftShift = (!isFirstPktReg[old]) ? invByteNum/BitNum[old] : 0 + preFragWIsFirst := r.prePayloadFrag(289 downto 2) & r.isFirstFrag & r.prePayloadFrag(0); + v.isFirstFrag := '0'; + if r.isFirstPkt = '0' then + lsByteNum := r.sgeFirstPktLastFragInvByteNum; + lsBitNum := r.sgeFirstPktLastFragInvBitNum; + else + lsByteNum := (others => '0'); + lsBitNum := (others => '0'); + end if; + fragShiftQWrEn <= '1'; + fragShiftQDin <= preFragWIsFirst -- [594:305] + & sgePayloadPipeInData -- [304:15] + & lsByteNum -- [14:9] + & lsBitNum; -- [8:0] + end if; + + -- ============================================================ + -- LAST_OR_ONLY_PKT_S: mergeLastOrOnlyPktSGE + -- Branch selector = prePayloadFragReg.isLast (OLD). The WHOLE + -- rule (incl. stateReg) is gated on fragShiftQFull='0' + -- (OQ-FSM-MPES-03); Branch B additionally needs the payload pipe. + -- ============================================================ + when LAST_OR_ONLY_PKT_S => + preIsLast := r.prePayloadFrag(0); + isLastFrag := preIsLast; -- BSV: isLastFrag = prePayloadFragReg.isLast + nextFrag := (others => '0'); -- BSV: nextPayloadFrag = genEmptyDataStream + fire := '0'; + + if preIsLast = '1' then + -- Branch A: fires whenever fragShiftQFull='0' (A1 or A2) + if fragShiftQFull = '0' then + fire := '1'; + if sgeCurMetaQValid = '1' and sgePayloadPipeInValid = '1' then + -- A1: start the next SGE + sgeCurMetaQRdEn <= '1'; + sgePayloadPipeInRdEn <= '1'; + prepareNextSGE(v, sgeCurMetaQDout, sgePayloadPipeInData, retFrag); + nextFrag := retFrag; + else + -- A2: no next SGE yet -> wait in INIT_S (empty frag) + v.state := INIT_S; + end if; + end if; + else + -- Branch B: needs sgePayloadPipeInValid (deqs it) AND room + if sgePayloadPipeInValid = '1' and fragShiftQFull = '0' then + fire := '1'; + sgePayloadPipeInRdEn <= '1'; + -- nextPayloadFrag = sgePayloadPipeIn.first, isFirst forced 0 + nextFrag := sgePayloadPipeInData(289 downto 2) & '0' & sgePayloadPipeInData(0); + if r.sgeHasOnlyPkt = '0' and r.hasExtraFrag = '0' and nextFrag(0) = '1' then + -- B1: no extra fragment -> finish this SGE + v.state := INIT_S; + isLastFrag := '1'; + else + -- B2: more fragments to come + isLastFrag := '0'; + end if; + end if; + end if; + + -- Common tail (BSV lines 1189-1215): only when the rule fires. + if fire = '1' then + v.prePayloadFrag := nextFrag; + -- enq first elem = prePayloadFragReg[old] with isLast:=isLastFrag + preFragWIsLast := r.prePayloadFrag(289 downto 1) & isLastFrag; + -- leftShift = (!sgeHasOnlyPktReg[old]) ? invByteNum/BitNum[old] : 0 + if r.sgeHasOnlyPkt = '0' then + lsByteNum := r.sgeFirstPktLastFragInvByteNum; + lsBitNum := r.sgeFirstPktLastFragInvBitNum; + else + lsByteNum := (others => '0'); + lsBitNum := (others => '0'); + end if; + fragShiftQWrEn <= '1'; + fragShiftQDin <= preFragWIsLast -- [594:305] + & nextFrag -- [304:15] + & lsByteNum -- [14:9] + & lsBitNum; -- [8:0] + end if; + + end case; + + ------------------------------------------------------------------- + -- shiftPayloadFrag (state-independent consumer) + -- guard: fragShiftQValid='1' AND pktPayloadOutQFull='0' + -- outPayloadFrag = leftShiftAndMergeFragData(pre, cur, + -- truncate(lsByteNum), truncate(lsBitNum)) + ------------------------------------------------------------------- + if fragShiftQValid = '1' and pktPayloadOutQFull = '0' then + -- Slice the 595-bit element + sPreData := fragShiftQDout(594 downto 339); -- prePayloadFrag.data + sPreByteEn := fragShiftQDout(338 downto 307); -- prePayloadFrag.byteEn + sCurData := fragShiftQDout(304 downto 49); -- curPayloadFrag.data + sCurByteEn := fragShiftQDout( 48 downto 17); -- curPayloadFrag.byteEn + sShByteNum := fragShiftQDout(13 downto 9); -- truncate(leftShiftInvByteNum 6->5) + sShBitNum := fragShiftQDout( 7 downto 0); -- truncate(leftShiftInvBitNum 9->8) + + -- byteEn: truncateLSB({pre,cur} << shByteNum) -> top 32 of 64 + byteEnCat := sPreByteEn & sCurByteEn; + shByteEn := std_logic_vector(shift_left(unsigned(byteEnCat), to_integer(unsigned(sShByteNum)))); + -- data: truncateLSB({pre,cur} << shBitNum) -> top 256 of 512 + dataCat := sPreData & sCurData; + shData := std_logic_vector(shift_left(unsigned(dataCat), to_integer(unsigned(sShBitNum)))); + + -- isFirst/isLast kept from preFrag + outFrag := shData(511 downto 256) -- data [289:34] + & shByteEn(63 downto 32) -- byteEn [33:2] + & fragShiftQDout(306) -- isFirst (prePayloadFrag.isFirst) + & fragShiftQDout(305); -- isLast (prePayloadFrag.isLast) + + fragShiftQRdEn <= '1'; + pktPayloadOutQWrEn <= '1'; + pktPayloadOutQDin <= outFrag; + end if; + + end if; + + -- Synchronous reset (stateReg = mkReg(MERGE_SGE_PAYLOAD_INIT)) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + --------------------------------------------------------------------------- + -- Simulation-only assertions (sim-only immAssert calls, no synth effect): + -- mergeFirstOrMidPktSGE: remainingPktNumReg /= 0 when the rule fires. + -- mergeLastOrOnlyPktSGE: remainingPktNumReg = 0 when the rule fires. + --------------------------------------------------------------------------- + -- pragma translate_off + check : process (clk) is + begin + if rising_edge(clk) then + if rst = '0' and clearAllI = '0' then + if (r.state = FIRST_OR_MID_PKT_S + and sgePayloadPipeInValid = '1' and fragShiftQFull = '0') then + assert unsigned(r.remainingPktNum) /= 0 + report "MergePayloadEachSge: remainingPktNum must be > 0 in FIRST_OR_MID_PKT_S" + severity error; + end if; + if (r.state = LAST_OR_ONLY_PKT_S) then + assert unsigned(r.remainingPktNum) = 0 + report "MergePayloadEachSge: remainingPktNum must be 0 in LAST_OR_ONLY_PKT_S" + severity error; + end if; + end if; + end if; + end process check; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/MetaDataMRs.vhd b/ethernet/RoCEv2/rtl/MetaDataMRs.vhd new file mode 100644 index 0000000000..b27ed3c9ba --- /dev/null +++ b/ethernet/RoCEv2/rtl/MetaDataMRs.vhd @@ -0,0 +1,205 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Stateless, purely combinational adapter around a single child entity +-- instance `U_MrTagVec : TagVecSrv#(MAX_MR_PER_PD, MemRegion)`. This entity +-- has NO rules, NO registers, and NO SURF primitives of its own +-- (surf_instances: []); all sequential behaviour (the insert/remove FSM, the +-- tag/data register array, the req/resp FIFOs) lives inside the child +-- TagVecSrv (see out/04-vhdl/TagVecSrv.vhd). Therefore there is no RegType / +-- REG_INIT_C / two-process FSM here, exactly as the Stage-3 FSM spec directs +-- ("a thin wrapping architecture ... no RegType, no two-process FSM"). +-- +-- MetaDataMRs only: +-- 1. Request path : translate an MR key -> MR index +-- (key2IndexMR = top MR_INDEX_WIDTH bits of the 32-bit key), then forward +-- {allocOrNot, mr, mrIndex} to the child request port. +-- 2. Response path: reconstruct local/remote keys from the child response +-- (genLocalAndRmtKey = {mrIndex, mr.lkeyPart} / {mrIndex, mr.rkeyPart}). +-- 3. Lookup : a combinational getItem read (getMemRegionByLKey / +-- getMemRegionByRKey) — see the shared-port note below. +-- 4. Forward clear / notEmpty / notFull straight through to the child. +-- +-- Struct widths (traced from MetaData.bsv / DataTypes.bsv / Headers.bsv, +-- first-field-at-MSB BSV pack convention — project convention OQ-FSM-H2DS-04): +-- MemRegion = 186 b : laddr[185:122] len[121:90] accFlags[89:82] +-- pdHandler[81:50] lkeyPart[49:25] rkeyPart[24:0] +-- ReqMR = 252 b : allocOrNot[251] mr[250:65] lkeyOrNot[64] +-- lkey[63:32] rkey[31:0] +-- RespMR = 251 b : successOrNot[250] mr[249:64] lkey[63:32] rkey[31:0] +-- MR_INDEX_WIDTH = TLog#(MAX_MR_PER_PD=128) = 7 (KEY_WIDTH = 32) +-- Child TagVecSrv interface words (V_SZ_G=128 -> log2=7, T_SZ_G=186): +-- reqData = {allocOrNot[193], mr[192:7], mrIndex[6:0]} (194 b) +-- respData = {successOrNot[193], mrIndex[192:186], mr[185:0]} (194 b) +-- getItemOut = {valid[186], dataVec[185:0]} (187 b) +-- +-- getItem SHARED-PORT NOTE (OQ-FSM-MR-03, RESOLVED at emit — shared+select): +-- The BSV module exposes TWO combinational lookup methods +-- (getMemRegionByLKey, getMemRegionByRKey), each calling the child's +-- getItem. The emitted TagVecSrv has a SINGLE getItem port. Per the emit +-- decision, the two lookups SHARE that one child port, multiplexed by +-- getMrSel_i ('0' = LKey, '1' = RKey). This assumes the parent never needs +-- both lookups in the SAME cycle. Truly-concurrent lkey+rkey lookups would +-- require a second getItem read port on TagVecSrv (not added here, to keep +-- TagVecSrv and its passing testbench untouched). See OPEN_QUESTIONS.md. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity MetaDataMRs is + generic ( + TPD_G : time := 1 ns; + MAX_MR_PER_PD_G : positive := 128); -- TDiv#(MAX_MR=256, MAX_PD=2) (DataTypes.bsv) + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + + -- srvPort.request : Put#(ReqMR) (ReqMR = 252 b) + reqValid_i : in sl; -- request put enable + reqData_i : in slv(251 downto 0); -- ReqMR packed + reqReady_o : out sl; -- child reqQ not_full (backpressure) + + -- srvPort.response : Get#(RespMR) (RespMR = 251 b) + respValid_o : out sl; -- child respQ has a response + respData_o : out slv(250 downto 0); -- RespMR packed + respReady_i : in sl; -- response get enable (downstream) + + -- getMemRegionByLKey / getMemRegionByRKey : shared combinational lookup + -- (single child getItem port, multiplexed by getMrSel_i; see header note) + getMrLKey_i : in slv(31 downto 0); -- getMemRegionByLKey arg + getMrRKey_i : in slv(31 downto 0); -- getMemRegionByRKey arg + getMrSel_i : in sl; -- '0' = LKey lookup, '1' = RKey lookup + getMrValid_o : out sl; -- Maybe#(MemRegion) tag + getMrData_o : out slv(185 downto 0); -- MemRegion (valid when getMrValid_o='1') + + -- clear() method + clearEn_i : in sl; -- pulse child clear + + -- status methods + notEmpty_o : out sl; -- child notEmpty + notFull_o : out sl); -- child notFull +end entity MetaDataMRs; + +architecture rtl of MetaDataMRs is + + -- Widths (traced; see header) + constant MEM_REGION_WIDTH_C : integer := 186; + constant MR_INDEX_WIDTH_C : integer := log2(MAX_MR_PER_PD_G); -- 7 for 128 + constant CHILD_WORD_WIDTH_C : integer := MEM_REGION_WIDTH_C + MR_INDEX_WIDTH_C; -- 193 (=> slv 193:0, 194 b) + + -- MemRegion sub-field LSB positions within the 186-bit MemRegion word + constant MR_LKEY_PART_LOW_C : integer := 25; -- lkeyPart = [49:25] + constant MR_RKEY_PART_LOW_C : integer := 0; -- rkeyPart = [24:0] + + -- Request-path glue + signal reqMrKey : slv(31 downto 0); -- lkeyOrNot ? lkey : rkey + signal reqMrIndex : slv(MR_INDEX_WIDTH_C-1 downto 0); -- key2IndexMR = key[31:25] + + -- Child TagVecSrv handshake nets + signal childReqData : slv(CHILD_WORD_WIDTH_C downto 0); -- {allocOrNot, mr, mrIndex} (194 b) + signal childReqReady : sl; + signal childRespData : slv(CHILD_WORD_WIDTH_C downto 0); -- {success, mrIndex, mr} (194 b) + signal childRespValid : sl; + signal childGetItemIdx : slv(MR_INDEX_WIDTH_C-1 downto 0); + signal childGetItemOut : slv(MEM_REGION_WIDTH_C downto 0); -- {valid, dataVec} (187 b) + signal childNotEmpty : sl; + signal childNotFull : sl; + + -- Response-path glue + signal respSuccess : sl; + signal respMrIndex : slv(MR_INDEX_WIDTH_C-1 downto 0); + signal respMr : slv(MEM_REGION_WIDTH_C-1 downto 0); + signal lkeyOut : slv(31 downto 0); + signal rkeyOut : slv(31 downto 0); + + -- Lookup-path glue + signal lkupKey : slv(31 downto 0); + +begin + + --------------------------------------------------------------------------- + -- Request path: key -> index, forward {allocOrNot, mr, mrIndex} to child + -- mrReqKey = lkeyOrNot ? lkey : rkey ; mrIndex = key2IndexMR(mrReqKey) + --------------------------------------------------------------------------- + reqMrKey <= reqData_i(63 downto 32) when (reqData_i(64) = '1') else reqData_i(31 downto 0); + reqMrIndex <= reqMrKey(31 downto 31 - MR_INDEX_WIDTH_C + 1); -- key[31:25] (truncateLSB) + + childReqData <= reqData_i(251) & reqData_i(250 downto 65) & reqMrIndex; -- allocOrNot & mr & mrIndex + reqReady_o <= childReqReady; + + --------------------------------------------------------------------------- + -- Response path: rebuild local/remote keys from child response + -- resp_dout = {success, mrIndex(7), mr(186)} + -- lkey = {mrIndex, mr.lkeyPart} ; rkey = {mrIndex, mr.rkeyPart} + -- RespMR = {success, mr, lkey, rkey} + --------------------------------------------------------------------------- + respSuccess <= childRespData(CHILD_WORD_WIDTH_C); -- bit 193 + respMrIndex <= childRespData(CHILD_WORD_WIDTH_C-1 downto MEM_REGION_WIDTH_C); -- bits 192:186 + respMr <= childRespData(MEM_REGION_WIDTH_C-1 downto 0); -- bits 185:0 + + lkeyOut <= respMrIndex & respMr(MR_LKEY_PART_LOW_C + 24 downto MR_LKEY_PART_LOW_C); -- {idx, lkeyPart} + rkeyOut <= respMrIndex & respMr(MR_RKEY_PART_LOW_C + 24 downto MR_RKEY_PART_LOW_C); -- {idx, rkeyPart} + + respData_o <= respSuccess & respMr & lkeyOut & rkeyOut; -- {success, mr, lkey, rkey} (251 b) + respValid_o <= childRespValid; + + --------------------------------------------------------------------------- + -- Lookup path (shared single child getItem port, see header OQ-FSM-MR-03) + -- idx = key2IndexMR(selected key) ; result = child.getItem(idx) + --------------------------------------------------------------------------- + lkupKey <= getMrLKey_i when (getMrSel_i = '0') else getMrRKey_i; + childGetItemIdx <= lkupKey(31 downto 31 - MR_INDEX_WIDTH_C + 1); -- key[31:25] + + getMrValid_o <= childGetItemOut(MEM_REGION_WIDTH_C); -- valid tag (MSB) + getMrData_o <= childGetItemOut(MEM_REGION_WIDTH_C-1 downto 0); -- MemRegion data + + --------------------------------------------------------------------------- + -- Status / clear pass-through + --------------------------------------------------------------------------- + notEmpty_o <= childNotEmpty; + notFull_o <= childNotFull; + + --------------------------------------------------------------------------- + -- U_MrTagVec : child entity TagVecSrv#(MAX_MR_PER_PD, MemRegion) + -- src : out/04-vhdl/TagVecSrv.vhd (BSV mkTagVecSrv, MetaData.bsv:193) + -- NOT a SURF primitive — a project child entity (mapping child_entity_instances). + --------------------------------------------------------------------------- + U_MrTagVec : entity surf.TagVecSrv + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + MEMORY_TYPE_G => "distributed", + V_SZ_G => MAX_MR_PER_PD_G, -- 128 tag entries + T_SZ_G => MEM_REGION_WIDTH_C) -- 186-bit MemRegion per entry + port map ( + clk => clk, + rst => rst, + reqValid => reqValid_i, + reqData => childReqData, + reqReady => childReqReady, + respValid => childRespValid, + respData => childRespData, + respReady => respReady_i, + getItemIdx => childGetItemIdx, + getItemOut => childGetItemOut, + tagValid => open, -- not needed here (single reader) + notEmpty => childNotEmpty, + notFull => childNotFull, + clearEn => clearEn_i); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/MetaDataPDs.vhd b/ethernet/RoCEv2/rtl/MetaDataPDs.vhd new file mode 100644 index 0000000000..a40dac6ed8 --- /dev/null +++ b/ethernet/RoCEv2/rtl/MetaDataPDs.vhd @@ -0,0 +1,326 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Pure STRUCTURAL / combinational wrapper. mkMetaDataPDs declares ZERO rules +-- and ZERO own state (no mkReg/mkRegU, no FIFO, no counter). All PD-tag state +-- lives in the child TagVecSrv; per-PD memory-region tables live in the two +-- MetaDataMRs children. This entity is therefore emitted with NO two-process +-- RegType FSM (OQ-FSM-MDPD-03): child instances + combinational glue only. +-- +-- Children (OQ-FSM-MDPD-02 — counts come from the BSV source, not mapping.json +-- which records count=null): +-- * U_PdTagVec : TagVecSrv (1 instance, V_SZ_G=MAX_PD=2, T_SZ_G=KeyPD=31) +-- * U_PdMrVec : MetaDataMRs (MAX_PD = 2 instances, for..generate) +-- +-- Interface mapping (BSV method -> VHDL ports): +-- * srvPort (Server#(ReqPD,RespPD)) -> request/response handshake, repacked +-- to/from the child TagVecSrv tuple3 request/response. +-- ReqPD = {allocOrNot(1), pdKey(31), pdHandler(32)} = 64 b (first->MSB) +-- RespPD = {successOrNot(1), pdHandler(32), pdKey(31)} = 64 b +-- getIndexPD(h) = truncateLSB(h) = the TOP PD_INDEX_WIDTH(=1) bit(s) of +-- the 32-bit handler => index = pdHandler(31). +-- * getMRs4PD(pdHandler) returns a *MetaDataMRs interface handle* +-- (OQ-FSM-MDPD-01). TWO consumers exist, each flattened to its own group: +-- 1. mrLkup* : the getMemRegionByLKey/getMemRegionByRKey combinational +-- lookup of the selected child, qualified by tag-valid(idx). Consumer: +-- PermCheckSrv (names per OQ-FSM-PCS-01). +-- 2. mrSrv* : the selected child's REGISTRATION srvPort (request demux / +-- response mux by getIndexPD(mrSrvPdHandler)) + mrSrvPdValid = +-- tag-valid(idx). Consumer: MetaDataSrv (issueReq4MR/genResp4MR via +-- the getMRs4PD interface-return, MetaData.bsv:713-755). Single +-- client, one outstanding MR op (serialized by MetaDataSrv's FSM). +-- * isValidPD(pdHandler) = isValid(getItem(idx)) = tag-valid(idx). LIVE — +-- called from mkMetaDataSrv (MetaData.bsv:731, 775). Consumer: MetaDataSrv. +-- * clear() -> pulse TagVecSrv.clear AND every MetaDataMRs.clear. +-- * notEmpty/notFull -> passthrough from U_PdTagVec. +-- +-- REVISION HISTORY (supersedes two original judgment calls): +-- * OQ-FSM-MDPD-04 (was: "MR registration srvPorts tied off") INVALIDATED — +-- the original emit missed the interface-return path: mkMetaDataSrv +-- connects to the children's srvPort THROUGH getMRs4PD. Tie-off made MR +-- registration unreachable (every PermCheckSrv lookup would miss forever). +-- Fixed per RESOLVED OQ-FSM-MDSRV-01 sec.4.1: mrSrv* group + index +-- demux/mux added. +-- * OQ-FSM-MDPD-05 (was: "isValidPD dead; share getItem port, mrLkup +-- priority") premise INVALIDATED — isValidPD is live (see above), and the +-- shared-port arbitration could corrupt it exactly when sampled (mrLkup* +-- is driven concurrently by the PermCheckSrv datapath). Fixed per RESOLVED +-- OQ-FSM-MDSRV-01 sec.4.2 (preferred option): TagVecSrv now exports its +-- tag-valid vector (`tagValid`); isValidPd and mrSrvPdValid read it +-- directly, and the single getItem data port is DEDICATED to mrLkup*. +-- mrLkupReqValid is thereby unused here (retained for port stability; +-- the lookup is served every cycle). +-- +-- Bit-packing follows BSV deriving(Bits) first-field-at-MSB (project +-- convention, OQ-FSM-H2DS-04 / OQ-FSM-16). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity MetaDataPDs is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset + RST_ASYNC_G : boolean := false; + MAX_PD_G : positive := 2; -- MAX_PD (Settings.bsv:20) + PD_HANDLE_WIDTH_G : positive := 32; -- PD_HANDLE_WIDTH (DataTypes.bsv:28) + MR_REGION_WIDTH_G : positive := 186); -- SizeOf#(MemRegion) + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + + -- srvPort.request : Put#(ReqPD) (ReqPD = 1 + PD_KEY + PD_HANDLE = 64 b) + -- high index = 2*PD_HANDLE_WIDTH_G - PD_INDEX_WIDTH = 2*32 - 1 = 63 + srvReqValid : in sl; + srvReqData : in slv(2*PD_HANDLE_WIDTH_G - log2(MAX_PD_G) downto 0); -- 64 b + srvReqReady : out sl; + + -- srvPort.response : Get#(RespPD) (RespPD = 1 + PD_HANDLE + PD_KEY = 64 b) + srvRespValid : out sl; + srvRespData : out slv(2*PD_HANDLE_WIDTH_G - log2(MAX_PD_G) downto 0); -- 64 b + srvRespReady : in sl; + + -- isValidPD(pdHandler) : Bool (LIVE — called by MetaDataSrv, + -- MetaData.bsv:731/775; served from the TagVecSrv tag-valid vector) + isValidPdHandler : in slv(PD_HANDLE_WIDTH_G-1 downto 0); + isValidPd : out sl; + + -- getMRs4PD(pdHandler), consumer 1: MR-lookup group (-> PermCheckSrv, + -- OQ-FSM-MDPD-01 / PCS-01) + mrLkupPdHandler : in slv(PD_HANDLE_WIDTH_G-1 downto 0); + mrLkupKey : in slv(31 downto 0); -- LKEY/RKEY (KEY_WIDTH = 32) + mrLkupByLocal : in sl; -- '1' = LKey lookup, '0' = RKey + mrLkupReqValid : in sl; -- unused since sec.4.2 fix (kept) + mrLkupValid : out sl; -- Maybe#(MemRegion) tag + mrLkupData : out slv(MR_REGION_WIDTH_G-1 downto 0); + + -- getMRs4PD(pdHandler), consumer 2: selected child's registration srvPort + -- (-> MetaDataSrv.mrSrv*, RESOLVED OQ-FSM-MDSRV-01 sec.2.3/4.1). + -- Widths fixed by MetaDataMRs.vhd: ReqMR = 252 b, RespMR = 251 b. + mrSrvPdHandler : in slv(PD_HANDLE_WIDTH_G-1 downto 0); + mrSrvPdValid : out sl; -- tag-valid(getIndexPD(handler)) + mrSrvReqValid : in sl; + mrSrvReqData : in slv(251 downto 0); -- ReqMR + mrSrvReqReady : out sl; + mrSrvRespValid : out sl; + mrSrvRespData : out slv(250 downto 0); -- RespMR + mrSrvRespReady : in sl; + + -- clear() method + clearEn : in sl; + + -- status methods (passthrough from U_PdTagVec) + notEmpty : out sl; + notFull : out sl); +end entity MetaDataPDs; + +architecture rtl of MetaDataPDs is + + ----------------------------------------------------------------------------- + -- Derived widths (traced from BSV provisos, MetaData.bsv:247-263) + -- PD_INDEX_WIDTH = TLog#(MAX_PD) + -- PD_KEY_WIDTH = PD_HANDLE_WIDTH - PD_INDEX_WIDTH + -- ReqPD = 1 + PD_KEY_WIDTH + PD_HANDLE_WIDTH + -- RespPD = 1 + PD_HANDLE_WIDTH + PD_KEY_WIDTH + -- TagVecSrv tuple3 word = 1 + T_SZ + vLogSz (T_SZ = KeyPD = PD_KEY_WIDTH) + ----------------------------------------------------------------------------- + constant PD_IDX_W_C : integer := log2(MAX_PD_G); -- = 1 + constant PD_KEY_W_C : integer := PD_HANDLE_WIDTH_G - PD_IDX_W_C; -- = 31 + constant TAG_W_C : integer := 1 + PD_KEY_W_C + PD_IDX_W_C; -- = 33 + -- MSB index of the packed ReqPD/RespPD ports (width-1) + constant REQ_MSB_C : integer := 2*PD_HANDLE_WIDTH_G - PD_IDX_W_C; -- = 63 + -- MetaDataMRs srvPort word widths (fixed by that entity's port list) + constant REQ_MR_W_C : integer := 252; + constant RESP_MR_W_C : integer := 251; + + -- Per-child lookup / response arrays + type MrDataArray is array (0 to MAX_PD_G-1) of slv(MR_REGION_WIDTH_G-1 downto 0); + type MrRespArray is array (0 to MAX_PD_G-1) of slv(RESP_MR_W_C-1 downto 0); + + -- TagVecSrv interface signals + signal tagReqData : slv(TAG_W_C-1 downto 0); + signal tagRespData : slv(TAG_W_C-1 downto 0); + signal tagGetIdx : slv(PD_IDX_W_C-1 downto 0); + signal tagGetItem : slv(PD_KEY_W_C downto 0); -- {valid, dataVec(idx)} = 32 b + signal tagValidVec : slv(MAX_PD_G-1 downto 0); -- full tag-valid vector + signal getItemValid : sl; + + -- MetaDataMRs combinational lookup interface (per instance) + signal mrGetSel : sl; + signal mrValidVec : slv(MAX_PD_G-1 downto 0); + signal mrDataVec : MrDataArray; + + -- MetaDataMRs registration srvPort demux/mux (per instance) + signal mrReqValidVec : slv(MAX_PD_G-1 downto 0); + signal mrReqReadyVec : slv(MAX_PD_G-1 downto 0); + signal mrRespValidVec : slv(MAX_PD_G-1 downto 0); + signal mrRespReadyVec : slv(MAX_PD_G-1 downto 0); + signal mrRespDataVec : MrRespArray; + signal mrSrvIdx : slv(PD_IDX_W_C-1 downto 0); + + -- Selected (idx-routed) MR lookup result + signal selMrIdx : slv(PD_IDX_W_C-1 downto 0); + signal selMrValid : sl; + signal selMrData : slv(MR_REGION_WIDTH_G-1 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- U_PdTagVec : TagVecSrv (BSV: pdTagVec <- mkTagVecSrv, MetaData.bsv:279) + -- vSz = MAX_PD = 2 ; anytype = KeyPD = Bit#(31). + -- Holds all PD-tag state. clear() is routed via clearEn. + ----------------------------------------------------------------------------- + U_PdTagVec : entity surf.TagVecSrv + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + V_SZ_G => MAX_PD_G, + T_SZ_G => PD_KEY_W_C) + port map ( + clk => clk, + rst => rst, + -- request (srvPort.request, repacked from ReqPD) + reqValid => srvReqValid, + reqData => tagReqData, + reqReady => srvReqReady, + -- response (srvPort.response, repacked into RespPD) + respValid => srvRespValid, + respData => tagRespData, + respReady => srvRespReady, + -- getItem() combinational lookup (DEDICATED to mrLkup*, sec.4.2) + getItemIdx => tagGetIdx, + getItemOut => tagGetItem, + -- tag-valid vector (serves isValidPd + mrSrvPdValid, sec.4.2) + tagValid => tagValidVec, + -- status + notEmpty => notEmpty, + notFull => notFull, + -- clear() + clearEn => clearEn); + + ----------------------------------------------------------------------------- + -- U_PdMrVec[0..MAX_PD-1] : MetaDataMRs + -- (BSV: pdMrVec <- replicateM(mkMetaDataMRs), MetaData.bsv:280, MAX_PD = 2) + -- Registration srvPort demux/mux: MetaDataSrv drives the child selected by + -- getIndexPD(mrSrvPdHandler) through the getMRs4PD interface-return + -- (RESOLVED OQ-FSM-MDSRV-01 sec.4.1; single client, one outstanding op). + -- The combinational getMemRegionBy{L,R}Key lookup fans out to all children; + -- the selected result is routed upward via mrLkup*. + ----------------------------------------------------------------------------- + mrGetSel <= not mrLkupByLocal; -- MetaDataMRs getMrSel_i: '0'=LKey, '1'=RKey + -- getIndexPD: at MAX_PD_G=1 the BSV index is 0 bits, i.e. the constant 0 - + -- force 0 instead of reading a live handle bit (same idiom as getIndexQP) + mrSrvIdx <= ite(MAX_PD_G > 1, + mrSrvPdHandler(PD_HANDLE_WIDTH_G-1 downto PD_HANDLE_WIDTH_G - PD_IDX_W_C), + "0"); + + GEN_MR : for i in 0 to MAX_PD_G-1 generate + + -- getIndexPD demux: only the addressed child sees the put/get strobes + mrReqValidVec(i) <= mrSrvReqValid and toSl(to_integer(unsigned(mrSrvIdx)) = i); + mrRespReadyVec(i) <= mrSrvRespReady and toSl(to_integer(unsigned(mrSrvIdx)) = i); + + U_PdMr : entity surf.MetaDataMRs + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + -- srvPort.request : from MetaDataSrv via getMRs4PD (demuxed) + reqValid_i => mrReqValidVec(i), + reqData_i => mrSrvReqData, + reqReady_o => mrReqReadyVec(i), + -- srvPort.response : to MetaDataSrv via getMRs4PD (muxed) + respValid_o => mrRespValidVec(i), + respData_o => mrRespDataVec(i), + respReady_i => mrRespReadyVec(i), + -- getMemRegionByLKey / getMemRegionByRKey (combinational lookup) + getMrLKey_i => mrLkupKey, + getMrRKey_i => mrLkupKey, + getMrSel_i => mrGetSel, + getMrValid_o => mrValidVec(i), + getMrData_o => mrDataVec(i), + -- clear() : fanned out to all MetaDataMRs (mapM_ clearAllMRs) + clearEn_i => clearEn, + -- status : not exported by MetaDataPDs (only TagVecSrv's are) + notEmpty_o => open, + notFull_o => open); + end generate GEN_MR; + + ----------------------------------------------------------------------------- + -- Combinational glue (no registers — structural wrapper, OQ-FSM-MDPD-03) + ----------------------------------------------------------------------------- + + -- srvPort.request : ReqPD -> TagVecSrv tuple3(allocOrNot, pdKey, pdIndex) + -- ReqPD layout (first-field-MSB, 64 b): + -- allocOrNot = srvReqData(63) + -- pdKey = srvReqData(62 downto 32) + -- pdHandler = srvReqData(31 downto 0) ; index = pdHandler(31) = MSB + -- tuple3 word = {allocOrNot(1), pdKey(31), pdIndex(1)} (TagVecSrv reqData) + tagReqData <= srvReqData(REQ_MSB_C) & -- allocOrNot (MSB) + srvReqData(REQ_MSB_C - 1 downto PD_HANDLE_WIDTH_G) & -- pdKey (PD_KEY_W_C b) + ite(MAX_PD_G > 1, + srvReqData(PD_HANDLE_WIDTH_G-1 downto PD_HANDLE_WIDTH_G - PD_IDX_W_C), + "0"); -- pdIndex = top of handler; constant 0 at MAX_PD_G=1 + + -- srvPort.response : TagVecSrv tuple3(success, idx, value) -> RespPD + -- TagVecSrv respData = {success(1), pdIndex(1), pdKey(31)} + -- pdHandler = {pack(pdIndex), pdKey} = respData(31 downto 0) + -- RespPD layout (first-field-MSB, 64 b): + -- successOrNot = respData(32) + -- pdHandler = respData(31 downto 0) (62 downto 31) + -- pdKey = respData(30 downto 0) (30 downto 0) + srvRespData <= tagRespData(TAG_W_C-1) & -- successOrNot + tagRespData(TAG_W_C-2 downto 0) & -- pdHandler = {idx, key} + tagRespData(PD_KEY_W_C-1 downto 0); -- pdKey + + -- getItem() data port: DEDICATED to the mrLkup* consumer (sec.4.2 fix — no + -- arbitration; mrLkupReqValid no longer gates anything). + tagGetIdx <= ite(MAX_PD_G > 1, + mrLkupPdHandler(PD_HANDLE_WIDTH_G-1 downto PD_HANDLE_WIDTH_G - PD_IDX_W_C), + "0"); + + getItemValid <= tagGetItem(PD_KEY_W_C); -- {valid, data} : valid is the MSB + + -- isValidPD(pdHandler) = tag-valid(getIndexPD(handler)) — conflict-free read + -- of the exported vector (LIVE consumer: MetaDataSrv QP states). + isValidPd <= tagValidVec(ite(MAX_PD_G > 1, + to_integer(unsigned( + isValidPdHandler(PD_HANDLE_WIDTH_G-1 downto PD_HANDLE_WIDTH_G - PD_IDX_W_C))), + 0)); + + -- getMRs4PD validity for the registration client (MetaDataSrv MR states) + mrSrvPdValid <= tagValidVec(to_integer(unsigned(mrSrvIdx))); + + -- getMRs4PD registration srvPort response mux (selected child -> MetaDataSrv) + mrSrvReqReady <= mrReqReadyVec(to_integer(unsigned(mrSrvIdx))); + mrSrvRespValid <= mrRespValidVec(to_integer(unsigned(mrSrvIdx))); + mrSrvRespData <= mrRespDataVec(to_integer(unsigned(mrSrvIdx))); + + -- getMRs4PD lookup consumer: route the selected MetaDataMRs instance's + -- result, qualified by tag-valid(idx) (= isValid(getItem(idx)) in BSV). + selMrIdx <= ite(MAX_PD_G > 1, + mrLkupPdHandler(PD_HANDLE_WIDTH_G-1 downto PD_HANDLE_WIDTH_G - PD_IDX_W_C), + "0"); + selMrValid <= mrValidVec(to_integer(unsigned(selMrIdx))); + selMrData <= mrDataVec(to_integer(unsigned(selMrIdx))); + + mrLkupValid <= getItemValid and selMrValid; + mrLkupData <= selMrData; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/MetaDataQPs.vhd b/ethernet/RoCEv2/rtl/MetaDataQPs.vhd new file mode 100644 index 0000000000..520c037821 --- /dev/null +++ b/ethernet/RoCEv2/rtl/MetaDataQPs.vhd @@ -0,0 +1,461 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- QP metadata manager. A QP-control Server#(ReqQP, RespQP) face routes +-- CREATE/DESTROY requests through the tag-vector allocator (index+pdHandler +-- alloc/free) and forwards every accepted request to the addressed per-QP +-- controller via the per-QP client bundle. The module owns NO registers +-- (inventory state=[]): it is a 3-locus Mealy handshake router around two +-- surf.Fifo instances and the TagVecSrv child. The RegType record carries a +-- single dummy field so the two-process skeleton is retained for uniformity +-- (same pattern as PipeOutMux.vhd). +-- +-- The three atomic loci (may all fire in the same cycle — disjoint FIFO +-- ports, no priority): +-- A. srvPort.request.put : enq U_QpReqQ4Cntrl; CREATE/DESTROY also puts +-- {create, pdHandler, qpIndex} to the tag vector. +-- B. rule handleReqQP : deq U_QpReqQ4Cntrl; CREATE/DESTROY consumes the +-- tag-vector response (on success rewrites qpn := genQPN(idx, pd) and +-- pdHandler, then puts the request to QP[idx]); MODIFY/QUERY puts the +-- unmodified request to QP[getIndexQP(qpn)]; enq +-- {tagVecRespSuccess, qpReq'} to U_QpReqQ4Resp. +-- C. srvPort.response.get: deq U_QpReqQ4Resp; on success fetches the +-- addressed QP's RespQP, otherwise returns the default failure RespQP +-- (successOrNot='0', fields echoed from the stored request). +-- +-- ReqQP packing (301 b, traced via CntrlQp.vhd): +-- qpReqType[300:299] pdHandler[298:267] qpn[266:243] +-- qpAttrMask[242:217] qpAttr[216:5] qpInitAttr[4:0] +-- RespQP packing (274 b): +-- successOrNot[273] qpn[272:249] pdHandler[248:217] +-- qpAttr[216:5] qpInitAttr[4:0] +-- getIndexQP(qpn) = truncateLSB(qpn) = qpn's top log2(MAX_QP_G) bits. +-- genQPN(idx, pd) = { idx , truncate(pd) } (idx in the QPN MSBs). +-- +-- Per-QP srvPortQP client bundle (OQ-FSM-MDQPS-01 resolution §2.2): one +-- shared request payload + one-hot qpReqValid / per-QP qpReqReady; per-QP +-- response payloads (flattened, QP k at slice +-- qpRespData((k+1)*274-1 downto k*274)) + valid vector / one-hot ready. +-- In TransportLayer each bundle index wires 1:1 to U_Qp(k)'s srvPort* face +-- (Qp.vhd srvPortReq*/srvPortResp* ports); nothing else may drive it. +-- +-- Interface methods lowered to ports: +-- getPD(qpn) -> getPdQpn/getPdMaybeValid/getPdHandler (matches the +-- consumer-side names in InputRdmaPktBufAndHeaderValidation) +-- isValidQP(qpn) = isValid(getPD(qpn)) -> same lookup; use getPdMaybeValid. +-- (No live BSV consumer besides getPD @ InputPktHandle:490.) +-- getQueuePairByQPN / getQueuePairByIndexQP -> DELETED per OQ-FSM-MDQPS-01 +-- (static wiring + status mux move to TransportLayer / +-- InputRdmaPktBufAndHeaderValidation). +-- notEmpty/notFull -> forwarded TagVecSrv status. +-- clear() is commented out in the BSV source -> U_QpTagVec.clearEn tied '0'. +-- +-- SURF components instantiated (surf/base/fifo/rtl/Fifo.vhd): +-- U_QpReqQ4Cntrl : surf.Fifo (BSV qpReqQ4Cntrl <- mkFIFOF, ReqQP, 301 b) +-- U_QpReqQ4Resp : surf.Fifo (BSV qpReqQ4Resp <- mkFIFOF, +-- Tuple2#(Bool,ReqQP), 302 b, flag in MSB) +-- Both sync + FWFT (valid = notEmpty, dout = first, rd_en = deq). +-- Child entity: U_QpTagVec : surf.TagVecSrv (V_SZ_G=MAX_QP_G, T_SZ_G=32). +------------------------------------------------------------------------------- +-- This file is part of the BSV->VHDL transpilation output. It targets the SURF +-- VHDL library and follows the SURF coding standard (style/vhdl-style-rules.md). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity MetaDataQPs is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset + RST_ASYNC_G : boolean := false; + MEMORY_TYPE_G : string := "distributed"; -- small FIFOs + MAX_QP_G : positive := 4; -- MAX_QP (Settings.bsv), power of 2 + PD_HANDLE_WIDTH_G : positive := 32); -- PD_HANDLE_WIDTH (DataTypes.bsv) + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- srvPort : Server#(ReqQP(301b), RespQP(274b)) (request face) + srvReqValid : in sl; + srvReqData : in slv(300 downto 0); + srvReqReady : out sl; -- CAN_PUT (type-dependent, see A) + -- srvPort (response face; FWFT: srvRespReady = deq strobe) + srvRespValid : out sl; + srvRespData : out slv(273 downto 0); + srvRespReady : in sl; + -- Per-QP srvPortQP client bundle (index k <-> U_Qp(k).srvPort* in parent) + qpReqValid : out slv(MAX_QP_G-1 downto 0); -- one-hot request put + qpReqData : out slv(300 downto 0); -- shared ReqQP payload + qpReqReady : in slv(MAX_QP_G-1 downto 0); -- per-QP CAN_PUT + qpRespValid : in slv(MAX_QP_G-1 downto 0); -- per-QP response valid + qpRespData : in slv(MAX_QP_G*274-1 downto 0); -- per-QP RespQP slices + qpRespReady : out slv(MAX_QP_G-1 downto 0); -- one-hot response deq + -- getPD(qpn) / isValidQP(qpn) combinational lookup + getPdQpn : in slv(23 downto 0); + getPdMaybeValid : out sl; -- Maybe tag (= isValidQP result) + getPdHandler : out slv(PD_HANDLE_WIDTH_G-1 downto 0); + -- Status methods (forwarded TagVecSrv status) + notEmpty : out sl; + notFull : out sl); +end entity MetaDataQPs; + +architecture rtl of MetaDataQPs is + + ----------------------------------------------------------------------------- + -- Constants (widths traced from BSV types via CntrlQp.vhd / Qp.vhd) + ----------------------------------------------------------------------------- + constant QPN_W_C : integer := 24; -- QPN (IB spec) + constant PD_W_C : integer := PD_HANDLE_WIDTH_G; -- HandlerPD = 32 + constant QP_IDX_W_C : integer := log2(MAX_QP_G); -- IndexQP = 2 + constant REQ_QP_W_C : integer := 301; -- ReqQP packed + constant RESP_QP_W_C : integer := 274; -- RespQP packed + constant RESP_FIFO_W_C : integer := 1 + REQ_QP_W_C; -- {flag, ReqQP} = 302 + constant TAG_MSG_W_C : integer := 1 + PD_W_C + QP_IDX_W_C; -- TagVecSrv 35 + constant FIFO_ADDR_WIDTH_C : integer := 4; -- surf.Fifo minimum + + -- ReqQP field offsets (LSB index of each field) + constant REQ_TYPE_LSB_C : integer := 299; -- qpReqType[300:299] + constant REQ_PD_LSB_C : integer := 267; -- pdHandler[298:267] + constant REQ_QPN_LSB_C : integer := 243; -- qpn[266:243] + constant REQ_ATTR_LSB_C : integer := 5; -- qpAttr[216:5] + -- RespQP field offsets + constant RESP_QPN_LSB_C : integer := 249; -- qpn[272:249] + constant RESP_PD_LSB_C : integer := 217; -- pdHandler[248:217] + + -- qpReqType enum encoding (DataTypes.bsv, confirmed in CntrlQp.vhd) + constant REQ_QP_CREATE_C : slv(1 downto 0) := "00"; + constant REQ_QP_DESTROY_C : slv(1 downto 0) := "01"; + + ----------------------------------------------------------------------------- + -- Types / records: no owned BSV state (inventory state=[]) — one dummy bit + -- keeps the RegType record syntactically non-empty (PipeOutMux precedent). + ----------------------------------------------------------------------------- + type RegType is record + dummy : sl; + end record RegType; + + constant REG_INIT_C : RegType := (dummy => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_QpReqQ4Cntrl (ReqQP) interface signals + signal cntrlWrEn : sl; -- enq (locus A) + signal cntrlNotFull : sl; + signal cntrlRdEn : sl; -- deq (locus B) + signal cntrlDout : slv(REQ_QP_W_C-1 downto 0); + signal cntrlValid : sl; -- notEmpty (FWFT) + + -- U_QpReqQ4Resp ({flag, ReqQP}) interface signals + signal respWrEn : sl; -- enq (locus B) + signal respDin : slv(RESP_FIFO_W_C-1 downto 0); + signal respNotFull : sl; + signal respRdEn : sl; -- deq (locus C) + signal respDout : slv(RESP_FIFO_W_C-1 downto 0); + signal respValid : sl; -- notEmpty (FWFT) + + -- U_QpTagVec interface signals + signal tagReqValid : sl; -- put (locus A) + signal tagReqData : slv(TAG_MSG_W_C-1 downto 0); -- {create, pd, idx} + signal tagReqReady : sl; + signal tagRespValid : sl; + signal tagRespData : slv(TAG_MSG_W_C-1 downto 0); -- {success, idx, pd} + signal tagRespReady : sl; -- get (locus B) + signal tagGetOut : slv(PD_W_C downto 0); -- {valid, pdHandler} + -- getIndexQP(getPdQpn): forced to 0 at MAX_QP_G=1 (0-bit BSV index, + -- MetaData.bsv:349); intermediate signal because the ite sits in a port map + signal tagGetIdx : slv(QP_IDX_W_C-1 downto 0); + +begin + + -- pragma translate_off + assert isPowerOf2(MAX_QP_G) + report "MAX_QP_G must be a power of 2 @ MetaDataQPs" + severity failure; + -- pragma translate_on + + ----------------------------------------------------------------------------- + -- Control-request FIFO (BSV qpReqQ4Cntrl : FIFOF#(ReqQP)) + -- wr side = srvPort.request.put (locus A); rd side = rule handleReqQP (B). + ----------------------------------------------------------------------------- + U_QpReqQ4Cntrl : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, -- BSV first/deq peek semantics + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => REQ_QP_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C) + port map ( + rst => rst, + wr_clk => clk, + wr_en => cntrlWrEn, + din => srvReqData, + not_full => cntrlNotFull, + rd_clk => clk, + rd_en => cntrlRdEn, + dout => cntrlDout, + valid => cntrlValid); + + ----------------------------------------------------------------------------- + -- Response-descriptor FIFO (BSV qpReqQ4Resp : FIFOF#(Tuple2#(Bool, ReqQP))) + -- Tuple2 packs the Bool flag in the MSB: flag = dout(301), ReqQP = dout(300:0). + -- wr side = rule handleReqQP (B); rd side = srvPort.response.get (C). + ----------------------------------------------------------------------------- + U_QpReqQ4Resp : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => RESP_FIFO_W_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C) + port map ( + rst => rst, + wr_clk => clk, + wr_en => respWrEn, + din => respDin, + not_full => respNotFull, + rd_clk => clk, + rd_en => respRdEn, + dout => respDout, + valid => respValid); + + ----------------------------------------------------------------------------- + -- Tag-vector allocation server (BSV qpTagVec <- mkTagVecSrv, + -- TagVecSrv#(MAX_QP, HandlerPD)). reqData = {insOrRem, insVal(pd), remIdx}; + -- respData = {success, idx, value(pd)}; getItemOut = {valid, dataVec(idx)}. + -- BSV clear() is commented out (MetaData.bsv:497) -> clearEn tied '0'. + ----------------------------------------------------------------------------- + tagGetIdx <= ite(MAX_QP_G > 1, + getPdQpn(QPN_W_C-1 downto QPN_W_C-QP_IDX_W_C), + "0"); + + U_QpTagVec : entity surf.TagVecSrv + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + V_SZ_G => MAX_QP_G, + T_SZ_G => PD_W_C) + port map ( + clk => clk, + rst => rst, + reqValid => tagReqValid, + reqData => tagReqData, + reqReady => tagReqReady, + respValid => tagRespValid, + respData => tagRespData, + respReady => tagRespReady, + getItemIdx => tagGetIdx, + getItemOut => tagGetOut, + tagValid => open, -- not needed here (single reader) + notEmpty => notEmpty, + notFull => notFull, + clearEn => '0'); + + ----------------------------------------------------------------------------- + -- Combinatorial process: the three Mealy loci (A, B, C). All strobes are + -- combinational; they may all fire in the same cycle (disjoint FIFO ports). + -- Left ungated under reset: rst forces the FIFOs'/children's own synchronous + -- reset, which dominates any concurrent wr_en/rd_en (TagVecSrv precedent). + ----------------------------------------------------------------------------- + comb : process (r, rst, srvReqValid, srvReqData, srvRespReady, cntrlValid, + cntrlDout, cntrlNotFull, respValid, respDout, respNotFull, + tagReqReady, tagRespValid, tagRespData, qpReqReady, + qpRespValid, qpRespData) is + variable v : RegType; + -- Locus A (srvPort.request.put) + variable aType : slv(1 downto 0); + variable aIsCd : sl; -- CREATE or DESTROY + variable aReady : sl; + variable aFire : sl; + -- Locus B (rule handleReqQP) + variable bType : slv(1 downto 0); + variable bIsCd : sl; + variable bTagOk : sl; -- tag-vec success + variable bTagIdx : slv(QP_IDX_W_C-1 downto 0); + variable bTagPd : slv(PD_W_C-1 downto 0); + variable bFlag : sl; -- tagVecRespSuccess + variable bIdx : slv(QP_IDX_W_C-1 downto 0); -- target QP index + variable bIdxInt : natural; + variable bDoPut : sl; -- put to QP[bIdx]? + variable bReq : slv(REQ_QP_W_C-1 downto 0); -- qpReq' (maybe rewritten) + variable bChild : sl; -- type-dependent guard + variable bFire : sl; + -- Locus C (srvPort.response.get) + variable cFlag : sl; + variable cReq : slv(REQ_QP_W_C-1 downto 0); + variable cIdx : slv(QP_IDX_W_C-1 downto 0); + variable cIdxInt : natural; + variable cResp : slv(RESP_QP_W_C-1 downto 0); + variable cValid : sl; + variable cFire : sl; + -- Mealy strobe/data outputs + variable vQpReqValid : slv(MAX_QP_G-1 downto 0); + variable vQpRespReady : slv(MAX_QP_G-1 downto 0); + begin + v := r; + + -- Defaults for Mealy outputs (deasserted unless a locus fires) + vQpReqValid := (others => '0'); + vQpRespReady := (others => '0'); + + ----------------------------------------------------------------------- + -- Locus A — srvPort.request.put (MetaData.bsv:398-420) + -- Guard: cntrl notFull AND (MODIFY/QUERY OR tag-vec CAN_PUT). The + -- tag-vec term applies ONLY to CREATE/DESTROY (do not over-gate). + ----------------------------------------------------------------------- + aType := srvReqData(300 downto REQ_TYPE_LSB_C); + aIsCd := ite((aType = REQ_QP_CREATE_C) or (aType = REQ_QP_DESTROY_C), + '1', '0'); + aReady := cntrlNotFull and (not aIsCd or tagReqReady); + aFire := srvReqValid and aReady; + + -- tuple3(create, pdHandler, getIndexQP(qpn)) to the tag vector + -- (index term forced to 0 at MAX_QP_G=1: 0-bit BSV index, MetaData.bsv:349) + tagReqValid <= aFire and aIsCd; + tagReqData <= ite(aType = REQ_QP_CREATE_C, '1', '0') & + srvReqData(REQ_PD_LSB_C+PD_W_C-1 downto REQ_PD_LSB_C) & + ite(MAX_QP_G > 1, + srvReqData(REQ_QPN_LSB_C+QPN_W_C-1 downto + REQ_QPN_LSB_C+QPN_W_C-QP_IDX_W_C), + "0"); + cntrlWrEn <= aFire; + srvReqReady <= aReady; + + ----------------------------------------------------------------------- + -- Locus B — rule handleReqQP (MetaData.bsv:361-395) + ----------------------------------------------------------------------- + bType := cntrlDout(REQ_QP_W_C-1 downto REQ_TYPE_LSB_C); + bIsCd := ite((bType = REQ_QP_CREATE_C) or (bType = REQ_QP_DESTROY_C), + '1', '0'); + bTagOk := tagRespData(TAG_MSG_W_C-1); + bTagIdx := tagRespData(PD_W_C+QP_IDX_W_C-1 downto PD_W_C); + bTagPd := tagRespData(PD_W_C-1 downto 0); + + bReq := cntrlDout; + if (bIsCd = '1') then + -- consume the tag-vec response (alloc/free result) + bFlag := bTagOk; + bIdx := bTagIdx; + bDoPut := bTagOk; + if (bTagOk = '1') then + -- qpReq.qpn := genQPN(idx, pd); qpReq.pdHandler := pd + bReq(REQ_QPN_LSB_C+QPN_W_C-1 downto REQ_QPN_LSB_C) := + bTagIdx & bTagPd(QPN_W_C-QP_IDX_W_C-1 downto 0); + bReq(REQ_PD_LSB_C+PD_W_C-1 downto REQ_PD_LSB_C) := bTagPd; + end if; + bChild := tagRespValid and (not bTagOk or qpReqReady(to_integer(unsigned(bTagIdx)))); + else + -- MODIFY / QUERY: no tag-vec touch, initial True flag + -- (host-facing qpn index: forced 0 at MAX_QP_G=1, MetaData.bsv:349) + bFlag := '1'; + bIdx := ite(MAX_QP_G > 1, + cntrlDout(REQ_QPN_LSB_C+QPN_W_C-1 downto + REQ_QPN_LSB_C+QPN_W_C-QP_IDX_W_C), + "0"); + bDoPut := '1'; + bChild := qpReqReady(to_integer(unsigned(bIdx))); + end if; + bIdxInt := to_integer(unsigned(bIdx)); + + bFire := cntrlValid and respNotFull and bChild; + + cntrlRdEn <= bFire; + tagRespReady <= bFire and bIsCd; + if (bFire = '1' and bDoPut = '1') then + vQpReqValid(bIdxInt) := '1'; + end if; + qpReqData <= bReq; + respWrEn <= bFire; + respDin <= bFlag & bReq; + + ----------------------------------------------------------------------- + -- Locus C — srvPort.response.get (MetaData.bsv:423-475) + -- FWFT face: srvRespValid = CAN_GET; srvRespReady = caller deq strobe. + ----------------------------------------------------------------------- + cFlag := respDout(RESP_FIFO_W_C-1); + cReq := respDout(REQ_QP_W_C-1 downto 0); + -- response-demux qpn index: forced 0 at MAX_QP_G=1 (MetaData.bsv:349) + cIdx := ite(MAX_QP_G > 1, + cReq(REQ_QPN_LSB_C+QPN_W_C-1 downto + REQ_QPN_LSB_C+QPN_W_C-QP_IDX_W_C), + "0"); + cIdxInt := to_integer(unsigned(cIdx)); + + -- Default failure RespQP: successOrNot='0', fields echoed from qpReq' + cResp := (others => '0'); + cResp(RESP_QPN_LSB_C+QPN_W_C-1 downto RESP_QPN_LSB_C) := + cReq(REQ_QPN_LSB_C+QPN_W_C-1 downto REQ_QPN_LSB_C); + cResp(RESP_PD_LSB_C+PD_W_C-1 downto RESP_PD_LSB_C) := + cReq(REQ_PD_LSB_C+PD_W_C-1 downto REQ_PD_LSB_C); + cResp(RESP_PD_LSB_C-1 downto 0) := + cReq(RESP_PD_LSB_C-1 downto 0); -- qpAttr[216:5] + qpInitAttr[4:0] + if (cFlag = '1') then + -- successful descriptor: pass the addressed QP's RespQP through + cResp := qpRespData(cIdxInt*RESP_QP_W_C+RESP_QP_W_C-1 downto + cIdxInt*RESP_QP_W_C); + end if; + + cValid := respValid and (not cFlag or qpRespValid(cIdxInt)); + cFire := srvRespReady and cValid; + + respRdEn <= cFire; + if (cFire = '1' and cFlag = '1') then + vQpRespReady(cIdxInt) := '1'; + end if; + srvRespValid <= cValid; + srvRespData <= cResp; + + -- Synchronous reset (dummy register only) + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + + qpReqValid <= vQpReqValid; + qpRespReady <= vQpRespReady; + + end process comb; + + ----------------------------------------------------------------------------- + -- Sequential process: register update + async reset option. + ----------------------------------------------------------------------------- + seq : process (clk, rst) is + begin + if (RST_ASYNC_G and rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + + ----------------------------------------------------------------------------- + -- Combinational status methods (Moore-style reads of the tag vector). + -- getPD = getItem(getIndexQP(qpn)); isValidQP = the Maybe tag of the same + -- lookup (getPdMaybeValid). notEmpty/notFull are wired at U_QpTagVec. + ----------------------------------------------------------------------------- + getPdMaybeValid <= tagGetOut(PD_W_C); + getPdHandler <= tagGetOut(PD_W_C-1 downto 0); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/MetaDataSrv.vhd b/ethernet/RoCEv2/rtl/MetaDataSrv.vhd new file mode 100644 index 0000000000..434a457dd8 --- /dev/null +++ b/ethernet/RoCEv2/rtl/MetaDataSrv.vhd @@ -0,0 +1,467 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Classic 7-state Moore dispatcher (the only sibling in MetaData.bsv with a +-- real stateReg). Demultiplexes an incoming MetaDataReq (tagged union +-- PD/MR/QP) to the matching metadata sub-server, waits one state for the +-- response, and enqueues a MetaDataResp. Strictly one request in flight +-- ("Do not use pipeline to avoid conflict requests", MetaData.bsv:692): +-- RECV_REQ -> {MR,PD,QP}_REQ -> {MR,PD,QP}_RESP -> RECV_REQ. +-- +-- pdMetaData / qpMetaData are BSV module ARGUMENTS (interfaces passed in by +-- mkTransportLayer), NOT children of this module. Per the OQ-FSM-MDSRV-01 +-- resolution they surface here as external CLIENT port groups, wired by the +-- parent TransportLayer to the sibling MetaDataPDs / MetaDataQPs entities: +-- * pdReq*/pdResp* <-> MetaDataPDs.srvReq*/srvResp* +-- * isValidPdHandler/isValidPd <-> MetaDataPDs.isValidPdHandler/isValidPd +-- * mrSrv* <-> MetaDataPDs.mrSrv* (getMRs4PD interface- +-- return flattened; group added to MetaDataPDs per RESOLVED section 4.1) +-- * qpReq*/qpResp* <-> MetaDataQPs.srvReq*/srvResp* (parent nets +-- should be named mdSrvQp* to avoid MetaDataQPs' own qpReq* bundle) +-- +-- Invalid-PD behaviour (faithful to BSV `if` predication — do NOT over-gate): +-- * MR path: when mrSrvPdValid='0' no MR sub-server is touched; a default +-- RespMR{successOrNot=False, mr/lkey/rkey echoed from the request} is +-- enqueued immediately (MetaData.bsv:740-745). +-- * QP path: when isValidPd='0' no QP request is issued; a default +-- RespQP{successOrNot=False, qpn/pdHandler/qpAttr/qpInitAttr echoed} +-- is enqueued immediately (MetaData.bsv:767-773). +-- isValidPd / mrSrvPdValid are combinational lookups in MetaDataPDs, driven +-- from held registers here, and cannot change between the REQ and RESP +-- states of one op (PD dealloc only flows through this same serialized FSM). +-- +-- Bit packing (BSV deriving(Bits), first-field-at-MSB; unions tag-at-MSB +-- with LSB-justified payload — project convention): +-- MetaDataReq [302:0] : tag[302:301] (Req4PD=00, Req4MR=01, Req4QP=10), +-- payload LSB-justified in [300:0] (ReqPD [63:0], ReqMR [251:0], +-- ReqQP [300:0]); unused high payload bits ignored. +-- MetaDataResp [275:0]: tag[275:274] (Resp4PD=00, Resp4MR=01, Resp4QP=10), +-- payload LSB-justified in [273:0], zero-filled above. +-- ReqMR [251:0] : allocOrNot[251] mr[250:65] lkeyOrNot[64] lkey[63:32] +-- rkey[31:0] +-- RespMR [250:0] : successOrNot[250] mr[249:64] lkey[63:32] rkey[31:0] +-- MemRegion [185:0] (within mr): laddr[185:122] len[121:90] accFlags[89:82] +-- pdHandler[81:50] lkeyPart[49:25] rkeyPart[24:0] +-- => mrReq.mr.pdHandler = ReqMR[146:115] +-- ReqPD [63:0] : allocOrNot[63] pdKey[62:32] pdHandler[31:0] +-- (NOTE: fsm.md's REQ_PD_W=65 was an off-by-one; 64 b is correct, +-- reconciled against MetaDataPDs.srvReqData(63:0) — RESOLVED section 3) +-- RespPD [63:0] : successOrNot[63] pdHandler[62:31] pdKey[30:0] +-- ReqQP [300:0] : qpReqType[300:299] pdHandler[298:267] qpn[266:243] +-- qpAttrMask[242:217] qpAttr[216:5] qpInitAttr[4:0] +-- RespQP [273:0] : successOrNot[273] qpn[272:249] pdHandler[248:217] +-- qpAttr[216:5] qpInitAttr[4:0] +-- +-- SURF instances (BSV mkFIFOF -> surf.Fifo, sync FWFT, 16-deep at the +-- ADDR_WIDTH_G=4 minimum; extra depth over BSV's 2-deep is behaviour- +-- preserving for the notFull/notEmpty handshake, same call as OQ-EMIT-PCS-02): +-- U_MetaDataReqQ : surf.Fifo DATA_WIDTH_G=303, FWFT, sync, block +-- U_MetaDataRespQ : surf.Fifo DATA_WIDTH_G=276, FWFT, sync, block +-- +-- mkRegU note: mrReqReg/pdReqReg/qpReqReg have NO reset in BSV (mkRegU); +-- write-before-read is guaranteed by the REQ->RESP state ordering. Their +-- REG_INIT_C zeros are don't-care initials, not functional resets. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity MetaDataSrv is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + ----------------------------------------------------------------------- + -- srvPort : Server#(MetaDataReq(303b), MetaDataResp(276b)) + -- (request face: caller enq; ready = U_MetaDataReqQ not full) + ----------------------------------------------------------------------- + srvReqValid : in sl; + srvReqData : in slv(302 downto 0); -- MetaDataReq + srvReqReady : out sl; + -- (response face; FWFT: srvRespReady = caller deq strobe) + srvRespValid : out sl; + srvRespData : out slv(275 downto 0); -- MetaDataResp + srvRespReady : in sl; + ----------------------------------------------------------------------- + -- pdMetaData.srvPort client (-> MetaDataPDs.srvReq*/srvResp*) + ----------------------------------------------------------------------- + pdReqValid : out sl; + pdReqData : out slv(63 downto 0); -- ReqPD + pdReqReady : in sl; + pdRespValid : in sl; + pdRespData : in slv(63 downto 0); -- RespPD + pdRespReady : out sl; + ----------------------------------------------------------------------- + -- pdMetaData.isValidPD lookup (-> MetaDataPDs.isValidPdHandler/isValidPd) + -- combinational; sampled in QP_REQ_S and QP_RESP_S + ----------------------------------------------------------------------- + isValidPdHandler : out slv(31 downto 0); -- = qpReqReg.pdHandler + isValidPd : in sl; + ----------------------------------------------------------------------- + -- pdMetaData.getMRs4PD interface-return, flattened MR sub-server client + -- (-> MetaDataPDs.mrSrv* group, RESOLVED OQ-FSM-MDSRV-01 section 2.3/4.1) + ----------------------------------------------------------------------- + mrSrvPdHandler : out slv(31 downto 0); -- = mrReqReg.mr.pdHandler + mrSrvPdValid : in sl; -- isValid(getMRs4PD(handler)) + mrSrvReqValid : out sl; + mrSrvReqData : out slv(251 downto 0); -- ReqMR + mrSrvReqReady : in sl; + mrSrvRespValid : in sl; + mrSrvRespData : in slv(250 downto 0); -- RespMR + mrSrvRespReady : out sl; + ----------------------------------------------------------------------- + -- qpMetaData.srvPort client (-> MetaDataQPs.srvReq*/srvResp*) + ----------------------------------------------------------------------- + qpReqValid : out sl; + qpReqData : out slv(300 downto 0); -- ReqQP + qpReqReady : in sl; + qpRespValid : in sl; + qpRespData : in slv(273 downto 0); -- RespQP + qpRespReady : out sl); +end entity MetaDataSrv; + +architecture rtl of MetaDataSrv is + + --------------------------------------------------------------------------- + -- Widths (traced, see header packing table) + --------------------------------------------------------------------------- + constant MD_REQ_W_C : integer := 303; -- MetaDataReq = 2 + 301 + constant MD_RESP_W_C : integer := 276; -- MetaDataResp = 2 + 274 + + -- MetaDataReq / MetaDataResp union tags (declaration order = encoding) + constant TAG_PD_C : slv(1 downto 0) := "00"; + constant TAG_MR_C : slv(1 downto 0) := "01"; + constant TAG_QP_C : slv(1 downto 0) := "10"; + + --------------------------------------------------------------------------- + -- Types and records + --------------------------------------------------------------------------- + type StateType is ( + RECV_REQ_S, -- META_DATA_RECV_REQ (000) + MR_REQ_S, -- META_DATA_MR_REQ (001) + PD_REQ_S, -- META_DATA_PD_REQ (010) + QP_REQ_S, -- META_DATA_QP_REQ (011) + MR_RESP_S, -- META_DATA_MR_RESP (100) + PD_RESP_S, -- META_DATA_PD_RESP (101) + QP_RESP_S); -- META_DATA_QP_RESP (110) + + type RegType is record + state : StateType; + mrReq : slv(251 downto 0); -- mrReqReg (BSV mkRegU — init is don't-care) + pdReq : slv(63 downto 0); -- pdReqReg (BSV mkRegU — init is don't-care) + qpReq : slv(300 downto 0); -- qpReqReg (BSV mkRegU — init is don't-care) + end record RegType; + + constant REG_INIT_C : RegType := ( + state => RECV_REQ_S, -- mkReg(META_DATA_RECV_REQ) + mrReq => (others => '0'), + pdReq => (others => '0'), + qpReq => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + --------------------------------------------------------------------------- + -- U_MetaDataReqQ (303 b) : srvPort.request write side / recvMetaDataReq read + --------------------------------------------------------------------------- + signal reqQWrEn : sl; + signal reqQNotFull : sl; + signal reqQRdEn : sl; + signal reqQValid : sl; + signal reqQDout : slv(MD_REQ_W_C-1 downto 0); + + --------------------------------------------------------------------------- + -- U_MetaDataRespQ (276 b) : genResp4* write side / srvPort.response read + --------------------------------------------------------------------------- + signal respQWrEn : sl; + signal respQDin : slv(MD_RESP_W_C-1 downto 0); + signal respQNotFull : sl; + signal respQRdEn : sl; + signal respQValid : sl; + signal respQDout : slv(MD_RESP_W_C-1 downto 0); + +begin + + --------------------------------------------------------------------------- + -- U_MetaDataReqQ : BSV metaDataReqQ (mkFIFOF), server request face + -- source: surf/base/fifo/rtl/Fifo.vhd + --------------------------------------------------------------------------- + U_MetaDataReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => MD_REQ_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => reqQWrEn, + din => srvReqData, + not_full => reqQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => reqQRdEn, + dout => reqQDout, + valid => reqQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_MetaDataRespQ : BSV metaDataRespQ (mkFIFOF), server response face + -- source: surf/base/fifo/rtl/Fifo.vhd + --------------------------------------------------------------------------- + U_MetaDataRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => MD_RESP_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => respQWrEn, + din => respQDin, + not_full => respQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => respQRdEn, + dout => respQDout, + valid => respQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Server face glue (toGPServer(metaDataReqQ, metaDataRespQ), MetaData.bsv:784) + --------------------------------------------------------------------------- + reqQWrEn <= srvReqValid and reqQNotFull; + srvReqReady <= reqQNotFull; + + srvRespValid <= respQValid; + srvRespData <= respQDout; + respQRdEn <= srvRespReady and respQValid; + + --------------------------------------------------------------------------- + -- Combinational process — one BSV rule per state branch, atomic v-blocks + --------------------------------------------------------------------------- + comb : process (isValidPd, mrSrvPdValid, mrSrvReqReady, mrSrvRespData, + mrSrvRespValid, pdReqReady, pdRespData, pdRespValid, + qpReqReady, qpRespData, qpRespValid, r, reqQDout, reqQValid, + respQNotFull, rst) is + variable v : RegType; + variable vReqQRdEn : sl; + variable vRespQWrEn : sl; + variable vRespQDin : slv(MD_RESP_W_C-1 downto 0); + variable vPdReqValid : sl; + variable vPdRespRdy : sl; + variable vMrReqValid : sl; + variable vMrRespRdy : sl; + variable vQpReqValid : sl; + variable vQpRespRdy : sl; + variable vMrResp : slv(250 downto 0); + variable vQpResp : slv(273 downto 0); + begin + v := r; + + -- strobe defaults + vReqQRdEn := '0'; + vRespQWrEn := '0'; + vRespQDin := (others => '0'); + vPdReqValid := '0'; + vPdRespRdy := '0'; + vMrReqValid := '0'; + vMrRespRdy := '0'; + vQpReqValid := '0'; + vQpRespRdy := '0'; + + case r.state is + ------------------------------------------------------------------ + -- rule recvMetaDataReq (MetaData.bsv:693-711) + ------------------------------------------------------------------ + when RECV_REQ_S => + if (reqQValid = '1') then + vReqQRdEn := '1'; -- metaDataReqQ.deq + case reqQDout(302 downto 301) is + when TAG_MR_C => + v.mrReq := reqQDout(251 downto 0); + v.state := MR_REQ_S; + when TAG_PD_C => + v.pdReq := reqQDout(63 downto 0); + v.state := PD_REQ_S; + when TAG_QP_C => + v.qpReq := reqQDout(300 downto 0); + v.state := QP_REQ_S; + when others => + null; -- tag "11" unreachable; request dropped + end case; + end if; + + ------------------------------------------------------------------ + -- rule issueReq4MR (MetaData.bsv:713-721) + -- put only when getMRs4PD hit; advance unconditionally + ------------------------------------------------------------------ + when MR_REQ_S => + if (mrSrvPdValid = '0') then + v.state := MR_RESP_S; -- no MR server touched + else + vMrReqValid := '1'; -- srvPort.request.put + if (mrSrvReqReady = '1') then + v.state := MR_RESP_S; + end if; + end if; + + ------------------------------------------------------------------ + -- rule issueReq4PD (MetaData.bsv:723-727) — unconditional put + ------------------------------------------------------------------ + when PD_REQ_S => + vPdReqValid := '1'; -- srvPort.request.put + if (pdReqReady = '1') then + v.state := PD_RESP_S; + end if; + + ------------------------------------------------------------------ + -- rule issueReq4QP (MetaData.bsv:729-736) + -- put only when isValidPD; advance unconditionally + ------------------------------------------------------------------ + when QP_REQ_S => + if (isValidPd = '0') then + v.state := QP_RESP_S; -- no QP request issued + else + vQpReqValid := '1'; -- srvPort.request.put + if (qpReqReady = '1') then + v.state := QP_RESP_S; + end if; + end if; + + ------------------------------------------------------------------ + -- rule genResp4MR (MetaData.bsv:738-755) + -- default RespMR{successOrNot=False, mr, lkey, rkey} unless PD hit + ------------------------------------------------------------------ + when MR_RESP_S => + vMrResp := '0' & r.mrReq(250 downto 65) & r.mrReq(63 downto 0); + if (mrSrvPdValid = '1') then + vMrResp := mrSrvRespData; -- srvPort.response.get + end if; + if (respQNotFull = '1') and + ((mrSrvPdValid = '0') or (mrSrvRespValid = '1')) then + if (mrSrvPdValid = '1') then + vMrRespRdy := '1'; -- deq MR server response + end if; + vRespQWrEn := '1'; -- metaDataRespQ.enq + vRespQDin(275 downto 274) := TAG_MR_C; + vRespQDin(250 downto 0) := vMrResp; + v.state := RECV_REQ_S; + end if; + + ------------------------------------------------------------------ + -- rule genResp4PD (MetaData.bsv:757-763) — unconditional get + ------------------------------------------------------------------ + when PD_RESP_S => + if (pdRespValid = '1') and (respQNotFull = '1') then + vPdRespRdy := '1'; -- srvPort.response.get + vRespQWrEn := '1'; -- metaDataRespQ.enq + vRespQDin(275 downto 274) := TAG_PD_C; + vRespQDin(63 downto 0) := pdRespData; + v.state := RECV_REQ_S; + end if; + + ------------------------------------------------------------------ + -- rule genResp4QP (MetaData.bsv:765-782) + -- default RespQP{successOrNot=False, qpn, pdHandler, qpAttr, + -- qpInitAttr} unless PD valid + ------------------------------------------------------------------ + when QP_RESP_S => + vQpResp := '0' & r.qpReq(266 downto 243) -- qpn + & r.qpReq(298 downto 267) -- pdHandler + & r.qpReq(216 downto 5) -- qpAttr + & r.qpReq(4 downto 0); -- qpInitAttr + if (isValidPd = '1') then + vQpResp := qpRespData; -- srvPort.response.get + end if; + if (respQNotFull = '1') and + ((isValidPd = '0') or (qpRespValid = '1')) then + if (isValidPd = '1') then + vQpRespRdy := '1'; -- deq QP server response + end if; + vRespQWrEn := '1'; -- metaDataRespQ.enq + vRespQDin(275 downto 274) := TAG_QP_C; + vRespQDin(273 downto 0) := vQpResp; + v.state := RECV_REQ_S; + end if; + + end case; + + -- synchronous reset + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + + -- FIFO strobes and handshake outputs (Mealy strobes, single-cycle) + reqQRdEn <= vReqQRdEn; + respQWrEn <= vRespQWrEn; + respQDin <= vRespQDin; + pdReqValid <= vPdReqValid; + pdRespReady <= vPdRespRdy; + mrSrvReqValid <= vMrReqValid; + mrSrvRespReady <= vMrRespRdy; + qpReqValid <= vQpReqValid; + qpRespReady <= vQpRespRdy; + + -- Moore data outputs from held registers (stable across REQ->RESP pairs) + pdReqData <= r.pdReq; + mrSrvReqData <= r.mrReq; + mrSrvPdHandler <= r.mrReq(146 downto 115); -- mrReqReg.mr.pdHandler + qpReqData <= r.qpReq; + isValidPdHandler <= r.qpReq(298 downto 267); -- qpReqReg.pdHandler + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd b/ethernet/RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd new file mode 100644 index 0000000000..f4cb5d2a10 --- /dev/null +++ b/ethernet/RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd @@ -0,0 +1,295 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Accepts upstream WorkReq items and converts them to PendingWorkReq by +-- appending four Invalid-Maybe fields (78 bits of zeros), then enqueues them +-- into an output FIFO (U_OutQ). Tracks the number of in-flight pending work +-- requests via a CountCF sub-entity (U_PendingCnt, 8 bits). +-- +-- Three mutually-exclusive QP-state predicates drive three BSV rules: +-- resetAndClear — continuous FIFO clear + counter reset +-- while isReset_i='1' +-- flushWR — consume and forward WR when QP is in ERR state +-- genPendingWR — consume, forward, and increment count in RTS +-- A fourth rule, decrPendingNewWorkReqCnt, decrements the count on an +-- external completion pulse and may fire simultaneously with genPendingWR. +-- +-- No local registered state: all state lives in U_OutQ and U_PendingCnt. +-- The two-process skeleton is retained for uniformity; the RegType record +-- carries a single dummy field so the VHDL compiles without an empty record. +-- The comb process drives sub-instance control ports only. +-- +-- SURF components instantiated: +-- U_OutQ : surf.Fifo (DATA_WIDTH_G=679, FWFT, sync, block RAM) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- +-- Project entities instantiated: +-- U_PendingCnt : work.CountCF (WIDTH_G=8; tick FIFOs depth CNT_ADDR_WIDTH_G) +-- source: out/04-vhdl/CountCF.vhd +-- +-- FIFO clear (OQ-FSM-NPWRPO-02, resolved via OQ-FSM-06 in RESOLVED.md): +-- outQRst is held HIGH as a level for the duration that isReset_i='1'. +-- surf.FifoSync has no edge-detection on rst; holding it continuously +-- pins the FIFO logically empty. No pulse-generator needed. +-- +-- PendingWorkReq bit-packing (OQ-FSM-NPWRPO-03, resolved in RESOLVED.md): +-- BSV deriving(Bits) packs first-field-at-MSB. +-- Bits 678:78 = WorkReq (601 b), bits 77:0 = four Invalid-Maybe zeros: +-- isOnlyReqPkt [1:0], pktNum [27:2], endPSN [52:28], startPSN [77:53]. +-- VHDL: outQDin = workReqData_i & (77 downto 0 => '0'). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity NewPendingWorkReqPipeOut is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; -- U_OutQ depth = 2**G entries + CNT_ADDR_WIDTH_G : positive range 4 to 48 := 4; -- U_PendingCnt tick-FIFO depth + MAX_QP_WR_G : positive := 32); -- Settings.bsv MAX_QP_WR + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- QP state predicates — mutually exclusive; guaranteed by CntrlQP semantics + isReset_i : in sl; + isERR_i : in sl; + isRTS_i : in sl; + -- QP attribute: configured maximum number of pending work requests + getPendingWorkReqNum_i : in slv(7 downto 0); + -- External completion pulse: a pending WR has been acknowledged/completed + decrPendingReqCntPulse_i : in sl; + -- Upstream WorkReq PipeIn (workReqPipeIn) + workReqValid_i : in sl; + workReqData_i : in slv(600 downto 0); -- WorkReq, 601 bits + workReqRdy_o : out sl; + -- Output PipeOut (newPendingWorkReqOutQ exposed via U_OutQ) + outQValid_o : out sl; + outQDout_o : out slv(678 downto 0); -- PendingWorkReq, 679 bits + outQRdEn_i : in sl); +end NewPendingWorkReqPipeOut; + +architecture rtl of NewPendingWorkReqPipeOut is + + -- No local FSM state: all state in U_OutQ and U_PendingCnt. + -- One dummy bit keeps the RegType record syntactically non-empty. + type RegType is record + dummy : sl; + end record RegType; + + constant REG_INIT_C : RegType := (dummy => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- genNewPendingWorkReq packing constant (OQ-FSM-NPWRPO-03 resolved): + -- Four Invalid-Maybe fields occupy bits 77:0 of PendingWorkReq — all zeros. + constant MAYBE_PAD_C : slv(77 downto 0) := (others => '0'); + + -- U_OutQ signals + signal outQRst : sl; + signal outQWrEn : sl; + signal outQDin : slv(678 downto 0); + signal outQNotFull : sl; + + -- U_PendingCnt (CountCF) control signals + signal pendingCntOut : slv(7 downto 0); + signal pendingCntIncrEn : sl; + signal pendingCntDecrEn : sl; + signal pendingCntWriteEn : sl; + signal pendingCntWriteVal : slv(7 downto 0); + + -- Global reset normalised to active-high (for FIFO rst port) + signal rstActiveHigh : sl; + +begin + + -- Normalise global rst to active-high + rstActiveHigh <= rst when (RST_POLARITY_G = '1') else not rst; + + -- FIFO clear level: held '1' for the full duration of isReset_i='1'. + -- surf.FifoSync re-applies REG_INIT_C every cycle rst is asserted; + -- releasing rst makes the FIFO usable on the very next cycle. (OQ-FSM-06) + outQRst <= rstActiveHigh or isReset_i; + + -- genNewPendingWorkReq(wr): WorkReq in MSBs, Invalid-Maybe zeros in LSBs. + -- Packing is identical for both flushWR and genPendingWR paths. + outQDin <= workReqData_i & MAYBE_PAD_C; + + -------------------------------------------------------------------------- + -- U_OutQ : newPendingWorkReqOutQ + -- BSV: FIFOF#(PendingWorkReq), instantiated as mkFIFO (depth 2, FWFT) + -- SURF: surf.Fifo, GEN_SYNC_FIFO_G=true, FWFT_EN_G=true + -- Width: 679 bits (WorkReq 601b + four Invalid-Maybe fields 78b) + -------------------------------------------------------------------------- + U_OutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 679, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => outQRst, + wr_clk => clk, + wr_en => outQWrEn, + din => outQDin, + not_full => outQNotFull, + rd_clk => clk, + rd_en => outQRdEn_i, + dout => outQDout_o, + valid => outQValid_o); + + -------------------------------------------------------------------------- + -- U_PendingCnt : pendingNewWorkReqCnt + -- BSV: mkCountCF(0), PendingReqCnt = Bit#(QP_CAP_CNT_WIDTH) = Bit#(8) + -- Project entity: surf.CountCF, WIDTH_G=8, reset value = 0 + -------------------------------------------------------------------------- + U_PendingCnt : entity surf.CountCF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + WIDTH_G => 8, + FIFO_ADDR_WIDTH_G => CNT_ADDR_WIDTH_G) + port map ( + clk => clk, + rst => rst, + incrOneEn => pendingCntIncrEn, + incrOneRdy => open, + decrOneEn => pendingCntDecrEn, + decrOneRdy => open, + writeEn => pendingCntWriteEn, + writeVal => pendingCntWriteVal, + cntOut => pendingCntOut); + + -------------------------------------------------------------------------- + -- Combinatorial: per-cycle rule evaluation + -- All outputs are Mealy (from current inputs, not from registered state). + -- Rules are mutually exclusive per QP-state predicate: + -- isReset_i / isERR_i / isRTS_i are guaranteed disjoint by CntrlQP. + -- decrPendingNewWorkReqCnt may fire simultaneously with genPendingWR; + -- CountCF handles simultaneous incr+decr as a net-zero operation. + -------------------------------------------------------------------------- + comb : process (r, rst, isReset_i, isERR_i, isRTS_i, getPendingWorkReqNum_i, + decrPendingReqCntPulse_i, workReqValid_i, + outQNotFull, pendingCntOut) is + variable v : RegType; + variable wrRdyV : sl; + variable outQWrV : sl; + variable incrEnV : sl; + variable decrEnV : sl; + variable cntWrEnV : sl; + variable cntWrValV : slv(7 downto 0); + begin + v := r; + + -- Default all Mealy outputs to inactive + wrRdyV := '0'; + outQWrV := '0'; + incrEnV := '0'; + decrEnV := '0'; + cntWrEnV := '0'; + cntWrValV := (others => '0'); + + -- Rule: resetAndClear (no_implicit_conditions, fire_when_enabled) + -- Fires every cycle isReset='1'. + -- U_OutQ is cleared via the outQRst level signal (concurrent above). + -- U_PendingCnt is reset to 0 via write(). + if (isReset_i = '1') then + cntWrEnV := '1'; + cntWrValV := (others => '0'); + end if; + + -- Rule: flushWR (ERR_S implied state) + -- Consume upstream WR and enqueue PendingWorkReq; no count increment. + if (isERR_i = '1') and (workReqValid_i = '1') and (outQNotFull = '1') then + wrRdyV := '1'; + outQWrV := '1'; + end if; + + -- Rule: genPendingWR (RTS_S implied state) + -- Guard: pendingCnt + 1 < getPendingWorkReqNum (one slot reserved). + -- Equivalent to BSV: pendingCntRd < getPendingWorkReqNum - 1. + -- Using (count+1 < max) avoids unsigned-subtraction underflow when max=0 + -- (safe: in valid operation max >= 1). + if (isRTS_i = '1') and + (unsigned(pendingCntOut) + 1 < unsigned(getPendingWorkReqNum_i)) and + (workReqValid_i = '1') and (outQNotFull = '1') then + wrRdyV := '1'; + outQWrV := '1'; + incrEnV := '1'; + end if; + + -- Rule: decrPendingNewWorkReqCnt (RTS_S; may fire same cycle as genPendingWR) + if (isRTS_i = '1') and (decrPendingReqCntPulse_i = '1') then + decrEnV := '1'; + end if; + + -- Synchronous reset (dummy field only; no live state to restore) + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + + -- Drive outputs + workReqRdy_o <= wrRdyV; + outQWrEn <= outQWrV; + pendingCntIncrEn <= incrEnV; + pendingCntDecrEn <= decrEnV; + pendingCntWriteEn <= cntWrEnV; + pendingCntWriteVal <= cntWrValV; + + end process comb; + + -------------------------------------------------------------------------- + -- Sequential: register update (skeleton only; no live registered fields) + -------------------------------------------------------------------------- + seq : process (clk, rst) is + begin + if (RST_ASYNC_G) and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + + -- pragma translate_off + -------------------------------------------------------------------------- + -- Simulation assertions + -- checkPendingNewWorkReqCnt (QueuePair.bsv:133-143): MAX_QP_WR >= count + -- decrPendingNewWorkReqCnt immAssert (QueuePair.bsv:121-128): count > 0 + -------------------------------------------------------------------------- + check : process (clk) is + begin + if rising_edge(clk) then + assert unsigned(pendingCntOut) <= to_unsigned(MAX_QP_WR_G, 8) + report "NewPendingWorkReqPipeOut: pendingCnt > MAX_QP_WR" severity error; + if (pendingCntDecrEn = '1') then + assert unsigned(pendingCntOut) > 0 + report "NewPendingWorkReqPipeOut: pendingCnt underflow on decrement" severity error; + end if; + end if; + end process check; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd b/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd new file mode 100644 index 0000000000..7ca08eb4f8 --- /dev/null +++ b/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd @@ -0,0 +1,764 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- A dataflow pipeline (NOT a classic state-enum FSM). Accepts a PayloadConReq +-- (the server request), counts its fragments, pulls the matching number of +-- payload fragments out of a BRAM buffer (via child ConnectPipeOut2BramQConAndGen), +-- and per request either DISCARDs the payload, emits a dummy ATOMIC response, or +-- DMA-WRITEs the payload — issuing one DmaWriteReq to the external +-- dmaWriteCntrl.srvPort and, on the last fragment, generating a PayloadConResp +-- from the DMA write response. +-- +-- Pipeline stages (each a BSV rule, gated by FIFO occupancy + mode): +-- R1 recvReq — decode the request, classify tag, enq U_CountReqFragQ. +-- R2 countReqFrag — the ONLY sequential control state: a per-request fragment +-- down-counter (sub-FSM A); emits one U_PendingConReqQ entry +-- per fragment (holds the U_CountReqFragQ head until the last +-- fragment for non-discard requests). +-- R3 consumePayload— per tag: Discard (drain payload frags), Atomic (enq resp + +-- dma token, no payload read), SendWrite (read payload frag, +-- enq dma token, enq resp on last frag). +-- R4 issueDmaReq — Put one DmaWriteReq to dmaWriteSrv (SendWrite: payload; +-- Atomic: synthesised atomic dataStream; Discard: no put). +-- R5 genConResp — get the DmaWriteResp, build the PayloadConResp, enq it. +-- R6 flushDmaWriteResp / R7 flushPipelineQ / R8 flushPayloadConResp — error-mode +-- drains (see Clear / error-flush below). +-- +-- Mode inputs (cntrlStatus.comm; one-hot, NOT state): +-- isReset guards R0 (clear all); isNonErr guards R1-R5; isErr guards R1-R3,R6-R8. +-- In isNonErr: R1-R5 active, flushes idle. In isErr: R1-R3 + R6-R8 active, +-- R4/R5 idle. +-- +-- The ONLY sequential state (sub-FSM A counter, rule countReqFrag): +-- isFirstOrOnlyFragReg : sl reset '1' (FRAG_FIRST_S / FRAG_REST_S bit) +-- isRemainingFragNumZeroReg : sl reset '0' (countdown-reached-zero flag) +-- remainingFragNumReg : slv(7:0) mkRegU, NO RESET (only meaningful in +-- FRAG_REST_S; written before read). REG_INIT_C +-- gives it 0 only to constrain the constant. +-- countReqFrag enqueues the CURRENT (pre-update) isFirstOrOnlyFragReg into +-- U_PendingConReqQ, then updates the regs — so the comb uses r.isFirstOrOnlyFragReg +-- for the din and writes v.* for the next value (standard two-process). +-- +-- Clear / error-flush (fsm.md §Clear mapping, §Conflicts): +-- R0 resetAndClear (isReset): clear ALL 7 FIFOs + child skid (clearEnI); force +-- the two reset-valued counter regs. +-- R7 flushPipelineQ (isErr): clear U_PayloadBufQ, U_PendingConReqQ, U_PendingDmaReqQ. +-- R8 flushPayloadConResp (isErr): clear U_PayloadConRespQ. +-- These map to per-FIFO synchronous resets OR'd with the structural rst: +-- Rst = rst OR isReset [OR isErr for the R7/R8 targets]. +-- BSV mkFIFOF.clear is sequenced-BEFORE enq/deq, so in an error cycle the flush +-- DOMINATES any concurrent R3 enq (drain wins). Asserting the FIFO rst (level) +-- nullifies the same-cycle wr_en, reproducing that ordering structurally — no +-- extra wr_en gating needed (the cleared queues read empty, so the dependent +-- rules see notEmpty='0' and take no effect). Requires GEN_SYNC_FIFO_G=true, +-- RST_ASYNC_G=false, RST_POLARITY_G='1'. +-- +-- Boundaries: +-- * Server to its caller (srvPort: request Put PayloadConReq via U_PayloadConReqQ; +-- response Get PayloadConResp via U_PayloadConRespQ). +-- * Client of the external Server dmaWriteSrv (= dmaWriteCntrl.srvPort): request +-- Put DmaWriteReq (R4); response Get DmaWriteResp (R5 / R6). +-- * payloadPipeIn (DataStreamPipeOut input) → child → U_PayloadBufQ (parent-owned +-- BRAM buffer) → child pipeOut → FSM (R3). +-- +-- Output style (fsm.md §Moore vs Mealy): the counter regs are registered (Moore); +-- all inter-stage handoff is via registered SURF FIFOs; FIFO din/wrEn/rdEn and the +-- dmaWriteSrv request/response handshakes are combinational from v/r (Mealy w.r.t. +-- the FIFO write port — standard SURF two-process). No combinational path exists +-- between server request and response (always >=1 FIFO of latency). R4's +-- dmaWriteReqValid is asserted INDEPENDENT of dmaWriteReqReady (AXI-Stream master +-- rule); the dequeue is gated by valid AND ready (Stage-5 TC-06 fix, see R4). +-- +-- Open-question carry-forwards (out/04-vhdl/OPEN_QUESTIONS.md, fsm.md §Open issues): +-- OQ-FSM-PCCAG-01 / OQ-RHSQ-03 — RESOLVED (DEVIATION-PCCAG-01, Rq Stage-5 +-- integration TC-09). PayloadConInfo tagged-union intra-member alignment: +-- BSV deriving(Bits) LSB-justifies (zero-extends) narrower members. Only the +-- 193b AtomicRespInfoAndPayload struct has its DmaWriteMetaData MSB-aligned at +-- consumeInfo[192:64] (atomicRespPayload at [63:0]); the 129b members +-- SendWriteReqReadRespInfo and DiscardPayloadInfo sit at consumeInfo[128:0]. +-- The original emit assumed a uniform [192:64] slice (per the OQ-RHSQ-03 +-- producer note) — WRONG for SendWrite/Discard, corrupting the DmaWriteReq +-- metadata and PayloadConResp.psn (caught by WorkCompGenRq's PSN assert). +-- R4/R5 now select the metaData slice by tag (tag="01" Atomic → [192:64], +-- else → [128:0]), matching the ReqHandleRq producer's LSB-aligned packing. +-- OQ-EMIT-PCCAG-02 (new) — the fsm.md R4-Atomic note "byteEn=genByteEn(8)= +-- byteEn[7:0]='1'" is INCORRECT. genByteEn(n)=reverseBits((1< MSB; tagged-union tag at MSB; +-- fsm.md §Type widths / OQ-FSM-H2DS-04): +-- +-- DataStream (290b): +-- [289:34] data(256) [33:2] byteEn(32) [1] isFirst [0] isLast +-- DmaWriteMetaData (129b): +-- [128:125] initiator(4) [124:101] sqpn(24) [100:37] startAddr(64) +-- [36:24] len(13) [23:0] psn(24) +-- DmaWriteReq (419b) — dmaWriteReqData: +-- [418:290] metaData(129) [289:0] dataStream(290) +-- DmaWriteResp (53b) — dmaWriteRespData / PayloadConResp: +-- [52:49] initiator(4) [48:25] sqpn(24) [24:1] psn(24) [0] isRespErr +-- PayloadConInfo (195b): [194:193] tag (Discard=0,Atomic=1,SendWrite=2), +-- [192:0] member data, LSB-justified per BSV deriving(Bits): +-- tag=01 (Atomic, 193b struct): DmaWriteMetaData at [192:64], +-- atomicRespPayload(64) at [63:0]; +-- tag=00/10 (Discard/SendWrite, 129b): DmaWriteMetaData at [128:0]. +-- PayloadConReq (203b): [202:195] fragNum(8) [194:0] consumeInfo(195) +-- PayloadConResp (53b): DmaWriteResp(53) +-- Tuple3 countReqFragQ (205b): [204:2] consumeReq(203) [1] isFragNumLessOrEqOne [0] isDiscardReq +-- Tuple4 pendingConReqQ (206b): [205:3] consumeReq(203) [2] isFragNumLessOrEqOne +-- [1] isFirstOrOnlyFrag [0] isLastReqFrag +-- Tuple2 pendingDmaReqQ (493b): [492:290] consumeReq(203) [289:0] payload(DataStream) +-- +-- Helpers (PrimUtils.bsv:30-55, Utils.bsv:161-163; ATOMIC_WORK_REQ_LEN=8): +-- isLessOrEqOne(b) = (b(7:1)=0); isTwo(b)=(b(7:2)=0 and b(1) and not b(0)); +-- isOne(b)=(b(7:1)=0 and b(0)); genByteEn(8)=0xFF000000; +-- zeroExtendLSB(p64)= p64 & 0(192) into the 256b data field. +-- +-- SURF components instantiated (sources: surf/base/fifo/rtl/Fifo.vhd and +-- surf/base/fifo/rtl/inferred/FifoSync.vhd): +-- U_PayloadConReqQ : surf.Fifo DATA_WIDTH_G=203 (PayloadConReq) +-- U_PayloadConRespQ : surf.Fifo DATA_WIDTH_G=53 (PayloadConResp) +-- U_CountReqFragQ : surf.Fifo DATA_WIDTH_G=205 (Tuple3) +-- U_PendingConReqQ : surf.Fifo DATA_WIDTH_G=206 (Tuple4) +-- U_GenConRespQ : surf.Fifo DATA_WIDTH_G=203 (PayloadConReq) +-- U_PendingDmaReqQ : surf.Fifo DATA_WIDTH_G=493 (Tuple2) +-- U_PayloadBufQ : surf.FifoSync DATA_WIDTH_G=290, depth 256 (BRAM; bramQ +-- wired between the child's pipeIn and pipeOut paths) +-- Child entity instantiated: +-- U_PipeOut2Bram : ConnectPipeOut2BramQConAndGen +-- (out/04-vhdl/ConnectPipeOut2BramQConAndGen.vhd, DATA_W_G=290) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity PayloadConsumerConAndGen is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- cntrlStatus.comm mode inputs (one-hot; NOT state) + isReset : in sl; -- comm.isReset (guards R0 clear) + isNonErr : in sl; -- comm.isNonErr (guards R1-R5) + isErr : in sl; -- comm.isERR (guards R1-R3,R6-R8) + -- srvPort.request : Put#(PayloadConReq) (caller -> entity, enq payloadConReqQ) + reqInValid : in sl; -- caller offers a request (wr_en) + reqInData : in slv(202 downto 0); -- PayloadConReq packed + reqInReady : out sl; -- entity can accept (notFull) + -- srvPort.response : Get#(PayloadConResp) (entity -> caller, deq payloadConRespQ) + respOutReady : in sl; -- caller takes a response (rd_en) + respOutValid : out sl; -- response available (notEmpty) + respOutData : out slv(52 downto 0); -- PayloadConResp packed + -- payloadPipeIn : DataStreamPipeOut (caller -> entity; consumed by child) + payloadPipeInValid : in sl; -- pipeIn.notEmpty + payloadPipeInData : in slv(289 downto 0); -- pipeIn.first (DataStream) + payloadPipeInReady : out sl; -- pipeIn deq (back to caller) + -- dmaWriteSrv.request : Put#(DmaWriteReq) (entity -> external server, CLIENT) + dmaWriteReqValid : out sl; -- entity offers a request (Mealy) + dmaWriteReqData : out slv(418 downto 0); -- DmaWriteReq packed (Mealy) + dmaWriteReqReady : in sl; -- external server can accept + -- dmaWriteSrv.response : Get#(DmaWriteResp) (external server -> entity, CLIENT) + dmaWriteRespValid : in sl; -- external server offers a response + dmaWriteRespData : in slv(52 downto 0); -- DmaWriteResp packed + dmaWriteRespReady : out sl); -- entity takes the response (get) +end entity PayloadConsumerConAndGen; + +architecture rtl of PayloadConsumerConAndGen is + + -- Atomic-path constants (R4): zeroExtendLSB fill + genByteEn(ATOMIC_WORK_REQ_LEN=8) + constant ZERO_192_C : slv(191 downto 0) := (others => '0'); + constant ATOMIC_BYTE_EN_C : slv(31 downto 0) := x"FF000000"; -- top 8 bytes valid + + -- Sub-FSM A counter state (the only sequential control state). + type RegType is record + isFirstOrOnlyFragReg : sl; -- mkReg(True) -> '1' + isRemainingFragNumZeroReg : sl; -- mkReg(False) -> '0' + remainingFragNumReg : slv(7 downto 0);-- mkRegU (NO RESET; written-before-read) + end record RegType; + + constant REG_INIT_C : RegType := ( + isFirstOrOnlyFragReg => '1', + isRemainingFragNumZeroReg => '0', + remainingFragNumReg => (others => '0')); -- don't-care init (mkRegU) + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_PayloadConReqQ (PayloadConReq, 203b) + signal payReqValid : sl; + signal payReqDout : slv(202 downto 0); + signal payReqRdEn : sl; + signal payReqRst : sl; + + -- U_PayloadConRespQ (PayloadConResp, 53b) + signal payRespNotFull : sl; + signal payRespWrEn : sl; + signal payRespDin : slv(52 downto 0); + signal payRespRst : sl; + + -- U_CountReqFragQ (Tuple3, 205b) + signal countNotFull : sl; + signal countValid : sl; + signal countWrEn : sl; + signal countDin : slv(204 downto 0); + signal countRdEn : sl; + signal countDout : slv(204 downto 0); + signal countRst : sl; + + -- U_PendingConReqQ (Tuple4, 206b) + signal pendConNotFull : sl; + signal pendConValid : sl; + signal pendConWrEn : sl; + signal pendConDin : slv(205 downto 0); + signal pendConRdEn : sl; + signal pendConDout : slv(205 downto 0); + signal pendConRst : sl; + + -- U_GenConRespQ (PayloadConReq, 203b) + signal genRespNotFull : sl; + signal genRespValid : sl; + signal genRespWrEn : sl; + signal genRespDin : slv(202 downto 0); + signal genRespRdEn : sl; + signal genRespDout : slv(202 downto 0); + signal genRespRst : sl; + + -- U_PendingDmaReqQ (Tuple2, 493b) + signal pendDmaNotFull : sl; + signal pendDmaValid : sl; + signal pendDmaWrEn : sl; + signal pendDmaDin : slv(492 downto 0); + signal pendDmaRdEn : sl; + signal pendDmaDout : slv(492 downto 0); + signal pendDmaRst : sl; + + -- U_PayloadBufQ (DataStream, 290b; FifoSync BRAM) <-> child bramQ ports + signal bufNotFull : sl; + signal bufValid : sl; + signal bufWrEn : sl; + signal bufDin : slv(289 downto 0); + signal bufRdEn : sl; + signal bufDout : slv(289 downto 0); + signal bufRst : sl; + + -- Child pipeOut (DataStream, 290b) consumed by FSM (R3) + signal bufPipeNotEmpty : sl; + signal bufPipeFirst : slv(289 downto 0); + signal bufPipeDeq : sl; + +begin + + --------------------------------------------------------------------------- + -- Per-FIFO synchronous clear lines (resetAndClear R0 + error flush R7/R8). + --------------------------------------------------------------------------- + payReqRst <= rst or isReset; + payRespRst <= rst or isReset or isErr; -- + R8 + countRst <= rst or isReset; + pendConRst <= rst or isReset or isErr; -- + R7 + genRespRst <= rst or isReset; + pendDmaRst <= rst or isReset or isErr; -- + R7 + bufRst <= rst or isReset or isErr; -- + R7 + + -- srvPort response valid/data are driven directly by U_PayloadConRespQ + -- (valid => respOutValid, dout => respOutData below); request ready by + -- U_PayloadConReqQ (not_full => reqInReady). + + --------------------------------------------------------------------------- + -- U_PayloadConReqQ : surf.Fifo + -- Inbound PayloadConReq (BSV mkFIFOF payloadConReqQ). wr = caller's + -- srvPort.request.put (pass-through); rd = FSM (recvReq R1). + --------------------------------------------------------------------------- + U_PayloadConReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 203, + ADDR_WIDTH_G => 4) + port map ( + rst => payReqRst, + wr_clk => clk, + wr_en => reqInValid, -- pass-through (caller drives) + din => reqInData, -- pass-through (caller drives) + not_full => reqInReady, -- pass-through to caller + rd_clk => clk, + rd_en => payReqRdEn, -- FSM (recvReq) + dout => payReqDout, + valid => payReqValid); + + --------------------------------------------------------------------------- + -- U_PayloadConRespQ : surf.Fifo + -- Outbound PayloadConResp (BSV mkFIFOF payloadConRespQ). wr = FSM + -- (genConResp R5); rd = caller's srvPort.response.get (pass-through). + --------------------------------------------------------------------------- + U_PayloadConRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 53, + ADDR_WIDTH_G => 4) + port map ( + rst => payRespRst, + wr_clk => clk, + wr_en => payRespWrEn, -- FSM (genConResp) + din => payRespDin, -- FSM (genConResp) + not_full => payRespNotFull, + rd_clk => clk, + rd_en => respOutReady, -- pass-through (caller drives) + dout => respOutData, + valid => respOutValid); + + --------------------------------------------------------------------------- + -- U_CountReqFragQ : surf.Fifo + -- Tuple3(PayloadConReq,isFragNumLessOrEqOne,isDiscardReq). + -- wr = FSM (recvReq R1); rd = FSM (countReqFrag R2, held until last frag). + --------------------------------------------------------------------------- + U_CountReqFragQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 205, + ADDR_WIDTH_G => 4) + port map ( + rst => countRst, + wr_clk => clk, + wr_en => countWrEn, -- FSM (recvReq) + din => countDin, -- FSM (recvReq) + not_full => countNotFull, + rd_clk => clk, + rd_en => countRdEn, -- FSM (countReqFrag) + dout => countDout, + valid => countValid); + + --------------------------------------------------------------------------- + -- U_PendingConReqQ : surf.Fifo + -- Tuple4(PayloadConReq,isFragNumLessOrEqOne,isFirstOrOnlyFrag,isLastReqFrag). + -- wr = FSM (countReqFrag R2); rd = FSM (consumePayload R3). Error-flushed (R7). + --------------------------------------------------------------------------- + U_PendingConReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 206, + ADDR_WIDTH_G => 4) + port map ( + rst => pendConRst, + wr_clk => clk, + wr_en => pendConWrEn, -- FSM (countReqFrag) + din => pendConDin, -- FSM (countReqFrag) + not_full => pendConNotFull, + rd_clk => clk, + rd_en => pendConRdEn, -- FSM (consumePayload) + dout => pendConDout, + valid => pendConValid); + + --------------------------------------------------------------------------- + -- U_GenConRespQ : surf.Fifo + -- PayloadConReq pending a DMA-write response (BSV mkFIFOF genConRespQ). + -- wr = FSM (consumePayload R3, Atomic + SendWrite-last); rd = FSM (genConResp R5). + --------------------------------------------------------------------------- + U_GenConRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 203, + ADDR_WIDTH_G => 4) + port map ( + rst => genRespRst, + wr_clk => clk, + wr_en => genRespWrEn, -- FSM (consumePayload) + din => genRespDin, -- FSM (consumePayload) + not_full => genRespNotFull, + rd_clk => clk, + rd_en => genRespRdEn, -- FSM (genConResp) + dout => genRespDout, + valid => genRespValid); + + --------------------------------------------------------------------------- + -- U_PendingDmaReqQ : surf.Fifo + -- Tuple2(PayloadConReq,DataStream) awaiting issue to dmaWriteSrv. + -- wr = FSM (consumePayload R3); rd = FSM (issueDmaReq R4). Error-flushed (R7). + --------------------------------------------------------------------------- + U_PendingDmaReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 493, + ADDR_WIDTH_G => 4) + port map ( + rst => pendDmaRst, + wr_clk => clk, + wr_en => pendDmaWrEn, -- FSM (consumePayload) + din => pendDmaDin, -- FSM (consumePayload) + not_full => pendDmaNotFull, + rd_clk => clk, + rd_en => pendDmaRdEn, -- FSM (issueDmaReq) + dout => pendDmaDout, + valid => pendDmaValid); + + --------------------------------------------------------------------------- + -- U_PayloadBufQ : surf.FifoSync (BSV mkSizedBRAMFIFOF, depth 256) + -- Parent-owned BRAM buffer wired between the child's pipeIn and pipeOut + -- paths. The FSM never reads it directly (it reads the child's pipeOut); + -- it only clears it (R0/R7) via bufRst. Driven entirely by the child's + -- bramQ port group. ADDR_WIDTH_G=8 (depth 256). + --------------------------------------------------------------------------- + U_PayloadBufQ : entity surf.FifoSync + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + MEMORY_TYPE_G => "block", + FWFT_EN_G => true, + DATA_WIDTH_G => 290, + ADDR_WIDTH_G => 8) + port map ( + rst => bufRst, + clk => clk, + wr_en => bufWrEn, -- child bramQ.enq + rd_en => bufRdEn, -- child bramQ.deq + din => bufDin, -- child bramQ data + dout => bufDout, -- -> child bramQFirst + valid => bufValid, -- -> child bramQNotEmpty + not_full => bufNotFull); -- -> child bramQNotFull + + --------------------------------------------------------------------------- + -- U_PipeOut2Bram : ConnectPipeOut2BramQConAndGen (child entity, not SURF) + -- BSV: mkConnectPipeOut2BramQ(payloadPipeIn, payloadBufQ). Moves DataStream + -- from the entity input pipe through U_PayloadBufQ and presents pipeOut to + -- the FSM. Its internal skid is cleared on R0 only (clearEnI <= isReset). + --------------------------------------------------------------------------- + U_PipeOut2Bram : entity surf.ConnectPipeOut2BramQConAndGen + generic map ( + TPD_G => TPD_G, + DATA_W_G => 290) + port map ( + clk => clk, + rst => rst, + clearEnI => isReset, -- R0 child clear + -- pipeIn (entity input pipe) + pipeInNotEmpty => payloadPipeInValid, + pipeInFirst => payloadPipeInData, + pipeInDeq => payloadPipeInReady, + -- bramQ (parent-owned U_PayloadBufQ) + bramQNotFull => bufNotFull, + bramQWrEn => bufWrEn, + bramQDin => bufDin, + bramQNotEmpty => bufValid, + bramQFirst => bufDout, + bramQDeq => bufRdEn, + -- pipeOut (to FSM, R3) + pipeOutDeq => bufPipeDeq, + pipeOutFirst => bufPipeFirst, + pipeOutNotEmpty => bufPipeNotEmpty, + notEmpty => open); -- parent does not use the aggregate method + + --------------------------------------------------------------------------- + -- Combinatorial process (fsm.md §Conflicts §Suggested comb order) + --------------------------------------------------------------------------- + comb : process (r, rst, isReset, isNonErr, isErr, + payReqValid, payReqDout, + payRespNotFull, + countNotFull, countValid, countDout, + pendConNotFull, pendConValid, pendConDout, + genRespNotFull, genRespValid, genRespDout, + pendDmaNotFull, pendDmaValid, pendDmaDout, + bufPipeNotEmpty, bufPipeFirst, + dmaWriteReqReady, dmaWriteRespValid, dmaWriteRespData) is + variable v : RegType; + -- R1 recvReq datapath (off U_PayloadConReqQ front) + variable tagR1 : slv(1 downto 0); + variable fragNumR1 : slv(7 downto 0); + variable isDiscardR1 : sl; + variable isLeqOneR1 : sl; + -- R2 countReqFrag datapath (off U_CountReqFragQ front) + variable consumeR2 : slv(202 downto 0); + variable fragNumR2 : slv(7 downto 0); + variable isLeqOneR2 : sl; + variable isDiscardR2 : sl; + variable isLastFragR2 : sl; + -- R3 consumePayload datapath (off U_PendingConReqQ front + child pipeOut) + variable consumeR3 : slv(202 downto 0); + variable tagR3 : slv(1 downto 0); + variable isLastFragR3 : sl; + variable payloadLastR3 : sl; + -- R4 issueDmaReq datapath (off U_PendingDmaReqQ front) + variable consumeR4 : slv(202 downto 0); + variable payloadR4 : slv(289 downto 0); + variable tagR4 : slv(1 downto 0); + variable metaR4 : slv(128 downto 0); + variable atomicPayR4 : slv(63 downto 0); + variable atomicDsR4 : slv(289 downto 0); + variable dmaReqDataV : slv(418 downto 0); + -- R5 genConResp datapath (off U_GenConRespQ front + dmaWriteResp) + variable tagR5 : slv(1 downto 0); + variable metaR5 : slv(128 downto 0); + begin + v := r; + + ---------------------------------------------------------------------- + -- Combinational datapath extraction (harmless every cycle). + ---------------------------------------------------------------------- + -- R1 + tagR1 := payReqDout(194 downto 193); + fragNumR1 := payReqDout(202 downto 195); + if tagR1 = "00" then isDiscardR1 := '1'; else isDiscardR1 := '0'; end if; + if fragNumR1(7 downto 1) = "0000000" then isLeqOneR1 := '1'; else isLeqOneR1 := '0'; end if; + + -- R2 + consumeR2 := countDout(204 downto 2); + isLeqOneR2 := countDout(1); + isDiscardR2 := countDout(0); + fragNumR2 := consumeR2(202 downto 195); + if isLeqOneR2 = '1' then + isLastFragR2 := '1'; + else + isLastFragR2 := r.isRemainingFragNumZeroReg; + end if; + + -- R3 + consumeR3 := pendConDout(205 downto 3); + isLastFragR3 := pendConDout(0); + tagR3 := consumeR3(194 downto 193); + payloadLastR3 := bufPipeFirst(0); + + -- R4 + consumeR4 := pendDmaDout(492 downto 290); + payloadR4 := pendDmaDout(289 downto 0); + tagR4 := consumeR4(194 downto 193); + -- DmaWriteMetaData slice is TAG-DEPENDENT (DEVIATION-PCCAG-01): only the + -- 193b Atomic struct member is metadata-MSB-aligned; the 129b members + -- (SendWrite/Discard) are LSB-justified per BSV deriving(Bits). + if tagR4 = "01" then -- Atomic struct member + metaR4 := consumeR4(192 downto 64); + else -- SendWrite/Discard 129b member + metaR4 := consumeR4(128 downto 0); + end if; + atomicPayR4 := consumeR4(63 downto 0); + -- atomic DataStream: data = zeroExtendLSB(payload64) -> payload at MSB; + -- byteEn = genByteEn(8) = 0xFF000000; isFirst='1'; isLast='1' + atomicDsR4 := atomicPayR4 & ZERO_192_C & ATOMIC_BYTE_EN_C & '1' & '1'; + if tagR4 = "01" then -- Atomic + dmaReqDataV := metaR4 & atomicDsR4; + else -- SendWrite (Discard: unused) + dmaReqDataV := metaR4 & payloadR4; + end if; + + -- R5 (same tag-dependent metaData slice as R4; genRespDout carries the + -- 203b PayloadConReq layout, tag at [194:193]) + tagR5 := genRespDout(194 downto 193); + if tagR5 = "01" then -- Atomic struct member + metaR5 := genRespDout(192 downto 64); + else -- SendWrite/Discard 129b member + metaR5 := genRespDout(128 downto 0); + end if; + + ---------------------------------------------------------------------- + -- Default outputs / SURF & child drives (deasserted; din/data = fronts). + ---------------------------------------------------------------------- + payReqRdEn <= '0'; + countWrEn <= '0'; + countDin <= payReqDout & isLeqOneR1 & isDiscardR1; -- 203+1+1=205 + countRdEn <= '0'; + pendConWrEn <= '0'; + pendConDin <= consumeR2 & isLeqOneR2 & r.isFirstOrOnlyFragReg & isLastFragR2; -- 203+1+1+1=206 + pendConRdEn <= '0'; + genRespWrEn <= '0'; + genRespDin <= consumeR3; -- PayloadConReq (203) + genRespRdEn <= '0'; + pendDmaWrEn <= '0'; + pendDmaDin <= consumeR3 & bufPipeFirst; -- 203+290=493 (SendWrite) + pendDmaRdEn <= '0'; + payRespWrEn <= '0'; + -- PayloadConResp = DmaWriteResp{initiator,sqpn,psn from meta; isRespErr from resp} + payRespDin <= metaR5(128 downto 125) & metaR5(124 downto 101) & + metaR5(23 downto 0) & dmaWriteRespData(0); -- 4+24+24+1=53 + bufPipeDeq <= '0'; + dmaWriteReqValid <= '0'; + dmaWriteReqData <= dmaReqDataV; -- Mealy front (R4) + dmaWriteRespReady <= '0'; + + ---------------------------------------------------------------------- + -- R1 recvReq : (isNonErr||isErr) && payReqQ.notEmpty && countReqFragQ.notFull + ---------------------------------------------------------------------- + if ((isNonErr = '1' or isErr = '1') and payReqValid = '1' and countNotFull = '1') then + payReqRdEn <= '1'; -- deq U_PayloadConReqQ + countWrEn <= '1'; -- enq U_CountReqFragQ (din set above) + end if; + + ---------------------------------------------------------------------- + -- R2 countReqFrag : sub-FSM A. Always enq U_PendingConReqQ with the CURRENT + -- isFirstOrOnlyFragReg; deq U_CountReqFragQ only on discard or last frag. + ---------------------------------------------------------------------- + if ((isNonErr = '1' or isErr = '1') and countValid = '1' and pendConNotFull = '1') then + pendConWrEn <= '1'; -- enq U_PendingConReqQ (din set above) + if isDiscardR2 = '1' then + countRdEn <= '1'; -- deq (no counter update) + elsif isLastFragR2 = '1' then + countRdEn <= '1'; + v.isFirstOrOnlyFragReg := '1'; + v.isRemainingFragNumZeroReg := '0'; + else + -- hold the U_CountReqFragQ head (no deq); advance the down-counter + if r.isFirstOrOnlyFragReg = '1' then + v.remainingFragNumReg := slv(unsigned(fragNumR2) - 2); + v.isFirstOrOnlyFragReg := '0'; + -- isRemainingFragNumZeroReg := isTwo(fragNum) + if (fragNumR2(7 downto 2) = "000000" and fragNumR2(1) = '1' and + fragNumR2(0) = '0') then + v.isRemainingFragNumZeroReg := '1'; + else + v.isRemainingFragNumZeroReg := '0'; + end if; + else + v.remainingFragNumReg := slv(unsigned(r.remainingFragNumReg) - 1); + -- isRemainingFragNumZeroReg := isOne(remainingFragNumReg) + if (r.remainingFragNumReg(7 downto 1) = "0000000" and + r.remainingFragNumReg(0) = '1') then + v.isRemainingFragNumZeroReg := '1'; + else + v.isRemainingFragNumZeroReg := '0'; + end if; + end if; + end if; + end if; + + ---------------------------------------------------------------------- + -- R3 consumePayload : per-tag. Whole-branch atomic — if the branch's + -- implicit conditions fail, none of its actions (incl. the pendConReq deq) + -- take effect. + ---------------------------------------------------------------------- + if ((isNonErr = '1' or isErr = '1') and pendConValid = '1') then + case tagR3 is + when "00" => -- Discard: drain one payload fragment + if bufPipeNotEmpty = '1' then + bufPipeDeq <= '1'; + if payloadLastR3 = '1' then -- shouldDeqConReq = payload.isLast + pendConRdEn <= '1'; + end if; + end if; + when "01" => -- Atomic: dummy resp + dma token, no payload + if (genRespNotFull = '1' and pendDmaNotFull = '1') then + genRespWrEn <= '1'; + pendDmaWrEn <= '1'; + pendDmaDin <= consumeR3 & (289 downto 0 => '0'); -- payload dontCare + pendConRdEn <= '1'; + end if; + when "10" => -- SendWrite: payload + dma token (+resp on last) + if (bufPipeNotEmpty = '1' and pendDmaNotFull = '1' and + (isLastFragR3 = '0' or genRespNotFull = '1')) then + bufPipeDeq <= '1'; + if isLastFragR3 = '1' then + genRespWrEn <= '1'; + end if; + pendDmaWrEn <= '1'; -- pendDmaDin default = consumeR3 & payload + pendConRdEn <= '1'; + end if; + when others => + null; + end case; + end if; + + ---------------------------------------------------------------------- + -- R4 issueDmaReq : isNonErr only. Discard deqs without a Put; SendWrite/ + -- Atomic Put one DmaWriteReq. + -- AXI-Stream / SURF master rule: dmaWriteReqValid is asserted whenever a + -- non-Discard token is available (Mealy from pendDmaValid), INDEPENDENT of + -- dmaWriteReqReady; the transfer (FIFO dequeue) is gated by valid AND ready. + -- dmaWriteReqData is already driven combinationally (dmaReqDataV) and is held + -- stable while the token sits at the FIFO front, so valid+data hold across a + -- ready-low stall with no extra logic. (Stage-5 TC-06 fix: previously valid + -- was asserted only inside `if dmaWriteReqReady='1'`, making valid depend on + -- ready — a handshake violation / potential combinational deadlock.) + ---------------------------------------------------------------------- + if (isNonErr = '1' and pendDmaValid = '1') then + case tagR4 is + when "00" => -- Discard: deq, no DMA put + pendDmaRdEn <= '1'; + when others => -- SendWrite / Atomic: Put + dmaWriteReqValid <= '1'; -- valid independent of ready (data = dmaReqDataV) + if dmaWriteReqReady = '1' then + pendDmaRdEn <= '1'; -- dequeue only on accept (valid AND ready) + end if; + end case; + end if; + + ---------------------------------------------------------------------- + -- R5 genConResp : isNonErr. Get DmaWriteResp, build PayloadConResp, enq. + ---------------------------------------------------------------------- + if (isNonErr = '1' and dmaWriteRespValid = '1' and genRespValid = '1' and + payRespNotFull = '1') then + dmaWriteRespReady <= '1'; -- get external response + genRespRdEn <= '1'; -- deq U_GenConRespQ + payRespWrEn <= '1'; -- enq U_PayloadConRespQ (din set above) + end if; + + ---------------------------------------------------------------------- + -- R6 flushDmaWriteResp : isErr. Drop the DMA write response. + ---------------------------------------------------------------------- + if (isErr = '1' and dmaWriteRespValid = '1') then + dmaWriteRespReady <= '1'; -- get and discard + end if; + + ---------------------------------------------------------------------- + -- R0 resetAndClear (isReset) / hardware reset : force the two reset-valued + -- counter regs (remainingFragNumReg is mkRegU -> untouched). Dominates R2. + ---------------------------------------------------------------------- + if (rst = '1' or isReset = '1') then + v.isFirstOrOnlyFragReg := '1'; + v.isRemainingFragNumZeroReg := '0'; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/PayloadGeneratorConAndGen.vhd b/ethernet/RoCEv2/rtl/PayloadGeneratorConAndGen.vhd new file mode 100644 index 0000000000..82ab850052 --- /dev/null +++ b/ethernet/RoCEv2/rtl/PayloadGeneratorConAndGen.vhd @@ -0,0 +1,588 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Receives PayloadGenReq requests, issues one DmaReadCntrlReq per request to +-- the external dmaReadCntrl Server (this entity is its CLIENT), and re-streams +-- the returned DMA fragments into an output DataStream pipe, padding the last +-- fragment's byteEn when the request asked for padding. A single mode flag +-- (isNormalStateReg) switches the issue path off after a DMA response error. +-- +-- Two pipeline rules (conflict-free; may both fire the same cycle — they touch +-- disjoint FIFO endpoints and only lastFragAddPadding writes the mode flag): +-- recvPayloadGenReq (R1) — NORMAL mode (isNonErr ∧ isNormalStateReg): deq a +-- PayloadGenReq from U_PayloadGenReqQ; compute the padded last-fragment +-- byteEn + per-PMTU fragment count; enq Tuple3(req, byteEn, fragNum) into +-- the pipeline FIFO U_PendingGenReqQ; PUT a DmaReadCntrlReq{dmaReadMetaData, +-- pmtu} to the external dmaReadCntrl.request. (No mode-flag write.) +-- lastFragAddPadding (R2) — NORMAL or ERR mode (isNonErr ∨ isERR): GET one +-- DmaReadCntrlResp from dmaReadCntrl.response; read U_PendingGenReqQ.first; +-- on isOrigLast retire (deq) the pending entry and (if addPadding) override +-- the fragment byteEn with the precomputed padded byteEn; set +-- isNormalStateReg := NOT isRespErr; on (dataStream.isLast ∨ isRespErr) enq +-- a PayloadGenResp{addPadding, isRespErr} into U_PayloadGenRespQ; enq the +-- (possibly byteEn-patched) DataStream into the BRAM buffer U_PayloadBufQ. +-- +-- The entity is a Server to its caller (srvPort: request Put PayloadGenReq into +-- U_PayloadGenReqQ / response Get PayloadGenResp from U_PayloadGenRespQ — BSV +-- toGPServer(payloadGenReqQ, payloadGenRespQ)). Its DataStream output pipe and +-- payloadNotEmpty method are produced by the child U_BramQ2PipeOut, which owns +-- the read side of the BRAM buffer U_PayloadBufQ. +-- +-- Reliability note (memory: inventory-unreliable-payloadconandgen, +-- OQ-FSM-PGCAG-01): the Stage-1/2 records for this module are WRONG (fabricated +-- rule names recvReq/bufPayload/genResp; claim 0 state regs; omit pendingGenReqQ; +-- list DmaReadCntrlConAndGen as a child). This file follows the FSM spec / LIVE +-- BSV source: dmaReadCntrl is a MODULE PARAMETER (external Server → ports, NOT a +-- child instance); there are 4 FIFOs + 1 real child (U_BramQ2PipeOut). +-- +-- State register (fsm.md §State register): +-- isNormalStateReg : sl — NORMAL_S('1') / ERR_S('0'); reset '1'. The only +-- LIVE state. Read in R1's guard; written in R2 (:= NOT hasDmaRespErr). +-- Declared-but-dead regs (kept in RegType for source fidelity; assigned only by +-- the BSV resetAndClear; never read, never written by an active rule — drive +-- nothing): shouldSetFirstReg (mkReg False), isFragCntZeroReg (mkReg False), +-- pmtuFragCntReg (PktFragNum 8b, mkRegU — no reset; value irrelevant). +-- +-- Mealy (combinational) drives — MUST NOT be registered (would insert a spurious +-- cycle); the FIFOs latch them internally on the clock edge: +-- U_PendingGenReqQ.din, U_PayloadGenReqQ.rd_en, dmaReadCntrlReq{Valid,Out} (R1); +-- dmaReadCntrlRespReady, U_PendingGenReqQ.rd_en, U_PayloadGenRespQ.{wr_en,din}, +-- U_PayloadBufQ.{wr_en,din} (R2). isNormalStateReg is the only registered +-- (Moore) state. +-- +-- FIFO clear (OQ-FSM-01 carry-forward, RESOLVED in out/03-fsm/RESOLVED.md): +-- BSV payloadGenReqQ/payloadGenRespQ/pendingGenReqQ/payloadBufQ .clear map to +-- asserting each Fifo's rst, OR'd with the structural reset: fifoRst = rst OR +-- isReset. surf.Fifo/FifoSync (GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, +-- RST_POLARITY_G='1') holds the FIFO logically empty for the whole asserted +-- window (level-safe; no pulse generator). All four share fifoRst so the BSV +-- single-cycle simultaneous clear is preserved. The child clears via clearEnI. +-- +-- Helper functions (Utils.bsv) inlined below — verified against source: +-- calcPadCnt(len) = (0 - len[1:0]) mod 4 (PAD_WIDTH=2) +-- calcLastFragValidByteNum(len)= len[4:0], or 32 if len[4:0]=0 ∧ len[31:5]≠0 +-- genByteEn(n) = reverseBits((1< entity, enq to payloadGenReqQ) + reqInValid : in sl; -- caller offers a request (wr_en) + reqInData : in slv(198 downto 0); -- PayloadGenReq packed (199b) + reqInReady : out sl; -- entity can accept (notFull) + -- srvPort.response : Get#(PayloadGenResp) (entity -> caller, deq from payloadGenRespQ) + respOutReady : in sl; -- caller takes a response (rd_en) + respOutValid : out sl; -- response available (notEmpty) + respOutData : out slv(1 downto 0); -- PayloadGenResp packed (2b) + -- dmaReadCntrl.request : Put#(DmaReadCntrlReq) (entity -> external server, CLIENT) + dmaReadCntrlReqValid : out sl; -- entity offers a request (Mealy) + dmaReadCntrlReqData : out slv(197 downto 0); -- DmaReadCntrlReq packed (198b) + dmaReadCntrlReqReady : in sl; -- external server can accept + -- dmaReadCntrl.response : Get#(DmaReadCntrlResp) (external server -> entity, CLIENT) + dmaReadCntrlRespValid : in sl; -- external server offers a response + dmaReadCntrlRespData : in slv(384 downto 0); -- DmaReadCntrlResp packed (385b) + dmaReadCntrlRespReady : out sl; -- entity takes the response (get) + -- payloadDataStreamPipeOut : PipeOut#(DataStream) (entity output, via child) + payloadDataStreamDeq : in sl; -- consumer dequeues + payloadDataStreamFirst : out slv(289 downto 0); -- pipeOut.first (DataStream 290b) + payloadDataStreamNotEmpty : out sl; -- pipeOut.notEmpty + -- payloadNotEmpty() method result (Moore passthrough of the child) + payloadNotEmpty : out sl); +end entity PayloadGeneratorConAndGen; + +architecture rtl of PayloadGeneratorConAndGen is + + ----------------------------------------------------------------------------- + -- Width constants (traced from BSV; see header bit layouts) + ----------------------------------------------------------------------------- + constant PAYLOAD_GEN_REQ_W_C : positive := 199; -- PayloadGenReq + constant PAYLOAD_GEN_RESP_W_C : positive := 2; -- PayloadGenResp + constant PENDING_REQ_W_C : positive := 239; -- Tuple3 pipeline element + constant DATA_STREAM_W_C : positive := 290; -- DataStream (OQ-FSM-H2DS-02) + constant DMA_BYTE_WIDTH_C : natural := 32; -- DATA_BUS_BYTE_WIDTH + constant BUF_ADDR_WIDTH_C : positive := 8; -- depth 256 = DATA_STREAM_FRAG_BUF_SIZE + + ----------------------------------------------------------------------------- + -- Helper functions (Utils.bsv) — verified against source + ----------------------------------------------------------------------------- + -- calcPadCnt: PAD (2b) = (1<=32 -> all ones + function genByteEn (n : slv) return slv is + variable mask : slv(DMA_BYTE_WIDTH_C-1 downto 0) := (others => '0'); + variable cnt : integer; + begin + cnt := to_integer(unsigned(n)); + for i in mask'range loop + if (i < cnt) then + mask(i) := '1'; + end if; + end loop; + return bitReverse(mask); + end function genByteEn; + + -- calcFragNumByPMTU: PktFragNum (8b) = 1 << (getPmtuLogValue(pmtu) - log2(32)) + function calcFragNumByPMTU (pmtu : slv) return slv is + variable res : slv(7 downto 0); + begin + case pmtu is + when "001" => res := std_logic_vector(to_unsigned(8, 8)); -- IBV_MTU_256 + when "010" => res := std_logic_vector(to_unsigned(16, 8)); -- IBV_MTU_512 + when "011" => res := std_logic_vector(to_unsigned(32, 8)); -- IBV_MTU_1024 + when "100" => res := std_logic_vector(to_unsigned(64, 8)); -- IBV_MTU_2048 + when "101" => res := std_logic_vector(to_unsigned(128, 8)); -- IBV_MTU_4096 + when others => res := (others => '0'); + end case; + return res; + end function calcFragNumByPMTU; + + ----------------------------------------------------------------------------- + -- Register record (live mode flag + dead-but-faithful regs) + ----------------------------------------------------------------------------- + type RegType is record + isNormalStateReg : sl; -- NORMAL_S('1')/ERR_S('0'); reset '1' + -- dead: assigned only by BSV resetAndClear; never read/written live + shouldSetFirstReg : sl; -- mkReg(False) + isFragCntZeroReg : sl; -- mkReg(False) + pmtuFragCntReg : slv(7 downto 0); -- mkRegU (no reset; value irrelevant) + end record RegType; + + constant REG_INIT_C : RegType := ( + isNormalStateReg => '1', + shouldSetFirstReg => '0', + isFragCntZeroReg => '0', + pmtuFragCntReg => (others => '0')); -- mkRegU; '0' chosen, dead + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Shared FIFO clear: rst OR software clear (BSV *.clear under resetAndClear) + signal fifoRst : sl; + + -- U_PayloadGenReqQ (PayloadGenReq, 199b) + signal payloadGenReqQNotFull : sl; + signal payloadGenReqQValid : sl; -- = notEmpty (FWFT) + signal payloadGenReqQDout : slv(PAYLOAD_GEN_REQ_W_C-1 downto 0); + signal payloadGenReqQRdEn : sl; + + -- U_PayloadGenRespQ (PayloadGenResp, 2b) + signal payloadGenRespQNotFull : sl; + signal payloadGenRespQValid : sl; + signal payloadGenRespQDout : slv(PAYLOAD_GEN_RESP_W_C-1 downto 0); + signal payloadGenRespQWrEn : sl; + signal payloadGenRespQDin : slv(PAYLOAD_GEN_RESP_W_C-1 downto 0); + + -- U_PendingGenReqQ (Tuple3, 239b) + signal pendingGenReqQNotFull : sl; + signal pendingGenReqQValid : sl; + signal pendingGenReqQDout : slv(PENDING_REQ_W_C-1 downto 0); + signal pendingGenReqQWrEn : sl; + signal pendingGenReqQRdEn : sl; + signal pendingGenReqQDin : slv(PENDING_REQ_W_C-1 downto 0); + + -- U_PayloadBufQ (DataStream, 290b) — read side owned by U_BramQ2PipeOut + signal payloadBufQNotFull : sl; + signal payloadBufQValid : sl; -- = notEmpty (FWFT) + signal payloadBufQDout : slv(DATA_STREAM_W_C-1 downto 0); + signal payloadBufQWrEn : sl; + signal payloadBufQRdEn : sl; -- driven by child bramQDeq + signal payloadBufQDin : slv(DATA_STREAM_W_C-1 downto 0); + +begin + + ----------------------------------------------------------------------------- + -- Static wiring + ----------------------------------------------------------------------------- + -- FIFO clear (OQ-FSM-01, RESOLVED): level-sensitive flush via rst. + fifoRst <= rst or isReset; + + -- srvPort handshake passthroughs (BSV toGPServer implicit conditions) + reqInReady <= payloadGenReqQNotFull; -- request.put ready + respOutValid <= payloadGenRespQValid; -- response.get valid + respOutData <= payloadGenRespQDout; -- response.get data + + ----------------------------------------------------------------------------- + -- Combinatorial FSM (two conflict-free pipeline rules + sync soft-clear) + ----------------------------------------------------------------------------- + comb : process (r, rst, isReset, isNonErr, isERR, + payloadGenReqQValid, payloadGenReqQDout, pendingGenReqQNotFull, + dmaReadCntrlReqReady, dmaReadCntrlRespValid, dmaReadCntrlRespData, + pendingGenReqQValid, pendingGenReqQDout, + payloadBufQNotFull, payloadGenRespQNotFull) is + variable v : RegType; + -- recvPayloadGenReq temporaries + variable reqDmaMeta : slv(194 downto 0); + variable reqPmtu : slv(2 downto 0); + variable totalDmaLen : slv(31 downto 0); + variable padCnt : slv(1 downto 0); + variable lastFragVByteNum : slv(5 downto 0); + variable lastFragVByteNumWP: slv(5 downto 0); + variable lastFragByteEnWP : slv(31 downto 0); + variable pktFragNum : slv(7 downto 0); + variable recvFire : sl; + -- lastFragAddPadding temporaries + variable pendAddPadding : sl; + variable pendByteEnWP : slv(31 downto 0); + variable hasDmaRespErr : sl; + variable isOrigLast : sl; + variable curIsLast : sl; + variable curByteEn : slv(31 downto 0); + variable curDataOut : slv(DATA_STREAM_W_C-1 downto 0); + variable respEnq : sl; + variable lastFire : sl; + begin + v := r; + + -- Default combinational (Mealy) drives + payloadGenReqQRdEn <= '0'; + pendingGenReqQWrEn <= '0'; + pendingGenReqQDin <= (others => '0'); + dmaReadCntrlReqValid <= '0'; + dmaReadCntrlReqData <= (others => '0'); + dmaReadCntrlRespReady <= '0'; + pendingGenReqQRdEn <= '0'; + payloadGenRespQWrEn <= '0'; + payloadGenRespQDin <= (others => '0'); + payloadBufQWrEn <= '0'; + payloadBufQDin <= (others => '0'); + + ------------------------------------------------------------------------- + -- R1: recvPayloadGenReq (NORMAL issue) — no mode-flag write + ------------------------------------------------------------------------- + reqDmaMeta := payloadGenReqQDout(198 downto 4); -- dmaReadMetaData + reqPmtu := payloadGenReqQDout(2 downto 0); -- pmtu + totalDmaLen := payloadGenReqQDout(42 downto 11); -- dmaReadMetaData.len + + padCnt := calcPadCnt(totalDmaLen); + lastFragVByteNum := calcLastFragValidByteNum(totalDmaLen); + lastFragVByteNumWP := slv(unsigned(lastFragVByteNum) + resize(unsigned(padCnt), 6)); + lastFragByteEnWP := genByteEn(lastFragVByteNumWP); + pktFragNum := calcFragNumByPMTU(reqPmtu); + + recvFire := isNonErr and r.isNormalStateReg and payloadGenReqQValid + and pendingGenReqQNotFull and dmaReadCntrlReqReady; + + if (recvFire = '1') then + payloadGenReqQRdEn <= '1'; -- deq req + -- enq Tuple3(PayloadGenReq, lastFragByteEnWithPadding, pktFragNum) + pendingGenReqQWrEn <= '1'; + pendingGenReqQDin <= payloadGenReqQDout & lastFragByteEnWP & pktFragNum; + -- PUT DmaReadCntrlReq{dmaReadMetaData, pmtu} + dmaReadCntrlReqValid <= '1'; + dmaReadCntrlReqData <= reqDmaMeta & reqPmtu; + end if; + + ------------------------------------------------------------------------- + -- R2: lastFragAddPadding (drain DMA resp, pad last frag, set mode flag) + ------------------------------------------------------------------------- + -- pendingGenReqQ.first = Tuple3; PayloadGenReq=[238:40], addPadding bit=[43] + pendAddPadding := pendingGenReqQDout(43); + pendByteEnWP := pendingGenReqQDout(39 downto 8); -- lastFragByteEnWithPadding + + -- DmaReadCntrlResp fields + hasDmaRespErr := dmaReadCntrlRespData(292); -- dmaReadResp.isRespErr + isOrigLast := dmaReadCntrlRespData(0); -- isOrigLast + curIsLast := dmaReadCntrlRespData(2); -- dataStream.isLast + + -- byteEn override on the original last fragment when padding requested + if (isOrigLast = '1') and (pendAddPadding = '1') then + curByteEn := pendByteEnWP; + else + curByteEn := dmaReadCntrlRespData(35 downto 4); -- dataStream.byteEn + end if; + -- recompose curData: data | byteEn | isFirst | isLast + curDataOut := dmaReadCntrlRespData(291 downto 36) -- data(256) + & curByteEn -- byteEn(32) + & dmaReadCntrlRespData(3 downto 2); -- isFirst | isLast + + respEnq := curIsLast or hasDmaRespErr; + + -- payloadGenRespQ.notFull is an implicit condition ONLY when the enq is taken + lastFire := (isNonErr or isERR) and dmaReadCntrlRespValid and pendingGenReqQValid + and payloadBufQNotFull and (payloadGenRespQNotFull or (not respEnq)); + + if (lastFire = '1') then + dmaReadCntrlRespReady <= '1'; -- GET response + if (isOrigLast = '1') then + pendingGenReqQRdEn <= '1'; -- retire pending entry + end if; + v.isNormalStateReg := not hasDmaRespErr; -- registered mode flag + if (respEnq = '1') then + payloadGenRespQWrEn <= '1'; + -- PayloadGenResp{addPadding, isRespErr} + payloadGenRespQDin <= pendAddPadding & hasDmaRespErr; + end if; + payloadBufQWrEn <= '1'; + payloadBufQDin <= curDataOut; + end if; + + ------------------------------------------------------------------------- + -- resetAndClear (top priority): isReset is mutually exclusive with + -- isNonErr/isERR, so the worker drives above are already suppressed; the + -- register state is forced to its BSV reset. + ------------------------------------------------------------------------- + if (rst = '1') or (isReset = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + ----------------------------------------------------------------------------- + -- U_PayloadGenReqQ : surf.Fifo (BSV payloadGenReqQ <- mkFIFOF) + -- Write side = external srvPort.request; read side = recvPayloadGenReq. + ----------------------------------------------------------------------------- + U_PayloadGenReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PAYLOAD_GEN_REQ_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqInValid, + din => reqInData, + full => open, + not_full => payloadGenReqQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => payloadGenReqQRdEn, + dout => payloadGenReqQDout, + valid => payloadGenReqQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + ----------------------------------------------------------------------------- + -- U_PayloadGenRespQ : surf.Fifo (BSV payloadGenRespQ <- mkFIFOF) + -- Write side = lastFragAddPadding; read side = external srvPort.response. + -- 2-bit element -> distributed RAM (no BRAM read-latency penalty). + ----------------------------------------------------------------------------- + U_PayloadGenRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => PAYLOAD_GEN_RESP_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => payloadGenRespQWrEn, + din => payloadGenRespQDin, + full => open, + not_full => payloadGenRespQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => respOutReady, + dout => payloadGenRespQDout, + valid => payloadGenRespQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + ----------------------------------------------------------------------------- + -- U_PendingGenReqQ : surf.Fifo (BSV pendingGenReqQ <- mkFIFOF — pipeline) + -- Write side = recvPayloadGenReq; read side = lastFragAddPadding. + ----------------------------------------------------------------------------- + U_PendingGenReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PENDING_REQ_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pendingGenReqQWrEn, + din => pendingGenReqQDin, + full => open, + not_full => pendingGenReqQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pendingGenReqQRdEn, + dout => pendingGenReqQDout, + valid => pendingGenReqQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + ----------------------------------------------------------------------------- + -- U_PayloadBufQ : surf.Fifo (BSV payloadBufQ <- mkSizedBRAMFIFOF) + -- Write side = lastFragAddPadding; read side wired to the child + -- U_BramQ2PipeOut (it owns the dequeue / pipeOut re-export). + -- ADDR_WIDTH_G=8 -> depth 256 = DATA_STREAM_FRAG_BUF_SIZE. + ----------------------------------------------------------------------------- + U_PayloadBufQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DATA_STREAM_W_C, + ADDR_WIDTH_G => BUF_ADDR_WIDTH_C) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => payloadBufQWrEn, + din => payloadBufQDin, + full => open, + not_full => payloadBufQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => payloadBufQRdEn, + dout => payloadBufQDout, + valid => payloadBufQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + ----------------------------------------------------------------------------- + -- U_BramQ2PipeOut : ConnectBramQ2PipeOutConAndGen + -- Pulls fragments out of U_PayloadBufQ (bramQ side) into its internal skid + -- FIFO and re-exposes them as the entity's DataStream pipeOut + notEmpty. + -- clear() driven by isReset (BSV bramQ2PipeOut.clear in resetAndClear). + ----------------------------------------------------------------------------- + U_BramQ2PipeOut : entity surf.ConnectBramQ2PipeOutConAndGen + generic map ( + TPD_G => TPD_G, + DATA_W_G => DATA_STREAM_W_C) + port map ( + clk => clk, + rst => rst, + clearEnI => isReset, + -- upstream bramQ : Get#(DataStream) handshake on U_PayloadBufQ read side + bramQNotEmpty => payloadBufQValid, + bramQDout => payloadBufQDout, + bramQDeq => payloadBufQRdEn, + -- downstream pipeOut : PipeOut#(DataStream) + pipeOutDeq => payloadDataStreamDeq, + pipeOutFirst => payloadDataStreamFirst, + pipeOutNotEmpty => payloadDataStreamNotEmpty, + -- notEmpty() method result + notEmpty => payloadNotEmpty); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd b/ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd new file mode 100644 index 0000000000..9342de1df1 --- /dev/null +++ b/ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd @@ -0,0 +1,1265 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- A 7-stage feed-forward pipeline of FIFO-coupled rules (all conflict_free) +-- plus a small per-packet iterator FSM living in genPayloadGenResp. A +-- PayloadGenReqSG enters the srvPort.request; the pipeline splits the request +-- into per-packet PayloadGenRespSG descriptors (raddr / pktLen / padCnt / +-- isFirst / isLast) and re-streams the DMA-read payload (byteEn-padded on the +-- last fragment of first/last packets) out payloadDataStreamPipeOut. A +-- PayloadGenTotalMetaData is produced per request on totalMetaDataPipeOut. +-- +-- dmaReadCntrl is a MODULE PARAMETER (SendQ builds mkDmaReadCntrl and passes +-- it in), NOT a child instance — see fsm.md §Inventory/Partition Mismatch and +-- OQ-FSM-PGG-01. It is emitted as an external port group: a Client handshake +-- (request out / response in) plus TWO input PipeOuts (sgePktMetaData*, +-- sgeMergedMetaData*) that feed the two merge children. +-- +-- clearAll is the BSV module Bool parameter (→ clearAllI port): it guards +-- resetAndClear and appears as !clearAll on every worker rule, and is +-- forwarded to the four internal children. +-- +-- Iterator state (genPayloadGenResp only; single writer — no inter-rule reg +-- hazard, all rules conflict_free): +-- isFirstPktReg : sl mkReg(True); reset '1'. '1'=next packet is +-- FIRST of the current request. +-- pktRemoteAddrReg : slv(63:0) mkRegU (NO reset) — remote addr for next pkt. +-- remainingPktNumReg : slv(24:0) mkRegU (NO reset; PktNum=25b, OQ-FSM-PGG-01, +-- NOT the stale 16 in modules.json) — packets +-- still to emit; isLast when it reaches 1. +-- pktRemoteAddrReg/remainingPktNumReg are written in the isFirstPktReg='1' +-- branch before ever being read in the '0' branch, so the missing reset is safe. +-- +-- FIFO clear (OQ-FSM-01 family, RESOLVED): every FIFO reset is +-- fifoRst = rst OR clearAllI (level-safe synchronous flush of surf.Fifo / +-- FifoSync, RST_ASYNC_G=false, RST_POLARITY_G='1'). The four children clear +-- via their own clearAllI/clearEnI inputs. +-- +-- Struct bit layouts (BSV deriving(Bits), first-field-at-MSB; OQ-FSM-H2DS-04). +-- Base widths (traced): ADDR=64, Length=32, PktLen=13, PktNum=25, PMTU=3, +-- PAD=2, PktNumAddOn=2, ByteEnBitNum=6, ByteEn=32, PktFragNum=8, +-- DataStream=290, QPN=24, WorkReqID=64, LKEY=32, SGE=130, SGL=1040. +-- PayloadGenReqSG (1228): [1227:1164]wrID(64) [1163:1140]sqpn(24) +-- [1139:100]sgl(1040) [99:68]totalLen(32) [67:4]raddr(64) [3:1]pmtu(3) [0]addPadding +-- PayloadGenRespSG (81): [80:17]raddr(64) [16:4]pktLen(13) [3:2]padCnt(2) +-- [1]isFirst [0]isLast +-- PayloadGenTotalMetaData (27): [26:2]totalPktNum(25) [1]isOnlyPkt [0]isZeroPayloadLen +-- DataStream (290): [289:34]data(256) [33:2]byteEn(32) [1]isFirst [0]isLast +-- DmaReadCntrlReq (1163): [1162:123]sgl(1040) [122:91]totalLen(32) +-- [90:67]sqpn(24) [66:3]wrID(64) [2:0]pmtu(3) +-- DmaReadCntrlResp (385): [384:2]dmaReadResp(383) [1]isFirstFragInSGL +-- [0]isLastFragInSGL; within dmaReadResp: dataStream=[291:2] +-- Internal pipeline structs (packing is producer=consumer local; typedef order, +-- first-field-at-MSB): TmpPayloadGenMetaData=155, TmpAdjustFirstAndLastPktLen=247, +-- TmpAdjustTotalPayloadMetaData=229, AdjustedTotalPayloadMetaData=61, +-- TmpPayloadGenRespData=214, TmpPaddingData=66. Tuple2 = first elem at MSB. +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd — 11 FIFOs): +-- 10× surf.Fifo (FWFT, sync) + 1× surf.Fifo for the BRAM buffer +-- (U_PayloadBufQ: mkSizedBRAMFIFOF → surf.Fifo GEN_SYNC, block RAM, +-- ADDR_WIDTH_G=8 = DATA_STREAM_FRAG_BUF_SIZE = MIN_PKT_NUM_IN_RECV_BUF(2) * +-- PMTU_MAX_FRAG_NUM(128) = 256; read side owned by U_BramQ2PipeOut). +-- Child entities (4, from out/04-vhdl/): +-- U_SgeMergedPayload : MergePayloadEachSge +-- U_SglMergedPayload : MergePayloadAllSge +-- U_AdjustedPayload : AdjustPayloadSegment +-- U_BramQ2PipeOut : ConnectBramQ2PipeOutGen +-- +-- Mealy (combinational) drives — MUST NOT be registered (the FIFOs latch them +-- on the clock edge): every FIFO wr_en/din/rd_en and the dmaReadCntrl +-- request/response handshake. isFirstPktReg/pktRemoteAddrReg/remainingPktNumReg +-- are the only registered (Moore) state. payloadNotEmpty is a Moore passthrough +-- of the child. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity PayloadGeneratorGen is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high sync reset + -- Software clear (BSV module Bool parameter clearAll) + clearAllI : in sl; + -- srvPort.request : Put#(PayloadGenReqSG) (caller -> entity) + reqInValid : in sl; -- caller offers a request (wr_en) + reqInData : in slv(1227 downto 0); -- PayloadGenReqSG packed (1228b) + reqInReady : out sl; -- entity can accept (notFull) + -- srvPort.response : Get#(PayloadGenRespSG) (entity -> caller) + respOutReady : in sl; -- caller takes a response (rd_en) + respOutValid : out sl; -- response available (notEmpty) + respOutData : out slv(80 downto 0); -- PayloadGenRespSG packed (81b) + -- totalMetaDataPipeOut : PipeOut#(PayloadGenTotalMetaData) + totalMetaDataDeq : in sl; -- consumer dequeues + totalMetaDataFirst : out slv(26 downto 0); -- .first (27b) + totalMetaDataNotEmpty : out sl; -- .notEmpty + -- payloadDataStreamPipeOut : PipeOut#(DataStream) (via child U_BramQ2PipeOut) + payloadDataStreamDeq : in sl; -- consumer dequeues + payloadDataStreamFirst : out slv(289 downto 0); -- .first (DataStream 290b) + payloadDataStreamNotEmpty : out sl; -- .notEmpty + -- payloadNotEmpty() method result (Moore passthrough of the child) + payloadNotEmpty : out sl; + -- dmaReadCntrl.srvPort.request : Put#(DmaReadCntrlReq) (entity -> module param, CLIENT) + dmaReadCntrlReqValid : out sl; -- entity offers a request (Mealy) + dmaReadCntrlReqData : out slv(1162 downto 0); -- DmaReadCntrlReq packed (1163b) + dmaReadCntrlReqReady : in sl; -- module param can accept + -- dmaReadCntrl.srvPort.response : Get#(DmaReadCntrlResp) (module param -> entity, CLIENT) + dmaReadCntrlRespValid : in sl; -- module param offers a response + dmaReadCntrlRespData : in slv(384 downto 0); -- DmaReadCntrlResp packed (385b) + dmaReadCntrlRespReady : out sl; -- entity takes the response (get) + -- dmaReadCntrl.sgePktMetaDataPipeOut : PipeOut#(PktMetaDataSGE) (-> U_SgeMergedPayload) + sgePktMetaValid : in sl; -- .notEmpty + sgePktMetaData : in slv(53 downto 0); -- .first (PktMetaDataSGE 54b) + sgePktMetaRdEn : out sl; -- .deq + -- dmaReadCntrl.sgeMergedMetaDataPipeOut : PipeOut#(MergedMetaDataSGE) (-> U_SglMergedPayload) + sgeMergedMetaValid : in sl; -- .notEmpty + sgeMergedMetaData : in slv(7 downto 0); -- .first (MergedMetaDataSGE 8b) + sgeMergedMetaRdEn : out sl); -- .deq +end entity PayloadGeneratorGen; + +architecture rtl of PayloadGeneratorGen is + + ----------------------------------------------------------------------------- + -- Width constants (traced from BSV; see header) + ----------------------------------------------------------------------------- + constant ADDR_W_C : positive := 64; + constant LEN_W_C : positive := 32; + constant PKTLEN_W_C : positive := 13; + constant PKTNUM_W_C : positive := 25; + constant PMTU_W_C : positive := 3; + constant PAD_W_C : positive := 2; + constant ADDON_W_C : positive := 2; -- PktNumAddOn + constant BEBN_W_C : positive := 6; -- ByteEnBitNum + constant BYTEEN_W_C : positive := 32; + constant FRAGNUM_W_C : positive := 8; -- PktFragNum + constant DS_W_C : positive := 290; -- DataStream (OQ-FSM-H2DS-02) + constant SGL_W_C : positive := 1040; + constant QPN_W_C : positive := 24; + constant WRID_W_C : positive := 64; + constant DMA_BYTE_WIDTH_C : natural := 32; -- DATA_BUS_BYTE_WIDTH + + constant PAYLOAD_GEN_REQ_W_C : positive := 1228; + constant PAYLOAD_GEN_RESP_W_C : positive := 81; + constant TOTAL_META_W_C : positive := 27; + constant DMA_REQ_W_C : positive := 1163; + constant DMA_RESP_W_C : positive := 385; + + constant TMP_META_W_C : positive := 155; -- TmpPayloadGenMetaData + constant ADJ_REQ_Q_W_C : positive := PAYLOAD_GEN_REQ_W_C + TMP_META_W_C; -- 1383 + constant TMP_FL_W_C : positive := 247; -- TmpAdjustFirstAndLastPktLen + constant TMP_TOTAL_W_C : positive := 229; -- TmpAdjustTotalPayloadMetaData + constant ADJ_TOTAL_W_C : positive := 61; -- AdjustedTotalPayloadMetaData + constant TMP_RESP_W_C : positive := 214; -- TmpPayloadGenRespData + constant TMP_PAD_W_C : positive := 66; -- TmpPaddingData + constant ADD_PAD_Q_W_C : positive := PAYLOAD_GEN_RESP_W_C + TMP_PAD_W_C; -- 147 + + constant BUF_ADDR_WIDTH_C : positive := 8; -- DATA_STREAM_FRAG_BUF_SIZE = 256 + + -- PMTU enum encodings (PMTU deriving(Bits): IBV_MTU_256=1 .. IBV_MTU_4096=5) + constant IBV_MTU_256_C : slv(2 downto 0) := "001"; + constant IBV_MTU_512_C : slv(2 downto 0) := "010"; + constant IBV_MTU_1024_C : slv(2 downto 0) := "011"; + constant IBV_MTU_2048_C : slv(2 downto 0) := "100"; + constant IBV_MTU_4096_C : slv(2 downto 0) := "101"; + + ----------------------------------------------------------------------------- + -- Helper functions (Utils.bsv / PrimUtils.bsv) — verified against source + ----------------------------------------------------------------------------- + -- calcPmtuLen: PktLen (13b) size in bytes of one PMTU packet + function calcPmtuLen (pmtu : slv) return slv is + begin + case pmtu is + when IBV_MTU_256_C => return std_logic_vector(to_unsigned(256, PKTLEN_W_C)); + when IBV_MTU_512_C => return std_logic_vector(to_unsigned(512, PKTLEN_W_C)); + when IBV_MTU_1024_C => return std_logic_vector(to_unsigned(1024, PKTLEN_W_C)); + when IBV_MTU_2048_C => return std_logic_vector(to_unsigned(2048, PKTLEN_W_C)); + when IBV_MTU_4096_C => return std_logic_vector(to_unsigned(4096, PKTLEN_W_C)); + when others => return (PKTLEN_W_C-1 downto 0 => '0'); + end case; + end function calcPmtuLen; + + -- alignAddrByPMTU: clear the low log2(pmtu) address bits + function alignAddrByPMTU (addr : slv; pmtu : slv) return slv is + variable res : slv(ADDR_W_C-1 downto 0); + begin + res := addr(ADDR_W_C-1 downto 0); + case pmtu is + when IBV_MTU_256_C => res(7 downto 0) := (others => '0'); + when IBV_MTU_512_C => res(8 downto 0) := (others => '0'); + when IBV_MTU_1024_C => res(9 downto 0) := (others => '0'); + when IBV_MTU_2048_C => res(10 downto 0) := (others => '0'); + when IBV_MTU_4096_C => res(11 downto 0) := (others => '0'); + when others => null; + end case; + return res; + end function alignAddrByPMTU; + + -- addrAddPsnMultiplyPMTU with psn=1: { addr[63:k]+1, addr[k-1:0] } (adds one PMTU) + function addrAddOnePMTU (addr : slv; pmtu : slv) return slv is + variable a : slv(ADDR_W_C-1 downto 0); + variable res : slv(ADDR_W_C-1 downto 0); + begin + a := addr(ADDR_W_C-1 downto 0); + res := a; + case pmtu is + when IBV_MTU_256_C => res := slv(unsigned(a(63 downto 8)) + 1) & a(7 downto 0); + when IBV_MTU_512_C => res := slv(unsigned(a(63 downto 9)) + 1) & a(8 downto 0); + when IBV_MTU_1024_C => res := slv(unsigned(a(63 downto 10)) + 1) & a(9 downto 0); + when IBV_MTU_2048_C => res := slv(unsigned(a(63 downto 11)) + 1) & a(10 downto 0); + when IBV_MTU_4096_C => res := slv(unsigned(a(63 downto 12)) + 1) & a(11 downto 0); + when others => null; + end case; + return res; + end function addrAddOnePMTU; + + -- truncateByPMTU: ResiduePMTU (12b) = zeroExtend(bits[k-1:0]) + function truncateByPMTU (bits : slv; pmtu : slv) return slv is + variable res : slv(11 downto 0) := (others => '0'); + begin + res := (others => '0'); + case pmtu is + when IBV_MTU_256_C => res(7 downto 0) := bits(7 downto 0); + when IBV_MTU_512_C => res(8 downto 0) := bits(8 downto 0); + when IBV_MTU_1024_C => res(9 downto 0) := bits(9 downto 0); + when IBV_MTU_2048_C => res(10 downto 0) := bits(10 downto 0); + when IBV_MTU_4096_C => res(11 downto 0) := bits(11 downto 0); + when others => null; + end case; + return res; + end function truncateByPMTU; + + -- stepOne pieces (per-PMTU slices of raddr/totalLen) ----------------------- + -- pmtuMask: PktLen (13b) with low k bits set + function pmtuMaskF (pmtu : slv) return slv is + variable res : slv(PKTLEN_W_C-1 downto 0) := (others => '0'); + begin + res := (others => '0'); + case pmtu is + when IBV_MTU_256_C => res(7 downto 0) := (others => '1'); + when IBV_MTU_512_C => res(8 downto 0) := (others => '1'); + when IBV_MTU_1024_C => res(9 downto 0) := (others => '1'); + when IBV_MTU_2048_C => res(10 downto 0) := (others => '1'); + when IBV_MTU_4096_C => res(11 downto 0) := (others => '1'); + when others => null; + end case; + return res; + end function pmtuMaskF; + + -- addrLowPart: PktLen (13b) zeroExtend of addr[k-1:0] + function addrLowPartF (addr : slv; pmtu : slv) return slv is + variable res : slv(PKTLEN_W_C-1 downto 0) := (others => '0'); + begin + res := (others => '0'); + case pmtu is + when IBV_MTU_256_C => res(7 downto 0) := addr(7 downto 0); + when IBV_MTU_512_C => res(8 downto 0) := addr(8 downto 0); + when IBV_MTU_1024_C => res(9 downto 0) := addr(9 downto 0); + when IBV_MTU_2048_C => res(10 downto 0) := addr(10 downto 0); + when IBV_MTU_4096_C => res(11 downto 0) := addr(11 downto 0); + when others => null; + end case; + return res; + end function addrLowPartF; + + -- lenLowPart: PktLen (13b) zeroExtend of len[k-1:0] + function lenLowPartF (len : slv; pmtu : slv) return slv is + variable res : slv(PKTLEN_W_C-1 downto 0) := (others => '0'); + begin + res := (others => '0'); + case pmtu is + when IBV_MTU_256_C => res(7 downto 0) := len(7 downto 0); + when IBV_MTU_512_C => res(8 downto 0) := len(8 downto 0); + when IBV_MTU_1024_C => res(9 downto 0) := len(9 downto 0); + when IBV_MTU_2048_C => res(10 downto 0) := len(10 downto 0); + when IBV_MTU_4096_C => res(11 downto 0) := len(11 downto 0); + when others => null; + end case; + return res; + end function lenLowPartF; + + -- truncatedPktNum: PktNum (25b) zeroExtend of len[31:k] (truncateLSB) + function truncatedPktNumF (len : slv; pmtu : slv) return slv is + variable res : slv(PKTNUM_W_C-1 downto 0) := (others => '0'); + begin + res := (others => '0'); + case pmtu is + when IBV_MTU_256_C => res(23 downto 0) := len(31 downto 8); + when IBV_MTU_512_C => res(22 downto 0) := len(31 downto 9); + when IBV_MTU_1024_C => res(21 downto 0) := len(31 downto 10); + when IBV_MTU_2048_C => res(20 downto 0) := len(31 downto 11); + when IBV_MTU_4096_C => res(19 downto 0) := len(31 downto 12); + when others => null; + end case; + return res; + end function truncatedPktNumF; + + -- calcLastFragValidByteNum: ByteEnBitNum (6b); len[4:0], or 32 if [4:0]=0 and [.:5]/=0 + function calcLastFragValidByteNum (len : slv) return slv is + variable residue : slv(4 downto 0); + variable truncatedLen : slv(len'length-1 downto 5); + variable res : slv(BEBN_W_C-1 downto 0); + begin + residue := len(4 downto 0); + truncatedLen := len(len'length-1 downto 5); + res := '0' & residue; -- zeroExtend(residue) to 6b + if (unsigned(residue) = 0) and (unsigned(truncatedLen) /= 0) then + res := std_logic_vector(to_unsigned(DMA_BYTE_WIDTH_C, BEBN_W_C)); -- 32 + end if; + return res; + end function calcLastFragValidByteNum; + + -- calcFragNumByPktLen: PktFragNum (8b) = pktLen[12:5] + (pktLen[4:0]/=0 ? 1 : 0) + function calcFragNumByPktLen (pktLen : slv) return slv is + variable residue : slv(4 downto 0); + variable truncatedLen : slv(FRAGNUM_W_C-1 downto 0); + variable res : unsigned(FRAGNUM_W_C-1 downto 0); + begin + residue := pktLen(4 downto 0); + truncatedLen := pktLen(12 downto 5); + res := unsigned(truncatedLen); + if (unsigned(residue) /= 0) then + res := res + 1; + end if; + return std_logic_vector(res); + end function calcFragNumByPktLen; + + -- calcPadCnt: PAD (2b) = (1<=32 -> all ones + function genByteEn (n : slv) return slv is + variable mask : slv(BYTEEN_W_C-1 downto 0) := (others => '0'); + variable cnt : integer; + begin + cnt := to_integer(unsigned(n)); + for i in mask'range loop + if (i < cnt) then + mask(i) := '1'; + end if; + end loop; + return bitReverse(mask); + end function genByteEn; + + ----------------------------------------------------------------------------- + -- Register record (iterator state only — genPayloadGenResp) + ----------------------------------------------------------------------------- + type RegType is record + isFirstPktReg : sl; -- mkReg(True); reset '1' + pktRemoteAddrReg : slv(ADDR_W_C-1 downto 0); -- mkRegU (no reset) + remainingPktNumReg : slv(PKTNUM_W_C-1 downto 0); -- mkRegU (no reset) + end record RegType; + + constant REG_INIT_C : RegType := ( + isFirstPktReg => '1', + pktRemoteAddrReg => (others => '0'), -- mkRegU; placeholder, not reset + remainingPktNumReg => (others => '0')); -- mkRegU; placeholder, not reset + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Shared FIFO clear (rst OR software clear) + signal fifoRst : sl; + + -- U_PayloadGenReqQ (PayloadGenReqSG, 1228b) + signal payloadGenReqQNotFull : sl; + signal payloadGenReqQValid : sl; + signal payloadGenReqQDout : slv(PAYLOAD_GEN_REQ_W_C-1 downto 0); + signal payloadGenReqQRdEn : sl; + + -- U_AdjustReqPktLenQ (Tuple2(PayloadGenReqSG,TmpPayloadGenMetaData), 1383b) + signal adjustReqPktLenQNotFull : sl; + signal adjustReqPktLenQValid : sl; + signal adjustReqPktLenQDout : slv(ADJ_REQ_Q_W_C-1 downto 0); + signal adjustReqPktLenQWrEn : sl; + signal adjustReqPktLenQRdEn : sl; + signal adjustReqPktLenQDin : slv(ADJ_REQ_Q_W_C-1 downto 0); + + -- U_AdjustFirstAndLastPktLenQ (TmpAdjustFirstAndLastPktLen, 247b) + signal adjustFirstLastQNotFull : sl; + signal adjustFirstLastQValid : sl; + signal adjustFirstLastQDout : slv(TMP_FL_W_C-1 downto 0); + signal adjustFirstLastQWrEn : sl; + signal adjustFirstLastQRdEn : sl; + signal adjustFirstLastQDin : slv(TMP_FL_W_C-1 downto 0); + + -- U_AdjustTotalPayloadMetaDataQ (TmpAdjustTotalPayloadMetaData, 229b) + signal adjustTotalQNotFull : sl; + signal adjustTotalQValid : sl; + signal adjustTotalQDout : slv(TMP_TOTAL_W_C-1 downto 0); + signal adjustTotalQWrEn : sl; + signal adjustTotalQRdEn : sl; + signal adjustTotalQDin : slv(TMP_TOTAL_W_C-1 downto 0); + + -- U_AdjustedTotalPayloadMetaDataQ (AdjustedTotalPayloadMetaData, 61b) — read by child + signal adjustedTotalQNotFull : sl; + signal adjustedTotalQValid : sl; + signal adjustedTotalQDout : slv(ADJ_TOTAL_W_C-1 downto 0); + signal adjustedTotalQWrEn : sl; + signal adjustedTotalQRdEn : sl; + signal adjustedTotalQDin : slv(ADJ_TOTAL_W_C-1 downto 0); + + -- U_GenPayloadRespQ (TmpPayloadGenRespData, 214b) + signal genPayloadRespQNotFull : sl; + signal genPayloadRespQValid : sl; + signal genPayloadRespQDout : slv(TMP_RESP_W_C-1 downto 0); + signal genPayloadRespQWrEn : sl; + signal genPayloadRespQRdEn : sl; + signal genPayloadRespQDin : slv(TMP_RESP_W_C-1 downto 0); + + -- U_TotalMetaDataOutQ (PayloadGenTotalMetaData, 27b) — read by external pipe + signal totalMetaDataOutQNotFull : sl; + signal totalMetaDataOutQValid : sl; + signal totalMetaDataOutQDout : slv(TOTAL_META_W_C-1 downto 0); + signal totalMetaDataOutQWrEn : sl; + signal totalMetaDataOutQDin : slv(TOTAL_META_W_C-1 downto 0); + + -- U_AddPaddingDataQ (Tuple2(PayloadGenRespSG,TmpPaddingData), 147b) + signal addPaddingDataQNotFull : sl; + signal addPaddingDataQValid : sl; + signal addPaddingDataQDout : slv(ADD_PAD_Q_W_C-1 downto 0); + signal addPaddingDataQWrEn : sl; + signal addPaddingDataQRdEn : sl; + signal addPaddingDataQDin : slv(ADD_PAD_Q_W_C-1 downto 0); + + -- U_PayloadGenRespQ (PayloadGenRespSG, 81b) — read by external srvPort.response + signal payloadGenRespQNotFull : sl; + signal payloadGenRespQValid : sl; + signal payloadGenRespQDout : slv(PAYLOAD_GEN_RESP_W_C-1 downto 0); + signal payloadGenRespQWrEn : sl; + signal payloadGenRespQDin : slv(PAYLOAD_GEN_RESP_W_C-1 downto 0); + + -- U_SgePayloadOutQ (DataStream, 290b) — read by child U_SgeMergedPayload + signal sgePayloadOutQNotFull : sl; + signal sgePayloadOutQValid : sl; + signal sgePayloadOutQDout : slv(DS_W_C-1 downto 0); + signal sgePayloadOutQWrEn : sl; + signal sgePayloadOutQRdEn : sl; + signal sgePayloadOutQDin : slv(DS_W_C-1 downto 0); + + -- U_PayloadBufQ (DataStream, 290b, BRAM depth 256) — read by child U_BramQ2PipeOut + signal payloadBufQNotFull : sl; + signal payloadBufQValid : sl; + signal payloadBufQDout : slv(DS_W_C-1 downto 0); + signal payloadBufQWrEn : sl; + signal payloadBufQRdEn : sl; + signal payloadBufQDin : slv(DS_W_C-1 downto 0); + + -- Internal child-to-child PipeOut(DataStream) links + signal sgeMergedPayloadValid : sl; + signal sgeMergedPayloadData : slv(DS_W_C-1 downto 0); + signal sgeMergedPayloadRdEn : sl; + + signal sglMergedPayloadValid : sl; + signal sglMergedPayloadData : slv(DS_W_C-1 downto 0); + signal sglMergedPayloadRdEn : sl; + + signal adjustedPayloadValid : sl; + signal adjustedPayloadData : slv(DS_W_C-1 downto 0); + signal adjustedPayloadRdEn : sl; + +begin + + ----------------------------------------------------------------------------- + -- Static wiring + ----------------------------------------------------------------------------- + fifoRst <= rst or clearAllI; -- shared FIFO soft clear + + -- srvPort handshake passthroughs (BSV toGPServer implicit conditions) + reqInReady <= payloadGenReqQNotFull; + respOutValid <= payloadGenRespQValid; + respOutData <= payloadGenRespQDout; + + -- totalMetaDataPipeOut passthrough (toPipeOut(totalMetaDataOutQ)) + totalMetaDataNotEmpty <= totalMetaDataOutQValid; + totalMetaDataFirst <= totalMetaDataOutQDout; + + ----------------------------------------------------------------------------- + -- Combinatorial FSM: 7 conflict_free workers + iterator + reset + ----------------------------------------------------------------------------- + comb : process (r, rst, clearAllI, + payloadGenReqQValid, payloadGenReqQDout, adjustReqPktLenQNotFull, + dmaReadCntrlRespValid, dmaReadCntrlRespData, sgePayloadOutQNotFull, + adjustReqPktLenQValid, adjustReqPktLenQDout, adjustFirstLastQNotFull, + dmaReadCntrlReqReady, + adjustFirstLastQValid, adjustFirstLastQDout, adjustTotalQNotFull, + adjustTotalQValid, adjustTotalQDout, adjustedTotalQNotFull, + genPayloadRespQNotFull, totalMetaDataOutQNotFull, + genPayloadRespQValid, genPayloadRespQDout, addPaddingDataQNotFull, + addPaddingDataQValid, addPaddingDataQDout, + adjustedPayloadValid, adjustedPayloadData, payloadBufQNotFull, + payloadGenRespQNotFull) is + variable v : RegType; + + -- recvReq temporaries + variable reqRaddr : slv(ADDR_W_C-1 downto 0); + variable reqTotalLen : slv(LEN_W_C-1 downto 0); + variable reqPmtu : slv(PMTU_W_C-1 downto 0); + variable reqZeroLen : sl; + variable soAlignAddr : slv(ADDR_W_C-1 downto 0); + variable soPmtuLen : slv(PKTLEN_W_C-1 downto 0); + variable soAddrLow : slv(PKTLEN_W_C-1 downto 0); + variable soLenLow : slv(PKTLEN_W_C-1 downto 0); + variable soPmtuMask : slv(PKTLEN_W_C-1 downto 0); + variable soTruncPktNum : slv(PKTNUM_W_C-1 downto 0); + variable soMaxFirst : slv(PKTLEN_W_C-1 downto 0); + variable soAddrLenSum : slv(PKTLEN_W_C-1 downto 0); + variable metaVec : slv(TMP_META_W_C-1 downto 0); + + -- issueDmaReadCntrlReq temporaries + variable reqV : slv(PAYLOAD_GEN_REQ_W_C-1 downto 0); + variable metaV : slv(TMP_META_W_C-1 downto 0); + variable stPmtuMask : slv(PKTLEN_W_C-1 downto 0); + variable stAddrLenSum : slv(PKTLEN_W_C-1 downto 0); + variable stPmtuLen : slv(PKTLEN_W_C-1 downto 0); + variable stLenLow : slv(PKTLEN_W_C-1 downto 0); + variable stMaxFirst : slv(PKTLEN_W_C-1 downto 0); + variable stTruncPktNum : slv(PKTNUM_W_C-1 downto 0); + variable stAlignAddr : slv(ADDR_W_C-1 downto 0); + variable stZeroLen : sl; + variable stRaddr : slv(ADDR_W_C-1 downto 0); + variable stPmtu : slv(PMTU_W_C-1 downto 0); + variable stAddPadding : sl; + variable secondAddr : slv(ADDR_W_C-1 downto 0); + variable tmpLastPktLen : slv(PKTLEN_W_C-1 downto 0); + variable pmtuInvMask : slv(PKTLEN_W_C-1 downto 0); + variable hasResidue : sl; + variable hasExtraPkt : sl; + variable notFullPkt : sl; + variable pktNumAddOne : slv(ADDON_W_C-1 downto 0); + variable resBit : slv(ADDON_W_C-1 downto 0); + variable extBit : slv(ADDON_W_C-1 downto 0); + + -- adjustFirstAndLastPktLen temporaries + variable aOrigAddr : slv(ADDR_W_C-1 downto 0); + variable aSecondAddr : slv(ADDR_W_C-1 downto 0); + variable aTotalLen : slv(LEN_W_C-1 downto 0); + variable aTruncPktNum : slv(PKTNUM_W_C-1 downto 0); + variable aPktNumAddOne : slv(ADDON_W_C-1 downto 0); + variable aLenLow : slv(PKTLEN_W_C-1 downto 0); + variable aMaxFirst : slv(PKTLEN_W_C-1 downto 0); + variable aTmpLast : slv(PKTLEN_W_C-1 downto 0); + variable aPmtuLen : slv(PKTLEN_W_C-1 downto 0); + variable aPmtu : slv(PMTU_W_C-1 downto 0); + variable aNotFullPkt : sl; + variable aHasExtraPkt : sl; + variable aHasResidue : sl; + variable aZeroLen : sl; + variable aAddPadding : sl; + variable aTotalPktNum : slv(PKTNUM_W_C-1 downto 0); + variable aFirstPktLen : slv(PKTLEN_W_C-1 downto 0); + variable aLastPktLen : slv(PKTLEN_W_C-1 downto 0); + + -- calcAdjustedTotalPayloadMetaData temporaries + variable cFirstAddr : slv(ADDR_W_C-1 downto 0); + variable cSecondAddr : slv(ADDR_W_C-1 downto 0); + variable cTotalLen : slv(LEN_W_C-1 downto 0); + variable cTotalPktNum : slv(PKTNUM_W_C-1 downto 0); + variable cFirstPktLen : slv(PKTLEN_W_C-1 downto 0); + variable cLastPktLen : slv(PKTLEN_W_C-1 downto 0); + variable cPmtuLen : slv(PKTLEN_W_C-1 downto 0); + variable cPmtu : slv(PMTU_W_C-1 downto 0); + variable cZeroLen : sl; + variable cAddPadding : sl; + variable cOrigLastVBN : slv(BEBN_W_C-1 downto 0); + variable cFirstLastVBN : slv(BEBN_W_C-1 downto 0); + variable cLastLastVBN : slv(BEBN_W_C-1 downto 0); + variable cFirstFragNum : slv(FRAGNUM_W_C-1 downto 0); + variable cFirstPad : slv(PAD_W_C-1 downto 0); + variable cLastPad : slv(PAD_W_C-1 downto 0); + variable cIsOnlyPkt : sl; + variable cFirstLastVBNwp : slv(BEBN_W_C-1 downto 0); + variable cLastLastVBNwp : slv(BEBN_W_C-1 downto 0); + + -- genPayloadGenResp temporaries + variable gFirstAddr : slv(ADDR_W_C-1 downto 0); + variable gSecondAddr : slv(ADDR_W_C-1 downto 0); + variable gFirstPktLen : slv(PKTLEN_W_C-1 downto 0); + variable gLastPktLen : slv(PKTLEN_W_C-1 downto 0); + variable gPmtuLen : slv(PKTLEN_W_C-1 downto 0); + variable gFirstLastVBNwp : slv(BEBN_W_C-1 downto 0); + variable gLastLastVBNwp : slv(BEBN_W_C-1 downto 0); + variable gFirstPad : slv(PAD_W_C-1 downto 0); + variable gLastPad : slv(PAD_W_C-1 downto 0); + variable gTotalPktNum : slv(PKTNUM_W_C-1 downto 0); + variable gPmtu : slv(PMTU_W_C-1 downto 0); + variable gIsOnlyPkt : sl; + variable gZeroLen : sl; + variable gAddPadding : sl; + variable gRemoteAddr : slv(ADDR_W_C-1 downto 0); + variable gNextAddr : slv(ADDR_W_C-1 downto 0); + variable gRemainPktNum : slv(PKTNUM_W_C-1 downto 0); + variable gIsFirstPkt : sl; + variable gIsLastPkt : sl; + variable gPktLen : slv(PKTLEN_W_C-1 downto 0); + variable gPadCnt : slv(PAD_W_C-1 downto 0); + variable gFirstByteEn : slv(BYTEEN_W_C-1 downto 0); + variable gLastByteEn : slv(BYTEEN_W_C-1 downto 0); + variable gResp : slv(PAYLOAD_GEN_RESP_W_C-1 downto 0); + variable gPad : slv(TMP_PAD_W_C-1 downto 0); + + -- outputAndAddPadding temporaries + variable oResp : slv(PAYLOAD_GEN_RESP_W_C-1 downto 0); + variable oPad : slv(TMP_PAD_W_C-1 downto 0); + variable oRespIsFirst : sl; + variable oRespIsLast : sl; + variable oZeroLen : sl; + variable oAddPadding : sl; + variable oFirstByteEn : slv(BYTEEN_W_C-1 downto 0); + variable oLastByteEn : slv(BYTEEN_W_C-1 downto 0); + variable oFrag : slv(DS_W_C-1 downto 0); + variable oFragIsLast : sl; + variable oByteEn : slv(BYTEEN_W_C-1 downto 0); + begin + v := r; + + -- Default Mealy drives (all deasserted) + payloadGenReqQRdEn <= '0'; + adjustReqPktLenQWrEn <= '0'; + adjustReqPktLenQDin <= (others => '0'); + adjustReqPktLenQRdEn <= '0'; + dmaReadCntrlRespReady <= '0'; + sgePayloadOutQWrEn <= '0'; + sgePayloadOutQDin <= (others => '0'); + dmaReadCntrlReqValid <= '0'; + dmaReadCntrlReqData <= (others => '0'); + adjustFirstLastQWrEn <= '0'; + adjustFirstLastQDin <= (others => '0'); + adjustFirstLastQRdEn <= '0'; + adjustTotalQWrEn <= '0'; + adjustTotalQDin <= (others => '0'); + adjustTotalQRdEn <= '0'; + adjustedTotalQWrEn <= '0'; + adjustedTotalQDin <= (others => '0'); + genPayloadRespQWrEn <= '0'; + genPayloadRespQDin <= (others => '0'); + genPayloadRespQRdEn <= '0'; + totalMetaDataOutQWrEn <= '0'; + totalMetaDataOutQDin <= (others => '0'); + addPaddingDataQWrEn <= '0'; + addPaddingDataQDin <= (others => '0'); + addPaddingDataQRdEn <= '0'; + payloadGenRespQWrEn <= '0'; + payloadGenRespQDin <= (others => '0'); + payloadBufQWrEn <= '0'; + payloadBufQDin <= (others => '0'); + adjustedPayloadRdEn <= '0'; + + ------------------------------------------------------------------------- + -- recvReq (stepOne): split PayloadGenReqSG head, enq adjustReqPktLenQ + ------------------------------------------------------------------------- + reqRaddr := payloadGenReqQDout(67 downto 4); + reqTotalLen := payloadGenReqQDout(99 downto 68); + reqPmtu := payloadGenReqQDout(3 downto 1); + if (unsigned(reqTotalLen) = 0) then reqZeroLen := '1'; else reqZeroLen := '0'; end if; + + soAlignAddr := alignAddrByPMTU(reqRaddr, reqPmtu); + soPmtuLen := calcPmtuLen(reqPmtu); + soAddrLow := addrLowPartF(reqRaddr, reqPmtu); + soLenLow := lenLowPartF(reqTotalLen, reqPmtu); + soPmtuMask := pmtuMaskF(reqPmtu); + soTruncPktNum := truncatedPktNumF(reqTotalLen, reqPmtu); + soMaxFirst := slv(unsigned(soPmtuLen) - unsigned(soAddrLow)); + soAddrLenSum := slv(unsigned(soAddrLow) + unsigned(soLenLow)); + + -- TmpPayloadGenMetaData (155b): pmtuMask, addrAndLenLowPartSum, pmtuLen, + -- lenLowPart, maxFirstPktLen, truncatedPktNum, pmtuAlignedStartAddr, isZeroPayloadLen + metaVec := soPmtuMask & soAddrLenSum & soPmtuLen & soLenLow & soMaxFirst & + soTruncPktNum & soAlignAddr & reqZeroLen; + + if (clearAllI = '0') and (payloadGenReqQValid = '1') and (adjustReqPktLenQNotFull = '1') then + payloadGenReqQRdEn <= '1'; + adjustReqPktLenQWrEn <= '1'; + adjustReqPktLenQDin <= payloadGenReqQDout & metaVec; -- Tuple2 (req at MSB) + end if; + + ------------------------------------------------------------------------- + -- recvDmaReadCntrlResp: get DmaReadCntrlResp, enq its DataStream to sgePayloadOutQ + ------------------------------------------------------------------------- + if (clearAllI = '0') and (dmaReadCntrlRespValid = '1') and (sgePayloadOutQNotFull = '1') then + dmaReadCntrlRespReady <= '1'; + sgePayloadOutQWrEn <= '1'; + sgePayloadOutQDin <= dmaReadCntrlRespData(291 downto 2); -- dmaReadResp.dataStream + end if; + + ------------------------------------------------------------------------- + -- issueDmaReadCntrlReq (stepTwo): optional DMA request + enq adjustFirstAndLastPktLenQ + ------------------------------------------------------------------------- + reqV := adjustReqPktLenQDout(ADJ_REQ_Q_W_C-1 downto TMP_META_W_C); -- PayloadGenReqSG (1228) + metaV := adjustReqPktLenQDout(TMP_META_W_C-1 downto 0); -- TmpPayloadGenMetaData (155) + + stPmtuMask := metaV(154 downto 142); + stAddrLenSum := metaV(141 downto 129); + stPmtuLen := metaV(128 downto 116); + stLenLow := metaV(115 downto 103); + stMaxFirst := metaV(102 downto 90); + stTruncPktNum := metaV(89 downto 65); + stAlignAddr := metaV(64 downto 1); + stZeroLen := metaV(0); + stRaddr := reqV(67 downto 4); + stPmtu := reqV(3 downto 1); + stAddPadding := reqV(0); + + secondAddr := addrAddOnePMTU(stAlignAddr, stPmtu); + tmpLastPktLen := '0' & truncateByPMTU(stAddrLenSum, stPmtu); -- zeroExtend 12b->13b + pmtuInvMask := not stPmtuMask; + if (unsigned(stPmtuMask and stAddrLenSum) = 0) then hasResidue := '0'; else hasResidue := '1'; end if; + if (unsigned(pmtuInvMask and stAddrLenSum) = 0) then hasExtraPkt := '0'; else hasExtraPkt := '1'; end if; + if (unsigned(stTruncPktNum) = 0) then notFullPkt := '1'; else notFullPkt := '0'; end if; + resBit := '0' & hasResidue; + extBit := '0' & hasExtraPkt; + pktNumAddOne := slv(unsigned(resBit) + unsigned(extBit)); + + -- TmpAdjustFirstAndLastPktLen (247b): origRemoteAddr, secondChunkStartAddr, + -- totalLen, truncatedPktNum, pktNumAddOne, lenLowPart, maxFirstPktLen, + -- tmpLastPktLen, pmtuLen, pmtu, notFullPkt, hasExtraPkt, hasResidue, + -- isZeroPayloadLen, shouldAddPadding + adjustFirstLastQDin <= stRaddr & secondAddr & reqV(99 downto 68) & stTruncPktNum & + pktNumAddOne & stLenLow & stMaxFirst & tmpLastPktLen & stPmtuLen & + stPmtu & notFullPkt & hasExtraPkt & hasResidue & stZeroLen & stAddPadding; + + if (clearAllI = '0') and (adjustReqPktLenQValid = '1') and (adjustFirstLastQNotFull = '1') + and ((stZeroLen = '1') or (dmaReadCntrlReqReady = '1')) then + adjustReqPktLenQRdEn <= '1'; + adjustFirstLastQWrEn <= '1'; + if (stZeroLen = '0') then + dmaReadCntrlReqValid <= '1'; + -- DmaReadCntrlReq (1163b): sgl, totalLen, sqpn, wrID, pmtu + dmaReadCntrlReqData <= reqV(1139 downto 100) & -- sgl (1040) + reqV(99 downto 68) & -- totalLen (32) + reqV(1163 downto 1140) & -- sqpn (24) + reqV(1227 downto 1164) & -- wrID (64) + reqV(3 downto 1); -- pmtu (3) + end if; + end if; + + ------------------------------------------------------------------------- + -- adjustFirstAndLastPktLen (stepThree): enq adjustTotalPayloadMetaDataQ + ------------------------------------------------------------------------- + aOrigAddr := adjustFirstLastQDout(246 downto 183); + aSecondAddr := adjustFirstLastQDout(182 downto 119); + aTotalLen := adjustFirstLastQDout(118 downto 87); + aTruncPktNum := adjustFirstLastQDout(86 downto 62); + aPktNumAddOne := adjustFirstLastQDout(61 downto 60); + aLenLow := adjustFirstLastQDout(59 downto 47); + aMaxFirst := adjustFirstLastQDout(46 downto 34); + aTmpLast := adjustFirstLastQDout(33 downto 21); + aPmtuLen := adjustFirstLastQDout(20 downto 8); + aPmtu := adjustFirstLastQDout(7 downto 5); + aNotFullPkt := adjustFirstLastQDout(4); + aHasExtraPkt := adjustFirstLastQDout(3); + aHasResidue := adjustFirstLastQDout(2); + aZeroLen := adjustFirstLastQDout(1); + aAddPadding := adjustFirstLastQDout(0); + + aTotalPktNum := slv(unsigned(aTruncPktNum) + resize(unsigned(aPktNumAddOne), PKTNUM_W_C)); + if (aNotFullPkt = '1') and (aHasExtraPkt = '0') then + aFirstPktLen := aLenLow; + else + aFirstPktLen := aMaxFirst; + end if; + if (aHasResidue = '1') then + aLastPktLen := aTmpLast; + elsif (aNotFullPkt = '1') then + aLastPktLen := aLenLow; + else + aLastPktLen := aPmtuLen; + end if; + + -- TmpAdjustTotalPayloadMetaData (229b): firstRemoteAddr, secondRemoteAddr, + -- totalLen, totalPktNum, firstPktLen, lastPktLen, pmtuLen, pmtu, + -- isZeroPayloadLen, shouldAddPadding + adjustTotalQDin <= aOrigAddr & aSecondAddr & aTotalLen & aTotalPktNum & + aFirstPktLen & aLastPktLen & aPmtuLen & aPmtu & aZeroLen & aAddPadding; + + if (clearAllI = '0') and (adjustFirstLastQValid = '1') and (adjustTotalQNotFull = '1') then + adjustFirstLastQRdEn <= '1'; + adjustTotalQWrEn <= '1'; + end if; + + ------------------------------------------------------------------------- + -- calcAdjustedTotalPayloadMetaData: enq adjustedTotalQ (opt), genPayloadRespQ, totalMetaDataOutQ + ------------------------------------------------------------------------- + cFirstAddr := adjustTotalQDout(228 downto 165); + cSecondAddr := adjustTotalQDout(164 downto 101); + cTotalLen := adjustTotalQDout(100 downto 69); + cTotalPktNum := adjustTotalQDout(68 downto 44); + cFirstPktLen := adjustTotalQDout(43 downto 31); + cLastPktLen := adjustTotalQDout(30 downto 18); + cPmtuLen := adjustTotalQDout(17 downto 5); + cPmtu := adjustTotalQDout(4 downto 2); + cZeroLen := adjustTotalQDout(1); + cAddPadding := adjustTotalQDout(0); + + cOrigLastVBN := calcLastFragValidByteNum(cTotalLen); + cFirstLastVBN := calcLastFragValidByteNum(cFirstPktLen); + cLastLastVBN := calcLastFragValidByteNum(cLastPktLen); + cFirstFragNum := calcFragNumByPktLen(cFirstPktLen); + cFirstPad := calcPadCnt(cFirstPktLen); + cLastPad := calcPadCnt(cLastPktLen); + if (unsigned(cTotalPktNum(PKTNUM_W_C-1 downto 1)) = 0) then cIsOnlyPkt := '1'; else cIsOnlyPkt := '0'; end if; + cFirstLastVBNwp := slv(unsigned(cFirstLastVBN) + resize(unsigned(cFirstPad), BEBN_W_C)); + cLastLastVBNwp := slv(unsigned(cLastLastVBN) + resize(unsigned(cLastPad), BEBN_W_C)); + + -- AdjustedTotalPayloadMetaData (61b): firstPktLen, firstPktFragNum, + -- firstPktLastFragValidByteNum, origLastFragValidByteNum, adjustedPktNum, pmtu + adjustedTotalQDin <= cFirstPktLen & cFirstFragNum & cFirstLastVBN & + cOrigLastVBN & cTotalPktNum & cPmtu; + + -- TmpPayloadGenRespData (214b): firstRemoteAddr, secondRemoteAddr, firstPktLen, + -- lastPktLen, pmtuLen, firstPktLastFragValidByteNumWithPadding, + -- lastPktLastFragValidByteNumWithPadding, firstPktPadCnt, lastPktPadCnt, + -- totalPktNum, pmtu, isOnlyPkt, isZeroPayloadLen, shouldAddPadding + genPayloadRespQDin <= cFirstAddr & cSecondAddr & cFirstPktLen & cLastPktLen & cPmtuLen & + cFirstLastVBNwp & cLastLastVBNwp & cFirstPad & cLastPad & + cTotalPktNum & cPmtu & cIsOnlyPkt & cZeroLen & cAddPadding; + + -- PayloadGenTotalMetaData (27b): totalPktNum, isOnlyPkt, isZeroPayloadLen + totalMetaDataOutQDin <= cTotalPktNum & cIsOnlyPkt & cZeroLen; + + if (clearAllI = '0') and (adjustTotalQValid = '1') and (genPayloadRespQNotFull = '1') + and (totalMetaDataOutQNotFull = '1') + and ((cZeroLen = '1') or (adjustedTotalQNotFull = '1')) then + adjustTotalQRdEn <= '1'; + genPayloadRespQWrEn <= '1'; + totalMetaDataOutQWrEn <= '1'; + if (cZeroLen = '0') then + adjustedTotalQWrEn <= '1'; + end if; + end if; + + ------------------------------------------------------------------------- + -- genPayloadGenResp (iterator): 2-phase Mealy on isFirstPktReg + ------------------------------------------------------------------------- + gFirstAddr := genPayloadRespQDout(213 downto 150); + gSecondAddr := genPayloadRespQDout(149 downto 86); + gFirstPktLen := genPayloadRespQDout(85 downto 73); + gLastPktLen := genPayloadRespQDout(72 downto 60); + gPmtuLen := genPayloadRespQDout(59 downto 47); + gFirstLastVBNwp := genPayloadRespQDout(46 downto 41); + gLastLastVBNwp := genPayloadRespQDout(40 downto 35); + gFirstPad := genPayloadRespQDout(34 downto 33); + gLastPad := genPayloadRespQDout(32 downto 31); + gTotalPktNum := genPayloadRespQDout(30 downto 6); + gPmtu := genPayloadRespQDout(5 downto 3); + gIsOnlyPkt := genPayloadRespQDout(2); + gZeroLen := genPayloadRespQDout(1); + gAddPadding := genPayloadRespQDout(0); + + if (r.isFirstPktReg = '1') then + gRemoteAddr := gFirstAddr; + gNextAddr := gSecondAddr; + if (gIsOnlyPkt = '1') then + gRemainPktNum := std_logic_vector(to_unsigned(1, PKTNUM_W_C)); + else + gRemainPktNum := slv(unsigned(gTotalPktNum) - 1); + end if; + else + gRemoteAddr := r.pktRemoteAddrReg; + gNextAddr := addrAddOnePMTU(r.pktRemoteAddrReg, gPmtu); + gRemainPktNum := slv(unsigned(r.remainingPktNumReg) - 1); + end if; + + gIsFirstPkt := r.isFirstPktReg; + -- isLastPkt = isOnlyPkt or (!isFirstPktReg and isOne(remainingPktNumReg)) + gIsLastPkt := '0'; + if (gIsOnlyPkt = '1') then + gIsLastPkt := '1'; + elsif (r.isFirstPktReg = '0') and (unsigned(r.remainingPktNumReg(PKTNUM_W_C-1 downto 1)) = 0) + and (r.remainingPktNumReg(0) = '1') then + gIsLastPkt := '1'; + end if; + + if (gIsFirstPkt = '1') then + gPktLen := gFirstPktLen; + gPadCnt := gFirstPad; + elsif (gIsLastPkt = '1') then + gPktLen := gLastPktLen; + gPadCnt := gLastPad; + else + gPktLen := gPmtuLen; + gPadCnt := (others => '0'); + end if; + + gFirstByteEn := genByteEn(gFirstLastVBNwp); + gLastByteEn := genByteEn(gLastLastVBNwp); + + -- PayloadGenRespSG (81b): raddr, pktLen, padCnt, isFirst, isLast + gResp := gRemoteAddr & gPktLen & gPadCnt & gIsFirstPkt & gIsLastPkt; + -- TmpPaddingData (66b): firstPktLastFragByteEnWithPadding, + -- lastPktLastFragByteEnWithPadding, isZeroPayloadLen, shouldAddPadding + gPad := gFirstByteEn & gLastByteEn & gZeroLen & gAddPadding; + + -- Tuple2(PayloadGenRespSG, TmpPaddingData) (147b, resp at MSB) + addPaddingDataQDin <= gResp & gPad; + + if (clearAllI = '0') and (genPayloadRespQValid = '1') and (addPaddingDataQNotFull = '1') then + addPaddingDataQWrEn <= '1'; + v.isFirstPktReg := gIsLastPkt; + v.pktRemoteAddrReg := gNextAddr; + v.remainingPktNumReg := gRemainPktNum; + if (gIsLastPkt = '1') then + genPayloadRespQRdEn <= '1'; + end if; + end if; + + ------------------------------------------------------------------------- + -- outputAndAddPadding: zero-payload / data(non-last frag) / data(last frag) + ------------------------------------------------------------------------- + oResp := addPaddingDataQDout(ADD_PAD_Q_W_C-1 downto TMP_PAD_W_C); -- PayloadGenRespSG (81) + oPad := addPaddingDataQDout(TMP_PAD_W_C-1 downto 0); -- TmpPaddingData (66) + oRespIsFirst := oResp(1); + oRespIsLast := oResp(0); + oFirstByteEn := oPad(65 downto 34); + oLastByteEn := oPad(33 downto 2); + oZeroLen := oPad(1); + oAddPadding := oPad(0); + + oFrag := adjustedPayloadData; + oFragIsLast := adjustedPayloadData(0); -- DataStream.isLast + + -- last-fragment byteEn override (only when shouldAddPadding on the orig last frag) + oByteEn := oFrag(33 downto 2); + if (oAddPadding = '1') then + if (oRespIsFirst = '1') then + oByteEn := oFirstByteEn; + elsif (oRespIsLast = '1') then + oByteEn := oLastByteEn; + end if; + end if; + + if (clearAllI = '0') then + if (oZeroLen = '1') then + -- zero-payload path: emit response only, no BRAM write + if (addPaddingDataQValid = '1') and (payloadGenRespQNotFull = '1') then + addPaddingDataQRdEn <= '1'; + payloadGenRespQWrEn <= '1'; + payloadGenRespQDin <= oResp; + end if; + else + -- data path + if (addPaddingDataQValid = '1') and (adjustedPayloadValid = '1') and (payloadBufQNotFull = '1') then + if (oFragIsLast = '0') then + -- non-last fragment: forward frag, keep pending pad entry + adjustedPayloadRdEn <= '1'; + payloadBufQWrEn <= '1'; + payloadBufQDin <= oFrag; + elsif (payloadGenRespQNotFull = '1') then + -- last fragment: (opt) pad byteEn, retire pad entry, emit response + adjustedPayloadRdEn <= '1'; + addPaddingDataQRdEn <= '1'; + payloadGenRespQWrEn <= '1'; + payloadGenRespQDin <= oResp; + payloadBufQWrEn <= '1'; + payloadBufQDin <= oFrag(DS_W_C-1 downto 34) & oByteEn & oFrag(1 downto 0); + end if; + end if; + end if; + end if; + + ------------------------------------------------------------------------- + -- resetAndClear (top priority): force isFirstPktReg; mkRegU regs unreset + ------------------------------------------------------------------------- + if (rst = '1') or (clearAllI = '1') then + v.isFirstPktReg := '1'; -- BSV: isFirstPktReg <= True + -- pktRemoteAddrReg / remainingPktNumReg are mkRegU: NOT reset + end if; + + rin <= v; + end process comb; + + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + ----------------------------------------------------------------------------- + -- SURF FIFOs (source: surf/base/fifo/rtl/Fifo.vhd) + ----------------------------------------------------------------------------- + U_PayloadGenReqQ : entity surf.Fifo -- payloadGenReqQ <- mkFIFOF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PAYLOAD_GEN_REQ_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => reqInValid, din => reqInData, + not_full => payloadGenReqQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadGenReqQRdEn, dout => payloadGenReqQDout, + valid => payloadGenReqQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_AdjustReqPktLenQ : entity surf.Fifo -- adjustReqPktLenQ <- mkFIFOF (Tuple2) + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => ADJ_REQ_Q_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => adjustReqPktLenQWrEn, din => adjustReqPktLenQDin, + not_full => adjustReqPktLenQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => adjustReqPktLenQRdEn, dout => adjustReqPktLenQDout, + valid => adjustReqPktLenQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_AdjustFirstAndLastPktLenQ : entity surf.Fifo -- adjustFirstAndLastPktLenQ <- mkFIFOF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => TMP_FL_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => adjustFirstLastQWrEn, din => adjustFirstLastQDin, + not_full => adjustFirstLastQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => adjustFirstLastQRdEn, dout => adjustFirstLastQDout, + valid => adjustFirstLastQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_AdjustTotalPayloadMetaDataQ : entity surf.Fifo -- adjustTotalPayloadMetaDataQ <- mkFIFOF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => TMP_TOTAL_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => adjustTotalQWrEn, din => adjustTotalQDin, + not_full => adjustTotalQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => adjustTotalQRdEn, dout => adjustTotalQDout, + valid => adjustTotalQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_AdjustedTotalPayloadMetaDataQ : entity surf.Fifo -- adjustedTotalPayloadMetaDataQ <- mkFIFOF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => ADJ_TOTAL_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => adjustedTotalQWrEn, din => adjustedTotalQDin, + not_full => adjustedTotalQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => adjustedTotalQRdEn, dout => adjustedTotalQDout, + valid => adjustedTotalQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_GenPayloadRespQ : entity surf.Fifo -- genPayloadRespQ <- mkFIFOF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => TMP_RESP_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => genPayloadRespQWrEn, din => genPayloadRespQDin, + not_full => genPayloadRespQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => genPayloadRespQRdEn, dout => genPayloadRespQDout, + valid => genPayloadRespQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_TotalMetaDataOutQ : entity surf.Fifo -- totalMetaDataOutQ <- mkFIFOF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => TOTAL_META_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => totalMetaDataOutQWrEn, din => totalMetaDataOutQDin, + not_full => totalMetaDataOutQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => totalMetaDataDeq, dout => totalMetaDataOutQDout, + valid => totalMetaDataOutQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_AddPaddingDataQ : entity surf.Fifo -- addPaddingDataQ <- mkFIFOF (Tuple2) + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => ADD_PAD_Q_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => addPaddingDataQWrEn, din => addPaddingDataQDin, + not_full => addPaddingDataQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => addPaddingDataQRdEn, dout => addPaddingDataQDout, + valid => addPaddingDataQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadGenRespQ : entity surf.Fifo -- payloadGenRespQ <- mkFIFOF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => PAYLOAD_GEN_RESP_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => payloadGenRespQWrEn, din => payloadGenRespQDin, + not_full => payloadGenRespQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => respOutReady, dout => payloadGenRespQDout, + valid => payloadGenRespQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_SgePayloadOutQ : entity surf.Fifo -- sgePayloadOutQ <- mkFIFOF (pipeline) + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => sgePayloadOutQWrEn, din => sgePayloadOutQDin, + not_full => sgePayloadOutQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => sgePayloadOutQRdEn, dout => sgePayloadOutQDout, + valid => sgePayloadOutQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + U_PayloadBufQ : entity surf.Fifo -- payloadBufQ <- mkSizedBRAMFIFOF (depth 256) + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DS_W_C, + ADDR_WIDTH_G => BUF_ADDR_WIDTH_C) + port map ( + rst => fifoRst, wr_clk => clk, wr_en => payloadBufQWrEn, din => payloadBufQDin, + not_full => payloadBufQNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => payloadBufQRdEn, dout => payloadBufQDout, + valid => payloadBufQValid, underflow => open, prog_empty => open, + almost_empty => open, empty => open, rd_data_count => open); + + ----------------------------------------------------------------------------- + -- Child entities + ----------------------------------------------------------------------------- + -- U_SgeMergedPayload : merges per-SGE payload (dmaReadCntrl.sgePktMetaDataPipeOut + -- + sgePayloadOutQ) -> sgeMergedPayloadPipeOut + U_SgeMergedPayload : entity surf.MergePayloadEachSge + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, rst => rst, clearAllI => clearAllI, + sgePktMetaDataPipeInValid => sgePktMetaValid, + sgePktMetaDataPipeInData => sgePktMetaData, + sgePktMetaDataPipeInRdEn => sgePktMetaRdEn, + sgePayloadPipeInValid => sgePayloadOutQValid, + sgePayloadPipeInData => sgePayloadOutQDout, + sgePayloadPipeInRdEn => sgePayloadOutQRdEn, + pktPayloadOutValid => sgeMergedPayloadValid, + pktPayloadOutData => sgeMergedPayloadData, + pktPayloadOutRdEn => sgeMergedPayloadRdEn); + + -- U_SglMergedPayload : merges all-SGE payload (dmaReadCntrl.sgeMergedMetaDataPipeOut + -- + sgeMergedPayloadPipeOut) -> sglMergedPayloadPipeOut + U_SglMergedPayload : entity surf.MergePayloadAllSge + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, rst => rst, clearAllI => clearAllI, + sgeMergedMetaDataPipeInValid => sgeMergedMetaValid, + sgeMergedMetaDataPipeInData => sgeMergedMetaData, + sgeMergedMetaDataPipeInRdEn => sgeMergedMetaRdEn, + sgeMergedPayloadPipeInValid => sgeMergedPayloadValid, + sgeMergedPayloadPipeInData => sgeMergedPayloadData, + sgeMergedPayloadPipeInRdEn => sgeMergedPayloadRdEn, + pktPayloadOutValid => sglMergedPayloadValid, + pktPayloadOutData => sglMergedPayloadData, + pktPayloadOutRdEn => sglMergedPayloadRdEn); + + -- U_AdjustedPayload : re-segments payload by adjustedTotalPayloadMetaDataQ -> + -- adjustedPayloadPipeOut (consumed by outputAndAddPadding) + U_AdjustedPayload : entity surf.AdjustPayloadSegment + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, rst => rst, clearAllI => clearAllI, + adjustedMetaPipeInValid => adjustedTotalQValid, + adjustedMetaPipeInData => adjustedTotalQDout, + adjustedMetaPipeInRdEn => adjustedTotalQRdEn, + sglAllPayloadPipeInValid => sglMergedPayloadValid, + sglAllPayloadPipeInData => sglMergedPayloadData, + sglAllPayloadPipeInRdEn => sglMergedPayloadRdEn, + pktPayloadOutValid => adjustedPayloadValid, + pktPayloadOutData => adjustedPayloadData, + pktPayloadOutRdEn => adjustedPayloadRdEn); + + -- U_BramQ2PipeOut : drains payloadBufQ into the entity's DataStream pipeOut + U_BramQ2PipeOut : entity surf.ConnectBramQ2PipeOutGen + generic map ( + TPD_G => TPD_G, + DATA_W_G => DS_W_C) + port map ( + clk => clk, rst => rst, clearEnI => clearAllI, + bramQNotEmpty => payloadBufQValid, + bramQDout => payloadBufQDout, + bramQDeq => payloadBufQRdEn, + pipeOutDeq => payloadDataStreamDeq, + pipeOutFirst => payloadDataStreamFirst, + pipeOutNotEmpty => payloadDataStreamNotEmpty, + notEmpty => payloadNotEmpty); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/PermCheckCltArbiter.vhd b/ethernet/RoCEv2/rtl/PermCheckCltArbiter.vhd new file mode 100644 index 0000000000..570052d14a --- /dev/null +++ b/ethernet/RoCEv2/rtl/PermCheckCltArbiter.vhd @@ -0,0 +1,175 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Pure structural wrapper. `mkPermCheckCltArbiter` owns NO registered state, +-- NO rules and NO FIFOs of its own; its entire body defines two constant +-- predicate functions and instantiates ONE mkClientArbiter, returning that +-- interface unchanged: +-- +-- function Bool isPermCheckReqFinished (PermCheckReq req) = True; +-- function Bool isPermCheckRespFinished(Bool resp) = True; +-- let arbitratedClient <- mkClientArbiter( +-- permCheckCltVec, isPermCheckReqFinished, isPermCheckRespFinished); +-- return arbitratedClient; +-- +-- It specializes the generic ClientArbiter to: +-- reqType = PermCheckReq -> REQ_WIDTH_G = 267 (DataTypes.bsv:244-254) +-- respType = Bool -> RESP_WIDTH_G = 1 (PermCheckClt = Client#(PermCheckReq,Bool)) +-- portSz = 2*MAX_QP -> PORT_COUNT_G = 2*MAX_QP_G (default 8; OQ-FSM-PERMARB-01) +-- Each QP exposes TWO perm-check clients (permCheckClt4RQ, permCheckClt4SQ; +-- TransportLayer.bsv:112,139-140), so the vector size is TMul#(2,MAX_QP), NOT +-- MAX_QP. Even k = QP's RQ client, odd k = its SQ client (k = 2*qpIdx / 2*qpIdx+1). +-- +-- OQ-FSM-17 (predicate handling): mkClientArbiter takes isReqFinished / +-- isRespFinished as elaboration-time FUNCTION arguments; VHDL has no +-- function-type ports, so the parent (where the concrete type is known) feeds +-- them to the child as 1-bit inputs. For PermCheck BOTH predicates are the +-- constant function `= True`, so ALL child finished inputs are tied '1': +-- U_PermCheckArb.cltReqFinished(k) = isPermCheckReqFinished = True -> '1' (k=0..PORT_COUNT-1) +-- U_PermCheckArb.outRespFinished = isPermCheckRespFinished = True -> '1' +-- Consequence (for the TB writer): the child's shouldSaveGrantIdxReg stays '1' +-- forever, so every issued request records its grant index and every response +-- releases one — strict 1-request<->1-response, no multi-beat bursts. This is +-- the simplest arbiter case (contrast DmaWriteCltArbiter, whose req predicate +-- is req.dataStream.isLast). +-- +-- Because there is no state to translate, this architecture is emitted as pure +-- structural VHDL (one child instance + 1:1 boundary wiring + two constant +-- tie-offs) rather than the SURF two-process comb/seq template. There is no +-- RegType / REG_INIT_C — mkPermCheckCltArbiter has zero mkReg/mkRegU/mkCReg +-- fields (FSM spec §"State register": NONE). Same convention as the sibling +-- structural containers DmaArbiter4Qp.vhd (OQ-EMIT-DMAARB-01) and +-- SqQueuePair.vhd (OQ-EMIT-SQQP-01). +-- +-- Boundary is exposed VECTORED to mirror the child ClientArbiter's flattened +-- per-client buses (client k's REQ slice = ((k+1)*W-1 downto k*W)); the wrapper +-- forwards each bus straight through. Upstream group `permSrv*` = the per-QP +-- perm-check client faces (arbiter is master: it *gets* requests, *puts* +-- responses); downstream group `permClt*` = the single aggregated client face +-- toward mkPermCheckSrv (TransportLayer.bsv:157). +-- +-- Child entity instantiated (separately emitted): +-- U_PermCheckArb : work.ClientArbiter +-- (PORT_COUNT_G=2*MAX_QP_G, REQ_WIDTH_G=267, RESP_WIDTH_G=1) +-- source: out/04-vhdl/ClientArbiter.vhd +-- +-- SURF components instantiated DIRECTLY by this entity: NONE. Every surf.Fifo +-- (inputReqWithIdxVec, reqQ, respQ, preGrantIdxQ) and the arbitration tree live +-- inside the ClientArbiter child. +-- +-- MAX_QP_G generic convention: MAX_QP-dependent entities expose a top-level +-- MAX_QP_G generic (power of 2, >= 2; default 4 = Settings.bsv:14) rather than a +-- hard-locked 4. PORT_COUNT_G is derived as 2*MAX_QP_G (also a power of 2). +-- +-- NOTE: emitting does not prove equivalence — simulate this entity (cocotb/GHDL) +-- against the BSV behaviour before trusting it. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; + +entity PermCheckCltArbiter is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + MAX_QP_G : positive := 4; -- queue-pair count; power of 2, >= 2 (Settings.bsv:14) + PERM_REQ_WIDTH_G : positive := 267; -- Bits#(PermCheckReq) (DataTypes.bsv:244-254) + PERM_RESP_WIDTH_G : positive := 1; -- Bits#(Bool) (PermCheckClt resp type) + MEMORY_TYPE_G : string := "distributed"; -- child FIFO RAM style + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- child FIFO depth = 2**ADDR + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + + ----------------------------------------------------------------------- + -- Upstream per-QP PermCheck client faces (permCheckCltVec[k], + -- k = 0 .. 2*MAX_QP_G-1; arbiter is master). Client k's REQ payload slice + -- is ((k+1)*PERM_REQ_WIDTH_G-1 downto k*PERM_REQ_WIDTH_G); RESP likewise. + -- Even k = QP RQ perm-check client, odd k = QP SQ perm-check client. + ----------------------------------------------------------------------- + permSrvReqValid : in slv(2*MAX_QP_G-1 downto 0); -- client k request available + permSrvReqData : in slv(2*MAX_QP_G*PERM_REQ_WIDTH_G-1 downto 0); -- client k request payload, flattened + permSrvReqGet : out slv(2*MAX_QP_G-1 downto 0); -- arbiter takes client k's request + permSrvRespValid : out slv(2*MAX_QP_G-1 downto 0); -- arbiter drives a response to client k + permSrvRespData : out slv(2*MAX_QP_G*PERM_RESP_WIDTH_G-1 downto 0); -- response payload, flattened (selected port valid) + permSrvRespReady : in slv(2*MAX_QP_G-1 downto 0); -- client k can accept a response + + ----------------------------------------------------------------------- + -- Downstream aggregated PermCheck client face (toward mkPermCheckSrv) + ----------------------------------------------------------------------- + permCltReqValid : out sl; -- aggregated request valid + permCltReqData : out slv(PERM_REQ_WIDTH_G-1 downto 0); -- PermCheckReq + permCltReqRd : in sl; -- downstream request.get + permCltRespValid : in sl; -- downstream response.put fired + permCltRespData : in slv(PERM_RESP_WIDTH_G-1 downto 0); -- Bool response payload + permCltRespReady : out sl); -- can accept a response put +end entity PermCheckCltArbiter; + +architecture rtl of PermCheckCltArbiter is + + -- portSz = TMul#(2, MAX_QP) = 2*MAX_QP (OQ-FSM-PERMARB-01). Power-of-2 whenever + -- MAX_QP_G is, satisfying the child arbitration-tree proviso. + constant PORT_COUNT_C : positive := 2*MAX_QP_G; + + -- isPermCheckReqFinished = True for every port (OQ-FSM-17). Explicit constant + -- so the vector tie-off has an unambiguous subtype in the port association. + constant ALL_REQ_FINISHED_C : slv(PORT_COUNT_C-1 downto 0) := (others => '1'); + +begin + + -- MAX_QP proviso (MAX_QP_G generic convention). The child ClientArbiter carries + -- the same power-of-2 guard on PORT_COUNT_G; this local copy names the offending + -- entity if a parent mis-parameterizes MAX_QP_G. + assert isPowerOf2(MAX_QP_G) + report "PermCheckCltArbiter: MAX_QP_G must be a power of 2, >= 1 " & + "(child gets PORT_COUNT_G = 2*MAX_QP_G >= 2; OQ-FSM-PERMARB-01)" + severity failure; + + -------------------------------------------------------------------------- + -- U_PermCheckArb : the sole child (mkClientArbiter specialization). + -- Boundary forwarded 1:1; both finished predicates constant True -> tie '1'. + -------------------------------------------------------------------------- + U_PermCheckArb : entity surf.ClientArbiter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PORT_COUNT_G => PORT_COUNT_C, -- 2*MAX_QP (OQ-FSM-PERMARB-01) + REQ_WIDTH_G => PERM_REQ_WIDTH_G, -- 267 (PermCheckReq) + RESP_WIDTH_G => PERM_RESP_WIDTH_G, -- 1 (Bool) + MEMORY_TYPE_G => MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + clk => clk, + rst => rst, + -- Upstream per-QP client faces (1:1 forward) + cltReqValid => permSrvReqValid, + cltReqData => permSrvReqData, + cltReqFinished => ALL_REQ_FINISHED_C, -- isPermCheckReqFinished = True (OQ-FSM-17) + cltReqGet => permSrvReqGet, + cltRespValid => permSrvRespValid, + cltRespData => permSrvRespData, + cltRespReady => permSrvRespReady, + -- Downstream aggregated client face (1:1 forward) + outReqValid => permCltReqValid, + outReqData => permCltReqData, + outReqRd => permCltReqRd, + outRespValid => permCltRespValid, + outRespData => permCltRespData, + outRespFinished => '1', -- isPermCheckRespFinished = True (OQ-FSM-17) + outRespReady => permCltRespReady); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/PermCheckSrv.vhd b/ethernet/RoCEv2/rtl/PermCheckSrv.vhd new file mode 100644 index 0000000000..2b90dd4b50 --- /dev/null +++ b/ethernet/RoCEv2/rtl/PermCheckSrv.vhd @@ -0,0 +1,482 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Server#(PermCheckReq, Bool) that validates a memory-region permission +-- request and returns a single Bool (granted='1' / denied='0'). It is a +-- 3-stage dataflow pipeline (rules recvReq → checkReqStepOne → checkReqStepTwo) +-- with NO explicit state register: every rule deqs one FIFO, does a purely +-- combinational compute, and enqs the next FIFO, all in one atomic BSV firing. +-- All sequential storage lives in the four surf.Fifo instances, so this entity +-- has NO RegType and NO seq process (same stateless-pipeline shape as +-- CombineHeaderAndPayload) — the three stages are concurrent combinational +-- FIFO handshakes, each gated only by its own input notEmpty and output +-- notFull. The rules are conflict-free (disjoint FIFO read/write sets) and may +-- all fire in the same cycle (full-throughput pipeline). +-- +-- The BSV `immAssert(!isZeroDmaLen)` in recvReq is simulation-only and is NOT +-- emitted (synthesis drops it). +-- +-- External pdMetaData MR lookup (OQ-FSM-PCS-01): +-- `mkPermCheckSrv#(MetaDataPDs pdMetaData)` — pdMetaData is a MODULE ARGUMENT, +-- not an internal child (mapping.json child_entity_instances=[]). recvReq's MR +-- lookup is therefore exposed as an external combinational port group that the +-- PARENT wires to the flattened MetaDataPDs lookup ports; this entity does NOT +-- instantiate a MetaDataPDs/MetaDataMRs. The lookup address is presented from +-- the U_ReqInQ head and its result {mrLkupValid,mrLkupData} is captured into +-- the checkStepOneQ write word the SAME cycle recvReq fires. Confirm the exact +-- MetaDataPDs lookup-port names against that entity when it is emitted. +-- +-- Widths (traced — see out/03-fsm/PermCheckSrv.fsm.md, confirmed vs BSV): +-- PermCheckReq = 267 b (DataTypes.bsv:244-254) +-- MemRegion = 186 b (MetaData.bsv:155-162) +-- Maybe#(MemRegion) = 187 b ([186]=Valid tag, [185:0]=MemRegion) +-- checkStepOneQ elem = 455 b (PermCheckReq, Bool, Maybe#(MemRegion)) +-- checkStepTwoQ elem = 455 b (PermCheckReq, Maybe#(MemRegion), Bool) +-- respOutQ elem = 1 b (Bool) +-- +-- Bit packing (BSV deriving(Bits), first-field-at-MSB; project convention): +-- PermCheckReq [266:0]: +-- [266:202]=wrID(65) [201:170]=lkey(32) [169:138]=rkey(32) +-- [137]=localOrRmtKey [136:73]=reqAddr(64) [72:41]=totalLen(32) +-- [40:9]=pdHandler(32) [8]=isZeroDmaLen [7:0]=accFlags(8) +-- MemRegion [185:0]: +-- [185:122]=laddr(64) [121:90]=len(32) [89:82]=accFlags(8) +-- [81:50]=pdHandler(32) [49:25]=lkeyPart(25) [24:0]=rkeyPart(25) +-- Tuple3 first-field-at-MSB: +-- checkStepOneQ: [454:188]=req [187]=isZeroDmaLen [186:0]=maybeMR +-- checkStepTwoQ: [454:188]=req [187:1]=maybeMR [0]=stepOneResult +-- +-- Datapath (faithful to MetaData.bsv / Utils.bsv / PrimUtils.bsv): +-- recvReq : deq reqInQ; isZeroDmaLen=isZero(totalLen); +-- maybeMR = pdMetaData lookup by (localOrRmtKey?lkey:rkey); +-- enq checkStepOneQ (req, isZeroDmaLen, maybeMR). +-- checkReqStepOne : stepOneResult=isZeroDmaLen; if !isZeroDmaLen & MR.Valid: +-- keyMatch = truncate(key)==keyPart (low 25 bits); +-- accTypeMatch = compareAccessTypeFlags(mr.accFlags,accFlags) +-- = containFlags = (mr.accFlags & accFlags)==accFlags; +-- stepOneResult = keyMatch & accTypeMatch. +-- enq checkStepTwoQ (req, maybeMR, stepOneResult). +-- checkReqStepTwo : stepTwoResult=stepOneResult; if stepOneResult & MR.Valid: +-- stepTwoResult = checkAddrAndLenWithinRange(reqAddr,totalLen, +-- mr.laddr,mr.len); +-- enq respOutQ (stepTwoResult). +-- checkAddrAndLenWithinRange(laddr,dlen,raddr,rlen) (Utils.bsv:717-739): +-- hi[63:32], lo[31:0]; addrHighPartEq=(laddr.hi==raddr.hi); +-- addrLowPartMatch=(laddr.lo >= raddr.lo) [unsigned]; +-- lSum={0,laddr.lo}+{0,dlen}; rSum={0,raddr.lo}+{0,rlen} [33-bit]; +-- addrLenMatch=(rSum >= lSum); result = all three. (l=request, r=MR) +-- +-- SURF components instantiated (read at emit from surf/base/fifo/rtl/Fifo.vhd): +-- U_ReqInQ : surf.Fifo DATA_WIDTH_G=267, FWFT, sync, block +-- U_CheckStepOneQ: surf.Fifo DATA_WIDTH_G=455, FWFT, sync, block +-- U_CheckStepTwoQ: surf.Fifo DATA_WIDTH_G=455, FWFT, sync, block +-- U_RespOutQ : surf.Fifo DATA_WIDTH_G=1, FWFT, sync, distributed +-- All four are BSV mkFIFOF (2-deep). Emitted at ADDR_WIDTH_G=4 (16-deep) — the +-- SURF Fifo minimum; extra depth is behaviour-preserving for the notFull/ +-- notEmpty handshake (see OQ-EMIT-PCS-02). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity PermCheckSrv is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + ----------------------------------------------------------------------- + -- Server request : request.put -> reqInQ.enq (PermCheckReq, 267 b) + ----------------------------------------------------------------------- + reqPutValid : in sl; -- upstream has a request + reqPutData : in slv(266 downto 0); -- PermCheckReq + reqPutReady : out sl; -- = reqInQ.notFull + ----------------------------------------------------------------------- + -- Server response : respOutQ -> response.get (Bool) + ----------------------------------------------------------------------- + respGetValid : out sl; -- = respOutQ.notEmpty + respGetData : out sl; -- granted(1)/denied(0) + respGetRdEn : in sl; -- response.get (deq respOutQ) + ----------------------------------------------------------------------- + -- External pdMetaData MR lookup (module arg; combinational) — OQ-FSM-PCS-01 + ----------------------------------------------------------------------- + mrLkupPdHandler : out slv(31 downto 0); -- req.pdHandler + mrLkupKey : out slv(31 downto 0); -- localOrRmtKey ? lkey : rkey + mrLkupByLocal : out sl; -- localOrRmtKey (LKEY vs RKEY) + mrLkupReqValid : out sl; -- recvReq fire (head is live) + mrLkupValid : in sl; -- returned Maybe tag + mrLkupData : in slv(185 downto 0)); -- returned MemRegion (186 b) +end entity PermCheckSrv; + +architecture rtl of PermCheckSrv is + + --------------------------------------------------------------------------- + -- Element widths + --------------------------------------------------------------------------- + constant REQ_WIDTH_C : natural := 267; -- PermCheckReq + constant MR_WIDTH_C : natural := 186; -- MemRegion + constant MAYBE_MR_WIDTH_C : natural := 187; -- Maybe#(MemRegion) + constant STEP_WIDTH_C : natural := 455; -- checkStepOne/TwoQ element + + --------------------------------------------------------------------------- + -- U_ReqInQ (267 b) : request.put write side / recvReq read side + --------------------------------------------------------------------------- + signal reqInQWrEn : sl; + signal reqInQDin : slv(REQ_WIDTH_C-1 downto 0); + signal reqInQNotFull : sl; + signal reqInQRdEn : sl; + signal reqInQValid : sl; + signal reqInQDout : slv(REQ_WIDTH_C-1 downto 0); + + --------------------------------------------------------------------------- + -- U_CheckStepOneQ (455 b) : recvReq write side / checkReqStepOne read side + --------------------------------------------------------------------------- + signal stepOneQWrEn : sl; + signal stepOneQDin : slv(STEP_WIDTH_C-1 downto 0); + signal stepOneQNotFull : sl; + signal stepOneQRdEn : sl; + signal stepOneQValid : sl; + signal stepOneQDout : slv(STEP_WIDTH_C-1 downto 0); + + --------------------------------------------------------------------------- + -- U_CheckStepTwoQ (455 b) : checkReqStepOne write side / checkReqStepTwo read + --------------------------------------------------------------------------- + signal stepTwoQWrEn : sl; + signal stepTwoQDin : slv(STEP_WIDTH_C-1 downto 0); + signal stepTwoQNotFull : sl; + signal stepTwoQRdEn : sl; + signal stepTwoQValid : sl; + signal stepTwoQDout : slv(STEP_WIDTH_C-1 downto 0); + + --------------------------------------------------------------------------- + -- U_RespOutQ (1 b) : checkReqStepTwo write side / response.get read side + --------------------------------------------------------------------------- + signal respOutQWrEn : sl; + signal respOutQDin : slv(0 downto 0); + signal respOutQNotFull : sl; + signal respOutQRdEn : sl; + signal respOutQValid : sl; + signal respOutQDout : slv(0 downto 0); + +begin + + --------------------------------------------------------------------------- + -- Server request-side wiring (request.put -> U_ReqInQ.enq) + -- ready = notFull ; enq on valid & ready (FIFO ignores writes when full). + --------------------------------------------------------------------------- + reqPutReady <= reqInQNotFull; + reqInQWrEn <= reqPutValid and reqInQNotFull; + reqInQDin <= reqPutData; + + --------------------------------------------------------------------------- + -- Server response-side wiring (U_RespOutQ.first/deq -> response.get) + --------------------------------------------------------------------------- + respGetValid <= respOutQValid; + respGetData <= respOutQDout(0); + respOutQRdEn <= respGetRdEn; + + --------------------------------------------------------------------------- + -- U_ReqInQ : surf.Fifo (BSV: reqInQ <- mkFIFOF, PermCheckReq = 267 b) + --------------------------------------------------------------------------- + U_ReqInQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => REQ_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => reqInQWrEn, + din => reqInQDin, + not_full => reqInQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => reqInQRdEn, + dout => reqInQDout, + valid => reqInQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_CheckStepOneQ : surf.Fifo (BSV: checkStepOneQ <- mkFIFOF, 455 b) + --------------------------------------------------------------------------- + U_CheckStepOneQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => STEP_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => stepOneQWrEn, + din => stepOneQDin, + not_full => stepOneQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => stepOneQRdEn, + dout => stepOneQDout, + valid => stepOneQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_CheckStepTwoQ : surf.Fifo (BSV: checkStepTwoQ <- mkFIFOF, 455 b) + --------------------------------------------------------------------------- + U_CheckStepTwoQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => STEP_WIDTH_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => stepTwoQWrEn, + din => stepTwoQDin, + not_full => stepTwoQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => stepTwoQRdEn, + dout => stepTwoQDout, + valid => stepTwoQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_RespOutQ : surf.Fifo (BSV: respOutQ <- mkFIFOF, Bool = 1 b) + --------------------------------------------------------------------------- + U_RespOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => respOutQWrEn, + din => respOutQDin, + not_full => respOutQNotFull, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => respOutQRdEn, + dout => respOutQDout, + valid => respOutQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial pipeline : the three conflict-free BSV rules, each a + -- single-cycle deq + combinational compute + enq. No registered state + -- (all state is in the four FIFOs) so there is no seq process / RegType. + --------------------------------------------------------------------------- + comb : process (reqInQValid, reqInQDout, stepOneQNotFull, + stepOneQValid, stepOneQDout, stepTwoQNotFull, + stepTwoQValid, stepTwoQDout, respOutQNotFull, + mrLkupValid, mrLkupData) is + -- fire conditions + variable recvFire : sl; + variable s1Fire : sl; + variable s2Fire : sl; + -- recvReq + variable req0 : slv(REQ_WIDTH_C-1 downto 0); + variable localKey0 : sl; + variable zeroLen0 : sl; + variable maybeMR0 : slv(MAYBE_MR_WIDTH_C-1 downto 0); + -- checkReqStepOne + variable req1 : slv(REQ_WIDTH_C-1 downto 0); + variable zeroLen1 : sl; + variable mrValid1 : sl; + variable mr1 : slv(MR_WIDTH_C-1 downto 0); + variable local1 : sl; + variable keyLow1 : slv(24 downto 0); + variable keyPart1 : slv(24 downto 0); + variable accReq1 : slv(7 downto 0); + variable accMr1 : slv(7 downto 0); + variable keyMatch : sl; + variable accMatch : sl; + variable s1Result : sl; + -- checkReqStepTwo + variable req2 : slv(REQ_WIDTH_C-1 downto 0); + variable mrValid2 : sl; + variable mr2 : slv(MR_WIDTH_C-1 downto 0); + variable s1In2 : sl; + variable reqAddr2 : slv(63 downto 0); + variable totalLen2 : slv(31 downto 0); + variable mrLaddr2 : slv(63 downto 0); + variable mrLen2 : slv(31 downto 0); + variable hiEq : sl; + variable loGe : sl; + variable lSum : unsigned(32 downto 0); + variable rSum : unsigned(32 downto 0); + variable lenOk : sl; + variable rangeOk : sl; + variable s2Result : sl; + begin + -- Defaults (all drives deasserted) + reqInQRdEn <= '0'; + stepOneQWrEn <= '0'; + stepOneQDin <= (others => '0'); + stepOneQRdEn <= '0'; + stepTwoQWrEn <= '0'; + stepTwoQDin <= (others => '0'); + stepTwoQRdEn <= '0'; + respOutQWrEn <= '0'; + respOutQDin <= (others => '0'); + mrLkupPdHandler <= (others => '0'); + mrLkupKey <= (others => '0'); + mrLkupByLocal <= '0'; + mrLkupReqValid <= '0'; + + ----------------------------------------------------------------------- + -- recvReq : deq reqInQ; combinational MR lookup via pdMetaData; + -- enq checkStepOneQ (req, isZeroDmaLen, maybeMR). + ----------------------------------------------------------------------- + recvFire := reqInQValid and stepOneQNotFull; + req0 := reqInQDout; + localKey0 := req0(137); -- localOrRmtKey + zeroLen0 := toSl(unsigned(req0(72 downto 41)) = 0); -- isZero(totalLen) + + -- Present the lookup address from the U_ReqInQ head (combinational) + mrLkupPdHandler <= req0(40 downto 9); -- pdHandler + mrLkupKey <= ite(localKey0 = '1', req0(201 downto 170), req0(169 downto 138)); + mrLkupByLocal <= localKey0; + mrLkupReqValid <= recvFire; + + -- Capture the returned Maybe#(MemRegion) this same cycle + maybeMR0 := mrLkupValid & mrLkupData; -- [186]=tag [185:0]=MR + + if recvFire = '1' then + reqInQRdEn <= '1'; -- reqInQ.deq + stepOneQWrEn <= '1'; -- checkStepOneQ.enq + stepOneQDin <= req0 & zeroLen0 & maybeMR0; -- 267+1+187 = 455 + end if; + + ----------------------------------------------------------------------- + -- checkReqStepOne : deq checkStepOneQ; key + access-flag match; + -- enq checkStepTwoQ (req, maybeMR, stepOneResult). + ----------------------------------------------------------------------- + s1Fire := stepOneQValid and stepTwoQNotFull; + req1 := stepOneQDout(454 downto 188); + zeroLen1 := stepOneQDout(187); + mrValid1 := stepOneQDout(186); -- Maybe tag + mr1 := stepOneQDout(185 downto 0); -- MemRegion + local1 := req1(137); + accReq1 := req1(7 downto 0); -- req.accFlags + accMr1 := mr1(89 downto 82); -- mr.accFlags + -- truncate(key) keeps low 25 bits (KeyPartMR); keyPart per local/remote + keyLow1 := ite(local1 = '1', req1(194 downto 170), req1(162 downto 138)); + keyPart1 := ite(local1 = '1', mr1(49 downto 25), mr1(24 downto 0)); + keyMatch := toSl(keyLow1 = keyPart1); + accMatch := toSl((accMr1 and accReq1) = accReq1); -- containFlags + + s1Result := zeroLen1; -- default + if (zeroLen1 = '0') and (mrValid1 = '1') then + s1Result := keyMatch and accMatch; + end if; + + if s1Fire = '1' then + stepOneQRdEn <= '1'; -- checkStepOneQ.deq + stepTwoQWrEn <= '1'; -- checkStepTwoQ.enq + stepTwoQDin <= req1 & (mrValid1 & mr1) & s1Result; -- 267+187+1 = 455 + end if; + + ----------------------------------------------------------------------- + -- checkReqStepTwo : deq checkStepTwoQ; address/length-in-range check; + -- enq respOutQ (stepTwoResult). + ----------------------------------------------------------------------- + s2Fire := stepTwoQValid and respOutQNotFull; + req2 := stepTwoQDout(454 downto 188); + mrValid2 := stepTwoQDout(187); -- Maybe tag + mr2 := stepTwoQDout(186 downto 1); -- MemRegion + s1In2 := stepTwoQDout(0); -- stepOneResult + reqAddr2 := req2(136 downto 73); -- req.reqAddr + totalLen2 := req2(72 downto 41); -- req.totalLen (dlen) + mrLaddr2 := mr2(185 downto 122); -- mr.laddr + mrLen2 := mr2(121 downto 90); -- mr.len (rlen) + + -- checkAddrAndLenWithinRange (l=request, r=MR) + hiEq := toSl(reqAddr2(63 downto 32) = mrLaddr2(63 downto 32)); + loGe := toSl(unsigned(reqAddr2(31 downto 0)) >= unsigned(mrLaddr2(31 downto 0))); + lSum := ('0' & unsigned(reqAddr2(31 downto 0))) + ('0' & unsigned(totalLen2)); + rSum := ('0' & unsigned(mrLaddr2(31 downto 0))) + ('0' & unsigned(mrLen2)); + lenOk := toSl(rSum >= lSum); + rangeOk := hiEq and loGe and lenOk; + + s2Result := s1In2; -- default + if (s1In2 = '1') and (mrValid2 = '1') then + s2Result := rangeOk; + end if; + + if s2Fire = '1' then + stepTwoQRdEn <= '1'; -- checkStepTwoQ.deq + respOutQWrEn <= '1'; -- respOutQ.enq + respOutQDin <= (others => s2Result); -- Bool (1 b) + end if; + + end process comb; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/PipeOutArbiter.vhd b/ethernet/RoCEv2/rtl/PipeOutArbiter.vhd new file mode 100644 index 0000000000..bb24609ec5 --- /dev/null +++ b/ethernet/RoCEv2/rtl/PipeOutArbiter.vhd @@ -0,0 +1,123 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Purely structural wrapper — this entity owns NO state, NO rules, and NO +-- SURF instances directly (mapping.json: rule_count=0, state_registers=[], +-- surf_instances=[]). Per the FSM spec, mkPipeOutArbiter is a 1:1 passthrough: +-- it instantiates mkLeafBinaryPipeOutArbiterVec + mkBinaryPipeOutArbiterTree, +-- which are exactly the pair collapsed into the BinaryArbTree entity +-- (out/03-fsm/BinaryArbTree.fsm.md / out/04-vhdl/BinaryArbTree.vhd). This +-- entity therefore instantiates a single BinaryArbTree (U_Tree) and re-exposes +-- its ports unchanged. The sole rule in the BSV source (`rule debug`, +-- lines 379-395) is commented out and carries no behavior, so nothing is +-- dropped by omitting it. +-- +-- OQ-FSM-PERMARB-01 (supersedes the OQ-HIER-01 fixed unroll): generic +-- PORT_COUNT_G (any power of 2, >= 1; 1 = passthrough per the BSV base case +-- Arbitration.bsv:317-319, GEN_BYPASS) forwarded to U_Tree unchanged; the +-- power-of-2 assert and the bit-reverse leaf permutation live inside +-- BinaryArbTree. Concrete BSV uses span PORT_COUNT_G = 8 (dataStreamArb over +-- qpDataStreamPipeOutVec, and the three ClientArbiter specializations at +-- 2*MAX_QP) and PORT_COUNT_G = 4 (rqWcArb/sqWcArb WorkComp arbiters at +-- MAX_QP). Ports are vectored/flattened to match BinaryArbTree: input k's +-- payload is inDout((k+1)*DATA_WIDTH_G-1 downto k*DATA_WIDTH_G). +-- +-- outFinished: forwarded 1:1 from U_Tree (OQ-FSM-ARBTREE-01 companion) so +-- downstream consumers (ServerArbiter, DmaArbiter4Qp, TransportLayer) that +-- need the finish predicate can wire it directly. +-- +-- SURF components instantiated: NONE directly. All arbitration and the +-- surf.Fifo (U_OutQ) instances live inside U_Tree's BinaryPipeOutArbiter +-- children — see out/04-vhdl/BinaryArbTree.vhd / BinaryPipeOutArbiter.vhd. +-- +-- NOTE: emitting does not prove equivalence — simulate this entity against +-- the BSV behaviour before trusting it, even though it is pure wiring: +-- a testbench still needs to confirm no port got swapped/mis-mapped. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity PipeOutArbiter is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + PORT_COUNT_G : positive := 8; -- number of PipeOut inputs; any power of 2, >= 1 (1 = passthrough, Arbitration.bsv:317) (OQ-FSM-PERMARB-01) + DATA_WIDTH_G : positive := 8; -- payload width = tSz of BSV anytype + MEMORY_TYPE_G : string := "distributed"; -- child output FIFO RAM style + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- child output FIFO depth = 2**ADDR + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- PORT_COUNT_G upstream PipeOut inputs, forwarded 1:1 to U_Tree; + -- input k's payload is inDout((k+1)*DATA_WIDTH_G-1 downto k*DATA_WIDTH_G) + inValid : in slv(PORT_COUNT_G-1 downto 0); -- in(k).notEmpty + inDout : in slv(PORT_COUNT_G*DATA_WIDTH_G-1 downto 0); -- in(k).first, flattened + inFinished : in slv(PORT_COUNT_G-1 downto 0); -- isPipePayloadFinished(in(k).first) + inRd : out slv(PORT_COUNT_G-1 downto 0); -- in(k).deq strobe + -- tree PipeOut output, forwarded 1:1 from U_Tree + outNotEmpty : out sl; -- tree PipeOut.notEmpty + outDout : out slv(DATA_WIDTH_G-1 downto 0); -- tree PipeOut.first + outFinished : out sl; -- tree head finish predicate (see note above) + outDeq : in sl); -- external dequeue of the tree output +end entity PipeOutArbiter; + +architecture struct of PipeOutArbiter is + +begin + + -------------------------------------------------------------------------- + -- GEN_BYPASS : PORT_COUNT_G = 1 — BSV base case (Arbitration.bsv:317-319, + -- mkBinaryPipeOutArbiterTree returns inputPipeOutVec[0]): + -- a 1-port arbiter is a pure passthrough, zero logic. + -------------------------------------------------------------------------- + GEN_BYPASS : if PORT_COUNT_G = 1 generate + outNotEmpty <= inValid(0); + outDout <= inDout; -- widths identical at PORT_COUNT_G=1 + outFinished <= inFinished(0); + inRd(0) <= outDeq; + end generate GEN_BYPASS; + + -------------------------------------------------------------------------- + -- GEN_TREE : PORT_COUNT_G > 1 — + -- U_Tree : mkLeafBinaryPipeOutArbiterVec + mkBinaryPipeOutArbiterTree, + -- collapsed into BinaryArbTree — every port forwarded unchanged. + -------------------------------------------------------------------------- + GEN_TREE : if PORT_COUNT_G > 1 generate + U_Tree : entity surf.BinaryArbTree + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + PORT_COUNT_G => PORT_COUNT_G, + DATA_WIDTH_G => DATA_WIDTH_G, + MEMORY_TYPE_G => MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + clk => clk, + rst => rst, + inValid => inValid, + inDout => inDout, + inFinished => inFinished, + inRd => inRd, + outNotEmpty => outNotEmpty, + outDout => outDout, + outFinished => outFinished, + outDeq => outDeq); + end generate GEN_TREE; + +end architecture struct; diff --git a/ethernet/RoCEv2/rtl/PipeOutMux.vhd b/ethernet/RoCEv2/rtl/PipeOutMux.vhd new file mode 100644 index 0000000000..3acf06de38 --- /dev/null +++ b/ethernet/RoCEv2/rtl/PipeOutMux.vhd @@ -0,0 +1,194 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Combinatorially selects one of two upstream PipeOut sources and forwards its +-- head element into an output FIFO (U_PipeMuxOutQ), whose read side is the +-- entity's own PipeOut interface. +-- +-- BSV has two mutually-exclusive rules driven by the Boolean argument `sel`: +-- outputPipeIn1 if (sel) : enq(pipeIn1.first); pipeIn1.deq +-- outputPipeIn2 if (!sel) : enq(pipeIn2.first); pipeIn2.deq +-- Each rule additionally carries the implicit conditions of the FIFO methods: +-- the chosen source must be notEmpty (Valid) and the output FIFO notFull. +-- The two guards (`sel` / `!sel`) are complements, so at most one fires per +-- cycle — a plain if/else in the comb process suffices (no priority needed). +-- +-- No local registered state: mkPipeOutMux has zero mkReg/mkRegU. The only +-- persistent element is pipeMuxOutQ, a SURF Fifo. The two-process skeleton is +-- retained for uniformity; the RegType record carries a single dummy field so +-- the VHDL compiles without an empty record. All datapath outputs are Mealy +-- (combinatorial from `sel` and the *Valid/*Dout/notFull inputs). +-- +-- SURF components instantiated: +-- U_PipeMuxOutQ : surf.Fifo (DATA_WIDTH_G=679, FWFT, sync, block RAM) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- +-- DATA_WIDTH_G (OQ resolved at emit): +-- BSV `anytype` = PendingWorkReq at the QueuePair.bsv:176 instantiation +-- (pipeIn1 = scanPipeOut, pipeIn2 = newPendingWorkReqPiptOut, both +-- PipeOut#(PendingWorkReq)). sizeof(PendingWorkReq) = 679 bits, matching the +-- output width of sibling entity NewPendingWorkReqPipeOut (outQDout_o). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity PipeOutMux is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + DATA_WIDTH_G : positive := 679; -- sizeof(PendingWorkReq) + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- U_PipeMuxOutQ depth = 2**G + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- Select: BSV module argument `sel` (Bool). '1' -> pipeIn1, '0' -> pipeIn2 + sel : in sl; + -- Upstream PipeOut #1 (pipeIn1) + pipeIn1Valid : in sl; -- pipeIn1.notEmpty + pipeIn1Dout : in slv(DATA_WIDTH_G-1 downto 0); -- pipeIn1.first + pipeIn1RdEn : out sl; -- pipeIn1.deq + -- Upstream PipeOut #2 (pipeIn2) + pipeIn2Valid : in sl; -- pipeIn2.notEmpty + pipeIn2Dout : in slv(DATA_WIDTH_G-1 downto 0); -- pipeIn2.first + pipeIn2RdEn : out sl; -- pipeIn2.deq + -- Output PipeOut (toPipeOut(pipeMuxOutQ) exposed via U_PipeMuxOutQ read side) + pipeOutValid : out sl; -- pipeMuxOutQ.notEmpty + pipeOutDout : out slv(DATA_WIDTH_G-1 downto 0); -- pipeMuxOutQ.first + pipeOutRdEn : in sl); -- pipeMuxOutQ.deq (downstream) +end PipeOutMux; + +architecture rtl of PipeOutMux is + + -- No local FSM state: all state lives in U_PipeMuxOutQ. + -- One dummy bit keeps the RegType record syntactically non-empty. + type RegType is record + dummy : sl; + end record RegType; + + constant REG_INIT_C : RegType := (dummy => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_PipeMuxOutQ (SURF Fifo) signals + signal muxOutQRst : sl; + signal muxOutQWrEn : sl; + signal muxOutQDin : slv(DATA_WIDTH_G-1 downto 0); + signal muxOutQNotFull : sl; + + -- Global reset normalised to active-high (for FIFO rst port) + signal rstActiveHigh : sl; + +begin + + -- Normalise global rst to active-high for the SURF Fifo rst port + rstActiveHigh <= rst when (RST_POLARITY_G = '1') else not rst; + muxOutQRst <= rstActiveHigh; + + -------------------------------------------------------------------------- + -- U_PipeMuxOutQ : pipeMuxOutQ + -- BSV: FIFOF#(anytype), instantiated as mkFIFOF (depth 2, FWFT) + -- SURF: surf.Fifo, GEN_SYNC_FIFO_G=true, FWFT_EN_G=true + -- Width: DATA_WIDTH_G = 679 bits (PendingWorkReq) + -------------------------------------------------------------------------- + U_PipeMuxOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DATA_WIDTH_G, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => muxOutQRst, + wr_clk => clk, + wr_en => muxOutQWrEn, + din => muxOutQDin, + not_full => muxOutQNotFull, + rd_clk => clk, + rd_en => pipeOutRdEn, + dout => pipeOutDout, + valid => pipeOutValid); + + -------------------------------------------------------------------------- + -- Combinatorial: per-cycle rule evaluation (all outputs Mealy) + -- outputPipeIn1 (sel='1') and outputPipeIn2 (sel='0') are mutually + -- exclusive by guard complement — a plain if/else, no priority ordering. + -------------------------------------------------------------------------- + comb : process (r, rst, sel, pipeIn1Valid, pipeIn1Dout, pipeIn2Valid, + pipeIn2Dout, muxOutQNotFull) is + variable v : RegType; + variable in1RdEnV : sl; + variable in2RdEnV : sl; + variable wrEnV : sl; + variable dinV : slv(DATA_WIDTH_G-1 downto 0); + begin + v := r; + + -- Default all Mealy outputs to inactive + in1RdEnV := '0'; + in2RdEnV := '0'; + wrEnV := '0'; + dinV := (others => '0'); + + if (sel = '1') then + -- Rule outputPipeIn1: forward pipeIn1 head into the output FIFO + if (pipeIn1Valid = '1') and (muxOutQNotFull = '1') then + wrEnV := '1'; + dinV := pipeIn1Dout; + in1RdEnV := '1'; + end if; + else + -- Rule outputPipeIn2: forward pipeIn2 head into the output FIFO + if (pipeIn2Valid = '1') and (muxOutQNotFull = '1') then + wrEnV := '1'; + dinV := pipeIn2Dout; + in2RdEnV := '1'; + end if; + end if; + + -- Synchronous reset (dummy field only; no live state to restore) + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + + -- Drive outputs + pipeIn1RdEn <= in1RdEnV; + pipeIn2RdEn <= in2RdEnV; + muxOutQWrEn <= wrEnV; + muxOutQDin <= dinV; + + end process comb; + + -------------------------------------------------------------------------- + -- Sequential: register update (skeleton only; no live registered fields) + -------------------------------------------------------------------------- + seq : process (clk, rst) is + begin + if (RST_ASYNC_G) and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd b/ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd new file mode 100644 index 0000000000..3e556b549c --- /dev/null +++ b/ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd @@ -0,0 +1,497 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Prepends a (right-aligned) header DataStream onto a payload DataStream and +-- emits one merged, left-aligned DataStream. The header's last fragment is +-- only partially valid; payload fragments are shifted by the header's +-- valid-bit amount and concatenated across fragment boundaries, producing an +-- extra trailing fragment when the merge overflows the 256-bit bus. +-- +-- Single SURF Fifo (U_DataStreamOutQ); its read side IS the module's +-- toPipeOut(dataStreamOutQ) — i.e. the entity's DataStream output port. The +-- three upstream pipes (headerMetaDataPipeIn / headerPipeIn / dataPipeIn) are +-- PipeOut *arguments* (input handshake ports), NOT FIFOs instantiated here. +-- +-- FIVE rules (fsm.md transition table): +-- resetAndClear (guard clearAllI, fire_when_enabled) — flush the FIFO and +-- force stageReg = HEADER_META_DATA_POP_S. +-- popHeaderMetaData (POP) — latch HeaderMetaData, branch to HOUT or DOUT. +-- outputHeader (HOUT) — stream header frags; on the last frag stash a +-- right-shifted residue into preDataStreamReg. +-- outputData (DOUT) — merge payload frags with the header residue. +-- extraLastFrag (EXTRA) — emit the overflow tail fragment. +-- The four stage rules are guarded on distinct stageReg values (one-hot) and +-- are mutually exclusive; emitted as a single `case r.stageReg` under +-- `if clearAllI = '0'`. +-- +-- Mapping note (OQ-FSM-PH2PO-01): mapping.json / modules.json are STALE for +-- this entity — they record a single bogus rule `merge`, a non-existent +-- `mergeQ` FIFO (321b), and a non-existent internal `hdr2DS = +-- mkHeader2DataStream` submodule. None exist in the BSV source. This file +-- follows PrependHeader2PipeOut.fsm.md, which is authoritative. +-- +-- Width / packing resolutions applied: +-- - DataStream width = 290 bits (OQ-FSM-H2DS-02 / PH2PO-02 RESOLVED) +-- - all struct packing first-field-at-MSB (OQ-FSM-H2DS-04 / PH2PO-02 RESOLVED) +-- +-- FIFO clear (OQ-FSM-01 / PH2PO-02 RESOLVED): surf.Fifo has no clear port; the +-- BSV FIFOF.clear (asserted as a LEVEL by resetAndClear while clearAll='1') +-- is modelled by asserting the synchronous FIFO reset: +-- fifoRst = rst OR clearAllI. +-- +-- Atomicity (fsm.md "Atomicity caution"): in outputData, outDS.isFirst reads +-- OLD r.isFirstReg while v.isFirstReg := '0' is assigned the same cycle; +-- tmpData/tmpByteEn read OLD r.preDataStreamReg while v.preDataStreamReg := +-- frag. All reads are taken from r.*, all writes go to v.* — no +-- read-after-write within the comb evaluation. A stage rule fires only when +-- its upstream notEmpty AND (for the enq'ing arms) downstream notFull hold; +-- stageReg, the deq strobes and wrEn are gated together (BSV rule atomicity). +-- +-- Bit layouts (BSV deriving(Bits), first-field-at-MSB): +-- DataStream (290): [289:34] data[255:0] | [33:2] byteEn[31:0] | +-- [1] isFirst | [0] isLast +-- HeaderMetaData (17): +-- [16:10] headerLen[6:0] (sim-assert only) | [9:8] headerFragNum[1:0] | +-- [7:2] lastFragValidByteNum[5:0] | [1] hasPayload | [0] isEmptyHeader +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_DataStreamOutQ : surf.Fifo DATA_WIDTH_G=290 (output, read side exposed) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity PrependHeader2PipeOut is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (BSV constructor parameter clearAll : Bool) + clearAllI : in sl; + -- Upstream: HeaderMetaData pipe (headerMetaDataPipeIn argument) + headerMetaPipeInValid : in sl; -- .notEmpty + headerMetaPipeInData : in slv(16 downto 0); -- .first (HeaderMetaData) + headerMetaPipeInRdEn : out sl; -- .deq + -- Upstream: header DataStream pipe (headerPipeIn argument) + headerPipeInValid : in sl; -- .notEmpty + headerPipeInData : in slv(289 downto 0); -- .first (DataStream) + headerPipeInRdEn : out sl; -- .deq + -- Upstream: payload DataStream pipe (dataPipeIn argument) + dataPipeInValid : in sl; -- .notEmpty + dataPipeInData : in slv(289 downto 0); -- .first (DataStream) + dataPipeInRdEn : out sl; -- .deq + -- Downstream: returned PipeOut#(DataStream) (read side of U_DataStreamOutQ) + dataStreamOutValid : out sl; -- PipeOut.notEmpty + dataStreamOutData : out slv(289 downto 0); -- PipeOut.first + dataStreamOutRdEn : in sl); -- PipeOut.deq +end entity PrependHeader2PipeOut; + +architecture rtl of PrependHeader2PipeOut is + + -- Maps BSV ExtractOrPrependHeaderStage: + -- HEADER_META_DATA_POP -> HEADER_META_DATA_POP_S + -- HEADER_OUTPUT -> HEADER_OUTPUT_S + -- DATA_OUTPUT -> DATA_OUTPUT_S + -- EXTRA_LAST_FRAG_OUTPUT -> EXTRA_LAST_FRAG_OUTPUT_S + type StateType is ( + HEADER_META_DATA_POP_S, + HEADER_OUTPUT_S, + DATA_OUTPUT_S, + EXTRA_LAST_FRAG_OUTPUT_S); + + type RegType is record + stageReg : StateType; -- mkReg(HEADER_META_DATA_POP) + preDataStreamReg : slv(289 downto 0); -- mkRegU (DataStream, right-aligned) + headerFragCntReg : slv(1 downto 0); -- mkRegU (HeaderFragNum) + headerLastFragInvalidBitNumReg : slv(8 downto 0); -- mkRegU (BusBitNum) + headerLastFragInvalidByteNumReg: slv(5 downto 0); -- mkRegU (ByteEnBitNum) + headerLastFragValidBitNumReg : slv(8 downto 0); -- mkRegU (BusBitNum) + headerLastFragValidByteNumReg : slv(5 downto 0); -- mkRegU (ByteEnBitNum) + headerHasPayloadReg : sl; -- mkRegU + isFirstReg : sl; -- mkRegU + end record RegType; + + -- mkRegU fields set to '0' in REG_INIT_C (OQ-FSM-04 precedent): every field + -- is written before it is read on any live path (popHeaderMetaData sets the + -- header context; preDataStreamReg/isFirstReg are written before the merge + -- arms read them), so the reset value is don't-care (no correctness risk). + constant REG_INIT_C : RegType := ( + stageReg => HEADER_META_DATA_POP_S, + preDataStreamReg => (others => '0'), + headerFragCntReg => (others => '0'), + headerLastFragInvalidBitNumReg => (others => '0'), + headerLastFragInvalidByteNumReg => (others => '0'), + headerLastFragValidBitNumReg => (others => '0'), + headerLastFragValidByteNumReg => (others => '0'), + headerHasPayloadReg => '0', + isFirstReg => '0'); + + constant DATA_BUS_BYTE_WIDTH_C : natural := 32; -- DATA_BUS_BYTE_WIDTH + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Shared synchronous clear for the output FIFO (rst OR clearAllI) + signal fifoRst : sl; + + -- U_DataStreamOutQ control / status (output queue; read side exposed) + signal dsOutQWrEn : sl; + signal dsOutQDin : slv(289 downto 0); + signal dsOutQFull : sl; + +begin + + -- FIFO reset: level-sensitive synchronous clear (OQ-FSM-01 RESOLVED). + -- resetAndClear calls dataStreamOutQ.clear while clearAllI='1'. + fifoRst <= rst or clearAllI; + + --------------------------------------------------------------------------- + -- U_DataStreamOutQ : surf.Fifo + -- Output queue; its read side IS the returned PipeOut#(DataStream). + -- Written by outputHeader / outputData / extraLastFrag. + -- DATA_WIDTH_G=290, FWFT, sync, block RAM. + --------------------------------------------------------------------------- + U_DataStreamOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 290, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => dsOutQWrEn, + din => dsOutQDin, + full => dsOutQFull, + not_full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => dataStreamOutRdEn, + dout => dataStreamOutData, + valid => dataStreamOutValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, clearAllI, + headerMetaPipeInValid, headerMetaPipeInData, + headerPipeInValid, headerPipeInData, + dataPipeInValid, dataPipeInData, + dsOutQFull) is + variable v : RegType; + + -- popHeaderMetaData locals + variable hmdFragNum : slv(1 downto 0); + variable hmdValidByteN : slv(5 downto 0); + variable hmdValidBitN : slv(8 downto 0); + variable hmdInvalidByteN: slv(5 downto 0); + variable hmdInvalidBitN : slv(8 downto 0); + variable hmdHasPayload : sl; + variable hmdIsEmpty : sl; + + -- outputHeader locals + variable hFragIsLast : sl; + variable hFragIsFirst: sl; + variable hRsData : slv(255 downto 0); + variable hRsByteEn : slv(31 downto 0); + variable hFire : sl; + + -- outputData locals + variable dFragIsLast : sl; + variable dLastFragByteEn: slv(31 downto 0); + variable dNoExtraLast : sl; + variable dDataCat : slv(511 downto 0); + variable dByteEnCat : slv(63 downto 0); + variable dTmpData : slv(511 downto 0); + variable dTmpByteEn : slv(63 downto 0); + variable dOutDS : slv(289 downto 0); + + -- extraLastFrag locals + variable eLeftData : slv(255 downto 0); + variable eLeftByteEn: slv(31 downto 0); + variable eExtraDS : slv(289 downto 0); + begin + v := r; + + -- default Mealy outputs (deasserted; overridden below per transition) + headerMetaPipeInRdEn <= '0'; + headerPipeInRdEn <= '0'; + dataPipeInRdEn <= '0'; + dsOutQWrEn <= '0'; + dsOutQDin <= (others => '0'); + + if clearAllI = '1' then + -- resetAndClear: FIFO flushed via fifoRst; stageReg forced to POP. + -- The mkRegU context registers are deliberately untouched (matches BSV; + -- rewritten by the next popHeaderMetaData before any read). + v.stageReg := HEADER_META_DATA_POP_S; + + else + + case r.stageReg is + + -- ============================================================ + -- HEADER_META_DATA_POP_S : popHeaderMetaData + -- implicit cond: headerMetaPipeInValid='1' (no enq, no notFull) + -- ============================================================ + when HEADER_META_DATA_POP_S => + if headerMetaPipeInValid = '1' then + -- HeaderMetaData slice (headerLen[16:10] used by sim assert only) + hmdFragNum := headerMetaPipeInData(9 downto 8); + hmdValidByteN := headerMetaPipeInData(7 downto 2); + hmdHasPayload := headerMetaPipeInData(1); + hmdIsEmpty := headerMetaPipeInData(0); + + -- calcFragBitNumAndByteNum(validByteNum): + -- validBitNum = zeroExtend(validByteNum) << 3 + -- invalidByteNum= DATA_BUS_BYTE_WIDTH - validByteNum + -- invalidBitNum = zeroExtend(invalidByteNum) << 3 + hmdValidBitN := hmdValidByteN & "000"; + hmdInvalidByteN := std_logic_vector( + to_unsigned(DATA_BUS_BYTE_WIDTH_C, 6) - unsigned(hmdValidByteN)); + hmdInvalidBitN := hmdInvalidByteN & "000"; + + headerMetaPipeInRdEn <= '1'; + + v.headerLastFragValidByteNumReg := hmdValidByteN; + v.headerLastFragValidBitNumReg := hmdValidBitN; + v.headerLastFragInvalidByteNumReg := hmdInvalidByteN; + v.headerLastFragInvalidBitNumReg := hmdInvalidBitN; + + if hmdIsEmpty = '1' then + v.headerFragCntReg := (others => '0'); + else + v.headerFragCntReg := std_logic_vector(unsigned(hmdFragNum) - 1); + end if; + + v.headerHasPayloadReg := hmdHasPayload; + v.isFirstReg := '1'; + + if hmdIsEmpty = '1' then + v.stageReg := DATA_OUTPUT_S; + else + v.stageReg := HEADER_OUTPUT_S; + end if; + end if; + + -- ============================================================ + -- HEADER_OUTPUT_S : outputHeader + -- implicit cond: headerPipeInValid='1'; the two enq'ing arms + -- (non-last frag, last-frag-no-payload) additionally need notFull. + -- The last-frag-with-payload arm does NO enq -> no notFull needed. + -- ============================================================ + when HEADER_OUTPUT_S => + hFragIsLast := headerPipeInData(0); + hFragIsFirst := headerPipeInData(1); + + hFire := '0'; + if headerPipeInValid = '1' then + if hFragIsLast = '1' and r.headerHasPayloadReg = '1' then + hFire := '1'; -- row 4: no enq + elsif dsOutQFull = '0' then + hFire := '1'; -- rows 3 / 5: enq + end if; + end if; + + if hFire = '1' then + headerPipeInRdEn <= '1'; + + if hFragIsLast = '0' then + -- row 3: non-last header fragment -> stream it out as-is + v.isFirstReg := '0'; + v.headerFragCntReg := std_logic_vector(unsigned(r.headerFragCntReg) - 1); + dsOutQWrEn <= '1'; + dsOutQDin <= headerPipeInData; -- raw frag + else + -- rows 4 / 5: last header fragment. Stash a right-shifted + -- residue into preDataStreamReg; isLast := !headerHasPayloadReg. + hRsData := std_logic_vector(shift_right( + unsigned(headerPipeInData(289 downto 34)), + to_integer(unsigned(r.headerLastFragInvalidBitNumReg)))); + hRsByteEn := std_logic_vector(shift_right( + unsigned(headerPipeInData(33 downto 2)), + to_integer(unsigned(r.headerLastFragInvalidByteNumReg)))); + + v.preDataStreamReg := hRsData -- data + & hRsByteEn -- byteEn + & hFragIsFirst -- isFirst + & (not r.headerHasPayloadReg); -- isLast + + if r.headerHasPayloadReg = '1' then + -- row 4: header has payload -> go merge it, no enq + v.stageReg := DATA_OUTPUT_S; + else + -- row 5: header has no payload -> emit raw last frag, done + v.stageReg := HEADER_META_DATA_POP_S; + dsOutQWrEn <= '1'; + dsOutQDin <= headerPipeInData; -- raw frag (NOT shifted) + end if; + end if; + end if; + + -- ============================================================ + -- DATA_OUTPUT_S : outputData + -- implicit cond: dataPipeInValid='1' AND dsOutQFull='0' (always enqs) + -- All register reads are OLD (r) values (BSV rule semantics). + -- ============================================================ + when DATA_OUTPUT_S => + if dataPipeInValid = '1' and dsOutQFull = '0' then + dFragIsLast := dataPipeInData(0); + + -- lastFragByteEn = truncate(frag.byteEn << invalidByteNum) + -- (Bit#(32) << keeps width 32; truncate is identity) + dLastFragByteEn := std_logic_vector(shift_left( + unsigned(dataPipeInData(33 downto 2)), + to_integer(unsigned(r.headerLastFragInvalidByteNumReg)))); + -- noExtraLastFrag = isZeroByteEn(lastFragByteEn) + if unsigned(dLastFragByteEn) = 0 then + dNoExtraLast := '1'; + else + dNoExtraLast := '0'; + end if; + + -- tmpData = ({preDataStreamReg.data, frag.data} >> validBitNum) + -- tmpByteEn = ({preDataStreamReg.byteEn,frag.byteEn}>> validByteNum) + -- BSV {MSB-operand, LSB-operand}: pre = high half, frag = low half + dDataCat := r.preDataStreamReg(289 downto 34) & dataPipeInData(289 downto 34); + dByteEnCat := r.preDataStreamReg(33 downto 2) & dataPipeInData(33 downto 2); + dTmpData := std_logic_vector(shift_right(unsigned(dDataCat), + to_integer(unsigned(r.headerLastFragValidBitNumReg)))); + dTmpByteEn := std_logic_vector(shift_right(unsigned(dByteEnCat), + to_integer(unsigned(r.headerLastFragValidByteNumReg)))); + + -- outDS: data/byteEn = truncate (low bits); isFirst = OLD + -- r.isFirstReg; isLast = frag.isLast AND noExtraLastFrag + dOutDS := dTmpData(255 downto 0) -- data [289:34] + & dTmpByteEn(31 downto 0) -- byteEn [33:2] + & r.isFirstReg -- isFirst [1] + & (dFragIsLast and dNoExtraLast); -- isLast [0] + + dataPipeInRdEn <= '1'; + dsOutQWrEn <= '1'; + dsOutQDin <= dOutDS; + + -- write-after-read: latch the raw frag and clear isFirst + v.preDataStreamReg := dataPipeInData; + v.isFirstReg := '0'; + + if dFragIsLast = '1' then + if dNoExtraLast = '1' then + v.stageReg := HEADER_META_DATA_POP_S; + else + v.stageReg := EXTRA_LAST_FRAG_OUTPUT_S; + end if; + end if; + end if; + + -- ============================================================ + -- EXTRA_LAST_FRAG_OUTPUT_S : extraLastFrag + -- implicit cond: dsOutQFull='0' (always enqs; no upstream read) + -- ============================================================ + when EXTRA_LAST_FRAG_OUTPUT_S => + if dsOutQFull = '0' then + -- leftShiftData = truncate(preDataStreamReg.data << invalidBitNum) + -- leftShiftByteEn= truncate(preDataStreamReg.byteEn<< invalidByteNum) + eLeftData := std_logic_vector(shift_left( + unsigned(r.preDataStreamReg(289 downto 34)), + to_integer(unsigned(r.headerLastFragInvalidBitNumReg)))); + eLeftByteEn := std_logic_vector(shift_left( + unsigned(r.preDataStreamReg(33 downto 2)), + to_integer(unsigned(r.headerLastFragInvalidByteNumReg)))); + + eExtraDS := eLeftData -- data [289:34] + & eLeftByteEn -- byteEn [33:2] + & '0' -- isFirst [1] + & '1'; -- isLast [0] + + dsOutQWrEn <= '1'; + dsOutQDin <= eExtraDS; + v.stageReg := HEADER_META_DATA_POP_S; + end if; + + end case; + + end if; + + -- Synchronous reset (stageReg = mkReg(HEADER_META_DATA_POP)) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + --------------------------------------------------------------------------- + -- Simulation-only assertions (BSV immAssert calls; no synthesizable effect). + -- popHeaderMetaData: when isEmptyHeader, validBitNum and validByteNum must + -- be zero; else headerLen must be non-zero. + -- outputHeader : on the last header fragment, headerFragCntReg must be 0. + --------------------------------------------------------------------------- + -- pragma translate_off + check : process (clk) is + begin + if rising_edge(clk) then + if rst = '0' and clearAllI = '0' then + if (r.stageReg = HEADER_META_DATA_POP_S and headerMetaPipeInValid = '1') then + if headerMetaPipeInData(0) = '1' then -- isEmptyHeader + assert unsigned(headerMetaPipeInData(7 downto 2)) = 0 + report "PrependHeader2PipeOut: lastFragValidByteNum must be 0 " + & "when isEmptyHeader" + severity error; + else + assert unsigned(headerMetaPipeInData(16 downto 10)) /= 0 + report "PrependHeader2PipeOut: headerLen must be non-zero " + & "when not isEmptyHeader" + severity error; + end if; + end if; + if (r.stageReg = HEADER_OUTPUT_S and headerPipeInValid = '1' + and headerPipeInData(0) = '1') then -- last header fragment + assert unsigned(r.headerFragCntReg) = 0 + report "PrependHeader2PipeOut: headerFragCntReg must be 0 on the " + & "last header fragment" + severity error; + end if; + end if; + end if; + end process check; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/Qp.vhd b/ethernet/RoCEv2/rtl/Qp.vhd new file mode 100644 index 0000000000..d440f05c0a --- /dev/null +++ b/ethernet/RoCEv2/rtl/Qp.vhd @@ -0,0 +1,1523 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Top-level Queue-Pair integration. mkQP is 95% a wiring container: it +-- instantiates the controller, the SQ and RQ datapaths, their payload +-- generators, DMA read/write controllers, DMA/perm server proxies and the two +-- RDMA packet meta+payload pipes, threads the shared controller context down +-- to every child, and re-exports a handful of child interfaces on the +-- QueuePair interface. The only genuine FSM state it owns is FOUR cancel +-- flags (mkReg(False)) driven by an error-flush / graceful-stop controller +-- (7 rules) that is inert in normal operation. +-- +-- Because the sequential state is tiny (4 sl flags) but the wiring is large, +-- this file is emitted as: SURF two-process FSM (comb/seq over a RegType with +-- the 4 flags) for the flush controller + Mealy method-strobes, PLUS a large +-- structural instantiation/port-map body for the child netlist (same pattern +-- as the sibling container SqQueuePair.vhd, OQ-EMIT-SQQP-01). +-- +-- Child entity instances (each separately emitted; module-variant resolution +-- below is from QueuePair.bsv's imports — it imports ONLY PayloadConAndGen, and +-- the module signatures take a CntrlStatus first arg, so mkDmaReadCntrl / +-- mkPayloadGenerator bind the ConAndGen variants, NOT the PayloadGen ones): +-- U_CntrlQp : work.CntrlQp (mkCntrlQP) +-- U_Sq : work.SqQueuePair (mkSQ) +-- U_Rq : work.Rq (mkRQ) +-- U_PayGenRq/Sq : work.PayloadGeneratorConAndGen(mkPayloadGenerator ×2) +-- U_DmaRdCntrlRq/Sq: work.DmaReadCntrlConAndGen (mkDmaReadCntrl ×2) +-- U_DmaWrCntrlRq/Sq: work.DmaWriteCntrl (mkDmaWriteCntrl ×2) +-- U_DmaRdProxyRq/Sq: work.ServerProxy (mkServerProxy, DmaRead) +-- U_DmaWrProxyRq/Sq: work.ServerProxy (mkServerProxy, DmaWrite) +-- U_PermProxyRq/Sq : work.ServerProxy (mkServerProxy, PermCheck) +-- U_ReqPktPipe : work.RdmaPktMetaDataAndPayloadPipe (mkRdmaPkt…Pipe) +-- U_RespPktPipe : work.RdmaPktMetaDataAndPayloadPipe (mkRdmaPkt…Pipe) +-- +-- SURF components instantiated DIRECTLY by this entity: +-- U_RecvReqQ : surf.Fifo (BSV recvReqQ <- mkSizedFIFOF(MAX_QP_WR), RecvReq) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- U_WorkReqQ : surf.Fifo (BSV workReqQ <- mkFIFOF, WorkReq) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- Both are FWFT (valid == notEmpty, dout == first) so toPipeOut lowers to +-- valid/dout/rd_en. clear() is lowered to a synchronous flush by OR-ing the +-- controller isReset LEVEL into the FIFO reset (OQ-FSM-QP-02 recommendation: +-- fifoRst <= rst or isReset). +-- +-- statusSQ / statusRQ export (OQ-EMIT-QP-01): the QueuePair interface exports +-- two CntrlStatus interfaces (statusSQ, statusRQ). In mkCntrlQP both share the +-- SAME comm sub-interface (Controller.bsv:954-975: interface comm = +-- getCntrlCommStatus for both), differing only in getTypeQP (sqTypeReg vs +-- rqTypeReg) and the constant isSQ (True vs False). To avoid duplicating ~30 +-- identical comm output ports, this entity exports ONE shared comm bundle +-- (comm*) plus statusGetTypeSq/statusGetTypeRq and the two constant isSQ flags. +-- A downstream consumer wires both statusSQ.comm and statusRQ.comm to the same +-- comm* ports. This is faithful to the hardware (single shared status) and is +-- documented in OQ-EMIT-QP-01. +-- +-- Composite word widths (traced from child port declarations already emitted): +-- RecvReq = 216 WorkReq = 601 ReqQP = 301 +-- RespQP = 274 DataStream = 290 WorkComp = 222 +-- RdmaPktMetaData = 649 DmaReadReq = 176 DmaReadResp = 383 +-- DmaWriteReq = 419 DmaWriteResp = 53 DmaReadCntrlReq = 198 +-- DmaReadCntrlResp= 385 PayloadGenReq = 199 PayloadGenResp = 2 +-- PermCheckReq = 267 MAX_QP_WR = 32 +-- +-- Open questions (out/04-vhdl/OPEN_QUESTIONS.md): OQ-EMIT-QP-01 (shared comm +-- export), OQ-EMIT-QP-02 (FIFO clear lowered to reset OR, from OQ-FSM-QP-02), +-- OQ-EMIT-QP-03 (dmaReadCntrl isSQ tied to a constant per context; the child +-- has no internal sink anyway — OQ-FSM-DRCCAG-02). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; + +entity Qp is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active-HIGH reset + RST_ASYNC_G : boolean := false; + -- Pruning generics (all true = full engine, identical to the verified + -- netlist). EN_TX_G=false removes the requester (SQ) subtree; EN_RX_G= + -- false removes the responder (RQ) subtree (ACK/NAK reception lives on + -- the SQ side and is NOT affected); EN_READ_G=false removes RDMA READ / + -- atomic support on both sides. Pruned-side ports are tied inert: + -- user-facing inputs refuse (ready='0'), wire-side pipes drain + -- (ready='1'), outputs quiesce (valid='0'). + EN_TX_G : boolean := true; + EN_RX_G : boolean := true; + EN_READ_G : boolean := true); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; -- FPGA async/sync reset + + ----------------------------------------------------------------------- + -- srvPortQP = cntrl.srvPort : Server#(ReqQP(301b), RespQP(274b)) + ----------------------------------------------------------------------- + srvPortReqValid : in sl; + srvPortReqData : in slv(300 downto 0); + srvPortReqReady : out sl; + srvPortRespValid : out sl; + srvPortRespData : out slv(273 downto 0); + srvPortRespReady : in sl; + + ----------------------------------------------------------------------- + -- recvReqIn = toPut(recvReqQ) : Put#(RecvReq(216b)) + -- workReqIn = toPut(workReqQ) : Put#(WorkReq(601b)) + ----------------------------------------------------------------------- + recvReqInValid : in sl; + recvReqInData : in slv(215 downto 0); + recvReqInReady : out sl; -- = recvReqQ.not_full + workReqInValid : in sl; + workReqInData : in slv(600 downto 0); + workReqInReady : out sl; -- = workReqQ.not_full + + ----------------------------------------------------------------------- + -- dmaReadClt4RQ / dmaReadClt4SQ : Client#(DmaReadReq(176b), DmaReadResp(383b)) + -- dmaWriteClt4RQ / dmaWriteClt4SQ: Client#(DmaWriteReq(419b), DmaWriteResp(53b)) + -- (each = a mkServerProxy cltPort) + ----------------------------------------------------------------------- + dmaReadClt4RqReqValid : out sl; + dmaReadClt4RqReqData : out slv(175 downto 0); + dmaReadClt4RqReqReady : in sl; + dmaReadClt4RqRespValid : in sl; + dmaReadClt4RqRespData : in slv(382 downto 0); + dmaReadClt4RqRespReady : out sl; + dmaWriteClt4RqReqValid : out sl; + dmaWriteClt4RqReqData : out slv(418 downto 0); + dmaWriteClt4RqReqReady : in sl; + dmaWriteClt4RqRespValid : in sl; + dmaWriteClt4RqRespData : in slv(52 downto 0); + dmaWriteClt4RqRespReady : out sl; + dmaReadClt4SqReqValid : out sl; + dmaReadClt4SqReqData : out slv(175 downto 0); + dmaReadClt4SqReqReady : in sl; + dmaReadClt4SqRespValid : in sl; + dmaReadClt4SqRespData : in slv(382 downto 0); + dmaReadClt4SqRespReady : out sl; + dmaWriteClt4SqReqValid : out sl; + dmaWriteClt4SqReqData : out slv(418 downto 0); + dmaWriteClt4SqReqReady : in sl; + dmaWriteClt4SqRespValid : in sl; + dmaWriteClt4SqRespData : in slv(52 downto 0); + dmaWriteClt4SqRespReady : out sl; + + ----------------------------------------------------------------------- + -- permCheckClt4RQ / permCheckClt4SQ : Client#(PermCheckReq(267b), Bool) + ----------------------------------------------------------------------- + permCheckClt4RqReqValid : out sl; + permCheckClt4RqReqData : out slv(266 downto 0); + permCheckClt4RqReqReady : in sl; + permCheckClt4RqRespValid : in sl; + permCheckClt4RqRespData : in sl; + permCheckClt4RqRespReady : out sl; + permCheckClt4SqReqValid : out sl; + permCheckClt4SqReqData : out slv(266 downto 0); + permCheckClt4SqReqReady : in sl; + permCheckClt4SqRespValid : in sl; + permCheckClt4SqRespData : in sl; + permCheckClt4SqRespReady : out sl; + + ----------------------------------------------------------------------- + -- reqPktPipeIn / respPktPipeIn : RdmaPktMetaDataAndPayloadPipeIn + -- .pktMetaData.put (RdmaPktMetaData 649b) + .payload.put (DataStream 290b) + ----------------------------------------------------------------------- + reqPktMetaWrEn : in sl; + reqPktMetaData : in slv(648 downto 0); + reqPktMetaReady : out sl; + reqPktPayloadWrEn : in sl; + reqPktPayloadData : in slv(289 downto 0); + reqPktPayloadReady : out sl; + respPktMetaWrEn : in sl; + respPktMetaData : in slv(648 downto 0); + respPktMetaReady : out sl; + respPktPayloadWrEn : in sl; + respPktPayloadData : in slv(289 downto 0); + respPktPayloadReady : out sl; + + ----------------------------------------------------------------------- + -- statusSQ / statusRQ export : shared CntrlCommStatus bundle (comm*) plus + -- per-context getTypeQP and the constant isSQ (OQ-EMIT-QP-01). + ----------------------------------------------------------------------- + commIsCreate : out sl; + commIsErr : out sl; + commIsInit : out sl; + commIsNonErr : out sl; + commIsReset : out sl; + commIsRTR : out sl; + commIsRTS : out sl; + commIsSQD : out sl; + commIsUnknown : out sl; + commIsRTR2RTS : out sl; + commIsStableRTS : out sl; + commGetAccessFlags : out slv(7 downto 0); + commGetMaxRnrCnt : out slv(2 downto 0); + commGetMaxRetryCnt : out slv(2 downto 0); + commGetMinRnrTimer : out slv(4 downto 0); + commGetMaxTimeOut : out slv(4 downto 0); + commGetPendingWorkReqNum : out slv(7 downto 0); + commGetPendingRecvReqNum : out slv(7 downto 0); + commGetPendingReadAtomicReqNum : out slv(7 downto 0); + commGetPendingDestReadAtomicReqNum : out slv(7 downto 0); + commGetSigAll : out sl; + commGetSQPN : out slv(23 downto 0); + commGetDQPN : out slv(23 downto 0); + commGetPKEY : out slv(15 downto 0); + commGetQKEY : out slv(31 downto 0); + commGetPMTU : out slv(2 downto 0); + statusGetTypeSq : out slv(3 downto 0); + statusGetTypeRq : out slv(3 downto 0); + statusSqIsSQ : out sl; + statusRqIsSQ : out sl; + + ----------------------------------------------------------------------- + -- rdmaReqPipeOut = sq.rdmaReqDataStreamPipeOut (DataStream 290b) + -- rdmaRespPipeOut = rq.rdmaRespDataStreamPipeOut (DataStream 290b) + -- workCompPipeOutRQ = rq.workCompRQ.workCompPipeOut (WorkComp 222b) + -- workCompPipeOutSQ = sq.workCompSQ.workCompPipeOut (WorkComp 222b) + ----------------------------------------------------------------------- + rdmaReqValid : out sl; + rdmaReqData : out slv(289 downto 0); + rdmaReqRdEn : in sl; + rdmaRespValid : out sl; + rdmaRespData : out slv(289 downto 0); + rdmaRespRdEn : in sl; + workCompRqValid : out sl; + workCompRqData : out slv(221 downto 0); + workCompRqRdEn : in sl; + workCompSqValid : out sl; + workCompSqData : out slv(221 downto 0); + workCompSqRdEn : in sl); +end entity Qp; + +architecture rtl of Qp is + + ----------------------------------------------------------------------------- + -- Word widths (traced from already-emitted child ports) + ----------------------------------------------------------------------------- + constant RECV_REQ_C : positive := 216; + constant WORK_REQ_C : positive := 601; + constant DATA_STREAM_C : positive := 290; + constant RDMA_META_C : positive := 649; + constant DMA_READ_REQ_C : positive := 176; + constant DMA_READ_RESP_C : positive := 383; + constant DMA_WRITE_REQ_C : positive := 419; + constant DMA_WRITE_RESP_C : positive := 53; + constant PERM_CHECK_REQ_C : positive := 267; + -- recvReqQ = mkSizedFIFOF(MAX_QP_WR=32) -> 2**5; workReqQ = mkFIFOF -> min depth + constant RECV_REQ_AW_C : positive := 5; -- 2**5 = 32 = MAX_QP_WR + constant WORK_REQ_AW_C : positive := 4; -- min surf.Fifo depth (BSV mkFIFOF) + + ----------------------------------------------------------------------------- + -- FSM state : the four DMA-cancel flags (mkReg(False)) + ----------------------------------------------------------------------------- + type RegType is record + rqDmaReadCancelReg : sl; + sqDmaReadCancelReg : sl; + rqDmaWriteCancelReg : sl; + sqDmaWriteCancelReg : sl; + end record RegType; + + constant REG_INIT_C : RegType := ( + rqDmaReadCancelReg => '0', + sqDmaReadCancelReg => '0', + rqDmaWriteCancelReg => '0', + sqDmaWriteCancelReg => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Mealy method-strobes (combinational, driven by the comb process) + signal setStateErrStrobe : sl; -- errTrigger -> cntrl.setStateErr + signal errFlushDoneStrobe : sl; -- waitGracefulStop -> cntrl.errFlushDone + signal cancelReadRq : sl; -- cancelDmaReadRQ -> dmaReadCntrl4RQ.cancel + signal cancelReadSq : sl; -- cancelDmaReadSQ -> dmaReadCntrl4SQ.cancel + signal cancelWriteRq : sl; -- cancelDmaWriteRQ -> dmaWriteCntrl4RQ.cancel + signal cancelWriteSq : sl; -- cancelDmaWriteSQ -> dmaWriteCntrl4SQ.cancel + signal reqPipeClr : sl; -- resetAndClear -> reqPktPipe.clear + signal respPipeClr : sl; -- resetAndClear -> respPktPipe.clear + signal fifoClr : sl; -- resetAndClear -> recvReqQ/workReqQ clear + + ----------------------------------------------------------------------------- + -- Controller (U_CntrlQp) status/context outputs (shared, fanned to children + -- and re-exported on statusSQ/statusRQ). + ----------------------------------------------------------------------------- + signal cIsCreate : sl; + signal cIsErr : sl; + signal cIsInit : sl; + signal cIsNonErr : sl; + signal cIsReset : sl; + signal cIsRtr : sl; + signal cIsRts : sl; + signal cIsSqd : sl; + signal cIsUnknown : sl; + signal cIsRtr2Rts : sl; + signal cIsStableRts : sl; + signal cAccessFlags : slv(7 downto 0); + signal cMaxRnrCnt : slv(2 downto 0); + signal cMaxRetryCnt : slv(2 downto 0); + signal cMaxTimeOut : slv(4 downto 0); + signal cMinRnrTimer : slv(4 downto 0); + signal cPendingWorkReqNum : slv(7 downto 0); + signal cPendingRecvReqNum : slv(7 downto 0); + signal cPendingReadAtomicReqNum : slv(7 downto 0); + signal cPendingDestReadAtomicReqNum : slv(7 downto 0); + signal cSigAll : sl; + signal cSqpn : slv(23 downto 0); + signal cDqpn : slv(23 downto 0); + signal cPkey : slv(15 downto 0); + signal cQkey : slv(31 downto 0); + signal cPmtu : slv(2 downto 0); + signal cTypeSq : slv(3 downto 0); + signal cTypeRq : slv(3 downto 0); + -- contextSQ shared next-PSN register + signal cGetNpsn : slv(23 downto 0); + signal sqSetNpsnEn : sl; + signal sqSetNpsn : slv(23 downto 0); + -- contextRQ RMW registers (cntrl get* out; rq set*/restore in) + signal cPermCheckReq : slv(266 downto 0); + signal cTotalDmaWriteLen : slv(31 downto 0); + signal cRemainingDmaWriteLen: slv(31 downto 0); + signal cNextDmaWriteAddr : slv(63 downto 0); + signal cSendWriteReqPktNum : slv(24 downto 0); + signal cPreReqOpCode : slv(4 downto 0); + signal cEpoch : sl; + signal cMsn : slv(23 downto 0); + signal cIsRespPktNumZero : sl; + signal cRespPktNum : slv(24 downto 0); + signal cCurRespPSN : slv(23 downto 0); + signal cEpsn : slv(23 downto 0); + + ----------------------------------------------------------------------------- + -- U_Rq -> U_CntrlQp contextRQ write-backs / restore + ----------------------------------------------------------------------------- + signal rqIncEpoch : sl; + signal rqSetRespPktNumValid : sl; + signal rqSetRespPktNumData : slv(24 downto 0); + signal rqSetEPSNValid : sl; + signal rqSetEPSNData : slv(23 downto 0); + signal rqSetPreReqOpCodeValid : sl; + signal rqSetPreReqOpCodeData : slv(4 downto 0); + signal rqRestoreValid : sl; + signal rqRestorePreOpCodeData : slv(4 downto 0); + signal rqRestorePsnData : slv(23 downto 0); + signal rqSetPermCheckReqValid : sl; + signal rqSetPermCheckReqData : slv(266 downto 0); + signal rqSetNextDmaWriteAddrValid : sl; + signal rqSetNextDmaWriteAddrData : slv(63 downto 0); + signal rqSetSendWriteReqPktNumValid: sl; + signal rqSetSendWriteReqPktNumData : slv(24 downto 0); + signal rqSetRemainingDmaWriteLenValid : sl; + signal rqSetRemainingDmaWriteLenData : slv(31 downto 0); + signal rqSetTotalDmaWriteLenValid : sl; + signal rqSetTotalDmaWriteLenData : slv(31 downto 0); + signal rqSetCurRespPSNValid : sl; + signal rqSetCurRespPSNData : slv(23 downto 0); + signal rqSetMSNValid : sl; + signal rqSetMSNData : slv(23 downto 0); + + ----------------------------------------------------------------------------- + -- Payload generators (PayloadGeneratorConAndGen) <-> Rq / Sq / DmaReadCntrl + ----------------------------------------------------------------------------- + -- payloadGenerator4RQ + signal pgRqReqValid : sl; -- rq -> pg srvPort.request + signal pgRqReqData : slv(198 downto 0); + signal pgRqReqReady : sl; + signal pgRqRespValid : sl; -- pg -> rq srvPort.response + signal pgRqRespData : slv(1 downto 0); + signal pgRqRespReady : sl; + signal pgRqDataValid : sl; -- pg payloadDataStreamPipeOut -> rq + signal pgRqDataData : slv(289 downto 0); + signal pgRqDataDeq : sl; + signal pgRqNotEmpty : sl; -- pg.payloadNotEmpty (-> FSM) + signal pgRqDmaReqValid : sl; -- pg -> dmaReadCntrl4RQ.request + signal pgRqDmaReqData : slv(197 downto 0); + signal pgRqDmaReqReady : sl; + signal pgRqDmaRespValid: sl; -- dmaReadCntrl4RQ.response -> pg + signal pgRqDmaRespData : slv(384 downto 0); + signal pgRqDmaRespReady: sl; + -- payloadGenerator4SQ + signal pgSqReqValid : sl; + signal pgSqReqData : slv(198 downto 0); + signal pgSqReqReady : sl; + signal pgSqRespValid : sl; + signal pgSqRespData : slv(1 downto 0); + signal pgSqRespReady : sl; + signal pgSqDataValid : sl; + signal pgSqDataData : slv(289 downto 0); + signal pgSqDataDeq : sl; + signal pgSqNotEmpty : sl; + signal pgSqDmaReqValid : sl; + signal pgSqDmaReqData : slv(197 downto 0); + signal pgSqDmaReqReady : sl; + signal pgSqDmaRespValid: sl; + signal pgSqDmaRespData : slv(384 downto 0); + signal pgSqDmaRespReady: sl; + + ----------------------------------------------------------------------------- + -- DMA read/write controllers <-> server proxies (dmaReadSrv/dmaWriteSrv client) + ----------------------------------------------------------------------------- + -- dmaReadCntrl4RQ dmaReadSrv client -> dmaReadProxy4RQ.srvPort + signal drRqDmaReqValid : sl; + signal drRqDmaReqData : slv(DMA_READ_REQ_C-1 downto 0); + signal drRqDmaReqReady : sl; + signal drRqDmaRespValid: sl; + signal drRqDmaRespData : slv(DMA_READ_RESP_C-1 downto 0); + signal drRqDmaRespReady: sl; + signal drRqIsIdle : sl; + -- dmaReadCntrl4SQ + signal drSqDmaReqValid : sl; + signal drSqDmaReqData : slv(DMA_READ_REQ_C-1 downto 0); + signal drSqDmaReqReady : sl; + signal drSqDmaRespValid: sl; + signal drSqDmaRespData : slv(DMA_READ_RESP_C-1 downto 0); + signal drSqDmaRespReady: sl; + signal drSqIsIdle : sl; + -- dmaWriteCntrl4RQ srvPort.request (from rq) + dmaWriteSrv client -> proxy + signal dwRqReqValid : sl; -- rq -> dmaWriteCntrl4RQ.request + signal dwRqReqData : slv(DMA_WRITE_REQ_C-1 downto 0); + signal dwRqReqReady : sl; + signal dwRqRespValid : sl; -- dmaWriteCntrl4RQ.response -> rq + signal dwRqRespData : slv(DMA_WRITE_RESP_C-1 downto 0); + signal dwRqRespReady : sl; + signal dwRqDmaReqValid : sl; -- dmaWriteCntrl4RQ -> proxy + signal dwRqDmaReqData : slv(DMA_WRITE_REQ_C-1 downto 0); + signal dwRqDmaReqReady : sl; + signal dwRqDmaRespValid: sl; -- proxy -> dmaWriteCntrl4RQ + signal dwRqDmaRespData : slv(DMA_WRITE_RESP_C-1 downto 0); + signal dwRqDmaRespReady: sl; + signal dwRqIsIdle : sl; + -- dmaWriteCntrl4SQ srvPort.request (from sq) + dmaWriteSrv client -> proxy + signal dwSqReqValid : sl; -- sq -> dmaWriteCntrl4SQ.request + signal dwSqReqData : slv(DMA_WRITE_REQ_C-1 downto 0); + signal dwSqReqReady : sl; + signal dwSqRespValid : sl; -- dmaWriteCntrl4SQ.response -> sq + signal dwSqRespData : slv(DMA_WRITE_RESP_C-1 downto 0); + signal dwSqRespReady : sl; + signal dwSqDmaReqValid : sl; + signal dwSqDmaReqData : slv(DMA_WRITE_REQ_C-1 downto 0); + signal dwSqDmaReqReady : sl; + signal dwSqDmaRespValid: sl; + signal dwSqDmaRespData : slv(DMA_WRITE_RESP_C-1 downto 0); + signal dwSqDmaRespReady: sl; + signal dwSqIsIdle : sl; + + ----------------------------------------------------------------------------- + -- Perm-check server clients (rq / sq) -> perm proxies + ----------------------------------------------------------------------------- + signal rqPermReqValid : sl; + signal rqPermReqData : slv(PERM_CHECK_REQ_C-1 downto 0); + signal rqPermReqReady : sl; + signal rqPermRespValid : sl; + signal rqPermRespData : sl; + signal rqPermRespReady : sl; + signal sqPermReqValid : sl; + signal sqPermReqData : slv(PERM_CHECK_REQ_C-1 downto 0); + signal sqPermReqReady : sl; + signal sqPermRespValid : sl; + signal sqPermRespData : sl; + signal sqPermRespReady : sl; + + ----------------------------------------------------------------------------- + -- Packet pipes (reqPktPipe -> rq, respPktPipe -> sq) read side + ----------------------------------------------------------------------------- + signal reqPipeMetaValid : sl; + signal reqPipeMetaData : slv(RDMA_META_C-1 downto 0); + signal reqPipeMetaRdEn : sl; + signal reqPipePayloadValid : sl; + signal reqPipePayloadData : slv(DATA_STREAM_C-1 downto 0); + signal reqPipePayloadRdEn : sl; + signal respPipeMetaValid : sl; + signal respPipeMetaData : slv(RDMA_META_C-1 downto 0); + signal respPipeMetaRdEn : sl; + signal respPipePayloadValid : sl; + signal respPipePayloadData : slv(DATA_STREAM_C-1 downto 0); + signal respPipePayloadRdEn : sl; + + ----------------------------------------------------------------------------- + -- Input FIFOs (surf.Fifo) read side + reset + ----------------------------------------------------------------------------- + signal recvReqRst : sl; + signal recvReqValid : sl; -- = not empty (FWFT) + signal recvReqDout : slv(RECV_REQ_C-1 downto 0); + signal recvReqRdEn : sl; + signal workReqRst : sl; + signal workReqValid : sl; + signal workReqDout : slv(WORK_REQ_C-1 downto 0); + signal workReqRdEn : sl; + + ----------------------------------------------------------------------------- + -- Sq / Rq status/method outputs consumed by the flush FSM + ----------------------------------------------------------------------------- + signal rqWorkCompHasErr : sl; + signal sqWorkCompHasErr : sl; + signal rqRespHeaderNotEmpty: sl; -- rq.respHeaderOutNotEmpty + signal sqReqHeaderNotEmpty : sl; -- sq.reqHeaderOutNotEmpty + signal sqPendingNotEmpty : sl; -- sq.pendingWorkReqNotEmpty + +begin + + ----------------------------------------------------------------------------- + -- statusSQ / statusRQ export (shared comm; per-context type + isSQ) + ----------------------------------------------------------------------------- + commIsCreate <= cIsCreate; + commIsErr <= cIsErr; + commIsInit <= cIsInit; + commIsNonErr <= cIsNonErr; + commIsReset <= cIsReset; + commIsRTR <= cIsRtr; + commIsRTS <= cIsRts; + commIsSQD <= cIsSqd; + commIsUnknown <= cIsUnknown; + commIsRTR2RTS <= cIsRtr2Rts; + commIsStableRTS <= cIsStableRts; + commGetAccessFlags <= cAccessFlags; + commGetMaxRnrCnt <= cMaxRnrCnt; + commGetMaxRetryCnt <= cMaxRetryCnt; + commGetMinRnrTimer <= cMinRnrTimer; + commGetMaxTimeOut <= cMaxTimeOut; + commGetPendingWorkReqNum <= cPendingWorkReqNum; + commGetPendingRecvReqNum <= cPendingRecvReqNum; + commGetPendingReadAtomicReqNum <= cPendingReadAtomicReqNum; + commGetPendingDestReadAtomicReqNum <= cPendingDestReadAtomicReqNum; + commGetSigAll <= cSigAll; + commGetSQPN <= cSqpn; + commGetDQPN <= cDqpn; + commGetPKEY <= cPkey; + commGetQKEY <= cQkey; + commGetPMTU <= cPmtu; + statusGetTypeSq <= cTypeSq; + statusGetTypeRq <= cTypeRq; + statusSqIsSQ <= '1'; -- CntrlStatus.isSQ (statusSQ) + statusRqIsSQ <= '0'; -- CntrlStatus.isSQ (statusRQ) + + ----------------------------------------------------------------------------- + -- Input-FIFO clear() lowered to a synchronous flush (OQ-EMIT-QP-02): OR the + -- controller isReset LEVEL into the surf.Fifo reset while a QP soft-reset is + -- held (resetAndClear -> recvReqQ.clear / workReqQ.clear). + ----------------------------------------------------------------------------- + recvReqRst <= rst or fifoClr; + workReqRst <= rst or fifoClr; + + ----------------------------------------------------------------------------- + -- Error-flush / graceful-stop FSM (mkQP rules resetAndClear, errTrigger, + -- cancelDmaRead/Write RQ/SQ, waitGracefulStop). Two-process comb/seq over + -- the four cancel flags; every method call is a Mealy strobe. The three + -- controller phases (isReset / isNonErr / isERR) are mutually exclusive, so + -- they lower to an if/elsif on the shared comm status. + ----------------------------------------------------------------------------- + comb : process (r, cIsReset, cIsNonErr, cIsErr, rqWorkCompHasErr, + sqWorkCompHasErr, rqRespHeaderNotEmpty, pgRqNotEmpty, + sqReqHeaderNotEmpty, pgSqNotEmpty, recvReqValid, workReqValid, + sqPendingNotEmpty, drRqIsIdle, dwRqIsIdle, drSqIsIdle, + dwSqIsIdle) is + variable v : RegType; + begin + v := r; + + -- default: all Mealy strobes deasserted + setStateErrStrobe <= '0'; + errFlushDoneStrobe <= '0'; + cancelReadRq <= '0'; + cancelReadSq <= '0'; + cancelWriteRq <= '0'; + cancelWriteSq <= '0'; + reqPipeClr <= '0'; + respPipeClr <= '0'; + fifoClr <= '0'; + + if (cIsReset = '1') then + -- rule resetAndClear: flush both input FIFOs + both packet pipes and + -- clear all four cancel flags every cycle isReset is held. + fifoClr <= '1'; + reqPipeClr <= '1'; + respPipeClr <= '1'; + v.rqDmaReadCancelReg := '0'; + v.sqDmaReadCancelReg := '0'; + v.rqDmaWriteCancelReg := '0'; + v.sqDmaWriteCancelReg := '0'; + + elsif (cIsErr = '1') then + -- rule cancelDmaReadRQ: gated on !flag AND the RQ read/response path + -- being drained; fires once then latches. + if (r.rqDmaReadCancelReg = '0') and + not (rqRespHeaderNotEmpty = '1' and pgRqNotEmpty = '1') then + cancelReadRq <= '1'; + v.rqDmaReadCancelReg := '1'; + end if; + -- rule cancelDmaReadSQ + if (r.sqDmaReadCancelReg = '0') and + not (sqReqHeaderNotEmpty = '1' and pgSqNotEmpty = '1') then + cancelReadSq <= '1'; + v.sqDmaReadCancelReg := '1'; + end if; + -- rule cancelDmaWriteRQ: no flag guard -> re-asserts every isERR cycle. + cancelWriteRq <= '1'; + v.rqDmaWriteCancelReg := '1'; + -- rule cancelDmaWriteSQ + cancelWriteSq <= '1'; + v.sqDmaWriteCancelReg := '1'; + -- rule waitGracefulStop: reads the OLD (registered) flag values, so + -- write flags only satisfy this from the cycle AFTER they latch. + if (recvReqValid = '0') and (workReqValid = '0') and + (sqPendingNotEmpty = '0') and + (r.rqDmaReadCancelReg = '1') and (r.rqDmaWriteCancelReg = '1') and + (r.sqDmaReadCancelReg = '1') and (r.sqDmaWriteCancelReg = '1') and + (drRqIsIdle = '1') and (dwRqIsIdle = '1') and + (drSqIsIdle = '1') and (dwSqIsIdle = '1') then + errFlushDoneStrobe <= '1'; + end if; + + elsif (cIsNonErr = '1') then + -- rule errTrigger: request controller -> ERR on any child WorkComp error + if (rqWorkCompHasErr = '1') or (sqWorkCompHasErr = '1') then + setStateErrStrobe <= '1'; + end if; + end if; + + rin <= v; + end process comb; + + seq : process (clk, rst) is + begin + if (RST_ASYNC_G and rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + else + r <= rin after TPD_G; + end if; + end if; + end process seq; + + ----------------------------------------------------------------------------- + -- Pruning tie-offs. Each block drives ONLY signals that a kept process, + -- kept instance, or entity output still reads; signals whose producer AND + -- consumer are both pruned are left undriven (no reader). The flush FSM + -- inputs are tied to their "permanently drained/idle" values so the + -- graceful-stop condition is unaffected. + ----------------------------------------------------------------------------- + GEN_NO_TX : if not EN_TX_G generate + -- top ports + workReqInReady <= '0'; -- refuse work requests + respPktMetaReady <= '1'; -- drain resp pkt pipe write side + respPktPayloadReady <= '1'; + rdmaReqValid <= '0'; -- DataStreamArb slot 2i+1 idle + rdmaReqData <= (others => '0'); + workCompSqValid <= '0'; + workCompSqData <= (others => '0'); + dmaReadClt4SqReqValid <= '0'; + dmaReadClt4SqReqData <= (others => '0'); + dmaReadClt4SqRespReady <= '1'; + -- into U_CntrlQp (only Sq-driven context write) + sqSetNpsnEn <= '0'; + sqSetNpsn <= (others => '0'); + -- into flush FSM: SQ permanently drained/idle + sqWorkCompHasErr <= '0'; + sqReqHeaderNotEmpty <= '0'; + sqPendingNotEmpty <= '0'; + pgSqNotEmpty <= '0'; + drSqIsIdle <= '1'; + workReqValid <= '0'; + end generate GEN_NO_TX; + + GEN_NO_RX : if not EN_RX_G generate + -- top ports + recvReqInReady <= '0'; -- refuse recv requests + reqPktMetaReady <= '1'; -- drain req pkt pipe write side + reqPktPayloadReady <= '1'; + rdmaRespValid <= '0'; -- DataStreamArb slot 2i idle + rdmaRespData <= (others => '0'); + workCompRqValid <= '0'; + workCompRqData <= (others => '0'); + dmaWriteClt4RqReqValid <= '0'; + dmaWriteClt4RqReqData <= (others => '0'); + dmaWriteClt4RqRespReady <= '1'; + permCheckClt4RqReqValid <= '0'; + permCheckClt4RqReqData <= (others => '0'); + permCheckClt4RqRespReady <= '1'; + -- into U_CntrlQp (all Rq-driven contextRQ RMW writes) + rqRestoreValid <= '0'; + rqRestorePreOpCodeData <= (others => '0'); + rqRestorePsnData <= (others => '0'); + rqIncEpoch <= '0'; + rqSetPermCheckReqValid <= '0'; + rqSetPermCheckReqData <= (others => '0'); + rqSetTotalDmaWriteLenValid <= '0'; + rqSetTotalDmaWriteLenData <= (others => '0'); + rqSetRemainingDmaWriteLenValid <= '0'; + rqSetRemainingDmaWriteLenData <= (others => '0'); + rqSetNextDmaWriteAddrValid <= '0'; + rqSetNextDmaWriteAddrData <= (others => '0'); + rqSetSendWriteReqPktNumValid <= '0'; + rqSetSendWriteReqPktNumData <= (others => '0'); + rqSetPreReqOpCodeValid <= '0'; + rqSetPreReqOpCodeData <= (others => '0'); + rqSetMSNValid <= '0'; + rqSetMSNData <= (others => '0'); + rqSetRespPktNumValid <= '0'; + rqSetRespPktNumData <= (others => '0'); + rqSetCurRespPSNValid <= '0'; + rqSetCurRespPSNData <= (others => '0'); + rqSetEPSNValid <= '0'; + rqSetEPSNData <= (others => '0'); + -- into flush FSM: RQ permanently drained/idle + rqWorkCompHasErr <= '0'; + rqRespHeaderNotEmpty <= '0'; + dwRqIsIdle <= '1'; + recvReqValid <= '0'; + end generate GEN_NO_RX; + + -- READ-responder payload-fetch chain (U_DmaRdCntrlRq/U_PayGenRq/proxy) + GEN_NO_RQ_READ : if not (EN_RX_G and EN_READ_G) generate + dmaReadClt4RqReqValid <= '0'; + dmaReadClt4RqReqData <= (others => '0'); + dmaReadClt4RqRespReady <= '1'; + -- toward U_Rq (present when EN_RX_G; its forced classifiers guarantee + -- pgRqReqValid never asserts) + pgRqReqReady <= '1'; + pgRqRespValid <= '0'; + pgRqRespData <= (others => '0'); + pgRqDataValid <= '0'; + pgRqDataData <= (others => '0'); + -- into flush FSM + pgRqNotEmpty <= '0'; + drRqIsIdle <= '1'; + end generate GEN_NO_RQ_READ; + + -- Requester read-response landing chain (U_DmaWrCntrlSq/U_DmaWrProxySq) + -- plus the SQ perm check (only queried for read/atomic responses). + GEN_NO_SQ_READ : if not (EN_TX_G and EN_READ_G) generate + dmaWriteClt4SqReqValid <= '0'; + dmaWriteClt4SqReqData <= (others => '0'); + dmaWriteClt4SqRespReady <= '1'; + permCheckClt4SqReqValid <= '0'; + permCheckClt4SqReqData <= (others => '0'); + permCheckClt4SqRespReady <= '1'; + -- toward U_Sq (present when EN_TX_G) + dwSqReqReady <= '1'; + dwSqRespValid <= '0'; + dwSqRespData <= (others => '0'); + sqPermReqReady <= '1'; + sqPermRespValid <= '0'; + sqPermRespData <= '0'; + -- into flush FSM + dwSqIsIdle <= '1'; + end generate GEN_NO_SQ_READ; + + ----------------------------------------------------------------------------- + -- U_CntrlQp : cntrl (mkCntrlQP) — owns the shared context; srvPort = srvPortQP. + ----------------------------------------------------------------------------- + U_CntrlQp : entity surf.CntrlQp + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + -- srvPort = srvPortQP + srvReqValid => srvPortReqValid, + srvReqData => srvPortReqData, + srvReqReady => srvPortReqReady, + srvRespValid => srvPortRespValid, + srvRespData => srvPortRespData, + srvRespReady => srvPortRespReady, + -- restorePort <- rq.restore + restoreValid => rqRestoreValid, + restorePreOpCode => rqRestorePreOpCodeData, + restoreEpsn => rqRestorePsnData, + restoreReady => open, -- rq does not consume ready + -- error control <- flush FSM + setStateErr => setStateErrStrobe, + errFlushDoneIn => errFlushDoneStrobe, + inited => open, + -- comm status decodes + isCreate => cIsCreate, + isErr => cIsErr, + isInit => cIsInit, + isNonErr => cIsNonErr, + isReset => cIsReset, + isRTR => cIsRtr, + isRTS => cIsRts, + isSQD => cIsSqd, + isUnknown => cIsUnknown, + isRTR2RTS => cIsRtr2Rts, + isStableRTS => cIsStableRts, + -- comm getters + getAccessFlags => cAccessFlags, + getMaxRnrCnt => cMaxRnrCnt, + getMaxRetryCnt => cMaxRetryCnt, + getMaxTimeOut => cMaxTimeOut, + getMinRnrTimer => cMinRnrTimer, + getPendingWorkReqNum => cPendingWorkReqNum, + getPendingRecvReqNum => cPendingRecvReqNum, + getPendingReadAtomicReqNum => cPendingReadAtomicReqNum, + getPendingDestReadAtomicReqNum => cPendingDestReadAtomicReqNum, + getSigAll => cSigAll, + getSQPN => cSqpn, + getDQPN => cDqpn, + getPKEY => cPkey, + getQKEY => cQkey, + getPMTU => cPmtu, + getTypeSq => cTypeSq, + getTypeRq => cTypeRq, + -- contextSQ next-PSN (rq/sq: only sq uses it) + getNPSN => cGetNpsn, + setNPSNen => sqSetNpsnEn, + setNPSN => sqSetNpsn, + -- contextRQ RMW registers (<-> rq) + getPermCheckReq => cPermCheckReq, + setPermCheckReqEn => rqSetPermCheckReqValid, + setPermCheckReq => rqSetPermCheckReqData, + getTotalDmaWriteLen => cTotalDmaWriteLen, + setTotalDmaWriteLenEn => rqSetTotalDmaWriteLenValid, + setTotalDmaWriteLen => rqSetTotalDmaWriteLenData, + getRemainingDmaWriteLen => cRemainingDmaWriteLen, + setRemainingDmaWriteLenEn => rqSetRemainingDmaWriteLenValid, + setRemainingDmaWriteLen => rqSetRemainingDmaWriteLenData, + getNextDmaWriteAddr => cNextDmaWriteAddr, + setNextDmaWriteAddrEn => rqSetNextDmaWriteAddrValid, + setNextDmaWriteAddr => rqSetNextDmaWriteAddrData, + getSendWriteReqPktNum => cSendWriteReqPktNum, + setSendWriteReqPktNumEn => rqSetSendWriteReqPktNumValid, + setSendWriteReqPktNum => rqSetSendWriteReqPktNumData, + getPreReqOpCode => cPreReqOpCode, + setPreReqOpCodeEn => rqSetPreReqOpCodeValid, + setPreReqOpCode => rqSetPreReqOpCodeData, + getEpoch => cEpoch, + incEpochEn => rqIncEpoch, + getMSN => cMsn, + setMSNen => rqSetMSNValid, + setMSN => rqSetMSNData, + getIsRespPktNumZero => cIsRespPktNumZero, + getRespPktNum => cRespPktNum, + setRespPktNumEn => rqSetRespPktNumValid, + setRespPktNum => rqSetRespPktNumData, + getCurRespPSN => cCurRespPSN, + setCurRespPSNen => rqSetCurRespPSNValid, + setCurRespPSN => rqSetCurRespPSNData, + getEPSN => cEpsn, + setEPSNen => rqSetEPSNValid, + setEPSN => rqSetEPSNData); + + ----------------------------------------------------------------------------- + -- U_RecvReqQ : recvReqQ (surf.Fifo, FWFT) — mkSizedFIFOF(MAX_QP_WR), RecvReq. + -- Write side = recvReqIn (toPut); read side = recvReqBufPipeOut -> rq. + ----------------------------------------------------------------------------- + GEN_RECVREQ_Q : if EN_RX_G generate + U_RecvReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => RECV_REQ_C, + ADDR_WIDTH_G => RECV_REQ_AW_C) + port map ( + rst => recvReqRst, + wr_clk => clk, + wr_en => recvReqInValid, + din => recvReqInData, + not_full => recvReqInReady, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => recvReqRdEn, + dout => recvReqDout, + valid => recvReqValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + end generate GEN_RECVREQ_Q; + + ----------------------------------------------------------------------------- + -- U_WorkReqQ : workReqQ (surf.Fifo, FWFT) — mkFIFOF, WorkReq. + -- Write side = workReqIn (toPut); read side = workReqBufPipeOut -> sq. + ----------------------------------------------------------------------------- + GEN_WORKREQ_Q : if EN_TX_G generate + U_WorkReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => WORK_REQ_C, + ADDR_WIDTH_G => WORK_REQ_AW_C) + port map ( + rst => workReqRst, + wr_clk => clk, + wr_en => workReqInValid, + din => workReqInData, + not_full => workReqInReady, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => workReqRdEn, + dout => workReqDout, + valid => workReqValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + end generate GEN_WORKREQ_Q; + + ----------------------------------------------------------------------------- + -- U_ReqPktPipe : reqPktPipe (mkRdmaPktMetaDataAndPayloadPipe) + -- write side = reqPktPipeIn (top); read side (pktPipeOut) -> rq. + -- clear() = resetAndClear reqPktPipe.clear (level, isReset). + ----------------------------------------------------------------------------- + GEN_REQPKT_PIPE : if EN_RX_G generate + U_ReqPktPipe : entity surf.RdmaPktMetaDataAndPayloadPipe + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + clk => clk, + rst => rst, + clrEn_i => reqPipeClr, + -- write side <- reqPktPipeIn + metaWrEn_i => reqPktMetaWrEn, + metaDin_i => reqPktMetaData, + metaRdy_o => reqPktMetaReady, + payloadWrEn_i => reqPktPayloadWrEn, + payloadDin_i => reqPktPayloadData, + payloadRdy_o => reqPktPayloadReady, + -- read side -> rq + metaValid_o => reqPipeMetaValid, + metaDout_o => reqPipeMetaData, + metaRdEn_i => reqPipeMetaRdEn, + payloadValid_o => reqPipePayloadValid, + payloadDout_o => reqPipePayloadData, + payloadRdEn_i => reqPipePayloadRdEn); + end generate GEN_REQPKT_PIPE; + + ----------------------------------------------------------------------------- + -- U_RespPktPipe : respPktPipe (mkRdmaPktMetaDataAndPayloadPipe) + -- write side = respPktPipeIn (top); read side (pktPipeOut) -> sq. + ----------------------------------------------------------------------------- + GEN_RESPPKT_PIPE : if EN_TX_G generate + U_RespPktPipe : entity surf.RdmaPktMetaDataAndPayloadPipe + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G) + port map ( + clk => clk, + rst => rst, + clrEn_i => respPipeClr, + metaWrEn_i => respPktMetaWrEn, + metaDin_i => respPktMetaData, + metaRdy_o => respPktMetaReady, + payloadWrEn_i => respPktPayloadWrEn, + payloadDin_i => respPktPayloadData, + payloadRdy_o => respPktPayloadReady, + metaValid_o => respPipeMetaValid, + metaDout_o => respPipeMetaData, + metaRdEn_i => respPipeMetaRdEn, + payloadValid_o => respPipePayloadValid, + payloadDout_o => respPipePayloadData, + payloadRdEn_i => respPipePayloadRdEn); + end generate GEN_RESPPKT_PIPE; + + ----------------------------------------------------------------------------- + -- U_DmaRdCntrlRq : dmaReadCntrl4RQ (mkDmaReadCntrl(statusRQ, dmaReadProxy4RQ)) + -- srvPort <- payloadGenerator4RQ ; dmaReadSrv client -> dmaReadProxy4RQ. + ----------------------------------------------------------------------------- + GEN_DMARD_CNTRL_RQ : if EN_RX_G and EN_READ_G generate + U_DmaRdCntrlRq : entity surf.DmaReadCntrlConAndGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAll => cIsReset, + isSQ => '0', -- statusRQ.isSQ = False (no internal sink) + cancelEn => cancelReadRq, + -- srvPort.request <- payloadGenerator4RQ.dmaReadCntrl.request + reqInValid => pgRqDmaReqValid, + reqInData => pgRqDmaReqData, + reqInReady => pgRqDmaReqReady, + -- srvPort.response -> payloadGenerator4RQ.dmaReadCntrl.response + respOutReady => pgRqDmaRespReady, + respOutValid => pgRqDmaRespValid, + respOutData => pgRqDmaRespData, + -- dmaReadSrv client -> dmaReadProxy4RQ.srvPort + dmaReqValid => drRqDmaReqValid, + dmaReqOut => drRqDmaReqData, + dmaReqReady => drRqDmaReqReady, + dmaRespValid => drRqDmaRespValid, + dmaRespIn => drRqDmaRespData, + dmaRespReady => drRqDmaRespReady, + isIdle => drRqIsIdle); + end generate GEN_DMARD_CNTRL_RQ; + + ----------------------------------------------------------------------------- + -- U_DmaRdCntrlSq : dmaReadCntrl4SQ (mkDmaReadCntrl(statusSQ, dmaReadProxy4SQ)) + ----------------------------------------------------------------------------- + GEN_DMARD_CNTRL_SQ : if EN_TX_G generate + U_DmaRdCntrlSq : entity surf.DmaReadCntrlConAndGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAll => cIsReset, + isSQ => '1', -- statusSQ.isSQ = True (no internal sink) + cancelEn => cancelReadSq, + reqInValid => pgSqDmaReqValid, + reqInData => pgSqDmaReqData, + reqInReady => pgSqDmaReqReady, + respOutReady => pgSqDmaRespReady, + respOutValid => pgSqDmaRespValid, + respOutData => pgSqDmaRespData, + dmaReqValid => drSqDmaReqValid, + dmaReqOut => drSqDmaReqData, + dmaReqReady => drSqDmaReqReady, + dmaRespValid => drSqDmaRespValid, + dmaRespIn => drSqDmaRespData, + dmaRespReady => drSqDmaRespReady, + isIdle => drSqIsIdle); + end generate GEN_DMARD_CNTRL_SQ; + + ----------------------------------------------------------------------------- + -- U_DmaWrCntrlRq : dmaWriteCntrl4RQ (mkDmaWriteCntrl(statusRQ, dmaWriteProxy4RQ)) + -- srvPort <- rq (payloadConsumer) ; dmaWriteSrv client -> dmaWriteProxy4RQ. + ----------------------------------------------------------------------------- + GEN_DMAWR_CNTRL_RQ : if EN_RX_G generate + U_DmaWrCntrlRq : entity surf.DmaWriteCntrl + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAllI => cIsReset, + cancelEn => cancelWriteRq, + reqInValid => dwRqReqValid, + reqInData => dwRqReqData, + reqInReady => dwRqReqReady, + respOutReady => dwRqRespReady, + respOutValid => dwRqRespValid, + respOutData => dwRqRespData, + dmaReqValid => dwRqDmaReqValid, + dmaReqOut => dwRqDmaReqData, + dmaReqReady => dwRqDmaReqReady, + dmaRespValid => dwRqDmaRespValid, + dmaRespIn => dwRqDmaRespData, + dmaRespReady => dwRqDmaRespReady, + isIdle => dwRqIsIdle); + end generate GEN_DMAWR_CNTRL_RQ; + + ----------------------------------------------------------------------------- + -- U_DmaWrCntrlSq : dmaWriteCntrl4SQ (mkDmaWriteCntrl(statusSQ, dmaWriteProxy4SQ)) + -- srvPort <- sq ; dmaWriteSrv client -> dmaWriteProxy4SQ. + ----------------------------------------------------------------------------- + GEN_DMAWR_CNTRL_SQ : if EN_TX_G and EN_READ_G generate + U_DmaWrCntrlSq : entity surf.DmaWriteCntrl + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAllI => cIsReset, + cancelEn => cancelWriteSq, + reqInValid => dwSqReqValid, + reqInData => dwSqReqData, + reqInReady => dwSqReqReady, + respOutReady => dwSqRespReady, + respOutValid => dwSqRespValid, + respOutData => dwSqRespData, + dmaReqValid => dwSqDmaReqValid, + dmaReqOut => dwSqDmaReqData, + dmaReqReady => dwSqDmaReqReady, + dmaRespValid => dwSqDmaRespValid, + dmaRespIn => dwSqDmaRespData, + dmaRespReady => dwSqDmaRespReady, + isIdle => dwSqIsIdle); + end generate GEN_DMAWR_CNTRL_SQ; + + ----------------------------------------------------------------------------- + -- U_PayGenRq : payloadGenerator4RQ (mkPayloadGenerator(statusRQ, dmaReadCntrl4RQ)) + -- srvPort <-> rq ; dmaReadCntrl client -> U_DmaRdCntrlRq ; dataStream -> rq. + ----------------------------------------------------------------------------- + GEN_PAYGEN_RQ : if EN_RX_G and EN_READ_G generate + U_PayGenRq : entity surf.PayloadGeneratorConAndGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + isReset => cIsReset, + isNonErr => cIsNonErr, + isERR => cIsErr, + -- srvPort <-> rq + reqInValid => pgRqReqValid, + reqInData => pgRqReqData, + reqInReady => pgRqReqReady, + respOutReady => pgRqRespReady, + respOutValid => pgRqRespValid, + respOutData => pgRqRespData, + -- dmaReadCntrl client -> U_DmaRdCntrlRq.srvPort + dmaReadCntrlReqValid => pgRqDmaReqValid, + dmaReadCntrlReqData => pgRqDmaReqData, + dmaReadCntrlReqReady => pgRqDmaReqReady, + dmaReadCntrlRespValid => pgRqDmaRespValid, + dmaReadCntrlRespData => pgRqDmaRespData, + dmaReadCntrlRespReady => pgRqDmaRespReady, + -- payloadDataStreamPipeOut -> rq + payloadDataStreamDeq => pgRqDataDeq, + payloadDataStreamFirst => pgRqDataData, + payloadDataStreamNotEmpty => pgRqDataValid, + payloadNotEmpty => pgRqNotEmpty); + end generate GEN_PAYGEN_RQ; + + ----------------------------------------------------------------------------- + -- U_PayGenSq : payloadGenerator4SQ (mkPayloadGenerator(statusSQ, dmaReadCntrl4SQ)) + ----------------------------------------------------------------------------- + GEN_PAYGEN_SQ : if EN_TX_G generate + U_PayGenSq : entity surf.PayloadGeneratorConAndGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + isReset => cIsReset, + isNonErr => cIsNonErr, + isERR => cIsErr, + reqInValid => pgSqReqValid, + reqInData => pgSqReqData, + reqInReady => pgSqReqReady, + respOutReady => pgSqRespReady, + respOutValid => pgSqRespValid, + respOutData => pgSqRespData, + dmaReadCntrlReqValid => pgSqDmaReqValid, + dmaReadCntrlReqData => pgSqDmaReqData, + dmaReadCntrlReqReady => pgSqDmaReqReady, + dmaReadCntrlRespValid => pgSqDmaRespValid, + dmaReadCntrlRespData => pgSqDmaRespData, + dmaReadCntrlRespReady => pgSqDmaRespReady, + payloadDataStreamDeq => pgSqDataDeq, + payloadDataStreamFirst => pgSqDataData, + payloadDataStreamNotEmpty => pgSqDataValid, + payloadNotEmpty => pgSqNotEmpty); + end generate GEN_PAYGEN_SQ; + + ----------------------------------------------------------------------------- + -- U_DmaRdProxyRq : dmaReadProxy4RQ (mkServerProxy) — srvPort <- U_DmaRdCntrlRq, + -- cltPort -> dmaReadClt4RQ (top). + ----------------------------------------------------------------------------- + GEN_DMARD_PROXY_RQ : if EN_RX_G and EN_READ_G generate + U_DmaRdProxyRq : entity surf.ServerProxy + generic map ( + TPD_G => TPD_G, + REQ_WIDTH_G => DMA_READ_REQ_C, + RESP_WIDTH_G => DMA_READ_RESP_C) + port map ( + clk => clk, + rst => rst, + -- srvPort <- dmaReadCntrl4RQ client + srvReqValid => drRqDmaReqValid, + srvReqData => drRqDmaReqData, + srvReqReady => drRqDmaReqReady, + srvRespValid => drRqDmaRespValid, + srvRespData => drRqDmaRespData, + srvRespReady => drRqDmaRespReady, + -- cltPort -> top dmaReadClt4RQ + cltReqValid => dmaReadClt4RqReqValid, + cltReqData => dmaReadClt4RqReqData, + cltReqReady => dmaReadClt4RqReqReady, + cltRespValid => dmaReadClt4RqRespValid, + cltRespData => dmaReadClt4RqRespData, + cltRespReady => dmaReadClt4RqRespReady); + end generate GEN_DMARD_PROXY_RQ; + + ----------------------------------------------------------------------------- + -- U_DmaRdProxySq : dmaReadProxy4SQ + ----------------------------------------------------------------------------- + GEN_DMARD_PROXY_SQ : if EN_TX_G generate + U_DmaRdProxySq : entity surf.ServerProxy + generic map ( + TPD_G => TPD_G, + REQ_WIDTH_G => DMA_READ_REQ_C, + RESP_WIDTH_G => DMA_READ_RESP_C) + port map ( + clk => clk, + rst => rst, + srvReqValid => drSqDmaReqValid, + srvReqData => drSqDmaReqData, + srvReqReady => drSqDmaReqReady, + srvRespValid => drSqDmaRespValid, + srvRespData => drSqDmaRespData, + srvRespReady => drSqDmaRespReady, + cltReqValid => dmaReadClt4SqReqValid, + cltReqData => dmaReadClt4SqReqData, + cltReqReady => dmaReadClt4SqReqReady, + cltRespValid => dmaReadClt4SqRespValid, + cltRespData => dmaReadClt4SqRespData, + cltRespReady => dmaReadClt4SqRespReady); + end generate GEN_DMARD_PROXY_SQ; + + ----------------------------------------------------------------------------- + -- U_DmaWrProxyRq : dmaWriteProxy4RQ + ----------------------------------------------------------------------------- + GEN_DMAWR_PROXY_RQ : if EN_RX_G generate + U_DmaWrProxyRq : entity surf.ServerProxy + generic map ( + TPD_G => TPD_G, + REQ_WIDTH_G => DMA_WRITE_REQ_C, + RESP_WIDTH_G => DMA_WRITE_RESP_C) + port map ( + clk => clk, + rst => rst, + srvReqValid => dwRqDmaReqValid, + srvReqData => dwRqDmaReqData, + srvReqReady => dwRqDmaReqReady, + srvRespValid => dwRqDmaRespValid, + srvRespData => dwRqDmaRespData, + srvRespReady => dwRqDmaRespReady, + cltReqValid => dmaWriteClt4RqReqValid, + cltReqData => dmaWriteClt4RqReqData, + cltReqReady => dmaWriteClt4RqReqReady, + cltRespValid => dmaWriteClt4RqRespValid, + cltRespData => dmaWriteClt4RqRespData, + cltRespReady => dmaWriteClt4RqRespReady); + end generate GEN_DMAWR_PROXY_RQ; + + ----------------------------------------------------------------------------- + -- U_DmaWrProxySq : dmaWriteProxy4SQ + ----------------------------------------------------------------------------- + GEN_DMAWR_PROXY_SQ : if EN_TX_G and EN_READ_G generate + U_DmaWrProxySq : entity surf.ServerProxy + generic map ( + TPD_G => TPD_G, + REQ_WIDTH_G => DMA_WRITE_REQ_C, + RESP_WIDTH_G => DMA_WRITE_RESP_C) + port map ( + clk => clk, + rst => rst, + srvReqValid => dwSqDmaReqValid, + srvReqData => dwSqDmaReqData, + srvReqReady => dwSqDmaReqReady, + srvRespValid => dwSqDmaRespValid, + srvRespData => dwSqDmaRespData, + srvRespReady => dwSqDmaRespReady, + cltReqValid => dmaWriteClt4SqReqValid, + cltReqData => dmaWriteClt4SqReqData, + cltReqReady => dmaWriteClt4SqReqReady, + cltRespValid => dmaWriteClt4SqRespValid, + cltRespData => dmaWriteClt4SqRespData, + cltRespReady => dmaWriteClt4SqRespReady); + end generate GEN_DMAWR_PROXY_SQ; + + ----------------------------------------------------------------------------- + -- U_PermProxyRq : permCheckProxy4RQ (mkServerProxy) — srvPort <- rq, + -- cltPort -> permCheckClt4RQ (top). + ----------------------------------------------------------------------------- + GEN_PERM_PROXY_RQ : if EN_RX_G generate + U_PermProxyRq : entity surf.ServerProxy + generic map ( + TPD_G => TPD_G, + REQ_WIDTH_G => PERM_CHECK_REQ_C, + RESP_WIDTH_G => 1) + port map ( + clk => clk, + rst => rst, + srvReqValid => rqPermReqValid, + srvReqData => rqPermReqData, + srvReqReady => rqPermReqReady, + srvRespValid => rqPermRespValid, + srvRespData(0) => rqPermRespData, + srvRespReady => rqPermRespReady, + cltReqValid => permCheckClt4RqReqValid, + cltReqData => permCheckClt4RqReqData, + cltReqReady => permCheckClt4RqReqReady, + cltRespValid => permCheckClt4RqRespValid, + cltRespData(0) => permCheckClt4RqRespData, + cltRespReady => permCheckClt4RqRespReady); + end generate GEN_PERM_PROXY_RQ; + + ----------------------------------------------------------------------------- + -- U_PermProxySq : permCheckProxy4SQ — srvPort <- sq, cltPort -> permCheckClt4SQ. + ----------------------------------------------------------------------------- + GEN_PERM_PROXY_SQ : if EN_TX_G and EN_READ_G generate + U_PermProxySq : entity surf.ServerProxy + generic map ( + TPD_G => TPD_G, + REQ_WIDTH_G => PERM_CHECK_REQ_C, + RESP_WIDTH_G => 1) + port map ( + clk => clk, + rst => rst, + srvReqValid => sqPermReqValid, + srvReqData => sqPermReqData, + srvReqReady => sqPermReqReady, + srvRespValid => sqPermRespValid, + srvRespData(0) => sqPermRespData, + srvRespReady => sqPermRespReady, + cltReqValid => permCheckClt4SqReqValid, + cltReqData => permCheckClt4SqReqData, + cltReqReady => permCheckClt4SqReqReady, + cltRespValid => permCheckClt4SqRespValid, + cltRespData(0) => permCheckClt4SqRespData, + cltRespReady => permCheckClt4SqRespReady); + end generate GEN_PERM_PROXY_SQ; + + ----------------------------------------------------------------------------- + -- U_Rq : rq (mkRQ(contextRQ, payloadGenerator4RQ, dmaWriteCntrl4RQ, + -- permCheckProxy4RQ.srvPort, recvReqBufPipeOut, reqPktPipe.pktPipeOut)) + ----------------------------------------------------------------------------- + GEN_RQ : if EN_RX_G generate + U_Rq : entity surf.Rq + generic map ( + TPD_G => TPD_G, + EN_READ_G => EN_READ_G) + port map ( + clk => clk, + rst => rst, + -- contextRQ.statusRQ.comm status + isReset => cIsReset, + isNonErr => cIsNonErr, + isERR => cIsErr, + getTypeQP => cTypeRq, + getPMTU => cPmtu, + getPKEY => cPkey, + getSQPN => cSqpn, + getDQPN => cDqpn, + getMinRnrTimer => cMinRnrTimer, + getAccessFlags => cAccessFlags, + getPendingWorkReqNum => cPendingWorkReqNum, + getPendingDestReadAtomicReqNum => cPendingDestReadAtomicReqNum, + -- contextRQ shared registers (external RMW) + getEpoch => cEpoch, + incEpoch => rqIncEpoch, + getEPSN => cEpsn, + getRespPktNum => cRespPktNum, + setRespPktNumValid => rqSetRespPktNumValid, + setRespPktNumData => rqSetRespPktNumData, + getIsRespPktNumZero => cIsRespPktNumZero, + setEPSNValid => rqSetEPSNValid, + setEPSNData => rqSetEPSNData, + getPreReqOpCode => cPreReqOpCode, + setPreReqOpCodeValid => rqSetPreReqOpCodeValid, + setPreReqOpCodeData => rqSetPreReqOpCodeData, + restoreValid => rqRestoreValid, + restorePreOpCodeData => rqRestorePreOpCodeData, + restorePsnData => rqRestorePsnData, + getPermCheckReq => cPermCheckReq, + setPermCheckReqValid => rqSetPermCheckReqValid, + setPermCheckReqData => rqSetPermCheckReqData, + getNextDmaWriteAddr => cNextDmaWriteAddr, + setNextDmaWriteAddrValid => rqSetNextDmaWriteAddrValid, + setNextDmaWriteAddrData => rqSetNextDmaWriteAddrData, + getSendWriteReqPktNum => cSendWriteReqPktNum, + setSendWriteReqPktNumValid => rqSetSendWriteReqPktNumValid, + setSendWriteReqPktNumData => rqSetSendWriteReqPktNumData, + getRemainingDmaWriteLen => cRemainingDmaWriteLen, + setRemainingDmaWriteLenValid => rqSetRemainingDmaWriteLenValid, + setRemainingDmaWriteLenData => rqSetRemainingDmaWriteLenData, + getTotalDmaWriteLen => cTotalDmaWriteLen, + setTotalDmaWriteLenValid => rqSetTotalDmaWriteLenValid, + setTotalDmaWriteLenData => rqSetTotalDmaWriteLenData, + getCurRespPSN => cCurRespPSN, + setCurRespPSNValid => rqSetCurRespPSNValid, + setCurRespPSNData => rqSetCurRespPSNData, + getMSN => cMsn, + setMSNValid => rqSetMSNValid, + setMSNData => rqSetMSNData, + -- payloadGenerator (payloadGenerator4RQ) server + data stream + payloadGenReqValid => pgRqReqValid, + payloadGenReqData => pgRqReqData, + payloadGenReqReady => pgRqReqReady, + payloadGenRespValid => pgRqRespValid, + payloadGenRespData => pgRqRespData, + payloadGenRespGetEn => pgRqRespReady, + payloadDataStreamValid => pgRqDataValid, + payloadDataStreamData => pgRqDataData, + payloadDataStreamRdEn => pgRqDataDeq, + -- permCheckSrv (permCheckProxy4RQ.srvPort) + permReqValid => rqPermReqValid, + permReqData => rqPermReqData, + permReqReady => rqPermReqReady, + permRespValid => rqPermRespValid, + permRespData => rqPermRespData, + permRespGetEn => rqPermRespReady, + -- recvReqBuf (recvReqQ pipe out) + recvReqValid => recvReqValid, + recvReqData => recvReqDout, + recvReqDeq => recvReqRdEn, + -- reqPktPipeIn.pktMetaData + pktMetaValid => reqPipeMetaValid, + pktMetaData => reqPipeMetaData, + pktMetaDeq => reqPipeMetaRdEn, + -- reqPktPipeIn.payload + payloadPipeInValid => reqPipePayloadValid, + payloadPipeInData => reqPipePayloadData, + payloadPipeInReady => reqPipePayloadRdEn, + -- dmaWriteCntrl (dmaWriteCntrl4RQ) client + dmaWriteReqValid => dwRqReqValid, + dmaWriteReqData => dwRqReqData, + dmaWriteReqReady => dwRqReqReady, + dmaWriteRespValid => dwRqRespValid, + dmaWriteRespData => dwRqRespData, + dmaWriteRespReady => dwRqRespReady, + -- forwarded outputs + rdmaRespDataStreamValid => rdmaRespValid, + rdmaRespDataStreamData => rdmaRespData, + rdmaRespDataStreamRdEn => rdmaRespRdEn, + respHeaderOutNotEmpty => rqRespHeaderNotEmpty, + workCompValid => workCompRqValid, + workCompData => workCompRqData, + workCompRdEn => workCompRqRdEn, + workCompHasErr => rqWorkCompHasErr); + end generate GEN_RQ; + + ----------------------------------------------------------------------------- + -- U_Sq : sq (mkSQ(contextSQ, payloadGenerator4SQ, dmaWriteCntrl4SQ, + -- permCheckProxy4SQ.srvPort, workReqBufPipeOut, respPktPipe.pktPipeOut)) + ----------------------------------------------------------------------------- + GEN_SQ : if EN_TX_G generate + U_Sq : entity surf.SqQueuePair + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + EN_READ_G => EN_READ_G) + port map ( + clk => clk, + rst => rst, + -- contextSQ.statusSQ status bundle + isReset => cIsReset, + isNonErr => cIsNonErr, + isStableRTS => cIsStableRts, + isRTS => cIsRts, + isERR => cIsErr, + isSQD => cIsSqd, + isRTR2RTS => cIsRtr2Rts, + qpType => cTypeSq, + sqpn => cSqpn, + pmtu => cPmtu, + pkey => cPkey, + dqpn => cDqpn, + sigAll => cSigAll, + getMaxRetryCnt => cMaxRetryCnt, + getMaxRnrCnt => cMaxRnrCnt, + getMaxTimeOut => cMaxTimeOut, + getMinRnrTimer => cMinRnrTimer, + getPendingWorkReqNum => cPendingWorkReqNum, + -- contextSQ next-PSN register (RMW -> cntrl) + npsnIn => cGetNpsn, + npsnOut => sqSetNpsn, + npsnWrEn => sqSetNpsnEn, + -- payloadGenerator (payloadGenerator4SQ) server + data stream + payloadGenReqValid => pgSqReqValid, + payloadGenReqData => pgSqReqData, + payloadGenReqReady => pgSqReqReady, + payloadGenRespValid => pgSqRespValid, + payloadGenRespData => pgSqRespData, + payloadGenRespReady => pgSqRespReady, + payloadGenDataValid => pgSqDataValid, + payloadGenDataData => pgSqDataData, + payloadGenDataRdEn => pgSqDataDeq, + -- dmaWriteCntrl (dmaWriteCntrl4SQ) client + dmaWriteReqValid => dwSqReqValid, + dmaWriteReqData => dwSqReqData, + dmaWriteReqReady => dwSqReqReady, + dmaWriteRespValid => dwSqRespValid, + dmaWriteRespData => dwSqRespData, + dmaWriteRespReady => dwSqRespReady, + -- permCheckSrv (permCheckProxy4SQ.srvPort) + permReqValid => sqPermReqValid, + permReqData => sqPermReqData, + permReqReady => sqPermReqReady, + permRespValid => sqPermRespValid, + permRespData => sqPermRespData, + permRespGetEn => sqPermRespReady, + -- workReqPipeIn (workReqQ pipe out) + workReqInValid => workReqValid, + workReqInData => workReqDout, + workReqInRdEn => workReqRdEn, + -- respPktPipeOut (respPktPipe.pktPipeOut) + respPayloadValid => respPipePayloadValid, + respPayloadData => respPipePayloadData, + respPayloadRdEn => respPipePayloadRdEn, + respPktMetaValid => respPipeMetaValid, + respPktMetaData => respPipeMetaData, + respPktMetaRdEn => respPipeMetaRdEn, + -- SQ interface outputs + rdmaReqDataValid => rdmaReqValid, + rdmaReqDataData => rdmaReqData, + rdmaReqDataRdEn => rdmaReqRdEn, + workCompValid => workCompSqValid, + workCompData => workCompSqData, + workCompRdEn => workCompSqRdEn, + workCompHasErr => sqWorkCompHasErr, + reqHeaderOutNotEmpty => sqReqHeaderNotEmpty, + pendingWorkReqNotEmpty => sqPendingNotEmpty); + end generate GEN_SQ; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/RdmaPktMetaDataAndPayloadPipe.vhd b/ethernet/RoCEv2/rtl/RdmaPktMetaDataAndPayloadPipe.vhd new file mode 100644 index 0000000000..a82ad7a64f --- /dev/null +++ b/ethernet/RoCEv2/rtl/RdmaPktMetaDataAndPayloadPipe.vhd @@ -0,0 +1,142 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Pure structural wrapper: exposes a metadata FIFO (649-bit RdmaPktMetaData) +-- and a payload FIFO (290-bit DataStream) as an entity interface. No rules, +-- no local registers, no FSM. Instantiated twice inside mkQP: +-- reqPktPipe (incoming RQ packet pipe, written by TransportLayer) +-- respPktPipe (incoming SQ response packet pipe, written by TransportLayer) +-- +-- SURF components instantiated: +-- U_MetaDataQ : surf.Fifo (DATA_WIDTH_G=649, FWFT, sync) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- U_PayloadQ : surf.Fifo (DATA_WIDTH_G=290, FWFT, sync) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- +-- DataStream width resolution (OQ-FSM-H2DS-02, resolved Stage 4): +-- DataTypes.bsv:183-188: data(256) + byteEn(32) + isFirst(1) + isLast(1) +-- = 290 bits. The Stage-1 inventory value of 321 is incorrect; all +-- DataStream-carrying FIFOs in this project use DATA_WIDTH_G=290. +-- +-- FIFO clear (OQ-FSM-06 / OQ-FSM-NPWRPO-02, resolved in RESOLVED.md): +-- clrEn_i is a level, held HIGH for the full duration of QP reset by the +-- parent mkQP.resetAndClear rule (fire_when_enabled, no_implicit_conditions). +-- surf.FifoSync is level-sensitive on rst; holding it continuously pins +-- both FIFOs logically empty each cycle. No pulse-generator needed. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity RdmaPktMetaDataAndPayloadPipe is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- depth = 2**G entries per FIFO + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- clear() method: level-asserted for full duration of QP reset + clrEn_i : in sl := '0'; + -- Metadata FIFO — write side (pktPipeIn.pktMetaData.put) + metaWrEn_i : in sl := '0'; + metaDin_i : in slv(648 downto 0); -- RdmaPktMetaData, 649 bits + metaRdy_o : out sl; -- notFull (= write-side readiness) + -- Metadata FIFO — read side (pktPipeOut.pktMetaData.first / .deq) + metaValid_o : out sl; -- notEmpty + metaDout_o : out slv(648 downto 0); + metaRdEn_i : in sl := '0'; + -- Payload FIFO — write side (pktPipeIn.payload.put) + payloadWrEn_i : in sl := '0'; + payloadDin_i : in slv(289 downto 0); -- DataStream, 290 bits (resolved OQ-FSM-H2DS-02) + payloadRdy_o : out sl; -- notFull + -- Payload FIFO — read side (pktPipeOut.payload.first / .deq) + payloadValid_o : out sl; -- notEmpty + payloadDout_o : out slv(289 downto 0); + payloadRdEn_i : in sl := '0'); +end entity RdmaPktMetaDataAndPayloadPipe; + +architecture rtl of RdmaPktMetaDataAndPayloadPipe is + + -- Normalised active-high reset (for FIFO rst port, which is always active-high) + signal rstActiveHigh : sl; + -- Combined FIFO clear: global hardware reset OR BSV clear() method level + signal fifoRst : sl; + +begin + + rstActiveHigh <= rst when (RST_POLARITY_G = '1') else not rst; + + -- Level-clear: fifoRst held '1' for the full duration of clrEn_i='1'. + -- surf.FifoSync re-applies REG_INIT_C (empty state) every cycle rst is + -- asserted; releasing rst makes both FIFOs usable on the very next cycle. + fifoRst <= rstActiveHigh or clrEn_i; + + -------------------------------------------------------------------------- + -- U_MetaDataQ : metaDataQ + -- BSV: FIFOF#(RdmaPktMetaData) via mkFIFO (FWFT, depth 2) + -- Width: 649 bits — see RdmaPktMetaData derivation in FSM spec + -------------------------------------------------------------------------- + U_MetaDataQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 649, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => metaWrEn_i, + din => metaDin_i, + not_full => metaRdy_o, + rd_clk => clk, + rd_en => metaRdEn_i, + dout => metaDout_o, + valid => metaValid_o); + + -------------------------------------------------------------------------- + -- U_PayloadQ : payloadQ + -- BSV: FIFOF#(DataStream) via mkFIFO (FWFT, depth 2) + -- Width: 290 bits — data[255:0]+byteEn[31:0]+isFirst[1]+isLast[0] + -- (OQ-FSM-H2DS-02 closed: DataTypes.bsv 256+32+1+1=290, not 321) + -------------------------------------------------------------------------- + U_PayloadQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 290, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => payloadWrEn_i, + din => payloadDin_i, + not_full => payloadRdy_o, + rd_clk => clk, + rd_en => payloadRdEn_i, + dout => payloadDout_o, + valid => payloadValid_o); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/RecursiveSearch.vhd b/ethernet/RoCEv2/rtl/RecursiveSearch.vhd new file mode 100644 index 0000000000..d24d736f5f --- /dev/null +++ b/ethernet/RoCEv2/rtl/RecursiveSearch.vhd @@ -0,0 +1,1038 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Reduces VSZ_G Maybe#(anytype) input pipes to one output using +-- left-priority pairwise comparison at each tree level. +-- Structural complement to BinaryTreeFork. +-- +-- Five design units (layered to replace BSV recursive self-instantiation; +-- OQ-FSM-RS-02 resolved — same approach as OQ-FSM-BTF-02): +-- +-- RecursiveSearch_L0 (base, VSZ=1, 1 searchQ FIFO, popOut rule) +-- RecursiveSearch_L1 (VSZ=2, 1 pairCmp, 1 FIFO + U_SubSearch:L0) +-- RecursiveSearch_L2 (VSZ=4, 2 pairCmp, 2 FIFOs + U_SubSearch:L1) +-- RecursiveSearch_L3 (VSZ=8, 4 pairCmp, 4 FIFOs + U_SubSearch:L2) +-- RecursiveSearch (top,VSZ=16, 8 pairCmp, 8 FIFOs + U_SubSearch:L3) +-- +-- Interface correction (OQ-FSM-RS-01 resolved): +-- mapping.json listed Server#(SearchReq,SearchResp) — WRONG. +-- Port list follows RecursiveSearch.fsm.md. +-- Ports: clearAll, inputVec_i_{valid,dout,rdEn} (i=0..VSZ_G-1), +-- resultValid, resultDout, resultRdEn. +-- +-- Maybe#(anytype) valid-tag (OQ-FSM-RS-05 resolved, RESOLVED.md): +-- BSV deriving(Bits) packs tag as MSB → bit[ITEM_W_G]. +-- winner = left when left(ITEM_W_G)='1' else right. +-- +-- clearAll semantics (OQ-FSM-RS-04 resolved via OQ-FSM-06/BTF-04): +-- nextLayerQRst = rstNorm OR clearAll (level-sensitive; FifoSync safe). +-- No pulse generator required. +-- +-- ITEM_W_G is the bit width of anytype (not including the valid tag). +-- All FIFO DATA_WIDTH_G = ITEM_W_G+1 (the packed Maybe#(anytype) word). +-- Concrete values: readCacheQ = 176; atomicCacheQ = TBD (OQ-FSM-RS-03). +-- +-- SURF components (16 total for VSZ_G=16): +-- surf.Fifo GEN_SYNC_FIFO_G=true, FWFT_EN_G=true, RST_POLARITY_G='1' +-- source: surf/base/fifo/rtl/Fifo.vhd +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + + +-- =========================================================================== +-- RecursiveSearch_L0 (base case, VSZ=1) +-- BSV rules: popOut, discardInput[0], resetAndClear +-- =========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library surf; +use surf.StdRtlPkg.all; + +entity RecursiveSearch_L0 is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + ITEM_W_G : positive := 176; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "distributed"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + clearAll : in sl; + -- Single input lane (inputVec[0]) + inputVec_0_valid : in sl; + inputVec_0_dout : in slv(ITEM_W_G downto 0); + inputVec_0_rdEn : out sl; + -- Result output + resultValid : out sl; + resultDout : out slv(ITEM_W_G downto 0); + resultRdEn : in sl); +end entity RecursiveSearch_L0; + +architecture rtl of RecursiveSearch_L0 is + + -- No live registered state; dummy field keeps RegType non-empty. + type RegType is record + dummy : sl; + end record RegType; + constant REG_INIT_C : RegType := (dummy => '0'); + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rstNorm : sl; + signal searchQRst : sl; + signal searchQWrEn : sl; + signal searchQNotFull : sl; + +begin + + rstNorm <= rst when (RST_POLARITY_G = '1') else not rst; + searchQRst <= rstNorm or clearAll; + + -- U_SearchQ: resultQ in BSV source + U_SearchQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => ITEM_W_G+1, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => searchQRst, + wr_clk => clk, + wr_en => searchQWrEn, + din => inputVec_0_dout, + not_full => searchQNotFull, + rd_clk => clk, + rd_en => resultRdEn, + dout => resultDout, + valid => resultValid); + + -- popOut / discardInput + comb : process (r, rst, clearAll, inputVec_0_valid, searchQNotFull) is + variable v : RegType; + variable rdEnV : sl; + variable wrEnV : sl; + begin + v := r; + rdEnV := '0'; + wrEnV := '0'; + + if clearAll = '1' then + -- discardInput[0]: drain upstream (searchQRst clears FIFO via level) + rdEnV := inputVec_0_valid; + else + -- popOut: forward input to resultQ + if inputVec_0_valid = '1' and searchQNotFull = '1' then + rdEnV := '1'; + wrEnV := '1'; + end if; + end if; + + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + inputVec_0_rdEn <= rdEnV; + searchQWrEn <= wrEnV; + end process comb; + + seq : process (clk, rst) is + begin + if RST_ASYNC_G and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; + + +-- =========================================================================== +-- RecursiveSearch_L1 (VSZ=2, 1 pairCmp rule) +-- BSV rules: pairCmp[0], discardInput[0..1], resetAndClear[0] +-- =========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library surf; +use surf.StdRtlPkg.all; + +entity RecursiveSearch_L1 is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + ITEM_W_G : positive := 176; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "distributed"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + clearAll : in sl; + inputVec_0_valid : in sl; + inputVec_0_dout : in slv(ITEM_W_G downto 0); + inputVec_0_rdEn : out sl; + inputVec_1_valid : in sl; + inputVec_1_dout : in slv(ITEM_W_G downto 0); + inputVec_1_rdEn : out sl; + resultValid : out sl; + resultDout : out slv(ITEM_W_G downto 0); + resultRdEn : in sl); +end entity RecursiveSearch_L1; + +architecture rtl of RecursiveSearch_L1 is + + type RegType is record + dummy : sl; + end record RegType; + constant REG_INIT_C : RegType := (dummy => '0'); + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rstNorm : sl; + signal nextLayerQRst : sl; + -- U_NextLayerQ_0 + signal nlqDin0 : slv(ITEM_W_G downto 0); + signal nlqWrEn0 : sl; + signal nlq0NotFull : sl; + signal nlq0Valid : sl; + signal nlq0Dout : slv(ITEM_W_G downto 0); + signal nlq0RdEn : sl; + +begin + + rstNorm <= rst when (RST_POLARITY_G = '1') else not rst; + nextLayerQRst <= rstNorm or clearAll; + + -- Winner-select: left(ITEM_W_G)=valid tag (MSB); left has priority + nlqDin0 <= inputVec_0_dout when inputVec_0_dout(ITEM_W_G) = '1' + else inputVec_1_dout; + + U_NextLayerQ_0 : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + DATA_WIDTH_G => ITEM_W_G+1, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G => MEM_TYPE_G) + port map ( + rst => nextLayerQRst, + wr_clk => clk, + wr_en => nlqWrEn0, + din => nlqDin0, + not_full => nlq0NotFull, + rd_clk => clk, + rd_en => nlq0RdEn, + dout => nlq0Dout, + valid => nlq0Valid); + + -- Sub-search (L0) consumes U_NextLayerQ_0 output + U_SubSearch : entity surf.RecursiveSearch_L0 + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + ITEM_W_G => ITEM_W_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G, + MEM_TYPE_G => MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + clearAll => clearAll, + inputVec_0_valid => nlq0Valid, + inputVec_0_dout => nlq0Dout, + inputVec_0_rdEn => nlq0RdEn, + resultValid => resultValid, + resultDout => resultDout, + resultRdEn => resultRdEn); + + -- pairCmp[0] / discardInput[0..1] + comb : process (r, rst, clearAll, + inputVec_0_valid, inputVec_1_valid, + nlq0NotFull) is + variable v : RegType; + variable rdEn0V : sl; + variable rdEn1V : sl; + variable wrEn0V : sl; + begin + v := r; + rdEn0V := '0'; + rdEn1V := '0'; + wrEn0V := '0'; + + if clearAll = '1' then + rdEn0V := inputVec_0_valid; + rdEn1V := inputVec_1_valid; + else + -- pairCmp[0]: both must be valid; winner selected by concurrent mux + if inputVec_0_valid = '1' and inputVec_1_valid = '1' and nlq0NotFull = '1' then + rdEn0V := '1'; + rdEn1V := '1'; + wrEn0V := '1'; + end if; + end if; + + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + inputVec_0_rdEn <= rdEn0V; + inputVec_1_rdEn <= rdEn1V; + nlqWrEn0 <= wrEn0V; + end process comb; + + seq : process (clk, rst) is + begin + if RST_ASYNC_G and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; + + +-- =========================================================================== +-- RecursiveSearch_L2 (VSZ=4, 2 pairCmp rules) +-- BSV rules: pairCmp[0..1], discardInput[0..3], resetAndClear[0..1] +-- =========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library surf; +use surf.StdRtlPkg.all; + +entity RecursiveSearch_L2 is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + ITEM_W_G : positive := 176; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "distributed"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + clearAll : in sl; + inputVec_0_valid : in sl; + inputVec_0_dout : in slv(ITEM_W_G downto 0); + inputVec_0_rdEn : out sl; + inputVec_1_valid : in sl; + inputVec_1_dout : in slv(ITEM_W_G downto 0); + inputVec_1_rdEn : out sl; + inputVec_2_valid : in sl; + inputVec_2_dout : in slv(ITEM_W_G downto 0); + inputVec_2_rdEn : out sl; + inputVec_3_valid : in sl; + inputVec_3_dout : in slv(ITEM_W_G downto 0); + inputVec_3_rdEn : out sl; + resultValid : out sl; + resultDout : out slv(ITEM_W_G downto 0); + resultRdEn : in sl); +end entity RecursiveSearch_L2; + +architecture rtl of RecursiveSearch_L2 is + + type RegType is record + dummy : sl; + end record RegType; + constant REG_INIT_C : RegType := (dummy => '0'); + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rstNorm : sl; + signal nextLayerQRst : sl; + signal nlqDin0 : slv(ITEM_W_G downto 0); + signal nlqDin1 : slv(ITEM_W_G downto 0); + signal nlqWrEn0 : sl; + signal nlqWrEn1 : sl; + signal nlq0NotFull : sl; + signal nlq1NotFull : sl; + signal nlq0Valid : sl; + signal nlq1Valid : sl; + signal nlq0Dout : slv(ITEM_W_G downto 0); + signal nlq1Dout : slv(ITEM_W_G downto 0); + signal nlq0RdEn : sl; + signal nlq1RdEn : sl; + +begin + + rstNorm <= rst when (RST_POLARITY_G = '1') else not rst; + nextLayerQRst <= rstNorm or clearAll; + + nlqDin0 <= inputVec_0_dout when inputVec_0_dout(ITEM_W_G) = '1' else inputVec_1_dout; + nlqDin1 <= inputVec_2_dout when inputVec_2_dout(ITEM_W_G) = '1' else inputVec_3_dout; + + U_NextLayerQ_0 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn0, din=>nlqDin0, + not_full=>nlq0NotFull, rd_clk=>clk, rd_en=>nlq0RdEn, + dout=>nlq0Dout, valid=>nlq0Valid); + + U_NextLayerQ_1 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn1, din=>nlqDin1, + not_full=>nlq1NotFull, rd_clk=>clk, rd_en=>nlq1RdEn, + dout=>nlq1Dout, valid=>nlq1Valid); + + U_SubSearch : entity surf.RecursiveSearch_L1 + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>RST_POLARITY_G, + RST_ASYNC_G=>RST_ASYNC_G, ITEM_W_G=>ITEM_W_G, + FIFO_ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, MEM_TYPE_G=>MEM_TYPE_G) + port map ( + clk => clk, + rst => rst, + clearAll => clearAll, + inputVec_0_valid => nlq0Valid, + inputVec_0_dout => nlq0Dout, + inputVec_0_rdEn => nlq0RdEn, + inputVec_1_valid => nlq1Valid, + inputVec_1_dout => nlq1Dout, + inputVec_1_rdEn => nlq1RdEn, + resultValid => resultValid, + resultDout => resultDout, + resultRdEn => resultRdEn); + + comb : process (r, rst, clearAll, + inputVec_0_valid, inputVec_1_valid, + inputVec_2_valid, inputVec_3_valid, + nlq0NotFull, nlq1NotFull) is + variable v : RegType; + variable rdEn0V : sl; + variable rdEn1V : sl; + variable rdEn2V : sl; + variable rdEn3V : sl; + variable wrEn0V : sl; + variable wrEn1V : sl; + begin + v := r; + rdEn0V := '0'; rdEn1V := '0'; rdEn2V := '0'; rdEn3V := '0'; + wrEn0V := '0'; wrEn1V := '0'; + + if clearAll = '1' then + rdEn0V := inputVec_0_valid; + rdEn1V := inputVec_1_valid; + rdEn2V := inputVec_2_valid; + rdEn3V := inputVec_3_valid; + else + -- pairCmp[0]: pair (0,1) → U_NextLayerQ_0 + if inputVec_0_valid = '1' and inputVec_1_valid = '1' and nlq0NotFull = '1' then + rdEn0V := '1'; rdEn1V := '1'; wrEn0V := '1'; + end if; + -- pairCmp[1]: pair (2,3) → U_NextLayerQ_1 + if inputVec_2_valid = '1' and inputVec_3_valid = '1' and nlq1NotFull = '1' then + rdEn2V := '1'; rdEn3V := '1'; wrEn1V := '1'; + end if; + end if; + + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + inputVec_0_rdEn <= rdEn0V; + inputVec_1_rdEn <= rdEn1V; + inputVec_2_rdEn <= rdEn2V; + inputVec_3_rdEn <= rdEn3V; + nlqWrEn0 <= wrEn0V; + nlqWrEn1 <= wrEn1V; + end process comb; + + seq : process (clk, rst) is + begin + if RST_ASYNC_G and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; + + +-- =========================================================================== +-- RecursiveSearch_L3 (VSZ=8, 4 pairCmp rules) +-- BSV rules: pairCmp[0..3], discardInput[0..7], resetAndClear[0..3] +-- =========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library surf; +use surf.StdRtlPkg.all; + +entity RecursiveSearch_L3 is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + ITEM_W_G : positive := 176; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "distributed"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + clearAll : in sl; + inputVec_0_valid : in sl; + inputVec_0_dout : in slv(ITEM_W_G downto 0); + inputVec_0_rdEn : out sl; + inputVec_1_valid : in sl; + inputVec_1_dout : in slv(ITEM_W_G downto 0); + inputVec_1_rdEn : out sl; + inputVec_2_valid : in sl; + inputVec_2_dout : in slv(ITEM_W_G downto 0); + inputVec_2_rdEn : out sl; + inputVec_3_valid : in sl; + inputVec_3_dout : in slv(ITEM_W_G downto 0); + inputVec_3_rdEn : out sl; + inputVec_4_valid : in sl; + inputVec_4_dout : in slv(ITEM_W_G downto 0); + inputVec_4_rdEn : out sl; + inputVec_5_valid : in sl; + inputVec_5_dout : in slv(ITEM_W_G downto 0); + inputVec_5_rdEn : out sl; + inputVec_6_valid : in sl; + inputVec_6_dout : in slv(ITEM_W_G downto 0); + inputVec_6_rdEn : out sl; + inputVec_7_valid : in sl; + inputVec_7_dout : in slv(ITEM_W_G downto 0); + inputVec_7_rdEn : out sl; + resultValid : out sl; + resultDout : out slv(ITEM_W_G downto 0); + resultRdEn : in sl); +end entity RecursiveSearch_L3; + +architecture rtl of RecursiveSearch_L3 is + + type RegType is record + dummy : sl; + end record RegType; + constant REG_INIT_C : RegType := (dummy => '0'); + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rstNorm : sl; + signal nextLayerQRst : sl; + signal nlqDin0 : slv(ITEM_W_G downto 0); + signal nlqDin1 : slv(ITEM_W_G downto 0); + signal nlqDin2 : slv(ITEM_W_G downto 0); + signal nlqDin3 : slv(ITEM_W_G downto 0); + signal nlqWrEn0 : sl; + signal nlqWrEn1 : sl; + signal nlqWrEn2 : sl; + signal nlqWrEn3 : sl; + signal nlq0NotFull : sl; + signal nlq1NotFull : sl; + signal nlq2NotFull : sl; + signal nlq3NotFull : sl; + signal nlq0Valid : sl; + signal nlq1Valid : sl; + signal nlq2Valid : sl; + signal nlq3Valid : sl; + signal nlq0Dout : slv(ITEM_W_G downto 0); + signal nlq1Dout : slv(ITEM_W_G downto 0); + signal nlq2Dout : slv(ITEM_W_G downto 0); + signal nlq3Dout : slv(ITEM_W_G downto 0); + signal nlq0RdEn : sl; + signal nlq1RdEn : sl; + signal nlq2RdEn : sl; + signal nlq3RdEn : sl; + +begin + + rstNorm <= rst when (RST_POLARITY_G = '1') else not rst; + nextLayerQRst <= rstNorm or clearAll; + + nlqDin0 <= inputVec_0_dout when inputVec_0_dout(ITEM_W_G) = '1' else inputVec_1_dout; + nlqDin1 <= inputVec_2_dout when inputVec_2_dout(ITEM_W_G) = '1' else inputVec_3_dout; + nlqDin2 <= inputVec_4_dout when inputVec_4_dout(ITEM_W_G) = '1' else inputVec_5_dout; + nlqDin3 <= inputVec_6_dout when inputVec_6_dout(ITEM_W_G) = '1' else inputVec_7_dout; + + U_NextLayerQ_0 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn0, din=>nlqDin0, + not_full=>nlq0NotFull, rd_clk=>clk, rd_en=>nlq0RdEn, + dout=>nlq0Dout, valid=>nlq0Valid); + + U_NextLayerQ_1 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn1, din=>nlqDin1, + not_full=>nlq1NotFull, rd_clk=>clk, rd_en=>nlq1RdEn, + dout=>nlq1Dout, valid=>nlq1Valid); + + U_NextLayerQ_2 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn2, din=>nlqDin2, + not_full=>nlq2NotFull, rd_clk=>clk, rd_en=>nlq2RdEn, + dout=>nlq2Dout, valid=>nlq2Valid); + + U_NextLayerQ_3 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn3, din=>nlqDin3, + not_full=>nlq3NotFull, rd_clk=>clk, rd_en=>nlq3RdEn, + dout=>nlq3Dout, valid=>nlq3Valid); + + U_SubSearch : entity surf.RecursiveSearch_L2 + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>RST_POLARITY_G, + RST_ASYNC_G=>RST_ASYNC_G, ITEM_W_G=>ITEM_W_G, + FIFO_ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, MEM_TYPE_G=>MEM_TYPE_G) + port map ( + clk => clk, rst => rst, clearAll => clearAll, + inputVec_0_valid => nlq0Valid, inputVec_0_dout => nlq0Dout, inputVec_0_rdEn => nlq0RdEn, + inputVec_1_valid => nlq1Valid, inputVec_1_dout => nlq1Dout, inputVec_1_rdEn => nlq1RdEn, + inputVec_2_valid => nlq2Valid, inputVec_2_dout => nlq2Dout, inputVec_2_rdEn => nlq2RdEn, + inputVec_3_valid => nlq3Valid, inputVec_3_dout => nlq3Dout, inputVec_3_rdEn => nlq3RdEn, + resultValid => resultValid, + resultDout => resultDout, + resultRdEn => resultRdEn); + + comb : process (r, rst, clearAll, + inputVec_0_valid, inputVec_1_valid, + inputVec_2_valid, inputVec_3_valid, + inputVec_4_valid, inputVec_5_valid, + inputVec_6_valid, inputVec_7_valid, + nlq0NotFull, nlq1NotFull, nlq2NotFull, nlq3NotFull) is + variable v : RegType; + variable rdEn0V : sl; variable rdEn1V : sl; + variable rdEn2V : sl; variable rdEn3V : sl; + variable rdEn4V : sl; variable rdEn5V : sl; + variable rdEn6V : sl; variable rdEn7V : sl; + variable wrEn0V : sl; variable wrEn1V : sl; + variable wrEn2V : sl; variable wrEn3V : sl; + begin + v := r; + rdEn0V := '0'; rdEn1V := '0'; rdEn2V := '0'; rdEn3V := '0'; + rdEn4V := '0'; rdEn5V := '0'; rdEn6V := '0'; rdEn7V := '0'; + wrEn0V := '0'; wrEn1V := '0'; wrEn2V := '0'; wrEn3V := '0'; + + if clearAll = '1' then + rdEn0V := inputVec_0_valid; rdEn1V := inputVec_1_valid; + rdEn2V := inputVec_2_valid; rdEn3V := inputVec_3_valid; + rdEn4V := inputVec_4_valid; rdEn5V := inputVec_5_valid; + rdEn6V := inputVec_6_valid; rdEn7V := inputVec_7_valid; + else + if inputVec_0_valid='1' and inputVec_1_valid='1' and nlq0NotFull='1' then + rdEn0V:='1'; rdEn1V:='1'; wrEn0V:='1'; + end if; + if inputVec_2_valid='1' and inputVec_3_valid='1' and nlq1NotFull='1' then + rdEn2V:='1'; rdEn3V:='1'; wrEn1V:='1'; + end if; + if inputVec_4_valid='1' and inputVec_5_valid='1' and nlq2NotFull='1' then + rdEn4V:='1'; rdEn5V:='1'; wrEn2V:='1'; + end if; + if inputVec_6_valid='1' and inputVec_7_valid='1' and nlq3NotFull='1' then + rdEn6V:='1'; rdEn7V:='1'; wrEn3V:='1'; + end if; + end if; + + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + inputVec_0_rdEn <= rdEn0V; inputVec_1_rdEn <= rdEn1V; + inputVec_2_rdEn <= rdEn2V; inputVec_3_rdEn <= rdEn3V; + inputVec_4_rdEn <= rdEn4V; inputVec_5_rdEn <= rdEn5V; + inputVec_6_rdEn <= rdEn6V; inputVec_7_rdEn <= rdEn7V; + nlqWrEn0 <= wrEn0V; nlqWrEn1 <= wrEn1V; + nlqWrEn2 <= wrEn2V; nlqWrEn3 <= wrEn3V; + end process comb; + + seq : process (clk, rst) is + begin + if RST_ASYNC_G and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; + + +-- =========================================================================== +-- RecursiveSearch (top / VSZ=16, 8 pairCmp rules) +-- Public entity name consumed by CacheFifo. +-- BSV rules: pairCmp[0..7], discardInput[0..15], resetAndClear[0..7] +-- =========================================================================== +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library surf; +use surf.StdRtlPkg.all; + +entity RecursiveSearch is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; + RST_ASYNC_G : boolean := false; + ITEM_W_G : positive := 176; + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; + MEM_TYPE_G : string := "distributed"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + clearAll : in sl; + -- 16 input lanes + inputVec_0_valid : in sl; + inputVec_0_dout : in slv(ITEM_W_G downto 0); + inputVec_0_rdEn : out sl; + inputVec_1_valid : in sl; + inputVec_1_dout : in slv(ITEM_W_G downto 0); + inputVec_1_rdEn : out sl; + inputVec_2_valid : in sl; + inputVec_2_dout : in slv(ITEM_W_G downto 0); + inputVec_2_rdEn : out sl; + inputVec_3_valid : in sl; + inputVec_3_dout : in slv(ITEM_W_G downto 0); + inputVec_3_rdEn : out sl; + inputVec_4_valid : in sl; + inputVec_4_dout : in slv(ITEM_W_G downto 0); + inputVec_4_rdEn : out sl; + inputVec_5_valid : in sl; + inputVec_5_dout : in slv(ITEM_W_G downto 0); + inputVec_5_rdEn : out sl; + inputVec_6_valid : in sl; + inputVec_6_dout : in slv(ITEM_W_G downto 0); + inputVec_6_rdEn : out sl; + inputVec_7_valid : in sl; + inputVec_7_dout : in slv(ITEM_W_G downto 0); + inputVec_7_rdEn : out sl; + inputVec_8_valid : in sl; + inputVec_8_dout : in slv(ITEM_W_G downto 0); + inputVec_8_rdEn : out sl; + inputVec_9_valid : in sl; + inputVec_9_dout : in slv(ITEM_W_G downto 0); + inputVec_9_rdEn : out sl; + inputVec_10_valid : in sl; + inputVec_10_dout : in slv(ITEM_W_G downto 0); + inputVec_10_rdEn : out sl; + inputVec_11_valid : in sl; + inputVec_11_dout : in slv(ITEM_W_G downto 0); + inputVec_11_rdEn : out sl; + inputVec_12_valid : in sl; + inputVec_12_dout : in slv(ITEM_W_G downto 0); + inputVec_12_rdEn : out sl; + inputVec_13_valid : in sl; + inputVec_13_dout : in slv(ITEM_W_G downto 0); + inputVec_13_rdEn : out sl; + inputVec_14_valid : in sl; + inputVec_14_dout : in slv(ITEM_W_G downto 0); + inputVec_14_rdEn : out sl; + inputVec_15_valid : in sl; + inputVec_15_dout : in slv(ITEM_W_G downto 0); + inputVec_15_rdEn : out sl; + -- Result output + resultValid : out sl; + resultDout : out slv(ITEM_W_G downto 0); + resultRdEn : in sl); +end entity RecursiveSearch; + +architecture rtl of RecursiveSearch is + + type RegType is record + dummy : sl; + end record RegType; + constant REG_INIT_C : RegType := (dummy => '0'); + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal rstNorm : sl; + signal nextLayerQRst : sl; + -- Winner-select FIFO din + signal nlqDin0 : slv(ITEM_W_G downto 0); + signal nlqDin1 : slv(ITEM_W_G downto 0); + signal nlqDin2 : slv(ITEM_W_G downto 0); + signal nlqDin3 : slv(ITEM_W_G downto 0); + signal nlqDin4 : slv(ITEM_W_G downto 0); + signal nlqDin5 : slv(ITEM_W_G downto 0); + signal nlqDin6 : slv(ITEM_W_G downto 0); + signal nlqDin7 : slv(ITEM_W_G downto 0); + -- FIFO write enables + signal nlqWrEn0 : sl; + signal nlqWrEn1 : sl; + signal nlqWrEn2 : sl; + signal nlqWrEn3 : sl; + signal nlqWrEn4 : sl; + signal nlqWrEn5 : sl; + signal nlqWrEn6 : sl; + signal nlqWrEn7 : sl; + -- FIFO not_full feedback + signal nlq0NotFull : sl; + signal nlq1NotFull : sl; + signal nlq2NotFull : sl; + signal nlq3NotFull : sl; + signal nlq4NotFull : sl; + signal nlq5NotFull : sl; + signal nlq6NotFull : sl; + signal nlq7NotFull : sl; + -- FIFO valid / dout + signal nlq0Valid : sl; signal nlq0Dout : slv(ITEM_W_G downto 0); + signal nlq1Valid : sl; signal nlq1Dout : slv(ITEM_W_G downto 0); + signal nlq2Valid : sl; signal nlq2Dout : slv(ITEM_W_G downto 0); + signal nlq3Valid : sl; signal nlq3Dout : slv(ITEM_W_G downto 0); + signal nlq4Valid : sl; signal nlq4Dout : slv(ITEM_W_G downto 0); + signal nlq5Valid : sl; signal nlq5Dout : slv(ITEM_W_G downto 0); + signal nlq6Valid : sl; signal nlq6Dout : slv(ITEM_W_G downto 0); + signal nlq7Valid : sl; signal nlq7Dout : slv(ITEM_W_G downto 0); + -- FIFO read enables (driven by U_SubSearch) + signal nlq0RdEn : sl; + signal nlq1RdEn : sl; + signal nlq2RdEn : sl; + signal nlq3RdEn : sl; + signal nlq4RdEn : sl; + signal nlq5RdEn : sl; + signal nlq6RdEn : sl; + signal nlq7RdEn : sl; + +begin + + rstNorm <= rst when (RST_POLARITY_G = '1') else not rst; + nextLayerQRst <= rstNorm or clearAll; + + -- 8 concurrent winner-select muxes (one per pairCmp instance) + nlqDin0 <= inputVec_0_dout when inputVec_0_dout(ITEM_W_G) = '1' else inputVec_1_dout; + nlqDin1 <= inputVec_2_dout when inputVec_2_dout(ITEM_W_G) = '1' else inputVec_3_dout; + nlqDin2 <= inputVec_4_dout when inputVec_4_dout(ITEM_W_G) = '1' else inputVec_5_dout; + nlqDin3 <= inputVec_6_dout when inputVec_6_dout(ITEM_W_G) = '1' else inputVec_7_dout; + nlqDin4 <= inputVec_8_dout when inputVec_8_dout(ITEM_W_G) = '1' else inputVec_9_dout; + nlqDin5 <= inputVec_10_dout when inputVec_10_dout(ITEM_W_G) = '1' else inputVec_11_dout; + nlqDin6 <= inputVec_12_dout when inputVec_12_dout(ITEM_W_G) = '1' else inputVec_13_dout; + nlqDin7 <= inputVec_14_dout when inputVec_14_dout(ITEM_W_G) = '1' else inputVec_15_dout; + + U_NextLayerQ_0 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn0, din=>nlqDin0, + not_full=>nlq0NotFull, rd_clk=>clk, rd_en=>nlq0RdEn, + dout=>nlq0Dout, valid=>nlq0Valid); + + U_NextLayerQ_1 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn1, din=>nlqDin1, + not_full=>nlq1NotFull, rd_clk=>clk, rd_en=>nlq1RdEn, + dout=>nlq1Dout, valid=>nlq1Valid); + + U_NextLayerQ_2 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn2, din=>nlqDin2, + not_full=>nlq2NotFull, rd_clk=>clk, rd_en=>nlq2RdEn, + dout=>nlq2Dout, valid=>nlq2Valid); + + U_NextLayerQ_3 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn3, din=>nlqDin3, + not_full=>nlq3NotFull, rd_clk=>clk, rd_en=>nlq3RdEn, + dout=>nlq3Dout, valid=>nlq3Valid); + + U_NextLayerQ_4 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn4, din=>nlqDin4, + not_full=>nlq4NotFull, rd_clk=>clk, rd_en=>nlq4RdEn, + dout=>nlq4Dout, valid=>nlq4Valid); + + U_NextLayerQ_5 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn5, din=>nlqDin5, + not_full=>nlq5NotFull, rd_clk=>clk, rd_en=>nlq5RdEn, + dout=>nlq5Dout, valid=>nlq5Valid); + + U_NextLayerQ_6 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn6, din=>nlqDin6, + not_full=>nlq6NotFull, rd_clk=>clk, rd_en=>nlq6RdEn, + dout=>nlq6Dout, valid=>nlq6Valid); + + U_NextLayerQ_7 : entity surf.Fifo + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>'1', RST_ASYNC_G=>false, + GEN_SYNC_FIFO_G=>true, FWFT_EN_G=>true, + DATA_WIDTH_G=>ITEM_W_G+1, ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, + MEMORY_TYPE_G=>MEM_TYPE_G) + port map (rst=>nextLayerQRst, wr_clk=>clk, wr_en=>nlqWrEn7, din=>nlqDin7, + not_full=>nlq7NotFull, rd_clk=>clk, rd_en=>nlq7RdEn, + dout=>nlq7Dout, valid=>nlq7Valid); + + U_SubSearch : entity surf.RecursiveSearch_L3 + generic map (TPD_G=>TPD_G, RST_POLARITY_G=>RST_POLARITY_G, + RST_ASYNC_G=>RST_ASYNC_G, ITEM_W_G=>ITEM_W_G, + FIFO_ADDR_WIDTH_G=>FIFO_ADDR_WIDTH_G, MEM_TYPE_G=>MEM_TYPE_G) + port map ( + clk => clk, rst => rst, clearAll => clearAll, + inputVec_0_valid => nlq0Valid, inputVec_0_dout => nlq0Dout, inputVec_0_rdEn => nlq0RdEn, + inputVec_1_valid => nlq1Valid, inputVec_1_dout => nlq1Dout, inputVec_1_rdEn => nlq1RdEn, + inputVec_2_valid => nlq2Valid, inputVec_2_dout => nlq2Dout, inputVec_2_rdEn => nlq2RdEn, + inputVec_3_valid => nlq3Valid, inputVec_3_dout => nlq3Dout, inputVec_3_rdEn => nlq3RdEn, + inputVec_4_valid => nlq4Valid, inputVec_4_dout => nlq4Dout, inputVec_4_rdEn => nlq4RdEn, + inputVec_5_valid => nlq5Valid, inputVec_5_dout => nlq5Dout, inputVec_5_rdEn => nlq5RdEn, + inputVec_6_valid => nlq6Valid, inputVec_6_dout => nlq6Dout, inputVec_6_rdEn => nlq6RdEn, + inputVec_7_valid => nlq7Valid, inputVec_7_dout => nlq7Dout, inputVec_7_rdEn => nlq7RdEn, + resultValid => resultValid, + resultDout => resultDout, + resultRdEn => resultRdEn); + + -- 8 concurrent pairCmp rules + discardInput[0..15] + comb : process (r, rst, clearAll, + inputVec_0_valid, inputVec_1_valid, + inputVec_2_valid, inputVec_3_valid, + inputVec_4_valid, inputVec_5_valid, + inputVec_6_valid, inputVec_7_valid, + inputVec_8_valid, inputVec_9_valid, + inputVec_10_valid, inputVec_11_valid, + inputVec_12_valid, inputVec_13_valid, + inputVec_14_valid, inputVec_15_valid, + nlq0NotFull, nlq1NotFull, nlq2NotFull, nlq3NotFull, + nlq4NotFull, nlq5NotFull, nlq6NotFull, nlq7NotFull) is + variable v : RegType; + variable rdEn0V : sl; variable rdEn1V : sl; + variable rdEn2V : sl; variable rdEn3V : sl; + variable rdEn4V : sl; variable rdEn5V : sl; + variable rdEn6V : sl; variable rdEn7V : sl; + variable rdEn8V : sl; variable rdEn9V : sl; + variable rdEn10V : sl; variable rdEn11V : sl; + variable rdEn12V : sl; variable rdEn13V : sl; + variable rdEn14V : sl; variable rdEn15V : sl; + variable wrEn0V : sl; variable wrEn1V : sl; + variable wrEn2V : sl; variable wrEn3V : sl; + variable wrEn4V : sl; variable wrEn5V : sl; + variable wrEn6V : sl; variable wrEn7V : sl; + begin + v := r; + rdEn0V := '0'; rdEn1V := '0'; rdEn2V := '0'; rdEn3V := '0'; + rdEn4V := '0'; rdEn5V := '0'; rdEn6V := '0'; rdEn7V := '0'; + rdEn8V := '0'; rdEn9V := '0'; rdEn10V := '0'; rdEn11V := '0'; + rdEn12V := '0'; rdEn13V := '0'; rdEn14V := '0'; rdEn15V := '0'; + wrEn0V := '0'; wrEn1V := '0'; wrEn2V := '0'; wrEn3V := '0'; + wrEn4V := '0'; wrEn5V := '0'; wrEn6V := '0'; wrEn7V := '0'; + + if clearAll = '1' then + -- discardInput[j] for j=0..15: drain all input lanes + rdEn0V := inputVec_0_valid; rdEn1V := inputVec_1_valid; + rdEn2V := inputVec_2_valid; rdEn3V := inputVec_3_valid; + rdEn4V := inputVec_4_valid; rdEn5V := inputVec_5_valid; + rdEn6V := inputVec_6_valid; rdEn7V := inputVec_7_valid; + rdEn8V := inputVec_8_valid; rdEn9V := inputVec_9_valid; + rdEn10V := inputVec_10_valid; rdEn11V := inputVec_11_valid; + rdEn12V := inputVec_12_valid; rdEn13V := inputVec_13_valid; + rdEn14V := inputVec_14_valid; rdEn15V := inputVec_15_valid; + else + -- pairCmp[0]: pair (0,1) → U_NextLayerQ_0 + if inputVec_0_valid='1' and inputVec_1_valid='1' and nlq0NotFull='1' then + rdEn0V:='1'; rdEn1V:='1'; wrEn0V:='1'; + end if; + -- pairCmp[1]: pair (2,3) → U_NextLayerQ_1 + if inputVec_2_valid='1' and inputVec_3_valid='1' and nlq1NotFull='1' then + rdEn2V:='1'; rdEn3V:='1'; wrEn1V:='1'; + end if; + -- pairCmp[2]: pair (4,5) → U_NextLayerQ_2 + if inputVec_4_valid='1' and inputVec_5_valid='1' and nlq2NotFull='1' then + rdEn4V:='1'; rdEn5V:='1'; wrEn2V:='1'; + end if; + -- pairCmp[3]: pair (6,7) → U_NextLayerQ_3 + if inputVec_6_valid='1' and inputVec_7_valid='1' and nlq3NotFull='1' then + rdEn6V:='1'; rdEn7V:='1'; wrEn3V:='1'; + end if; + -- pairCmp[4]: pair (8,9) → U_NextLayerQ_4 + if inputVec_8_valid='1' and inputVec_9_valid='1' and nlq4NotFull='1' then + rdEn8V:='1'; rdEn9V:='1'; wrEn4V:='1'; + end if; + -- pairCmp[5]: pair (10,11) → U_NextLayerQ_5 + if inputVec_10_valid='1' and inputVec_11_valid='1' and nlq5NotFull='1' then + rdEn10V:='1'; rdEn11V:='1'; wrEn5V:='1'; + end if; + -- pairCmp[6]: pair (12,13) → U_NextLayerQ_6 + if inputVec_12_valid='1' and inputVec_13_valid='1' and nlq6NotFull='1' then + rdEn12V:='1'; rdEn13V:='1'; wrEn6V:='1'; + end if; + -- pairCmp[7]: pair (14,15) → U_NextLayerQ_7 + if inputVec_14_valid='1' and inputVec_15_valid='1' and nlq7NotFull='1' then + rdEn14V:='1'; rdEn15V:='1'; wrEn7V:='1'; + end if; + end if; + + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + inputVec_0_rdEn <= rdEn0V; inputVec_1_rdEn <= rdEn1V; + inputVec_2_rdEn <= rdEn2V; inputVec_3_rdEn <= rdEn3V; + inputVec_4_rdEn <= rdEn4V; inputVec_5_rdEn <= rdEn5V; + inputVec_6_rdEn <= rdEn6V; inputVec_7_rdEn <= rdEn7V; + inputVec_8_rdEn <= rdEn8V; inputVec_9_rdEn <= rdEn9V; + inputVec_10_rdEn <= rdEn10V; inputVec_11_rdEn <= rdEn11V; + inputVec_12_rdEn <= rdEn12V; inputVec_13_rdEn <= rdEn13V; + inputVec_14_rdEn <= rdEn14V; inputVec_15_rdEn <= rdEn15V; + nlqWrEn0 <= wrEn0V; nlqWrEn1 <= wrEn1V; + nlqWrEn2 <= wrEn2V; nlqWrEn3 <= wrEn3V; + nlqWrEn4 <= wrEn4V; nlqWrEn5 <= wrEn5V; + nlqWrEn6 <= wrEn6V; nlqWrEn7 <= wrEn7V; + end process comb; + + seq : process (clk, rst) is + begin + if RST_ASYNC_G and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ReqGenSq.vhd b/ethernet/RoCEv2/rtl/ReqGenSq.vhd new file mode 100644 index 0000000000..011e95a454 --- /dev/null +++ b/ethernet/RoCEv2/rtl/ReqGenSq.vhd @@ -0,0 +1,1141 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Nine-stage dataflow request pipeline, wrapped by a 2-state mode bit +-- (isNormalStateReg: NORMAL / ERR_FLUSH) and a per-WR packet loop +-- (isFirstOrOnlyReqPktReg + remainingPktNumReg + curPsnReg). All 11 worker +-- rules are BSV (* conflict_free *): each fires independently when its input +-- FIFO is non-empty, its output FIFO has room, and (where used) the external +-- payloadGenerator / contextSQ handshakes hold. Handoff between stages is +-- FIFO-carried. Emitted as 11 parallel comb blocks (R1..R11) computing each +-- stage's FIFO drives, plus a Moore-registered mode bit / packet-loop. +-- +-- 13 pipeline FIFOs (all surf.Fifo, FWFT, sync) + 2 internal children: +-- U_HeaderGenReqSQ : work.HeaderGenReqSQ (combinational request-header +-- packer, split out of mkReqGenSQ — see +-- ADDENDUM-HeaderGenReqSQ.md; emit+verify before this) +-- U_RdmaReqPipeOut : work.CombineHeaderAndPayload (mkCombineHeaderAndPayload) +-- +-- Module parameters become ports (OQ-FSM-RGS-01, same pattern as SendQ): +-- contextSQ -> status bundle (isReset/isStableRTS/isRTS/isERR/isSQD, +-- qpType/sqpn/pmtu/pkey/dqpn/sigAll) + getNPSN in / +-- setNPSN out (npsnIn / npsnOut+npsnWrEn : external +-- shared next-PSN register, read-modify-write in R4). +-- payloadGenerator -> external Server (req PayloadGenReq out / resp +-- PayloadGenResp in) + payloadDataStreamPipeOut in +-- (the last consumed only by the child, not by a rule). +-- pendingWorkReqPipeIn / pendingWorkReqBufNotEmpty -> input ports. +-- +-- resetAndClear (BSV, guard cntrlStatus.comm.isReset, fire_when_enabled): the +-- QP-status isReset is the synchronous clear (NOT the FPGA async reset). +-- While isReset='1' all 13 FIFOs are held cleared (fifoRst = rst OR isReset, +-- level clear — OQ-FSM-01/06 resolution: surf.FifoSync rst is level-safe), +-- isNormalStateReg forced '1', isFirstOrOnlyReqPktReg forced '1'. +-- (OQ-FSM-RGS-02.) +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_PendingWorkReqOutQ, U_WorkCompGenReqOutQ, U_WorkReqPayloadGenQ, +-- U_WorkReqPktNumQ, U_WorkReqPsnQ, U_WorkReqOutQ, U_WorkReqCheckQ, +-- U_ReqCountQ, U_ReqHeaderPrepareQ, U_PendingReqHeaderQ, U_ReqHeaderGenQ, +-- U_ReqHeaderOutQ, U_PsnReqOutQ. +-- +-- Refactor vs BSV Maybe-carrying FIFOs (mirrors SendQ): the Maybe# tuple +-- fields are carried as an explicit tag bit + payload slv in the FIFO word; +-- R9/R10 mux on the tag bit. genHeaderRDMA (byteEn + metaData) stays inline +-- in R9 (Utils.bsv:319); genFirstOrOnly/genMiddleOrLastReqHeader are in the +-- U_HeaderGenReqSQ child. +-- +-- Composite word layouts (first-field-at-MSB, from BSV deriving(Bits); +-- widths traced in memory resphandlesq-emit-facts + DataTypes.bsv): +-- WorkReq (601): id[600:537] opcode[536:533] flags[532:528] raddr[527:464] +-- rkey[463:432] len[431:400] laddr[399:336] lkey[335:304] sqpn[303:280] +-- solicited[279] comp{tag[278],val[277:214]} swap{tag[213],val[212:149]} +-- immDt{tag[148],val[147:116]} rkey2Inv{tag[115],val[114:83]} +-- srqn{tag[82],val[81:58]} dqpn{tag[57],val[56:33]} qkey{tag[32],val[31:0]} +-- (flags bit i = 2**i : FENCE=flags(0), SIGNALED=flags(1), SOLICITED=flags(2)) +-- PendingWorkReq (679): wr[678:78] startPSN{tag[77],val[76:53]} +-- endPSN{tag[52],val[51:28]} pktNum{tag[27],val[26:2]} +-- isOnlyReqPkt{tag[1],val[0]} (wr fields above are all +78) +-- WorkReqInfo (5): isNewWorkReq[4] isZeroPmtuResidue[3] isReliableConnection[2] +-- isUnreliableDatagram[1] needDmaRead[0] +-- ReqPktHeaderInfo (705): curPSN[704:681] pendingWR[680:2] isFirstReqPkt[1] +-- isLastReqPkt[0] +-- HeaderRDMA (593): headerData[592:81] headerByteEn[80:17] +-- headerMetaData[16:0] = headerLen[16:10] headerFragNum[9:8] +-- lastFragValidByteNum[7:2] hasPayload[1] isEmptyHeader[0] +-- PayloadGenReq (199): dmaReadMetaData[198:4]{initiator[198:195] sqpn[194:171] +-- wrID[170:107] startAddr[106:43] len[42:11] mrIdx[10:4]} addPadding[3] pmtu[2:0] +-- PayloadGenResp (2): addPadding[1] isRespErr[0] +-- WorkCompGenReqSQ (633): wr[632:32] wcWaitDmaResp[31] wcReqType[30:29] +-- triggerPSN[28:5] wcStatus[4:0] +-- +-- Open questions (see out/04-vhdl/OPEN_QUESTIONS.md): OQ-EMIT-RGS-SPLIT, +-- OQ-EMIT-RGS-NPSN, OQ-EMIT-RGS-PGRESP. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ReqGenSq is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset (FPGA) + + ----------------------------------------------------------------------- + -- contextSQ.statusSQ bundle (cntrlStatus) + ----------------------------------------------------------------------- + isReset : in sl; -- comm.isReset (soft clear) + isStableRTS : in sl; -- comm.isStableRTS + isRTS : in sl; -- comm.isRTS + isERR : in sl; -- comm.isERR + isSQD : in sl; -- comm.isSQD + qpType : in slv(3 downto 0); -- getTypeQP + sqpn : in slv(23 downto 0); -- comm.getSQPN + pmtu : in slv(2 downto 0); -- comm.getPMTU + pkey : in slv(15 downto 0); -- comm.getPKEY + dqpn : in slv(23 downto 0); -- comm.getDQPN + sigAll : in sl; -- comm.getSigAll + -- contextSQ next-PSN shared register (read+write same cycle in R4) + npsnIn : in slv(23 downto 0); -- contextSQ.getNPSN + npsnOut : out slv(23 downto 0); -- contextSQ.setNPSN value + npsnWrEn : out sl; -- contextSQ.setNPSN write-enable + + ----------------------------------------------------------------------- + -- pendingWorkReqPipeIn : PipeOut#(PendingWorkReq) (input) + ----------------------------------------------------------------------- + pendingWorkReqInValid : in sl; -- .notEmpty + pendingWorkReqInData : in slv(678 downto 0); -- .first (PendingWorkReq) + pendingWorkReqInRdEn : out sl; -- .deq + pendingWorkReqBufNotEmpty : in sl; -- fence fence-drain fence flag + + ----------------------------------------------------------------------- + -- payloadGenerator external Server + PipeOut + ----------------------------------------------------------------------- + -- srvPort.request : PayloadGenReq (out / put) + payloadGenReqValid : out sl; + payloadGenReqData : out slv(198 downto 0); + payloadGenReqReady : in sl; + -- srvPort.response : PayloadGenResp (in / get) + payloadGenRespValid : in sl; + payloadGenRespData : in slv(1 downto 0); + payloadGenRespReady : out sl; + -- payloadDataStreamPipeOut : DataStream (in) — consumed by the child only + payloadDataStreamValid : in sl; + payloadDataStreamData : in slv(289 downto 0); + payloadDataStreamRdEn : out sl; + + ----------------------------------------------------------------------- + -- Outputs + ----------------------------------------------------------------------- + -- pendingWorkReqPipeOut : PipeOut#(PendingWorkReq) + pendingWorkReqOutValid : out sl; + pendingWorkReqOutData : out slv(678 downto 0); + pendingWorkReqOutRdEn : in sl; + -- workCompGenReqPipeOut : PipeOut#(WorkCompGenReqSQ) + workCompGenReqValid : out sl; + workCompGenReqData : out slv(632 downto 0); + workCompGenReqRdEn : in sl; + -- rdmaReqDataStreamPipeOut : DataStreamPipeOut (from child) + rdmaReqDataValid : out sl; + rdmaReqDataData : out slv(289 downto 0); + rdmaReqDataRdEn : in sl; + -- method Bool reqHeaderOutNotEmpty() (combinational) + reqHeaderOutNotEmpty : out sl); +end entity ReqGenSq; + +architecture rtl of ReqGenSq is + + -- TypeQP encodings (4 bits) + constant QPT_RC_C : slv(3 downto 0) := x"2"; + constant QPT_UD_C : slv(3 downto 0) := x"4"; + constant QPT_XRC_SEND_C : slv(3 downto 0) := x"9"; + -- PMTU encodings (3 bits) + constant PMTU_256_C : slv(2 downto 0) := "001"; + constant PMTU_512_C : slv(2 downto 0) := "010"; + constant PMTU_1024_C : slv(2 downto 0) := "011"; + constant PMTU_2048_C : slv(2 downto 0) := "100"; + constant PMTU_4096_C : slv(2 downto 0) := "101"; + -- WorkReqOpCode encodings (4 bits) — DMA-read opcodes + read + constant WR_RDMA_WRITE_C : slv(3 downto 0) := x"0"; + constant WR_WRITE_IMM_C : slv(3 downto 0) := x"1"; + constant WR_SEND_C : slv(3 downto 0) := x"2"; + constant WR_SEND_IMM_C : slv(3 downto 0) := x"3"; + constant WR_RDMA_READ_C : slv(3 downto 0) := x"4"; + constant WR_SEND_INV_C : slv(3 downto 0) := x"9"; + -- DmaReqSrcType.DMA_SRC_SQ_RD (4 bits) + constant DMA_SRC_SQ_RD_C : slv(3 downto 0) := x"5"; + -- WorkCompReqType.WC_REQ_TYPE_PARTIAL_ACK (2 bits) / WorkCompStatus.IBV_WC_LOC_QP_OP_ERR (5 bits) + constant WC_REQ_PARTIAL_ACK_C : slv(1 downto 0) := "01"; + constant WC_LOC_QP_OP_ERR_C : slv(4 downto 0) := "00010"; + + -- Element / FIFO widths + constant PWR_W_C : integer := 679; -- PendingWorkReq + constant WCREQ_W_C : integer := 633; -- WorkCompGenReqSQ + constant WRPG_W_C : integer := 720; -- Tuple7(PWR,PktNum,ResiduePMTU,4xBool) + constant WRPKTNUM_W_C : integer := 709; -- Tuple3(PWR,PktNum,WorkReqInfo) + constant TUP2_W_C : integer := 684; -- Tuple2(PWR,WorkReqInfo) + constant REQHDRPREP_W_C : integer := 710; -- Tuple2(ReqPktHeaderInfo,WorkReqInfo) + constant PENDREQHDR_W_C : integer := 1229; -- Tuple4(PWR,WRInfo,Maybe(Tup3),PSN) + constant REQHDRGEN_W_C : integer := 1300; -- Tuple4(PWR,Maybe(HRDMA),Maybe(PGResp),PSN) + constant HRDMA_W_C : integer := 593; -- HeaderRDMA + constant PSN_W_C : integer := 24; -- PSN + + type RegType is record + isNormalStateReg : sl; -- mkReg(True) + isFirstOrOnlyReqPktReg : sl; -- mkReg(True) + remainingPktNumReg : slv(24 downto 0); -- mkRegU (loaded before use) + curPsnReg : slv(23 downto 0); -- mkRegU (loaded from startPSN) + end record RegType; + + -- remainingPktNumReg / curPsnReg are mkRegU (written before read); given '0' + -- for a defined start (REG_INIT don't-care per FSM spec). + constant REG_INIT_C : RegType := ( + isNormalStateReg => '1', + isFirstOrOnlyReqPktReg => '1', + remainingPktNumReg => (others => '0'), + curPsnReg => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal fifoRst : sl; + + -- FIFO interconnect + signal pwrOutDin : slv(PWR_W_C-1 downto 0); + signal pwrOutWrEn : sl; + signal pwrOutNotFull : sl; + + signal wcOutDin : slv(WCREQ_W_C-1 downto 0); + signal wcOutWrEn : sl; + signal wcOutNotFull : sl; + + signal wrPgDin : slv(WRPG_W_C-1 downto 0); + signal wrPgWrEn : sl; + signal wrPgDout : slv(WRPG_W_C-1 downto 0); + signal wrPgValid : sl; + signal wrPgNotFull : sl; + signal wrPgRdEn : sl; + + signal wrPktNumDin : slv(WRPKTNUM_W_C-1 downto 0); + signal wrPktNumWrEn : sl; + signal wrPktNumDout : slv(WRPKTNUM_W_C-1 downto 0); + signal wrPktNumValid : sl; + signal wrPktNumNotFull: sl; + signal wrPktNumRdEn : sl; + + signal wrPsnDin : slv(TUP2_W_C-1 downto 0); + signal wrPsnWrEn : sl; + signal wrPsnDout : slv(TUP2_W_C-1 downto 0); + signal wrPsnValid : sl; + signal wrPsnNotFull : sl; + signal wrPsnRdEn : sl; + + signal wrOutDin : slv(TUP2_W_C-1 downto 0); + signal wrOutWrEn : sl; + signal wrOutDout : slv(TUP2_W_C-1 downto 0); + signal wrOutValid : sl; + signal wrOutNotFull : sl; + signal wrOutRdEn : sl; + + signal wrChkDin : slv(TUP2_W_C-1 downto 0); + signal wrChkWrEn : sl; + signal wrChkDout : slv(TUP2_W_C-1 downto 0); + signal wrChkValid : sl; + signal wrChkNotFull : sl; + signal wrChkRdEn : sl; + + signal reqCntDin : slv(TUP2_W_C-1 downto 0); + signal reqCntWrEn : sl; + signal reqCntDout : slv(TUP2_W_C-1 downto 0); + signal reqCntValid : sl; + signal reqCntNotFull : sl; + signal reqCntRdEn : sl; + + signal reqPrepDin : slv(REQHDRPREP_W_C-1 downto 0); + signal reqPrepWrEn : sl; + signal reqPrepDout : slv(REQHDRPREP_W_C-1 downto 0); + signal reqPrepValid : sl; + signal reqPrepNotFull : sl; + signal reqPrepRdEn : sl; + + signal pendHdrDin : slv(PENDREQHDR_W_C-1 downto 0); + signal pendHdrWrEn : sl; + signal pendHdrDout : slv(PENDREQHDR_W_C-1 downto 0); + signal pendHdrValid : sl; + signal pendHdrNotFull : sl; + signal pendHdrRdEn : sl; + + signal hdrGenDin : slv(REQHDRGEN_W_C-1 downto 0); + signal hdrGenWrEn : sl; + signal hdrGenDout : slv(REQHDRGEN_W_C-1 downto 0); + signal hdrGenValid : sl; + signal hdrGenNotFull : sl; + signal hdrGenRdEn : sl; + + signal reqHdrOutDin : slv(HRDMA_W_C-1 downto 0); + signal reqHdrOutWrEn : sl; + signal reqHdrOutDout : slv(HRDMA_W_C-1 downto 0); + signal reqHdrOutValid : sl; + signal reqHdrOutNotFull : sl; + signal reqHdrOutRdEn : sl; + + signal psnOutDin : slv(PSN_W_C-1 downto 0); + signal psnOutWrEn : sl; + signal psnOutDout : slv(PSN_W_C-1 downto 0); + signal psnOutValid : sl; + signal psnOutNotFull : sl; + signal psnOutRdEn : sl; + + -- U_HeaderGenReqSQ interconnect (driven from reqHeaderPrepareQ.dout) + signal hpPwr : slv(678 downto 0); -- ReqPktHeaderInfo.pendingWR + signal hgIsFirstOrOnly : sl; + signal hgIsOnlyOrLast : sl; + signal hgHeaderValid : sl; + signal hgHeaderData : slv(511 downto 0); + signal hgHeaderByteNum : slv(6 downto 0); + signal hgHasPayload : sl; + +begin + + fifoRst <= rst or isReset; + + --------------------------------------------------------------------------- + -- 13 pipeline FIFOs (all surf.Fifo, FWFT, synchronous) + --------------------------------------------------------------------------- + U_PendingWorkReqOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PWR_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pwrOutWrEn, + din => pwrOutDin, + not_full => pwrOutNotFull, + rd_clk => clk, + rd_en => pendingWorkReqOutRdEn, + dout => pendingWorkReqOutData, + valid => pendingWorkReqOutValid, + empty => open); + + U_WorkCompGenReqOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => WCREQ_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => wcOutWrEn, + din => wcOutDin, + not_full => wcOutNotFull, + rd_clk => clk, + rd_en => workCompGenReqRdEn, + dout => workCompGenReqData, + valid => workCompGenReqValid, + empty => open); + + U_WorkReqPayloadGenQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => WRPG_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => wrPgWrEn, + din => wrPgDin, + not_full => wrPgNotFull, + rd_clk => clk, + rd_en => wrPgRdEn, + dout => wrPgDout, + valid => wrPgValid, + empty => open); + + U_WorkReqPktNumQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => WRPKTNUM_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => wrPktNumWrEn, + din => wrPktNumDin, + not_full => wrPktNumNotFull, + rd_clk => clk, + rd_en => wrPktNumRdEn, + dout => wrPktNumDout, + valid => wrPktNumValid, + empty => open); + + U_WorkReqPsnQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => TUP2_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => wrPsnWrEn, + din => wrPsnDin, + not_full => wrPsnNotFull, + rd_clk => clk, + rd_en => wrPsnRdEn, + dout => wrPsnDout, + valid => wrPsnValid, + empty => open); + + U_WorkReqOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => TUP2_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => wrOutWrEn, + din => wrOutDin, + not_full => wrOutNotFull, + rd_clk => clk, + rd_en => wrOutRdEn, + dout => wrOutDout, + valid => wrOutValid, + empty => open); + + U_WorkReqCheckQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => TUP2_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => wrChkWrEn, + din => wrChkDin, + not_full => wrChkNotFull, + rd_clk => clk, + rd_en => wrChkRdEn, + dout => wrChkDout, + valid => wrChkValid, + empty => open); + + U_ReqCountQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => TUP2_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqCntWrEn, + din => reqCntDin, + not_full => reqCntNotFull, + rd_clk => clk, + rd_en => reqCntRdEn, + dout => reqCntDout, + valid => reqCntValid, + empty => open); + + U_ReqHeaderPrepareQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => REQHDRPREP_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqPrepWrEn, + din => reqPrepDin, + not_full => reqPrepNotFull, + rd_clk => clk, + rd_en => reqPrepRdEn, + dout => reqPrepDout, + valid => reqPrepValid, + empty => open); + + U_PendingReqHeaderQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PENDREQHDR_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pendHdrWrEn, + din => pendHdrDin, + not_full => pendHdrNotFull, + rd_clk => clk, + rd_en => pendHdrRdEn, + dout => pendHdrDout, + valid => pendHdrValid, + empty => open); + + U_ReqHeaderGenQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => REQHDRGEN_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => hdrGenWrEn, + din => hdrGenDin, + not_full => hdrGenNotFull, + rd_clk => clk, + rd_en => hdrGenRdEn, + dout => hdrGenDout, + valid => hdrGenValid, + empty => open); + + U_ReqHeaderOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => HRDMA_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqHdrOutWrEn, + din => reqHdrOutDin, + not_full => reqHdrOutNotFull, + rd_clk => clk, + rd_en => reqHdrOutRdEn, + dout => reqHdrOutDout, + valid => reqHdrOutValid, + empty => open); + + U_PsnReqOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => PSN_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => psnOutWrEn, + din => psnOutDin, + not_full => psnOutNotFull, + rd_clk => clk, + rd_en => psnOutRdEn, + dout => psnOutDout, + valid => psnOutValid, + empty => open); + + --------------------------------------------------------------------------- + -- Internal children + --------------------------------------------------------------------------- + -- HeaderGenReqSQ is combinational; its inputs are the reqHeaderPrepareQ head + -- (ReqPktHeaderInfo + cntrlStatus bundle). Driven concurrently below. + hpPwr <= reqPrepDout(685 downto 7); -- ReqPktHeaderInfo.pendingWR + hgIsFirstOrOnly <= reqPrepDout(6); -- isFirstReqPkt + -- isOnlyOrLast = isFirstReqPkt ? isOnlyReqPkt(pendingWR val) : isLastReqPkt + hgIsOnlyOrLast <= reqPrepDout(7) when reqPrepDout(6) = '1' else reqPrepDout(5); + + U_HeaderGenReqSQ : entity surf.HeaderGenReqSQ + generic map ( + TPD_G => TPD_G) + port map ( + isFirstOrOnly => hgIsFirstOrOnly, + isOnlyOrLast => hgIsOnlyOrLast, + psn => reqPrepDout(709 downto 686), -- ReqPktHeaderInfo.curPSN + qpType => qpType, + pkey => pkey, + sigAll => sigAll, + commDqpn => dqpn, + sqpn => sqpn, + opcode => hpPwr(614 downto 611), + solicited => hpPwr(357), + sendSignaled => hpPwr(607), -- flags(1)=IBV_SEND_SIGNALED + len => hpPwr(509 downto 478), + raddr => hpPwr(605 downto 542), + rkey => hpPwr(541 downto 510), + wrDqpn => hpPwr(134 downto 111), -- Maybe#(QPN) value (tag dropped) + srqn => hpPwr(159 downto 136), -- Maybe#(QPN) value + qkey => hpPwr(109 downto 78), -- Maybe#(QKEY) value + swapData => hpPwr(290 downto 227), -- Maybe#(Long) value + compData => hpPwr(355 downto 292), -- Maybe#(Long) value + immDtData => hpPwr(225 downto 194), -- Maybe#(IMM) value + invRkey => hpPwr(192 downto 161), -- Maybe#(RKEY) value + headerValid => hgHeaderValid, + headerData => hgHeaderData, + headerByteNum => hgHeaderByteNum, + hasPayload => hgHasPayload); + + U_RdmaReqPipeOut : entity surf.CombineHeaderAndPayload + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false) + port map ( + clk => clk, + rst => rst, + clearAllI => isReset, + -- headerPipeIn <- reqHeaderOutQ + headerPipeInValid => reqHdrOutValid, + headerPipeInData => reqHdrOutDout, + headerPipeInRdEn => reqHdrOutRdEn, + -- payloadPipeIn <- external payloadGenerator.payloadDataStreamPipeOut + payloadPipeInValid => payloadDataStreamValid, + payloadPipeInData => payloadDataStreamData, + payloadPipeInRdEn => payloadDataStreamRdEn, + -- psnPipeIn <- psnReqOutQ (value unused; handshake only) + psnPipeInValid => psnOutValid, + psnPipeInData => psnOutDout, + psnPipeInRdEn => psnOutRdEn, + -- output -> rdmaReqDataStreamPipeOut + dataStreamOutValid => rdmaReqDataValid, + dataStreamOutData => rdmaReqDataData, + dataStreamOutRdEn => rdmaReqDataRdEn); + + --------------------------------------------------------------------------- + -- Combinational pipeline (11 conflict_free worker rules + mode/loop regs) + --------------------------------------------------------------------------- + comb : process (all) is + variable v : RegType; + + variable notReset : sl; + + -- R1 recvWorkReq + variable r1Opcode : slv(3 downto 0); + variable r1Len : slv(31 downto 0); + variable r1IsRC : sl; + variable r1IsUD : sl; + variable r1NeedDma : sl; + variable r1IsNew : sl; + variable r1Fence : sl; + variable r1ShouldDeq : sl; + variable r1TmpPkt : slv(24 downto 0); + variable r1Residue : slv(11 downto 0); + variable r1Guard : sl; + variable r1Fire : sl; + variable r1Do : sl; + + -- R2 issuePayloadGenReq + variable r2Pwr : slv(678 downto 0); + variable r2NeedDma : sl; + variable r2ZeroRes : sl; + variable r2Wi : slv(4 downto 0); + variable r2Guard : sl; + variable r2Fire : sl; + + -- R3 calcPktNum4NewWorkReq + variable r3Pwr : slv(678 downto 0); + variable r3Wi : slv(4 downto 0); + variable r3IsNew : sl; + variable r3ZeroRes : sl; + variable r3TmpPkt : slv(24 downto 0); + variable r3TotPkt : slv(24 downto 0); + variable r3IsOnly : sl; + variable r3Fire : sl; + + -- R4 calcPktSeqNum4NewWorkReq + variable r4Pwr : slv(678 downto 0); + variable r4Wi : slv(4 downto 0); + variable r4IsNew : sl; + variable r4TotPkt : slv(24 downto 0); + variable r4IsOnly : sl; + variable r4Opcode : slv(3 downto 0); + variable r4StartPsn : slv(23 downto 0); + variable r4NextPsn25 : slv(24 downto 0); + variable r4NextPsn : slv(23 downto 0); + variable r4EndPsn : slv(23 downto 0); + variable r4HasOnly : sl; + variable r4Fire : sl; + + -- R5 checkPendingWorkReq + variable r5Pwr : slv(678 downto 0); + variable r5Wi : slv(4 downto 0); + variable r5IsOnly : sl; + variable r5IsUD : sl; + variable r5Valid : sl; + variable r5Fire : sl; + + -- R6 outputNewPendingWorkReq + variable r6Pwr : slv(678 downto 0); + variable r6Wi : slv(4 downto 0); + variable r6Enq : sl; + variable r6Fire : sl; + variable r6DoEnq : sl; + + -- R7 countReqPkt (packet loop) + variable r7Pwr : slv(678 downto 0); + variable r7Wi : slv(4 downto 0); + variable r7StartPsn : slv(23 downto 0); + variable r7TotPkt : slv(24 downto 0); + variable r7IsOnly : sl; + variable r7LastOrOnly : sl; + variable r7FirstPkt : sl; + variable r7LastPkt : sl; + variable r7CurPsn : slv(23 downto 0); + variable r7RemPkt : slv(24 downto 0); + variable r7Rphi : slv(704 downto 0); + variable r7Fire : sl; + + -- R8 prepareReqHeaderGen + variable r8Fire : sl; + + -- R9 genReqHeader + variable r9Valid : sl; + variable r9NeedDma : sl; + variable r9GetResp : sl; + variable r9Hlen : slv(6 downto 0); + variable r9HlenInt : integer range 0 to 127; + variable r9ByteEn : slv(63 downto 0); + variable r9Frag : slv(1 downto 0); + variable r9Last : slv(5 downto 0); + variable r9Res5 : slv(4 downto 0); + variable r9Hdr : slv(592 downto 0); + variable r9MaybeHdr : slv(593 downto 0); + variable r9MaybeResp : slv(2 downto 0); + variable r9Fire : sl; + + -- R10 recvPayloadGenRespAndGenErrWorkComp + variable r10HasHdr : sl; + variable r10HasResp : sl; + variable r10RespErr : sl; + variable r10Success : sl; + variable r10Cond : sl; + variable r10Fire : sl; + + -- R11 errFlushWR + variable r11Pwr : slv(678 downto 0); + variable r11Enq : sl; + variable r11Guard : sl; + variable r11Fire : sl; + variable r11DoEnq : sl; + + begin + v := r; + notReset := not isReset; + + ---------------------------------------------------------------------- + -- Stage 1 : recvWorkReq (guard isStableRTS || isERR) + ---------------------------------------------------------------------- + r1Opcode := pendingWorkReqInData(614 downto 611); + r1Len := pendingWorkReqInData(509 downto 478); + r1IsRC := ite(qpType = QPT_RC_C or qpType = QPT_XRC_SEND_C, '1', '0'); + r1IsUD := ite(qpType = QPT_UD_C, '1', '0'); + r1NeedDma := ite((r1Opcode = WR_RDMA_WRITE_C or r1Opcode = WR_WRITE_IMM_C or + r1Opcode = WR_SEND_C or r1Opcode = WR_SEND_IMM_C or + r1Opcode = WR_SEND_INV_C) and r1Len /= x"00000000", '1', '0'); + r1IsNew := not pendingWorkReqInData(1); -- !isValid(isOnlyReqPkt) + r1Fence := pendingWorkReqInData(606); -- wr.flags(0)=IBV_SEND_FENCE + + if (isRTS = '1' and r1Fence = '1') then + r1ShouldDeq := not pendingWorkReqBufNotEmpty; -- fence: wait for buffer drain + else + r1ShouldDeq := not isSQD; -- SQ-drain stall + end if; + + -- truncateLenByPMTU(len, pmtu) -> (tmpReqPktNum:25, pmtuResidue:12) + r1TmpPkt := (others => '0'); + r1Residue := (others => '0'); + case pmtu is + when PMTU_256_C => + r1TmpPkt(23 downto 0) := r1Len(31 downto 8); + r1Residue(7 downto 0) := r1Len(7 downto 0); + when PMTU_512_C => + r1TmpPkt(22 downto 0) := r1Len(31 downto 9); + r1Residue(8 downto 0) := r1Len(8 downto 0); + when PMTU_1024_C => + r1TmpPkt(21 downto 0) := r1Len(31 downto 10); + r1Residue(9 downto 0) := r1Len(9 downto 0); + when PMTU_2048_C => + r1TmpPkt(20 downto 0) := r1Len(31 downto 11); + r1Residue(10 downto 0) := r1Len(10 downto 0); + when others => -- PMTU_4096_C + r1TmpPkt(19 downto 0) := r1Len(31 downto 12); + r1Residue(11 downto 0) := r1Len(11 downto 0); + end case; + + r1Guard := notReset and (isStableRTS or isERR) and pendingWorkReqInValid; + r1Fire := r1Guard and (not r1ShouldDeq or wrPgNotFull); + r1Do := r1Fire and r1ShouldDeq; + + pendingWorkReqInRdEn <= r1Do; + wrPgWrEn <= r1Do; + -- Tuple7(pendingWR, tmpReqPktNum, pmtuResidue, needDmaRead, isNewWorkReq, + -- isReliableConnection, isUnreliableDatagram) + wrPgDin <= pendingWorkReqInData & r1TmpPkt & r1Residue & + r1NeedDma & r1IsNew & r1IsRC & r1IsUD; + + ---------------------------------------------------------------------- + -- Stage 2 : issuePayloadGenReq (guard isStableRTS && isNormalStateReg) + ---------------------------------------------------------------------- + r2Pwr := wrPgDout(719 downto 41); + r2NeedDma := wrPgDout(3); + r2ZeroRes := ite(wrPgDout(15 downto 4) = "000000000000", '1', '0'); + -- WorkReqInfo = isNew & isZeroResidue & isRC & isUD & needDma + r2Wi := wrPgDout(2) & r2ZeroRes & wrPgDout(1) & wrPgDout(0) & wrPgDout(3); + + r2Guard := notReset and isStableRTS and r.isNormalStateReg and + wrPgValid and wrPktNumNotFull; + r2Fire := r2Guard and (not r2NeedDma or payloadGenReqReady); + + payloadGenReqValid <= r2Fire and r2NeedDma; + -- PayloadGenReq: {initiator,sqpn,wrID,startAddr,len,mrIdx}, addPadding, pmtu + payloadGenReqData <= DMA_SRC_SQ_RD_C & -- initiator = DMA_SRC_SQ_RD + sqpn & -- cntrlStatus.comm.getSQPN + r2Pwr(678 downto 615) & -- wr.id (WorkReqID) + r2Pwr(477 downto 414) & -- wr.laddr (startAddr) + r2Pwr(509 downto 478) & -- wr.len + r2Pwr(413 downto 407) & -- key2IndexMR(wr.lkey)=lkey[31:25] + '1' & -- addPadding = True + pmtu; -- cntrlStatus.comm.getPMTU + + wrPktNumWrEn <= r2Fire; + -- Tuple3(pendingWR, tmpReqPktNum, workReqInfo) + wrPktNumDin <= r2Pwr & wrPgDout(40 downto 16) & r2Wi; + + ---------------------------------------------------------------------- + -- Stage 3 : calcPktNum4NewWorkReq (guard isStableRTS && isNormalStateReg) + ---------------------------------------------------------------------- + r3Pwr := wrPktNumDout(708 downto 30); + r3TmpPkt := wrPktNumDout(29 downto 5); + r3Wi := wrPktNumDout(4 downto 0); + r3IsNew := r3Wi(4); + r3ZeroRes := r3Wi(3); + + if (r3ZeroRes = '1') then + r3TotPkt := r3TmpPkt; + else + r3TotPkt := slv(unsigned(r3TmpPkt) + 1); + end if; + r3IsOnly := ite(unsigned(r3TotPkt) <= 1, '1', '0'); -- isLessOrEqOneR + + if (r3IsNew = '1') then + r3Pwr(27) := '1'; -- pktNum := Valid totalPktNum + r3Pwr(26 downto 2) := r3TotPkt; + r3Pwr(1) := '1'; -- isOnlyReqPkt := Valid isOnlyPkt + r3Pwr(0) := r3IsOnly; + end if; + + r3Fire := notReset and isStableRTS and r.isNormalStateReg and + wrPktNumValid and wrPsnNotFull; + + wrPktNumRdEn <= r3Fire; + wrPsnWrEn <= r3Fire; + wrPsnDin <= r3Pwr & r3Wi; -- Tuple2(pendingWR, workReqInfo) + + ---------------------------------------------------------------------- + -- Stage 4 : calcPktSeqNum4NewWorkReq (guard isStableRTS && isNormalStateReg) + ---------------------------------------------------------------------- + r4Pwr := wrPsnDout(683 downto 5); + r4Wi := wrPsnDout(4 downto 0); + r4IsNew := r4Wi(4); + r4TotPkt := r4Pwr(26 downto 2); -- unwrap pktNum + r4IsOnly := r4Pwr(0); -- unwrap isOnlyReqPkt + r4Opcode := r4Pwr(614 downto 611); + r4StartPsn := npsnIn; -- contextSQ.getNPSN + + -- calcNextAndEndPSN(startPSN, pktNum, isOnlyPkt, pmtu) + if (r4IsOnly = '1') then + r4NextPsn := slv(unsigned(r4StartPsn) + 1); + r4EndPsn := r4StartPsn; + else + r4NextPsn25 := slv(resize(unsigned(r4StartPsn), 25) + unsigned(r4TotPkt)); + r4NextPsn := r4NextPsn25(23 downto 0); + r4EndPsn := slv(unsigned(r4NextPsn) - 1); + end if; + r4HasOnly := r4IsOnly or ite(r4Opcode = WR_RDMA_READ_C, '1', '0'); + + if (r4IsNew = '1') then + r4Pwr(77) := '1'; -- startPSN := Valid startPSN + r4Pwr(76 downto 53) := r4StartPsn; + r4Pwr(52) := '1'; -- endPSN := Valid endPSN + r4Pwr(51 downto 28) := r4EndPsn; + r4Pwr(1) := '1'; -- isOnlyReqPkt := Valid hasOnlyReqPkt + r4Pwr(0) := r4HasOnly; + end if; + + r4Fire := notReset and isStableRTS and r.isNormalStateReg and + wrPsnValid and wrChkNotFull; + + npsnWrEn <= r4Fire and r4IsNew; -- contextSQ.setNPSN + npsnOut <= r4NextPsn; + + wrPsnRdEn <= r4Fire; + wrChkWrEn <= r4Fire; + wrChkDin <= r4Pwr & r4Wi; -- Tuple2(pendingWR, workReqInfo) + + ---------------------------------------------------------------------- + -- Stage 5 : checkPendingWorkReq (guard isStableRTS && isNormalStateReg) + ---------------------------------------------------------------------- + r5Pwr := wrChkDout(683 downto 5); + r5Wi := wrChkDout(4 downto 0); + r5IsOnly := r5Pwr(0); + r5IsUD := r5Wi(1); + r5Valid := (not r5IsUD) or r5IsOnly; -- isValidWorkReq + + r5Fire := notReset and isStableRTS and r.isNormalStateReg and + wrChkValid and wrOutNotFull and (not r5Valid or reqCntNotFull); + + wrChkRdEn <= r5Fire; + reqCntWrEn <= r5Fire and r5Valid; + reqCntDin <= r5Pwr & r5Wi; + wrOutWrEn <= r5Fire; + wrOutDin <= r5Pwr & r5Wi; + + ---------------------------------------------------------------------- + -- Stage 6 : outputNewPendingWorkReq (guard isStableRTS && isNormalStateReg) + ---------------------------------------------------------------------- + r6Pwr := wrOutDout(683 downto 5); + r6Wi := wrOutDout(4 downto 0); + r6Enq := r6Wi(4) and r6Wi(2); -- isNewWorkReq && isReliableConnection + + r6Fire := notReset and isStableRTS and r.isNormalStateReg and + wrOutValid and (not r6Enq or pwrOutNotFull); + wrOutRdEn <= r6Fire; + r6DoEnq := r6Fire and r6Enq; + + ---------------------------------------------------------------------- + -- Stage 7 : countReqPkt (packet loop) (guard isStableRTS && isNormalStateReg) + ---------------------------------------------------------------------- + r7Pwr := reqCntDout(683 downto 5); + r7Wi := reqCntDout(4 downto 0); + r7StartPsn := r7Pwr(76 downto 53); -- unwrap startPSN + r7TotPkt := r7Pwr(26 downto 2); -- unwrap pktNum + r7IsOnly := r7Pwr(0); -- unwrap isOnlyReqPkt + + r7LastOrOnly := r7IsOnly or + ((not r.isFirstOrOnlyReqPktReg) and + ite(unsigned(r.remainingPktNumReg) = 0, '1', '0')); + r7FirstPkt := r.isFirstOrOnlyReqPktReg; + r7LastPkt := r7LastOrOnly; + + r7CurPsn := r.curPsnReg; + r7RemPkt := r.remainingPktNumReg; + if (r.isFirstOrOnlyReqPktReg = '1') then + r7CurPsn := r7StartPsn; + if (r7IsOnly = '1') then + r7RemPkt := (others => '0'); + else + r7RemPkt := slv(unsigned(r7TotPkt) - 2); + end if; + elsif (r7LastPkt = '0') then + r7RemPkt := slv(unsigned(r.remainingPktNumReg) - 1); + end if; + + r7Fire := notReset and isStableRTS and r.isNormalStateReg and + reqCntValid and reqPrepNotFull; + + reqCntRdEn <= r7Fire and r7LastOrOnly; -- deq only on last/only packet + + -- ReqPktHeaderInfo(curPSN, pendingWR, isFirstReqPkt, isLastReqPkt) + r7Rphi := r7CurPsn & r7Pwr & r7FirstPkt & r7LastPkt; + reqPrepWrEn <= r7Fire; + reqPrepDin <= r7Rphi & r7Wi; -- Tuple2(ReqPktHeaderInfo, workReqInfo) + + if (r7Fire = '1') then + if (r7LastOrOnly = '1') then + v.isFirstOrOnlyReqPktReg := '1'; + else + v.isFirstOrOnlyReqPktReg := '0'; + end if; + v.remainingPktNumReg := r7RemPkt; + v.curPsnReg := slv(unsigned(r7CurPsn) + 1); + end if; + + ---------------------------------------------------------------------- + -- Stage 8 : prepareReqHeaderGen (drives U_HeaderGenReqSQ, enq pendingReqHeaderQ) + ---------------------------------------------------------------------- + -- HeaderGenReqSQ combinational outputs (hgHeaderValid/Data/ByteNum/HasPayload) + -- are wired concurrently from reqPrepDout above. + r8Fire := notReset and isStableRTS and r.isNormalStateReg and + reqPrepValid and pendHdrNotFull; + reqPrepRdEn <= r8Fire; + pendHdrWrEn <= r8Fire; + -- Tuple4(pendingWR, workReqInfo, Maybe(Tuple3(headerData,headerByteNum,hasPayload)), curPSN) + pendHdrDin <= hpPwr & reqPrepDout(4 downto 0) & + hgHeaderValid & hgHeaderData & hgHeaderByteNum & hgHasPayload & + reqPrepDout(709 downto 686); + + ---------------------------------------------------------------------- + -- Stage 9 : genReqHeader (guard isStableRTS && isNormalStateReg) + ---------------------------------------------------------------------- + r9Valid := pendHdrDout(544); + r9NeedDma := pendHdrDout(545); -- workReqInfo.needDmaRead + r9GetResp := r9Valid and r9NeedDma; + r9Hlen := pendHdrDout(31 downto 25); + r9HlenInt := to_integer(unsigned(r9Hlen)); + + -- genHeaderRDMA: byteEn = headerLen ones at MSB + for i in 0 to 63 loop + if (i < r9HlenInt) then + r9ByteEn(63 - i) := '1'; + else + r9ByteEn(63 - i) := '0'; + end if; + end loop; + r9Res5 := r9Hlen(4 downto 0); + if (r9Res5 /= "00000") then + r9Frag := slv(unsigned(r9Hlen(6 downto 5)) + 1); + else + r9Frag := r9Hlen(6 downto 5); + end if; + if (r9Res5 /= "00000") then + r9Last := "0" & r9Res5; + elsif (r9Hlen(6 downto 5) /= "00") then + r9Last := toSlv(32, 6); + else + r9Last := (others => '0'); + end if; + -- HeaderRDMA = headerData & byteEn & headerLen & fragNum & lastValid & hasPayload & isEmptyHeader + r9Hdr := pendHdrDout(543 downto 32) & r9ByteEn & r9Hlen & r9Frag & r9Last & + pendHdrDout(24) & '0'; + r9MaybeHdr := r9Valid & r9Hdr; -- Maybe#(HeaderRDMA) + r9MaybeResp := r9GetResp & payloadGenRespData; -- Maybe#(PayloadGenResp) + + r9Fire := notReset and isStableRTS and r.isNormalStateReg and + pendHdrValid and hdrGenNotFull and (not r9GetResp or payloadGenRespValid); + + pendHdrRdEn <= r9Fire; + payloadGenRespReady <= r9Fire and r9GetResp; -- response.get + hdrGenWrEn <= r9Fire; + -- Tuple4(pendingWR, maybeReqHeader, maybePayloadGenResp, triggerPSN) + hdrGenDin <= pendHdrDout(1228 downto 550) & r9MaybeHdr & r9MaybeResp & + pendHdrDout(23 downto 0); + + ---------------------------------------------------------------------- + -- Stage 10 : recvPayloadGenRespAndGenErrWorkComp + ---------------------------------------------------------------------- + r10HasHdr := hdrGenDout(620); + r10HasResp := hdrGenDout(26); + r10RespErr := hdrGenDout(24); + r10Success := r10HasHdr and (not r10HasResp or not r10RespErr); + if (r10Success = '1') then + r10Cond := reqHdrOutNotFull and psnOutNotFull; + else + r10Cond := wcOutNotFull; + end if; + r10Fire := notReset and isStableRTS and r.isNormalStateReg and + hdrGenValid and r10Cond; + + hdrGenRdEn <= r10Fire; + -- success -> reqHeaderOutQ + psnReqOutQ + reqHdrOutWrEn <= r10Fire and r10Success; + reqHdrOutDin <= hdrGenDout(619 downto 27); -- HeaderRDMA + psnOutWrEn <= r10Fire and r10Success; + psnOutDin <= hdrGenDout(23 downto 0); -- triggerPSN + -- error -> workCompGenReqOutQ + isNormalStateReg := False + wcOutWrEn <= r10Fire and (not r10Success); + -- WorkCompGenReqSQ(wr, wcWaitDmaResp=False, WC_REQ_TYPE_PARTIAL_ACK, triggerPSN, IBV_WC_LOC_QP_OP_ERR) + wcOutDin <= hdrGenDout(1299 downto 699) & -- pendingWR.wr + '0' & WC_REQ_PARTIAL_ACK_C & + hdrGenDout(23 downto 0) & WC_LOC_QP_OP_ERR_C; + if (r10Fire = '1' and r10Success = '0') then + v.isNormalStateReg := '0'; + end if; + + ---------------------------------------------------------------------- + -- Stage 11 : errFlushWR (guard isERR || (isRTS && !isNormalStateReg)) + ---------------------------------------------------------------------- + r11Pwr := wrPgDout(719 downto 41); + r11Enq := wrPgDout(2) and wrPgDout(1); -- isNewWorkReq && isReliableConnection + r11Guard := notReset and (isERR or (isRTS and not r.isNormalStateReg)) and wrPgValid; + r11Fire := r11Guard and (not r11Enq or pwrOutNotFull); + r11DoEnq := r11Fire and r11Enq; + + -- workReqPayloadGenQ dequeued by R2 (normal) or R11 (err-flush) — mutually + -- exclusive on the mode bit / QP status (FSM spec Conflicts/scheduling). + wrPgRdEn <= r2Fire or r11Fire; + + -- pendingWorkReqOutQ enqueued by R6 (normal) or R11 (err-flush) — mutually + -- exclusive on the mode bit. + if (r6DoEnq = '1') then + pwrOutWrEn <= '1'; + pwrOutDin <= r6Pwr; + elsif (r11DoEnq = '1') then + pwrOutWrEn <= '1'; + pwrOutDin <= r11Pwr; + else + pwrOutWrEn <= '0'; + pwrOutDin <= (others => '0'); + end if; + + ---------------------------------------------------------------------- + -- resetAndClear : while isReset asserted force mode/loop bits + ---------------------------------------------------------------------- + if (isReset = '1') then + v.isNormalStateReg := '1'; + v.isFirstOrOnlyReqPktReg := '1'; + end if; + + -- synchronous FPGA reset + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + + ---------------------------------------------------------------------- + -- Combinational method output + ---------------------------------------------------------------------- + reqHeaderOutNotEmpty <= psnOutValid; -- psnReqOutQ.notEmpty + + end process comb; + + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ReqHandleRq.vhd b/ethernet/RoCEv2/rtl/ReqHandleRq.vhd new file mode 100644 index 0000000000..a3f65fe995 --- /dev/null +++ b/ethernet/RoCEv2/rtl/ReqHandleRq.vhd @@ -0,0 +1,2777 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- The RQ request-handling datapath: a 32-stage linear pipeline of SURF FIFOs +-- (supportedReqOpCodeCheckQ -> ... -> pendingRespQ -> {respHeaderOutQ, +-- psnRespOutQ, workCompReqQ} -> workCompGenReqOutQ) wrapped by five control +-- machines that thread registers across the pipeline (⚑S3 OQ-PART-01 RESOLVED: +-- KEEP FUSED — the error/retry control plane defeats the FIFO-boundary cut). +-- +-- The five control sub-FSMs (RegType blocks A–E): +-- A pre-stage FSM : preStageState (build -> calc -> done) meters one +-- packet at a time into the pipeline. +-- B retry FSM : retryState + retryStart CReg(2) + RNR-wait counter. +-- C error/flush mode : hasReqStatusErr/hasDmaReadRespErr/hasErrRespGen -> +-- hasErrHappened/inErrorState; errFlush rules. +-- D response-packet loop: isFirstOrOnlyRespPkt inside countPendingResp. +-- E coalesce counter : coalesceWorkReqCnt + isCoalesceWorkReqCntZero. +-- +-- CReg(2) intra-cycle forward (OQ-FSM-RHR-02): retryStartReg port-0 write in +-- triggerRNR (stage 4) is visible to the port-1 read in retryStart (retry FSM) +-- the SAME cycle. Enforced by comb ordering: the pipeline block (incl. stage 4) +-- runs BEFORE the retry-rule block, so retryStart reads v.retryStart* (already +-- written by triggerRNR) not r.retryStart*. +-- +-- contextRQ shared registers (OQ-FSM-RHR-01) are external port pairs, NOT local +-- state: getEpoch/incEpoch, getEPSN, getRespPktNum/setRespPktNum, getIsRespPktNumZero. +-- +-- Child instances (NOT SURF, NOT state): +-- U_PendingDestReadAtomicReqCnt : CountCF (RQ-02, full incrQ/decrQ/cntReg) +-- U_AtomicSrv : AtomicSrvConAndGen (RQ-06 STUB — genResp sets +-- original := compData; CAS/FetchAdd NOT implemented) +-- U_RdmaRespPipeOut : CombineHeaderAndPayload (drives rdmaRespDataStreamPipeOut) +-- +-- FIFO clear: BSV FIFOF.clear under resetAndClear -> fifoClr = rst or isReset, +-- asserted to every Fifo rst (level-safe sync clear; OQ-FSM-01 carry-forward). +-- +-- *** STAGED EMIT — PHASE 2 DONE (front end + perm-check build/query stages 5-8) *** +-- Phase 0 emitted the full compilable STRUCTURE (entity, 35 surf.Fifo, 3 children, +-- RegType/REG_INIT_C, control-FSM scaffolding + per-stage handshake/back-pressure). +-- PHASE 1 fills the error-free request-classification front end: +-- pre-stage A (preBuildReqInfo/preCalcReqInfo/checkEPSN): BTH/RETH parse, +-- opcode classify, truncateLenByPMTU, access check, ePSN check + setEPSN; +-- stages 1-4 (checkSupportedReqOpCode/checkNormalReqOpCodeSeq/checkRNR/triggerRNR): +-- opcode-support, opcode-seq (setPreReqOpCode), RNR + recvReqBuf + restore, +-- retry trigger (retryStartReg CReg port-0 write + incEpoch + minRnrTimer); +-- retry FSM downstream rules (retryStart/RnrRetryFlush/RnrWait/retryDone) + +-- getRnrTimeOutValue LUT. Added contextRQ ports: setEPSN, getPreReqOpCode, +-- setPreReqOpCode, restorePreReqOpCodeAndEPSN (OQ-FSM-RHR-01 external RMW). +-- PHASE 2 fills the permission-check build/query chain: +-- stage 5 checkQpAccPermAndReadAtomicReqNum (CountCF incrOne + read/atomic +-- over-limit -> InvReqStatus); stage 6a buildPermCheckReq4SendWrite and +-- 6b buildPermCheckReq4ReadAtomic (PermCheckReq construction from RecvReq/ +-- RETH/AtomicEth, ERR_FLUSH_RR override, multi-pkt setPermCheckReq/getPermCheckReq +-- carry); stage 7 queryPerm4NormalReq (conditional permCheckSrv.request.put + +-- expectPermCheckResp); stage 8 checkPerm4NormalReq (conditional response.get, +-- atomic-addr alignment, RMT_ACC on failure). Added contextRQ ports: +-- getPermCheckReq/setPermCheckReq (OQ-FSM-RHR-01 external RMW). +-- Stages 9-31 datapath remains `-- TODO(phase N): ` (phases 3-9); those +-- output FIFOs still carry-through/zero their din. Do NOT trust full functional +-- behaviour until phases 2-9 are complete and Stage-5 verified. See the plan file +-- and ReqHandleRq.tb-spec.md §9. +-- +-- Type widths (BSV deriving(Bits), first-field-at-MSB; traced from DataTypes.bsv/ +-- Headers.bsv/ReqHandleRQ.bsv): leaf PSN/QPN/MSN=24, ADDR/Long/WorkReqID=64, +-- Length/RKEY/LKEY/IMM=32, PKEY=16, PktLen=13, PktFragNum=8, PktNum=25, RnrTimer=5, +-- Epoch=1, RdmaOpCode/WorkCompStatus=5, HandlerPD=32, IndexMR=7, BTH=96, AETH=32, +-- RETH=128, AtomicEth=224, AtomicAckEth=64, HeaderRDMA=593, RdmaPktMetaData=649, +-- PermCheckReq=267, DataStream=290. Enums RdmaReqStatus=4, RetryStateRQ=3, +-- PreStageStateRQ=2, DupReadReqStartState=1, TypeQP=4, DmaReqSrcType=4. +-- Structs RdmaReqPktInfo=161, RespPktGenInfo=73, RespPktSeqInfo=2, +-- RespPktHeaderInfo=50, ReqLenCheckResult=130, EnoughDmaSpaceCheck=4, +-- WorkCompGenReqRQ=198, Maybe#RecvReq=217, Maybe#HeaderRDMA=594, RecvReq=216, +-- ReadCacheItem=176, AtomicCacheItem=317, PayloadGenReq=199, PayloadGenResp=2, +-- PayloadConReq=203, AtomicOpReq=245, AtomicOpResp=116, +-- Maybe#Tuple3(ReadCacheItem,ADDR,DupReadReqStartState)=242, Maybe#AtomicCacheItem=318. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ReqHandleRq is + generic ( + TPD_G : time := 1 ns; + -- false = no RDMA READ/atomic serving: read/atomic-request classifiers + -- are forced false, so incoming READ/CMP_SWP/FETCH_ADD requests take the + -- existing unsupported-opcode NAK-INV_REQ path and the read/atomic + -- serving datapath (dup cache, payload gen, atomic srv) constant-folds. + EN_READ_G : boolean := true); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + ----------------------------------------------------------------------- + -- contextRQ.statusRQ.comm status methods (combinational inputs) + ----------------------------------------------------------------------- + isReset : in sl; -- comm.isReset -> resetAndClear + isNonErr : in sl; -- comm.isNonErr + isERR : in sl; -- comm.isERR + getTypeQP : in slv(3 downto 0); -- TypeQP enum + getPMTU : in slv(2 downto 0); -- PMTU enum (256="001"..4096="101") + getPKEY : in slv(15 downto 0); + getSQPN : in slv(23 downto 0); + getDQPN : in slv(23 downto 0); + getMinRnrTimer : in slv(4 downto 0); -- RnrTimer + getAccessFlags : in slv(7 downto 0); -- FlagsType#(MemAccessTypeFlag) + getPendingWorkReqNum : in slv(7 downto 0); -- PendingReqCnt + getPendingDestReadAtomicReqNum : in slv(7 downto 0); -- PendingReqCnt + ----------------------------------------------------------------------- + -- contextRQ shared registers (OQ-FSM-RHR-01; external RMW, NOT local state) + ----------------------------------------------------------------------- + getEpoch : in sl; -- Epoch (1b) + incEpoch : out sl; -- pulse: contextRQ.incEpoch + getEPSN : in slv(23 downto 0); -- expected PSN + getRespPktNum : in slv(24 downto 0); -- PktNum + setRespPktNumValid : out sl; -- setRespPktNum write-enable + setRespPktNumData : out slv(24 downto 0); + getIsRespPktNumZero : in sl; + -- expected-PSN write-back (contextRQ.setEPSN; checkEPSN advances ePSN) + setEPSNValid : out sl; -- setEPSN write-enable + setEPSNData : out slv(23 downto 0); -- PSN + -- previous request opcode (contextRQ.getPreReqOpCode / setPreReqOpCode; RdmaOpCode 5b) + getPreReqOpCode : in slv(4 downto 0); + setPreReqOpCodeValid : out sl; -- setPreReqOpCode write-enable + setPreReqOpCodeData : out slv(4 downto 0); + -- combined restore (contextRQ.restorePreReqOpCodeAndEPSN; checkRNR RNR path) + restoreValid : out sl; -- restorePreReqOpCodeAndEPSN write-enable + restorePreOpCodeData : out slv(4 downto 0); -- RdmaOpCode + restorePsnData : out slv(23 downto 0); -- PSN + -- multi-packet perm-check carry (contextRQ.getPermCheckReq / setPermCheckReq; PermCheckReq 267b) + getPermCheckReq : in slv(266 downto 0); + setPermCheckReqValid : out sl; -- setPermCheckReq write-enable + setPermCheckReqData : out slv(266 downto 0); + -- DMA-write context registers (Phase 4; contextRQ get/set per multi-packet send/write) + getNextDmaWriteAddr : in slv(63 downto 0); -- ADDR + setNextDmaWriteAddrValid : out sl; -- setNextDmaWriteAddr write-enable + setNextDmaWriteAddrData : out slv(63 downto 0); + getSendWriteReqPktNum : in slv(24 downto 0); -- PktNum + setSendWriteReqPktNumValid : out sl; -- setSendWriteReqPktNum write-enable + setSendWriteReqPktNumData : out slv(24 downto 0); + getRemainingDmaWriteLen : in slv(31 downto 0); -- Length + setRemainingDmaWriteLenValid : out sl; -- setRemainingDmaWriteLen write-enable + setRemainingDmaWriteLenData : out slv(31 downto 0); + getTotalDmaWriteLen : in slv(31 downto 0); -- Length + setTotalDmaWriteLenValid : out sl; -- setTotalDmaWriteLen write-enable + setTotalDmaWriteLenData : out slv(31 downto 0); + -- response PSN/MSN context registers (Phase 7; stage 23 updateRespPsnAndMsn) + getCurRespPSN : in slv(23 downto 0); -- PSN (current response PSN) + setCurRespPSNValid : out sl; -- setCurRespPSN write-enable + setCurRespPSNData : out slv(23 downto 0); + getMSN : in slv(23 downto 0); -- MSN + setMSNValid : out sl; -- setMSN write-enable + setMSNData : out slv(23 downto 0); + ----------------------------------------------------------------------- + -- pktMetaDataPipeIn : PipeOut#(RdmaPktMetaData) (649b) + ----------------------------------------------------------------------- + pktMetaValid : in sl; -- .notEmpty + pktMetaData : in slv(648 downto 0); -- .first + pktMetaDeq : out sl; -- .deq + ----------------------------------------------------------------------- + -- recvReqBuf : RecvReqBuf (RecvReq 216b) — .first/.deq/.notEmpty + ----------------------------------------------------------------------- + recvReqValid : in sl; + recvReqData : in slv(215 downto 0); + recvReqDeq : out sl; + ----------------------------------------------------------------------- + -- payloadConReqPort : Put#(PayloadConReq) (203b) + ----------------------------------------------------------------------- + payloadConReqValid : out sl; + payloadConReqData : out slv(202 downto 0); + payloadConReqReady : in sl; + ----------------------------------------------------------------------- + -- permCheckSrv : Server#(PermCheckReq (267b), Bool) + ----------------------------------------------------------------------- + permReqValid : out sl; + permReqData : out slv(266 downto 0); + permReqReady : in sl; + permRespValid : in sl; + permRespData : in sl; -- mrCheckResult + permRespGetEn : out sl; + ----------------------------------------------------------------------- + -- payloadGenerator : Server#(PayloadGenReq (199b), PayloadGenResp (2b)) + -- + payloadDataStreamPipeOut : DataStream (290b) + ----------------------------------------------------------------------- + payloadGenReqValid : out sl; + payloadGenReqData : out slv(198 downto 0); + payloadGenReqReady : in sl; + payloadGenRespValid : in sl; + payloadGenRespData : in slv(1 downto 0); + payloadGenRespGetEn : out sl; + payloadDataStreamValid : in sl; + payloadDataStreamData : in slv(289 downto 0); + payloadDataStreamRdEn : out sl; + ----------------------------------------------------------------------- + -- dupReadAtomicCache : DupReadAtomicCache + ----------------------------------------------------------------------- + insertReadValid : out sl; -- insertRead(ReadCacheItem 176b) + insertReadData : out slv(175 downto 0); + insertReadReady : in sl; + searchReadReqValid : out sl; -- searchReadReq(ReadCacheItem 176b) + searchReadReqData : out slv(175 downto 0); + searchReadReqReady : in sl; + searchReadRespValid : in sl; -- searchReadResp Maybe#Tuple3 (242b) + searchReadRespData : in slv(241 downto 0); + searchReadRespGetEn : out sl; + insertAtomicValid : out sl; -- insertAtomic(AtomicCacheItem 317b) + insertAtomicData : out slv(316 downto 0); + insertAtomicReady : in sl; + searchAtomicReqValid : out sl; -- searchAtomicReq(AtomicCacheItem 317b) + searchAtomicReqData : out slv(316 downto 0); + searchAtomicReqReady : in sl; + searchAtomicRespValid : in sl; -- searchAtomicResp Maybe#AtomicCacheItem (318b) + searchAtomicRespData : in slv(317 downto 0); + searchAtomicRespGetEn : out sl; + dupCacheClear : out sl; -- clear() pulse (from isReset) + ----------------------------------------------------------------------- + -- Outputs + ----------------------------------------------------------------------- + -- rdmaRespDataStreamPipeOut : DataStreamPipeOut (290b) — from U_RdmaRespPipeOut + rdmaRespDataStreamValid : out sl; + rdmaRespDataStreamData : out slv(289 downto 0); + rdmaRespDataStreamRdEn : in sl; + -- workCompGenReqPipeOut : PipeOut#(WorkCompGenReqRQ) (198b) + workCompGenReqValid : out sl; + workCompGenReqData : out slv(197 downto 0); + workCompGenReqRdEn : in sl; -- downstream .deq + -- respHeaderOutNotEmpty() = psnRespOutQ.notEmpty (combinational Mealy method) + respHeaderOutNotEmpty : out sl); +end entity ReqHandleRq; + +architecture rtl of ReqHandleRq is + + --------------------------------------------------------------------------- + -- Control-FSM state enums + --------------------------------------------------------------------------- + -- Block A — PreStageStateRQ (BSV 4-member enum; RQ_PRE_RETRY_FLUSH unused in rules) + type PreStageStateType is ( + RQ_PRE_BUILD_STAGE_S, + RQ_PRE_CALC_STAGE_S, + RQ_PRE_STAGE_DONE_S, + RQ_PRE_RETRY_FLUSH_S); + -- Block B — RetryStateRQ + type RetryStateType is ( + RQ_SEQ_RETRY_FLUSH_S, + RQ_RNR_RETRY_FLUSH_S, + RQ_RNR_WAIT_S, + RQ_RNR_WAIT_DONE_S, + RQ_NOT_RETRY_S); + + --------------------------------------------------------------------------- + -- RegType : ONE fused record; sub-FSM blocks A–E delimited below. + --------------------------------------------------------------------------- + type RegType is record + -- (A) pre-stage control FSM + its mkRegU latch registers + preStageState : PreStageStateType; + preStagePktMetaData : slv(648 downto 0); -- mkRegU + preStageReqStatus : slv(3 downto 0); -- mkRegU (RdmaReqStatus) + preStageReqPktInfo : slv(160 downto 0); -- mkRegU (RdmaReqPktInfo) + preStageIsZeroPmtuResidue : sl; -- mkRegU + -- (B) retry FSM + retryState : RetryStateType; + retryStartValid : sl; -- mkCReg(2) Maybe tag + retryStartState : RetryStateType; -- mkCReg(2) Maybe value + rnrWaitCnt : slv(28 downto 0); -- mkRegU (RNR_WAIT_CYCLE_CNT_WIDTH=29) + minRnrTimer : slv(4 downto 0); -- mkRegU (RnrTimer) + isRnrWaitCntZero : sl; -- mkRegU + -- (C) error/flush mode flags (all mkReg False) + hasReqStatusErr : sl; + hasDmaReadRespErr : sl; + hasErrRespGen : sl; + -- (D) response-packet loop + isFirstOrOnlyRespPkt : sl; -- mkReg True + -- (E) coalesce counter + coalesceWorkReqCnt : slv(7 downto 0); -- mkCount(MAX_QP_WR-1=31) + isCoalesceWorkReqCntZero : sl; + end record RegType; + + constant COALESCE_INIT_C : slv(7 downto 0) := std_logic_vector(to_unsigned(31, 8)); -- MAX_QP_WR-1 + + constant REG_INIT_C : RegType := ( + preStageState => RQ_PRE_BUILD_STAGE_S, + preStagePktMetaData => (others => '0'), + preStageReqStatus => (others => '0'), + preStageReqPktInfo => (others => '0'), + preStageIsZeroPmtuResidue => '0', + retryState => RQ_NOT_RETRY_S, + retryStartValid => '0', + retryStartState => RQ_NOT_RETRY_S, + rnrWaitCnt => (others => '0'), + minRnrTimer => (others => '0'), + isRnrWaitCntZero => '0', + hasReqStatusErr => '0', + hasDmaReadRespErr => '0', + hasErrRespGen => '0', + isFirstOrOnlyRespPkt => '1', + coalesceWorkReqCnt => COALESCE_INIT_C, + isCoalesceWorkReqCntZero => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + --------------------------------------------------------------------------- + -- Enum encodings (constants) + --------------------------------------------------------------------------- + -- RdmaReqStatus (4b) + constant ST_NORMAL_C : slv(3 downto 0) := x"0"; + constant ST_SEQ_ERR_C : slv(3 downto 0) := x"1"; + constant ST_RNR_C : slv(3 downto 0) := x"2"; + constant ST_INV_REQ_C : slv(3 downto 0) := x"3"; + constant ST_INV_RD_C : slv(3 downto 0) := x"4"; + constant ST_RMT_ACC_C : slv(3 downto 0) := x"5"; + constant ST_RMT_OP_C : slv(3 downto 0) := x"6"; + constant ST_DUP_C : slv(3 downto 0) := x"7"; + constant ST_ERR_FLUSH_RR_C : slv(3 downto 0) := x"8"; + constant ST_DISCARD_C : slv(3 downto 0) := x"9"; + constant ST_UNKNOWN_C : slv(3 downto 0) := x"A"; + + -- DmaReqSrcType (4b) — DataTypes.bsv (RQ initiators used by Phase 5) + constant DMA_SRC_RQ_RD_C : slv(3 downto 0) := x"0"; + constant DMA_SRC_RQ_WR_C : slv(3 downto 0) := x"1"; + constant DMA_SRC_RQ_ATOMIC_C : slv(3 downto 0) := x"3"; + constant DMA_SRC_RQ_DISCARD_C : slv(3 downto 0) := x"4"; + + --------------------------------------------------------------------------- + -- TransType (3b) / TypeQP (4b) encodings (Headers.bsv, DataTypes.bsv) + --------------------------------------------------------------------------- + constant TRANS_RC_C : slv(2 downto 0) := "000"; + constant TRANS_UC_C : slv(2 downto 0) := "001"; + constant TRANS_RD_C : slv(2 downto 0) := "010"; + constant TRANS_UD_C : slv(2 downto 0) := "011"; + constant TRANS_CNP_C : slv(2 downto 0) := "100"; + constant TRANS_XRC_C : slv(2 downto 0) := "101"; + -- TypeQP: RC=2, UC=3, UD=4, RAW=8, XRC_SEND=9, XRC_RECV=10 + constant QPT_RC_C : slv(3 downto 0) := x"2"; + constant QPT_UC_C : slv(3 downto 0) := x"3"; + constant QPT_UD_C : slv(3 downto 0) := x"4"; + constant QPT_XRC_RECV_C : slv(3 downto 0) := x"A"; + + --------------------------------------------------------------------------- + -- Struct slice offsets (first-field-at-MSB deriving(Bits)) + --------------------------------------------------------------------------- + -- RdmaPktMetaData (649b): pktPayloadLen[648:636] pktFragNum[635:628] + -- isZeroPayloadLen[627] pktHeader(HeaderRDMA 593)[626:34] pdHandler[33:2] + -- pktValid[1] pktStatus[0]. HeaderRDMA: headerData(512)[626:115] + -- headerByteEn(64)[114:51] headerMetaData(17)[50:34]. + -- headerData[i] = pktMetaData[115+i]. BTH=headerData[511:416]=pmd[626:531]; + -- RETH(default,128)=headerData[415:288]=pmd[530:403]; RETH.dlen=RETH[31:0]=pmd[434:403]. + constant PMD_ISZEROPAYLOAD_C : integer := 627; + constant PMD_PKTVALID_C : integer := 1; + constant PMD_PKTSTATUS_C : integer := 0; -- PktVeriStatus: 0=VALID, 1=LEN_ERR + -- BTH (96b): trans[95:93] opcode[92:88] ... dqpn[55:32] ... psn[23:0] + -- RdmaReqPktInfo (161b): bth[160:65] epoch[64] respPktNum(25)[63:39] endPSN(24)[38:15] + -- isSendReq[14] isWriteReq[13] isWriteImmReq[12] isReadReq[11] isAtomicReq[10] + -- isOnlyPkt[9] isFirstPkt[8] isMidPkt[7] isLastPkt[6] isFirstOrOnlyPkt[5] + -- isLastOrOnlyPkt[4] isOnlyRespPkt[3] isExpected[2] isDuplicated[1] isAccCheckPass[0] + -- RETH (128b): va[127:64] rkey[63:32] dlen[31:0]; RETH=pmd[530:403]. + -- AtomicEth (224b): va[223:160] rkey[159:128] swap[127:64] comp[63:0]; + -- AtomicEth=headerData[415:192]=pmd[530:307]; AtomicEth.va=pmd[530:467]. + -- PermCheckReq (267b): wrID(Maybe#64=65)[266:202] lkey[201:170] rkey[169:138] + -- localOrRmtKey[137] reqAddr[136:73] totalLen[72:41] pdHandler[40:9] + -- isZeroDmaLen[8] accFlags(8)[7:0]. + -- RecvReq (216b): id[215:152] len[151:120] laddr[119:56] lkey[55:24] sqpn[23:0]. + -- MemAccessTypeFlag (FlagsType 8b) = enum2Flag(pack(enum)); enum values are 1< ST_INV_REQ_C -> NAK INV_REQ), and every + -- downstream read/atomic arm (dup-read cache, atomicSrv, payloadGen issue) + -- constant-folds away in synthesis. + function isReadReqOp (op : slv(4 downto 0)) return boolean is + begin + return EN_READ_G and (opInt(op) = 12); + end function; + function isAtomicReqOp (op : slv(4 downto 0)) return boolean is + variable u : integer := opInt(op); + begin + return EN_READ_G and ((u=19) or (u=20)); + end function; + function isFirstOp (op : slv(4 downto 0)) return boolean is + variable u : integer := opInt(op); + begin + return (u=0) or (u=6) or (u=13); + end function; + function isMiddleOp (op : slv(4 downto 0)) return boolean is + variable u : integer := opInt(op); + begin + return (u=1) or (u=7) or (u=14); + end function; + function isLastOp (op : slv(4 downto 0)) return boolean is + variable u : integer := opInt(op); + begin + return (u=2) or (u=3) or (u=22) or (u=8) or (u=9) or (u=15); + end function; + function isOnlyOp (op : slv(4 downto 0)) return boolean is + variable u : integer := opInt(op); + begin + return (u=4) or (u=5) or (u=23) or (u=10) or (u=11) or (u=12) or + (u=19) or (u=20) or (u=16) or (u=17) or (u=18); + end function; + function isFirstOrOnlyOp (op : slv(4 downto 0)) return boolean is + begin + return isFirstOp(op) or isOnlyOp(op); + end function; + function isLastOrOnlyOp (op : slv(4 downto 0)) return boolean is + begin + return isLastOp(op) or isOnlyOp(op); + end function; + + -- isSupportedReqOpCodeRQ(qpt, opcode) + function isSupportedReqOp (qpt : slv(3 downto 0); op : slv(4 downto 0)) return boolean is + begin + if (qpt = QPT_UC_C) then + -- UC: SEND_{FIRST..ONLY_IMM}={0..5} (excludes *_WITH_INVALIDATE) or WRITE_* + return (opInt(op) <= 5) or isWriteReqOp(op); + end if; + if (qpt = QPT_UD_C) then + return (opInt(op) = 4) or (opInt(op) = 5); + end if; + if (qpt = QPT_RC_C) or (qpt = QPT_XRC_RECV_C) then + return isSendReqOp(op) or isWriteReqOp(op) or isReadReqOp(op) or isAtomicReqOp(op); + end if; + return false; + end function; + + -- checkNormalReqOpCodeSeqRQ(preOpCode, curOpCode) + function checkNormalSeq (preOp : slv(4 downto 0); curOp : slv(4 downto 0)) return boolean is + variable p : integer := opInt(preOp); + variable c : integer := opInt(curOp); + begin + if (p=0) or (p=1) then -- SEND_FIRST / SEND_MIDDLE + return (c=1) or (c=2) or (c=3) or (c=22); + elsif (p=2) or (p=3) or (p=22) or (p=4) or (p=5) or (p=23) then + return true; -- SEND_LAST*/SEND_ONLY* + elsif (p=6) or (p=7) then -- RDMA_WRITE_FIRST / MIDDLE + return (c=7) or (c=8) or (c=9); + elsif (p=8) or (p=9) or (p=10) or (p=11) or (p=12) or (p=19) or (p=20) then + return true; -- WRITE_LAST*/ONLY*/READ/ATOMIC + else + return false; + end if; + end function; + + -- getInvReqStatusByTransType(transType) -> RdmaReqStatus (4b) + function invReqStatus (trans : slv(2 downto 0)) return slv is + begin + if (trans = TRANS_RC_C) then return ST_INV_REQ_C; + elsif (trans = TRANS_UC_C) then return ST_DISCARD_C; + elsif (trans = TRANS_RD_C) then return ST_INV_RD_C; + elsif (trans = TRANS_UD_C) then return ST_DISCARD_C; + elsif (trans = TRANS_CNP_C) then return ST_DISCARD_C; + elsif (trans = TRANS_XRC_C) then return ST_INV_RD_C; + else return ST_UNKNOWN_C; + end if; + end function; + + -- calcOldestValidPsn4RQ(ePSN) = ePSN - 2^23 = { ~ePSN[23], ePSN[22:0] } + function oldestValidPsn (epsn : slv(23 downto 0)) return slv is + begin + return (not epsn(23)) & epsn(22 downto 0); + end function; + + -- psnInRangeExclusive(psn, psnStart, psnEnd) (24b PSN) + function psnInRangeExcl (psn : slv(23 downto 0); psnStart : slv(23 downto 0); + psnEnd : slv(23 downto 0)) return boolean is + variable psnGtStart : boolean := unsigned(psnStart) < unsigned(psn); + variable psnLtEnd : boolean := unsigned(psn) < unsigned(psnEnd); + begin + if (psnStart(23) = psnEnd(23)) then + return psnGtStart and psnLtEnd; + else + return (psnGtStart and (psnStart(23) = psn(23))) or + (psnLtEnd and (psn(23) = psnEnd(23))); + end if; + end function; + + -- truncateLenByPMTU: PktNum(25b) = len >> log2(pmtuBytes) + function truncLenPktNum (len : slv(31 downto 0); pmtu : slv(2 downto 0)) return slv is + variable sh : integer; + begin + case to_integer(unsigned(pmtu)) is + when 1 => sh := 8; -- 256 + when 2 => sh := 9; -- 512 + when 3 => sh := 10; -- 1024 + when 4 => sh := 11; -- 2048 + when others => sh := 12; -- 4096 (=5) + end case; + return slv(resize(shift_right(unsigned(len), sh), 25)); + end function; + -- isZero(pmtuResidue): low log2(pmtuBytes) bits of len are all zero + function pmtuResidueZero (len : slv(31 downto 0); pmtu : slv(2 downto 0)) return boolean is + variable sh : integer; + begin + case to_integer(unsigned(pmtu)) is + when 1 => sh := 8; + when 2 => sh := 9; + when 3 => sh := 10; + when 4 => sh := 11; + when others => sh := 12; + end case; + return unsigned(len(sh-1 downto 0)) = 0; + end function; + + -- isLessOrEqOneR(x) : x <= 1 + function isLessOrEqOne (x : slv) return boolean is + begin + return unsigned(x) <= 1; + end function; + + --------------------------------------------------------------------------- + -- Phase 4 DMA addr/len PMTU arithmetic (Utils.bsv @422-665). oneAsPSN=1 + -- everywhere in stages 12-16, so *PsnMultiplyPMTU reduce to +/- 2^log. + --------------------------------------------------------------------------- + -- getPmtuLogValue: 256->8, 512->9, 1024->10, 2048->11, 4096->12 + function pmtuLog (pmtu : slv(2 downto 0)) return integer is + begin + case to_integer(unsigned(pmtu)) is + when 1 => return 8; -- IBV_MTU_256 + when 2 => return 9; -- IBV_MTU_512 + when 3 => return 10; -- IBV_MTU_1024 + when 4 => return 11; -- IBV_MTU_2048 + when others => return 12; -- IBV_MTU_4096 (=5) + end case; + end function; + -- addrAddPsnMultiplyPMTU(addr, 1, pmtu) = addr + 2^log + function addrAddOnePmtu (addr : slv(63 downto 0); pmtu : slv(2 downto 0)) return slv is + begin + return slv(unsigned(addr) + to_unsigned(2**pmtuLog(pmtu), 64)); + end function; + -- lenSubtractPsnMultiplyPMTU(len, 1, pmtu) = len - 2^log + function lenSubOnePmtu (len : slv(31 downto 0); pmtu : slv(2 downto 0)) return slv is + begin + return slv(unsigned(len) - to_unsigned(2**pmtuLog(pmtu), 32)); + end function; + -- lenAddPsnMultiplyPMTU(len, 1, pmtu) = len + 2^log + function lenAddOnePmtu (len : slv(31 downto 0); pmtu : slv(2 downto 0)) return slv is + begin + return slv(unsigned(len) + to_unsigned(2**pmtuLog(pmtu), 32)); + end function; + -- calcPmtuLen(pmtu) = 2^log (PktLen 13b) + function calcPmtuLen (pmtu : slv(2 downto 0)) return slv is + begin + return slv(to_unsigned(2**pmtuLog(pmtu), 13)); + end function; + -- pktLenEqPMTU(pktLen, pmtu): pktLen with bit[log] cleared is zero (i.e. == PMTU) + function pktLenEqPmtu (pktLen : slv(12 downto 0); pmtu : slv(2 downto 0)) return boolean is + variable t : slv(12 downto 0); + begin + t := pktLen; + t(pmtuLog(pmtu)) := '0'; + return unsigned(t) = 0; + end function; + -- lenSubtractPktLen: low (log+1) bits subtract, no borrow into high part + function lenSubPktLen (len : slv(31 downto 0); pktLen : slv(12 downto 0); + pmtu : slv(2 downto 0)) return slv is + begin + case to_integer(unsigned(pmtu)) is + when 1 => return len(31 downto 9) & slv(unsigned(len(8 downto 0)) - unsigned(pktLen(8 downto 0))); + when 2 => return len(31 downto 10) & slv(unsigned(len(9 downto 0)) - unsigned(pktLen(9 downto 0))); + when 3 => return len(31 downto 11) & slv(unsigned(len(10 downto 0)) - unsigned(pktLen(10 downto 0))); + when 4 => return len(31 downto 12) & slv(unsigned(len(11 downto 0)) - unsigned(pktLen(11 downto 0))); + when others => return len(31 downto 13) & slv(unsigned(len(12 downto 0)) - unsigned(pktLen(12 downto 0))); + end case; + end function; + -- lenAddPktLen: if pktLen==PMTU add one PMTU, else replace low log bits with pktLen + function lenAddPktLen (len : slv(31 downto 0); pktLen : slv(12 downto 0); + pmtu : slv(2 downto 0)) return slv is + begin + if (pktLenEqPmtu(pktLen, pmtu)) then + return lenAddOnePmtu(len, pmtu); + else + case to_integer(unsigned(pmtu)) is + when 1 => return len(31 downto 8) & pktLen(7 downto 0); + when 2 => return len(31 downto 9) & pktLen(8 downto 0); + when 3 => return len(31 downto 10) & pktLen(9 downto 0); + when 4 => return len(31 downto 11) & pktLen(10 downto 0); + when others => return len(31 downto 12) & pktLen(11 downto 0); + end case; + end if; + end function; + -- lenGtEqPktLen: high part (above log) nonzero, or low (log+1) bits >= pktLen + function lenGtEqPktLen (len : slv(31 downto 0); pktLen : slv(12 downto 0); + pmtu : slv(2 downto 0)) return boolean is + begin + case to_integer(unsigned(pmtu)) is + when 1 => return (unsigned(len(31 downto 9)) /= 0) or (unsigned(len(8 downto 0)) >= unsigned(pktLen(8 downto 0))); + when 2 => return (unsigned(len(31 downto 10)) /= 0) or (unsigned(len(9 downto 0)) >= unsigned(pktLen(9 downto 0))); + when 3 => return (unsigned(len(31 downto 11)) /= 0) or (unsigned(len(10 downto 0)) >= unsigned(pktLen(10 downto 0))); + when 4 => return (unsigned(len(31 downto 12)) /= 0) or (unsigned(len(11 downto 0)) >= unsigned(pktLen(11 downto 0))); + when others => return (unsigned(len(31 downto 13)) /= 0) or (unsigned(len(12 downto 0)) >= unsigned(pktLen(12 downto 0))); + end case; + end function; + -- lenGtEqPMTU: bits above (log-1) nonzero, i.e. len >= 2^log + function lenGtEqPmtu (len : slv(31 downto 0); pmtu : slv(2 downto 0)) return boolean is + begin + case to_integer(unsigned(pmtu)) is + when 1 => return unsigned(len(31 downto 8)) /= 0; + when 2 => return unsigned(len(31 downto 9)) /= 0; + when 3 => return unsigned(len(31 downto 10)) /= 0; + when 4 => return unsigned(len(31 downto 11)) /= 0; + when others => return unsigned(len(31 downto 12)) /= 0; + end case; + end function; + + -- isErrReqStatus(reqStatus): INV_REQ(3) | INV_RD(4) | RMT_ACC(5) | RMT_OP(6) (Phase 5) + function isErrReqStatus (st : slv(3 downto 0)) return boolean is + begin + return (unsigned(st) >= 3) and (unsigned(st) <= 6); + end function; + + -- qpNeedGenResp(trans): RC(000) | RD(010) | XRC(101) generate responses (Phase 6) + function qpNeedGenResp (trans : slv(2 downto 0)) return boolean is + begin + return (trans = "000") or (trans = "010") or (trans = "101"); + end function; + + --------------------------------------------------------------------------- + -- Phase 8 : response RdmaOpCode + header generation (BSV Utils.bsv / + -- ReqHandleRQ.bsv:77-319). RdmaOpCode encodings (Headers.bsv:100). + --------------------------------------------------------------------------- + constant OP_READ_REQUEST_C : slv(4 downto 0) := "01100"; -- 0x0c + constant OP_READ_RESP_FIRST_C : slv(4 downto 0) := "01101"; -- 0x0d + constant OP_READ_RESP_MIDDLE_C : slv(4 downto 0) := "01110"; -- 0x0e + constant OP_READ_RESP_LAST_C : slv(4 downto 0) := "01111"; -- 0x0f + constant OP_READ_RESP_ONLY_C : slv(4 downto 0) := "10000"; -- 0x10 + constant OP_ACKNOWLEDGE_C : slv(4 downto 0) := "10001"; -- 0x11 + constant OP_ATOMIC_ACK_C : slv(4 downto 0) := "10010"; -- 0x12 + + -- isNormalOrErrorReqStatus (ReqHandleRQ.bsv:43): NORMAL|INV_REQ|INV_RD|RMT_ACC|RMT_OP + function isNormalOrErrStatus (st : slv(3 downto 0)) return boolean is + begin + case st is + when ST_NORMAL_C | ST_INV_REQ_C | ST_INV_RD_C | ST_RMT_ACC_C | ST_RMT_OP_C => + return true; + when others => return false; + end case; + end function; + + -- calcPadCnt (Utils.bsv:830), PAD_WIDTH=2: padCnt = (4 - len[1:0]) mod 4 + function calcPadCnt (len : slv(31 downto 0)) return slv is + begin + return slv(to_unsigned((4 - to_integer(unsigned(len(1 downto 0)))) mod 4, 2)); + end function; + + -- AETH validity + build (ReqHandleRQ.bsv:125 genAethByReqStatus). + -- AETH(32) = rsvd[31] code[30:29] value[28:24] msn[23:0]. + function aethValid (st : slv(3 downto 0)) return boolean is + begin + case st is + when ST_NORMAL_C | ST_DUP_C | ST_RNR_C | ST_SEQ_ERR_C + | ST_INV_REQ_C | ST_INV_RD_C | ST_RMT_ACC_C | ST_RMT_OP_C => return true; + when others => return false; + end case; + end function; + + function genAeth (st : slv(3 downto 0); minRnrTimer : slv(4 downto 0); + msn : slv(23 downto 0)) return slv is + variable code : slv(1 downto 0); + variable val : slv(4 downto 0); + begin + case st is + when ST_NORMAL_C | ST_DUP_C => code := "00"; val := "11111"; -- ACK, INVALID_CREDIT_CNT + when ST_RNR_C => code := "01"; val := minRnrTimer; + when ST_SEQ_ERR_C => code := "11"; val := "00000"; -- NAK SEQ_ERR + when ST_INV_REQ_C => code := "11"; val := "00001"; -- NAK INV_REQ + when ST_RMT_ACC_C => code := "11"; val := "00010"; -- NAK RMT_ACC + when ST_RMT_OP_C => code := "11"; val := "00011"; -- NAK RMT_OP + when ST_INV_RD_C => code := "11"; val := "00100"; -- NAK INV_RD + when others => code := "00"; val := "00000"; -- unused (Invalid path) + end case; + return '0' & code & val & msn; + end function; + + -- genFirstOrOnlyRespRdmaOpCode (ReqHandleRQ.bsv:77): [5]=valid, [4:0]=opcode. + function genFirstOnlyRespOp (reqOp : slv(4 downto 0); st : slv(3 downto 0); + isOnlyReadResp : boolean) return slv is + variable op : integer := to_integer(unsigned(reqOp)); + begin + case st is + when ST_NORMAL_C | ST_DUP_C => + if ((op >= 0 and op <= 11) or op = 22 or op = 23) then -- SEND*/WRITE*/*INVALIDATE + return '1' & OP_ACKNOWLEDGE_C; + elsif (op = 12) then -- RDMA_READ_REQUEST + if isOnlyReadResp then return '1' & OP_READ_RESP_ONLY_C; + else return '1' & OP_READ_RESP_FIRST_C; end if; + elsif (op = 19 or op = 20) then -- COMPARE_SWAP/FETCH_ADD + return '1' & OP_ATOMIC_ACK_C; + else return "000000"; end if; + when ST_SEQ_ERR_C | ST_RNR_C | ST_INV_REQ_C | ST_INV_RD_C | ST_RMT_ACC_C | ST_RMT_OP_C => + return '1' & OP_ACKNOWLEDGE_C; + when others => return "000000"; + end case; + end function; + + -- genMiddleOrLastRespRdmaOpCode (ReqHandleRQ.bsv:116): [5]=valid, [4:0]=opcode. + function genMidLastRespOp (st : slv(3 downto 0); isLastResp : boolean) return slv is + begin + case st is + when ST_NORMAL_C | ST_DUP_C => + if isLastResp then return '1' & OP_READ_RESP_LAST_C; + else return '1' & OP_READ_RESP_MIDDLE_C; end if; + when ST_RMT_OP_C => return '1' & OP_ACKNOWLEDGE_C; + when others => return "000000"; + end case; + end function; + + -- qpType2TransType (Utils.bsv:741): [3]=valid, [2:0]=trans + function qpType2Trans (qpt : slv(3 downto 0)) return slv is + begin + case qpt is + when QPT_RC_C => return '1' & TRANS_RC_C; + when QPT_UC_C => return '1' & TRANS_UC_C; + when QPT_UD_C => return '1' & TRANS_UD_C; + when QPT_XRC_RECV_C => return '1' & TRANS_XRC_C; + when others => return "0000"; + end case; + end function; + + -- getMaybeDestQpnRQ (ReqHandleRQ.bsv:54): valid for RC/UC/XRC_RECV + function destQpnValid (qpt : slv(3 downto 0)) return boolean is + begin + case qpt is + when QPT_RC_C | QPT_UC_C | QPT_XRC_RECV_C => return true; + when others => return false; + end case; + end function; + + -- genHeaderRDMA (Utils.bsv:319). HeaderRDMA(593) = headerData[592:81] + -- byteEn[80:17] metaData[16:0]; meta = headerLen[16:10] fragNum[9:8] + -- lastFragValidByteNum[7:2] hasPayload[1] isEmptyHeader[0]. All response + -- headers are <=24 bytes -> single fragment, byteEn is MSB-aligned ones. + function genHeaderRDMA (hdrData : slv(511 downto 0); lenBytes : integer; + hasPayloadV : sl) return slv is + variable byteEn : slv(63 downto 0) := (others => '0'); + variable meta : slv(16 downto 0); + begin + byteEn(63 downto 64 - lenBytes) := (others => '1'); + meta := slv(to_unsigned(lenBytes, 7)) & "01" + & slv(to_unsigned(lenBytes, 6)) & hasPayloadV & '0'; + return hdrData & byteEn & meta; + end function; + + -- BTH(96) builder — reserved/solicited/migReq/tver/fecn/becn/ackReq all 0. + function mkRespBth (trans : slv(2 downto 0); opcode : slv(4 downto 0); + padCnt : slv(1 downto 0); pkey : slv(15 downto 0); + dqpn : slv(23 downto 0); psn : slv(23 downto 0)) return slv is + begin + return trans & opcode & '0' & '0' & padCnt & "0000" & pkey + & '0' & '0' & "000000" & dqpn & '0' & "0000000" & psn; + end function; + + -- genFirstOrOnlyRespHeader (ReqHandleRQ.bsv:188) -> Maybe#HeaderRDMA(594): + -- [593]=valid, [592:0]=HeaderRDMA. + function genFirstOrOnlyRespHeader ( + reqOp : slv(4 downto 0); st : slv(3 downto 0); payloadLen : slv(31 downto 0); + atomicOrig : slv(64 downto 0); qpType : slv(3 downto 0); pkey : slv(15 downto 0); + dqpn : slv(23 downto 0); minRnrTimer : slv(4 downto 0); psn : slv(23 downto 0); + msn : slv(23 downto 0); isOnlyReadResp : boolean) return slv is + variable transM : slv(3 downto 0) := qpType2Trans(qpType); + variable opM : slv(5 downto 0) := genFirstOnlyRespOp(reqOp, st, isOnlyReadResp); + variable opcode : slv(4 downto 0); + variable padV : slv(1 downto 0); + variable bth : slv(95 downto 0); + variable aeth : slv(31 downto 0); + variable hdrData : slv(511 downto 0) := (others => '0'); + begin + if (transM(3) = '1' and opM(5) = '1' and destQpnValid(qpType) and aethValid(st)) then + opcode := opM(4 downto 0); + if isOnlyReadResp then padV := calcPadCnt(payloadLen); else padV := "00"; end if; + bth := mkRespBth(transM(2 downto 0), opcode, padV, pkey, dqpn, psn); + aeth := genAeth(st, minRnrTimer, msn); + case opcode is + when OP_ACKNOWLEDGE_C => + hdrData(511 downto 384) := bth & aeth; + return '1' & genHeaderRDMA(hdrData, 16, '0'); + when OP_ATOMIC_ACK_C => + hdrData(511 downto 320) := bth & aeth & atomicOrig(63 downto 0); + return '1' & genHeaderRDMA(hdrData, 24, '0'); + when OP_READ_RESP_FIRST_C | OP_READ_RESP_ONLY_C => + hdrData(511 downto 384) := bth & aeth; + if (unsigned(payloadLen) = 0) then + return '1' & genHeaderRDMA(hdrData, 16, '0'); + else + return '1' & genHeaderRDMA(hdrData, 16, '1'); + end if; + when others => return (593 downto 0 => '0'); + end case; + else + return (593 downto 0 => '0'); + end if; + end function; + + -- genMiddleOrLastRespHeader (ReqHandleRQ.bsv:258) -> Maybe#HeaderRDMA(594). + function genMidLastRespHeader ( + st : slv(3 downto 0); payloadLen : slv(31 downto 0); qpType : slv(3 downto 0); + pkey : slv(15 downto 0); dqpn : slv(23 downto 0); minRnrTimer : slv(4 downto 0); + psn : slv(23 downto 0); msn : slv(23 downto 0); isLastResp : boolean) return slv is + variable transM : slv(3 downto 0) := qpType2Trans(qpType); + variable opM : slv(5 downto 0) := genMidLastRespOp(st, isLastResp); + variable opcode : slv(4 downto 0); + variable padV : slv(1 downto 0); + variable bth : slv(95 downto 0); + variable aeth : slv(31 downto 0); + variable hdrData : slv(511 downto 0) := (others => '0'); + begin + if (transM(3) = '1' and opM(5) = '1' and destQpnValid(qpType) and aethValid(st)) then + opcode := opM(4 downto 0); + if isLastResp then padV := calcPadCnt(payloadLen); else padV := "00"; end if; + bth := mkRespBth(transM(2 downto 0), opcode, padV, pkey, dqpn, psn); + aeth := genAeth(st, minRnrTimer, msn); + case opcode is + when OP_ACKNOWLEDGE_C => + hdrData(511 downto 384) := bth & aeth; + return '1' & genHeaderRDMA(hdrData, 16, '0'); + when OP_READ_RESP_LAST_C => + hdrData(511 downto 384) := bth & aeth; + return '1' & genHeaderRDMA(hdrData, 16, '1'); + when OP_READ_RESP_MIDDLE_C => + hdrData(511 downto 416) := bth; + return '1' & genHeaderRDMA(hdrData, 12, '1'); + when others => return (593 downto 0 => '0'); + end case; + else + return (593 downto 0 => '0'); + end if; + end function; + + --------------------------------------------------------------------------- + -- getRnrTimeOutValue(minRnrTimer) LUT — cycles = usValue*1000/TARGET_CYCLE_NS + -- with TARGET_CYCLE_NS=2 (Settings.bsv) -> value*500. RNR_WAIT_CYCLE_CNT_WIDTH=29. + --------------------------------------------------------------------------- + type Slv29Array is array (0 to 31) of slv(28 downto 0); + function rnrTo (n : integer) return slv is + begin + return slv(to_unsigned(n, 29)); + end function; + constant RNR_TIMEOUT_C : Slv29Array := ( + 0 => rnrTo(327680000), 1 => rnrTo(5000), 2 => rnrTo(10000), + 3 => rnrTo(15000), 4 => rnrTo(20000), 5 => rnrTo(30000), + 6 => rnrTo(40000), 7 => rnrTo(60000), 8 => rnrTo(80000), + 9 => rnrTo(120000), 10 => rnrTo(160000), 11 => rnrTo(240000), + 12 => rnrTo(320000), 13 => rnrTo(480000), 14 => rnrTo(640000), + 15 => rnrTo(960000), 16 => rnrTo(1280000), 17 => rnrTo(1920000), + 18 => rnrTo(2560000), 19 => rnrTo(3840000), 20 => rnrTo(5120000), + 21 => rnrTo(7680000), 22 => rnrTo(10240000), 23 => rnrTo(15360000), + 24 => rnrTo(20480000), 25 => rnrTo(30720000), 26 => rnrTo(40960000), + 27 => rnrTo(61440000), 28 => rnrTo(81920000), 29 => rnrTo(122880000), + 30 => rnrTo(163840000), 31 => rnrTo(245760000)); + + --------------------------------------------------------------------------- + -- Phase 9 : genWorkCompRQ helpers (BSV ReqHandleRQ.bsv:65,3385; Utils.bsv:942/ + -- 971/1182/1192). RdmaOpCode (low-5) encodings from Headers.bsv:36. + -- WorkCompStatus (DataTypes.bsv:613) encodings (5b): SUCCESS=0, WR_FLUSH=5, + -- REM_INV_REQ=9, REM_ACCESS=10, REM_OP=11, REM_INV_RD=15. + --------------------------------------------------------------------------- + -- rdmaReqHasImmDt (Utils.bsv:1182): SEND/WRITE _LAST/_ONLY_WITH_IMMEDIATE + function opHasImmDt (op : slv(4 downto 0)) return boolean is + begin + case op is + when "00011" | "00101" | "01001" | "01011" => return true; -- 0x03,0x05,0x09,0x0b + when others => return false; + end case; + end function; + + -- rdmaReqHasIETH (Utils.bsv:1192): SEND_LAST/_ONLY_WITH_INVALIDATE (0x16,0x17) + function opHasIETH (op : slv(4 downto 0)) return boolean is + begin + case op is + when "10110" | "10111" => return true; + when others => return false; + end case; + end function; + + -- genWorkCompStatusFromReqStatusRQ (ReqHandleRQ.bsv:65). Returns slv(5:0): + -- [5]=Valid tag; [4:0]=WorkCompStatus (only meaningful when tag='1'). + function genWcStatus (st : slv(3 downto 0)) return slv is + begin + case st is + when ST_NORMAL_C => return "1" & "00000"; -- IBV_WC_SUCCESS=0 + when ST_INV_REQ_C => return "1" & "01001"; -- REM_INV_REQ_ERR=9 + when ST_INV_RD_C => return "1" & "01111"; -- REM_INV_RD_REQ_ERR=15 + when ST_RMT_ACC_C => return "1" & "01010"; -- REM_ACCESS_ERR=10 + when ST_RMT_OP_C => return "1" & "01011"; -- REM_OP_ERR=11 + when ST_ERR_FLUSH_RR_C => return "1" & "00101"; -- WR_FLUSH_ERR=5 + when others => return "0" & "00000"; -- tagged Invalid + end case; + end function; + + --------------------------------------------------------------------------- + -- SURF Fifo interface signals — one bundle per instance. + -- Naming: fNN follows the pipeline dataflow order (== BSV declaration order): + -- f01 supportedReqOpCodeCheckQ f17 reqLenCheckQ + -- f02 reqOpCodeSeqCheckQ f18 issuePayloadConReqQ + -- f03 rnrCheckQ f19 issuePayloadGenReqQ + -- f04 rnrTriggerQ f20 issueAtomicReqQ + -- f05 qpAccPermCheckQ f21 respGenCheck4NormalCaseQ + -- f06 reqPermInfoBuildQ f22 respGenCheck4OtherCasesQ + -- f07 reqPermQueryTmpQ f23 respCountQ + -- f08 reqPermQueryQ f24 respPsnAndMsnQ + -- f09 reqPermCheckQ f25 waitAtomicRespQ + -- f10 readCacheInsertQ f26 atomicCacheInsertQ + -- f11 dupReadReqPermQueryQ f27 respCheckQ + -- f12 dupReadReqPermCheckQ f28 dupAtomicReqPermQueryQ + -- f13 reqAddrCalcQ f29 dupAtomicReqPermCheckQ + -- f14 reqRemainingLenCalcQ f30 respHeaderGenQ + -- f15 reqEnoughDmaSpaceQ f31 pendingRespQ + -- f16 reqTotalLenCalcQ f32 workCompReqQ + -- Output FIFOs: wcOut workCompGenReqOutQ, rhOut respHeaderOutQ, psnOut psnRespOutQ + --------------------------------------------------------------------------- + -- widths, in fNN order + constant W01_C : integer := 838; constant W17_C : integer := 1212; + constant W02_C : integer := 814; constant W18_C : integer := 1146; + constant W03_C : integer := 819; constant W19_C : integer := 1083; + constant W04_C : integer := 1036; constant W20_C : integer := 1154; + constant W05_C : integer := 1031; constant W21_C : integer := 1154; + constant W06_C : integer := 1031; constant W22_C : integer := 1154; + constant W07_C : integer := 1426; constant W23_C : integer := 1154; + constant W08_C : integer := 1209; constant W24_C : integer := 1156; + constant W09_C : integer := 1210; constant W25_C : integer := 1204; + constant W10_C : integer := 1209; constant W26_C : integer := 1204; + constant W11_C : integer := 1209; constant W27_C : integer := 1428; + constant W12_C : integer := 1210; constant W28_C : integer := 1428; + constant W13_C : integer := 1082; constant W29_C : integer := 1204; + constant W14_C : integer := 1146; constant W30_C : integer := 1204; + constant W15_C : integer := 1210; constant W31_C : integer := 1798; + constant W16_C : integer := 1182; constant W32_C : integer := 1204; + constant WCW_C : integer := 198; -- workCompGenReqOutQ + constant RHW_C : integer := 593; -- respHeaderOutQ + constant PSW_C : integer := 24; -- psnRespOutQ + + -- per-FIFO handshake bundles + signal f01WrEn, f01RdEn, f01Valid, f01NotFull : sl; signal f01Din, f01Dout : slv(W01_C-1 downto 0); + signal f02WrEn, f02RdEn, f02Valid, f02NotFull : sl; signal f02Din, f02Dout : slv(W02_C-1 downto 0); + signal f03WrEn, f03RdEn, f03Valid, f03NotFull : sl; signal f03Din, f03Dout : slv(W03_C-1 downto 0); + signal f04WrEn, f04RdEn, f04Valid, f04NotFull : sl; signal f04Din, f04Dout : slv(W04_C-1 downto 0); + signal f05WrEn, f05RdEn, f05Valid, f05NotFull : sl; signal f05Din, f05Dout : slv(W05_C-1 downto 0); + signal f06WrEn, f06RdEn, f06Valid, f06NotFull : sl; signal f06Din, f06Dout : slv(W06_C-1 downto 0); + signal f07WrEn, f07RdEn, f07Valid, f07NotFull : sl; signal f07Din, f07Dout : slv(W07_C-1 downto 0); + signal f08WrEn, f08RdEn, f08Valid, f08NotFull : sl; signal f08Din, f08Dout : slv(W08_C-1 downto 0); + signal f09WrEn, f09RdEn, f09Valid, f09NotFull : sl; signal f09Din, f09Dout : slv(W09_C-1 downto 0); + signal f10WrEn, f10RdEn, f10Valid, f10NotFull : sl; signal f10Din, f10Dout : slv(W10_C-1 downto 0); + signal f11WrEn, f11RdEn, f11Valid, f11NotFull : sl; signal f11Din, f11Dout : slv(W11_C-1 downto 0); + signal f12WrEn, f12RdEn, f12Valid, f12NotFull : sl; signal f12Din, f12Dout : slv(W12_C-1 downto 0); + signal f13WrEn, f13RdEn, f13Valid, f13NotFull : sl; signal f13Din, f13Dout : slv(W13_C-1 downto 0); + signal f14WrEn, f14RdEn, f14Valid, f14NotFull : sl; signal f14Din, f14Dout : slv(W14_C-1 downto 0); + signal f15WrEn, f15RdEn, f15Valid, f15NotFull : sl; signal f15Din, f15Dout : slv(W15_C-1 downto 0); + signal f16WrEn, f16RdEn, f16Valid, f16NotFull : sl; signal f16Din, f16Dout : slv(W16_C-1 downto 0); + signal f17WrEn, f17RdEn, f17Valid, f17NotFull : sl; signal f17Din, f17Dout : slv(W17_C-1 downto 0); + signal f18WrEn, f18RdEn, f18Valid, f18NotFull : sl; signal f18Din, f18Dout : slv(W18_C-1 downto 0); + signal f19WrEn, f19RdEn, f19Valid, f19NotFull : sl; signal f19Din, f19Dout : slv(W19_C-1 downto 0); + signal f20WrEn, f20RdEn, f20Valid, f20NotFull : sl; signal f20Din, f20Dout : slv(W20_C-1 downto 0); + signal f21WrEn, f21RdEn, f21Valid, f21NotFull : sl; signal f21Din, f21Dout : slv(W21_C-1 downto 0); + signal f22WrEn, f22RdEn, f22Valid, f22NotFull : sl; signal f22Din, f22Dout : slv(W22_C-1 downto 0); + signal f23WrEn, f23RdEn, f23Valid, f23NotFull : sl; signal f23Din, f23Dout : slv(W23_C-1 downto 0); + signal f24WrEn, f24RdEn, f24Valid, f24NotFull : sl; signal f24Din, f24Dout : slv(W24_C-1 downto 0); + signal f25WrEn, f25RdEn, f25Valid, f25NotFull : sl; signal f25Din, f25Dout : slv(W25_C-1 downto 0); + signal f26WrEn, f26RdEn, f26Valid, f26NotFull : sl; signal f26Din, f26Dout : slv(W26_C-1 downto 0); + signal f27WrEn, f27RdEn, f27Valid, f27NotFull : sl; signal f27Din, f27Dout : slv(W27_C-1 downto 0); + signal f28WrEn, f28RdEn, f28Valid, f28NotFull : sl; signal f28Din, f28Dout : slv(W28_C-1 downto 0); + signal f29WrEn, f29RdEn, f29Valid, f29NotFull : sl; signal f29Din, f29Dout : slv(W29_C-1 downto 0); + signal f30WrEn, f30RdEn, f30Valid, f30NotFull : sl; signal f30Din, f30Dout : slv(W30_C-1 downto 0); + signal f31WrEn, f31RdEn, f31Valid, f31NotFull : sl; signal f31Din, f31Dout : slv(W31_C-1 downto 0); + signal f32WrEn, f32RdEn, f32Valid, f32NotFull : sl; signal f32Din, f32Dout : slv(W32_C-1 downto 0); + -- output FIFOs + signal wcOutWrEn, wcOutRdEn, wcOutValid, wcOutNotFull : sl; signal wcOutDin, wcOutDout : slv(WCW_C-1 downto 0); + signal rhOutWrEn, rhOutRdEn, rhOutValid, rhOutNotFull : sl; signal rhOutDin, rhOutDout : slv(RHW_C-1 downto 0); + signal psnOutWrEn, psnOutRdEn, psnOutValid, psnOutNotFull : sl; signal psnOutDin, psnOutDout : slv(PSW_C-1 downto 0); + + signal fifoClr : sl; + + --------------------------------------------------------------------------- + -- Child-instance interconnect signals + --------------------------------------------------------------------------- + -- U_AtomicSrv (internal): request 245b / response 116b + signal atomicReqValid : sl; + signal atomicReqData : slv(244 downto 0); + signal atomicReqRdy : sl; + signal atomicRespValid : sl; + signal atomicRespData : slv(115 downto 0); + signal atomicRespRdEn : sl; + -- U_PendingDestReadAtomicReqCnt (CountCF, WIDTH_G=8) + signal ccIncrEn : sl; + signal ccIncrRdy : sl; + signal ccDecrEn : sl; + signal ccDecrRdy : sl; + signal ccWriteEn : sl; + signal ccWriteVal : slv(7 downto 0); + signal ccCnt : slv(7 downto 0); + +begin + + fifoClr <= rst or isReset; + + -- Combinational Mealy method: respHeaderOutNotEmpty() = psnRespOutQ.notEmpty + respHeaderOutNotEmpty <= psnOutValid; + + -- workCompGenReqPipeOut read face (downstream drives rd_en) + workCompGenReqValid <= wcOutValid; + workCompGenReqData <= wcOutDout; + wcOutRdEn <= workCompGenReqRdEn; + + --------------------------------------------------------------------------- + -- 35 SURF Fifo instances (all FWFT / sync / block; cleared by fifoClr). + -- Minimal port map (surf.Fifo unmapped ports carry their entity defaults — + -- same instantiation style as the emitted CountCF/RespHandleSq children). + --------------------------------------------------------------------------- + U_SupportedReqOpCodeCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W01_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f01WrEn, din => f01Din, + not_full => f01NotFull, rd_clk => clk, rd_en => f01RdEn, + dout => f01Dout, valid => f01Valid); + U_ReqOpCodeSeqCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W02_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f02WrEn, din => f02Din, + not_full => f02NotFull, rd_clk => clk, rd_en => f02RdEn, + dout => f02Dout, valid => f02Valid); + U_RnrCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W03_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f03WrEn, din => f03Din, + not_full => f03NotFull, rd_clk => clk, rd_en => f03RdEn, + dout => f03Dout, valid => f03Valid); + U_RnrTriggerQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W04_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f04WrEn, din => f04Din, + not_full => f04NotFull, rd_clk => clk, rd_en => f04RdEn, + dout => f04Dout, valid => f04Valid); + U_QpAccPermCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W05_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f05WrEn, din => f05Din, + not_full => f05NotFull, rd_clk => clk, rd_en => f05RdEn, + dout => f05Dout, valid => f05Valid); + U_ReqPermInfoBuildQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W06_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f06WrEn, din => f06Din, + not_full => f06NotFull, rd_clk => clk, rd_en => f06RdEn, + dout => f06Dout, valid => f06Valid); + U_ReqPermQueryTmpQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W07_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f07WrEn, din => f07Din, + not_full => f07NotFull, rd_clk => clk, rd_en => f07RdEn, + dout => f07Dout, valid => f07Valid); + U_ReqPermQueryQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W08_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f08WrEn, din => f08Din, + not_full => f08NotFull, rd_clk => clk, rd_en => f08RdEn, + dout => f08Dout, valid => f08Valid); + U_ReqPermCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W09_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f09WrEn, din => f09Din, + not_full => f09NotFull, rd_clk => clk, rd_en => f09RdEn, + dout => f09Dout, valid => f09Valid); + U_ReadCacheInsertQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W10_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f10WrEn, din => f10Din, + not_full => f10NotFull, rd_clk => clk, rd_en => f10RdEn, + dout => f10Dout, valid => f10Valid); + U_DupReadReqPermQueryQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W11_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f11WrEn, din => f11Din, + not_full => f11NotFull, rd_clk => clk, rd_en => f11RdEn, + dout => f11Dout, valid => f11Valid); + U_DupReadReqPermCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W12_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f12WrEn, din => f12Din, + not_full => f12NotFull, rd_clk => clk, rd_en => f12RdEn, + dout => f12Dout, valid => f12Valid); + U_ReqAddrCalcQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W13_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f13WrEn, din => f13Din, + not_full => f13NotFull, rd_clk => clk, rd_en => f13RdEn, + dout => f13Dout, valid => f13Valid); + U_ReqRemainingLenCalcQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W14_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f14WrEn, din => f14Din, + not_full => f14NotFull, rd_clk => clk, rd_en => f14RdEn, + dout => f14Dout, valid => f14Valid); + U_ReqEnoughDmaSpaceQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W15_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f15WrEn, din => f15Din, + not_full => f15NotFull, rd_clk => clk, rd_en => f15RdEn, + dout => f15Dout, valid => f15Valid); + U_ReqTotalLenCalcQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W16_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f16WrEn, din => f16Din, + not_full => f16NotFull, rd_clk => clk, rd_en => f16RdEn, + dout => f16Dout, valid => f16Valid); + U_ReqLenCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W17_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f17WrEn, din => f17Din, + not_full => f17NotFull, rd_clk => clk, rd_en => f17RdEn, + dout => f17Dout, valid => f17Valid); + U_IssuePayloadConReqQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W18_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f18WrEn, din => f18Din, + not_full => f18NotFull, rd_clk => clk, rd_en => f18RdEn, + dout => f18Dout, valid => f18Valid); + U_IssuePayloadGenReqQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W19_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f19WrEn, din => f19Din, + not_full => f19NotFull, rd_clk => clk, rd_en => f19RdEn, + dout => f19Dout, valid => f19Valid); + U_IssueAtomicReqQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W20_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f20WrEn, din => f20Din, + not_full => f20NotFull, rd_clk => clk, rd_en => f20RdEn, + dout => f20Dout, valid => f20Valid); + U_RespGenCheck4NormalCaseQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W21_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f21WrEn, din => f21Din, + not_full => f21NotFull, rd_clk => clk, rd_en => f21RdEn, + dout => f21Dout, valid => f21Valid); + U_RespGenCheck4OtherCasesQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W22_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f22WrEn, din => f22Din, + not_full => f22NotFull, rd_clk => clk, rd_en => f22RdEn, + dout => f22Dout, valid => f22Valid); + U_RespCountQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W23_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f23WrEn, din => f23Din, + not_full => f23NotFull, rd_clk => clk, rd_en => f23RdEn, + dout => f23Dout, valid => f23Valid); + U_RespPsnAndMsnQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W24_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f24WrEn, din => f24Din, + not_full => f24NotFull, rd_clk => clk, rd_en => f24RdEn, + dout => f24Dout, valid => f24Valid); + U_WaitAtomicRespQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W25_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f25WrEn, din => f25Din, + not_full => f25NotFull, rd_clk => clk, rd_en => f25RdEn, + dout => f25Dout, valid => f25Valid); + U_AtomicCacheInsertQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W26_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f26WrEn, din => f26Din, + not_full => f26NotFull, rd_clk => clk, rd_en => f26RdEn, + dout => f26Dout, valid => f26Valid); + U_RespCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W27_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f27WrEn, din => f27Din, + not_full => f27NotFull, rd_clk => clk, rd_en => f27RdEn, + dout => f27Dout, valid => f27Valid); + U_DupAtomicReqPermQueryQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W28_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f28WrEn, din => f28Din, + not_full => f28NotFull, rd_clk => clk, rd_en => f28RdEn, + dout => f28Dout, valid => f28Valid); + U_DupAtomicReqPermCheckQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W29_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f29WrEn, din => f29Din, + not_full => f29NotFull, rd_clk => clk, rd_en => f29RdEn, + dout => f29Dout, valid => f29Valid); + U_RespHeaderGenQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W30_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f30WrEn, din => f30Din, + not_full => f30NotFull, rd_clk => clk, rd_en => f30RdEn, + dout => f30Dout, valid => f30Valid); + U_PendingRespQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W31_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f31WrEn, din => f31Din, + not_full => f31NotFull, rd_clk => clk, rd_en => f31RdEn, + dout => f31Dout, valid => f31Valid); + U_WorkCompReqQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => W32_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => f32WrEn, din => f32Din, + not_full => f32NotFull, rd_clk => clk, rd_en => f32RdEn, + dout => f32Dout, valid => f32Valid); + -- output FIFOs + U_WorkCompGenReqOutQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => WCW_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => wcOutWrEn, din => wcOutDin, + not_full => wcOutNotFull, rd_clk => clk, rd_en => wcOutRdEn, + dout => wcOutDout, valid => wcOutValid); + U_RespHeaderOutQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => RHW_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => rhOutWrEn, din => rhOutDin, + not_full => rhOutNotFull, rd_clk => clk, rd_en => rhOutRdEn, + dout => rhOutDout, valid => rhOutValid); + U_PsnRespOutQ : entity surf.Fifo + generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PSW_C, ADDR_WIDTH_G => 4) + port map (rst => fifoClr, wr_clk => clk, wr_en => psnOutWrEn, din => psnOutDin, + not_full => psnOutNotFull, rd_clk => clk, rd_en => psnOutRdEn, + dout => psnOutDout, valid => psnOutValid); + + --------------------------------------------------------------------------- + -- Child entity instances + --------------------------------------------------------------------------- + -- CountCF child (RQ-02): pendingDestReadAtomicReqCnt <- mkCountCF(0) + U_PendingDestReadAtomicReqCnt : entity surf.CountCF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + WIDTH_G => 8, -- PendingReqCnt + RESET_VAL_G => "00000000", -- mkCountCF(0) + FIFO_ADDR_WIDTH_G => 4) + port map ( + clk => clk, + rst => fifoClr, -- rst OR isReset (write/clear path handled inside) + incrOneEn => ccIncrEn, + incrOneRdy => ccIncrRdy, + decrOneEn => ccDecrEn, + decrOneRdy => ccDecrRdy, + writeEn => ccWriteEn, + writeVal => ccWriteVal, + cntOut => ccCnt); + + -- AtomicSrv child (RQ-06 STUB): mkAtomicSrv(cntrlStatus) — CAS/FetchAdd NOT implemented + U_AtomicSrv : entity surf.AtomicSrvConAndGen + generic map ( + TPD_G => TPD_G, + REQ_WIDTH_G => 245, -- AtomicOpReq + RESP_WIDTH_G => 116) -- AtomicOpResp + port map ( + clk => clk, + rst => fifoClr, + reqValid => atomicReqValid, + reqData => atomicReqData, + reqRdy => atomicReqRdy, + respValid => atomicRespValid, + respData => atomicRespData, + respRdy => atomicRespRdEn); + + -- CombineHeaderAndPayload child: drives rdmaRespDataStreamPipeOut. + -- header <- respHeaderOutQ read side; psn <- psnRespOutQ read side; + -- payload <- payloadGenerator.payloadDataStreamPipeOut (external). + U_RdmaRespPipeOut : entity surf.CombineHeaderAndPayload + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false) + port map ( + clk => clk, + rst => rst, + clearAllI => isReset, + headerPipeInValid => rhOutValid, + headerPipeInData => rhOutDout, + headerPipeInRdEn => rhOutRdEn, + payloadPipeInValid => payloadDataStreamValid, + payloadPipeInData => payloadDataStreamData, + payloadPipeInRdEn => payloadDataStreamRdEn, + psnPipeInValid => psnOutValid, + psnPipeInData => psnOutDout, + psnPipeInRdEn => psnOutRdEn, + dataStreamOutValid => rdmaRespDataStreamValid, + dataStreamOutData => rdmaRespDataStreamData, + dataStreamOutRdEn => rdmaRespDataStreamRdEn); + + --------------------------------------------------------------------------- + -- Combinatorial process + -- NOTE: VHDL-2008 process(all) is used deliberately — this entity reads + -- ~150 signals across 9 datapath fill-in phases; an explicit list would be + -- a recurring source of simulation/synthesis mismatch as stages are filled. + --------------------------------------------------------------------------- + comb : process (all) is + variable v : RegType; + -- Block-C combinational error state (BSV: hasErrHappened / inErrorState) + variable hasErrHappened : sl; + variable inErrorState : sl; + -- convenience: pipeline worker enable (BSV workers fire on isNonErr||isERR) + variable workerEnable : boolean; + -- Pre-stage / pipeline datapath temporaries (Phase 1) + variable bthV : slv(95 downto 0); + variable opcodeV : slv(4 downto 0); + variable transV : slv(2 downto 0); + variable psnV : slv(23 downto 0); + variable dlenV : slv(31 downto 0); + variable reqPktInfoV : slv(160 downto 0); + variable reqStatusV : slv(3 downto 0); + variable isReadReqV : boolean; + variable isAccPassV : boolean; + variable respPktNumV : slv(24 downto 0); -- PktNum + variable totRespPktNumV : slv(24 downto 0); + variable isOnlyRespPktV : boolean; + variable curEPSNv : slv(23 downto 0); + variable nextEPSNv : slv(23 downto 0); + variable nextPsnV : slv(23 downto 0); + variable endPsnV : slv(23 downto 0); + variable epochV : sl; + variable preOpCodeV : slv(4 downto 0); + variable maybeRecvReqV : slv(216 downto 0); -- Maybe#RecvReq (tag @216) + -- Phase 2 (perm-check build/query) + variable permCheckReqV : slv(266 downto 0); -- PermCheckReq + variable rethV : slv(127 downto 0); -- RETH + variable pdHandlerV : slv(31 downto 0); -- HandlerPD + variable recvReqV : slv(215 downto 0); -- RecvReq + variable atomicVaV : slv(63 downto 0); -- AtomicEth.va + variable isZeroPayloadV : sl; + variable doPermReqV : boolean; + variable expectPermV : sl; + variable doDupCacheV : boolean; -- Phase 3: gate insertRead / searchReadReq + variable expectDupV : sl; -- Phase 3: expectDupReadCheckResp carry + variable dupStartV : sl; -- Phase 3: DupReadReqStartState (0=FROM_FIRST) + -- Phase 4: DMA addr/len arithmetic (stages 12-16) + variable isSendWrV : boolean; -- isSendReq or isWriteReq + variable curDmaAddrV : slv(63 downto 0); + variable nextDmaAddrV : slv(63 downto 0); + variable sendPktNumV : slv(24 downto 0); + variable remLenV : slv(31 downto 0); + variable totLenV : slv(31 downto 0); + variable pktPayLenV : slv(12 downto 0); -- PktLen + variable enoughChkV : slv(3 downto 0); -- EnoughDmaSpaceCheck (only/first/mid/last) + variable lastOnlyEnV : sl; -- lastOrOnlyPktHasEnoughDmaSpace + variable firstMidEnV : sl; -- firstOrMidPktHasEnoughDmaSpace + variable enoughSpaceV : sl; + variable isLastZeroV : sl; -- isLastPayloadLenZero + variable reqLenResV : slv(129 downto 0); -- ReqLenCheckResult + variable writeMatchV : boolean; + -- Phase 5: PayloadConReq / PayloadGenReq / AtomicOpReq build (stages 17-19) + variable dmaWrMetaV : slv(128 downto 0); -- DmaWriteMetaData + variable dmaRdMetaV : slv(194 downto 0); -- DmaReadMetaData + variable respGenV : slv(72 downto 0); -- RespPktGenInfo + variable hasReqStErrV : sl; + variable doConPutV : boolean; -- stage 17 payloadConReqPort.put fired + variable doGenReqV : boolean; -- stage 18 payloadGenerator.request.put fired + variable doAtomicReqV : boolean; -- stage 19 atomicSrv.request.put fired + variable expRdPayV : sl; -- expectReadRespPayload + variable expAtomicV : sl; -- expectAtomicRespOrig + -- Phase 6: response-gen decision + response-packet loop (stages 20-22) + variable qpHasRespV : boolean; -- qpNeedGenResp(bth.trans) + variable shouldGenRespV : sl; + variable reloadCntV : boolean; -- reloadPendingWorkReqCnt + variable decrCntV : boolean; -- decrPendingWorkReqCnt + variable genEvenNoAckV : boolean; -- shouldGenRespEvenNoAckReq + variable isFirstRespV : boolean; -- isFirstOrOnlyRespPkt (this cycle) + variable isLastRespV : boolean; -- isLastOrOnlyRespPkt (this cycle) + variable remRespPktV : slv(24 downto 0); -- remainingRespPktNum + variable deqRespV : boolean; -- respCountQ.deq this cycle + -- Phase 7: resp PSN/MSN update + atomic resp / atomic-cache insert / read-resp err (stages 23-26) + variable respPSNv : slv(23 downto 0); -- respPSN (stage 23) + variable msnV : slv(23 downto 0); -- MSN (stage 23) + variable isFirstOrOnlyRespV : sl; -- isFirstOrOnlyRespPkt (stage 23, may clear) + variable respPktHdrV : slv(49 downto 0); -- RespPktHeaderInfo + variable doAtomicRespV : boolean; -- stage 24 atomicSrv.response.get fired + variable atomicAckOrigV : slv(64 downto 0); -- Maybe#Long (stage 24) + variable doInsertAtomicV : boolean; -- stage 25 insertAtomic fired + variable atomicEthV : slv(223 downto 0); -- AtomicEth (stage 25) + variable atomicCacheItemV : slv(316 downto 0); -- AtomicCacheItem (stage 25) + variable doPayloadRespV : boolean; -- stage 26 payloadGen.response.get fired + variable hasDmaRdErrV : sl; -- hasDmaReadRespErr (stage 26) + variable expectReadV : sl; -- expectReadRespPayload (stage 26) + -- Phase 8: dup-atomic query/check + response-header gen + resp-pkt emit (stages 27-30) + variable doSearchAtomicV : boolean; -- stage 27 searchAtomicReq fired + variable reqStatus28V : slv(3 downto 0); -- stage 28 reqStatus (may -> DISCARD) + variable shouldGen28V : sl; -- stage 28 shouldGenResp + variable atomicAck28V : slv(64 downto 0); -- stage 28 atomicAckOrig (Maybe#Long) + variable reqStatus29V : slv(3 downto 0); -- stage 29 reqStatus (may -> RMT_OP/DISCARD) + variable shouldGen29V : sl; -- stage 29 shouldGenResp + variable hasErrRespGenV : sl; -- stage 29 hasErrRespGen (Block C sticky) + variable maybeHeaderV : slv(593 downto 0); -- stage 29 Maybe#HeaderRDMA + variable isOnlyReadResp29V : boolean; -- stage 29 isOnlyRespPkt & isReadReq + variable doHeaderEnqV : boolean; -- stage 30 header/psn enq + -- Phase 9 (stage 31 genWorkCompRQ) + variable reqStatus31V : slv(3 downto 0); -- workCompReqQ reqStatus + variable reqOp31V : slv(4 downto 0); -- bth.opcode + variable trans31V : slv(2 downto 0); -- bth.trans + variable wcStatus31V : slv(5 downto 0); -- [5]=valid,[4:0]=WorkCompStatus + variable immDt31V : slv(31 downto 0); -- extractImmDt + variable ieth31V : slv(31 downto 0); -- extractIETH (rkey) + variable immM31V : slv(32 downto 0); -- Maybe#IMM + variable rkeyM31V : slv(32 downto 0); -- Maybe#RKEY + variable doDecr31V : boolean; -- pendingDestReadAtomicReqCnt.decrOne + variable doWcEnq31V : boolean; -- workCompGenReqOutQ.enq + begin + v := r; + + --------------------------------------------------------------------- + -- Default drives (Moore: everything computed into v / driven low) + --------------------------------------------------------------------- + f01WrEn <= '0'; f01RdEn <= '0'; f01Din <= (others => '0'); + f02WrEn <= '0'; f02RdEn <= '0'; f02Din <= (others => '0'); + f03WrEn <= '0'; f03RdEn <= '0'; f03Din <= (others => '0'); + f04WrEn <= '0'; f04RdEn <= '0'; f04Din <= (others => '0'); + f05WrEn <= '0'; f05RdEn <= '0'; f05Din <= (others => '0'); + f06WrEn <= '0'; f06RdEn <= '0'; f06Din <= (others => '0'); + f07WrEn <= '0'; f07RdEn <= '0'; f07Din <= (others => '0'); + f08WrEn <= '0'; f08RdEn <= '0'; f08Din <= (others => '0'); + f09WrEn <= '0'; f09RdEn <= '0'; f09Din <= (others => '0'); + f10WrEn <= '0'; f10RdEn <= '0'; f10Din <= (others => '0'); + f11WrEn <= '0'; f11RdEn <= '0'; f11Din <= (others => '0'); + f12WrEn <= '0'; f12RdEn <= '0'; f12Din <= (others => '0'); + f13WrEn <= '0'; f13RdEn <= '0'; f13Din <= (others => '0'); + f14WrEn <= '0'; f14RdEn <= '0'; f14Din <= (others => '0'); + f15WrEn <= '0'; f15RdEn <= '0'; f15Din <= (others => '0'); + f16WrEn <= '0'; f16RdEn <= '0'; f16Din <= (others => '0'); + f17WrEn <= '0'; f17RdEn <= '0'; f17Din <= (others => '0'); + f18WrEn <= '0'; f18RdEn <= '0'; f18Din <= (others => '0'); + f19WrEn <= '0'; f19RdEn <= '0'; f19Din <= (others => '0'); + f20WrEn <= '0'; f20RdEn <= '0'; f20Din <= (others => '0'); + f21WrEn <= '0'; f21RdEn <= '0'; f21Din <= (others => '0'); + f22WrEn <= '0'; f22RdEn <= '0'; f22Din <= (others => '0'); + f23WrEn <= '0'; f23RdEn <= '0'; f23Din <= (others => '0'); + f24WrEn <= '0'; f24RdEn <= '0'; f24Din <= (others => '0'); + f25WrEn <= '0'; f25RdEn <= '0'; f25Din <= (others => '0'); + f26WrEn <= '0'; f26RdEn <= '0'; f26Din <= (others => '0'); + f27WrEn <= '0'; f27RdEn <= '0'; f27Din <= (others => '0'); + f28WrEn <= '0'; f28RdEn <= '0'; f28Din <= (others => '0'); + f29WrEn <= '0'; f29RdEn <= '0'; f29Din <= (others => '0'); + f30WrEn <= '0'; f30RdEn <= '0'; f30Din <= (others => '0'); + f31WrEn <= '0'; f31RdEn <= '0'; f31Din <= (others => '0'); + f32WrEn <= '0'; f32RdEn <= '0'; f32Din <= (others => '0'); + wcOutWrEn <= '0'; wcOutDin <= (others => '0'); + rhOutWrEn <= '0'; rhOutDin <= (others => '0'); + psnOutWrEn <= '0'; psnOutDin <= (others => '0'); + + pktMetaDeq <= '0'; + recvReqDeq <= '0'; + incEpoch <= '0'; + setRespPktNumValid <= '0'; setRespPktNumData <= (others => '0'); + setEPSNValid <= '0'; setEPSNData <= (others => '0'); + setPreReqOpCodeValid <= '0'; setPreReqOpCodeData <= (others => '0'); + restoreValid <= '0'; restorePreOpCodeData <= (others => '0'); restorePsnData <= (others => '0'); + setPermCheckReqValid <= '0'; setPermCheckReqData <= (others => '0'); + setNextDmaWriteAddrValid <= '0'; setNextDmaWriteAddrData <= (others => '0'); + setSendWriteReqPktNumValid <= '0'; setSendWriteReqPktNumData <= (others => '0'); + setRemainingDmaWriteLenValid <= '0'; setRemainingDmaWriteLenData <= (others => '0'); + setTotalDmaWriteLenValid <= '0'; setTotalDmaWriteLenData <= (others => '0'); + setCurRespPSNValid <= '0'; setCurRespPSNData <= (others => '0'); + setMSNValid <= '0'; setMSNData <= (others => '0'); + payloadConReqValid <= '0'; payloadConReqData <= (others => '0'); + permReqValid <= '0'; permReqData <= (others => '0'); permRespGetEn <= '0'; + payloadGenReqValid <= '0'; payloadGenReqData <= (others => '0'); payloadGenRespGetEn <= '0'; + insertReadValid <= '0'; insertReadData <= (others => '0'); + searchReadReqValid <= '0'; searchReadReqData <= (others => '0'); searchReadRespGetEn <= '0'; + insertAtomicValid <= '0'; insertAtomicData <= (others => '0'); + searchAtomicReqValid <= '0'; searchAtomicReqData <= (others => '0'); searchAtomicRespGetEn <= '0'; + dupCacheClear <= isReset; + atomicReqValid <= '0'; atomicReqData <= (others => '0'); atomicRespRdEn <= '0'; + ccIncrEn <= '0'; ccDecrEn <= '0'; ccWriteEn <= '0'; ccWriteVal <= (others => '0'); + + -- Block C combinational error state (BSV lines 523-524) + hasErrHappened := r.hasReqStatusErr or r.hasDmaReadRespErr; + inErrorState := (isNonErr and hasErrHappened) or isERR; + workerEnable := (isNonErr = '1') or (isERR = '1'); + + -------------------------------------------------------------------- + -- 32-STAGE PIPELINE (conflict-free workers; fire on isNonErr||isERR + -- with input notEmpty + output notFull). Datapath transforms are + -- filled per phase; Phase-0 wires handshake/back-pressure only and + -- leaves each output FIFO din at zero (see file header). + -- The triggerRNR retry-start write (stage 4) is placed here, BEFORE + -- the retry-rule block, to honour the CReg(2) same-cycle forward + -- (OQ-FSM-RHR-02). + -------------------------------------------------------------------- + -- Stage 1 : checkSupportedReqOpCode (f01 -> f02) ReqHandleRQ.bsv:899 + -- f01 = tuple4(pmd[837:189], reqStatus[188:185], reqPktInfo[184:24], curEPSN[23:0]). + -- reqPktInfo[b]=f01[24+b]: bth.opcode=[157:153] bth.trans=[160:158] bth.psn=[88:65] epoch=[64]. + if (workerEnable and f01Valid = '1' and f02NotFull = '1') then + f01RdEn <= '1'; f02WrEn <= '1'; + reqPktInfoV := f01Dout(184 downto 24); + reqStatusV := f01Dout(188 downto 185); + opcodeV := reqPktInfoV(157 downto 153); + transV := reqPktInfoV(160 downto 158); + epochV := reqPktInfoV(64); + curEPSNv := f01Dout(23 downto 0); + if (epochV = getEpoch) then + if (hasErrHappened = '0') then + if (reqStatusV = ST_SEQ_ERR_C) then + reqPktInfoV(88 downto 65) := curEPSNv; -- bth.psn = curEPSN + elsif (not isSupportedReqOp(getTypeQP, opcodeV)) then + if (reqStatusV = ST_NORMAL_C) then + reqStatusV := invReqStatus(transV); + elsif (reqStatusV = ST_DUP_C) then + reqStatusV := ST_DISCARD_C; + end if; + end if; + end if; + else + reqStatusV := ST_DISCARD_C; + end if; + f02Din <= f01Dout(837 downto 189) & reqStatusV & reqPktInfoV; -- tuple3 + end if; + -- Stage 2 : checkNormalReqOpCodeSeq (f02 -> f03) ReqHandleRQ.bsv:952 + -- f02 = tuple3(pmd[813:165], reqStatus[164:161], reqPktInfo[160:0]). + if (workerEnable and f02Valid = '1' and f03NotFull = '1') then + f02RdEn <= '1'; f03WrEn <= '1'; + reqPktInfoV := f02Dout(160 downto 0); + reqStatusV := f02Dout(164 downto 161); + opcodeV := reqPktInfoV(157 downto 153); + transV := reqPktInfoV(160 downto 158); + epochV := reqPktInfoV(64); + preOpCodeV := getPreReqOpCode; -- enqueued as-read + if (epochV = getEpoch) then + if (reqStatusV = ST_NORMAL_C and hasErrHappened = '0') then + if (checkNormalSeq(preOpCodeV, opcodeV)) then + setPreReqOpCodeValid <= '1'; + setPreReqOpCodeData <= opcodeV; + else + reqStatusV := invReqStatus(transV); + end if; + end if; + else + reqStatusV := ST_DISCARD_C; + end if; + f03Din <= f02Dout(813 downto 165) & reqStatusV & reqPktInfoV & preOpCodeV; -- tuple4 + end if; + -- Stage 3 : checkRNR (f03 -> f04) ReqHandleRQ.bsv:999 + -- f03 = tuple4(pmd[818:170], reqStatus[169:166], reqPktInfo[165:5], preOpCode[4:0]). + -- pmd[i]=f03[170+i]: isZeroPayloadLen=pmd[627]=f03[797]. + if (workerEnable and f03Valid = '1' and f04NotFull = '1') then + f03RdEn <= '1'; f04WrEn <= '1'; + reqPktInfoV := f03Dout(165 downto 5); + reqStatusV := f03Dout(169 downto 166); + preOpCodeV := f03Dout(4 downto 0); + epochV := reqPktInfoV(64); + psnV := reqPktInfoV(88 downto 65); -- bth.psn + maybeRecvReqV := (others => '0'); -- tagged Invalid + if (epochV = getEpoch) then + -- Duplicate requests do not use RecvReq + if (reqStatusV = ST_NORMAL_C and hasErrHappened = '0' and + ((reqPktInfoV(5) = '1' and reqPktInfoV(14) = '1') -- isFirstOrOnlyPkt & isSendReq + or reqPktInfoV(12) = '1')) then -- isWriteImmReq + if (recvReqValid = '1') then + maybeRecvReqV := '1' & recvReqData; -- tagged Valid recvReq + recvReqDeq <= '1'; + else + reqStatusV := ST_RNR_C; + restoreValid <= '1'; -- restorePreReqOpCodeAndEPSN + restorePreOpCodeData <= preOpCodeV; + restorePsnData <= psnV; + end if; + elsif (reqStatusV = ST_ERR_FLUSH_RR_C) then + if (recvReqValid = '1') then + maybeRecvReqV := '1' & recvReqData; + recvReqDeq <= '1'; + end if; + end if; + else + reqStatusV := ST_DISCARD_C; + end if; + f04Din <= f03Dout(818 downto 170) & reqStatusV & reqPktInfoV & preOpCodeV & maybeRecvReqV; -- tuple5 + end if; + -- Stage 4 : triggerRNR (f04 -> f05) ReqHandleRQ.bsv:1094 + -- f04 = tuple5(pmd[1035:387], reqStatus[386:383], reqPktInfo[382:222], + -- preOpCode[221:217], maybeRecvReq[216:0]). f05 = tuple4 drops preOpCode. + -- retryStartReg[0] write (v.retryStart*) is placed here, BEFORE the retry-rule + -- block, so retryStart's port-1 read sees it this cycle (CReg(2), OQ-FSM-RHR-02). + if (workerEnable and f04Valid = '1' and f05NotFull = '1') then + f04RdEn <= '1'; f05WrEn <= '1'; + reqPktInfoV := f04Dout(382 downto 222); + reqStatusV := f04Dout(386 downto 383); + epochV := reqPktInfoV(64); + v.retryStartValid := '0'; -- retryStartReg[0] <= Invalid (default) + if (epochV = getEpoch) then + if (hasErrHappened = '0') then + if (reqStatusV = ST_RNR_C) then + incEpoch <= '1'; + v.retryStartValid := '1'; + v.retryStartState := RQ_RNR_RETRY_FLUSH_S; + elsif (reqStatusV = ST_SEQ_ERR_C) then + incEpoch <= '1'; + v.retryStartValid := '1'; + v.retryStartState := RQ_SEQ_RETRY_FLUSH_S; + end if; + end if; + else + reqStatusV := ST_DISCARD_C; + end if; + v.minRnrTimer := getMinRnrTimer; + f05Din <= f04Dout(1035 downto 387) & reqStatusV & reqPktInfoV & f04Dout(216 downto 0); -- tuple4 + end if; + -- Stage 5 : checkQpAccPermAndReadAtomicReqNum (f05 -> f06) + CountCF incrOne + -- (BSV checkQpAccPermAndReadAtomicReqNum @1144) + -- f05/f06 tuple4: pmd[1030:382] reqStatus[381:378] reqPktInfo[377:217] maybeRecvReq[216:0] + if (workerEnable and f05Valid = '1' and f06NotFull = '1') then + f05RdEn <= '1'; f06WrEn <= '1'; + reqPktInfoV := f05Dout(377 downto 217); + reqStatusV := f05Dout(381 downto 378); + transV := reqPktInfoV(160 downto 158); + if (reqStatusV = ST_NORMAL_C and hasErrHappened = '0') then + if (reqPktInfoV(11) = '1' or reqPktInfoV(10) = '1') then -- isReadReq or isAtomicReq + ccIncrEn <= '1'; -- pendingDestReadAtomicReqCnt.incrOne + if (unsigned(ccCnt) >= unsigned(getPendingDestReadAtomicReqNum)) then + reqStatusV := invReqStatus(transV); -- getInvReqStatusByTransType + end if; + end if; + end if; + f06Din <= f05Dout(1030 downto 382) & reqStatusV & reqPktInfoV & f05Dout(216 downto 0); + end if; + -- Stage 6a : buildPermCheckReq4SendWrite (f06 -> f07) (BSV @1197) + -- The commented-out "buildPermCheckReq" (BSV @1404) is NOT in the design; the + -- perm-build flow is the linear 6a -> 6b chain (send/write here, read/atomic in 6b). + -- f07 tuple6: pmd[1425:777] reqStatus[776:773] permCheckReq[772:506] + -- reqPktInfo[505:345] reth[344:217] maybeRecvReq[216:0] + if (workerEnable and f06Valid = '1' and f07NotFull = '1') then + f06RdEn <= '1'; f07WrEn <= '1'; + reqPktInfoV := f06Dout(377 downto 217); + reqStatusV := f06Dout(381 downto 378); + maybeRecvReqV := f06Dout(216 downto 0); + recvReqV := f06Dout(215 downto 0); + pdHandlerV := f06Dout(415 downto 384); -- pmd.pdHandler = pmd[33:2] + isZeroPayloadV := f06Dout(1009); -- pmd.isZeroPayloadLen = pmd[627] + rethV := f06Dout(912 downto 785); -- RETH = pmd[530:403] + -- default PermCheckReq (BSV @1216): wrID Invalid, keys/addr/len 0, + -- localOrRmtKey=True, pdHandler, isZeroDmaLen=True, accFlags=LOCAL_WRITE + permCheckReqV := (others => '0'); + permCheckReqV(137) := '1'; -- localOrRmtKey = True + permCheckReqV(40 downto 9) := pdHandlerV; -- pdHandler + permCheckReqV(8) := '1'; -- isZeroDmaLen = True + permCheckReqV(7 downto 0) := ACC_LOCAL_WRITE_C; -- accFlags + if (hasErrHappened = '0') then + if (reqPktInfoV(14) = '1' and reqStatusV = ST_NORMAL_C) then -- send && normal + if (reqPktInfoV(5) = '1') then -- isFirstOrOnlyPkt + permCheckReqV := (others => '0'); + permCheckReqV(266) := '1'; -- wrID Valid + permCheckReqV(265 downto 202) := recvReqV(215 downto 152); -- wrID = recvReq.id + permCheckReqV(201 downto 170) := recvReqV(55 downto 24); -- lkey = recvReq.lkey + permCheckReqV(137) := '1'; -- localOrRmtKey = True + permCheckReqV(136 downto 73) := recvReqV(119 downto 56); -- reqAddr = recvReq.laddr + if (isZeroPayloadV = '0') then + permCheckReqV(72 downto 41) := recvReqV(151 downto 120); -- totalLen = recvReq.len + end if; + permCheckReqV(40 downto 9) := pdHandlerV; + permCheckReqV(8) := isZeroPayloadV; -- isZeroDmaLen + permCheckReqV(7 downto 0) := ACC_LOCAL_WRITE_C; + setPermCheckReqValid <= '1'; + setPermCheckReqData <= permCheckReqV; + else + permCheckReqV := getPermCheckReq; -- continuation packet + end if; + elsif (reqPktInfoV(13) = '1' and reqStatusV = ST_NORMAL_C) then -- write && normal + if (reqPktInfoV(5) = '1') then -- isFirstOrOnlyPkt + permCheckReqV := (others => '0'); -- wrID Invalid + permCheckReqV(169 downto 138) := rethV(63 downto 32); -- rkey = reth.rkey + permCheckReqV(137) := '0'; -- localOrRmtKey = False + permCheckReqV(136 downto 73) := rethV(127 downto 64); -- reqAddr = reth.va + permCheckReqV(72 downto 41) := rethV(31 downto 0); -- totalLen = reth.dlen + permCheckReqV(40 downto 9) := pdHandlerV; + permCheckReqV(8) := toSl(unsigned(rethV(31 downto 0)) = 0); -- isZeroRethLen + permCheckReqV(7 downto 0) := ACC_REMOTE_WRITE_C; + setPermCheckReqValid <= '1'; + setPermCheckReqData <= permCheckReqV; + else + permCheckReqV := getPermCheckReq; -- continuation packet + end if; + if (reqPktInfoV(12) = '1') then -- isWriteImmReq + permCheckReqV(266) := '1'; -- wrID Valid + permCheckReqV(265 downto 202) := recvReqV(215 downto 152); -- wrID = recvReq.id + end if; + end if; + end if; + f07Din <= f06Dout(1030 downto 382) & reqStatusV & permCheckReqV + & reqPktInfoV & rethV & maybeRecvReqV; + end if; + -- Stage 6b : buildPermCheckReq4ReadAtomic (f07 -> f08) (BSV @1326) + -- f08 tuple5: pmd[1208:560] reqStatus[559:556] permCheckReq[555:289] + -- reqPktInfo[288:128] reth[127:0] + if (workerEnable and f07Valid = '1' and f08NotFull = '1') then + f07RdEn <= '1'; f08WrEn <= '1'; + reqPktInfoV := f07Dout(505 downto 345); + reqStatusV := f07Dout(776 downto 773); + permCheckReqV := f07Dout(772 downto 506); + rethV := f07Dout(344 downto 217); + maybeRecvReqV := f07Dout(216 downto 0); + recvReqV := f07Dout(215 downto 0); + pdHandlerV := f07Dout(810 downto 779); -- pmd.pdHandler + atomicVaV := f07Dout(1307 downto 1244); -- AtomicEth.va = pmd[530:467] + if (hasErrHappened = '0') then + if (reqPktInfoV(11) = '1' and (reqStatusV = ST_NORMAL_C or reqStatusV = ST_DUP_C)) then -- read + permCheckReqV(266) := '0'; -- wrID Invalid + permCheckReqV(169 downto 138) := rethV(63 downto 32); -- rkey = reth.rkey + permCheckReqV(137) := '0'; -- localOrRmtKey = False + permCheckReqV(136 downto 73) := rethV(127 downto 64); -- reqAddr = reth.va + permCheckReqV(72 downto 41) := rethV(31 downto 0); -- totalLen = reth.dlen + permCheckReqV(40 downto 9) := pdHandlerV; + permCheckReqV(8) := toSl(unsigned(rethV(31 downto 0)) = 0); + permCheckReqV(7 downto 0) := ACC_REMOTE_READ_C; + elsif (reqPktInfoV(10) = '1' and reqStatusV = ST_NORMAL_C) then -- atomic + permCheckReqV(266) := '0'; -- wrID Invalid + permCheckReqV(169 downto 138) := f07Dout(1243 downto 1212); -- rkey = AtomicEth.rkey = pmd[466:435] + permCheckReqV(137) := '0'; -- localOrRmtKey = False + permCheckReqV(136 downto 73) := atomicVaV; -- reqAddr = atomicEth.va + permCheckReqV(72 downto 41) := ATOMIC_WORK_REQ_LEN_C; -- totalLen = ATOMIC_WORK_REQ_LEN + permCheckReqV(40 downto 9) := pdHandlerV; + permCheckReqV(8) := '0'; -- isZeroDmaLen = False + permCheckReqV(7 downto 0) := ACC_REMOTE_ATOMIC_C; + end if; + end if; + if (reqStatusV = ST_ERR_FLUSH_RR_C) then + if (maybeRecvReqV(216) = '1') then -- Valid recvReq + permCheckReqV(266) := '1'; -- wrID Valid + permCheckReqV(265 downto 202) := recvReqV(215 downto 152); -- wrID = recvReq.id + permCheckReqV(201 downto 170) := recvReqV(55 downto 24); -- lkey = recvReq.lkey + permCheckReqV(136 downto 73) := recvReqV(119 downto 56); -- reqAddr = recvReq.laddr + permCheckReqV(72 downto 41) := recvReqV(151 downto 120); -- totalLen = recvReq.len + end if; + end if; + f08Din <= f07Dout(1425 downto 777) & reqStatusV & permCheckReqV + & reqPktInfoV & rethV; + end if; + -- Stage 7 : queryPerm4NormalReq (f08 -> f09) + permCheckSrv.request.put (BSV @1646) + -- f09 tuple6: pmd[1209:561] reqStatus[560:557] permCheckReq[556:290] + -- reqPktInfo[289:129] reth[128:1] expectPermCheckResp[0] + -- The permCheckSrv.request.put is conditional (inside the if); the rule fires + -- (deq/enq) even when not putting, so gate on permReqReady only when doPermReq. + reqPktInfoV := f08Dout(288 downto 128); + permCheckReqV := f08Dout(555 downto 289); + reqStatusV := f08Dout(559 downto 556); + doPermReqV := (reqPktInfoV(5) = '1') and (hasErrHappened = '0') + and (reqStatusV = ST_NORMAL_C) and (permCheckReqV(8) = '0'); -- !isZeroDmaLen + if (workerEnable and f08Valid = '1' and f09NotFull = '1' + and (not doPermReqV or permReqReady = '1')) then + f08RdEn <= '1'; f09WrEn <= '1'; + expectPermV := '0'; + if (doPermReqV) then + permReqValid <= '1'; + permReqData <= permCheckReqV; + expectPermV := '1'; + end if; + f09Din <= f08Dout(1208 downto 560) & reqStatusV & permCheckReqV + & reqPktInfoV & f08Dout(127 downto 0) & expectPermV; + end if; + -- Stage 8 : checkPerm4NormalReq (f09 -> f10) + permCheckSrv.response.get (BSV @1675) + -- f10 tuple5 (same layout as f08): pmd[1208:560] reqStatus[559:556] + -- permCheckReq[555:289] reqPktInfo[288:128] reth[127:0] + -- response.get is conditional on expectPermCheckResp; gate on permRespValid only then. + expectPermV := f09Dout(0); + if (workerEnable and f09Valid = '1' and f10NotFull = '1' + and (expectPermV = '0' or permRespValid = '1')) then + f09RdEn <= '1'; f10WrEn <= '1'; + reqPktInfoV := f09Dout(289 downto 129); + permCheckReqV := f09Dout(556 downto 290); + reqStatusV := f09Dout(560 downto 557); + transV := reqPktInfoV(160 downto 158); + atomicVaV := f09Dout(1091 downto 1028); -- AtomicEth.va = pmd[530:467] + if (expectPermV = '1') then + permRespGetEn <= '1'; + if (permRespData = '1') then -- mrCheckResult granted + if (reqPktInfoV(10) = '1') then -- isAtomicReq + if (atomicVaV(2 downto 0) /= "000") then -- !isAlignedAtomicAddr + reqStatusV := invReqStatus(transV); + end if; + end if; + else + reqStatusV := ST_RMT_ACC_C; -- RDMA_REQ_ST_RMT_ACC + end if; + end if; + f10Din <= f09Dout(1209 downto 561) & reqStatusV & permCheckReqV + & reqPktInfoV & f09Dout(128 downto 1); + end if; + -- Stage 9 : insertIntoReadCache (f10 -> f11) + dupReadAtomicCache.insertRead (BSV @1751) + -- f10/f11 tuple5: pmd[1208:560] reqStatus[559:556] permCheckReq[555:289] + -- reqPktInfo[288:128] reth[127:0]. ReadCacheItem(176): startPSN=bth.psn[175:152] + -- endPSN=reqPktInfo.endPSN[151:128] reth[127:0]. + -- insertRead is CONDITIONAL (NORMAL first/only read, no error): fire deq/enq + -- unconditionally, gate on insertReadReady only when inserting; payload is unchanged. + reqStatusV := f10Dout(559 downto 556); + reqPktInfoV := f10Dout(288 downto 128); + doDupCacheV := (reqStatusV = ST_NORMAL_C) and (reqPktInfoV(11) = '1') -- isReadReq + and (reqPktInfoV(5) = '1') and (hasErrHappened = '0'); -- isFirstOrOnlyPkt + if (workerEnable and f10Valid = '1' and f11NotFull = '1' + and (not doDupCacheV or insertReadReady = '1')) then + f10RdEn <= '1'; f11WrEn <= '1'; + if (doDupCacheV) then + insertReadValid <= '1'; + insertReadData <= f10Dout(216 downto 193) -- startPSN = bth.psn = reqPktInfo[88:65] + & f10Dout(166 downto 143) -- endPSN = reqPktInfo[38:15] + & f10Dout(127 downto 0); -- reth + end if; + f11Din <= f10Dout; -- tuple5 threaded unchanged + end if; + -- Stage 10 : queryPerm4DupReadReq (f11 -> f12) + dupReadAtomicCache.searchReadReq (BSV @1785) + -- f12 tuple6: f11 payload + expectDupReadCheckResp[0]. + -- searchReadReq is CONDITIONAL (DUP first/only read, no error); expectDup mirrors it. + reqStatusV := f11Dout(559 downto 556); + reqPktInfoV := f11Dout(288 downto 128); + doDupCacheV := (reqStatusV = ST_DUP_C) and (reqPktInfoV(11) = '1') -- isReadReq + and (reqPktInfoV(5) = '1') and (hasErrHappened = '0'); -- isFirstOrOnlyPkt + if (workerEnable and f11Valid = '1' and f12NotFull = '1' + and (not doDupCacheV or searchReadReqReady = '1')) then + f11RdEn <= '1'; f12WrEn <= '1'; + expectDupV := '0'; + if (doDupCacheV) then + searchReadReqValid <= '1'; + searchReadReqData <= f11Dout(216 downto 193) -- startPSN = bth.psn + & f11Dout(166 downto 143) -- endPSN + & f11Dout(127 downto 0); -- reth + expectDupV := '1'; + end if; + f12Din <= f11Dout & expectDupV; + end if; + -- Stage 11 : checkPerm4DupReadReq (f12 -> f13) + dupReadAtomicCache.searchReadResp (BSV @1821) + -- f12 tuple6: pmd[1209:561] reqStatus[560:557] permCheckReq[556:290] + -- reqPktInfo[289:129] reth[128:1] expectDup[0]. + -- f13 tuple5: pmd[1081:433] reqStatus[432:429] permCheckReq[428:162] + -- reqPktInfo[161:1] dupReadReqStartState[0]. + -- searchReadResp Maybe#Tuple3 (242b): valid[241] origReadCacheItem[240:65] + -- verifiedDupReadAddr(ADDR)[64:1] dupReadReqStart(DupReadReqStartState)[0]. + -- response.get is CONDITIONAL on expectDup; on Valid patch permCheckReq.reqAddr and + -- carry dupReadReqStart; on Invalid mark DISCARD (drop erroneous duplicate). + expectDupV := f12Dout(0); + if (workerEnable and f12Valid = '1' and f13NotFull = '1' + and (expectDupV = '0' or searchReadRespValid = '1')) then + f12RdEn <= '1'; f13WrEn <= '1'; + reqStatusV := f12Dout(560 downto 557); + permCheckReqV := f12Dout(556 downto 290); + dupStartV := '0'; -- DUP_READ_REQ_START_FROM_FIRST + if (expectDupV = '1') then + searchReadRespGetEn <= '1'; + if (searchReadRespData(241) = '1') then -- tagged Valid + permCheckReqV(136 downto 73) := searchReadRespData(64 downto 1); -- reqAddr = verifiedDupReadAddr + dupStartV := searchReadRespData(0); -- dupReadReqStart + else + reqStatusV := ST_DISCARD_C; -- discard duplicate w/ error + end if; + end if; + f13Din <= f12Dout(1209 downto 561) & reqStatusV & permCheckReqV + & f12Dout(289 downto 129) & dupStartV; + end if; + -- Stage 12 : calcNormalSendWriteReqDmaAddr (f13 -> f14 = f13 & curDmaWriteAddr[63:0]) (BSV @1888) + -- f13 tuple5: pmd[1081:433] reqStatus[432:429] permCheckReq[428:162] reqPktInfo[161:1] + -- dupReadReqStartState[0]. reqPktInfo.isSendReq=[15] isWriteReq=[14] isOnlyPkt=[10] + -- isFirstPkt=[9] isMidPkt=[8] isLastPkt=[7]; permCheckReq.reqAddr=f13[298:235]. oneAsPSN=1. + if (workerEnable and f13Valid = '1' and f14NotFull = '1') then + f13RdEn <= '1'; f14WrEn <= '1'; + reqStatusV := f13Dout(432 downto 429); + isSendWrV := (f13Dout(15) = '1') or (f13Dout(14) = '1'); + curDmaAddrV := f13Dout(298 downto 235); -- default: permCheckReq.reqAddr + nextDmaAddrV := getNextDmaWriteAddr; -- default: keep context reg + sendPktNumV := getSendWriteReqPktNum; -- default: keep context reg + if (isSendWrV) then + if (f13Dout(10) = '1') then -- isOnlyPkt + nextDmaAddrV := f13Dout(298 downto 235); + sendPktNumV := slv(to_unsigned(1, 25)); + elsif (f13Dout(9) = '1') then -- isFirstPkt + nextDmaAddrV := addrAddOnePmtu(f13Dout(298 downto 235), getPMTU); + sendPktNumV := slv(to_unsigned(1, 25)); + elsif (f13Dout(8) = '1') then -- isMidPkt + curDmaAddrV := getNextDmaWriteAddr; + nextDmaAddrV := addrAddOnePmtu(getNextDmaWriteAddr, getPMTU); + sendPktNumV := slv(unsigned(getSendWriteReqPktNum) + 1); + elsif (f13Dout(7) = '1') then -- isLastPkt + curDmaAddrV := getNextDmaWriteAddr; + nextDmaAddrV := f13Dout(298 downto 235); + sendPktNumV := slv(unsigned(getSendWriteReqPktNum) + 1); + end if; + if (reqStatusV = ST_NORMAL_C and hasErrHappened = '0') then + setNextDmaWriteAddrValid <= '1'; setNextDmaWriteAddrData <= nextDmaAddrV; + setSendWriteReqPktNumValid <= '1'; setSendWriteReqPktNumData <= sendPktNumV; + end if; + end if; + f14Din <= f13Dout & curDmaAddrV; + end if; + -- Stage 13 : calcNormalSendWriteReqDmaRemainingLen (f14 -> f15) (BSV @1966) + -- f14 tuple6: pmd[1145:497] reqStatus[496:493] permCheckReq[492:226] reqPktInfo[225:65] + -- dupReadReqStartState[64] curDmaWriteAddr[63:0]. isSendReq=[79] isWriteReq=[78] + -- isOnlyPkt=[74] isFirstPkt=[73] isMidPkt=[72] isLastPkt=[71]; permCheckReq.totalLen=f14[298:267]; + -- pmd.pktPayloadLen=f14[1145:1133]. f15 = f14 & remainingDmaWriteLen[63:32] & preRemaining[31:0]. + if (workerEnable and f14Valid = '1' and f15NotFull = '1') then + f14RdEn <= '1'; f15WrEn <= '1'; + reqStatusV := f14Dout(496 downto 493); + isSendWrV := (f14Dout(79) = '1') or (f14Dout(78) = '1'); + pktPayLenV := f14Dout(1145 downto 1133); + remLenV := getRemainingDmaWriteLen; -- default: keep context reg + if (isSendWrV) then + if (f14Dout(74) = '1') then -- isOnlyPkt + remLenV := lenSubPktLen(f14Dout(298 downto 267), pktPayLenV, getPMTU); + elsif (f14Dout(73) = '1') then -- isFirstPkt + remLenV := lenSubOnePmtu(f14Dout(298 downto 267), getPMTU); + elsif (f14Dout(72) = '1') then -- isMidPkt + remLenV := lenSubOnePmtu(getRemainingDmaWriteLen, getPMTU); + elsif (f14Dout(71) = '1') then -- isLastPkt + remLenV := lenSubPktLen(getRemainingDmaWriteLen, pktPayLenV, getPMTU); + end if; + if (reqStatusV = ST_NORMAL_C and hasErrHappened = '0') then + setRemainingDmaWriteLenValid <= '1'; setRemainingDmaWriteLenData <= remLenV; + end if; + end if; + -- preRemainingDmaWriteLen = contextRQ.getRemainingDmaWriteLen (pre-update value) + f15Din <= f14Dout & remLenV & getRemainingDmaWriteLen; + end if; + -- Stage 14 : calcNormalSendWriteReqEnoughDmaSpace (f15 -> f16) (BSV @2039) + -- f15 tuple8: pmd[1209:561] reqStatus[560:557] permCheckReq[556:290] reqPktInfo[289:129] + -- dupReadReqStartState[128] curDmaWriteAddr[127:64] remainingDmaWriteLen[63:32] + -- preRemainingDmaWriteLen[31:0]. isSendReq=[143] isWriteReq=[142] isOnlyPkt=[138] + -- isFirstPkt=[137]; permCheckReq.totalLen=f15[362:331]; pmd.pktPayloadLen=f15[1209:1197]. + -- EnoughDmaSpaceCheck(4): onlyPktCase[3] firstPktCase[2] midPktCase[1] lastPktCase[0]. + if (workerEnable and f15Valid = '1' and f16NotFull = '1') then + f15RdEn <= '1'; f16WrEn <= '1'; + isSendWrV := (f15Dout(143) = '1') or (f15Dout(142) = '1'); + pktPayLenV := f15Dout(1209 downto 1197); + if (f15Dout(138) = '1') then -- isOnlyPkt ? totalLen : preRemaining + lastOnlyEnV := toSl(lenGtEqPktLen(f15Dout(362 downto 331), pktPayLenV, getPMTU)); + else + lastOnlyEnV := toSl(lenGtEqPktLen(f15Dout(31 downto 0), pktPayLenV, getPMTU)); + end if; + if (f15Dout(137) = '1') then -- isFirstPkt ? totalLen : preRemaining + firstMidEnV := toSl(lenGtEqPmtu(f15Dout(362 downto 331), getPMTU)); + else + firstMidEnV := toSl(lenGtEqPmtu(f15Dout(31 downto 0), getPMTU)); + end if; + enoughChkV := (others => '0'); + if (isSendWrV) then + enoughChkV := lastOnlyEnV & firstMidEnV & firstMidEnV & lastOnlyEnV; -- only/first/mid/last + end if; + f16Din <= f15Dout(1209 downto 32) & enoughChkV; -- drop preRemaining[31:0], append check + end if; + -- Stage 15 : calcNormalSendWriteReqDmaTotalLen (f16 -> f17) (BSV @2095) + -- f16 tuple8: pmd[1181:533] reqStatus[532:529] permCheckReq[528:262] reqPktInfo[261:101] + -- dupReadReqStartState[100] curDmaWriteAddr[99:36] remainingDmaWriteLen[35:4] + -- enoughDmaSpaceCheck[3:0]. isSendReq=[115] isWriteReq=[114] isOnlyPkt=[110] isFirstPkt=[109] + -- isMidPkt=[108] isLastPkt=[107]; pmd.pktPayloadLen=f16[1181:1169]; pmd.isZeroPayloadLen=f16[1160]; + -- enoughDmaSpaceCheck onlyPktCase=[3] firstPktCase=[2] midPktCase=[1] lastPktCase=[0]. + -- f17 tuple6: pmd reqStatus permCheckReq reqPktInfo reqLenCheckResult[130:1] dupReadReqStartState[0]. + -- ReqLenCheckResult(130): enoughDmaSpace[129] isLastPayloadLenZero[128] curDmaWriteAddr[127:64] + -- remainingDmaWriteLen[63:32] totalDmaWriteLen[31:0]. + if (workerEnable and f16Valid = '1' and f17NotFull = '1') then + f16RdEn <= '1'; f17WrEn <= '1'; + reqStatusV := f16Dout(532 downto 529); + isSendWrV := (f16Dout(115) = '1') or (f16Dout(114) = '1'); + pktPayLenV := f16Dout(1181 downto 1169); + totLenV := getTotalDmaWriteLen; -- default: keep context reg + enoughSpaceV := '0'; + isLastZeroV := '0'; + if (isSendWrV) then + if (f16Dout(110) = '1') then -- isOnlyPkt + totLenV := slv(resize(unsigned(pktPayLenV), 32)); + enoughSpaceV := f16Dout(0); -- lastPktCase + elsif (f16Dout(109) = '1') then -- isFirstPkt + totLenV := slv(resize(unsigned(calcPmtuLen(getPMTU)), 32)); + enoughSpaceV := f16Dout(1); -- midPktCase + elsif (f16Dout(108) = '1') then -- isMidPkt + totLenV := lenAddOnePmtu(getTotalDmaWriteLen, getPMTU); + enoughSpaceV := f16Dout(2); -- firstPktCase + elsif (f16Dout(107) = '1') then -- isLastPkt + totLenV := lenAddPktLen(getTotalDmaWriteLen, pktPayLenV, getPMTU); + enoughSpaceV := f16Dout(3); -- onlyPktCase + isLastZeroV := f16Dout(1160); -- isZeroPayloadLen + end if; + if (reqStatusV = ST_NORMAL_C and hasErrHappened = '0') then + setTotalDmaWriteLenValid <= '1'; setTotalDmaWriteLenData <= totLenV; + end if; + end if; + reqLenResV := enoughSpaceV & isLastZeroV & f16Dout(99 downto 36) -- curDmaWriteAddr + & f16Dout(35 downto 4) & totLenV; -- remainingDmaWriteLen, totalDmaWriteLen + f17Din <= f16Dout(1181 downto 101) & reqLenResV & f16Dout(100); + end if; + -- Stage 16 : checkReqLen (f17 -> f18) (BSV @2179) + -- f17 tuple6: pmd[1211:563] reqStatus[562:559] permCheckReq[558:292] reqPktInfo[291:131] + -- reqLenCheckResult[130:1] dupReadReqStartState[0]. reqLenCheckResult: enoughDmaSpace=[130] + -- isLastPayloadLenZero=[129] curDmaWriteAddr=[128:65] remainingDmaWriteLen=[64:33] + -- totalDmaWriteLen=[32:1]. reqPktInfo.isSendReq=[145] isWriteReq=[144] isOnlyPkt=[140] + -- isLastPkt=[137]; bth.trans=f17[291:289]; permCheckReq.totalLen field=permCheckReqV[72:41]. + -- f18 tuple6: pmd reqStatus permCheckReq reqPktInfo curDmaWriteAddr[64:1] dupReadReqStartState[0]. + if (workerEnable and f17Valid = '1' and f18NotFull = '1') then + f17RdEn <= '1'; f18WrEn <= '1'; + reqStatusV := f17Dout(562 downto 559); + permCheckReqV := f17Dout(558 downto 292); + enoughSpaceV := f17Dout(130); + isLastZeroV := f17Dout(129); + remLenV := f17Dout(64 downto 33); + totLenV := f17Dout(32 downto 1); + isSendWrV := (f17Dout(145) = '1') or (f17Dout(144) = '1'); + if (isSendWrV and reqStatusV = ST_NORMAL_C and hasErrHappened = '0') then + -- writeReqLenMatch = (isWrite && (last||only)) ? isZero(remaining) : True + if ((f17Dout(144) = '1') and ((f17Dout(137) = '1') or (f17Dout(140) = '1'))) then + writeMatchV := (unsigned(remLenV) = 0); + else + writeMatchV := true; + end if; + if (enoughSpaceV = '0' or (not writeMatchV) or isLastZeroV = '1') then + reqStatusV := invReqStatus(f17Dout(291 downto 289)); -- getInvReqStatusByTransType(bth.trans) + elsif ((f17Dout(145) = '1') and ((f17Dout(137) = '1') or (f17Dout(140) = '1'))) then + permCheckReqV(72 downto 41) := totLenV; -- send req: update totalLen + end if; + end if; + f18Din <= f17Dout(1211 downto 563) & reqStatusV & permCheckReqV + & f17Dout(291 downto 131) & f17Dout(128 downto 65) & f17Dout(0); + end if; + -- Stage 17 : issuePayloadConReqOrDiscard (f18 -> f19) + payloadConReqPort.put (BSV @2248) + -- f18 tuple6: pmd[1145:497] reqStatus[496:493] permCheckReq[492:226] reqPktInfo[225:65] + -- curDmaWriteAddr[64:1] dupReadReqStartState[0]. isSendReq=[79] isWriteReq=[78]; + -- permCheckReq.isZeroDmaLen=f18[234]; pmd.isZeroPayloadLen=f18[1124]; + -- pmd.pktFragNum=f18[1132:1125]; pmd.pktPayloadLen=f18[1145:1133]; bth.psn=f18[153:130]. + -- PayloadConReq(203): fragNum[202:195] consumeInfo[194:0]; consumeInfo = tag[194:193] & + -- pad[192:129] & DmaWriteMetaData[128:0]. DmaWriteMetaData: initiator[128:125] sqpn[124:101] + -- startAddr[100:37] len(PktLen)[36:24] psn[23:0]. tag: DiscardPayloadInfo="00", + -- SendWriteReqReadRespInfo="10". put is CONDITIONAL (gate ready only when putting). + -- f19 tuple6: pmd reqStatus permCheckReq reqPktInfo hasReqStatusErr[1] dupReadReqStartState[0]. + reqStatusV := f18Dout(496 downto 493); + -- normalPut = NORMAL & !err & (send|write) & !isZeroDmaLen ; discardPut = !(NORMAL&!err) & !isZeroPayloadLen + doConPutV := ((reqStatusV = ST_NORMAL_C) and (hasErrHappened = '0') + and ((f18Dout(79) = '1') or (f18Dout(78) = '1')) and (f18Dout(234) = '0')) + or ((not ((reqStatusV = ST_NORMAL_C) and (hasErrHappened = '0'))) and (f18Dout(1124) = '0')); + if (workerEnable and f18Valid = '1' and f19NotFull = '1' + and (not doConPutV or payloadConReqReady = '1')) then + f18RdEn <= '1'; f19WrEn <= '1'; + if (doConPutV) then + payloadConReqValid <= '1'; + -- DmaWriteMetaData: initiator (WR normal / DISCARD else), sqpn, startAddr=curDmaWriteAddr, + -- len=pktPayloadLen, psn=bth.psn + if ((reqStatusV = ST_NORMAL_C) and (hasErrHappened = '0')) then + dmaWrMetaV := DMA_SRC_RQ_WR_C & getSQPN & f18Dout(64 downto 1) + & f18Dout(1145 downto 1133) & f18Dout(153 downto 130); + payloadConReqData <= f18Dout(1132 downto 1125) -- fragNum + & "10" & slv(to_unsigned(0, 64)) & dmaWrMetaV; -- SendWrite tag + else + dmaWrMetaV := DMA_SRC_RQ_DISCARD_C & getSQPN & f18Dout(64 downto 1) + & f18Dout(1145 downto 1133) & f18Dout(153 downto 130); + payloadConReqData <= f18Dout(1132 downto 1125) -- fragNum + & "00" & slv(to_unsigned(0, 64)) & dmaWrMetaV; -- Discard tag + end if; + end if; + -- Block C error latch: sticky hasReqStatusErr, set on any error request status + hasReqStErrV := r.hasReqStatusErr; + if (isErrReqStatus(reqStatusV)) then + hasReqStErrV := '1'; + end if; + v.hasReqStatusErr := hasReqStErrV; + f19Din <= f18Dout(1145 downto 65) & hasReqStErrV & f18Dout(0); + end if; + -- Stage 18 : issuePayloadGenReq (f19 -> f20) + payloadGenerator.request.put (BSV @2331) + -- f19 tuple6: pmd[1082:434] reqStatus[433:430] permCheckReq[429:163] reqPktInfo[162:2] + -- hasReqStatusErr[1] dupReadReqStartState[0]. isReadReq=f19[13]; + -- permCheckReq.isZeroDmaLen=f19[171] reqAddr=f19[299:236] totalLen=f19[235:204] rkey=f19[332:301]. + -- PayloadGenReq(199): dmaReadMetaData[198:4] addPadding[3] pmtu[2:0]. DmaReadMetaData(195): + -- initiator[194:191] sqpn[190:167] wrID[166:103] startAddr[102:39] len[38:7] mrIdx[6:0]. + -- mrIdx=key2IndexMR(rkey)=rkey[31:25]. request.put is CONDITIONAL. + -- f20 tuple5: pmd reqStatus permCheckReq reqPktInfo respPktGenInfo[72:0]. + -- RespPktGenInfo(73): hasReqStatusErr[72] hasDmaReadRespErr[71] hasErrRespGen[70] shouldGenResp[69] + -- expectReadRespPayload[68] expectAtomicRespOrig[67] expectDupAtomicCheckResp[66] + -- atomicAckOrig(Maybe#Long)[65:1] dupReadReqStartState[0]. + reqStatusV := f19Dout(433 downto 430); + doGenReqV := (f19Dout(1) = '0') and (r.hasDmaReadRespErr = '0') -- !hasReqStatusErr & !hasDmaReadRespErr + and (f19Dout(171) = '0') and (f19Dout(13) = '1') -- !isZeroDmaLen & isReadReq + and ((reqStatusV = ST_NORMAL_C) or (reqStatusV = ST_DUP_C)); + if (workerEnable and f19Valid = '1' and f20NotFull = '1' + and (not doGenReqV or payloadGenReqReady = '1')) then + f19RdEn <= '1'; f20WrEn <= '1'; + expRdPayV := '0'; + if (doGenReqV) then + payloadGenReqValid <= '1'; + -- DmaReadMetaData: initiator=RD, sqpn, wrID=dontCare(0), startAddr=reqAddr, len=totalLen, + -- mrIdx=key2IndexMR(rkey)=rkey[31:25] + dmaRdMetaV := DMA_SRC_RQ_RD_C & getSQPN & slv(to_unsigned(0, 64)) + & f19Dout(299 downto 236) & f19Dout(235 downto 204) & f19Dout(332 downto 326); + payloadGenReqData <= dmaRdMetaV & '1' & getPMTU; -- addPadding=True + expRdPayV := '1'; + end if; + -- RespPktGenInfo: only hasReqStatusErr / hasDmaReadRespErr / expectReadRespPayload / + -- dupReadReqStartState set here; the rest False / Invalid. + respGenV := (others => '0'); + respGenV(72) := f19Dout(1); -- hasReqStatusErr + respGenV(71) := r.hasDmaReadRespErr; -- hasDmaReadRespErr + respGenV(68) := expRdPayV; -- expectReadRespPayload + respGenV(0) := f19Dout(0); -- dupReadReqStartState + f20Din <= f19Dout(1082 downto 2) & respGenV; + end if; + -- Stage 19 : issueAtomicReq (f20 -> f21) + U_AtomicSrv request (RQ-06 STUB) (BSV @2399) + -- f20 tuple5: pmd[1153:505] reqStatus[504:501] permCheckReq[500:234] reqPktInfo[233:73] + -- respPktGenInfo[72:0]. isAtomicReq=f20[83]; bth.opcode=f20[230:226]; bth.psn=f20[161:138]; + -- respPktGenInfo.hasReqStatusErr=f20[72]. AtomicEth from pmd: va=f20[1035:972] + -- swap=f20[939:876] comp=f20[875:812]. + -- AtomicOpReq(245): initiator[244:241] casOrFetchAdd[240] startAddr[239:176] compData[175:112] + -- swapData[111:48] sqpn[47:24] psn[23:0]. casOrFetchAdd = (opcode==COMPARE_SWAP=5'h13). + -- request.put is CONDITIONAL. f21 = f20 with respPktGenInfo.{hasDmaReadRespErr,expectAtomicRespOrig}. + reqStatusV := f20Dout(504 downto 501); + doAtomicReqV := (f20Dout(72) = '0') and (r.hasDmaReadRespErr = '0') -- !hasReqStatusErr & !hasDmaReadRespErr + and (reqStatusV = ST_NORMAL_C) and (f20Dout(83) = '1'); -- NORMAL & isAtomicReq + if (workerEnable and f20Valid = '1' and f21NotFull = '1' + and (not doAtomicReqV or atomicReqRdy = '1')) then + f20RdEn <= '1'; f21WrEn <= '1'; + expAtomicV := '0'; + if (doAtomicReqV) then + atomicReqValid <= '1'; + atomicReqData <= DMA_SRC_RQ_ATOMIC_C & toSl(f20Dout(230 downto 226) = "10011") -- casOrFetchAdd + & f20Dout(1035 downto 972) -- startAddr = atomicEth.va + & f20Dout(875 downto 812) -- compData = atomicEth.comp + & f20Dout(939 downto 876) -- swapData = atomicEth.swap + & getSQPN & f20Dout(161 downto 138); -- sqpn, psn + expAtomicV := '1'; + end if; + respGenV := f20Dout(72 downto 0); + respGenV(71) := r.hasDmaReadRespErr; -- hasDmaReadRespErr + respGenV(67) := expAtomicV; -- expectAtomicRespOrig + f21Din <= f20Dout(1153 downto 73) & respGenV; + end if; + -- Stage 20 : shouldGenResp4NormalCase (f21 -> f22) + coalesce counter (Block E) (BSV @2447) + -- f21 tuple5: pmd[1153:505] reqStatus[504:501] permCheckReq[500:234] reqPktInfo[233:73] + -- respPktGenInfo[72:0]. isSendReq=[87] isWriteReq=[86] isReadReq=[84] isAtomicReq=[83] + -- isLastOrOnlyPkt=[77]; bth.ackReq=[169] bth.trans=[233:231]; respPktGenInfo.hasReqStatusErr=[72] + -- expectAtomicRespOrig=[67] shouldGenResp=[69]. + reqStatusV := f21Dout(504 downto 501); + qpHasRespV := qpNeedGenResp(f21Dout(233 downto 231)); + shouldGenRespV := '0'; + reloadCntV := false; + decrCntV := false; + genEvenNoAckV := (f21Dout(77) = '1') and (r.isCoalesceWorkReqCntZero = '1'); + if (workerEnable and f21Valid = '1' and f22NotFull = '1') then + f21RdEn <= '1'; f22WrEn <= '1'; + if (reqStatusV = ST_NORMAL_C) then + if ((f21Dout(87) = '1') or (f21Dout(86) = '1')) then -- send or write + if ((f21Dout(169) = '1') or genEvenNoAckV) then -- ackReq or coalesce-forced + shouldGenRespV := toSl(qpHasRespV); + reloadCntV := true; + else + decrCntV := (f21Dout(77) = '1'); -- decr on isLastOrOnlyPkt + end if; + elsif (f21Dout(84) = '1') then -- read + shouldGenRespV := toSl(qpHasRespV); + reloadCntV := true; + elsif (f21Dout(83) = '1') then -- atomic + if (f21Dout(67) = '1') then -- expectAtomicRespOrig + shouldGenRespV := toSl(qpHasRespV); + reloadCntV := true; + end if; + end if; + if (qpHasRespV and (f21Dout(72) = '0')) then -- qpHasResp and !hasReqStatusErr + if (reloadCntV) then + v.coalesceWorkReqCnt := slv(unsigned(getPendingWorkReqNum) - 1); + v.isCoalesceWorkReqCntZero := toSl(unsigned(getPendingWorkReqNum) = 1); + elsif (decrCntV) then + v.coalesceWorkReqCnt := slv(unsigned(r.coalesceWorkReqCnt) - 1); + v.isCoalesceWorkReqCntZero := toSl(unsigned(r.coalesceWorkReqCnt) = 1); + end if; + end if; + end if; + respGenV := f21Dout(72 downto 0); + respGenV(69) := shouldGenRespV; -- respPktGenInfo.shouldGenResp + f22Din <= f21Dout(1153 downto 73) & respGenV; + end if; + -- Stage 21 : shouldGenResp4OtherCases (f22 -> f23) (BSV @2546) + -- Recompute shouldGenResp per reqStatus (NORMAL keeps stage-20 value; DUP send/write + -- needs ackReq|last; DUP read always; SEQ_ERR/RNR/INV_*/RMT_* always; DISCARD/FLUSH none). + reqStatusV := f22Dout(504 downto 501); + qpHasRespV := qpNeedGenResp(f22Dout(233 downto 231)); + shouldGenRespV := '0'; + if (workerEnable and f22Valid = '1' and f23NotFull = '1') then + f22RdEn <= '1'; f23WrEn <= '1'; + if (reqStatusV = ST_NORMAL_C) then + shouldGenRespV := f22Dout(69); -- keep stage-20 shouldGenResp + elsif (reqStatusV = ST_DUP_C) then + if ((f22Dout(87) = '1') or (f22Dout(86) = '1')) then -- dup send/write + if ((f22Dout(169) = '1') or (f22Dout(77) = '1')) then -- ackReq or isLastOrOnlyPkt + shouldGenRespV := toSl(qpHasRespV); + end if; + elsif (f22Dout(84) = '1') then -- dup read + shouldGenRespV := toSl(qpHasRespV); + end if; -- dup atomic: none + elsif (reqStatusV = ST_SEQ_ERR_C or reqStatusV = ST_RNR_C or reqStatusV = ST_INV_REQ_C + or reqStatusV = ST_INV_RD_C or reqStatusV = ST_RMT_ACC_C or reqStatusV = ST_RMT_OP_C) then + shouldGenRespV := toSl(qpHasRespV); + end if; -- DISCARD/ERR_FLUSH_RR: no resp + respGenV := f22Dout(72 downto 0); + respGenV(69) := shouldGenRespV; + f23Din <= f22Dout(1153 downto 73) & respGenV; + end if; + -- Stage 22 : countPendingResp (f23 -> f24) — Sub-FSM D response-packet LOOP (BSV @2636) + -- Multi-cycle: emits one respPsnAndMsnQ entry per response packet, deqs respCountQ only on + -- the last/only response packet. f24 tuple6 = f23 tuple5 + respPktSeqInfo[1:0] + -- (isFirstOrOnlyRespPkt[1] isLastOrOnlyRespPkt[0]). reqPktInfo.isOnlyRespPkt=f23[76] + -- respPktNum=f23[136:112]. contextRQ.getRespPktNum/getIsRespPktNumZero/setRespPktNum (RMW). + reqStatusV := f23Dout(504 downto 501); + remRespPktV := getRespPktNum; + isFirstRespV := (r.isFirstOrOnlyRespPkt = '1'); + isLastRespV := (f23Dout(76) = '1') + or ((r.isFirstOrOnlyRespPkt = '0') and (getIsRespPktNumZero = '1')); + deqRespV := false; + if (workerEnable and f23Valid = '1' and f24NotFull = '1') then + f24WrEn <= '1'; + if ((not (reqStatusV = ST_NORMAL_C or reqStatusV = ST_DUP_C)) or (r.hasErrRespGen = '1')) then + -- No response counting after an error response (single-packet error responses) + isFirstRespV := true; + isLastRespV := true; + deqRespV := true; + else + if (isLastRespV) then + deqRespV := true; + end if; + if (isFirstRespV) then + if (f23Dout(76) = '1') then -- isOnlyRespPkt + remRespPktV := (others => '0'); + else + remRespPktV := slv(unsigned(f23Dout(136 downto 112)) - 2); -- respPktNum - 2 + end if; + setRespPktNumValid <= '1'; + setRespPktNumData <= remRespPktV; + elsif (not isLastRespV) then -- middle response packet + setRespPktNumValid <= '1'; + setRespPktNumData <= slv(unsigned(remRespPktV) - 1); + end if; + end if; + v.isFirstOrOnlyRespPkt := toSl(isLastRespV or (r.hasErrRespGen = '1')); + if (deqRespV) then + f23RdEn <= '1'; + end if; + f24Din <= f23Dout & toSl(isFirstRespV) & toSl(isLastRespV); + end if; + -- Stage 23 : updateRespPsnAndMsn (f24 -> f25) (BSV @2708) + -- f24 (1156, tuple6) = pmd[1155:507] reqStatus[506:503] permCheckReq[502:236] + -- reqPktInfo[235:75] respPktGenInfo[74:2] respPktSeqInfo[1:0]. + -- reqPktInfo base 75 (bth = reqPktInfo[160:65]): bth.psn[163:140] isReadReq[86] isLastOrOnlyPkt[79]. + -- respPktSeqInfo: isFirstOrOnlyRespPkt[1] isLastOrOnlyRespPkt[0]. + -- respPktGenInfo base 2: dupReadReqStartState[2] (FROM_MIDDLE=1). + -- respPSN = isFirstOrOnlyRespPkt ? bth.psn : getCurRespPSN; msn = getMSN. + -- f25 (1204, tuple6) = f24[1155:2] (tuple5) & respPktHeaderInfo[49:0] + -- (psn[49:26] msn[25:2] isFirstOrOnlyRespPkt[1] isLastOrOnlyRespPkt[0]). + if (workerEnable and f24Valid = '1' and f25NotFull = '1') then + f24RdEn <= '1'; f25WrEn <= '1'; + isFirstOrOnlyRespV := f24Dout(1); + if (isFirstOrOnlyRespV = '1') then + respPSNv := f24Dout(163 downto 140); -- bth.psn + else + respPSNv := getCurRespPSN; + end if; + msnV := getMSN; + if (r.hasErrRespGen = '0') then + setCurRespPSNValid <= '1'; + setCurRespPSNData <= slv(unsigned(respPSNv) + 1); + if ((f24Dout(506 downto 503) = ST_NORMAL_C) and (f24Dout(79) = '1') and (f24Dout(0) = '1')) then + msnV := slv(unsigned(msnV) + 1); -- isLastOrOnlyReqPkt & isLastOrOnlyRespPkt + setMSNValid <= '1'; + setMSNData <= msnV; + end if; + -- DUP read starting from middle: this resp pkt is no longer the first + if ((f24Dout(506 downto 503) = ST_DUP_C) and (f24Dout(2) = '1')) then + isFirstOrOnlyRespV := '0'; + end if; + end if; + respPktHdrV := respPSNv & msnV & isFirstOrOnlyRespV & f24Dout(0); + f25Din <= f24Dout(1155 downto 2) & respPktHdrV; + end if; + -- Stage 24 : waitAtomicResp (f25 -> f26) + atomicSrv.response.get (BSV @2780) + -- f25/f26 (1204, tuple6): respPktGenInfo[122:50] (expectAtomicRespOrig[117], + -- atomicAckOrig Maybe#Long[115:51]). AtomicOpResp: original[111:48]. + -- response.get is CONDITIONAL on expectAtomicRespOrig; atomicAckOrig := Valid original + -- (else Invalid). f26 = f25 with respPktGenInfo.atomicAckOrig patched. + doAtomicRespV := (f25Dout(117) = '1'); + if (workerEnable and f25Valid = '1' and f26NotFull = '1' + and (not doAtomicRespV or atomicRespValid = '1')) then + f25RdEn <= '1'; f26WrEn <= '1'; + if (doAtomicRespV) then + atomicRespRdEn <= '1'; + atomicAckOrigV := '1' & atomicRespData(111 downto 48); -- tagged Valid original + else + atomicAckOrigV := (others => '0'); -- tagged Invalid + end if; + f26Din <= f25Dout(1203 downto 116) & atomicAckOrigV & f25Dout(50 downto 0); + end if; + -- Stage 25 : insertIntoAtomicCache (f26 -> f27) + dupReadAtomicCache.insertAtomic (BSV @2834) + -- atomicEth = pmd[530:307] (pmd-rel: va[530:467] rkey[466:435] swap[434:371] comp[370:307]); + -- in f26 pmd base 555 -> atomicEth = f26[1085:862]. + -- reqPktInfo base 123 (bth = reqPktInfo[160:65]): bth.psn[211:188] bth.opcode[280:276]. + -- atomicAckOrig[115:51] (value[114:51]). + -- insertAtomic is CONDITIONAL on expectAtomicRespOrig (f26[117]). + -- AtomicCacheItem(317): atomicPSN[316:293] atomicOpCode[292:288] atomicEth[287:64] atomicAckEth[63:0]. + -- f27 (1428, tuple7) = f26 & atomicEth[223:0]. + atomicEthV := f26Dout(1085 downto 862); + doInsertAtomicV := (f26Dout(117) = '1'); + atomicCacheItemV := f26Dout(211 downto 188) & f26Dout(280 downto 276) + & atomicEthV & f26Dout(114 downto 51); + if (workerEnable and f26Valid = '1' and f27NotFull = '1' + and (not doInsertAtomicV or insertAtomicReady = '1')) then + f26RdEn <= '1'; f27WrEn <= '1'; + if (doInsertAtomicV) then + insertAtomicValid <= '1'; + insertAtomicData <= atomicCacheItemV; + end if; + f27Din <= f26Dout & atomicEthV; + end if; + -- Stage 26 : checkReadResp (f27 -> f28) + payloadGen.response.get; sets hasDmaReadRespErr (Block C) (BSV @2903) + -- f27/f28 (1428, tuple7): respPktGenInfo base 274 -> hasDmaReadRespErr[345] + -- hasErrRespGen[344] shouldGenResp[343] expectReadRespPayload[342]. + -- PayloadGenResp(2): addPadding[1] isRespErr[0]. + -- response.get CONDITIONAL on (!hasDmaReadRespErrReg & expectReadRespPayload); on isRespErr: + -- latch sticky v.hasDmaReadRespErr, clear expectReadRespPayload. + doPayloadRespV := (r.hasDmaReadRespErr = '0') and (f27Dout(342) = '1'); + if (workerEnable and f27Valid = '1' and f28NotFull = '1' + and (not doPayloadRespV or payloadGenRespValid = '1')) then + f27RdEn <= '1'; f28WrEn <= '1'; + hasDmaRdErrV := f27Dout(345); -- incoming respPktGenInfo.hasDmaReadRespErr + expectReadV := f27Dout(342); + if (doPayloadRespV) then + payloadGenRespGetEn <= '1'; + if (payloadGenRespData(0) = '1') then -- isRespErr + hasDmaRdErrV := '1'; + v.hasDmaReadRespErr := '1'; -- sticky Block-C flag + expectReadV := '0'; + end if; + end if; + f28Din <= f27Dout(1427 downto 346) & hasDmaRdErrV & f27Dout(344 downto 343) + & expectReadV & f27Dout(341 downto 0); + end if; + -- Stage 27 : queryPerm4DupAtomicReq (f28 -> f29) + searchAtomicReq (BSV @3003) + -- On DUP atomic w/o error, issue dupReadAtomicCache.searchAtomicReq; set + -- respPktGenInfo.expectDupAtomicCheckResp. searchAtomicReq is CONDITIONAL + -- (gate its ready only when performed); atomicEth field (f28[223:0]) is dropped. + doSearchAtomicV := (f28Dout(778 downto 775) = ST_DUP_C) and (f28Dout(357) = '1') + and (f28Dout(346) = '0') and (f28Dout(345) = '0'); -- DUP & isAtomic & !reqErr & !dmaErr + if (workerEnable and f28Valid = '1' and f29NotFull = '1' + and (not doSearchAtomicV or searchAtomicReqReady = '1')) then + f28RdEn <= '1'; f29WrEn <= '1'; + if (doSearchAtomicV) then + searchAtomicReqValid <= '1'; + -- AtomicCacheItem(317): atomicPSN bth.psn | atomicOpCode bth.opcode | atomicEth | atomicAckEth(dontCare) + searchAtomicReqData <= f28Dout(435 downto 412) & f28Dout(504 downto 500) + & f28Dout(223 downto 0) & slv(to_unsigned(0, 64)); + end if; + -- f29 = f28 minus atomicEth, with expectDupAtomicCheckResp (respPktGenInfo[66]=f28[340]) updated + f29Din <= f28Dout(1427 downto 341) & toSl(doSearchAtomicV) & f28Dout(339 downto 224); + end if; + -- Stage 28 : checkPerm4DupAtomicReq (f29 -> f30) + searchAtomicResp (BSV @3042) + -- If a dup-atomic search was issued, get its result: Valid -> patch + -- atomicAckOrig + shouldGenResp(qpNeedGenResp); Invalid -> reqStatus DISCARD. + -- searchAtomicResp.get is CONDITIONAL (gate its valid only when expected). + reqStatus28V := f29Dout(554 downto 551); + shouldGen28V := f29Dout(119); -- respPktGenInfo.shouldGenResp + atomicAck28V := f29Dout(115 downto 51); -- respPktGenInfo.atomicAckOrig (Maybe#Long) + if (workerEnable and f29Valid = '1' and f30NotFull = '1' + and (f29Dout(116) = '0' or searchAtomicRespValid = '1')) then -- expectDupAtomicCheckResp + f29RdEn <= '1'; f30WrEn <= '1'; + if (f29Dout(116) = '1') then + searchAtomicRespGetEn <= '1'; + if (searchAtomicRespData(317) = '1') then -- Valid atomicCache + atomicAck28V := '1' & searchAtomicRespData(63 downto 0); -- Valid atomicAckEth.orig + shouldGen28V := toSl(qpNeedGenResp(f29Dout(283 downto 281))); -- bth.trans + else + reqStatus28V := ST_DISCARD_C; + end if; + end if; + f30Din <= f29Dout(1203 downto 555) & reqStatus28V & f29Dout(550 downto 120) + & shouldGen28V & f29Dout(118 downto 116) & atomicAck28V & f29Dout(50 downto 0); + end if; + -- Stage 29 : genRespHeader (f30 -> f31) + sets hasErrRespGen (Block C) (BSV @3097) + -- Build the response HeaderRDMA (first/only vs middle/last), promote + -- hasDmaReadRespErr to RMT_OP/DISCARD, and latch the sticky hasErrRespGen + -- flag on any error request status. maybeHeader is appended (tuple7 -> f31). + reqStatus29V := f30Dout(554 downto 551); + shouldGen29V := f30Dout(119); + hasErrRespGenV := r.hasErrRespGen; + maybeHeaderV := (others => '0'); + if (workerEnable and f30Valid = '1' and f31NotFull = '1') then + f30RdEn <= '1'; f31WrEn <= '1'; + if (r.hasErrRespGen = '1') then + shouldGen29V := '0'; + else + if (f30Dout(121) = '1') then -- hasDmaReadRespErr + if (isNormalOrErrStatus(reqStatus29V)) then + reqStatus29V := ST_RMT_OP_C; shouldGen29V := '1'; + elsif (reqStatus29V = ST_DUP_C) then + reqStatus29V := ST_DISCARD_C; shouldGen29V := '0'; + end if; + end if; + isOnlyReadResp29V := (f30Dout(126) = '1') and (f30Dout(134) = '1'); -- isOnlyRespPkt & isReadReq + if (f30Dout(1) = '1') then -- isFirstOrOnlyRespPkt + maybeHeaderV := genFirstOrOnlyRespHeader( + f30Dout(280 downto 276), reqStatus29V, f30Dout(356 downto 325), + f30Dout(115 downto 51), getTypeQP, getPKEY, getDQPN, getMinRnrTimer, + f30Dout(49 downto 26), f30Dout(25 downto 2), isOnlyReadResp29V); + else + maybeHeaderV := genMidLastRespHeader( + reqStatus29V, f30Dout(356 downto 325), getTypeQP, getPKEY, getDQPN, + getMinRnrTimer, f30Dout(49 downto 26), f30Dout(25 downto 2), f30Dout(0) = '1'); + end if; + end if; + if (isErrReqStatus(reqStatus29V)) then + hasErrRespGenV := '1'; + end if; + v.hasErrRespGen := hasErrRespGenV; + -- f31 (tuple7): patch reqStatus, respPktGenInfo.{hasErrRespGen,shouldGenResp}, append maybeHeader + f31Din <= f30Dout(1203 downto 555) & reqStatus29V & f30Dout(550 downto 123) + & f30Dout(122 downto 121) & hasErrRespGenV & shouldGen29V + & f30Dout(118 downto 50) & f30Dout(49 downto 0) & maybeHeaderV; + end if; + -- Stage 30 : genRespPkt (f31 -> respHeaderOutQ + psnRespOutQ + workCompReqQ) (BSV @3214) + -- Emit the header + respPSN to the output FIFOs iff shouldGenResp and the + -- header is Valid (same rule for first/only and middle/last). Always enq + -- the tuple6 into workCompReqQ (drop maybeHeader). Header enq is CONDITIONAL. + doHeaderEnqV := (f31Dout(713) = '1') and (f31Dout(593) = '1'); -- shouldGenResp & maybeHeader.valid + if (workerEnable and f31Valid = '1' and f32NotFull = '1' + and (not doHeaderEnqV or (rhOutNotFull = '1' and psnOutNotFull = '1'))) then + f31RdEn <= '1'; f32WrEn <= '1'; + if (doHeaderEnqV) then + rhOutWrEn <= '1'; rhOutDin <= f31Dout(592 downto 0); -- HeaderRDMA + psnOutWrEn <= '1'; psnOutDin <= f31Dout(643 downto 620); -- respPSN + end if; + f32Din <= f31Dout(1797 downto 594); -- workCompReqQ tuple6 (drop maybeHeader) + end if; + -- Stage 31 : genWorkCompRQ (f32 -> workCompGenReqOutQ) + CountCF decrOne + -- (BSV genWorkCompRQ @3385). Runs at normal, retry AND error state. + -- f32 workCompReqQ tuple6 (=1204): pmd[1203:555] reqStatus[554:551] + -- permCheckReq[550:284] reqPktInfo[283:123] respPktGenInfo[122:50] + -- respPktHeaderInfo[49:0]. permCheckReq.wrID[550:486] totalLen[356:325] + -- isZeroDmaLen[292]; reqPktInfo bth.psn[211:188] isAtomicReq[133] + -- isReadReq[134] bth.opcode[280:276] bth.trans[283:281]; hasErrRespGen[120]; + -- respPktHeaderInfo.isFirstOrOnlyRespPkt[1]. headerData bit h -> f32[670+h]. + reqStatus31V := f32Dout(554 downto 551); + reqOp31V := f32Dout(280 downto 276); + trans31V := f32Dout(283 downto 281); + -- (a) pendingDestReadAtomicReqCnt.decrOne when this WC closes a read/atomic req + -- (BSV: reqStatus==NORMAL && !hasErrRespGen && ((isReadReq && + -- isFirstOrOnlyRespPkt) || isAtomicReq) && cnt > 0). + doDecr31V := (reqStatus31V = ST_NORMAL_C) and (f32Dout(120) = '0') + and (((f32Dout(134) = '1') and (f32Dout(1) = '1')) -- isReadReq & isFirstOrOnlyResp + or (f32Dout(133) = '1')) -- isAtomicReq + and (unsigned(ccCnt) > 0); + -- (b) extractImmDt/extractIETH (Utils.bsv:942,971) — 32b slices of headerData. + if (reqOp31V = "01011") then -- RDMA_WRITE_ONLY_WITH_IMMEDIATE + if (trans31V = "101") then immDt31V := f32Dout(925 downto 894); -- XRC: hdr[255:224] + else immDt31V := f32Dout(957 downto 926); -- hdr[287:256] (after RETH) + end if; + else + if (trans31V = "101") then immDt31V := f32Dout(1053 downto 1022); -- XRC: hdr[383:352] + else immDt31V := f32Dout(1085 downto 1054); -- hdr[415:384] (after BTH) + end if; + end if; + if (trans31V = "101") then ieth31V := f32Dout(1053 downto 1022); -- XRC: hdr[383:352] + else ieth31V := f32Dout(1085 downto 1054); -- hdr[415:384] + end if; + -- (c) Maybe#IMM / Maybe#RKEY : tag[32] & data[31:0] + if (opHasImmDt(reqOp31V)) then immM31V := '1' & immDt31V; else immM31V := (32 downto 0 => '0'); end if; + if (opHasIETH(reqOp31V)) then rkeyM31V := '1' & ieth31V; else rkeyM31V := (32 downto 0 => '0'); end if; + -- (d) WorkComp is generated only when genWorkCompStatusFromReqStatusRQ Valid. + wcStatus31V := genWcStatus(reqStatus31V); + doWcEnq31V := (wcStatus31V(5) = '1'); + if (workerEnable and f32Valid = '1' + and (not doWcEnq31V or wcOutNotFull = '1')) then + f32RdEn <= '1'; + if (doDecr31V) then + ccDecrEn <= '1'; -- pendingDestReadAtomicReqCnt.decrOne + end if; + if (doWcEnq31V) then + wcOutWrEn <= '1'; + -- WorkCompGenReqRQ(198): rrID[197:133] len[132:101] reqPSN[100:77] + -- isZeroDmaLen[76] wcStatus[75:71] reqOpCode[70:66] immDt[65:33] + -- rkey2Inv[32:0] + wcOutDin <= f32Dout(550 downto 486) -- rrID = permCheckReq.wrID + & f32Dout(356 downto 325) -- len = permCheckReq.totalLen + & f32Dout(211 downto 188) -- reqPSN = bth.psn + & f32Dout(292) -- isZeroDmaLen + & wcStatus31V(4 downto 0) -- wcStatus + & reqOp31V -- reqOpCode = bth.opcode + & immM31V -- immDt (Maybe#IMM) + & rkeyM31V; -- rkey2Inv (Maybe#RKEY) + end if; + end if; + + -------------------------------------------------------------------- + -- SUB-FSM A : pre-stage (preBuildReqInfo / preCalcReqInfo / checkEPSN) + -- Meters one packet at a time from pktMetaDataPipeIn into f01. Normal + -- mode only (isNonErr && !hasErrHappened). Field extraction is datapath + -- (Phase 1); Phase 0 wires the 3-state control + deq/enq handshake. + -------------------------------------------------------------------- + if (isNonErr = '1' and hasErrHappened = '0') then + case r.preStageState is + when RQ_PRE_BUILD_STAGE_S => + -- preBuildReqInfo (594): read pktMetaDataPipeIn.first (no deq), parse + -- BTH/RETH, classify opcode, compute isExpected/isDuplicated, latch. + if (pktMetaValid = '1') then + bthV := pktMetaData(626 downto 531); -- extractBTH + opcodeV := bthV(92 downto 88); + psnV := bthV(23 downto 0); + dlenV := pktMetaData(434 downto 403); -- extractRETH.dlen (default trans) + epochV := getEpoch; + isReadReqV := isReadReqOp(opcodeV); + -- respPktNum = isReadReq ? truncateLenByPMTU(dlen) : 1 + respPktNumV := ite(isReadReqV, truncLenPktNum(dlenV, getPMTU), + slv(to_unsigned(1, 25))); + -- RdmaReqPktInfo (161b): endPSN/isOnlyRespPkt/isAccCheckPass dontCare here + reqPktInfoV := bthV -- [160:65] + & epochV -- [64] + & respPktNumV -- [63:39] + & slv(to_unsigned(0, 24)) -- [38:15] endPSN + & toSl(isSendReqOp(opcodeV)) -- [14] + & toSl(isWriteReqOp(opcodeV)) -- [13] + & toSl(isWriteImmReqOp(opcodeV)) -- [12] + & toSl(isReadReqV) -- [11] + & toSl(isAtomicReqOp(opcodeV)) -- [10] + & toSl(isOnlyOp(opcodeV)) -- [9] + & toSl(isFirstOp(opcodeV)) -- [8] + & toSl(isMiddleOp(opcodeV)) -- [7] + & toSl(isLastOp(opcodeV)) -- [6] + & toSl(isFirstOrOnlyOp(opcodeV)) -- [5] + & toSl(isLastOrOnlyOp(opcodeV)) -- [4] + & '0' -- [3] isOnlyRespPkt + & toSl(psnV = getEPSN) -- [2] isExpected + & toSl(psnInRangeExcl(psnV, oldestValidPsn(getEPSN), getEPSN)) -- [1] isDuplicated + & '0'; -- [0] isAccCheckPass + v.preStageIsZeroPmtuResidue := toSl(pmtuResidueZero(dlenV, getPMTU)); + v.preStagePktMetaData := pktMetaData; + v.preStageReqPktInfo := reqPktInfoV; + v.preStageState := RQ_PRE_CALC_STAGE_S; + end if; + when RQ_PRE_CALC_STAGE_S => + -- preCalcReqInfo (692): totalRespPktNum, isOnlyRespPkt, access check, + -- reqStatus = pktStatus2ReqStatusRQ (+ getInvReqStatusByTransType on !acc). + reqPktInfoV := r.preStageReqPktInfo; + respPktNumV := reqPktInfoV(63 downto 39); + isReadReqV := reqPktInfoV(11) = '1'; + transV := reqPktInfoV(160 downto 158); -- bth.trans + totRespPktNumV := ite(r.preStageIsZeroPmtuResidue = '1', respPktNumV, + slv(unsigned(respPktNumV) + 1)); + isOnlyRespPktV := isLessOrEqOne(totRespPktNumV); + reqPktInfoV(3) := toSl(ite(isReadReqV, isOnlyRespPktV, true)); -- isOnlyRespPkt + reqPktInfoV(63 downto 39) := ite(isReadReqV, totRespPktNumV, slv(to_unsigned(1, 25))); + -- access check: send/write->REMOTE_WRITE(bit1); read->REMOTE_READ(bit2); atomic->REMOTE_ATOMIC(bit3) + if (reqPktInfoV(14) = '1' or reqPktInfoV(13) = '1') then + isAccPassV := getAccessFlags(1) = '1'; + elsif (reqPktInfoV(11) = '1') then + isAccPassV := getAccessFlags(2) = '1'; + else + isAccPassV := getAccessFlags(3) = '1'; + end if; + if (r.preStagePktMetaData(PMD_PKTSTATUS_C) = '0') then -- PKT_ST_VALID + reqStatusV := ST_NORMAL_C; + else -- PKT_ST_LEN_ERR + reqStatusV := invReqStatus(transV); + end if; + if (reqStatusV = ST_NORMAL_C and not isAccPassV) then + reqStatusV := invReqStatus(transV); + end if; + reqPktInfoV(0) := toSl(isAccPassV); -- isAccCheckPass + v.preStageReqStatus := reqStatusV; + v.preStageReqPktInfo := reqPktInfoV; + v.preStageState := RQ_PRE_STAGE_DONE_S; + when RQ_PRE_STAGE_DONE_S => + -- checkEPSN (821): only when retryState == NOT_RETRY. calcNextAndEndPSN, + -- ePSN check, setEPSN, deq + enq f01 = tuple4(pmd, reqStatus, reqPktInfo, curEPSN). + if (r.retryState = RQ_NOT_RETRY_S and f01NotFull = '1') then + reqStatusV := r.preStageReqStatus; + reqPktInfoV := r.preStageReqPktInfo; + bthV := reqPktInfoV(160 downto 65); + psnV := bthV(23 downto 0); + transV := bthV(95 downto 93); + epochV := reqPktInfoV(64); + isReadReqV := reqPktInfoV(11) = '1'; + respPktNumV := reqPktInfoV(63 downto 39); + isOnlyRespPktV := reqPktInfoV(3) = '1'; + curEPSNv := getEPSN; + -- calcNextAndEndPSN(psn, respPktNum, isOnlyPkt=isOnlyRespPkt, pmtu[unused]) + nextPsnV := ite(isOnlyRespPktV, slv(unsigned(psnV) + 1), + slv(resize(unsigned(psnV) + unsigned(respPktNumV), 24))); + endPsnV := ite(isOnlyRespPktV, psnV, slv(unsigned(nextPsnV) - 1)); + nextEPSNv := curEPSNv; + if (epochV = getEpoch) then + if (reqStatusV = ST_NORMAL_C and transV /= TRANS_UD_C) then + case slv'(reqPktInfoV(2) & reqPktInfoV(1)) is -- {isExpected, isDuplicated} + when "10" => + nextEPSNv := ite(isReadReqV, nextPsnV, slv(unsigned(psnV) + 1)); + reqStatusV := ST_NORMAL_C; + when "01" => + reqStatusV := ST_DUP_C; + when others => + reqStatusV := ST_SEQ_ERR_C; + end case; + end if; + else + reqStatusV := ST_DISCARD_C; + end if; + reqPktInfoV(38 downto 15) := endPsnV; -- reqPktInfo.endPSN + setEPSNValid <= '1'; + setEPSNData <= nextEPSNv; + pktMetaDeq <= '1'; + f01WrEn <= '1'; + f01Din <= r.preStagePktMetaData & reqStatusV & reqPktInfoV & curEPSNv; + v.preStageState := RQ_PRE_BUILD_STAGE_S; + end if; + when others => + v.preStageState := RQ_PRE_BUILD_STAGE_S; + end case; + + -- retryFlush (3655): DONE stage while a retry is in progress -> discard-enq f01 + if (r.preStageState = RQ_PRE_STAGE_DONE_S and r.retryState /= RQ_NOT_RETRY_S + and f01NotFull = '1') then + curEPSNv := getEPSN; + pktMetaDeq <= '1'; + f01WrEn <= '1'; + f01Din <= r.preStagePktMetaData & ST_DISCARD_C & r.preStageReqPktInfo & curEPSNv; + v.preStageState := RQ_PRE_BUILD_STAGE_S; + end if; + end if; + + -------------------------------------------------------------------- + -- SUB-FSM B : retry rules (all fire on isNonErr && !hasErrHappened). + -- retryStart reads v.retryStart* (already written by triggerRNR above) + -- for the CReg(2) same-cycle forward (OQ-FSM-RHR-02). + -------------------------------------------------------------------- + if (isNonErr = '1' and hasErrHappened = '0') then + -- retryStart (3623): consume a pending retry-start request (CReg port 1) + if (v.retryStartValid = '1' and r.retryState = RQ_NOT_RETRY_S) then + v.retryState := v.retryStartState; + v.retryStartValid := '0'; + end if; + -- retryStageRnrRetryFlush (3601) + if (r.retryState = RQ_RNR_RETRY_FLUSH_S) then + v.retryState := RQ_RNR_WAIT_S; + v.rnrWaitCnt := RNR_TIMEOUT_C(to_integer(unsigned(r.minRnrTimer))); + v.isRnrWaitCntZero := '0'; + end if; + -- retryStageRnrWait (3610) + if (r.retryState = RQ_RNR_WAIT_S) then + if (r.isRnrWaitCntZero = '1') then + v.retryState := RQ_RNR_WAIT_DONE_S; + else + v.rnrWaitCnt := slv(unsigned(r.rnrWaitCnt) - 1); + if (unsigned(r.rnrWaitCnt) = 1) then + v.isRnrWaitCntZero := '1'; + end if; + end if; + end if; + -- retryDone (3632): needs preStage in CALC and WAIT_DONE/SEQ_RETRY_FLUSH + if (r.preStageState = RQ_PRE_CALC_STAGE_S and + (r.retryState = RQ_RNR_WAIT_DONE_S or r.retryState = RQ_SEQ_RETRY_FLUSH_S)) then + -- retryFlushDone = reqPktInfo.isExpected && reqPktInfo.epoch == getEpoch + if (r.preStageReqPktInfo(2) = '1' and r.preStageReqPktInfo(64) = getEpoch) then + v.retryState := RQ_NOT_RETRY_S; + end if; + end if; + end if; + + -------------------------------------------------------------------- + -- SUB-FSM C : error-flush rules (inErrorState). Exactly one of the + -- normal pre-stage / errFlush consumers touches pktMetaDataPipeIn per + -- cycle — inErrorState is mutually exclusive with the normal guard. + -------------------------------------------------------------------- + if (inErrorState = '1' and f01NotFull = '1') then + if (pktMetaValid = '0') then + -- errFlushRecvReq (synthesised flush RR, no deq) + f01WrEn <= '1'; + -- TODO(phase-err): f01Din <= flush-RR tuple (reqStatus=ERR_FLUSH_RR) + else + -- errFlushIncomingReq (deq + discard) + pktMetaDeq <= '1'; + f01WrEn <= '1'; + -- TODO(phase-err): f01Din <= tuple4(pktMetaData, DISCARD, ...) + end if; + end if; + + -------------------------------------------------------------------- + -- resetAndClear (isReset): synchronous clear of control state. FIFOs are + -- cleared via fifoClr; CountCF via its own write/clear. (BSV line 530) + -------------------------------------------------------------------- + if (isReset = '1') then + v.retryState := RQ_NOT_RETRY_S; + v.retryStartValid := '0'; + v.preStageState := RQ_PRE_BUILD_STAGE_S; + v.hasReqStatusErr := '0'; + v.hasDmaReadRespErr := '0'; + v.hasErrRespGen := '0'; + v.isFirstOrOnlyRespPkt := '1'; + v.coalesceWorkReqCnt := COALESCE_INIT_C; + v.isCoalesceWorkReqCntZero := '0'; + -- pendingDestReadAtomicReqCnt <= 0 : drive CountCF write port + ccWriteEn <= '1'; + ccWriteVal <= (others => '0'); + end if; + + -- Synchronous reset (SURF rst port) dominates + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/RespHandleSq.vhd b/ethernet/RoCEv2/rtl/RespHandleSq.vhd new file mode 100644 index 0000000000..de884f63e2 --- /dev/null +++ b/ethernet/RoCEv2/rtl/RespHandleSq.vhd @@ -0,0 +1,1621 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- The SQ response-handling datapath: an 11-stage linear pipeline of SURF FIFOs +-- (incomingRespQ -> pendingRespQ -> ... -> pendingWorkCompQ -> workCompGenReqOutQ) +-- wrapped around (a) a 3-state pre-stage control FSM (preStageState) that builds +-- incoming-response tokens from the pendingWorkReq + pktMetaData inputs, and +-- (b) a deferred error/retry/timeout sub-FSM expressed as mode flags +-- (recvErrResp/recvRetryResp/errOccurred/retryFlush + 2 CRegs). +-- +-- ⚑S3 (OQ-PART-02) RESOLVED: KEEP FUSED — the err/retry control is threaded +-- through scalar/CReg registers written on both sides of the proposed cut, so a +-- split cannot preserve the same-cycle CReg ordering. ONE entity, one RegType; +-- the sub-FSM block is delimited in RegType below. +-- +-- Mode signals (combinational from r): +-- inNormalState = (not retryFlush) and (not errOccurred) and (not recvErrResp) +-- inRetryState = retryFlush and (not errOccurred) and (not recvErrResp) +-- inErrState = errOccurred or isERR +-- inErrStateAlt = (isRTS and (recvErrResp or errOccurred)) or isERR +-- +-- Cross-stage server handshakes (OQ-S3-RESP-01, in-order assumed): retryHandler +-- srvPort request issued in handleRespByType, response consumed in checkRetryErr; +-- permCheckSrv request in queryPerm4NormalReadAtomicResp, response in +-- checkPerm4NormalReadAtomicResp. Modelled as valid/ready (req) + valid/getEn +-- (resp) ports; the consuming stage's firing is gated on resp-valid only on the +-- branch that actually consumes the response (conditional implicit condition). +-- +-- CReg(2) ordering (OQ-S3-RESP-02): hasInternalErr port0 written by issueDmaReq, +-- port1 read+cleared by canonicalize SAME cycle; hasTimeOutErr port0 written by +-- checkTimeOutErr / read+cleared by errFlushWorkReq, port1 read by canonicalize. +-- In comb: all port0 writers run BEFORE canonicalize (port1 read of v.*). +-- +-- FIFO clear: BSV FIFOF.clear under resetAndClear -> fifoClr = rst or isReset +-- asserted to every Fifo rst (level-safe sync clear; OQ-FSM-01 carry-forward). +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd), all +-- surf.Fifo FWFT/sync/block, DATA_WIDTH_G = tuple width, ADDR_WIDTH_G=4: +-- U_IncomingRespQ 1470 U_PendingRespQ 1473 U_PendingPermQueryQ 1469 +-- U_PendingRetryCheckQ 1470 U_PendingPermCheckQ 1476 U_PendingAddrCalcQ 1475 +-- U_PendingLenCalcQ 1539 U_PendingSpaceCalcQ 1605 U_PendingLenCheckQ 1573 +-- U_PendingDmaReqQ 1539 U_PendingWorkCompQ 768 U_WorkCompGenReqOutQ 633 +-- +-- Type widths (BSV deriving(Bits), first-field-at-MSB; traced from +-- DataTypes.bsv/Headers.bsv): PendingWorkReq=679 (wr[678:78]; startPSN.val +-- [76:53]; endPSN.val [51:28]; wr.id [678:615]; wr.opcode [614:611]; wr.flags +-- [610:606] (signaled=bit1=[607]); wr.len [509:478]; wr.laddr [477:414]; +-- wr.lkey [413:382]). RdmaPktMetaData=649 (pktPayloadLen [648:636]; pktFragNum +-- [635:628]; isZeroPayloadLen [627]; pktHeader [626:34]; pdHandler [33:2]; +-- pktValid [1]; pktStatus [0]; within header headerData=[626:115], extractBTH= +-- [626:531], extractAETH=[530:499], extractAtomicAckEth=[498:435]; bth.opcode= +-- [623:619], bth.psn=[554:531]; aeth.code=[529:528], aeth.value=[527:523]). +-- RespPktInfo=135 (bth[134:39]|aeth[38:7]|isFirstOrOnly[6]|isLastOrOnly[5]| +-- isReadResp[4]|isAtomicResp[3]|hasLocalErr[2]|shouldDiscard[1]|genWorkComp[0]). +-- WorkCompGenReqSQ=633 (wr[632:32]|wcWaitDmaResp[31]|wcReqType[30:29]| +-- triggerPSN[28:5]|wcStatus[4:0]). RespLenCheckResult=98 (enoughDmaSpace[97]| +-- isLastPayloadLenZero[96]|nextAddr[95:32]|remLen[31:0]). Maybe#WorkCompStatus=6 +-- (tag[5]|status[4:0]). PermCheckReq=267, RetryReq=97, PayloadConReq=203. +-- +-- Excluded/Deferred (see OPEN_QUESTIONS.md OQ-RHSQ-04..07): BSV immAsserts are +-- simulation-only and are NOT reproduced here; mkRegU latches zero-initialised; +-- permCheckReq.accFlags local-write encoding confirmed against PermCheckSrv; +-- the two server in-order/bounded-latency assumptions (OQ-S3-RESP-01). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity RespHandleSq is + generic ( + TPD_G : time := 1 ns; + -- false = no RDMA READ/atomic support: read/atomic-response classifiers + -- are forced false so all read-response landing logic constant-folds + -- (software contract: never post READ/atomic work requests). + EN_READ_G : boolean := true); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- contextSQ.statusSQ.comm status methods (combinational inputs) + isReset : in sl; -- isReset -> resetAndClear + isRTS : in sl; -- isRTS + isERR : in sl; -- isERR + isStableRTS : in sl; -- isStableRTS + getPMTU : in slv(2 downto 0); -- PMTU enum (256="001"..4096="101") + getSQPN : in slv(23 downto 0); -- getSQPN + getNPSN : in slv(23 downto 0); -- getNPSN + -- pendingWorkReqPipeIn : PipeOut#(PendingWorkReq) (679b) + pendingWrValid : in sl; -- notEmpty + pendingWrData : in slv(678 downto 0); -- first + pendingWrDeq : out sl; -- deq + -- pktMetaDataPipeIn : PipeOut#(RdmaPktMetaData) (649b) + pktMetaValid : in sl; -- notEmpty + pktMetaData : in slv(648 downto 0); -- first + pktMetaDeq : out sl; -- deq + -- payloadConReqPort : Put#(PayloadConReq) (203b) + payloadConReqValid : out sl; -- put valid + payloadConReqData : out slv(202 downto 0); -- put data (PayloadConReq) + payloadConReqReady : in sl; -- put ready (consumer not full) + -- retryHandler.resetRetryCntAndTimeOutBySQ : Action(ResetRetryCntAndTimeOutReq) + retryResetValid : out sl; + retryResetData : out sl; -- 1b enum + retryResetReady : in sl; + -- retryHandler.srvPort.request : Put#(RetryReq) (97b) + retryReqValid : out sl; + retryReqData : out slv(96 downto 0); + retryReqReady : in sl; + -- retryHandler.srvPort.response : Get#(RetryResp) (1b) + retryRespValid : in sl; + retryRespData : in sl; -- RETRY_LIMIT_EXC='1' + retryRespGetEn : out sl; + -- retryHandler.notifyTimeOut2SQ : Get#(TimeOutNotification) (1b) + timeOutValid : in sl; + timeOutData : in sl; -- TIMEOUT_ERR='1' + timeOutGetEn : out sl; + -- retryHandler.isRetrying : Bool method + isRetrying : in sl; + -- permCheckSrv.request : Put#(PermCheckReq) (267b) + permReqValid : out sl; + permReqData : out slv(266 downto 0); + permReqReady : in sl; + -- permCheckSrv.response : Get#(Bool) (1b) + permRespValid : in sl; + permRespData : in sl; -- mrCheckResult + permRespGetEn : out sl; + -- workCompGenReqPipeOut : PipeOut#(WorkCompGenReqSQ) (633b) + wcGenReqValid : out sl; -- notEmpty + wcGenReqData : out slv(632 downto 0); -- first + wcGenReqRdEn : in sl); -- deq (downstream drives) +end entity RespHandleSq; + +architecture rtl of RespHandleSq is + + --------------------------------------------------------------------------- + -- Pre-stage control FSM state + --------------------------------------------------------------------------- + type StateType is (SQ_PRE_BUILD_STAGE_S, SQ_PRE_PROC_STAGE_S, SQ_PRE_STAGE_DONE_S); + + --------------------------------------------------------------------------- + -- RegType : ONE record (fused). Sub-FSM block delimited below. + --------------------------------------------------------------------------- + type RegType is record + -- (a) pre-stage control FSM + preStageState : StateType; + -- (b) pre-stage latch registers (mkRegU — no reset; zero-init for determinism) + preStageRespAndWorkReqRelation : slv(4 downto 0); + preStagePktMetaData : slv(648 downto 0); + preStageReqPktInfo : slv(134 downto 0); + preStageRespType : slv(1 downto 0); + preStageDeqPktMetaData : sl; + preStageDeqPendingWorkReq : sl; + preStageWorkReqAckType : slv(3 downto 0); + preStageWorkCompReqType : slv(1 downto 0); + retryResetReq : sl; -- ResetRetryCntAndTimeOutReq (1b) + -- (c) pipeline accumulators + preRdmaOpCode : slv(4 downto 0); -- reset ACKNOWLEDGE + remainingReadRespLen : slv(31 downto 0); -- mkRegU + nextReadRespWriteAddr : slv(63 downto 0); -- mkRegU + readRespPktNum : slv(24 downto 0); -- mkRegU + -- (d) ⚑ DEFERRED-SUB-FSM block — error/retry/timeout mode flags + recvErrResp : sl; + recvRetryResp : sl; + errOccurred : sl; + retryFlush : sl; + hasInternalErr : sl; -- mkCReg(2) + hasTimeOutErr : sl; -- mkCReg(2) + end record RegType; + + constant ACKNOWLEDGE_C : slv(4 downto 0) := "10001"; -- RdmaOpCode ACKNOWLEDGE = 0x11 + + constant REG_INIT_C : RegType := ( + preStageState => SQ_PRE_BUILD_STAGE_S, + preStageRespAndWorkReqRelation => (others => '0'), + preStagePktMetaData => (others => '0'), + preStageReqPktInfo => (others => '0'), + preStageRespType => (others => '0'), + preStageDeqPktMetaData => '0', + preStageDeqPendingWorkReq => '0', + preStageWorkReqAckType => (others => '0'), + preStageWorkCompReqType => (others => '0'), + retryResetReq => '0', + preRdmaOpCode => ACKNOWLEDGE_C, + remainingReadRespLen => (others => '0'), + nextReadRespWriteAddr => (others => '0'), + readRespPktNum => (others => '0'), + recvErrResp => '0', + recvRetryResp => '0', + errOccurred => '0', + retryFlush => '0', + hasInternalErr => '0', + hasTimeOutErr => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + --------------------------------------------------------------------------- + -- Enum encodings + --------------------------------------------------------------------------- + -- RdmaRespType (2b) + constant RESP_NORMAL_C : slv(1 downto 0) := "00"; + constant RESP_RETRY_C : slv(1 downto 0) := "01"; + constant RESP_ERROR_C : slv(1 downto 0) := "10"; + constant RESP_UNK_C : slv(1 downto 0) := "11"; + -- WorkReqAckType (4b) + constant WRA_EWN_C : slv(3 downto 0) := x"0"; -- EXPLICIT_WHOLE_NORMAL + constant WRA_EWR_C : slv(3 downto 0) := x"1"; -- EXPLICIT_WHOLE_RETRY + constant WRA_EWE_C : slv(3 downto 0) := x"2"; -- EXPLICIT_WHOLE_ERROR + constant WRA_EPN_C : slv(3 downto 0) := x"3"; -- EXPLICIT_PARTIAL_NORMAL + constant WRA_EPR_C : slv(3 downto 0) := x"4"; -- EXPLICIT_PARTIAL_RETRY + constant WRA_EPE_C : slv(3 downto 0) := x"5"; -- EXPLICIT_PARTIAL_ERROR + constant WRA_CN_C : slv(3 downto 0) := x"6"; -- COALESCE_NORMAL + constant WRA_CR_C : slv(3 downto 0) := x"7"; -- COALESCE_RETRY + constant WRA_DUP_C : slv(3 downto 0) := x"8"; -- DUPLICATE + constant WRA_GHOST_C : slv(3 downto 0) := x"9"; -- GHOST + constant WRA_ILL_C : slv(3 downto 0) := x"A"; -- ILLEGAL + constant WRA_DISC_C : slv(3 downto 0) := x"B"; -- DISCARD + constant WRA_FLUSH_C : slv(3 downto 0) := x"C"; -- ERR_FLUSH_WR + constant WRA_TMOUT_C : slv(3 downto 0) := x"D"; -- TIMOUT_ERR + constant WRA_UNK_C : slv(3 downto 0) := x"E"; -- UNKNOWN + -- RespActionSQ (4b) + constant ACT_BAD_C : slv(3 downto 0) := x"0"; + constant ACT_COALESCE_C : slv(3 downto 0) := x"1"; + constant ACT_ERROR_C : slv(3 downto 0) := x"2"; + constant ACT_EXP_NORM_C : slv(3 downto 0) := x"3"; + constant ACT_DISCARD_C : slv(3 downto 0) := x"4"; + constant ACT_DUP_C : slv(3 downto 0) := x"5"; + constant ACT_ILLEGAL_C : slv(3 downto 0) := x"6"; + constant ACT_FLUSH_WR_C : slv(3 downto 0) := x"7"; + constant ACT_TIMEOUT_C : slv(3 downto 0) := x"8"; + constant ACT_EXP_RETRY_C : slv(3 downto 0) := x"9"; + constant ACT_IMP_RETRY_C : slv(3 downto 0) := x"A"; + constant ACT_LOC_ACC_C : slv(3 downto 0) := x"B"; + constant ACT_LOC_LEN_C : slv(3 downto 0) := x"C"; + constant ACT_UNK_C : slv(3 downto 0) := x"D"; + -- WorkCompReqType (2b) + constant WC_FULL_C : slv(1 downto 0) := "00"; + constant WC_PART_C : slv(1 downto 0) := "01"; + constant WC_NO_C : slv(1 downto 0) := "10"; + constant WC_UNK_C : slv(1 downto 0) := "11"; + -- ResetRetryCntAndTimeOutReq (1b) + constant RESET_TIMEOUT_C : sl := '0'; + constant RESET_CNT_TMO_C : sl := '1'; + -- WorkCompStatus (5b) + constant WCS_SUCCESS_C : slv(4 downto 0) := "00000"; -- 0 + constant WCS_LOC_LEN_C : slv(4 downto 0) := "00001"; -- 1 + constant WCS_WR_FLUSH_C : slv(4 downto 0) := "00101"; -- 5 + constant WCS_BAD_RESP_C : slv(4 downto 0) := "00111"; -- 7 + constant WCS_LOC_ACC_C : slv(4 downto 0) := "01000"; -- 8 + constant WCS_REM_INV_REQ_C : slv(4 downto 0) := "01001"; -- 9 + constant WCS_REM_ACC_C : slv(4 downto 0) := "01010"; -- 10 + constant WCS_REM_OP_C : slv(4 downto 0) := "01011"; -- 11 + constant WCS_RETRY_EXC_C : slv(4 downto 0) := "01100"; -- 12 + constant WCS_REM_INV_RD_C : slv(4 downto 0) := "01111"; -- 15 + constant WCS_RESP_TMOUT_C : slv(4 downto 0) := "10100"; -- 20 + -- RdmaOpCode (5b) — relevant codes + constant OP_WRITE_ONLY_C : slv(4 downto 0) := "01010"; -- 10 (unused here) + -- AethCode (2b) + constant AETH_ACK_C : slv(1 downto 0) := "00"; + constant AETH_RNR_C : slv(1 downto 0) := "01"; + constant AETH_NAK_C : slv(1 downto 0) := "11"; + -- AETH NAK values (5b) + constant NAK_SEQ_C : slv(4 downto 0) := "00000"; -- 0 + constant NAK_INV_REQ_C : slv(4 downto 0) := "00001"; -- 1 + constant NAK_RMT_ACC_C : slv(4 downto 0) := "00010"; -- 2 + constant NAK_RMT_OP_C : slv(4 downto 0) := "00011"; -- 3 + constant NAK_INV_RD_C : slv(4 downto 0) := "00100"; -- 4 + -- DmaReqSrcType (4b) + constant DMA_SQ_WR_C : slv(3 downto 0) := x"6"; + constant DMA_SQ_ATOM_C : slv(3 downto 0) := x"7"; + constant DMA_SQ_DISC_C : slv(3 downto 0) := x"8"; + -- PermCheck access flags (FlagsType#(MemAccessTypeFlag), 8b): IBV_ACCESS_LOCAL_WRITE + constant ACC_LOCAL_WRITE_C : slv(7 downto 0) := x"01"; -- see OQ-RHSQ-07 + -- zero-fill constants for dontCare / union padding + constant ZERO_PWR_C : slv(678 downto 0) := (others => '0'); + constant ZERO64_C : slv(63 downto 0) := (others => '0'); + constant ZERO32_C : slv(31 downto 0) := (others => '0'); + + --------------------------------------------------------------------------- + -- FIFO interface signals (one bundle per surf.Fifo) + --------------------------------------------------------------------------- + signal incWrEn, incRdEn, incValid, incNotFull : sl; + signal incDin, incDout : slv(1469 downto 0); + signal prsWrEn, prsRdEn, prsValid, prsNotFull : sl; + signal prsDin, prsDout : slv(1472 downto 0); + signal pqWrEn, pqRdEn, pqValid, pqNotFull : sl; + signal pqDin, pqDout : slv(1468 downto 0); + signal prcWrEn, prcRdEn, prcValid, prcNotFull : sl; + signal prcDin, prcDout : slv(1469 downto 0); + signal ppcWrEn, ppcRdEn, ppcValid, ppcNotFull : sl; + signal ppcDin, ppcDout : slv(1475 downto 0); + signal pacWrEn, pacRdEn, pacValid, pacNotFull : sl; + signal pacDin, pacDout : slv(1474 downto 0); + signal plcWrEn, plcRdEn, plcValid, plcNotFull : sl; + signal plcDin, plcDout : slv(1538 downto 0); + signal pscWrEn, pscRdEn, pscValid, pscNotFull : sl; + signal pscDin, pscDout : slv(1604 downto 0); + signal plkWrEn, plkRdEn, plkValid, plkNotFull : sl; + signal plkDin, plkDout : slv(1572 downto 0); + signal pdrWrEn, pdrRdEn, pdrValid, pdrNotFull : sl; + signal pdrDin, pdrDout : slv(1538 downto 0); + signal pwcWrEn, pwcRdEn, pwcValid, pwcNotFull : sl; + signal pwcDin, pwcDout : slv(767 downto 0); + signal outWrEn, outValid, outNotFull : sl; + signal outDin, outDout : slv(632 downto 0); + + signal fifoClr : sl; + + --------------------------------------------------------------------------- + -- Helper functions (BSV Utils.bsv equivalents) + --------------------------------------------------------------------------- + -- RdmaOpCode classifiers (5b opcode) + function isFirstOp(op : slv(4 downto 0)) return boolean is + begin + return op = "00000" or op = "00110" or op = "01101"; -- SEND_FIRST/WRITE_FIRST/READ_RESP_FIRST + end function; + function isMidOp(op : slv(4 downto 0)) return boolean is + begin + return op = "00001" or op = "00111" or op = "01110"; -- SEND_MIDDLE/WRITE_MIDDLE/READ_RESP_MIDDLE + end function; + function isLastOp(op : slv(4 downto 0)) return boolean is + begin + return op = "00010" or op = "00011" or op = "10110" or -- SEND_LAST/_IMM/_INV + op = "01000" or op = "01001" or -- WRITE_LAST/_IMM + op = "01111"; -- READ_RESP_LAST + end function; + function isOnlyOp(op : slv(4 downto 0)) return boolean is + begin + return op = "00100" or op = "00101" or op = "10111" or -- SEND_ONLY/_IMM/_INV + op = "01010" or op = "01011" or -- WRITE_ONLY/_IMM + op = "01100" or op = "10011" or op = "10100" or -- READ_REQUEST/COMPARE_SWAP/FETCH_ADD + op = "10000" or op = "10001" or op = "10010"; -- READ_RESP_ONLY/ACK/ATOMIC_ACK + end function; + -- EN_READ_G=false forces both classifiers false: rpi isReadResp/isAtomicResp + -- bits become constant '0' and synthesis prunes the read-response datapath + -- (calcReadRespAddr/calcReadRespLen/checkReadRespLen, DMA-write issue, perm + -- queries); a real read response then falls into the RESP_UNK_C branch. + function isReadRespOp(op : slv(4 downto 0)) return boolean is + begin + return EN_READ_G and + (op = "01101" or op = "01110" or op = "01111" or op = "10000"); + end function; + function isAtomicRespOp(op : slv(4 downto 0)) return boolean is + begin + return EN_READ_G and (op = "10010"); -- ATOMIC_ACKNOWLEDGE + end function; + function isFirstOrOnlyOp(op : slv(4 downto 0)) return boolean is + begin + return isFirstOp(op) or isOnlyOp(op); + end function; + function isLastOrOnlyOp(op : slv(4 downto 0)) return boolean is + begin + return isLastOp(op) or isOnlyOp(op); + end function; + -- WorkReqOpCode classifiers (4b) + function isReadOrAtomicWR(op : slv(3 downto 0)) return boolean is + begin + return op = x"4" or op = x"5" or op = x"6"; -- RDMA_READ/CMP_SWP/FETCH_ADD + end function; + function rdmaRespMatchWR(rop : slv(4 downto 0); wop : slv(3 downto 0)) return boolean is + begin + if rop = "01101" or rop = "01110" or rop = "01111" or rop = "10000" then -- READ_RESP_* + return wop = x"4"; -- RDMA_READ + elsif rop = "10010" then -- ATOMIC_ACK + return wop = x"5" or wop = x"6"; + elsif rop = "10001" then -- ACKNOWLEDGE + return true; + else + return false; + end if; + end function; + function checkRespOpSeq(preOp, curOp : slv(4 downto 0)) return boolean is + begin + if preOp = "01101" or preOp = "01110" then -- READ_RESP_FIRST/MIDDLE + return curOp = "01110" or curOp = "01111"; -- MIDDLE/LAST + elsif preOp = "01111" or preOp = "10000" or preOp = "10001" or preOp = "10010" then + return true; -- READ_RESP_LAST/ONLY/ACK/ATOMIC_ACK + else + return false; + end if; + end function; + -- calcPmtuLen -> PktLen(13) + function calcPmtuLen(pmtu : slv(2 downto 0)) return unsigned is + variable v : unsigned(12 downto 0); + begin + case pmtu is + when "001" => v := to_unsigned(256, 13); + when "010" => v := to_unsigned(512, 13); + when "011" => v := to_unsigned(1024, 13); + when "100" => v := to_unsigned(2048, 13); + when others => v := to_unsigned(4096, 13); -- IBV_MTU_4096 (and default) + end case; + return v; + end function; + -- pmtu log2 (shift split point): 256->8 .. 4096->12 + function pmtuLog(pmtu : slv(2 downto 0)) return integer is + begin + case pmtu is + when "001" => return 8; + when "010" => return 9; + when "011" => return 10; + when "100" => return 11; + when others => return 12; + end case; + end function; + -- addrAddPsnMultiplyPMTU = addr + (psn << log2(PMTU)) (high-part add; BSV form) + function addrAddPsn(addr : slv(63 downto 0); psn : slv(23 downto 0); pmtu : slv(2 downto 0)) return slv is + begin + return slv(unsigned(addr) + shift_left(resize(unsigned(psn), 64), pmtuLog(pmtu))); + end function; + -- lenSubtractPsnMultiplyPMTU = len - (psn << log2(PMTU)) + function lenSubPsn(len : slv(31 downto 0); psn : slv(23 downto 0); pmtu : slv(2 downto 0)) return slv is + begin + return slv(unsigned(len) - shift_left(resize(unsigned(psn), 32), pmtuLog(pmtu))); + end function; + -- lenSubtractPktLen: { len[31:k+1], len[k:0]-pktLen } (low-part subtract, no borrow up) + function lenSubPktLen(len : slv(31 downto 0); pktLen : slv(12 downto 0); pmtu : slv(2 downto 0)) return slv is + begin + case pmtu is + when "001" => return len(31 downto 9) & slv(unsigned(len(8 downto 0)) - resize(unsigned(pktLen), 9)); + when "010" => return len(31 downto 10) & slv(unsigned(len(9 downto 0)) - resize(unsigned(pktLen), 10)); + when "011" => return len(31 downto 11) & slv(unsigned(len(10 downto 0)) - resize(unsigned(pktLen), 11)); + when "100" => return len(31 downto 12) & slv(unsigned(len(11 downto 0)) - resize(unsigned(pktLen), 12)); + when others => return len(31 downto 13) & slv(unsigned(len(12 downto 0)) - unsigned(pktLen)); + end case; + end function; + -- lenGtEqPktLen: (len >= 2^(k+1)) or (len[k:0] >= pktLen[k:0]) + function lenGtEqPktLen(len : slv(31 downto 0); pktLen : slv(12 downto 0); pmtu : slv(2 downto 0)) return boolean is + begin + case pmtu is + when "001" => return (unsigned(len(31 downto 9)) /= 0) or (unsigned(len(8 downto 0)) >= unsigned(pktLen(8 downto 0))); + when "010" => return (unsigned(len(31 downto 10)) /= 0) or (unsigned(len(9 downto 0)) >= unsigned(pktLen(9 downto 0))); + when "011" => return (unsigned(len(31 downto 11)) /= 0) or (unsigned(len(10 downto 0)) >= unsigned(pktLen(10 downto 0))); + when "100" => return (unsigned(len(31 downto 12)) /= 0) or (unsigned(len(11 downto 0)) >= unsigned(pktLen(11 downto 0))); + when others => return (unsigned(len(31 downto 13)) /= 0) or (unsigned(len(12 downto 0)) >= unsigned(pktLen)); + end case; + end function; + -- lenGtEqPMTU: len >= 2^log2(PMTU) + function lenGtEqPMTU(len : slv(31 downto 0); pmtu : slv(2 downto 0)) return boolean is + begin + return unsigned(len) >= shift_left(to_unsigned(1, 40), pmtuLog(pmtu)); + end function; + -- getRetryReasonFromAETH / IMPLICIT -> RetryReason(3b) + function getRetryReason(respAct, aCode, aVal : slv) return slv is + begin + if respAct = "1010" then -- SQ_ACT_IMPLICIT_RETRY + return "011"; -- RETRY_REASON_IMPLICIT + elsif aCode = "01" then -- AETH_CODE_RNR + return "001"; -- RETRY_REASON_RNR + elsif (aCode = "11") and (aVal = "00000") then -- NAK SEQ_ERR + return "010"; -- RETRY_REASON_SEQ_ERR + else + return "000"; -- RETRY_REASON_NOT_RETRY + end if; + end function; + -- Maybe#(RnrTimer) (tag|5b): Valid aeth.value iff reason==RNR (explicit retry, RNR code) + function getRnrTimer(respAct, aCode, aVal : slv) return slv is + begin + if (respAct = "1001") and (aCode = "01") then -- EXPLICIT_RETRY & RNR + return '1' & aVal; + else + return "000000"; + end if; + end function; + -- genErrWorkCompStatusFromAethSQ -> Maybe#(WorkCompStatus) (tag|5b) + function genErrWcStatusFromAeth(aCode, aVal : slv) return slv is + begin + if aCode = "11" then -- AETH_CODE_NAK + case aVal is + when "00001" => return '1' & "01001"; -- INV_REQ -> REM_INV_REQ_ERR(9) + when "00010" => return '1' & "01010"; -- RMT_ACC -> REM_ACCESS_ERR(10) + when "00011" => return '1' & "01011"; -- RMT_OP -> REM_OP_ERR(11) + when "00100" => return '1' & "01111"; -- INV_RD -> REM_INV_RD_REQ_ERR(15) + when others => return "000000"; + end case; + else + return "000000"; + end if; + end function; + -- psnInRangeExclusive(psn, start, end) — 24b PSN wrap-aware + function psnInRange(psn, ps, pe : slv(23 downto 0)) return boolean is + variable gtStart, ltEnd : boolean; + begin + gtStart := unsigned(ps) < unsigned(psn); + ltEnd := unsigned(psn) < unsigned(pe); + if ps(23) = pe(23) then + return gtStart and ltEnd; + else + return (gtStart and (ps(23) = psn(23))) or (ltEnd and (psn(23) = pe(23))); + end if; + end function; + +begin + + fifoClr <= rst or isReset; + + -- workCompGenReqPipeOut read face (downstream drives rd_en) + wcGenReqValid <= outValid; + wcGenReqData <= outDout; + + --------------------------------------------------------------------------- + -- 12 SURF Fifo instances (all FWFT/sync/block; cleared by fifoClr) + --------------------------------------------------------------------------- + U_IncomingRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1470, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => incWrEn, + din => incDin, + not_full => incNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => incRdEn, + dout => incDout, + valid => incValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1473, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => prsWrEn, + din => prsDin, + not_full => prsNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => prsRdEn, + dout => prsDout, + valid => prsValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingPermQueryQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1469, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => pqWrEn, + din => pqDin, + not_full => pqNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pqRdEn, + dout => pqDout, + valid => pqValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingRetryCheckQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1470, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => prcWrEn, + din => prcDin, + not_full => prcNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => prcRdEn, + dout => prcDout, + valid => prcValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingPermCheckQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1476, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => ppcWrEn, + din => ppcDin, + not_full => ppcNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => ppcRdEn, + dout => ppcDout, + valid => ppcValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingAddrCalcQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1475, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => pacWrEn, + din => pacDin, + not_full => pacNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pacRdEn, + dout => pacDout, + valid => pacValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingLenCalcQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1539, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => plcWrEn, + din => plcDin, + not_full => plcNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => plcRdEn, + dout => plcDout, + valid => plcValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingSpaceCalcQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1605, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => pscWrEn, + din => pscDin, + not_full => pscNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pscRdEn, + dout => pscDout, + valid => pscValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingLenCheckQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1573, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => plkWrEn, + din => plkDin, + not_full => plkNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => plkRdEn, + dout => plkDout, + valid => plkValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingDmaReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1539, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => pdrWrEn, + din => pdrDin, + not_full => pdrNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pdrRdEn, + dout => pdrDout, + valid => pdrValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_PendingWorkCompQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 768, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => pwcWrEn, + din => pwcDin, + not_full => pwcNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pwcRdEn, + dout => pwcDout, + valid => pwcValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + U_WorkCompGenReqOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 633, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => outWrEn, + din => outDin, + not_full => outNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => wcGenReqRdEn, + dout => outDout, + valid => outValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, isReset, isRTS, isERR, isStableRTS, getPMTU, + getSQPN, getNPSN, pendingWrValid, pendingWrData, + pktMetaValid, pktMetaData, payloadConReqReady, + retryResetReady, retryReqReady, retryRespValid, retryRespData, + timeOutValid, timeOutData, isRetrying, permReqReady, + permRespValid, permRespData, + incValid, incDout, incNotFull, prsValid, prsDout, prsNotFull, + pqValid, pqDout, pqNotFull, prcValid, prcDout, prcNotFull, + ppcValid, ppcDout, ppcNotFull, pacValid, pacDout, pacNotFull, + plcValid, plcDout, plcNotFull, pscValid, pscDout, pscNotFull, + plkValid, plkDout, plkNotFull, pdrValid, pdrDout, pdrNotFull, + pwcValid, pwcDout, pwcNotFull, outNotFull) is + variable v : RegType; + -- mode signals (from r) + variable inNormalState, inRetryState, inErrState, inErrStateAlt : boolean; + -- generic working vars + variable pwr : slv(678 downto 0); + variable pmd : slv(648 downto 0); + variable rpi : slv(134 downto 0); + variable opc : slv(4 downto 0); + variable wop : slv(3 downto 0); + variable aCode : slv(1 downto 0); + variable aVal : slv(4 downto 0); + variable bpsn : slv(23 downto 0); + variable respAct : slv(3 downto 0); + variable wcReq : slv(1 downto 0); + variable wcStat : slv(5 downto 0); -- Maybe#WorkCompStatus (tag|5) + variable mWcStat : slv(5 downto 0); + variable rlcr : slv(97 downto 0); + variable nAddr : slv(63 downto 0); + variable remLen : slv(31 downto 0); + variable preRem : slv(31 downto 0); + variable expectPerm : sl; + variable wcWaitDma : sl; + variable doPut : sl; + variable enqOut : sl; + variable fire : boolean; + variable wcGenReq : slv(632 downto 0); + variable rdmaRespType : slv(1 downto 0); + variable rel : slv(4 downto 0); + variable wrAck : slv(3 downto 0); + variable deqPmd, deqPwr : sl; + variable needPerm : boolean; + variable pcInfo : slv(194 downto 0); -- PayloadConInfo + begin + v := r; + + -- default outputs + incWrEn <= '0'; incRdEn <= '0'; incDin <= (others => '0'); + prsWrEn <= '0'; prsRdEn <= '0'; prsDin <= (others => '0'); + pqWrEn <= '0'; pqRdEn <= '0'; pqDin <= (others => '0'); + prcWrEn <= '0'; prcRdEn <= '0'; prcDin <= (others => '0'); + ppcWrEn <= '0'; ppcRdEn <= '0'; ppcDin <= (others => '0'); + pacWrEn <= '0'; pacRdEn <= '0'; pacDin <= (others => '0'); + plcWrEn <= '0'; plcRdEn <= '0'; plcDin <= (others => '0'); + pscWrEn <= '0'; pscRdEn <= '0'; pscDin <= (others => '0'); + plkWrEn <= '0'; plkRdEn <= '0'; plkDin <= (others => '0'); + pdrWrEn <= '0'; pdrRdEn <= '0'; pdrDin <= (others => '0'); + pwcWrEn <= '0'; pwcRdEn <= '0'; pwcDin <= (others => '0'); + outWrEn <= '0'; outDin <= (others => '0'); + pendingWrDeq <= '0'; pktMetaDeq <= '0'; + payloadConReqValid <= '0'; payloadConReqData <= (others => '0'); + retryResetValid <= '0'; retryResetData <= '0'; + retryReqValid <= '0'; retryReqData <= (others => '0'); + retryRespGetEn <= '0'; timeOutGetEn <= '0'; + permReqValid <= '0'; permReqData <= (others => '0'); permRespGetEn <= '0'; + + -- mode signals (combinational from r) + inNormalState := (r.retryFlush = '0') and (r.errOccurred = '0') and (r.recvErrResp = '0'); + inRetryState := (r.retryFlush = '1') and (r.errOccurred = '0') and (r.recvErrResp = '0'); + inErrState := (r.errOccurred = '1') or (isERR = '1'); + inErrStateAlt := ((isRTS = '1') and ((r.recvErrResp = '1') or (r.errOccurred = '1'))) or (isERR = '1'); + + -------------------------------------------------------------------- + -- (a) Pre-stage control FSM (normal mode only): preBuild/preProc/deq + -- BUGFIX 2026-07-08: gate on pktMetaValid as well. In BSV, + -- preBuildRespInfo reads pktMetaDataPipeIn.first (RespHandleSQ.bsv:211), + -- so pktMetaDataPipeIn.notEmpty is an IMPLICIT rule condition. Without + -- it the FSM classifies the empty FIFO's stale FWFT dout: at cold start + -- (zeros, pktValid=0) it raises an illegal-resp error flush; after a + -- NAK retry it re-classifies the stale NAK, firing a new retry request + -- every ~15 cycles until the retry budget is exhausted (observed as + -- IBV_WC_RETRY_EXC_ERR under DROP_REQ_PSN fault injection). The pktMeta + -- stays in the FIFO until the DONE stage deqs it, so pktMetaValid holds + -- through all three stages of one classification. + -------------------------------------------------------------------- + if (isRTS = '1' and pendingWrValid = '1' and pktMetaValid = '1' and + inNormalState) then + case r.preStageState is + ---------------------------------------------------------------- + when SQ_PRE_BUILD_STAGE_S => + -- read pktMetaDataPipeIn.first header + opc := pktMetaData(623 downto 619); -- bth.opcode + bpsn := pktMetaData(554 downto 531); -- bth.psn + aCode:= pktMetaData(529 downto 528); + aVal := pktMetaData(527 downto 523); + wop := pendingWrData(614 downto 611); -- wr.opcode + -- relation (5 Bools): isReadAtomicWR[4] isMatchEndPSN[3] isCoalesce[2] + -- isMatchStartPSN[1] isPartialResp[0] + rel := (others => '0'); + if isReadOrAtomicWR(wop) then rel(4) := '1'; end if; + if bpsn = pendingWrData(51 downto 28) then rel(3) := '1'; end if; -- endPSN.val + if psnInRange(bpsn, pendingWrData(51 downto 28), getNPSN) then rel(2) := '1'; end if; + if bpsn = pendingWrData(76 downto 53) then rel(1) := '1'; end if; -- startPSN.val + if psnInRange(bpsn, pendingWrData(76 downto 53), pendingWrData(51 downto 28)) then rel(0) := '1'; end if; + -- rdmaRespType from opcode + aeth + rdmaRespType := RESP_UNK_C; + if isReadRespOp(opc) or isAtomicRespOp(opc) then + rdmaRespType := RESP_NORMAL_C; + elsif opc = "10001" then -- ACKNOWLEDGE + if aCode = AETH_ACK_C then rdmaRespType := RESP_NORMAL_C; + elsif aCode = AETH_RNR_C then rdmaRespType := RESP_RETRY_C; + elsif aCode = AETH_NAK_C then + if aVal = NAK_SEQ_C then rdmaRespType := RESP_RETRY_C; + elsif aVal = NAK_INV_REQ_C or aVal = NAK_RMT_ACC_C or aVal = NAK_RMT_OP_C or aVal = NAK_INV_RD_C then + rdmaRespType := RESP_ERROR_C; + else rdmaRespType := RESP_UNK_C; end if; + else rdmaRespType := RESP_UNK_C; end if; + end if; + -- respPktInfo (135): bth | aeth | flags + rpi := (others => '0'); + rpi(134 downto 39) := pktMetaData(626 downto 531); -- bth (96) + rpi(38 downto 7) := pktMetaData(530 downto 499); -- aeth (32) + if isFirstOrOnlyOp(opc) then rpi(6) := '1'; end if; + if isLastOrOnlyOp(opc) then rpi(5) := '1'; end if; + if isReadRespOp(opc) then rpi(4) := '1'; end if; + if isAtomicRespOp(opc) then rpi(3) := '1'; end if; + -- latch + v.preStageRespAndWorkReqRelation := rel; + v.preStageReqPktInfo := rpi; + v.preStageRespType := rdmaRespType; + v.preStagePktMetaData := pktMetaData; + v.preStageState := SQ_PRE_PROC_STAGE_S; + ---------------------------------------------------------------- + when SQ_PRE_PROC_STAGE_S => + rel := r.preStageRespAndWorkReqRelation; + rdmaRespType := r.preStageRespType; + deqPmd := '1'; deqPwr := '0'; + wrAck := WRA_UNK_C; wcReq := WC_UNK_C; + if r.preStagePktMetaData(1) = '0' then -- isIllegalResp = !pktValid + wrAck := WRA_ILL_C; wcReq := WC_FULL_C; + else + -- case {isMatchEndPSN, isCoalesce, isMatchStartPSN, isPartialResp} + if (rel(3) = '1' and rel(2) = '0' and rel(1) = '0' and rel(0) = '0') or + (rel(3) = '1' and rel(2) = '0' and rel(1) = '1' and rel(0) = '0') then -- 1000 / 1010 whole WR + if rdmaRespType = RESP_RETRY_C then + wrAck := WRA_EWR_C; wcReq := WC_NO_C; + elsif rdmaRespType = RESP_ERROR_C then + wrAck := WRA_EWE_C; wcReq := WC_FULL_C; deqPwr := '1'; + else -- NORMAL + wrAck := WRA_EWN_C; wcReq := WC_FULL_C; deqPwr := '1'; + end if; + elsif (rel(3) = '0' and rel(2) = '1' and rel(1) = '0' and rel(0) = '0') then -- 0100 coalesce + deqPmd := '0'; + if rel(4) = '1' then -- isReadAtomicWR -> implicit retry + wrAck := WRA_CR_C; wcReq := WC_NO_C; + else + wrAck := WRA_CN_C; wcReq := WC_FULL_C; deqPwr := '1'; + end if; + elsif (rel(3) = '0' and rel(2) = '0' and rel(1) = '1' and rel(0) = '0') or + (rel(3) = '0' and rel(2) = '0' and rel(1) = '0' and rel(0) = '1') then -- 0010/0001 partial + if rdmaRespType = RESP_RETRY_C then + wrAck := WRA_EPR_C; wcReq := WC_NO_C; + elsif rdmaRespType = RESP_ERROR_C then + wrAck := WRA_EPE_C; wcReq := WC_FULL_C; deqPwr := '1'; + else -- NORMAL + wrAck := WRA_EPN_C; wcReq := WC_PART_C; + end if; + else -- duplicate + wrAck := WRA_DUP_C; wcReq := WC_NO_C; + end if; + end if; + if deqPwr = '1' then + v.retryResetReq := RESET_CNT_TMO_C; + else + v.retryResetReq := RESET_TIMEOUT_C; + end if; + v.preStageDeqPktMetaData := deqPmd; + v.preStageDeqPendingWorkReq := deqPwr; + v.preStageWorkReqAckType := wrAck; + v.preStageWorkCompReqType := wcReq; + v.preStageState := SQ_PRE_STAGE_DONE_S; + ---------------------------------------------------------------- + when SQ_PRE_STAGE_DONE_S => + -- deqPktMetaDataOrWorkReq: gated on incomingRespQ room + if (incNotFull = '1') then + if r.preStageDeqPktMetaData = '1' then pktMetaDeq <= '1'; end if; + if r.preStageDeqPendingWorkReq = '1' then pendingWrDeq <= '1'; end if; + incWrEn <= '1'; + incDin <= pendingWrData & r.preStagePktMetaData & r.preStageReqPktInfo & + r.retryResetReq & r.preStageWorkCompReqType & r.preStageWorkReqAckType; + v.preStageState := SQ_PRE_BUILD_STAGE_S; + end if; + end case; + end if; + + -------------------------------------------------------------------- + -- (c) incomingRespQ source rules (mode-disjoint with deq-stage above) + -------------------------------------------------------------------- + -- discardGhostResp: normal, pktMeta present, no pending WR + if (isRTS = '1' and inNormalState and pktMetaValid = '1' and + pendingWrValid = '0' and incNotFull = '1') then + pktMetaDeq <= '1'; + rpi := (others => '0'); + rpi(134 downto 39) := pktMetaData(626 downto 531); -- bth + rpi(6) := '1'; rpi(5) := '1'; -- isFirstOrOnly/isLastOrOnly = True + rpi(1) := '1'; -- shouldDiscard + incWrEn <= '1'; + incDin <= ZERO_PWR_C & pktMetaData & rpi & + RESET_TIMEOUT_C & WC_NO_C & WRA_GHOST_C; + -- retryFlushPktMetaDataAndPayload: retry mode (also forces preStage=BUILD) + elsif (isRTS = '1' and inRetryState) then + v.preStageState := SQ_PRE_BUILD_STAGE_S; + if (pktMetaValid = '1' and incNotFull = '1') then + pktMetaDeq <= '1'; + rpi := (others => '0'); + rpi(134 downto 39) := pktMetaData(626 downto 531); + rpi(38 downto 7) := pktMetaData(530 downto 499); + opc := pktMetaData(623 downto 619); + if isFirstOrOnlyOp(opc) then rpi(6) := '1'; end if; + if isLastOrOnlyOp(opc) then rpi(5) := '1'; end if; + if isReadRespOp(opc) then rpi(4) := '1'; end if; + if isAtomicRespOp(opc) then rpi(3) := '1'; end if; + rpi(1) := '1'; -- shouldDiscard + incWrEn <= '1'; + incDin <= ZERO_PWR_C & pktMetaData & rpi & + RESET_TIMEOUT_C & WC_NO_C & WRA_DISC_C; + end if; + -- errFlushWorkReq: err mode, pending WR present + elsif (inErrStateAlt and pendingWrValid = '1' and incNotFull = '1') then + pendingWrDeq <= '1'; + rpi := (others => '0'); + rpi(6) := '1'; rpi(5) := '1'; -- isFirstOrOnly/isLastOrOnly + rpi(2) := '1'; -- hasLocalErr + rpi(1) := '1'; -- shouldDiscard + rpi(0) := '1'; -- genWorkComp + pmd := (others => '0'); + pmd(627) := '1'; -- isZeroPayloadLen = True; pktValid=0 + if r.hasTimeOutErr = '1' then + wrAck := WRA_TMOUT_C; + v.hasTimeOutErr := '0'; -- CReg port[0] clear + else + wrAck := WRA_FLUSH_C; + end if; + incWrEn <= '1'; + incDin <= pendingWrData & pmd & rpi & RESET_TIMEOUT_C & WC_FULL_C & wrAck; + -- errFlushIncomingResp: err mode, no pending WR + elsif (inErrStateAlt and pendingWrValid = '0' and pktMetaValid = '1' and incNotFull = '1') then + pktMetaDeq <= '1'; + rpi := (others => '0'); + rpi(134 downto 39) := pktMetaData(626 downto 531); + rpi(38 downto 7) := pktMetaData(530 downto 499); + opc := pktMetaData(623 downto 619); + if isFirstOrOnlyOp(opc) then rpi(6) := '1'; end if; + if isLastOrOnlyOp(opc) then rpi(5) := '1'; end if; + if isReadRespOp(opc) then rpi(4) := '1'; end if; + if isAtomicRespOp(opc) then rpi(3) := '1'; end if; + rpi(1) := '1'; -- shouldDiscard + incWrEn <= '1'; + incDin <= ZERO_PWR_C & pktMetaData & rpi & + RESET_TIMEOUT_C & WC_NO_C & WRA_DISC_C; + end if; + + -------------------------------------------------------------------- + -- (b) Linear pipeline stages (fire when isRTS or isERR) + -------------------------------------------------------------------- + if (isRTS = '1' or isERR = '1') then + + ---------------- recvRespHeader : incomingRespQ -> pendingRespQ ---------------- + if (incValid = '1') then + wrAck := incDout(3 downto 0); + -- resetRetry put only when isStableRTS (conditional implicit cond) + fire := (prsNotFull = '1') and ((isStableRTS = '0') or (retryResetReady = '1')); + if fire then + incRdEn <= '1'; + if isStableRTS = '1' then + retryResetValid <= '1'; + retryResetData <= incDout(6); -- retryResetReq + end if; + -- map wrAckType -> respAction; set mode flags + respAct := ACT_UNK_C; + case wrAck is + when WRA_EWN_C | WRA_EPN_C => respAct := ACT_EXP_NORM_C; + when WRA_EWR_C | WRA_EPR_C => + respAct := ACT_EXP_RETRY_C; v.recvRetryResp := '1'; v.retryFlush := '1'; + when WRA_EWE_C | WRA_EPE_C => + respAct := ACT_ERROR_C; v.recvErrResp := '1'; + when WRA_CN_C => respAct := ACT_COALESCE_C; + when WRA_CR_C => + respAct := ACT_IMP_RETRY_C; v.recvRetryResp := '1'; v.retryFlush := '1'; + when WRA_DUP_C => respAct := ACT_DUP_C; + when WRA_DISC_C | WRA_GHOST_C => respAct := ACT_DISCARD_C; + when WRA_ILL_C => + -- pktStatus2RespActionSQ(pktStatus = pmd bit0 = incDout(142)): + -- PKT_ST_VALID(0)->EXPLICIT_NORMAL, PKT_ST_LEN_ERR(1)->ILLEGAL + if incDout(142) = '0' then respAct := ACT_EXP_NORM_C; else respAct := ACT_ILLEGAL_C; end if; + v.recvErrResp := '1'; + when WRA_FLUSH_C => respAct := ACT_FLUSH_WR_C; + when WRA_TMOUT_C => respAct := ACT_TIMEOUT_C; + when others => respAct := ACT_UNK_C; + end case; + -- pendingResp din: pwr | pmd | rpi | respAct | wcReqType | wrAck + prsWrEn <= '1'; + prsDin <= incDout(1469 downto 791) & incDout(790 downto 142) & incDout(141 downto 7) & + respAct & incDout(5 downto 4) & wrAck; + end if; + end if; + + ---------------- handleRespByType : pendingRespQ -> pendingPermQueryQ ---------------- + if (prsValid = '1') then + pwr := prsDout(1472 downto 794); + rpi := prsDout(144 downto 10); + respAct := prsDout(9 downto 6); + wcReq := prsDout(5 downto 4); + opc := rpi(131 downto 127); -- bth.opcode within rpi + bpsn:= rpi(62 downto 39); -- bth.psn + aCode := rpi(37 downto 36); + aVal := rpi(35 downto 31); + wop := pwr(614 downto 611); + doPut := '0'; -- retry request put wanted? + if (respAct = ACT_EXP_RETRY_C or respAct = ACT_IMP_RETRY_C) then doPut := '1'; end if; + fire := (pqNotFull = '1') and ((doPut = '0') or (retryReqReady = '1')); + if fire then + prsRdEn <= '1'; + if respAct = ACT_EXP_NORM_C then + if inErrState = false then + v.preRdmaOpCode := opc; + end if; + if (not rdmaRespMatchWR(opc, wop)) or (not checkRespOpSeq(r.preRdmaOpCode, opc)) then + respAct := ACT_BAD_C; v.recvErrResp := '1'; + rpi(2) := '1'; -- hasLocalErr + if prsDout(3 downto 0) = WRA_EPN_C then wcReq := WC_PART_C; else wcReq := WC_FULL_C; end if; + end if; + elsif doPut = '1' then + -- build RetryReq(97): wrID(64) | retryStartPSN(24) | retryReason(3) | Maybe#RnrTimer(6) + -- retryStartPSN (upstream fix f2e0789, RespHandleSQ.bsv:711-712): + -- bth.psn only for Read/Atomic WRs (ACK PSN = exact resume point); + -- Send/Write must restart from the whole WR's first PSN = + -- unwrapMaybe(pendingWR.startPSN) (value slice [76:53], valid + -- tag [77] deliberately ignored) or a fragmented WR restarts + -- mid-WR after an RNR NAK. + retryReqValid <= '1'; + retryReqData <= pwr(678 downto 615) & -- wr.id + ite(isReadOrAtomicWR(wop), bpsn, pwr(76 downto 53)) & + getRetryReason(respAct, aCode, aVal) & + getRnrTimer(respAct, aCode, aVal); + end if; + pqWrEn <= '1'; + pqDin <= pwr & prsDout(793 downto 145) & rpi & respAct & wcReq; + end if; + end if; + + ---------------- queryPerm4NormalReadAtomicResp : pendingPermQueryQ -> pendingRetryCheckQ ------- + if (pqValid = '1') then + pwr := pqDout(1468 downto 790); + pmd := pqDout(789 downto 141); + rpi := pqDout(140 downto 6); + respAct := pqDout(5 downto 2); + wcReq := pqDout(1 downto 0); + expectPerm := '0'; + needPerm := (respAct = ACT_EXP_NORM_C) and (rpi(6) = '1') and (inErrState = false) and + (((rpi(4) = '1') and (pmd(627) = '0')) or (rpi(3) = '1')); -- (read&!zeroPayload)|atomic + fire := (prcNotFull = '1') and ((not needPerm) or (permReqReady = '1')); + if fire then + pqRdEn <= '1'; + if needPerm then + expectPerm := '1'; + -- PermCheckReq(267): wrID Maybe(65) | lkey(32) | rkey(32) | localOrRmtKey(1) | + -- reqAddr ADDR(64) | totalLen Length(32) | pdHandler(32) | isZeroDmaLen(1) | accFlags(8) + permReqValid <= '1'; + permReqData <= '1' & pwr(678 downto 615) & -- wrID = Valid wr.id + pwr(413 downto 382) & -- lkey + ZERO32_C & -- rkey = dontCare + '1' & -- localOrRmtKey = True + pwr(477 downto 414) & -- reqAddr = wr.laddr + pwr(509 downto 478) & -- totalLen = wr.len + pmd(33 downto 2) & -- pdHandler + (pmd(627) and not rpi(3)) & -- isZeroDmaLen = atomic?False:isZeroPayloadLen + ACC_LOCAL_WRITE_C; -- accFlags + end if; + -- pendingRetryCheck din: pwr | pmd | rpi | respAct | wcReq | expectPerm + prcWrEn <= '1'; + prcDin <= pwr & pmd & rpi & respAct & wcReq & expectPerm; + end if; + end if; + + ---------------- checkRetryErr : pendingRetryCheckQ -> pendingPermCheckQ ---------------- + if (prcValid = '1') then + pwr := prcDout(1469 downto 791); + pmd := prcDout(790 downto 142); + rpi := prcDout(141 downto 7); + respAct := prcDout(6 downto 3); + wcReq := prcDout(2 downto 1); + expectPerm := prcDout(0); + opc := rpi(131 downto 127); + aCode := rpi(37 downto 36); + aVal := rpi(35 downto 31); + wop := pwr(614 downto 611); + mWcStat := (others => '0'); -- Invalid + doPut := '0'; -- consumes retry response? + if (respAct = ACT_EXP_RETRY_C or respAct = ACT_IMP_RETRY_C) then doPut := '1'; end if; + fire := (ppcNotFull = '1') and ((doPut = '0') or (retryRespValid = '1')); + if fire then + prcRdEn <= '1'; + case respAct is + when ACT_BAD_C => + rpi(0) := '1'; rpi(1) := '1'; -- genWorkComp, shouldDiscard + mWcStat := '1' & WCS_BAD_RESP_C; + when ACT_ERROR_C => + rpi(0) := '1'; + mWcStat := genErrWcStatusFromAeth(aCode, aVal); + when ACT_EXP_NORM_C => + -- needWorkComp = signaled flag (wr.flags bit1) or isReadOrAtomicWR + if ((pwr(607) = '1') or isReadOrAtomicWR(wop)) and (rpi(5) = '1') then -- needWC & isLastOrOnly + rpi(0) := '1'; + mWcStat := '1' & WCS_SUCCESS_C; + end if; + when ACT_COALESCE_C => + if (pwr(607) = '1') or isReadOrAtomicWR(wop) then + rpi(0) := '1'; + mWcStat := '1' & WCS_SUCCESS_C; + end if; + when ACT_DUP_C => + rpi(1) := '1'; + when ACT_ILLEGAL_C => + rpi(0) := '1'; rpi(1) := '1'; + -- pktStatus2WorkCompStatusSQ(pmd.pktStatus bit0): VALID->SUCCESS, LEN_ERR->LOC_LEN + if pmd(0) = '0' then mWcStat := '1' & WCS_SUCCESS_C; else mWcStat := '1' & WCS_LOC_LEN_C; end if; + when ACT_DISCARD_C => + rpi(1) := '1'; + when ACT_FLUSH_WR_C => + rpi(0) := '1'; + mWcStat := '1' & WCS_WR_FLUSH_C; + when ACT_EXP_RETRY_C | ACT_IMP_RETRY_C => + retryRespGetEn <= '1'; + if retryRespData = '1' then -- RETRY_LIMIT_EXC + mWcStat := '1' & WCS_RETRY_EXC_C; + wcReq := WC_PART_C; + rpi(0) := '1'; + end if; + rpi(1) := '1'; + when ACT_TIMEOUT_C => + rpi(0) := '1'; + mWcStat := '1' & WCS_RESP_TMOUT_C; + when others => null; + end case; + -- pendingPermCheck din: pwr|pmd|rpi|respAct|mWcStat|wcReq|expectPerm + ppcWrEn <= '1'; + ppcDin <= pwr & pmd & rpi & respAct & mWcStat & wcReq & expectPerm; + end if; + end if; + + ---------------- checkPerm4NormalReadAtomicResp : pendingPermCheckQ -> pendingAddrCalcQ ------- + if (ppcValid = '1') then + pwr := ppcDout(1475 downto 797); + pmd := ppcDout(796 downto 148); + rpi := ppcDout(147 downto 13); + respAct := ppcDout(12 downto 9); + mWcStat := ppcDout(8 downto 3); + wcReq := ppcDout(2 downto 1); + expectPerm := ppcDout(0); + doPut := '0'; -- consumes perm response? + if (respAct = ACT_EXP_NORM_C and expectPerm = '1') then doPut := '1'; end if; + fire := (pacNotFull = '1') and ((doPut = '0') or (permRespValid = '1')); + if fire then + ppcRdEn <= '1'; + if doPut = '1' then + permRespGetEn <= '1'; + if permRespData = '0' then -- mrCheckResult = False + mWcStat := '1' & WCS_LOC_ACC_C; + respAct := ACT_LOC_ACC_C; + rpi(0) := '1'; rpi(2) := '1'; rpi(1) := '1'; + end if; + end if; + pacWrEn <= '1'; + pacDin <= pwr & pmd & rpi & respAct & mWcStat & wcReq; + end if; + end if; + + ---------------- calcReadRespAddr : pendingAddrCalcQ -> pendingLenCalcQ ---------------- + if (pacValid = '1' and plcNotFull = '1') then + pacRdEn <= '1'; + pwr := pacDout(1474 downto 796); + pmd := pacDout(795 downto 147); + rpi := pacDout(146 downto 12); + respAct := pacDout(11 downto 8); + mWcStat := pacDout(7 downto 2); + wcReq := pacDout(1 downto 0); + opc := rpi(131 downto 127); + nAddr := r.nextReadRespWriteAddr; + if rpi(4) = '1' then -- isReadResp + if isOnlyOp(opc) then + nAddr := pwr(477 downto 414); -- wr.laddr + elsif isFirstOp(opc) then + nAddr := addrAddPsn(pwr(477 downto 414), x"000001", getPMTU); + elsif isMidOp(opc) then + nAddr := addrAddPsn(r.nextReadRespWriteAddr, x"000001", getPMTU); + end if; -- isLastOp: nAddr unchanged + if (respAct = ACT_EXP_NORM_C) and (inErrState = false) then + v.nextReadRespWriteAddr := nAddr; + end if; + end if; + plcWrEn <= '1'; + plcDin <= pwr & pmd & rpi & respAct & mWcStat & wcReq & nAddr; + end if; + + ---------------- calcReadRespLen : pendingLenCalcQ -> pendingSpaceCalcQ ---------------- + if (plcValid = '1' and pscNotFull = '1') then + plcRdEn <= '1'; + pwr := plcDout(1538 downto 860); + pmd := plcDout(859 downto 211); + rpi := plcDout(210 downto 76); + respAct := plcDout(75 downto 72); + mWcStat := plcDout(71 downto 66); + wcReq := plcDout(65 downto 64); + nAddr := plcDout(63 downto 0); + opc := rpi(131 downto 127); + remLen := r.remainingReadRespLen; + if rpi(4) = '1' then + if isOnlyOp(opc) then + remLen := slv(unsigned(pwr(509 downto 478)) - resize(unsigned(pmd(648 downto 636)), 32)); + elsif isFirstOp(opc) then + remLen := lenSubPsn(pwr(509 downto 478), x"000001", getPMTU); + elsif isMidOp(opc) then + remLen := lenSubPsn(r.remainingReadRespLen, x"000001", getPMTU); + else -- last + remLen := lenSubPktLen(r.remainingReadRespLen, pmd(648 downto 636), getPMTU); + end if; + if (respAct = ACT_EXP_NORM_C) and (inErrState = false) then + v.remainingReadRespLen := remLen; + end if; + end if; + -- RespLenCheckResult(98): enoughDmaSpace(F)|isLastPayloadLenZero(T)|nextAddr|remLen + rlcr := '0' & '1' & nAddr & remLen; + pscWrEn <= '1'; + pscDin <= pwr & pmd & rpi & respAct & mWcStat & wcReq & rlcr & r.remainingReadRespLen; + end if; + + ---------------- calcEnoughDmaSpace : pendingSpaceCalcQ -> pendingLenCheckQ ---------------- + if (pscValid = '1' and plkNotFull = '1') then + pscRdEn <= '1'; + pwr := pscDout(1604 downto 926); + pmd := pscDout(925 downto 277); + rpi := pscDout(276 downto 142); + respAct := pscDout(141 downto 138); + mWcStat := pscDout(137 downto 132); + wcReq := pscDout(131 downto 130); + rlcr := pscDout(129 downto 32); + preRem := pscDout(31 downto 0); + opc := rpi(131 downto 127); + -- enoughDmaSpace default True; isLastPayloadLenZero default False + rlcr(97) := '1'; rlcr(96) := '0'; + if rpi(4) = '1' then + if isOnlyOp(opc) then + if lenGtEqPktLen(pwr(509 downto 478), pmd(648 downto 636), getPMTU) then rlcr(97) := '1'; else rlcr(97) := '0'; end if; + elsif isFirstOp(opc) then + if lenGtEqPMTU(pwr(509 downto 478), getPMTU) then rlcr(97) := '1'; else rlcr(97) := '0'; end if; + elsif isMidOp(opc) then + if lenGtEqPMTU(preRem, getPMTU) then rlcr(97) := '1'; else rlcr(97) := '0'; end if; + else -- last + if lenGtEqPktLen(preRem, pmd(648 downto 636), getPMTU) then rlcr(97) := '1'; else rlcr(97) := '0'; end if; + rlcr(96) := pmd(627); -- isLastPayloadLenZero = isZeroPayloadLen + end if; + end if; + plkWrEn <= '1'; + plkDin <= pwr & pmd & rpi & respAct & mWcStat & wcReq & rlcr; + end if; + + ---------------- checkReadRespLen : pendingLenCheckQ -> pendingDmaReqQ ---------------- + if (plkValid = '1' and pdrNotFull = '1') then + plkRdEn <= '1'; + pwr := plkDout(1572 downto 894); + pmd := plkDout(893 downto 245); + rpi := plkDout(244 downto 110); + respAct := plkDout(109 downto 106); + mWcStat := plkDout(105 downto 100); + wcReq := plkDout(99 downto 98); + rlcr := plkDout(97 downto 0); + nAddr := rlcr(95 downto 32); + remLen := rlcr(31 downto 0); + if (rpi(4) = '1') and (respAct = ACT_EXP_NORM_C) and (inErrState = false) then + -- readRespLenMatch = isLastOrOnly ? isZero(remLen) : True + fire := true; + if rpi(5) = '1' then + fire := (unsigned(remLen) = 0); + end if; + if (rlcr(97) = '0') or (not fire) or (rlcr(96) = '1') then + respAct := ACT_LOC_LEN_C; + mWcStat := '1' & WCS_LOC_LEN_C; + if rpi(5) = '1' then wcReq := WC_FULL_C; else wcReq := WC_PART_C; end if; + rpi(0) := '1'; rpi(2) := '1'; rpi(1) := '1'; + end if; + end if; + pdrWrEn <= '1'; + pdrDin <= pwr & pmd & rpi & respAct & mWcStat & wcReq & nAddr; + end if; + + ---------------- issueDmaReq : pendingDmaReqQ -> pendingWorkCompQ ---------------- + if (pdrValid = '1') then + pwr := pdrDout(1538 downto 860); + pmd := pdrDout(859 downto 211); + rpi := pdrDout(210 downto 76); + respAct := pdrDout(75 downto 72); + mWcStat := pdrDout(71 downto 66); + wcReq := pdrDout(65 downto 64); + nAddr := pdrDout(63 downto 0); + opc := rpi(131 downto 127); + bpsn := rpi(62 downto 39); + wcWaitDma := '0'; + doPut := '0'; + pcInfo := (others => '0'); + if respAct = ACT_EXP_NORM_C then + if inErrState = false then + if (rpi(4) = '1') and (pmd(627) = '0') then -- read & !zeroPayload + -- PayloadConInfo : BSV deriving(Bits) LSB-justifies the 129b + -- union members, so SendWriteReqReadRespInfo/DiscardPayloadInfo + -- carry DmaWriteMetaData at [128:0] with zero-pad at [192:129] + -- (only the 193b Atomic member is metadata-MSB-aligned). + -- OQ-RHSQ-03 RESOLVED — was MSB-aligned, same emit bug as + -- DEVIATION-PCCAG-01's consumer side. + pcInfo := "10" & ZERO64_C & -- tag=2, pad [192:129] + DMA_SQ_WR_C & getSQPN & nAddr & pmd(648 downto 636) & bpsn; + doPut := '1'; wcWaitDma := '1'; + elsif rpi(3) = '1' then -- atomic + pcInfo := "01" & -- tag=1 (AtomicRespInfoAndPayload) + DMA_SQ_ATOM_C & getSQPN & pwr(477 downto 414) & + pwr(490 downto 478) & bpsn & -- len = truncate(wr.len) to 13b + pmd(498 downto 435); -- atomicRespPayload = atomicAckEth.orig(64) + doPut := '1'; wcWaitDma := '1'; + end if; + end if; + elsif ((rpi(1) = '1') or inErrState) and (pmd(627) = '0') then -- discard & !zeroPayload + pcInfo := "00" & ZERO64_C & -- tag=0, LSB-justified (OQ-RHSQ-03) + DMA_SQ_DISC_C & getSQPN & nAddr & pmd(648 downto 636) & bpsn; + doPut := '1'; + end if; + fire := (pwcNotFull = '1') and ((doPut = '0') or (payloadConReqReady = '1')); + if fire then + pdrRdEn <= '1'; + if doPut = '1' then + payloadConReqValid <= '1'; + payloadConReqData <= pmd(635 downto 628) & pcInfo; -- fragNum | consumeInfo + end if; + -- hasInternalErr port[0] <= True if wcStatus Valid and != SUCCESS + if (mWcStat(5) = '1') and (mWcStat(4 downto 0) /= WCS_SUCCESS_C) then + v.hasInternalErr := '1'; + end if; + -- WorkCompGenReqSQ(633): wr(601)|wcWaitDma(1)|wcReqType(2)|triggerPSN(24)|wcStatus(5) + if mWcStat(5) = '1' then wcStat := mWcStat; else wcStat := '1' & WCS_SUCCESS_C; end if; + wcGenReq := pwr(678 downto 78) & wcWaitDma & wcReq & bpsn & wcStat(4 downto 0); + pwcWrEn <= '1'; + pwcDin <= rpi & wcGenReq; + end if; + end if; + + ---------------- genWorkCompSQ : pendingWorkCompQ -> workCompGenReqOutQ ---------------- + if (pwcValid = '1') then + rpi := pwcDout(767 downto 633); + wcGenReq := pwcDout(632 downto 0); + -- enq when genWorkComp or wcWaitDmaResp + enqOut := rpi(0) or wcGenReq(31); + if (enqOut = '0') or (outNotFull = '1') then + pwcRdEn <= '1'; + if enqOut = '1' then + outWrEn <= '1'; + outDin <= wcGenReq; + end if; + end if; + end if; + + ---------------- checkTimeOutErr (normal): notifyTimeOut2SQ ---------------- + if (inNormalState and timeOutValid = '1') then + timeOutGetEn <= '1'; + if timeOutData = '1' then -- TIMEOUT_ERR + v.hasTimeOutErr := '1'; -- CReg port[0] + end if; + end if; + + ---------------- canonicalize : reads CReg port[1] (after port[0] writes above) ---------------- + if (v.hasInternalErr = '1') or (v.hasTimeOutErr = '1') then + v.errOccurred := '1'; + v.hasInternalErr := '0'; -- port[1] clear + end if; + + ---------------- retryFlushDone (retry) ---------------- + if (inRetryState and isRetrying = '1') then + v.retryFlush := '0'; + v.recvRetryResp := '0'; + end if; + + end if; + + -- resetAndClear (isReset): force pre-stage to BUILD, clear mode flags; FIFOs cleared via fifoClr + if (isReset = '1') then + v.preStageState := SQ_PRE_BUILD_STAGE_S; + v.preRdmaOpCode := ACKNOWLEDGE_C; + v.recvErrResp := '0'; + v.recvRetryResp := '0'; + v.errOccurred := '0'; + v.retryFlush := '0'; + v.hasInternalErr := '0'; + v.hasTimeOutErr := '0'; + end if; + + -- structural synchronous reset + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/RetryHandleSq.vhd b/ethernet/RoCEv2/rtl/RetryHandleSq.vhd new file mode 100644 index 0000000000..0cf87f1fb8 --- /dev/null +++ b/ethernet/RoCEv2/rtl/RetryHandleSq.vhd @@ -0,0 +1,951 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Three concurrent, FIFO-decoupled behaviours under ONE RegType (per the FSM +-- spec): +-- (1) Detection pipeline — 7 always-active rules gated only by isStableRTS + +-- FIFO occupancy (recvResetReq, recvRetryReq, checkTimeOut, +-- handleNotifiedRetryAndTimeOut, handleRetryAction, handleRetryCntUpdate, +-- sendRetryResp). No state register; pure feed-forward across FIFOs. +-- (2) Retry-control FSM — retryCntrlState (BSV mkCReg(2), 4 states). Rules +-- initRetry, waitRetryFinish, stopScanQ + port1 write from +-- handleRetryCntUpdate. +-- (3) Retry-handle FSM — retryHandleState (8 states). Rules startPreRetry, +-- rnrCheck, rnrWait, checkPartialRetry, modifyPartialRetryWR, startRetry, +-- waitRetryDone. +-- pauseRetryHandle partitions (2)/(3): handleRetryCntUpdate requires !pause; +-- initRetry requires pause; all handle-FSM rules require !pause. +-- +-- CReg(2) ORDERING (FSM-spec item 1, carried forward): retryCntrlState has two +-- write ports. port0 writers = resetAndClear, initRetry, waitRetryFinish. +-- port1 writer = handleRetryCntUpdate. A port1 write OVERRIDES a same-cycle +-- port0 write. The only pair that can fire together is waitRetryFinish +-- (port0 -> NOT_RETRY) and handleRetryCntUpdate (port1 -> INIT_RETRY); when both +-- fire handleRetryCntUpdate must win. Two-process encoding: port0 writers +-- update v.retryCntrlState FIRST (Block 2 below), handleRetryCntUpdate applies +-- its update LAST (later assignment wins) and reads the already-updated v for +-- its hasRetryErr test. +-- +-- FIFO clear: BSV FIFOF.clear under resetAndClear (isReset) -> fifoClr = rst or +-- isReset, asserted to every Fifo rst (level-safe sync clear; OQ-FSM-01 +-- carry-forward). timeOutNotificationQ is additionally cleared by +-- initRetryCntAndTimeOutTimer (isRTR2RTS) -> tnClr = fifoClr or isRTR2RTS. +-- wr_en left ungated: FifoWrFsm sync reset dominates a concurrent write +-- (clear-after-enq ordering, per OQ-FSM-01). +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd), all 11 +-- surf.Fifo FWFT/sync/block, ADDR_WIDTH_G=4: +-- U_ResetReqQ 1 U_TimeOutNotificationQ 1 U_RetryReqQ 97 +-- U_RetryRespQ 1 U_ResetTimeOutQ 1 U_ResetRetryCntQ 1 +-- U_TimeOutTriggerQ 1 U_RetryNotificationQ 98 U_RetryActionQ 98 +-- U_UpdateRetryCntQ 4 U_PrepareRetryRespQ 4 +-- +-- Type widths (BSV deriving(Bits), first-field-at-MSB; traced from +-- DataTypes.bsv/Headers.bsv/Settings.bsv): +-- RetryReq=97 (wrID[96:33] | retryStartPSN[32:9] | retryReason[8:6] | +-- Maybe#RnrTimer[5:0] = tag[5]|value[4:0]); Maybe#(RetryReq)=98 (tag@97). +-- Maybe#(RetryReason)=4 (tag[3]|reason[2:0]). +-- Tuple2#(Bool,RetryReason)=4 (hasRetryErr[3]|reason[2:0]). +-- PendingWorkReq=679 (scanGetHead/modifyHead): wr[678:78] within which +-- wr.id[678:615], wr.raddr[605:542], wr.len[509:478], wr.laddr[477:414]; +-- startPSN tag[77]/val[76:53]; endPSN tag[52]/val[51:28]. +-- RetryReason(3): NOT_RETRY=000 RNR=001 SEQ_ERR=010 IMPLICIT=011 TIMEOUT=100. +-- +-- Width corrections vs Stage-1 inventory (source-derived, not invented; same +-- class as OQ-FSM-DS2H-02 / OQ-FSM-CntrlQP-01): +-- rnrWaitCnt : RNR_WAIT_CYCLE_CNT_WIDTH = TLog#(MAX_RNR_WAIT_CYCLES) = +-- TLog#(655360000/2 = 327680000) = 29 bits (inventory said 32). +-- timeOutCnt : TIMEOUT_CYCLE_CNT_WIDTH = 1+TLog#(MAX_TIMEOUT_CYCLES) = +-- 1+TLog#(2^43/2 = 2^42) = 43 bits (inventory said 64). +-- retryReason 3 bits (5 enum values), retryHandleState 3 bits (8 enum values). +-- isZero4LargeBits(timeOutCnt[42:0]) splits low=[20:0](21b), high=[42:21](22b). +-- +-- Auxiliary datapath regs are BSV mkRegU (no reset) — zero-initialised here for +-- determinism; each is write-before-read within its retry episode so the chosen +-- init is not functionally observed (FSM-spec note). +-- +-- Excluded/Deferred: all immAssert / immFail calls in the BSV source are +-- simulation-only and are NOT reproduced here (decRetryCntByReason default, +-- handleRetryCntUpdate !hasRetryErr, startPreRetry retryReason!=NOT_RETRY, +-- handleRetryAction pendingWorkReqNotEmpty / retryRnrTimer valid, +-- checkPartialRetry retryWorkReqId / PSN-in-range). See OQ-S3-RETRY-01/02. +-- +-- REMINDER: emitting does not prove equivalence — simulate this entity (cocotb) +-- before trusting it (Stage 5, testbench-verify). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity RetryHandleSq is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- cntrlStatus.comm status methods (combinational inputs) + isReset : in sl; -- comm.isReset -> resetAndClear + isERR : in sl; -- comm.isERR -> stopScanQ + isStableRTS : in sl; -- comm.isStableRTS (gates all dataflow rules) + isRTR2RTS : in sl; -- comm.isRTR2RTS -> initRetryCntAndTimeOutTimer + getMaxRetryCnt : in slv(2 downto 0); -- comm.getMaxRetryCnt (RetryCnt) + getMaxRnrCnt : in slv(2 downto 0); -- comm.getMaxRnrCnt (RetryCnt) + getMaxTimeOut : in slv(4 downto 0); -- comm.getMaxTimeOut (TimeOutTimer) + getMinRnrTimer : in slv(4 downto 0); -- comm.getMinRnrTimer (RnrTimer) + getPMTU : in slv(2 downto 0); -- comm.getPMTU (PMTU enum) + -- pending-WR scan status (input) + pendingWorkReqNotEmpty : in sl; + -- pendingWorkReqScanCntrl : ScanCntrl#(PendingWorkReq) — FSM consumes (in) + scanGetHead : in slv(678 downto 0); -- getHead (PendingWorkReq) + scanIsScanDone : in sl; -- isScanDone + -- pendingWorkReqScanCntrl drives (out, combinational pulses) + scanClear : out sl; -- clear + scanStop : out sl; -- scanStop + scanStart : out sl; -- scanStart + scanPreScanStart : out sl; -- preScanStart + scanPreScanRestart : out sl; -- preScanRestart + scanModifyHeadValid : out sl; -- modifyHead strobe + scanModifyHeadData : out slv(678 downto 0); -- modifyHead(head) + -- status methods (combinational Moore outputs) + hasRetryErr : out sl; + isRetryDone : out sl; + isRetrying : out sl; + -- resetRetryCntAndTimeOutBySQ : Action(ResetRetryCntAndTimeOutReq) (1b) + resetReqValid : in sl; -- caller enable + resetReqData : in sl; -- 0=RESET_TIMEOUT, 1=RESET_CNT_AND_TIMEOUT + resetReqReady : out sl; -- isStableRTS and resetReqQ.notFull + -- notifyTimeOut2SQ : Get#(TimeOutNotification) (1b) + timeOutNotifValid : out sl; -- notEmpty + timeOutNotifData : out sl; -- 0=TIMEOUT_RETRY, 1=TIMEOUT_ERR + timeOutNotifGetEn : in sl; -- external deq + -- srvPort.request : Put#(RetryReq) (97b) + srvReqValid : in sl; + srvReqData : in slv(96 downto 0); + srvReqReady : out sl; -- retryReqQ.notFull + -- srvPort.response : Get#(RetryResp) (1b) + srvRespValid : out sl; -- notEmpty + srvRespData : out sl; -- 0=RECV_RETRY_REQ, 1=RETRY_LIMIT_EXC + srvRespGetEn : in sl); -- external deq +end entity RetryHandleSq; + +architecture rtl of RetryHandleSq is + + --------------------------------------------------------------------------- + -- Width constants (source-derived; see header) + --------------------------------------------------------------------------- + constant RNR_WAIT_W_C : integer := 29; -- RNR_WAIT_CYCLE_CNT_WIDTH + constant TIMEOUT_W_C : integer := 43; -- TIMEOUT_CYCLE_CNT_WIDTH + constant INFINITE_RETRY_C : slv(2 downto 0) := "111"; -- INFINITE_RETRY = 7 + + --------------------------------------------------------------------------- + -- Enum encodings + --------------------------------------------------------------------------- + -- RetryReason (3b) + constant RR_NOT_RETRY_C : slv(2 downto 0) := "000"; + constant RR_RNR_C : slv(2 downto 0) := "001"; + constant RR_SEQ_ERR_C : slv(2 downto 0) := "010"; + constant RR_IMPLICIT_C : slv(2 downto 0) := "011"; + constant RR_TIMEOUT_C : slv(2 downto 0) := "100"; + -- ResetRetryCntAndTimeOutReq (1b) + constant RESET_TIMEOUT_C : sl := '0'; + constant RESET_CNT_TIMEOUT_C : sl := '1'; + -- TimeOutNotification (1b): TIMEOUT_RETRY=0, TIMEOUT_ERR=1 + constant TIMEOUT_RETRY_C : sl := '0'; + constant TIMEOUT_ERR_C : sl := '1'; + -- RetryResp (1b): RECV_RETRY_REQ=0, RETRY_LIMIT_EXC=1 + constant RECV_RETRY_REQ_C : sl := '0'; + constant RETRY_LIMIT_EXC_C : sl := '1'; + + --------------------------------------------------------------------------- + -- FSM state types + --------------------------------------------------------------------------- + type RetryCntrlStateType is ( + RETRY_CNTRL_ST_NOT_RETRY_S, + RETRY_CNTRL_ST_RETRY_LIMIT_EXC_S, + RETRY_CNTRL_ST_INIT_RETRY_S, + RETRY_CNTRL_ST_WAIT_RETRY_DONE_S); + + type RetryHandleStateType is ( + RETRY_HANDLE_ST_NOT_RETRY_S, + RETRY_HANDLE_ST_START_PRE_RETRY_S, + RETRY_HANDLE_ST_RNR_CHECK_S, + RETRY_HANDLE_ST_RNR_WAIT_S, + RETRY_HANDLE_ST_CHECK_PARTIAL_RETRY_WR_S, + RETRY_HANDLE_ST_MODIFY_PARTIAL_RETRY_WR_S, + RETRY_HANDLE_ST_START_RETRY_S, + RETRY_HANDLE_ST_WAIT_RETRY_DONE_S); + + --------------------------------------------------------------------------- + -- RegType : ONE record (three coupled FSMs + aux datapath) + --------------------------------------------------------------------------- + type RegType is record + -- control + handle FSM state (real BSV mkReg/mkCReg inits) + retryCntrlState : RetryCntrlStateType; + retryHandleState : RetryHandleStateType; + pauseRetryHandle : sl; + -- auxiliary datapath (BSV mkRegU — zero-init for determinism) + rnrWaitCnt : slv(RNR_WAIT_W_C-1 downto 0); + isRnrWaitCntZero : sl; + timeOutCnt : slv(TIMEOUT_W_C-1 downto 0); + isTimeOutCntHighPartZero : sl; + isTimeOutCntLowPartZero : sl; + disableTimeOut : sl; + disableRetryCnt : sl; + retryReason : slv(2 downto 0); + retryWorkReqId : slv(63 downto 0); + retryStartPsn : slv(23 downto 0); + psnDiff : slv(23 downto 0); + retryRnrTimer : slv(4 downto 0); + retryCnt : slv(2 downto 0); + rnrCnt : slv(2 downto 0); + end record RegType; + + constant REG_INIT_C : RegType := ( + retryCntrlState => RETRY_CNTRL_ST_NOT_RETRY_S, + retryHandleState => RETRY_HANDLE_ST_NOT_RETRY_S, + pauseRetryHandle => '0', + rnrWaitCnt => (others => '0'), + isRnrWaitCntZero => '0', + timeOutCnt => (others => '0'), + isTimeOutCntHighPartZero => '0', + isTimeOutCntLowPartZero => '0', + disableTimeOut => '0', + disableRetryCnt => '0', + retryReason => (others => '0'), + retryWorkReqId => (others => '0'), + retryStartPsn => (others => '0'), + psnDiff => (others => '0'), + retryRnrTimer => (others => '0'), + retryCnt => (others => '0'), + rnrCnt => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + --------------------------------------------------------------------------- + -- FIFO interface signals (one bundle per surf.Fifo) + --------------------------------------------------------------------------- + -- resetReqQ (1b) + signal rrqWrEn, rrqRdEn, rrqValid, rrqNotFull : sl; + signal rrqDin, rrqDout : slv(0 downto 0); + -- timeOutNotificationQ (1b) + signal tnqWrEn, tnqRdEn, tnqValid, tnqNotFull : sl; + signal tnqDin, tnqDout : slv(0 downto 0); + signal tnqClr : sl; + -- retryReqQ (97b) + signal xrqWrEn, xrqRdEn, xrqValid, xrqNotFull : sl; + signal xrqDin, xrqDout : slv(96 downto 0); + -- retryRespQ (1b) + signal rsqWrEn, rsqRdEn, rsqValid, rsqNotFull : sl; + signal rsqDin, rsqDout : slv(0 downto 0); + -- resetTimeOutQ (1b) + signal rtqWrEn, rtqRdEn, rtqValid, rtqNotFull : sl; + signal rtqDin, rtqDout : slv(0 downto 0); + -- resetRetryCntQ (1b) + signal rcqWrEn, rcqRdEn, rcqValid, rcqNotFull : sl; + signal rcqDin, rcqDout : slv(0 downto 0); + -- timeOutTriggerQ (1b) + signal ttqWrEn, ttqRdEn, ttqValid, ttqNotFull : sl; + signal ttqDin, ttqDout : slv(0 downto 0); + -- retryNotificationQ (98b) + signal rnqWrEn, rnqRdEn, rnqValid, rnqNotFull : sl; + signal rnqDin, rnqDout : slv(97 downto 0); + -- retryActionQ (98b) + signal raqWrEn, raqRdEn, raqValid, raqNotFull : sl; + signal raqDin, raqDout : slv(97 downto 0); + -- updateRetryCntQ (4b) + signal urqWrEn, urqRdEn, urqValid, urqNotFull : sl; + signal urqDin, urqDout : slv(3 downto 0); + -- prepareRetryRespQ (4b) + signal prqWrEn, prqRdEn, prqValid, prqNotFull : sl; + signal prqDin, prqDout : slv(3 downto 0); + + signal fifoClr : sl; + + --------------------------------------------------------------------------- + -- Helper functions (BSV Utils.bsv / PrimUtils.bsv equivalents) + --------------------------------------------------------------------------- + -- PMTU enum -> log2(PMTU bytes): 256->8, 512->9, 1024->10, 2048->11, 4096->12 + function pmtuLog(pmtu : slv(2 downto 0)) return integer is + begin + case pmtu is + when "001" => return 8; + when "010" => return 9; + when "011" => return 10; + when "100" => return 11; + when others => return 12; + end case; + end function; + + -- addrAddPsnMultiplyPMTU = addr + (psn << log2(PMTU)) + function addrAddPsn(addr : slv(63 downto 0); psn : slv(23 downto 0); pmtu : slv(2 downto 0)) return slv is + begin + return slv(unsigned(addr) + shift_left(resize(unsigned(psn), 64), pmtuLog(pmtu))); + end function; + + -- lenSubtractPsnMultiplyPMTU = len - (psn << log2(PMTU)) + function lenSubPsn(len : slv(31 downto 0); psn : slv(23 downto 0); pmtu : slv(2 downto 0)) return slv is + begin + return slv(unsigned(len) - shift_left(resize(unsigned(psn), 32), pmtuLog(pmtu))); + end function; + + -- calcPsnDiff(a,b) = truncate({1'b1,a} - {1'b0,b}) = (a - b) mod 2^24 + function calcPsnDiff(a : slv(23 downto 0); b : slv(23 downto 0)) return slv is + begin + return slv(unsigned(a) - unsigned(b)); + end function; + + -- getRnrTimeOutValue(rnrTimer) in cycles (TARGET_CYCLE_NS = 2). Max 327680000 + -- fits in 29 bits and in a 32-bit integer. + function getRnrTimeOutValue(t : slv(4 downto 0)) return integer is + begin + case to_integer(unsigned(t)) is + when 0 => return 327680000; + when 1 => return 5000; + when 2 => return 10000; + when 3 => return 15000; + when 4 => return 20000; + when 5 => return 30000; + when 6 => return 40000; + when 7 => return 60000; + when 8 => return 80000; + when 9 => return 120000; + when 10 => return 160000; + when 11 => return 240000; + when 12 => return 320000; + when 13 => return 480000; + when 14 => return 640000; + when 15 => return 960000; + when 16 => return 1280000; + when 17 => return 1920000; + when 18 => return 2560000; + when 19 => return 3840000; + when 20 => return 5120000; + when 21 => return 7680000; + when 22 => return 10240000; + when 23 => return 15360000; + when 24 => return 20480000; + when 25 => return 30720000; + when 26 => return 40960000; + when 27 => return 61440000; + when 28 => return 81920000; + when 29 => return 122880000; + when 30 => return 163840000; + when others => return 245760000; -- 31 + end case; + end function; + + -- getTimeOutValue(t) in cycles (TARGET_CYCLE_NS = 2): t=0 -> 0 (infinite), + -- else 8192 * 2^(t-1) / 2 = 2^(11+t). Max 2^42, needs 43-bit (exceeds integer). + function getTimeOutValue(t : slv(4 downto 0)) return slv is + variable ti : integer; + begin + ti := to_integer(unsigned(t)); + if ti = 0 then + return slv(to_unsigned(0, TIMEOUT_W_C)); + else + return slv(shift_left(to_unsigned(1, TIMEOUT_W_C), 11 + ti)); + end if; + end function; + +begin + + --------------------------------------------------------------------------- + -- Clears (level-safe synchronous flush; OQ-FSM-01 carry-forward) + --------------------------------------------------------------------------- + fifoClr <= rst or isReset; + tnqClr <= rst or isReset or isRTR2RTS; -- initRetryCntAndTimeOutTimer clears timeOutNotificationQ + scanClear <= rst or isReset; -- resetAndClear: pendingWorkReqScanCntrl.clear + + --------------------------------------------------------------------------- + -- Status methods (combinational Moore outputs from registered state) + --------------------------------------------------------------------------- + hasRetryErr <= '1' when r.retryCntrlState = RETRY_CNTRL_ST_RETRY_LIMIT_EXC_S else '0'; + isRetryDone <= '1' when r.retryCntrlState = RETRY_CNTRL_ST_NOT_RETRY_S else '0'; + isRetrying <= '1' when r.retryHandleState = RETRY_HANDLE_ST_WAIT_RETRY_DONE_S else '0'; + + --------------------------------------------------------------------------- + -- Method handshakes (external put/get faces; constant w.r.t. r) + --------------------------------------------------------------------------- + -- resetRetryCntAndTimeOutBySQ : Action put, guard isStableRTS + notFull + resetReqReady <= isStableRTS and rrqNotFull; + rrqWrEn <= resetReqValid and isStableRTS and rrqNotFull; + rrqDin(0) <= resetReqData; + -- srvPort.request : Put#(RetryReq) + srvReqReady <= xrqNotFull; + xrqWrEn <= srvReqValid and xrqNotFull; + xrqDin <= srvReqData; + -- notifyTimeOut2SQ : Get#(TimeOutNotification) + timeOutNotifValid <= tnqValid; + timeOutNotifData <= tnqDout(0); + tnqRdEn <= timeOutNotifGetEn; + -- srvPort.response : Get#(RetryResp) + srvRespValid <= rsqValid; + srvRespData <= rsqDout(0); + rsqRdEn <= srvRespGetEn; + + --------------------------------------------------------------------------- + -- 11 SURF Fifo instances (all FWFT/sync/block, ADDR_WIDTH_G=4) + --------------------------------------------------------------------------- + U_ResetReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => rrqWrEn, din => rrqDin, + not_full => rrqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rrqRdEn, dout => rrqDout, valid => rrqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_TimeOutNotificationQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => 4) + port map ( + rst => tnqClr, wr_clk => clk, wr_en => tnqWrEn, din => tnqDin, + not_full => tnqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => tnqRdEn, dout => tnqDout, valid => tnqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_RetryReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 97, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => xrqWrEn, din => xrqDin, + not_full => xrqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => xrqRdEn, dout => xrqDout, valid => xrqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_RetryRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => rsqWrEn, din => rsqDin, + not_full => rsqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rsqRdEn, dout => rsqDout, valid => rsqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_ResetTimeOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => rtqWrEn, din => rtqDin, + not_full => rtqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rtqRdEn, dout => rtqDout, valid => rtqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_ResetRetryCntQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => rcqWrEn, din => rcqDin, + not_full => rcqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rcqRdEn, dout => rcqDout, valid => rcqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_TimeOutTriggerQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => ttqWrEn, din => ttqDin, + not_full => ttqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => ttqRdEn, dout => ttqDout, valid => ttqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_RetryNotificationQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 98, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => rnqWrEn, din => rnqDin, + not_full => rnqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => rnqRdEn, dout => rnqDout, valid => rnqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_RetryActionQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 98, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => raqWrEn, din => raqDin, + not_full => raqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => raqRdEn, dout => raqDout, valid => raqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_UpdateRetryCntQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 4, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => urqWrEn, din => urqDin, + not_full => urqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => urqRdEn, dout => urqDout, valid => urqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + U_PrepareRetryRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 4, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, wr_clk => clk, wr_en => prqWrEn, din => prqDin, + not_full => prqNotFull, full => open, wr_ack => open, overflow => open, + prog_full => open, almost_full => open, wr_data_count => open, + rd_clk => clk, rd_en => prqRdEn, dout => prqDout, valid => prqValid, + underflow => open, prog_empty => open, almost_empty => open, + empty => open, rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, isReset, isERR, isStableRTS, isRTR2RTS, + getMaxRetryCnt, getMaxRnrCnt, getMaxTimeOut, getMinRnrTimer, + getPMTU, pendingWorkReqNotEmpty, scanGetHead, scanIsScanDone, + rrqValid, rrqDout, rcqValid, rcqNotFull, rcqDout, + xrqValid, xrqDout, rtqValid, rtqNotFull, + ttqValid, ttqNotFull, ttqDout, + rnqValid, rnqDout, rnqNotFull, raqValid, raqDout, raqNotFull, + urqValid, urqDout, urqNotFull, prqValid, prqDout, prqNotFull, + tnqNotFull, rsqNotFull) is + variable v : RegType; + -- recvRetryReq + variable enqNotif : boolean; + -- handleNotified + variable hasTimeOut : boolean; + variable hasRetry : boolean; + variable timeoutMaybe : slv(97 downto 0); + -- handleRetryAction + variable reason : slv(2 downto 0); + variable updCntDin : slv(3 downto 0); + -- handleRetryCntUpdate + variable hRetryErr : sl; + variable exceed : boolean; + variable nextCtrl : RetryCntrlStateType; + -- handle FSM + variable rnrTimerV : slv(4 downto 0); + variable startPsnV : slv(23 downto 0); + variable retryStartV : slv(23 downto 0); + variable modHead : slv(678 downto 0); + begin + v := r; + + -- default FIFO/scan drives (comb-driven only; method faces are concurrent) + rrqRdEn <= '0'; + tnqWrEn <= '0'; tnqDin <= (others => '0'); + xrqRdEn <= '0'; + rsqWrEn <= '0'; rsqDin <= (others => '0'); + rtqWrEn <= '0'; rtqRdEn <= '0'; rtqDin <= (others => '0'); + rcqWrEn <= '0'; rcqRdEn <= '0'; rcqDin <= (others => '0'); + ttqWrEn <= '0'; ttqRdEn <= '0'; ttqDin <= (others => '0'); + rnqWrEn <= '0'; rnqRdEn <= '0'; rnqDin <= (others => '0'); + raqWrEn <= '0'; raqRdEn <= '0'; raqDin <= (others => '0'); + urqWrEn <= '0'; urqRdEn <= '0'; urqDin <= (others => '0'); + prqWrEn <= '0'; prqRdEn <= '0'; prqDin <= (others => '0'); + scanStop <= '0'; scanStart <= '0'; + scanPreScanStart <= '0'; scanPreScanRestart <= '0'; + scanModifyHeadValid <= '0'; scanModifyHeadData <= (others => '0'); + + ---------------------------------------------------------------------- + -- BLOCK 1 — detection pipeline (gated isStableRTS); no state register. + -- Each rule is independent and FIFO-decoupled. + ---------------------------------------------------------------------- + if (isStableRTS = '1') then + + -- recvResetReq: deq resetReqQ; enq resetTimeOutQ (+ resetRetryCntQ on + -- RESET_CNT). Atomicity: all enq targets must be notFull to fire. + if (rrqValid = '1') and (rtqNotFull = '1') and + ((rrqDout(0) = RESET_TIMEOUT_C) or (rcqNotFull = '1')) then + rrqRdEn <= '1'; + rtqWrEn <= '1'; rtqDin <= "1"; -- resetTimeOut = True + if (rrqDout(0) = RESET_CNT_TIMEOUT_C) then + rcqWrEn <= '1'; rcqDin <= "1"; -- resetRetryCnt = True + end if; + end if; + + -- recvRetryReq: retry has priority over reset-retry-cnt. + enqNotif := (rcqValid = '1') or (xrqValid = '1'); + if (not enqNotif) or (rnqNotFull = '1') then + if (rcqValid = '1') then rcqRdEn <= '1'; end if; + if (xrqValid = '1') then xrqRdEn <= '1'; end if; + if enqNotif then + rnqWrEn <= '1'; + if (xrqValid = '1') then + rnqDin <= '1' & xrqDout; -- Valid(retryReqQ.first) + else + rnqDin <= (others => '0'); -- Invalid + end if; + end if; + end if; + + -- checkTimeOut: timeout down-counter / trigger. + if (rtqValid = '1') or (r.retryCntrlState /= RETRY_CNTRL_ST_NOT_RETRY_S) then + -- resetTimeOutCntInternal + v.timeOutCnt := getTimeOutValue(getMaxTimeOut); + v.disableTimeOut := '1' when (getMaxTimeOut = "00000") else '0'; + v.isTimeOutCntHighPartZero := '0'; + v.isTimeOutCntLowPartZero := '0'; + if (rtqValid = '1') then rtqRdEn <= '1'; end if; + elsif (r.disableTimeOut = '0') and (pendingWorkReqNotEmpty = '1') then + if (r.isTimeOutCntHighPartZero = '1') and (r.isTimeOutCntLowPartZero = '1') then + if (ttqNotFull = '1') then + ttqWrEn <= '1'; ttqDin <= "1"; -- triggerTimeOut = True + v.timeOutCnt := getTimeOutValue(getMaxTimeOut); + v.disableTimeOut := '1' when (getMaxTimeOut = "00000") else '0'; + v.isTimeOutCntHighPartZero := '0'; + v.isTimeOutCntLowPartZero := '0'; + end if; + else + v.timeOutCnt := slv(unsigned(r.timeOutCnt) - 1); + -- isZero4LargeBits(timeOutCntReg) on the CURRENT value (BSV) + v.isTimeOutCntHighPartZero := '1' when (unsigned(r.timeOutCnt(TIMEOUT_W_C-1 downto 21)) = 0) else '0'; + v.isTimeOutCntLowPartZero := '1' when (unsigned(r.timeOutCnt(20 downto 0)) = 0) else '0'; + end if; + end if; + + -- handleNotifiedRetryAndTimeOut: retry req overrides synthesized timeout. + hasTimeOut := (ttqValid = '1'); + hasRetry := (rnqValid = '1'); + timeoutMaybe := (others => '0'); + timeoutMaybe(97) := '1'; -- Valid + timeoutMaybe(8 downto 6) := RR_TIMEOUT_C; -- retryReason = TIMEOUT + if (not (hasTimeOut or hasRetry)) or (raqNotFull = '1') then + if hasTimeOut then ttqRdEn <= '1'; end if; + if hasRetry then rnqRdEn <= '1'; end if; + if (hasTimeOut or hasRetry) then + raqWrEn <= '1'; + if hasRetry then + raqDin <= rnqDout; -- Valid(retryReq) passthrough + else + raqDin <= timeoutMaybe; + end if; + end if; + end if; + + -- handleRetryAction: latch retry context, push Maybe#(RetryReason). + if (raqValid = '1') and (urqNotFull = '1') then + raqRdEn <= '1'; + updCntDin := (others => '0'); -- Invalid + if (raqDout(97) = '1') then -- isValid(maybeReq) + reason := raqDout(8 downto 6); + if (reason /= RR_TIMEOUT_C) then + v.retryWorkReqId := raqDout(96 downto 33); + v.retryStartPsn := raqDout(32 downto 9); + if (reason = RR_RNR_C) then + v.retryRnrTimer := raqDout(4 downto 0); -- unwrap(retryRnrTimer) + end if; + end if; + v.retryReason := reason; + updCntDin := '1' & reason; -- Valid(reason) + end if; + urqWrEn <= '1'; urqDin <= updCntDin; + end if; + + -- sendRetryResp: emit response on timeOutNotificationQ or retryRespQ. + if (prqValid = '1') then + reason := prqDout(2 downto 0); + if (reason = RR_TIMEOUT_C) then + if (tnqNotFull = '1') then + prqRdEn <= '1'; + tnqWrEn <= '1'; + if (prqDout(3) = '1') then tnqDin <= (0 => TIMEOUT_ERR_C); + else tnqDin <= (0 => TIMEOUT_RETRY_C); end if; + end if; + else + if (rsqNotFull = '1') then + prqRdEn <= '1'; + rsqWrEn <= '1'; + if (prqDout(3) = '1') then rsqDin <= (0 => RETRY_LIMIT_EXC_C); + else rsqDin <= (0 => RECV_RETRY_REQ_C); end if; + end if; + end if; + end if; + + end if; -- isStableRTS (Block 1) + + ---------------------------------------------------------------------- + -- BLOCK 3 — retry-handle FSM (gated isStableRTS & !pause). Placed before + -- the CReg port1 write; touches retryHandleState only. + ---------------------------------------------------------------------- + if (isStableRTS = '1') and (r.pauseRetryHandle = '0') then + case r.retryHandleState is + when RETRY_HANDLE_ST_START_PRE_RETRY_S => + if (r.retryReason = RR_RNR_C) then + v.retryHandleState := RETRY_HANDLE_ST_RNR_CHECK_S; + else + v.retryHandleState := RETRY_HANDLE_ST_CHECK_PARTIAL_RETRY_WR_S; + end if; + if (scanIsScanDone = '1') then scanPreScanStart <= '1'; + else scanPreScanRestart <= '1'; end if; + + when RETRY_HANDLE_ST_RNR_CHECK_S => + if (unsigned(r.retryRnrTimer) > unsigned(getMinRnrTimer)) then + rnrTimerV := r.retryRnrTimer; + else + rnrTimerV := getMinRnrTimer; + end if; + v.rnrWaitCnt := slv(to_unsigned(getRnrTimeOutValue(rnrTimerV), RNR_WAIT_W_C)); + v.isRnrWaitCntZero := '0'; + v.retryHandleState := RETRY_HANDLE_ST_RNR_WAIT_S; + + when RETRY_HANDLE_ST_RNR_WAIT_S => + if (r.isRnrWaitCntZero = '1') then + v.retryHandleState := RETRY_HANDLE_ST_CHECK_PARTIAL_RETRY_WR_S; + else + v.rnrWaitCnt := slv(unsigned(r.rnrWaitCnt) - 1); + v.isRnrWaitCntZero := '1' when (unsigned(r.rnrWaitCnt) = 1) else '0'; -- isOne + end if; + + when RETRY_HANDLE_ST_CHECK_PARTIAL_RETRY_WR_S => + startPsnV := scanGetHead(76 downto 53); -- head.startPSN.val + if (r.retryReason = RR_TIMEOUT_C) then + retryStartV := startPsnV; + else + retryStartV := r.retryStartPsn; + end if; + v.psnDiff := calcPsnDiff(retryStartV, startPsnV); + v.retryHandleState := RETRY_HANDLE_ST_MODIFY_PARTIAL_RETRY_WR_S; + + when RETRY_HANDLE_ST_MODIFY_PARTIAL_RETRY_WR_S => + modHead := scanGetHead; + modHead(509 downto 478) := lenSubPsn (scanGetHead(509 downto 478), r.psnDiff, getPMTU); -- wr.len + modHead(477 downto 414) := addrAddPsn(scanGetHead(477 downto 414), r.psnDiff, getPMTU); -- wr.laddr + modHead(605 downto 542) := addrAddPsn(scanGetHead(605 downto 542), r.psnDiff, getPMTU); -- wr.raddr + if (r.retryReason /= RR_TIMEOUT_C) then + modHead(77) := '1'; -- startPSN tag = Valid + modHead(76 downto 53) := r.retryStartPsn; + end if; + scanModifyHeadValid <= '1'; + scanModifyHeadData <= modHead; + v.retryHandleState := RETRY_HANDLE_ST_START_RETRY_S; + + when RETRY_HANDLE_ST_START_RETRY_S => + scanStart <= '1'; + v.retryHandleState := RETRY_HANDLE_ST_WAIT_RETRY_DONE_S; + + when RETRY_HANDLE_ST_WAIT_RETRY_DONE_S => + if (scanIsScanDone = '1') then + v.retryHandleState := RETRY_HANDLE_ST_NOT_RETRY_S; + end if; + + when others => -- NOT_RETRY_S idle + null; + end case; + end if; + + ---------------------------------------------------------------------- + -- BLOCK 2 — retry-control FSM port0 writers (initRetry, waitRetryFinish) + -- + stopScanQ. Applied BEFORE the CReg port1 write below. + ---------------------------------------------------------------------- + -- initRetry (port0 -> WAIT_RETRY_DONE) + if (isStableRTS = '1') and (r.pauseRetryHandle = '1') and + (r.retryCntrlState = RETRY_CNTRL_ST_INIT_RETRY_S) then + v.pauseRetryHandle := '0'; + v.retryHandleState := RETRY_HANDLE_ST_START_PRE_RETRY_S; + v.retryCntrlState := RETRY_CNTRL_ST_WAIT_RETRY_DONE_S; + end if; + + -- waitRetryFinish (port0 -> NOT_RETRY) + if (isStableRTS = '1') and + (r.retryCntrlState = RETRY_CNTRL_ST_WAIT_RETRY_DONE_S) and + (r.retryHandleState = RETRY_HANDLE_ST_WAIT_RETRY_DONE_S) and + (scanIsScanDone = '1') then + v.retryCntrlState := RETRY_CNTRL_ST_NOT_RETRY_S; + end if; + + -- stopScanQ (no state change) + if (isERR = '1') or + ((r.pauseRetryHandle = '1') and (r.retryCntrlState = RETRY_CNTRL_ST_RETRY_LIMIT_EXC_S)) then + scanStop <= '1'; + end if; + + ---------------------------------------------------------------------- + -- handleRetryCntUpdate — CReg(2) port1 write (applied LAST; overrides the + -- port0 writers above). Gated isStableRTS & !pause & updateRetryCntQ.valid. + ---------------------------------------------------------------------- + if (isStableRTS = '1') and (r.pauseRetryHandle = '0') and (urqValid = '1') then + if (urqDout(3) = '1') then -- Valid(reason) + if (prqNotFull = '1') then -- prepareRetryRespQ.enq atomicity + reason := urqDout(2 downto 0); + urqRdEn <= '1'; + v.pauseRetryHandle := '1'; + -- decRetryCntByReason (reads current r counts) + if (r.disableRetryCnt = '0') then + if (reason = RR_RNR_C) then + if (r.rnrCnt /= "000") then v.rnrCnt := slv(unsigned(r.rnrCnt) - 1); end if; + elsif (reason = RR_SEQ_ERR_C) or (reason = RR_IMPLICIT_C) or (reason = RR_TIMEOUT_C) then + if (r.retryCnt /= "000") then v.retryCnt := slv(unsigned(r.retryCnt) - 1); end if; + end if; + end if; + -- retryCntExceedLimit + exceed := false; + if (reason = RR_RNR_C) then + exceed := (r.rnrCnt = "000"); + elsif (reason = RR_SEQ_ERR_C) or (reason = RR_IMPLICIT_C) or (reason = RR_TIMEOUT_C) then + exceed := (r.retryCnt = "000"); + end if; + -- hasRetryErr: port1 read sees the same-cycle port0 update in v + hRetryErr := '0'; + if (v.retryCntrlState = RETRY_CNTRL_ST_RETRY_LIMIT_EXC_S) then hRetryErr := '1'; end if; + nextCtrl := RETRY_CNTRL_ST_INIT_RETRY_S; + if exceed then + nextCtrl := RETRY_CNTRL_ST_RETRY_LIMIT_EXC_S; + hRetryErr := '1'; + end if; + v.retryCntrlState := nextCtrl; -- port1 write (overrides port0) + prqWrEn <= '1'; + prqDin <= hRetryErr & reason; -- tuple2(hasRetryErr, reason) + end if; + else -- Invalid -> resetRetryCntInternal + urqRdEn <= '1'; + v.retryCnt := getMaxRetryCnt; + v.rnrCnt := getMaxRnrCnt; + v.disableRetryCnt := '1' when (getMaxRetryCnt = INFINITE_RETRY_C) else '0'; + end if; + end if; + + ---------------------------------------------------------------------- + -- initRetryCntAndTimeOutTimer (isRTR2RTS): reload counters/timers. + -- timeOutNotificationQ cleared via tnqClr. + ---------------------------------------------------------------------- + if (isRTR2RTS = '1') then + v.retryCnt := getMaxRetryCnt; + v.rnrCnt := getMaxRnrCnt; + v.disableRetryCnt := '1' when (getMaxRetryCnt = INFINITE_RETRY_C) else '0'; + v.timeOutCnt := getTimeOutValue(getMaxTimeOut); + v.disableTimeOut := '1' when (getMaxTimeOut = "00000") else '0'; + v.isTimeOutCntHighPartZero := '0'; + v.isTimeOutCntLowPartZero := '0'; + end if; + + ---------------------------------------------------------------------- + -- resetAndClear (isReset): state regs -> NOT_RETRY, pause -> 0 + -- (fire_when_enabled; FIFOs/scan cleared via fifoClr/scanClear). + ---------------------------------------------------------------------- + if (isReset = '1') then + v.retryCntrlState := RETRY_CNTRL_ST_NOT_RETRY_S; + v.retryHandleState := RETRY_HANDLE_ST_NOT_RETRY_S; + v.pauseRetryHandle := '0'; + end if; + + -- synchronous (FPGA) reset + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/RoceConfigurator.vhd b/ethernet/RoCEv2/rtl/RoceConfigurator.vhd deleted file mode 100755 index 40551b4c9a..0000000000 --- a/ethernet/RoCEv2/rtl/RoceConfigurator.vhd +++ /dev/null @@ -1,168 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: RoCEv2 Configuration -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiLitePkg.all; -use surf.AxiStreamPkg.all; - -entity RoceConfigurator is - generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset - RST_ASYNC_G : boolean := false); - port ( - -- Clock and Reset - clk : in sl; - rst : in sl; - -- RoCE Metadata AXI stream Interface - mAxisMetaDataReqMaster : out AxiStreamMasterType; - mAxisMetaDataReqSlave : in AxiStreamSlaveType; - sAxisMetaDataRespMaster : in AxiStreamMasterType; - sAxisMetaDataRespSlave : out AxiStreamSlaveType; - -- AXI-Lite Interface - axilReadMaster : in AxiLiteReadMasterType; - axilReadSlave : out AxiLiteReadSlaveType; - axilWriteMaster : in AxiLiteWriteMasterType; - axilWriteSlave : out AxiLiteWriteSlaveType); -end entity RoceConfigurator; - -architecture rtl of RoceConfigurator is - - type StateType is ( - IDLE_S, - DUMP_CONFIG_S, - GET_RESPONSE_S); - - type RegType is record - -- AXI-Lite Interface - metaDataIsSet : sl; - metaDataTx : slv(302 downto 0); - axilReadSlave : AxiLiteReadSlaveType; - axilWriteSlave : AxiLiteWriteSlaveType; - -- RoCE Metadata AXI stream Interface - metaDataIsReady : sl; - metaDataRx : slv(275 downto 0); - txMaster : AxiStreamMasterType; - rxSlave : AxiStreamSlaveType; - state : StateType; - end record RegType; - - constant REG_INIT_C : RegType := ( - -- AXI-Lite Interface - metaDataIsSet => '0', - metaDataTx => (others => '0'), - axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, - axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, - -- RoCE Metadata AXI stream Interface - metaDataIsReady => '0', - metaDataRx => (others => '0'), - txMaster => AXI_STREAM_MASTER_INIT_C, - rxSlave => AXI_STREAM_SLAVE_INIT_C, - state => IDLE_S); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - -begin - - comb : process (axilReadMaster, axilWriteMaster, mAxisMetaDataReqSlave, r, - rst, sAxisMetaDataRespMaster) is - variable v : RegType; - variable axilEp : AxiLiteEndPointType; - begin - -- Latch the current value - v := r; - - ---------------------------------------------------------------------------------- - -- AXI-Lite Interface - ---------------------------------------------------------------------------------- - - -- Determine the transaction type - axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); - - -- Gen registers - axiSlaveRegister (axilEp, x"F00", 0, v.metaDataIsSet); - axiSlaveRegister (axilEp, x"F04", 0, v.metaDataTx); - axiSlaveRegisterR(axilEp, x"F00", 1, r.metaDataIsReady); - axiSlaveRegisterR(axilEp, x"F2C", 0, r.metaDataRx); - - -- Closeout the transaction - axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); - - ---------------------------------------------------------------------------------- - -- RoCE Metadata AXI stream Interface - ---------------------------------------------------------------------------------- - - -- AXI stream flow control - v.rxSlave.tReady := '0'; - if mAxisMetaDataReqSlave.tReady = '1' then - v.txMaster.tValid := '0'; - end if; - - case r.state is - ------------------------------------------------------------------------- - when IDLE_S => - -- Check for rising edge event - if (r.metaDataIsSet = '0') and (v.metaDataIsSet = '1') then - v.metaDataIsReady := '0'; - v.state := DUMP_CONFIG_S; - end if; - ----------------------------------------------------------------------- - when DUMP_CONFIG_S => - v.txMaster.tData(302 downto 0) := r.metaDataTx; - v.txMaster.tValid := '1'; - if mAxisMetaDataReqSlave.tReady = '1' then - v.state := GET_RESPONSE_S; - end if; - ----------------------------------------------------------------------- - when GET_RESPONSE_S => - if sAxisMetaDataRespMaster.tValid = '1' then - v.rxSlave.tReady := '1'; - v.metaDataRx := sAxisMetaDataRespMaster.tData(275 downto 0); - v.metaDataIsReady := '1'; - v.state := IDLE_S; - end if; - ----------------------------------------------------------------------- - end case; - - -- Outputs - axilWriteSlave <= r.axilWriteSlave; - axilReadSlave <= r.axilReadSlave; - sAxisMetaDataRespSlave <= v.rxSlave; - mAxisMetaDataReqMaster <= r.txMaster; - - -- Reset - if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then - v := REG_INIT_C; - end if; - - -- Register update - rin <= v; - - end process comb; - - seq : process (clk, rst) is - begin - if (RST_ASYNC_G and rst = RST_POLARITY_G) then - r <= REG_INIT_C after TPD_G; - elsif rising_edge(clk) then - r <= rin after TPD_G; - end if; - end process seq; - -end rtl; diff --git a/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd b/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd old mode 100755 new mode 100644 index ca7f829cb3..f2fc4566f5 --- a/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd +++ b/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd @@ -1,7 +1,38 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: RoCEv2 Configuration +-- Provenance : HAND-WRITTEN integration wrapper (not BSV-derived). Wraps the +-- Stage-5-verified out/04-vhdl/TransportLayer.vhd (BSV +-- mkTransportLayer, src-bsv/TransportLayer.bsv:76-185) with: +-- * standard SURF AXI-Stream on the network-facing dataStream +-- in/out (BYTE-SWAPPED to AXI lane order: first wire byte = +-- tData lane 0 / tKeep(0); isFirst -> SSI SOF on tUser; +-- isLast -> tLast). External beats are 16-byte +-- EMAC_AXIS_CONFIG_C format, directly connectable to the +-- server/client stream ports of surf.UdpEngineWrapper +-- (surf/ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd): +-- sAxisDataStream* <- obServerMasters/obServerSlaves, +-- mAxisDataStream* -> ibServerMasters/ibServerSlaves. +-- Two surf.AxiStreamResize instances convert 16 <-> 32 +-- bytes to/from the internal BLUE_DATA_STREAM_CONFIG_C +-- 32-byte RoCE beat; +-- * RocePkg TYPED RECORD ports on every other stream interface +-- (RoceWorkReqMasterType/SlaveType etc., valid/ready +-- handshake per record pair — style/examples/RocePkg.vhd +-- lineage); +-- * AXI-Lite on the MetaData server interface, one register +-- per struct field (see RoceMetaDataAxil.vhd for the map). +------------------------------------------------------------------------------- +-- Conventions: +-- * The typed-record ports carry the BSV-faithful structs; to attach an +-- AXI-Stream fabric to one of them, use the RocePkg conversion functions +-- OUTSIDE this entity (ToAxiStream / AxiStreamTo). +-- * Pure combinational mapping - no FIFOs (the DUT already buffers) - +-- except the two AxiStreamResize width converters on the wire streams +-- (one register stage each, ready/valid flow control preserved). +-- * The DUT's dataStreamOut/workComp*/dmaReadReq/dmaWriteReq FWFT faces: +-- master.valid/tValid <= DUT valid (never a function of ready); +-- DUT rdEn <= slave.ready/tReady. ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -14,338 +45,247 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; library surf; use surf.StdRtlPkg.all; use surf.AxiStreamPkg.all; use surf.AxiLitePkg.all; -use surf.SsiPkg.all; -use surf.RocePkg.all; +use surf.EthMacPkg.all; + +use work.RocePkg.all; entity RoceEngineWrapper is generic ( - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset - EXT_ROCE_CONFIG_G : boolean := false); + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + MAX_QP_G : positive := 4; -- power of 2, >= 1 (TransportLayer proviso) + -- Resource-pruning generics (pass-through to TransportLayer; all true = + -- full engine, identical to the verified netlist; at least one of + -- EN_TX_G/EN_RX_G must be true): + -- EN_TX_G=false : no requester (SQ) — engine cannot originate RDMA + -- requests; sWorkReq is refused (ready stays '0'); + -- mWorkCompSq never fires. + -- EN_RX_G=false : no responder (RQ) — engine cannot serve incoming + -- remote requests (they are dropped at the packet + -- buffer); sRecvReq is refused; mWorkCompRq never + -- fires. ACK/NAK reception for the engine's own + -- requests is NOT affected. + -- EN_READ_G=false : no RDMA READ / atomic support on either side. + -- SOFTWARE CONTRACT: never post READ or atomic work + -- requests; incoming READ/atomic requests get NAK + -- (invalid request). RDMA WRITE / WRITE_WITH_IMM / + -- SEND are unaffected. + -- Target config for a pure RDMA-WRITE requester: + -- EN_TX_G=true, EN_RX_G=false, EN_READ_G=false. + EN_TX_G : boolean := true; + EN_RX_G : boolean := true; + EN_READ_G : boolean := true); port ( clk : in sl; - rst : in sl; - -- Work Requests and Comps - workReqMaster : in RoceWorkReqMasterType; - workReqSlave : out RoceWorkReqSlaveType; - workCompMaster : out RoceWorkCompMasterType; - workCompSlave : in RoceWorkCompSlaveType; - -- Interface to UDP Engine - obUdpMaster : in AxiStreamMasterType; - obUdpSlave : out AxiStreamSlaveType; - ibUdpMaster : out AxiStreamMasterType; - ibUdpSlave : in AxiStreamSlaveType; - -- MetaData Config Bus - sAxisMetaDataMaster : in AxiStreamMasterType; - sAxisMetaDataSlave : out AxiStreamSlaveType; - mAxisMetaDataMaster : out AxiStreamMasterType; - mAxisMetaDataSlave : in AxiStreamSlaveType; - -- AXI-Lite Interface - axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + rst : in sl := not RST_POLARITY_G; + -- RoCE wire stream in (RX; 16-byte EMAC_AXIS_CONFIG_C beats, + -- byte-swapped lane order; connect to UdpEngineWrapper obServer*) + sAxisDataStreamMaster : in AxiStreamMasterType; + sAxisDataStreamSlave : out AxiStreamSlaveType; + -- RoCE wire stream out (TX; 16-byte EMAC_AXIS_CONFIG_C beats, + -- byte-swapped lane order; connect to UdpEngineWrapper ibServer*) + mAxisDataStreamMaster : out AxiStreamMasterType; + mAxisDataStreamSlave : in AxiStreamSlaveType; + -- WorkReq / RecvReq inputs + sWorkReqMaster : in RoceWorkReqMasterType; + sWorkReqSlave : out RoceWorkReqSlaveType; + sRecvReqMaster : in RoceRecvReqMasterType; + sRecvReqSlave : out RoceRecvReqSlaveType; + -- Work completion outputs + mWorkCompRqMaster : out RoceWorkCompMasterType; + mWorkCompRqSlave : in RoceWorkCompSlaveType; + mWorkCompSqMaster : out RoceWorkCompMasterType; + mWorkCompSqSlave : in RoceWorkCompSlaveType; + -- DMA read client + mDmaReadReqMaster : out RoceDmaReadReqMasterType; + mDmaReadReqSlave : in RoceDmaReadReqSlaveType; + sDmaReadRespMaster : in RoceDmaReadRespMasterType; + sDmaReadRespSlave : out RoceDmaReadRespSlaveType; + -- DMA write client + mDmaWriteReqMaster : out RoceDmaWriteReqMasterType; + mDmaWriteReqSlave : in RoceDmaWriteReqSlaveType; + sDmaWriteRespMaster : in RoceDmaWriteRespMasterType; + sDmaWriteRespSlave : out RoceDmaWriteRespSlaveType; + -- MetaData server as AXI-Lite registers (RoceMetaDataAxil map) + axilReadMaster : in AxiLiteReadMasterType; axilReadSlave : out AxiLiteReadSlaveType; - axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteMaster : in AxiLiteWriteMasterType; axilWriteSlave : out AxiLiteWriteSlaveType; - -- DMA Interface - dmaReadRespMaster : in RoceDmaReadRespMasterType; - dmaReadRespSlave : out RoceDmaReadRespSlaveType; - dmaReadReqMaster : out RoceDmaReadReqMasterType; - dmaReadReqSlave : in RoceDmaReadReqSlaveType); -end RoceEngineWrapper; + -- metadata completion interrupt (1-cycle pulse on DONE) + mdDoneIrq : out sl); +end entity RoceEngineWrapper; -architecture mapping of RoceEngineWrapper is +architecture rtl of RoceEngineWrapper is - component mkAxiSTransportLayer - port ( - CLK : in std_logic; - RST_N : in std_logic; - s_work_req_valid : in std_logic; - s_work_req_id : in std_logic_vector(63 downto 0); - s_work_req_op_code : in std_logic_vector(3 downto 0); - s_work_req_flags : in std_logic_vector(4 downto 0); - s_work_req_raddr : in std_logic_vector(63 downto 0); - s_work_req_rkey : in std_logic_vector(31 downto 0); - s_work_req_len : in std_logic_vector(31 downto 0); - s_work_req_laddr : in std_logic_vector(63 downto 0); - s_work_req_lkey : in std_logic_vector(31 downto 0); - s_work_req_sqpn : in std_logic_vector(23 downto 0); - s_work_req_solicited : in std_logic; - s_work_req_comp : in std_logic_vector(64 downto 0); - s_work_req_swap : in std_logic_vector(64 downto 0); - s_work_req_imm_dt : in std_logic_vector(32 downto 0); - s_work_req_rkey_to_inv : in std_logic_vector(32 downto 0); - s_work_req_srqn : in std_logic_vector(24 downto 0); - s_work_req_dqpn : in std_logic_vector(24 downto 0); - s_work_req_qkey : in std_logic_vector(32 downto 0); - s_work_req_ready : out std_logic; - s_data_stream_tvalid : in std_logic; - s_data_stream_tdata : in std_logic_vector(255 downto 0); - s_data_stream_tkeep : in std_logic_vector(31 downto 0); - s_data_stream_tfirst : in std_logic; - s_data_stream_tlast : in std_logic; - s_data_stream_tready : out std_logic; - m_data_stream_tvalid : out std_logic; - m_data_stream_tdata : out std_logic_vector(255 downto 0); - m_data_stream_tkeep : out std_logic_vector(31 downto 0); - m_data_stream_tfirst : out std_logic; - m_data_stream_tlast : out std_logic; - m_data_stream_tready : in std_logic; - m_work_comp_sq_valid : out std_logic; - m_work_comp_sq_id : out std_logic_vector(63 downto 0); - m_work_comp_sq_op_code : out std_logic_vector(7 downto 0); - m_work_comp_sq_flags : out std_logic_vector(6 downto 0); - m_work_comp_sq_status : out std_logic_vector(4 downto 0); - m_work_comp_sq_len : out std_logic_vector(31 downto 0); - m_work_comp_sq_pkey : out std_logic_vector(15 downto 0); - m_work_comp_sq_qpn : out std_logic_vector(23 downto 0); - m_work_comp_sq_imm_dt : out std_logic_vector(32 downto 0); - m_work_comp_sq_rkey_to_inv : out std_logic_vector(32 downto 0); - m_work_comp_sq_ready : in std_logic; - s_meta_data_tvalid : in std_logic; - s_meta_data_tdata : in std_logic_vector(302 downto 0); - s_meta_data_tready : out std_logic; - m_meta_data_tvalid : out std_logic; - m_meta_data_tdata : out std_logic_vector(275 downto 0); - m_meta_data_tready : in std_logic; - m_dma_read_valid : out std_logic; - m_dma_read_initiator : out std_logic_vector(3 downto 0); - m_dma_read_sqpn : out std_logic_vector(23 downto 0); - m_dma_read_wr_id : out std_logic_vector(63 downto 0); - m_dma_read_start_addr : out std_logic_vector(63 downto 0); - m_dma_read_len : out std_logic_vector(12 downto 0); - m_dma_read_mr_idx : out std_logic; - m_dma_read_ready : in std_logic; - s_dma_read_valid : in std_logic; - s_dma_read_initiator : in std_logic_vector(3 downto 0); - s_dma_read_sqpn : in std_logic_vector(23 downto 0); - s_dma_read_wr_id : in std_logic_vector(63 downto 0); - s_dma_read_is_resp_err : in std_logic; - s_dma_read_data_stream : in std_logic_vector(289 downto 0); - s_dma_read_ready : out std_logic); - end component; + -- flat DUT ports + signal dataStreamInReady : sl; + signal workReqInReady : sl; + signal recvReqInReady : sl; + signal dataStreamOutValid : sl; + signal dataStreamOutData : slv(ROCE_DATA_STREAM_W_C-1 downto 0); + signal workCompRqValid : sl; + signal workCompRqData : slv(ROCE_WORK_COMP_W_C-1 downto 0); + signal workCompSqValid : sl; + signal workCompSqData : slv(ROCE_WORK_COMP_W_C-1 downto 0); + signal mdSrvReqValid : sl; + signal mdSrvReqData : slv(ROCE_MD_REQ_W_C-1 downto 0); + signal mdSrvReqReady : sl; + signal mdSrvRespValid : sl; + signal mdSrvRespData : slv(ROCE_MD_RESP_W_C-1 downto 0); + signal mdSrvRespReady : sl; + signal dmaReadReqValid : sl; + signal dmaReadReqData : slv(ROCE_DMA_RD_REQ_W_C-1 downto 0); + signal dmaReadRespReady : sl; + signal dmaWriteReqValid : sl; + signal dmaWriteReqData : slv(ROCE_DMA_WR_REQ_W_C-1 downto 0); + signal dmaWriteRespReady : sl; - signal roceRstN : sl; - signal obUdpRoceMaster_tValid : sl; - signal obUdpRoceMaster_tData : slv(255 downto 0); - signal obUdpRoceMaster_tKeep : slv(31 downto 0); - signal obUdpRoceMaster_tFirst : sl; - signal obUdpRoceMaster_tLast : sl; - signal obUdpRoceMaster_tUser : slv(1 downto 0); - signal obUdpRoceSlave_tReady : sl; - signal ibUdpRoceMaster_tValid : sl; - signal ibUdpRoceMaster_tData : slv(255 downto 0); - signal ibUdpRoceMaster_tKeep : slv(31 downto 0); - signal ibUdpRoceMaster_tFirst : sl; - signal ibUdpRoceMaster_tLast : sl; - signal ibUdpRoceMaster_tUser : slv(1 downto 0); - signal ibUdpRoceSlave_tReady : sl; + -- typed view of the DUT-side wire streams (RocePkg records) + signal dataStreamIn : RoceDataStreamMasterType; + signal dataStreamOut : RoceDataStreamMasterType; - signal obUdpRoceMaster : AxiStreamMasterType; - signal obUdpRoceSlave : AxiStreamSlaveType; - signal ibUdpRoceMaster : AxiStreamMasterType; - signal ibUdpRoceSlave : AxiStreamSlaveType; - - signal s_axisMetaDataReqMaster : AxiStreamMasterType; - signal s_axisMetaDataReqSlave : AxiStreamSlaveType; - signal s_axisMetaDataRespMaster : AxiStreamMasterType; - signal s_axisMetaDataRespSlave : AxiStreamSlaveType; - signal s_axisMetaDataReqMasterMux : AxiStreamMasterType; - signal s_axisMetaDataReqSlaveMux : AxiStreamSlaveType; - signal s_axisMetaDataRespMasterMux : AxiStreamMasterType; - signal s_axisMetaDataRespSlaveMux : AxiStreamSlaveType; + -- internal 32-byte (BLUE_DATA_STREAM_CONFIG_C) side of the width converters + signal roceRxAxisMaster : AxiStreamMasterType; + signal roceRxAxisSlave : AxiStreamSlaveType; + signal roceTxAxisMaster : AxiStreamMasterType; + signal roceTxAxisSlave : AxiStreamSlaveType; begin - roceRstN <= not rst when (RST_POLARITY_G = '1') else rst; - - ----------------------------------------------------------------------------- - -- Adjust Roce/SURF interface - ----------------------------------------------------------------------------- - AxiStreamResize_Inst : entity surf.RoceResizeAndSwap + --------------------------------------------------------------------------- + -- Wire stream RX: 16-byte UDP beats -> 32-byte RoCE beat -> raw DataStream + --------------------------------------------------------------------------- + U_RxResize : entity surf.AxiStreamResize generic map ( - SLAVE_AXI_CONFIG_G => SURF_DATA_STREAM_CONFIG_C, - MASTER_AXI_CONFIG_G => BLUE_DATA_STREAM_CONFIG_C, - SWAP_ENDIAN_G => true, - LITTLE_ENDIAN_G => false) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + SLAVE_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C, + MASTER_AXI_CONFIG_G => BLUE_DATA_STREAM_CONFIG_C) port map ( axisClk => clk, axisRst => rst, - sAxisMaster => obUdpMaster, - sAxisSlave => obUdpSlave, - mAxisMaster => obUdpRoceMaster, - mAxisSlave => obUdpRoceSlave); + sAxisMaster => sAxisDataStreamMaster, + sAxisSlave => sAxisDataStreamSlave, + mAxisMaster => roceRxAxisMaster, + mAxisSlave => roceRxAxisSlave); - AxiStreamResize_1 : entity surf.RoceResizeAndSwap + dataStreamIn <= AxiStreamToDataStream(roceRxAxisMaster); + roceRxAxisSlave <= ToAxiStreamSlave(dataStreamInReady); + + --------------------------------------------------------------------------- + -- Wire stream TX: raw DataStream -> 32-byte RoCE beat -> 16-byte UDP beats + --------------------------------------------------------------------------- + dataStreamOut <= SlvToDataStream(dataStreamOutValid, dataStreamOutData); + roceTxAxisMaster <= DataStreamToAxiStream(dataStreamOut); + + U_TxResize : entity surf.AxiStreamResize generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, SLAVE_AXI_CONFIG_G => BLUE_DATA_STREAM_CONFIG_C, - MASTER_AXI_CONFIG_G => SURF_DATA_STREAM_CONFIG_C, - SWAP_ENDIAN_G => true, - LITTLE_ENDIAN_G => false) + MASTER_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C) port map ( axisClk => clk, axisRst => rst, - sAxisMaster => ibUdpRoceMaster, - sAxisSlave => ibUdpRoceSlave, - mAxisMaster => ibUdpMaster, - mAxisSlave => ibUdpSlave); + sAxisMaster => roceTxAxisMaster, + sAxisSlave => roceTxAxisSlave, + mAxisMaster => mAxisDataStreamMaster, + mAxisSlave => mAxisDataStreamSlave); - ----------------------------------------------------------------------------- - -- IP Integrator - ----------------------------------------------------------------------------- - MasterAxiStreamIpIntegrator_Inst : entity surf.MasterAxiStreamIpIntegrator - generic map ( - TDATA_NUM_BYTES => TDATA_ROCE_NUM_BYTES_C) - port map ( - M_AXIS_ACLK => clk, - M_AXIS_ARESETN => roceRstN, - M_AXIS_TVALID => obUdpRoceMaster_tValid, - M_AXIS_TDATA => obUdpRoceMaster_tData, - M_AXIS_TKEEP => obUdpRoceMaster_tKeep, - M_AXIS_TLAST => obUdpRoceMaster_tLast, - M_AXIS_TUSER => obUdpRoceMaster_tUser, - M_AXIS_TREADY => obUdpRoceSlave_tReady, - axisMaster => obUdpRoceMaster, - axisSlave => obUdpRoceSlave); + --------------------------------------------------------------------------- + -- Typed-record <-> flat conversions (pure wiring via RocePkg functions) + --------------------------------------------------------------------------- + sWorkReqSlave <= (ready => workReqInReady); + sRecvReqSlave <= (ready => recvReqInReady); + sDmaReadRespSlave <= (ready => dmaReadRespReady); + sDmaWriteRespSlave <= (ready => dmaWriteRespReady); + + mWorkCompRqMaster <= SlvToWorkComp(workCompRqValid, workCompRqData); + mWorkCompSqMaster <= SlvToWorkComp(workCompSqValid, workCompSqData); + mDmaReadReqMaster <= SlvToDmaReadReq(dmaReadReqValid, dmaReadReqData); + mDmaWriteReqMaster <= SlvToDmaWriteReq(dmaWriteReqValid, dmaWriteReqData); - SlaveAxiStreamIpIntegrator_Inst : entity surf.SlaveAxiStreamIpIntegrator + --------------------------------------------------------------------------- + -- U_MetaDataAxil : AXI-Lite register bank <-> mdSrv server pair + --------------------------------------------------------------------------- + U_MetaDataAxil : entity surf.RoceMetaDataAxil generic map ( - TDATA_NUM_BYTES => TDATA_ROCE_NUM_BYTES_C) + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + MAX_QP_G => MAX_QP_G) port map ( - S_AXIS_ACLK => clk, - S_AXIS_ARESETN => roceRstN, - S_AXIS_TVALID => ibUdpRoceMaster_tValid, - S_AXIS_TDATA => ibUdpRoceMaster_tData, - S_AXIS_TKEEP => ibUdpRoceMaster_tKeep, - S_AXIS_TLAST => ibUdpRoceMaster_tLast, - S_AXIS_TUSER => ibUdpRoceMaster_tUser, - S_AXIS_TREADY => ibUdpRoceSlave_tReady, - axisMaster => ibUdpRoceMaster, - axisSlave => ibUdpRoceSlave); + clk => clk, + rst => rst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave, + mdSrvReqValid => mdSrvReqValid, + mdSrvReqData => mdSrvReqData, + mdSrvReqReady => mdSrvReqReady, + mdSrvRespValid => mdSrvRespValid, + mdSrvRespData => mdSrvRespData, + mdSrvRespReady => mdSrvRespReady, + mdDoneIrq => mdDoneIrq); - obUdpRoceMaster_tFirst <= obUdpRoceMaster_tUser(1); - ibUdpRoceMaster_tUser <= ibUdpRoceMaster_tFirst & '0'; - - ----------------------------------------------------------------------------- - -- RoCE engine wrapper - ----------------------------------------------------------------------------- - mkAxiSTransportLayer_1 : mkAxiSTransportLayer + --------------------------------------------------------------------------- + -- U_TransportLayer : the verified BSV-derived core + --------------------------------------------------------------------------- + U_TransportLayer : entity surf.TransportLayer + generic map ( + TPD_G => TPD_G, + MAX_QP_G => MAX_QP_G, + EN_TX_G => EN_TX_G, + EN_RX_G => EN_RX_G, + EN_READ_G => EN_READ_G) port map ( - CLK => clk, - RST_N => roceRstN, - s_work_req_valid => workReqMaster.valid, - s_work_req_id => workReqMaster.id, - s_work_req_op_code => workReqMaster.opCode, - s_work_req_flags => workReqMaster.flags, - s_work_req_raddr => workReqMaster.rAddr, - s_work_req_rkey => workReqMaster.rKey, - s_work_req_len => workReqMaster.len, - s_work_req_laddr => workReqMaster.lAddr, - s_work_req_lkey => workReqMaster.lKey, - s_work_req_sqpn => workReqMaster.sQpn, - s_work_req_solicited => workReqMaster.solicited, - s_work_req_comp => workReqMaster.comp, - s_work_req_swap => workReqMaster.swap, - s_work_req_imm_dt => workReqMaster.immDt, - s_work_req_rkey_to_inv => workReqMaster.rkeyToInv, - s_work_req_srqn => workReqMaster.srqn, - s_work_req_dqpn => workReqMaster.dQpn, - s_work_req_qkey => workReqMaster.qKey, - s_work_req_ready => workReqSlave.ready, - s_data_stream_tvalid => obUdpRoceMaster_tValid, - s_data_stream_tdata => obUdpRoceMaster_tData, - s_data_stream_tkeep => obUdpRoceMaster_tKeep, - s_data_stream_tfirst => obUdpRoceMaster_tFirst, - s_data_stream_tlast => obUdpRoceMaster_tLast, - s_data_stream_tready => obUdpRoceSlave_tReady, - m_data_stream_tvalid => ibUdpRoceMaster_tValid, - m_data_stream_tdata => ibUdpRoceMaster_tData, - m_data_stream_tkeep => ibUdpRoceMaster_tKeep, - m_data_stream_tfirst => ibUdpRoceMaster_tFirst, - m_data_stream_tlast => ibUdpRoceMaster_tLast, - m_data_stream_tready => ibUdpRoceSlave_tReady, - m_work_comp_sq_valid => workCompMaster.valid, - m_work_comp_sq_id => workCompMaster.id, - m_work_comp_sq_op_code => workCompMaster.opCode, - m_work_comp_sq_flags => workCompMaster.flags, - m_work_comp_sq_status => workCompMaster.status, - m_work_comp_sq_len => workCompMaster.len, - m_work_comp_sq_pkey => workCompMaster.pKey, - m_work_comp_sq_qpn => workCompMaster.qpn, - m_work_comp_sq_imm_dt => workCompMaster.immDt, - m_work_comp_sq_rkey_to_inv => workCompMaster.rkeyToInv, - m_work_comp_sq_ready => workCompSlave.ready, - s_meta_data_tvalid => s_axisMetaDataReqMasterMux.tValid, - s_meta_data_tdata => s_axisMetaDataReqMasterMux.tData(302 downto 0), - s_meta_data_tready => s_axisMetaDataReqSlaveMux.tReady, - m_meta_data_tvalid => s_axisMetaDataRespMasterMux.tValid, - m_meta_data_tdata => s_axisMetaDataRespMasterMux.tData(275 downto 0), - m_meta_data_tready => s_axisMetaDataRespSlaveMux.tReady, - m_dma_read_valid => dmaReadReqMaster.valid, - m_dma_read_initiator => dmaReadReqMaster.initiator, - m_dma_read_sqpn => dmaReadReqMaster.sQpn, - m_dma_read_wr_id => dmaReadReqMaster.wrId, - m_dma_read_start_addr => dmaReadReqMaster.startAddr, - m_dma_read_len => dmaReadReqMaster.len, - m_dma_read_mr_idx => dmaReadReqMaster.mrIdx, - m_dma_read_ready => dmaReadReqSlave.ready, - s_dma_read_valid => dmaReadRespMaster.valid, - s_dma_read_initiator => dmaReadRespMaster.initiator, - s_dma_read_sqpn => dmaReadRespMaster.sQpn, - s_dma_read_wr_id => dmaReadRespMaster.wrId, - s_dma_read_is_resp_err => dmaReadRespMaster.isRespErr, - s_dma_read_data_stream => dmaReadRespMaster.dataStream, - s_dma_read_ready => dmaReadRespSlave.ready); - - ----------------------------------------------------------------------------- - -- RoCE Metadata Configurator - ----------------------------------------------------------------------------- - ROCE_EXT_CONFIG_GEN : if EXT_ROCE_CONFIG_G generate - s_axisMetaDataReqMaster <= AXI_STREAM_MASTER_INIT_C; - s_axisMetaDataRespSlave <= AXI_STREAM_SLAVE_FORCE_C; - axilReadSlave <= AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; - axilWriteSlave <= AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C; - end generate ROCE_EXT_CONFIG_GEN; - - ROCE_INT_CONFIG_GEN : if not EXT_ROCE_CONFIG_G generate - RoceConfigurator_1 : entity surf.RoceConfigurator - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G) - port map ( - clk => clk, - rst => rst, - mAxisMetaDataReqMaster => s_axisMetaDataReqMaster, - mAxisMetaDataReqSlave => s_axisMetaDataReqSlave, - sAxisMetaDataRespMaster => s_axisMetaDataRespMaster, - sAxisMetaDataRespSlave => s_axisMetaDataRespSlave, - axilReadMaster => axilReadMaster, - axilReadSlave => axilReadSlave, - axilWriteMaster => axilWriteMaster, - axilWriteSlave => axilWriteSlave); - end generate ROCE_INT_CONFIG_GEN; - - ----------------------------------------------------------------------------- - -- Axi-Stream Metadata source selection - ----------------------------------------------------------------------------- - metaSel : process (mAxisMetaDataSlave, sAxisMetaDataMaster, - s_axisMetaDataReqMaster, s_axisMetaDataReqSlaveMux, - s_axisMetaDataRespMasterMux, s_axisMetaDataRespSlave) is - begin -- process metadata_source_select - if EXT_ROCE_CONFIG_G then - s_axisMetaDataReqMasterMux <= sAxisMetaDataMaster; - sAxisMetaDataSlave <= s_axisMetaDataReqSlaveMux; - mAxisMetaDataMaster <= s_axisMetaDataRespMasterMux; - s_axisMetaDataRespSlaveMux <= mAxisMetaDataSlave; - else - s_axisMetaDataReqMasterMux <= s_axisMetaDataReqMaster; - s_axisMetaDataReqSlave <= s_axisMetaDataReqSlaveMux; - s_axisMetaDataRespMaster <= s_axisMetaDataRespMasterMux; - s_axisMetaDataRespSlaveMux <= s_axisMetaDataRespSlave; - end if; - end process metaSel; + clk => clk, + rst => rst, + dataStreamInValid => dataStreamIn.valid, + dataStreamInData => DataStreamToSlv(dataStreamIn), + dataStreamInReady => dataStreamInReady, + workReqInValid => sWorkReqMaster.valid, + workReqInData => WorkReqToSlv(sWorkReqMaster), + workReqInReady => workReqInReady, + recvReqInValid => sRecvReqMaster.valid, + recvReqInData => RecvReqToSlv(sRecvReqMaster), + recvReqInReady => recvReqInReady, + dataStreamOutValid => dataStreamOutValid, + dataStreamOutData => dataStreamOutData, + dataStreamOutRdEn => roceTxAxisSlave.tReady, + workCompRqValid => workCompRqValid, + workCompRqData => workCompRqData, + workCompRqRdEn => mWorkCompRqSlave.ready, + workCompSqValid => workCompSqValid, + workCompSqData => workCompSqData, + workCompSqRdEn => mWorkCompSqSlave.ready, + mdSrvReqValid => mdSrvReqValid, + mdSrvReqData => mdSrvReqData, + mdSrvReqReady => mdSrvReqReady, + mdSrvRespValid => mdSrvRespValid, + mdSrvRespData => mdSrvRespData, + mdSrvRespReady => mdSrvRespReady, + dmaReadReqValid => dmaReadReqValid, + dmaReadReqData => dmaReadReqData, + dmaReadReqRd => mDmaReadReqSlave.ready, + dmaReadRespValid => sDmaReadRespMaster.valid, + dmaReadRespData => DmaReadRespToSlv(sDmaReadRespMaster), + dmaReadRespReady => dmaReadRespReady, + dmaWriteReqValid => dmaWriteReqValid, + dmaWriteReqData => dmaWriteReqData, + dmaWriteReqRd => mDmaWriteReqSlave.ready, + dmaWriteRespValid => sDmaWriteRespMaster.valid, + dmaWriteRespData => DmaWriteRespToSlv(sDmaWriteRespMaster), + dmaWriteRespReady => dmaWriteRespReady); -end mapping; +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/RoceMetaDataAxil.vhd b/ethernet/RoCEv2/rtl/RoceMetaDataAxil.vhd new file mode 100644 index 0000000000..bed725c1c5 --- /dev/null +++ b/ethernet/RoCEv2/rtl/RoceMetaDataAxil.vhd @@ -0,0 +1,443 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Provenance : HAND-WRITTEN integration bridge (not BSV-derived). Supersedes +-- the old style/examples/RoceConfigurator.vhd mechanism (single +-- 303/276-bit register + edge-detected go bit) with per-field +-- 32-bit registers and a GO-strobe / BUSY / DONE protocol. +-- Struct refs: src-bsv/MetaData.bsv (MetaDataReq/Resp:661-671, ReqPD/RespPD: +-- 253-263, ReqMR/RespMR:163-177), src-bsv/Controller.bsv +-- (ReqQP/RespQP:60-76), src-bsv/DataTypes.bsv (AttrQP:423-450, +-- QpCapacity:415-421, QpInitAttr:452-455). +------------------------------------------------------------------------------- +-- Register map (32-bit registers; each BSV struct field at bit 0 of its own +-- word; 64-bit laddr spans two consecutive words LO/HI). RW unless (RO). +-- +-- 0x000 CONTROL [0] GO (self-clearing strobe) [2:1] REQ_TYPE (00 PD, +-- 01 MR, 10 QP) +-- 0x004 STATUS (RO) [0] DONE [1] BUSY [2] ERR (sticky; GO while BUSY) +-- [4:3] RESP_TAG [5] RESP_SUCCESS +-- 0x008 VERSION (RO) [7:0] bridge version [15:8] MAX_QP_G +-- 0x00C SCRATCH RW scratchpad +-- --- PD request bank (ReqPD) --- +-- 0x100 PD_CTRL [0] allocOrNot +-- 0x104 PD_KEY [30:0] +-- 0x108 PD_HANDLER [31:0] (for dealloc) +-- --- MR request bank (ReqMR) --- +-- 0x200 MR_CTRL [0] allocOrNot [1] lkeyOrNot +-- 0x204 MR_LADDR_LO [31:0] 0x208 MR_LADDR_HI [63:32] +-- 0x20C MR_LEN [31:0] +-- 0x210 MR_ACC_FLAGS [7:0] +-- 0x214 MR_PD_HANDLER [31:0] +-- 0x218 MR_LKEY_PART [24:0] +-- 0x21C MR_RKEY_PART [24:0] +-- 0x220 MR_LKEY [31:0] 0x224 MR_RKEY [31:0] (for dereg) +-- --- QP request bank (ReqQP, full AttrQP coverage) --- +-- 0x300 QP_CTRL [1:0] reqType (00 CREATE, 01 DESTROY, 10 MODIFY, +-- 11 QUERY) [5:2] qpState [8:6] pmtu [12:9] qpType +-- [13] sqSigAll +-- 0x304 QP_PD_HANDLER [31:0] +-- 0x308 QP_QPN [23:0] +-- 0x30C QP_ATTR_MASK [25:0] +-- 0x310 QP_QKEY [31:0] +-- 0x314 QP_RQ_PSN [23:0] 0x318 QP_SQ_PSN [23:0] +-- 0x31C QP_DQPN [23:0] +-- 0x320 QP_ACCESS_FLAGS [7:0] +-- 0x324 QP_PKEY_INDEX [15:0] +-- 0x328 QP_MAX_RD_ATOMIC [7:0] 0x32C QP_MAX_DEST_RD_ATOMIC [7:0] +-- 0x330 QP_MIN_RNR_TIMER [4:0] 0x334 QP_TIMEOUT [4:0] +-- 0x338 QP_RETRY_CNT [2:0] 0x33C QP_RNR_RETRY [2:0] +-- 0x340 QP_CUR_STATE [3:0] +-- 0x344 QP_MAX_SEND_WR [7:0] 0x348 QP_MAX_RECV_WR [7:0] +-- 0x34C QP_MAX_SEND_SGE [7:0] 0x350 QP_MAX_RECV_SGE [7:0] +-- 0x354 QP_MAX_INLINE_DATA [7:0] +-- 0x358 QP_SQ_DRAINING [0] +-- --- Response bank (RO; captured on completion) --- +-- 0x400 RESP_STATUS [0] success [2:1] tag +-- 0x404 RESP_PD_HANDLER [31:0] +-- 0x408 RESP_PD_KEY [30:0] +-- 0x40C RESP_MR_LKEY [31:0] 0x410 RESP_MR_RKEY [31:0] +-- 0x414 RESP_QP_QPN [23:0] +-- +-- Protocol: program the bank for REQ_TYPE, write CONTROL with GO=1 (single +-- write; GO self-clears). BUSY rises until the response is captured; DONE +-- then rises (cleared on the next accepted GO) and mdDoneIrq pulses one +-- cycle. GO while BUSY is ignored and sets the sticky ERR bit. The MemRegion +-- / qpAttr echo portions of RespMR/RespQP are intentionally not exposed (the +-- driver wrote them); RESP_* covers the allocated handles/keys/qpn + success. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +use work.RocePkg.all; + +entity RoceMetaDataAxil is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + MAX_QP_G : positive := 4; -- reported in VERSION only + VERSION_G : slv(7 downto 0) := x"01"); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- AXI-Lite slave (register access) + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType; + -- MetaData server pair (to TransportLayer mdSrv*) + mdSrvReqValid : out sl; + mdSrvReqData : out slv(ROCE_MD_REQ_W_C-1 downto 0); + mdSrvReqReady : in sl; + mdSrvRespValid : in sl; + mdSrvRespData : in slv(ROCE_MD_RESP_W_C-1 downto 0); + mdSrvRespReady : out sl; + -- completion interrupt (1-cycle pulse when DONE sets) + mdDoneIrq : out sl); +end entity RoceMetaDataAxil; + +architecture rtl of RoceMetaDataAxil is + + constant VERSION_C : slv(31 downto 0) := + x"0000" & toSlv(MAX_QP_G, 8) & VERSION_G; + + type StateType is ( + IDLE_S, + SEND_S, + WAIT_RESP_S); + + type RegType is record + axilReadSlave : AxiLiteReadSlaveType; + axilWriteSlave : AxiLiteWriteSlaveType; + state : StateType; + -- control/status + reqType : slv(1 downto 0); + scratch : slv(31 downto 0); + done : sl; + err : sl; + irq : sl; + -- PD request bank + pdAlloc : sl; + pdKey : slv(30 downto 0); + pdHandler : slv(31 downto 0); + -- MR request bank + mrAlloc : sl; + mrLkeyOrNot : sl; + mrLaddr : slv(63 downto 0); + mrLen : slv(31 downto 0); + mrAccFlags : slv(7 downto 0); + mrPdHandler : slv(31 downto 0); + mrLkeyPart : slv(24 downto 0); + mrRkeyPart : slv(24 downto 0); + mrLkey : slv(31 downto 0); + mrRkey : slv(31 downto 0); + -- QP request bank (full ReqQP coverage) + qpReqType : slv(1 downto 0); + qpState : slv(3 downto 0); + qpCurState : slv(3 downto 0); + qpPmtu : slv(2 downto 0); + qpType : slv(3 downto 0); + qpSqSigAll : sl; + qpPdHandler : slv(31 downto 0); + qpQpn : slv(23 downto 0); + qpAttrMask : slv(25 downto 0); + qpQkey : slv(31 downto 0); + qpRqPsn : slv(23 downto 0); + qpSqPsn : slv(23 downto 0); + qpDqpn : slv(23 downto 0); + qpAccessFlags : slv(7 downto 0); + qpPkeyIndex : slv(15 downto 0); + qpMaxRdAtomic : slv(7 downto 0); + qpMaxDestRdAtomic : slv(7 downto 0); + qpMinRnrTimer : slv(4 downto 0); + qpTimeout : slv(4 downto 0); + qpRetryCnt : slv(2 downto 0); + qpRnrRetry : slv(2 downto 0); + qpMaxSendWr : slv(7 downto 0); + qpMaxRecvWr : slv(7 downto 0); + qpMaxSendSge : slv(7 downto 0); + qpMaxRecvSge : slv(7 downto 0); + qpMaxInlineData : slv(7 downto 0); + qpSqDraining : sl; + -- response bank (RO) + respTag : slv(1 downto 0); + respSuccess : sl; + respPdHandler : slv(31 downto 0); + respPdKey : slv(30 downto 0); + respMrLkey : slv(31 downto 0); + respMrRkey : slv(31 downto 0); + respQpQpn : slv(23 downto 0); + -- mdSrv request face (registered) + mdReqValid : sl; + mdReqData : slv(ROCE_MD_REQ_W_C-1 downto 0); + end record RegType; + + constant REG_INIT_C : RegType := ( + axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, + axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, + state => IDLE_S, + reqType => (others => '0'), + scratch => (others => '0'), + done => '0', + err => '0', + irq => '0', + pdAlloc => '0', + pdKey => (others => '0'), + pdHandler => (others => '0'), + mrAlloc => '0', + mrLkeyOrNot => '0', + mrLaddr => (others => '0'), + mrLen => (others => '0'), + mrAccFlags => (others => '0'), + mrPdHandler => (others => '0'), + mrLkeyPart => (others => '0'), + mrRkeyPart => (others => '0'), + mrLkey => (others => '0'), + mrRkey => (others => '0'), + qpReqType => (others => '0'), + qpState => (others => '0'), + qpCurState => (others => '0'), + qpPmtu => (others => '0'), + qpType => (others => '0'), + qpSqSigAll => '0', + qpPdHandler => (others => '0'), + qpQpn => (others => '0'), + qpAttrMask => (others => '0'), + qpQkey => (others => '0'), + qpRqPsn => (others => '0'), + qpSqPsn => (others => '0'), + qpDqpn => (others => '0'), + qpAccessFlags => (others => '0'), + qpPkeyIndex => (others => '0'), + qpMaxRdAtomic => (others => '0'), + qpMaxDestRdAtomic => (others => '0'), + qpMinRnrTimer => (others => '0'), + qpTimeout => (others => '0'), + qpRetryCnt => (others => '0'), + qpRnrRetry => (others => '0'), + qpMaxSendWr => (others => '0'), + qpMaxRecvWr => (others => '0'), + qpMaxSendSge => (others => '0'), + qpMaxRecvSge => (others => '0'), + qpMaxInlineData => (others => '0'), + qpSqDraining => '0', + respTag => (others => '0'), + respSuccess => '0', + respPdHandler => (others => '0'), + respPdKey => (others => '0'), + respMrLkey => (others => '0'), + respMrRkey => (others => '0'), + respQpQpn => (others => '0'), + mdReqValid => '0', + mdReqData => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + +begin + + comb : process (axilReadMaster, axilWriteMaster, mdSrvReqReady, + mdSrvRespData, mdSrvRespValid, r, rst) is + variable v : RegType; + variable axilEp : AxiLiteEndpointType; + variable go : sl; + variable busy : sl; + begin + v := r; + + -- self-clearing strobes + go := '0'; + v.irq := '0'; + + busy := toSl(r.state /= IDLE_S); + + ------------------------------------------------------------------------ + -- AXI-Lite register decode + ------------------------------------------------------------------------ + axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, + v.axilWriteSlave, v.axilReadSlave); + + -- control / status + axiSlaveRegister (axilEp, x"000", 0, go); + axiSlaveRegister (axilEp, x"000", 1, v.reqType); + axiSlaveRegisterR(axilEp, x"004", 0, r.done); + axiSlaveRegisterR(axilEp, x"004", 1, busy); + axiSlaveRegisterR(axilEp, x"004", 2, r.err); + axiSlaveRegisterR(axilEp, x"004", 3, r.respTag); + axiSlaveRegisterR(axilEp, x"004", 5, r.respSuccess); + axiSlaveRegisterR(axilEp, x"008", 0, VERSION_C); + axiSlaveRegister (axilEp, x"00C", 0, v.scratch); + -- PD request bank + axiSlaveRegister (axilEp, x"100", 0, v.pdAlloc); + axiSlaveRegister (axilEp, x"104", 0, v.pdKey); + axiSlaveRegister (axilEp, x"108", 0, v.pdHandler); + -- MR request bank + axiSlaveRegister (axilEp, x"200", 0, v.mrAlloc); + axiSlaveRegister (axilEp, x"200", 1, v.mrLkeyOrNot); + axiSlaveRegister (axilEp, x"204", 0, v.mrLaddr); -- spans 0x204/0x208 + axiSlaveRegister (axilEp, x"20C", 0, v.mrLen); + axiSlaveRegister (axilEp, x"210", 0, v.mrAccFlags); + axiSlaveRegister (axilEp, x"214", 0, v.mrPdHandler); + axiSlaveRegister (axilEp, x"218", 0, v.mrLkeyPart); + axiSlaveRegister (axilEp, x"21C", 0, v.mrRkeyPart); + axiSlaveRegister (axilEp, x"220", 0, v.mrLkey); + axiSlaveRegister (axilEp, x"224", 0, v.mrRkey); + -- QP request bank + axiSlaveRegister (axilEp, x"300", 0, v.qpReqType); + axiSlaveRegister (axilEp, x"300", 2, v.qpState); + axiSlaveRegister (axilEp, x"300", 6, v.qpPmtu); + axiSlaveRegister (axilEp, x"300", 9, v.qpType); + axiSlaveRegister (axilEp, x"300", 13, v.qpSqSigAll); + axiSlaveRegister (axilEp, x"304", 0, v.qpPdHandler); + axiSlaveRegister (axilEp, x"308", 0, v.qpQpn); + axiSlaveRegister (axilEp, x"30C", 0, v.qpAttrMask); + axiSlaveRegister (axilEp, x"310", 0, v.qpQkey); + axiSlaveRegister (axilEp, x"314", 0, v.qpRqPsn); + axiSlaveRegister (axilEp, x"318", 0, v.qpSqPsn); + axiSlaveRegister (axilEp, x"31C", 0, v.qpDqpn); + axiSlaveRegister (axilEp, x"320", 0, v.qpAccessFlags); + axiSlaveRegister (axilEp, x"324", 0, v.qpPkeyIndex); + axiSlaveRegister (axilEp, x"328", 0, v.qpMaxRdAtomic); + axiSlaveRegister (axilEp, x"32C", 0, v.qpMaxDestRdAtomic); + axiSlaveRegister (axilEp, x"330", 0, v.qpMinRnrTimer); + axiSlaveRegister (axilEp, x"334", 0, v.qpTimeout); + axiSlaveRegister (axilEp, x"338", 0, v.qpRetryCnt); + axiSlaveRegister (axilEp, x"33C", 0, v.qpRnrRetry); + axiSlaveRegister (axilEp, x"340", 0, v.qpCurState); + axiSlaveRegister (axilEp, x"344", 0, v.qpMaxSendWr); + axiSlaveRegister (axilEp, x"348", 0, v.qpMaxRecvWr); + axiSlaveRegister (axilEp, x"34C", 0, v.qpMaxSendSge); + axiSlaveRegister (axilEp, x"350", 0, v.qpMaxRecvSge); + axiSlaveRegister (axilEp, x"354", 0, v.qpMaxInlineData); + axiSlaveRegister (axilEp, x"358", 0, v.qpSqDraining); + -- response bank (RO) + axiSlaveRegisterR(axilEp, x"400", 0, r.respSuccess); + axiSlaveRegisterR(axilEp, x"400", 1, r.respTag); + axiSlaveRegisterR(axilEp, x"404", 0, r.respPdHandler); + axiSlaveRegisterR(axilEp, x"408", 0, r.respPdKey); + axiSlaveRegisterR(axilEp, x"40C", 0, r.respMrLkey); + axiSlaveRegisterR(axilEp, x"410", 0, r.respMrRkey); + axiSlaveRegisterR(axilEp, x"414", 0, r.respQpQpn); + + axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); + + ------------------------------------------------------------------------ + -- Request/response FSM (one MetaDataReq in flight at a time) + ------------------------------------------------------------------------ + case r.state is + --------------------------------------------------------------------- + when IDLE_S => + if (go = '1') then + v.done := '0'; + v.err := '0'; + -- pack MetaDataReq = tag & member (member LSB-justified in the + -- 301-bit union payload, deriving(Bits) first-field-at-MSB) + v.mdReqData := (others => '0'); + case v.reqType is -- v: honor a REQ_TYPE written with GO + when ROCE_MD_TAG_MR_C => + v.mdReqData := ROCE_MD_TAG_MR_C & toSlv(0, 49) & + r.mrAlloc & + r.mrLaddr & r.mrLen & r.mrAccFlags & + r.mrPdHandler & r.mrLkeyPart & r.mrRkeyPart & + r.mrLkeyOrNot & r.mrLkey & r.mrRkey; + when ROCE_MD_TAG_QP_C => + v.mdReqData := ROCE_MD_TAG_QP_C & + r.qpReqType & r.qpPdHandler & r.qpQpn & + r.qpAttrMask & + r.qpState & r.qpCurState & r.qpPmtu & + r.qpQkey & r.qpRqPsn & r.qpSqPsn & r.qpDqpn & + r.qpAccessFlags & + r.qpMaxSendWr & r.qpMaxRecvWr & + r.qpMaxSendSge & r.qpMaxRecvSge & + r.qpMaxInlineData & + r.qpPkeyIndex & r.qpSqDraining & + r.qpMaxRdAtomic & r.qpMaxDestRdAtomic & + r.qpMinRnrTimer & r.qpTimeout & + r.qpRetryCnt & r.qpRnrRetry & + r.qpType & r.qpSqSigAll; + when others => -- ROCE_MD_TAG_PD_C + v.mdReqData := ROCE_MD_TAG_PD_C & toSlv(0, 237) & + r.pdAlloc & r.pdKey & r.pdHandler; + end case; + v.mdReqValid := '1'; + v.state := SEND_S; + end if; + --------------------------------------------------------------------- + when SEND_S => + if (go = '1') then + v.err := '1'; -- GO while BUSY: ignored, sticky ERR + end if; + if (mdSrvReqReady = '1') then + v.mdReqValid := '0'; + v.state := WAIT_RESP_S; + end if; + --------------------------------------------------------------------- + when WAIT_RESP_S => + if (go = '1') then + v.err := '1'; -- GO while BUSY: ignored, sticky ERR + end if; + if (mdSrvRespValid = '1') then + -- demux MetaDataResp by tag (RespPD/RespMR/RespQP layouts) + v.respTag := mdSrvRespData(275 downto 274); + case mdSrvRespData(275 downto 274) is + when ROCE_MD_TAG_MR_C => + v.respSuccess := mdSrvRespData(250); + v.respMrLkey := mdSrvRespData(63 downto 32); + v.respMrRkey := mdSrvRespData(31 downto 0); + when ROCE_MD_TAG_QP_C => + v.respSuccess := mdSrvRespData(273); + v.respQpQpn := mdSrvRespData(272 downto 249); + when others => -- ROCE_MD_TAG_PD_C + v.respSuccess := mdSrvRespData(63); + v.respPdHandler := mdSrvRespData(62 downto 31); + v.respPdKey := mdSrvRespData(30 downto 0); + end case; + v.done := '1'; + v.irq := '1'; + v.state := IDLE_S; + end if; + end case; + + -- synchronous reset + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + + -- outputs + axilReadSlave <= r.axilReadSlave; + axilWriteSlave <= r.axilWriteSlave; + mdSrvReqValid <= r.mdReqValid; + mdSrvReqData <= r.mdReqData; + -- FWFT pop: hold ready while waiting; the one response beat pops on the + -- edge where valid and ready are both high + mdSrvRespReady <= toSl(r.state = WAIT_RESP_S); + mdDoneIrq <= r.irq; + end process comb; + + seq : process (clk, rst) is + begin + if (RST_ASYNC_G and rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/RocePkg.vhd b/ethernet/RoCEv2/rtl/RocePkg.vhd index cc8338becb..45766bfba2 100644 --- a/ethernet/RoCEv2/rtl/RocePkg.vhd +++ b/ethernet/RoCEv2/rtl/RocePkg.vhd @@ -1,7 +1,31 @@ ------------------------------------------------------------------------------- -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- --- Description: RoCEv2 Package File +-- Provenance : HAND-WRITTEN integration package (not BSV-derived). Extended +-- from style/examples/RocePkg.vhd (SLAC, old blue-rdma design) +-- to match the structs emitted by THIS project's transpile. +-- Struct refs: src-bsv/DataTypes.bsv (WorkReq:525-543, RecvReq:578-586, +-- DmaReadReq:265-272, DmaReadResp:274-280, DmaWriteReq:282-293, +-- DmaWriteResp:295-300, DataStream), src-bsv/MetaData.bsv +-- (ReqPD/RespPD:253-263, ReqMR/RespMR:163-177, MetaDataReq/ +-- Resp:661-671), src-bsv/Controller.bsv (ReqQP/RespQP:60-76). +------------------------------------------------------------------------------- +-- Conventions: +-- * One record type per BSV struct, fields in BSV declaration order +-- (deriving(Bits) packs first-field-at-MSB in the flat slv). +-- * ToSlv / SlvTo : record <-> flat slv (TransportLayer port format). +-- * ToAxiStream / AxiStreamTo : record <-> single-beat AXI-Stream, +-- struct LSB-justified in tData, tLast='1' per beat. +-- * DataStream (the RoCE wire stream) is BYTE-SWAPPED on AXIS: BSV puts the +-- first wire byte in the data MSBs / byteEn bit 31; AXI-Stream puts it in +-- tData lane 0 / tKeep(0). isLast -> tLast, isFirst -> SSI SOF (tUser). +-- * The dataStream fields EMBEDDED in DmaReadResp/DmaWriteReq stay in raw +-- BSV format (slv(289:0), first byte at MSBs) inside tData - only the +-- network-facing stream is lane-swapped. +-- * Changes vs the old style/examples/RocePkg.vhd: mrIdx is slv(6:0) +-- (IndexMR = 7b here, DmaReadReq = 176b not 170b); RecvReq / DmaWrite +-- types added; metadata AXIS helpers dropped (metadata is AXI-Lite now, +-- see RoceMetaDataAxil.vhd). ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -14,8 +38,7 @@ library ieee; use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; +use ieee.numeric_std.all; library surf; use surf.StdRtlPkg.all; @@ -24,20 +47,69 @@ use surf.SsiPkg.all; package RocePkg is - -- Types + --------------------------------------------------------------------------- + -- Stream configurations + --------------------------------------------------------------------------- constant TDATA_ROCE_NUM_BYTES_C : natural range 1 to 128 := 32; constant TDATA_UDP_NUM_BYTES_C : natural range 1 to 128 := 16; constant BLUE_DATA_STREAM_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig( dataBytes => TDATA_ROCE_NUM_BYTES_C, - tDestBits => 0 - ); + tDestBits => 0); constant SURF_DATA_STREAM_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig( dataBytes => TDATA_UDP_NUM_BYTES_C, - tDestBits => 0 - ); + tDestBits => 0); + + --------------------------------------------------------------------------- + -- Flat struct widths (TransportLayer port formats) + --------------------------------------------------------------------------- + constant ROCE_DATA_STREAM_W_C : positive := 290; + constant ROCE_WORK_REQ_W_C : positive := 601; + constant ROCE_RECV_REQ_W_C : positive := 216; + constant ROCE_WORK_COMP_W_C : positive := 222; + constant ROCE_DMA_RD_REQ_W_C : positive := 176; + constant ROCE_DMA_RD_RESP_W_C : positive := 383; + constant ROCE_DMA_WR_REQ_W_C : positive := 419; + constant ROCE_DMA_WR_RESP_W_C : positive := 53; + constant ROCE_MD_REQ_W_C : positive := 303; + constant ROCE_MD_RESP_W_C : positive := 276; + + -- MetaDataReq/Resp union tags (MetaData.bsv:661-671, first member = 0) + constant ROCE_MD_TAG_PD_C : slv(1 downto 0) := "00"; + constant ROCE_MD_TAG_MR_C : slv(1 downto 0) := "01"; + constant ROCE_MD_TAG_QP_C : slv(1 downto 0) := "10"; + + --------------------------------------------------------------------------- + -- DataStream (raw RoCE wire beat; DataTypes.bsv DataStream) + -- flat: data[289:34] byteEn[33:2] isFirst[1] isLast[0] + -- first wire byte = data(255 downto 248) = byteEn bit 31 + --------------------------------------------------------------------------- + type RoceDataStreamMasterType is record + valid : sl; + data : slv(255 downto 0); + byteEn : slv(31 downto 0); + isFirst : sl; + isLast : sl; + end record RoceDataStreamMasterType; + + constant ROCE_DATA_STREAM_MASTER_INIT_C : RoceDataStreamMasterType := ( + valid => '0', + data => (others => '0'), + byteEn => (others => '0'), + isFirst => '0', + isLast => '0'); + + type RoceDataStreamSlaveType is record + ready : sl; + end record RoceDataStreamSlaveType; + + constant ROCE_DATA_STREAM_SLAVE_INIT_C : RoceDataStreamSlaveType := (ready => '0'); + constant ROCE_DATA_STREAM_SLAVE_FORCE_C : RoceDataStreamSlaveType := (ready => '1'); + --------------------------------------------------------------------------- + -- WorkReq (DataTypes.bsv:525-543; 601b) + --------------------------------------------------------------------------- type RoceWorkReqMasterType is record valid : sl; id : slv(63 downto 0); @@ -50,13 +122,13 @@ package RocePkg is lKey : slv(31 downto 0); sQpn : slv(23 downto 0); solicited : sl; - comp : slv(64 downto 0); - swap : slv(64 downto 0); - immDt : slv(32 downto 0); - rKeyToInv : slv(32 downto 0); - srqn : slv(24 downto 0); - dQpn : slv(24 downto 0); - qKey : slv(32 downto 0); + comp : slv(64 downto 0); -- Maybe#(Long), tag at MSB + swap : slv(64 downto 0); -- Maybe#(Long) + immDt : slv(32 downto 0); -- Maybe#(IMM) + rKeyToInv : slv(32 downto 0); -- Maybe#(RKEY) + srqn : slv(24 downto 0); -- Maybe#(QPN) + dQpn : slv(24 downto 0); -- Maybe#(QPN) + qKey : slv(32 downto 0); -- Maybe#(QKEY) end record RoceWorkReqMasterType; constant ROCE_WORK_REQ_MASTER_INIT_C : RoceWorkReqMasterType := ( @@ -77,19 +149,45 @@ package RocePkg is rKeyToInv => (others => '0'), srqn => (others => '0'), dQpn => (others => '0'), - qKey => (others => '0') - ); + qKey => (others => '0')); type RoceWorkReqSlaveType is record ready : sl; end record RoceWorkReqSlaveType; - constant ROCE_WORK_REQ_SLAVE_INIT_C : RoceWorkReqSlaveType := ( - ready => '0'); + constant ROCE_WORK_REQ_SLAVE_INIT_C : RoceWorkReqSlaveType := (ready => '0'); + constant ROCE_WORK_REQ_SLAVE_FORCE_C : RoceWorkReqSlaveType := (ready => '1'); - constant ROCE_WORK_REQ_SLAVE_FORCE_C : RoceWorkReqSlaveType := ( - ready => '1'); + --------------------------------------------------------------------------- + -- RecvReq (DataTypes.bsv:578-586; 216b) + --------------------------------------------------------------------------- + type RoceRecvReqMasterType is record + valid : sl; + id : slv(63 downto 0); + len : slv(31 downto 0); + lAddr : slv(63 downto 0); + lKey : slv(31 downto 0); + sQpn : slv(23 downto 0); + end record RoceRecvReqMasterType; + + constant ROCE_RECV_REQ_MASTER_INIT_C : RoceRecvReqMasterType := ( + valid => '0', + id => (others => '0'), + len => (others => '0'), + lAddr => (others => '0'), + lKey => (others => '0'), + sQpn => (others => '0')); + + type RoceRecvReqSlaveType is record + ready : sl; + end record RoceRecvReqSlaveType; + constant ROCE_RECV_REQ_SLAVE_INIT_C : RoceRecvReqSlaveType := (ready => '0'); + constant ROCE_RECV_REQ_SLAVE_FORCE_C : RoceRecvReqSlaveType := (ready => '1'); + + --------------------------------------------------------------------------- + -- WorkComp (DataTypes.bsv WorkComp; 222b) + --------------------------------------------------------------------------- type RoceWorkCompMasterType is record valid : sl; id : slv(63 downto 0); @@ -99,8 +197,8 @@ package RocePkg is len : slv(31 downto 0); pKey : slv(15 downto 0); qpn : slv(23 downto 0); - immDt : slv(32 downto 0); - rKeyToInv : slv(32 downto 0); + immDt : slv(32 downto 0); -- Maybe#(IMM) + rKeyToInv : slv(32 downto 0); -- Maybe#(RKEY) end record RoceWorkCompMasterType; constant ROCE_WORK_COMP_MASTER_INIT_C : RoceWorkCompMasterType := ( @@ -113,19 +211,18 @@ package RocePkg is pKey => (others => '0'), qpn => (others => '0'), immDt => (others => '0'), - rKeyToInv => (others => '0') - ); + rKeyToInv => (others => '0')); type RoceWorkCompSlaveType is record ready : sl; end record RoceWorkCompSlaveType; - constant ROCE_WORK_COMP_SLAVE_INIT_C : RoceWorkCompSlaveType := ( - ready => '0'); - - constant ROCE_WORK_COMP_SLAVE_FORCE_C : RoceWorkCompSlaveType := ( - ready => '1'); + constant ROCE_WORK_COMP_SLAVE_INIT_C : RoceWorkCompSlaveType := (ready => '0'); + constant ROCE_WORK_COMP_SLAVE_FORCE_C : RoceWorkCompSlaveType := (ready => '1'); + --------------------------------------------------------------------------- + -- DmaReadReq (DataTypes.bsv:265-272; 176b — IndexMR mrIdx is 7b here) + --------------------------------------------------------------------------- type RoceDmaReadReqMasterType is record valid : sl; initiator : slv(3 downto 0); @@ -133,7 +230,7 @@ package RocePkg is wrId : slv(63 downto 0); startAddr : slv(63 downto 0); len : slv(12 downto 0); - mrIdx : sl; + mrIdx : slv(6 downto 0); end record RoceDmaReadReqMasterType; constant ROCE_DMA_READ_REQ_MASTER_INIT_C : RoceDmaReadReqMasterType := ( @@ -143,19 +240,18 @@ package RocePkg is wrId => (others => '0'), startAddr => (others => '0'), len => (others => '0'), - mrIdx => '0' - ); + mrIdx => (others => '0')); type RoceDmaReadReqSlaveType is record ready : sl; end record RoceDmaReadReqSlaveType; - constant ROCE_DMA_READ_REQ_SLAVE_INIT_C : RoceDmaReadReqSlaveType := ( - ready => '0'); - - constant ROCE_DMA_READ_REQ_SLAVE_FORCE_C : RoceDmaReadReqSlaveType := ( - ready => '1'); + constant ROCE_DMA_READ_REQ_SLAVE_INIT_C : RoceDmaReadReqSlaveType := (ready => '0'); + constant ROCE_DMA_READ_REQ_SLAVE_FORCE_C : RoceDmaReadReqSlaveType := (ready => '1'); + --------------------------------------------------------------------------- + -- DmaReadResp (DataTypes.bsv:274-280; 383b; dataStream in raw BSV format) + --------------------------------------------------------------------------- type RoceDmaReadRespMasterType is record valid : sl; initiator : slv(3 downto 0); @@ -171,303 +267,452 @@ package RocePkg is sQpn => (others => '0'), wrId => (others => '0'), isRespErr => '0', - dataStream => (others => '0') - ); + dataStream => (others => '0')); type RoceDmaReadRespSlaveType is record ready : sl; end record RoceDmaReadRespSlaveType; - constant ROCE_DMA_READ_RESP_SLAVE_INIT_C : RoceDmaReadRespSlaveType := ( - ready => '0'); + constant ROCE_DMA_READ_RESP_SLAVE_INIT_C : RoceDmaReadRespSlaveType := (ready => '0'); + constant ROCE_DMA_READ_RESP_SLAVE_FORCE_C : RoceDmaReadRespSlaveType := (ready => '1'); - constant ROCE_DMA_READ_RESP_SLAVE_FORCE_C : RoceDmaReadRespSlaveType := ( - ready => '1'); + --------------------------------------------------------------------------- + -- DmaWriteReq (DataTypes.bsv:282-293; 419b = DmaWriteMetaData(129) + DataStream(290)) + --------------------------------------------------------------------------- + type RoceDmaWriteReqMasterType is record + valid : sl; + initiator : slv(3 downto 0); + sQpn : slv(23 downto 0); + startAddr : slv(63 downto 0); + len : slv(12 downto 0); + psn : slv(23 downto 0); + dataStream : slv(289 downto 0); + end record RoceDmaWriteReqMasterType; + + constant ROCE_DMA_WRITE_REQ_MASTER_INIT_C : RoceDmaWriteReqMasterType := ( + valid => '0', + initiator => (others => '0'), + sQpn => (others => '0'), + startAddr => (others => '0'), + len => (others => '0'), + psn => (others => '0'), + dataStream => (others => '0')); - -- Functions - function ToRoceWorkReqMasterType ( + type RoceDmaWriteReqSlaveType is record + ready : sl; + end record RoceDmaWriteReqSlaveType; + + constant ROCE_DMA_WRITE_REQ_SLAVE_INIT_C : RoceDmaWriteReqSlaveType := (ready => '0'); + constant ROCE_DMA_WRITE_REQ_SLAVE_FORCE_C : RoceDmaWriteReqSlaveType := (ready => '1'); + + --------------------------------------------------------------------------- + -- DmaWriteResp (DataTypes.bsv:295-300; 53b) + --------------------------------------------------------------------------- + type RoceDmaWriteRespMasterType is record valid : sl; - id : slv(63 downto 0); - opCode : slv(3 downto 0); - flags : slv(4 downto 0); - rAddr : slv(63 downto 0); - rKey : slv(31 downto 0); - len : slv(31 downto 0); - lAddr : slv(63 downto 0); - lKey : slv(31 downto 0); + initiator : slv(3 downto 0); sQpn : slv(23 downto 0); - solicited : sl; - comp : slv(64 downto 0); - swap : slv(64 downto 0); - immDt : slv(32 downto 0); - rKeyToInv : slv(32 downto 0); - srqn : slv(24 downto 0); - dQpn : slv(24 downto 0); - qKey : slv(32 downto 0)) - return RoceWorkReqMasterType; - - function toRoceWorkCompSlaveType ( - ready : sl) - return RoceWorkCompSlaveType; - - function ToAxisMetadataMasterType ( - valid : sl; - data : slv(302 downto 0)) - return AxiStreamMasterType; + psn : slv(23 downto 0); + isRespErr : sl; + end record RoceDmaWriteRespMasterType; - function ToAxisMetadataSlaveType ( - ready : sl) - return AxiStreamSlaveType; + constant ROCE_DMA_WRITE_RESP_MASTER_INIT_C : RoceDmaWriteRespMasterType := ( + valid => '0', + initiator => (others => '0'), + sQpn => (others => '0'), + psn => (others => '0'), + isRespErr => '0'); - function ToDmaReadRespMasterType ( - valid : sl; - initiator : slv(3 downto 0); - sqpn : slv(23 downto 0); - wrId : slv(63 downto 0); - isRespErr : sl; - dataStream : slv(289 downto 0)) - return RoceDmaReadRespMasterType; - - function ToDmaReadReqSlaveType ( - ready : sl) - return RoceDmaReadReqSlaveType; - - function DmaReadReqToAxiStreamMaster ( - wrIn : RoceDmaReadReqMasterType) - return AxiStreamMasterType; - - function DmaReadReqToAxiStreamSlave ( - wrIn : RoceDmaReadReqSlaveType) - return AxiStreamSlaveType; - - function AxiStreamToDmaReadReqMaster ( - wrIn : AxiStreamMasterType) - return RoceDmaReadReqMasterType; - - function AxiStreamToDmaReadReqSlave ( - wrIn : AxiStreamSlaveType) - return RoceDmaReadReqSlaveType; - - -- function WorkReqToAxiStreamMaster ( - -- wrIn : RoceWorkReqMasterType) - -- return AxiStreamMasterType; - - -- function AxiStreamToWorkReqMaster ( - -- wrIn : AxiStreamMasterType) - -- return RoceWorkReqMasterType; - - -- function WorkReqToAxiStreamSlave ( - -- wrIn : RoceWorkReqSlaveType) - -- return AxiStreamSlaveType; - - -- function AxiStreamToWorkReqSlave ( - -- wrIn : AxiStreamSlaveType) - -- return RoceWorkReqSlaveType; - - -- function FromRoceWorkReqSlaveType ( - -- roceWorkReqSlave : RoceWorkReqSlaveType) - -- return sl; - - -- function ToRoceWorkCompMasterType ( - -- valid : sl; - -- id : slv(63 downto 0); - -- opCode : slv(7 downto 0); - -- flags : slv(6 downto 0); - -- status : slv(4 downto 0); - -- len : slv(31 downto 0); - -- pKey : slv(15 downto 0); - -- qpn : slv(23 downto 0); - -- immDt : slv(32 downto 0); - -- rKeyToInv : slv(32 downto 0)) - -- return RoceWorkCompMasterType; + type RoceDmaWriteRespSlaveType is record + ready : sl; + end record RoceDmaWriteRespSlaveType; + + constant ROCE_DMA_WRITE_RESP_SLAVE_INIT_C : RoceDmaWriteRespSlaveType := (ready => '0'); + constant ROCE_DMA_WRITE_RESP_SLAVE_FORCE_C : RoceDmaWriteRespSlaveType := (ready => '1'); + + --------------------------------------------------------------------------- + -- Conversion functions + --------------------------------------------------------------------------- + -- generic AXIS slave helper + function ToAxiStreamSlave (ready : sl) return AxiStreamSlaveType; + + -- DataStream (network-facing; BYTE-SWAPPED on AXIS) + function DataStreamToSlv (ds : RoceDataStreamMasterType) return slv; + function SlvToDataStream (valid : sl; d : slv(289 downto 0)) return RoceDataStreamMasterType; + function DataStreamToAxiStream (ds : RoceDataStreamMasterType) return AxiStreamMasterType; + function AxiStreamToDataStream (axis : AxiStreamMasterType) return RoceDataStreamMasterType; + + -- WorkReq + function WorkReqToSlv (wr : RoceWorkReqMasterType) return slv; + function SlvToWorkReq (valid : sl; d : slv(600 downto 0)) return RoceWorkReqMasterType; + function WorkReqToAxiStream (wr : RoceWorkReqMasterType) return AxiStreamMasterType; + function AxiStreamToWorkReq (axis : AxiStreamMasterType) return RoceWorkReqMasterType; + + -- RecvReq + function RecvReqToSlv (rr : RoceRecvReqMasterType) return slv; + function SlvToRecvReq (valid : sl; d : slv(215 downto 0)) return RoceRecvReqMasterType; + function RecvReqToAxiStream (rr : RoceRecvReqMasterType) return AxiStreamMasterType; + function AxiStreamToRecvReq (axis : AxiStreamMasterType) return RoceRecvReqMasterType; + + -- WorkComp + function WorkCompToSlv (wc : RoceWorkCompMasterType) return slv; + function SlvToWorkComp (valid : sl; d : slv(221 downto 0)) return RoceWorkCompMasterType; + function WorkCompToAxiStream (wc : RoceWorkCompMasterType) return AxiStreamMasterType; + function AxiStreamToWorkComp (axis : AxiStreamMasterType) return RoceWorkCompMasterType; + + -- DmaReadReq + function DmaReadReqToSlv (req : RoceDmaReadReqMasterType) return slv; + function SlvToDmaReadReq (valid : sl; d : slv(175 downto 0)) return RoceDmaReadReqMasterType; + function DmaReadReqToAxiStream (req : RoceDmaReadReqMasterType) return AxiStreamMasterType; + function AxiStreamToDmaReadReq (axis : AxiStreamMasterType) return RoceDmaReadReqMasterType; + + -- DmaReadResp + function DmaReadRespToSlv (resp : RoceDmaReadRespMasterType) return slv; + function SlvToDmaReadResp (valid : sl; d : slv(382 downto 0)) return RoceDmaReadRespMasterType; + function DmaReadRespToAxiStream (resp : RoceDmaReadRespMasterType) return AxiStreamMasterType; + function AxiStreamToDmaReadResp (axis : AxiStreamMasterType) return RoceDmaReadRespMasterType; + + -- DmaWriteReq + function DmaWriteReqToSlv (req : RoceDmaWriteReqMasterType) return slv; + function SlvToDmaWriteReq (valid : sl; d : slv(418 downto 0)) return RoceDmaWriteReqMasterType; + function DmaWriteReqToAxiStream (req : RoceDmaWriteReqMasterType) return AxiStreamMasterType; + function AxiStreamToDmaWriteReq (axis : AxiStreamMasterType) return RoceDmaWriteReqMasterType; + + -- DmaWriteResp + function DmaWriteRespToSlv (resp : RoceDmaWriteRespMasterType) return slv; + function SlvToDmaWriteResp (valid : sl; d : slv(52 downto 0)) return RoceDmaWriteRespMasterType; + function DmaWriteRespToAxiStream (resp : RoceDmaWriteRespMasterType) return AxiStreamMasterType; + function AxiStreamToDmaWriteResp (axis : AxiStreamMasterType) return RoceDmaWriteRespMasterType; end package RocePkg; package body RocePkg is - function ToRoceWorkReqMasterType ( - valid : sl; - id : slv(63 downto 0); - opCode : slv(3 downto 0); - flags : slv(4 downto 0); - rAddr : slv(63 downto 0); - rKey : slv(31 downto 0); - len : slv(31 downto 0); - lAddr : slv(63 downto 0); - lKey : slv(31 downto 0); - sQpn : slv(23 downto 0); - solicited : sl; - comp : slv(64 downto 0); - swap : slv(64 downto 0); - immDt : slv(32 downto 0); - rKeyToInv : slv(32 downto 0); - srqn : slv(24 downto 0); - dQpn : slv(24 downto 0); - qKey : slv(32 downto 0)) - return RoceWorkReqMasterType is + function ToAxiStreamSlave (ready : sl) return AxiStreamSlaveType is + variable ret : AxiStreamSlaveType; + begin + ret.tReady := ready; + return ret; + end function ToAxiStreamSlave; + + --------------------------------------------------------------------------- + -- DataStream + --------------------------------------------------------------------------- + function DataStreamToSlv (ds : RoceDataStreamMasterType) return slv is + begin + return ds.data & ds.byteEn & ds.isFirst & ds.isLast; + end function DataStreamToSlv; + + function SlvToDataStream (valid : sl; d : slv(289 downto 0)) return RoceDataStreamMasterType is + variable ret : RoceDataStreamMasterType; + begin + ret.valid := valid; + ret.data := d(289 downto 34); + ret.byteEn := d(33 downto 2); + ret.isFirst := d(1); + ret.isLast := d(0); + return ret; + end function SlvToDataStream; + + -- BSV DataStream: first wire byte = data(255:248), byteEn(31). + -- AXI-Stream: first wire byte = tData(7:0), tKeep(0). + function DataStreamToAxiStream (ds : RoceDataStreamMasterType) return AxiStreamMasterType is + variable ret : AxiStreamMasterType; + begin + ret := axiStreamMasterInit(BLUE_DATA_STREAM_CONFIG_C); + ret.tValid := ds.valid; + for j in 0 to 31 loop + ret.tData(8*j+7 downto 8*j) := ds.data(255-8*j downto 248-8*j); + ret.tKeep(j) := ds.byteEn(31-j); + end loop; + ret.tLast := ds.isLast; + ssiSetUserSof(BLUE_DATA_STREAM_CONFIG_C, ret, ds.isFirst); + return ret; + end function DataStreamToAxiStream; + + function AxiStreamToDataStream (axis : AxiStreamMasterType) return RoceDataStreamMasterType is + variable ret : RoceDataStreamMasterType; + begin + ret.valid := axis.tValid; + for j in 0 to 31 loop + ret.data(255-8*j downto 248-8*j) := axis.tData(8*j+7 downto 8*j); + ret.byteEn(31-j) := axis.tKeep(j); + end loop; + ret.isFirst := ssiGetUserSof(BLUE_DATA_STREAM_CONFIG_C, axis); + ret.isLast := axis.tLast; + return ret; + end function AxiStreamToDataStream; + + --------------------------------------------------------------------------- + -- WorkReq (601b): id[600:537] opCode[536:533] flags[532:528] rAddr[527:464] + -- rKey[463:432] len[431:400] lAddr[399:336] lKey[335:304] sQpn[303:280] + -- solicited[279] comp[278:214] swap[213:149] immDt[148:116] + -- rKeyToInv[115:83] srqn[82:58] dQpn[57:33] qKey[32:0] + --------------------------------------------------------------------------- + function WorkReqToSlv (wr : RoceWorkReqMasterType) return slv is + begin + return wr.id & wr.opCode & wr.flags & wr.rAddr & wr.rKey & wr.len & + wr.lAddr & wr.lKey & wr.sQpn & wr.solicited & wr.comp & wr.swap & + wr.immDt & wr.rKeyToInv & wr.srqn & wr.dQpn & wr.qKey; + end function WorkReqToSlv; + + function SlvToWorkReq (valid : sl; d : slv(600 downto 0)) return RoceWorkReqMasterType is variable ret : RoceWorkReqMasterType; - begin -- function ToRoceWorkReqMasterType + begin ret.valid := valid; - ret.id := id; - ret.opCode := opCode; - ret.flags := flags; - ret.rAddr := rAddr; - ret.rKey := rKey; - ret.len := len; - ret.lAddr := lAddr; - ret.lKey := lKey; - ret.sQpn := sQpn; - ret.solicited := solicited; - ret.comp := comp; - ret.swap := swap; - ret.immDt := immDt; - ret.rKeyToInv := rKeyToInv; - ret.srqn := srqn; - ret.dQpn := dQpn; - ret.qKey := qKey; + ret.id := d(600 downto 537); + ret.opCode := d(536 downto 533); + ret.flags := d(532 downto 528); + ret.rAddr := d(527 downto 464); + ret.rKey := d(463 downto 432); + ret.len := d(431 downto 400); + ret.lAddr := d(399 downto 336); + ret.lKey := d(335 downto 304); + ret.sQpn := d(303 downto 280); + ret.solicited := d(279); + ret.comp := d(278 downto 214); + ret.swap := d(213 downto 149); + ret.immDt := d(148 downto 116); + ret.rKeyToInv := d(115 downto 83); + ret.srqn := d(82 downto 58); + ret.dQpn := d(57 downto 33); + ret.qKey := d(32 downto 0); return ret; - end function ToRoceWorkReqMasterType; + end function SlvToWorkReq; - function ToRoceWorkCompSlaveType ( - ready : sl) - return RoceWorkCompSlaveType is - variable ret : RoceWorkCompSlaveType; + function WorkReqToAxiStream (wr : RoceWorkReqMasterType) return AxiStreamMasterType is + variable ret : AxiStreamMasterType; begin - ret.ready := ready; + ret := AXI_STREAM_MASTER_INIT_C; + ret.tValid := wr.valid; + ret.tData(600 downto 0) := WorkReqToSlv(wr); + ret.tLast := '1'; return ret; - end function ToRoceWorkCompSlaveType; + end function WorkReqToAxiStream; - function ToAxisMetadataMasterType ( - valid : sl; - data : slv(302 downto 0)) - return AxiStreamMasterType is + function AxiStreamToWorkReq (axis : AxiStreamMasterType) return RoceWorkReqMasterType is + begin + return SlvToWorkReq(axis.tValid, axis.tData(600 downto 0)); + end function AxiStreamToWorkReq; + + --------------------------------------------------------------------------- + -- RecvReq (216b): id[215:152] len[151:120] lAddr[119:56] lKey[55:24] sQpn[23:0] + --------------------------------------------------------------------------- + function RecvReqToSlv (rr : RoceRecvReqMasterType) return slv is + begin + return rr.id & rr.len & rr.lAddr & rr.lKey & rr.sQpn; + end function RecvReqToSlv; + + function SlvToRecvReq (valid : sl; d : slv(215 downto 0)) return RoceRecvReqMasterType is + variable ret : RoceRecvReqMasterType; + begin + ret.valid := valid; + ret.id := d(215 downto 152); + ret.len := d(151 downto 120); + ret.lAddr := d(119 downto 56); + ret.lKey := d(55 downto 24); + ret.sQpn := d(23 downto 0); + return ret; + end function SlvToRecvReq; + + function RecvReqToAxiStream (rr : RoceRecvReqMasterType) return AxiStreamMasterType is variable ret : AxiStreamMasterType; begin ret := AXI_STREAM_MASTER_INIT_C; - ret.tValid := valid; - ret.tData(302 downto 0) := data; + ret.tValid := rr.valid; + ret.tData(215 downto 0) := RecvReqToSlv(rr); + ret.tLast := '1'; return ret; - end function ToAxisMetadataMasterType; + end function RecvReqToAxiStream; - function ToAxisMetadataSlaveType ( - ready : sl) - return AxiStreamSlaveType is - variable ret : AxiStreamSlaveType; + function AxiStreamToRecvReq (axis : AxiStreamMasterType) return RoceRecvReqMasterType is begin - ret.tReady := ready; + return SlvToRecvReq(axis.tValid, axis.tData(215 downto 0)); + end function AxiStreamToRecvReq; + + --------------------------------------------------------------------------- + -- WorkComp (222b): id[221:158] opCode[157:150] flags[149:143] status[142:138] + -- len[137:106] pKey[105:90] qpn[89:66] immDt[65:33] rKeyToInv[32:0] + --------------------------------------------------------------------------- + function WorkCompToSlv (wc : RoceWorkCompMasterType) return slv is + begin + return wc.id & wc.opCode & wc.flags & wc.status & wc.len & wc.pKey & + wc.qpn & wc.immDt & wc.rKeyToInv; + end function WorkCompToSlv; + + function SlvToWorkComp (valid : sl; d : slv(221 downto 0)) return RoceWorkCompMasterType is + variable ret : RoceWorkCompMasterType; + begin + ret.valid := valid; + ret.id := d(221 downto 158); + ret.opCode := d(157 downto 150); + ret.flags := d(149 downto 143); + ret.status := d(142 downto 138); + ret.len := d(137 downto 106); + ret.pKey := d(105 downto 90); + ret.qpn := d(89 downto 66); + ret.immDt := d(65 downto 33); + ret.rKeyToInv := d(32 downto 0); return ret; - end function ToAxisMetadataSlaveType; + end function SlvToWorkComp; - function ToDmaReadRespMasterType ( - valid : sl; - initiator : slv(3 downto 0); - sqpn : slv(23 downto 0); - wrId : slv(63 downto 0); - isRespErr : sl; - dataStream : slv(289 downto 0)) - return RoceDmaReadRespMasterType is + function WorkCompToAxiStream (wc : RoceWorkCompMasterType) return AxiStreamMasterType is + variable ret : AxiStreamMasterType; + begin + ret := AXI_STREAM_MASTER_INIT_C; + ret.tValid := wc.valid; + ret.tData(221 downto 0) := WorkCompToSlv(wc); + ret.tLast := '1'; + return ret; + end function WorkCompToAxiStream; + + function AxiStreamToWorkComp (axis : AxiStreamMasterType) return RoceWorkCompMasterType is + begin + return SlvToWorkComp(axis.tValid, axis.tData(221 downto 0)); + end function AxiStreamToWorkComp; + + --------------------------------------------------------------------------- + -- DmaReadReq (176b): initiator[175:172] sQpn[171:148] wrId[147:84] + -- startAddr[83:20] len[19:7] mrIdx[6:0] + --------------------------------------------------------------------------- + function DmaReadReqToSlv (req : RoceDmaReadReqMasterType) return slv is + begin + return req.initiator & req.sQpn & req.wrId & req.startAddr & req.len & req.mrIdx; + end function DmaReadReqToSlv; + + function SlvToDmaReadReq (valid : sl; d : slv(175 downto 0)) return RoceDmaReadReqMasterType is + variable ret : RoceDmaReadReqMasterType; + begin + ret.valid := valid; + ret.initiator := d(175 downto 172); + ret.sQpn := d(171 downto 148); + ret.wrId := d(147 downto 84); + ret.startAddr := d(83 downto 20); + ret.len := d(19 downto 7); + ret.mrIdx := d(6 downto 0); + return ret; + end function SlvToDmaReadReq; + + function DmaReadReqToAxiStream (req : RoceDmaReadReqMasterType) return AxiStreamMasterType is + variable ret : AxiStreamMasterType; + begin + ret := AXI_STREAM_MASTER_INIT_C; + ret.tValid := req.valid; + ret.tData(175 downto 0) := DmaReadReqToSlv(req); + ret.tLast := '1'; + return ret; + end function DmaReadReqToAxiStream; + + function AxiStreamToDmaReadReq (axis : AxiStreamMasterType) return RoceDmaReadReqMasterType is + begin + return SlvToDmaReadReq(axis.tValid, axis.tData(175 downto 0)); + end function AxiStreamToDmaReadReq; + + --------------------------------------------------------------------------- + -- DmaReadResp (383b): initiator[382:379] sQpn[378:355] wrId[354:291] + -- isRespErr[290] dataStream[289:0] + --------------------------------------------------------------------------- + function DmaReadRespToSlv (resp : RoceDmaReadRespMasterType) return slv is + begin + return resp.initiator & resp.sQpn & resp.wrId & resp.isRespErr & resp.dataStream; + end function DmaReadRespToSlv; + + function SlvToDmaReadResp (valid : sl; d : slv(382 downto 0)) return RoceDmaReadRespMasterType is variable ret : RoceDmaReadRespMasterType; begin ret.valid := valid; - ret.initiator := initiator; - ret.sqpn := sqpn; - ret.wrId := wrId; - ret.isRespErr := isRespErr; - ret.dataStream := dataStream; + ret.initiator := d(382 downto 379); + ret.sQpn := d(378 downto 355); + ret.wrId := d(354 downto 291); + ret.isRespErr := d(290); + ret.dataStream := d(289 downto 0); + return ret; + end function SlvToDmaReadResp; + + function DmaReadRespToAxiStream (resp : RoceDmaReadRespMasterType) return AxiStreamMasterType is + variable ret : AxiStreamMasterType; + begin + ret := AXI_STREAM_MASTER_INIT_C; + ret.tValid := resp.valid; + ret.tData(382 downto 0) := DmaReadRespToSlv(resp); + ret.tLast := '1'; return ret; - end function ToDmaReadRespMasterType; + end function DmaReadRespToAxiStream; + + function AxiStreamToDmaReadResp (axis : AxiStreamMasterType) return RoceDmaReadRespMasterType is + begin + return SlvToDmaReadResp(axis.tValid, axis.tData(382 downto 0)); + end function AxiStreamToDmaReadResp; + + --------------------------------------------------------------------------- + -- DmaWriteReq (419b): initiator[418:415] sQpn[414:391] startAddr[390:327] + -- len[326:314] psn[313:290] dataStream[289:0] + --------------------------------------------------------------------------- + function DmaWriteReqToSlv (req : RoceDmaWriteReqMasterType) return slv is + begin + return req.initiator & req.sQpn & req.startAddr & req.len & req.psn & req.dataStream; + end function DmaWriteReqToSlv; - function ToDmaReadReqSlaveType ( - ready : sl) - return RoceDmaReadReqSlaveType is - variable ret : RoceDmaReadReqSlaveType; + function SlvToDmaWriteReq (valid : sl; d : slv(418 downto 0)) return RoceDmaWriteReqMasterType is + variable ret : RoceDmaWriteReqMasterType; begin - ret.ready := ready; + ret.valid := valid; + ret.initiator := d(418 downto 415); + ret.sQpn := d(414 downto 391); + ret.startAddr := d(390 downto 327); + ret.len := d(326 downto 314); + ret.psn := d(313 downto 290); + ret.dataStream := d(289 downto 0); return ret; - end function ToDmaReadReqSlaveType; + end function SlvToDmaWriteReq; - function DmaReadReqToAxiStreamMaster ( - wrIn : RoceDmaReadReqMasterType) - return AxiStreamMasterType is + function DmaWriteReqToAxiStream (req : RoceDmaWriteReqMasterType) return AxiStreamMasterType is variable ret : AxiStreamMasterType; - begin -- function RoceWorkReqToAxiStream + begin ret := AXI_STREAM_MASTER_INIT_C; - ret.tValid := wrIn.valid; - ret.tData(169 downto 0) := wrIn.initiator & - wrIn.sQpn & - wrIn.wrId & - wrIn.startAddr & - wrIn.len & - wrIn.mrIdx; + ret.tValid := req.valid; + ret.tData(418 downto 0) := DmaWriteReqToSlv(req); + ret.tLast := '1'; return ret; - end function DmaReadReqToAxiStreamMaster; + end function DmaWriteReqToAxiStream; - function DmaReadReqToAxiStreamSlave ( - wrIn : RoceDmaReadReqSlaveType) - return AxiStreamSlaveType is - variable ret : AxiStreamSlaveType; - begin -- function RoceWorkReqToAxiStream - ret.tReady := wrIn.ready; - return ret; - end function DmaReadReqToAxiStreamSlave; + function AxiStreamToDmaWriteReq (axis : AxiStreamMasterType) return RoceDmaWriteReqMasterType is + begin + return SlvToDmaWriteReq(axis.tValid, axis.tData(418 downto 0)); + end function AxiStreamToDmaWriteReq; - function AxiStreamToDmaReadReqMaster ( - wrIn : AxiStreamMasterType) - return RoceDmaReadReqMasterType is - variable ret : RoceDmaReadReqMasterType; - begin -- function AxiStreamToRoceWorkReq - ret.valid := wrIn.tValid; - ret.mrIdx := wrIn.tData(0); - ret.len := wrIn.tData(13 downto 1); - ret.startAddr := wrIn.tData(77 downto 14); - ret.wrId := wrIn.tData(141 downto 78); - ret.sQpn := wrIn.tData(165 downto 142); - ret.initiator := wrIn.tData(169 downto 166); + --------------------------------------------------------------------------- + -- DmaWriteResp (53b): initiator[52:49] sQpn[48:25] psn[24:1] isRespErr[0] + --------------------------------------------------------------------------- + function DmaWriteRespToSlv (resp : RoceDmaWriteRespMasterType) return slv is + begin + return resp.initiator & resp.sQpn & resp.psn & resp.isRespErr; + end function DmaWriteRespToSlv; + + function SlvToDmaWriteResp (valid : sl; d : slv(52 downto 0)) return RoceDmaWriteRespMasterType is + variable ret : RoceDmaWriteRespMasterType; + begin + ret.valid := valid; + ret.initiator := d(52 downto 49); + ret.sQpn := d(48 downto 25); + ret.psn := d(24 downto 1); + ret.isRespErr := d(0); return ret; - end function AxiStreamToDmaReadReqMaster; - - function AxiStreamToDmaReadReqSlave ( - wrIn : AxiStreamSlaveType) - return RoceDmaReadReqSlaveType is - variable ret : RoceDmaReadReqSlaveType; - begin -- function AxiStreamToRoceWorkReq - ret.ready := wrIn.tReady; + end function SlvToDmaWriteResp; + + function DmaWriteRespToAxiStream (resp : RoceDmaWriteRespMasterType) return AxiStreamMasterType is + variable ret : AxiStreamMasterType; + begin + ret := AXI_STREAM_MASTER_INIT_C; + ret.tValid := resp.valid; + ret.tData(52 downto 0) := DmaWriteRespToSlv(resp); + ret.tLast := '1'; return ret; - end function AxiStreamToDmaReadReqSlave; - - -- function FromRoceWorkReqSlaveType ( - -- roceWorkReqSlave : RoceWorkReqSlaveType) - -- return sl is - -- begin - -- return roceWorkReqSlave.tReady; - -- end function FromRoceWorkReqSlaveType; - - -- function ToRoceWorkCompMasterType ( - -- valid : sl; - -- id : slv(63 downto 0); - -- opCode : slv(7 downto 0); - -- flags : slv(6 downto 0); - -- status : slv(4 downto 0); - -- len : slv(31 downto 0); - -- pKey : slv(15 downto 0); - -- qpn : slv(23 downto 0); - -- immDt : slv(32 downto 0); - -- rKeyToInv : slv(32 downto 0)) - -- return RoceWorkCompMasterType is - -- variable ret : RoceWorkCompMasterType; - -- begin -- function ToRoceWorkCompMasterType - -- ret.valid := valid; - -- ret.id := id; - -- ret.opCode := opCode; - -- ret.flags := flags; - -- ret.status := status; - -- ret.len := len; - -- ret.pKey := pKey; - -- ret.qpn := qpn; - -- ret.immDt := immDt; - -- ret.rKeyToInv := rKeyToInv; - -- return ret; - -- end function ToRoceWorkCompMasterType; + end function DmaWriteRespToAxiStream; + function AxiStreamToDmaWriteResp (axis : AxiStreamMasterType) return RoceDmaWriteRespMasterType is + begin + return SlvToDmaWriteResp(axis.tValid, axis.tData(52 downto 0)); + end function AxiStreamToDmaWriteResp; end package body RocePkg; diff --git a/ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd b/ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd deleted file mode 100755 index 3c0408821b..0000000000 --- a/ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd +++ /dev/null @@ -1,357 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Modified version of AxiStreamResize.vhd --- that will be optimized for RoCEv2 in the future -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; - -library surf; -use surf.StdRtlPkg.all; -use surf.AxiStreamPkg.all; - -entity RoceResizeAndSwap is - generic ( - -- General Configurations - TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset - RST_ASYNC_G : boolean := false; - READY_EN_G : boolean := true; - PIPE_STAGES_G : natural := 0; - SIDE_BAND_WIDTH_G : positive := 1; -- General purpose sideband - SWAP_ENDIAN_G : boolean := false; - LITTLE_ENDIAN_G : boolean := true; - - -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G : AxiStreamConfigType; - MASTER_AXI_CONFIG_G : AxiStreamConfigType); - port ( - - -- Clock and reset - axisClk : in sl; - axisRst : in sl; - - -- Slave Port - sAxisMaster : in AxiStreamMasterType; - sSideBand : in slv(SIDE_BAND_WIDTH_G-1 downto 0) := (others => '0'); - sAxisSlave : out AxiStreamSlaveType; - - -- Master Port - mAxisMaster : out AxiStreamMasterType; - mSideBand : out slv(SIDE_BAND_WIDTH_G-1 downto 0); - mAxisSlave : in AxiStreamSlaveType); -end RoceResizeAndSwap; - -architecture rtl of RoceResizeAndSwap is - - constant SLV_BYTES_C : positive := SLAVE_AXI_CONFIG_G.TDATA_BYTES_C; - constant MST_BYTES_C : positive := MASTER_AXI_CONFIG_G.TDATA_BYTES_C; - - constant SLV_USER_C : positive := ite(SLAVE_AXI_CONFIG_G.TUSER_BITS_C /= 0, SLAVE_AXI_CONFIG_G.TUSER_BITS_C, 1); - constant MST_USER_C : positive := ite(MASTER_AXI_CONFIG_G.TUSER_BITS_C /= 0, MASTER_AXI_CONFIG_G.TUSER_BITS_C, 1); - - constant COUNT_C : positive := ite(SLV_BYTES_C > MST_BYTES_C, SLV_BYTES_C / MST_BYTES_C, MST_BYTES_C / SLV_BYTES_C); - - type RegType is record - count : slv(bitSize(COUNT_C)-1 downto 0); - obMaster : AxiStreamMasterType; - sideBand : slv(SIDE_BAND_WIDTH_G-1 downto 0); - ibSlave : AxiStreamSlaveType; - end record RegType; - - constant REG_INIT_C : RegType := ( - count => (others => '0'), - obMaster => axiStreamMasterInit(MASTER_AXI_CONFIG_G), - sideBand => (others => '0'), - ibSlave => AXI_STREAM_SLAVE_INIT_C - ); - - signal r : RegType := REG_INIT_C; - signal rin : RegType; - - signal pipeAxisMaster : AxiStreamMasterType; - signal pipeSideBand : slv(SIDE_BAND_WIDTH_G-1 downto 0); - signal pipeAxisSlave : AxiStreamSlaveType; - - function ChangeEndian(vec : std_logic_vector) return std_logic_vector is - variable vRet : std_logic_vector(vec'range); - variable j : natural; - constant cNumBytes : natural := vec'length / 8; - begin - for i in 0 to cNumBytes-1 loop - j := cNumBytes-1-i; - vRet(((8*j)+7+vec'low) downto (8*j+vec'low)) := vec(((8*i)+7+vec'low) downto (8*i+vec'low)); - end loop; -- i - return vRet; - end function ChangeEndian; - - function ReverseBits(vec : std_logic_vector) return std_logic_vector is - variable vRet : std_logic_vector(vec'range); - variable j : natural; - constant cNumBits : natural := vec'length; - begin - for i in 0 to cNumBits-1 loop - j := cNumBits-1-i; - vRet(j+vec'low) := vec(i+vec'low); - end loop; -- i - return vRet; - end function ReverseBits; - -begin - - -- Make sure data widths are appropriate. - assert ((SLV_BYTES_C >= MST_BYTES_C and SLV_BYTES_C mod MST_BYTES_C = 0) or - (MST_BYTES_C >= SLV_BYTES_C and MST_BYTES_C mod SLV_BYTES_C = 0)) - report "Data widths must be even number multiples of each other" severity failure; - - -- When going from a large bus to a small bus, ready is necessary - assert (SLV_BYTES_C <= MST_BYTES_C or READY_EN_G = true) - report "READY_EN_G must be true if slave width is great than master" severity failure; - - -- Can't use tkeep_fixed on master side when resizing or if not on slave side - assert (not (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_FIXED_C and - SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_FIXED_C)) - report "AxiStreamResize: Can't have TKEEP_MODE = TKEEP_FIXED on master side if not on slave side" - severity failure; - - comb : process (pipeAxisSlave, r, sAxisMaster, sSideBand) is - variable v : RegType; - variable ibM : AxiStreamMasterType; - variable ibSide : slv(SIDE_BAND_WIDTH_G-1 downto 0); - variable idx : integer; -- index version of counter - variable idxResize : integer; -- index version of counter - variable byteCnt : integer; -- Number of valid bytes in incoming bus - variable bytes : integer; -- byte version of counter - begin - v := r; - idx := conv_integer(r.count); - idxResize := COUNT_C - 1 - idx; - bytes := (idx+1) * MST_BYTES_C; - if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - byteCnt := conv_integer(sAxisMaster.tKeep(bitSize(SLAVE_AXI_CONFIG_G.TDATA_BYTES_C)-1 downto 0)); - else - byteCnt := getTKeep(sAxisMaster.tKeep, SLAVE_AXI_CONFIG_G); - end if; - - -- Init ready - v.ibSlave.tReady := '0'; - - -- Choose ready source and clear valid - if READY_EN_G = false or pipeAxisSlave.tReady = '1' then - v.obMaster.tValid := '0'; - end if; - - -- Inbound data with normalized user bits (8 user bits) - ibM := sAxisMaster; - ibSide := sSideBand; - ibM.tUser := (others => '0'); - if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - ibM.tKeep := genTKeep(byteCnt); - end if; - - -- Check that both master and slave using tUser - if (SLAVE_AXI_CONFIG_G.TUSER_BITS_C /= 0) and - (MASTER_AXI_CONFIG_G.TUSER_BITS_C /= 0) and - (SLAVE_AXI_CONFIG_G.TUSER_MODE_C /= TUSER_NONE_C) and - (MASTER_AXI_CONFIG_G.TUSER_MODE_C /= TUSER_NONE_C) then - -- Loop through the tUser bit field - for i in 0 to AXI_STREAM_MAX_TKEEP_WIDTH_C-1 loop - ibM.tUser((i*8)+(SLV_USER_C-1) downto (i*8)) := sAxisMaster.tUser((i*SLV_USER_C)+(SLV_USER_C-1) downto (i*SLV_USER_C)); - end loop; - end if; - - -- Pipeline advance - if v.obMaster.tValid = '0' then - - -- Increasing size - if MST_BYTES_C > SLV_BYTES_C then - v.ibSlave.tReady := '1'; - - -- init when count = 0 - if (r.count = 0) then - v.obMaster := axiStreamMasterInit(MASTER_AXI_CONFIG_G); - v.obMaster.tKeep := (others => '0'); - v.obMaster.tStrb := (others => '0'); - end if; - - if SWAP_ENDIAN_G then - if LITTLE_ENDIAN_G then - v.obMaster.tData((SLV_BYTES_C*8*idx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*idx)) := ChangeEndian(ibM.tData((SLV_BYTES_C*8)-1 downto 0)); - v.obMaster.tKeep((SLV_BYTES_C*idx)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*idx)) := ReverseBits(ibM.tKeep(SLV_BYTES_C-1 downto 0)); - else - v.obMaster.tData((SLV_BYTES_C*8*idxResize)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*idxResize)) := ChangeEndian(ibM.tData((SLV_BYTES_C*8)-1 downto 0)); - v.obMaster.tKeep((SLV_BYTES_C*idxResize)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*idxResize)) := ReverseBits(ibM.tKeep(SLV_BYTES_C-1 downto 0)); - end if; - else - if LITTLE_ENDIAN_G then - v.obMaster.tData((SLV_BYTES_C*8*idx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*idx)) := ibM.tData((SLV_BYTES_C*8)-1 downto 0); - v.obMaster.tKeep((SLV_BYTES_C*idx)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*idx)) := ibM.tKeep(SLV_BYTES_C-1 downto 0); - else - v.obMaster.tData((SLV_BYTES_C*8*idxResize)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*idxResize)) := ibM.tData((SLV_BYTES_C*8)-1 downto 0); - v.obMaster.tKeep((SLV_BYTES_C*idxResize)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*idxResize)) := ibM.tKeep(SLV_BYTES_C-1 downto 0); - end if; - end if; - v.obMaster.tUser((SLV_BYTES_C*8*idx)+((SLV_BYTES_C*8)-1) downto (SLV_BYTES_C*8*idx)) := ibM.tUser((SLV_BYTES_C*8)-1 downto 0); - v.obMaster.tStrb((SLV_BYTES_C*idx)+(SLV_BYTES_C-1) downto (SLV_BYTES_C*idx)) := ibM.tStrb(SLV_BYTES_C-1 downto 0); - - v.obMaster.tId := ibM.tId; - v.obMaster.tDest := ibM.tDest; - v.obMaster.tLast := ibM.tLast; - v.sideBand := ibSide; - - -- Determine if we move data - if ibM.tValid = '1' then - if r.count = (COUNT_C-1) or ibM.tLast = '1' then - v.obMaster.tValid := '1'; - v.count := (others => '0'); - else - v.count := r.count + 1; - end if; - end if; - - -- Decreasing size - else - - v.obMaster := axiStreamMasterInit(MASTER_AXI_CONFIG_G); - - if SWAP_ENDIAN_G then - if LITTLE_ENDIAN_G then - v.obMaster.tData((MST_BYTES_C*8)-1 downto 0) := ChangeEndian(ibM.tData((MST_BYTES_C*8*idx)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*idx))); - v.obMaster.tKeep(MST_BYTES_C-1 downto 0) := ReverseBits(ibM.tKeep((MST_BYTES_C*idx)+(MST_BYTES_C-1) downto (MST_BYTES_C*idx))); - else - v.obMaster.tData((MST_BYTES_C*8)-1 downto 0) := ChangeEndian(ibM.tData((MST_BYTES_C*8*idxResize)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*idxResize))); - v.obMaster.tKeep(MST_BYTES_C-1 downto 0) := ReverseBits(ibM.tKeep((MST_BYTES_C*idxResize)+(MST_BYTES_C-1) downto (MST_BYTES_C*idxResize))); - end if; - else - if LITTLE_ENDIAN_G then - v.obMaster.tData((MST_BYTES_C*8)-1 downto 0) := ibM.tData((MST_BYTES_C*8*idx)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*idx)); - v.obMaster.tKeep(MST_BYTES_C-1 downto 0) := ibM.tKeep((MST_BYTES_C*idx)+(MST_BYTES_C-1) downto (MST_BYTES_C*idx)); - else - v.obMaster.tData((MST_BYTES_C*8)-1 downto 0) := ibM.tData((MST_BYTES_C*8*idxResize)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*idxResize)); - v.obMaster.tKeep(MST_BYTES_C-1 downto 0) := ibM.tKeep((MST_BYTES_C*idxResize)+(MST_BYTES_C-1) downto (MST_BYTES_C*idxResize)); - end if; - end if; - v.obMaster.tUser((MST_BYTES_C*8)-1 downto 0) := ibM.tUser((MST_BYTES_C*8*idx)+((MST_BYTES_C*8)-1) downto (MST_BYTES_C*8*idx)); - v.obMaster.tStrb(MST_BYTES_C-1 downto 0) := ibM.tStrb((MST_BYTES_C*idx)+(MST_BYTES_C-1) downto (MST_BYTES_C*idx)); - - v.obMaster.tId := ibM.tId; - v.obMaster.tDest := ibM.tDest; - v.sideBand := ibSide; - - -- Determine if we move data - if ibM.tValid = '1' then - if (r.count = (COUNT_C-1)) or ((bytes >= byteCnt) and (ibM.tLast = '1')) then - v.count := (others => '0'); - v.ibSlave.tReady := '1'; - v.obMaster.tLast := ibM.tLast; - else - v.count := r.count + 1; - v.ibSlave.tReady := '0'; - v.obMaster.tLast := '0'; - end if; - end if; - - -- Drop transfers with no tKeep bits set, except on tLast - v.obMaster.tValid := ibM.tValid and (uOr(v.obMaster.tKeep(COUNT_C-1 downto 0)) or v.obMaster.tLast); - - end if; - end if; - - -- Resize disabled - if SLV_BYTES_C = MST_BYTES_C then - sAxisSlave <= pipeAxisSlave; - pipeAxisMaster <= sAxisMaster; - pipeSideBand <= sSideBand; - - -- Check for TKEEP_COUNT_C mode on either side - if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) or (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - - -- Check for TKEEP_COUNT_C mode on slave side only - if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) and (MASTER_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_COUNT_C) then - pipeAxisMaster.tkeep <= genTKeep(conv_integer(sAxisMaster.tkeep(bitSize(SLAVE_AXI_CONFIG_G.TDATA_BYTES_C)-1 downto 0))); - - -- Check for TKEEP_COUNT_C mode on master side only - elsif (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C /= TKEEP_COUNT_C) and (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - pipeAxisMaster.tkeep <= toSlv(getTKeep(sAxisMaster.tKeep, SLAVE_AXI_CONFIG_G), AXI_STREAM_MAX_TKEEP_WIDTH_C); - - -- Else both sides are TKEEP_COUNT_C mode - else - null; - end if; - end if; - - -- Outbound data with proper user bits - pipeAxisMaster.tUser <= (others => '0'); - for i in 0 to AXI_STREAM_MAX_TKEEP_WIDTH_C-1 loop - if (SLV_USER_C > MST_USER_C) then - pipeAxisMaster.tUser((i*MST_USER_C)+(MST_USER_C-1) downto (i*MST_USER_C)) <= ibM.tUser((i*8)+(MST_USER_C-1) downto (i*8)); - else - pipeAxisMaster.tUser((i*MST_USER_C)+(SLV_USER_C-1) downto (i*MST_USER_C)) <= ibM.tUser((i*8)+(SLV_USER_C-1) downto (i*8)); - end if; - end loop; - - else - sAxisSlave <= v.ibSlave; - - -- Outbound data with proper user bits - pipeAxisMaster <= r.obMaster; - pipeSideBand <= r.sideBand; - pipeAxisMaster.tUser <= (others => '0'); - if (MASTER_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then - pipeAxisMaster.tKeep <= toSlv(getTKeep(r.obMaster.tKeep, MASTER_AXI_CONFIG_G), AXI_STREAM_MAX_TKEEP_WIDTH_C); - end if; - - for i in 0 to AXI_STREAM_MAX_TKEEP_WIDTH_C-1 loop - pipeAxisMaster.tUser((i*MST_USER_C)+(MST_USER_C-1) downto (i*MST_USER_C)) <= r.obMaster.tUser((i*8)+(MST_USER_C-1) downto (i*8)); - end loop; - end if; - - rin <= v; - - end process comb; - - seq : process (axisClk, axisRst) is - begin - if (RST_ASYNC_G) and (axisRst = RST_POLARITY_G or (SLV_BYTES_C = MST_BYTES_C)) then - r <= REG_INIT_C after TPD_G; - elsif (rising_edge(axisClk)) then - if (RST_ASYNC_G = false) and (axisRst = RST_POLARITY_G or (SLV_BYTES_C = MST_BYTES_C)) then - r <= REG_INIT_C after TPD_G; - else - r <= rin after TPD_G; - end if; - end if; - end process seq; - - -- Optional output pipeline registers to ease timing - AxiStreamPipeline_1 : entity surf.AxiStreamPipeline - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => RST_POLARITY_G, - RST_ASYNC_G => RST_ASYNC_G, - SIDE_BAND_WIDTH_G => SIDE_BAND_WIDTH_G, - PIPE_STAGES_G => PIPE_STAGES_G) - port map ( - axisClk => axisClk, - axisRst => axisRst, - sAxisMaster => pipeAxisMaster, - sSideBand => pipeSideBand, - sAxisSlave => pipeAxisSlave, - mAxisMaster => mAxisMaster, - mSideBand => mSideBand, - mAxisSlave => mAxisSlave); - -end rtl; - diff --git a/ethernet/RoCEv2/rtl/Rq.vhd b/ethernet/RoCEv2/rtl/Rq.vhd new file mode 100644 index 0000000000..ca01332ecb --- /dev/null +++ b/ethernet/RoCEv2/rtl/Rq.vhd @@ -0,0 +1,462 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Structural / wiring container — NOT a two-process FSM. mkRQ owns no +-- registered state and no datapath logic (RegType/comb/seq intentionally +-- absent, per Rq.fsm.md and OQ-FSM-RQTOP-01). It: +-- * instantiates four child entities: +-- U_DupReadAtomicCache, U_PayloadConsumer, U_ReqHandleRq, U_WorkCompGenRq +-- * wires them to each other and to this entity's module-argument ports +-- (contextRQ / payloadGenerator / dmaWriteCntrl / permCheckSrv / +-- recvReqBuf / reqPktPipeIn are BSV module arguments -> external +-- interface ports here, NOT sub-entities; same pattern as OQ-FSM-SQ-02) +-- * forwards three interface members outward +-- (rdmaRespDataStreamPipeOut, workCompRQ, respHeaderOutNotEmpty) +-- * carries the single reset-driven clear pulse +-- resetAndClear (BSV 304-309): isReset -> U_DupReadAtomicCache.clear +-- +-- NOTE (mapping.json is stale for this entity — use Rq.fsm.md): +-- mapping.json lists {ReqHandleRq, PayloadConsumerConAndGen, +-- DupReadAtomicCache, AtomicSrvConAndGen} with rules=[]. Source shows NO +-- AtomicSrv instance and DOES instantiate WorkCompGenRq, plus the one +-- resetAndClear rule. Correct child set is +-- {DupReadAtomicCache, PayloadConsumerConAndGen, ReqHandleRq, WorkCompGenRq}. +-- (OQ-FSM-RQTOP-01, RESOLVED — use the fsm.md.) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity Rq is + generic ( + TPD_G : time := 1 ns; + -- false = no RDMA READ/atomic serving: U_DupReadAtomicCache is not + -- generated (its client faces are tied inert) and ReqHandleRq NAKs + -- incoming READ/atomic requests as unsupported (INV_REQ). + EN_READ_G : boolean := true); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + ----------------------------------------------------------------------- + -- contextRQ.statusRQ.comm status methods (shared, fanned to children) + ----------------------------------------------------------------------- + isReset : in sl; -- comm.isReset (guards resetAndClear) + isNonErr : in sl; -- comm.isNonErr + isERR : in sl; -- comm.isERR + getTypeQP : in slv(3 downto 0); -- TypeQP enum + getPMTU : in slv(2 downto 0); -- PMTU enum (also -> DupReadAtomicCache.pmtu) + getPKEY : in slv(15 downto 0); + getSQPN : in slv(23 downto 0); + getDQPN : in slv(23 downto 0); + getMinRnrTimer : in slv(4 downto 0); + getAccessFlags : in slv(7 downto 0); + getPendingWorkReqNum : in slv(7 downto 0); + getPendingDestReadAtomicReqNum : in slv(7 downto 0); + ----------------------------------------------------------------------- + -- contextRQ shared registers (external RMW; -> U_ReqHandleRq only) + ----------------------------------------------------------------------- + getEpoch : in sl; + incEpoch : out sl; + getEPSN : in slv(23 downto 0); + getRespPktNum : in slv(24 downto 0); + setRespPktNumValid : out sl; + setRespPktNumData : out slv(24 downto 0); + getIsRespPktNumZero : in sl; + setEPSNValid : out sl; + setEPSNData : out slv(23 downto 0); + getPreReqOpCode : in slv(4 downto 0); + setPreReqOpCodeValid : out sl; + setPreReqOpCodeData : out slv(4 downto 0); + restoreValid : out sl; + restorePreOpCodeData : out slv(4 downto 0); + restorePsnData : out slv(23 downto 0); + getPermCheckReq : in slv(266 downto 0); + setPermCheckReqValid : out sl; + setPermCheckReqData : out slv(266 downto 0); + getNextDmaWriteAddr : in slv(63 downto 0); + setNextDmaWriteAddrValid : out sl; + setNextDmaWriteAddrData : out slv(63 downto 0); + getSendWriteReqPktNum : in slv(24 downto 0); + setSendWriteReqPktNumValid : out sl; + setSendWriteReqPktNumData : out slv(24 downto 0); + getRemainingDmaWriteLen : in slv(31 downto 0); + setRemainingDmaWriteLenValid : out sl; + setRemainingDmaWriteLenData : out slv(31 downto 0); + getTotalDmaWriteLen : in slv(31 downto 0); + setTotalDmaWriteLenValid : out sl; + setTotalDmaWriteLenData : out slv(31 downto 0); + getCurRespPSN : in slv(23 downto 0); + setCurRespPSNValid : out sl; + setCurRespPSNData : out slv(23 downto 0); + getMSN : in slv(23 downto 0); + setMSNValid : out sl; + setMSNData : out slv(23 downto 0); + ----------------------------------------------------------------------- + -- payloadGenerator : Server + DataStream (module arg -> U_ReqHandleRq) + ----------------------------------------------------------------------- + payloadGenReqValid : out sl; + payloadGenReqData : out slv(198 downto 0); + payloadGenReqReady : in sl; + payloadGenRespValid : in sl; + payloadGenRespData : in slv(1 downto 0); + payloadGenRespGetEn : out sl; + payloadDataStreamValid : in sl; + payloadDataStreamData : in slv(289 downto 0); + payloadDataStreamRdEn : out sl; + ----------------------------------------------------------------------- + -- permCheckSrv : Server#(PermCheckReq (267b), Bool) (module arg -> U_ReqHandleRq) + ----------------------------------------------------------------------- + permReqValid : out sl; + permReqData : out slv(266 downto 0); + permReqReady : in sl; + permRespValid : in sl; + permRespData : in sl; + permRespGetEn : out sl; + ----------------------------------------------------------------------- + -- recvReqBuf : RecvReqBuf (RecvReq 216b) (module arg -> U_ReqHandleRq) + ----------------------------------------------------------------------- + recvReqValid : in sl; + recvReqData : in slv(215 downto 0); + recvReqDeq : out sl; + ----------------------------------------------------------------------- + -- reqPktPipeIn.pktMetaData : PipeOut#(RdmaPktMetaData) (649b) (-> U_ReqHandleRq) + ----------------------------------------------------------------------- + pktMetaValid : in sl; + pktMetaData : in slv(648 downto 0); + pktMetaDeq : out sl; + ----------------------------------------------------------------------- + -- reqPktPipeIn.payload : DataStreamPipeOut (290b) (-> U_PayloadConsumer) + ----------------------------------------------------------------------- + payloadPipeInValid : in sl; + payloadPipeInData : in slv(289 downto 0); + payloadPipeInReady : out sl; + ----------------------------------------------------------------------- + -- dmaWriteCntrl : DmaWriteSrv (module arg -> U_PayloadConsumer, CLIENT) + ----------------------------------------------------------------------- + dmaWriteReqValid : out sl; + dmaWriteReqData : out slv(418 downto 0); + dmaWriteReqReady : in sl; + dmaWriteRespValid : in sl; + dmaWriteRespData : in slv(52 downto 0); + dmaWriteRespReady : out sl; + ----------------------------------------------------------------------- + -- Forwarded outputs (interface members of RQ) + ----------------------------------------------------------------------- + -- rdmaRespDataStreamPipeOut = U_ReqHandleRq.rdmaRespDataStreamPipeOut (290b) + rdmaRespDataStreamValid : out sl; + rdmaRespDataStreamData : out slv(289 downto 0); + rdmaRespDataStreamRdEn : in sl; + -- respHeaderOutNotEmpty() = U_ReqHandleRq.respHeaderOutNotEmpty (Bool method) + respHeaderOutNotEmpty : out sl; + -- workCompRQ = U_WorkCompGenRq (WorkCompGen interface: WorkComp 222b + hasErr) + workCompValid : out sl; + workCompData : out slv(221 downto 0); + workCompRdEn : in sl; + workCompHasErr : out sl); +end entity Rq; + +architecture rtl of Rq is + + -- No RegType / REG_INIT_C / comb / seq: mkRQ is a pure structural container + -- (Rq.fsm.md: "no registered state, no datapath logic"). Below are only the + -- internal child-to-child interconnect signals and one clear-merge. + + ------------------------------------------------------------------------------ + -- U_ReqHandleRq.payloadConReqPort <-> U_PayloadConsumer.request (PayloadConReq 203b) + ------------------------------------------------------------------------------ + signal payloadConReqValid : sl; + signal payloadConReqData : slv(202 downto 0); + signal payloadConReqReady : sl; + + ------------------------------------------------------------------------------ + -- U_PayloadConsumer.response <-> U_WorkCompGenRq.payloadConRespPort (PayloadConResp 53b) + ------------------------------------------------------------------------------ + signal payloadConRespValid : sl; + signal payloadConRespData : slv(52 downto 0); + signal payloadConRespGetEn : sl; + + ------------------------------------------------------------------------------ + -- U_ReqHandleRq.workCompGenReqPipeOut <-> U_WorkCompGenRq.wcGenReqPipeInFromRQ (198b) + ------------------------------------------------------------------------------ + signal workCompGenReqValid : sl; + signal workCompGenReqData : slv(197 downto 0); + signal workCompGenReqDeq : sl; + + ------------------------------------------------------------------------------ + -- U_ReqHandleRq <-> U_DupReadAtomicCache (dupReadAtomicCache methods) + ------------------------------------------------------------------------------ + signal insertReadValid : sl; + signal insertReadData : slv(175 downto 0); + signal insertReadReady : sl; + signal searchReadReqValid : sl; + signal searchReadReqData : slv(175 downto 0); + signal searchReadReqReady : sl; + signal searchReadRespValid : sl; + signal searchReadRespData : slv(241 downto 0); + signal searchReadRespGetEn : sl; + signal insertAtomicValid : sl; + signal insertAtomicData : slv(316 downto 0); + signal insertAtomicReady : sl; + signal searchAtomicReqValid : sl; + signal searchAtomicReqData : slv(316 downto 0); + signal searchAtomicReqReady : sl; + signal searchAtomicRespValid : sl; + signal searchAtomicRespData : slv(317 downto 0); + signal searchAtomicRespGetEn : sl; + + -- clear() has two BSV callers that both reduce to isReset: + -- * mkRQ.resetAndClear rule (isReset) [Rq.fsm.md] + -- * U_ReqHandleRq.dupCacheClear output (= isReset internally) + -- The faithful merge of multiple Action-method callers is an OR. + signal dupCacheClear : sl; -- from U_ReqHandleRq + signal dupCacheClearAll : sl; -- isReset OR dupCacheClear -> U_DupReadAtomicCache.clearEn + +begin + + ------------------------------------------------------------------------------ + -- resetAndClear (BSV 304-309): isReset -> DupReadAtomicCache.clear. + -- Level-driven combinational pulse (no_implicit_conditions, fire_when_enabled). + ------------------------------------------------------------------------------ + dupCacheClearAll <= isReset or dupCacheClear; + + ------------------------------------------------------------------------------ + -- U_DupReadAtomicCache : constructed with contextRQ.statusRQ.comm.getPMTU + ------------------------------------------------------------------------------ + -- Pruned when EN_READ_G=false: ReqHandleRq's forced classifiers guarantee + -- the insert/search request valids below never assert, so the tied readies + -- are never observed and the responses are never consumed. + GEN_NO_DUP_CACHE : if not EN_READ_G generate + insertReadReady <= '1'; + searchReadReqReady <= '1'; + searchReadRespValid <= '0'; + searchReadRespData <= (others => '0'); + insertAtomicReady <= '1'; + searchAtomicReqReady <= '1'; + searchAtomicRespValid <= '0'; + searchAtomicRespData <= (others => '0'); + end generate GEN_NO_DUP_CACHE; + + GEN_DUP_CACHE : if EN_READ_G generate + U_DupReadAtomicCache : entity surf.DupReadAtomicCache + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + pmtu => getPMTU, -- construct arg getPMTU + insertReadEn => insertReadValid, + insertReadData => insertReadData, + insertReadReady => insertReadReady, + searchReadReqEn => searchReadReqValid, + searchReadReqData => searchReadReqData, + searchReadReqReady => searchReadReqReady, + searchReadRespValid => searchReadRespValid, + searchReadRespData => searchReadRespData, + searchReadRespRdEn => searchReadRespGetEn, + insertAtomicEn => insertAtomicValid, + insertAtomicData => insertAtomicData, + insertAtomicReady => insertAtomicReady, + searchAtomicReqEn => searchAtomicReqValid, + searchAtomicReqData => searchAtomicReqData, + searchAtomicReqReady => searchAtomicReqReady, + searchAtomicRespValid => searchAtomicRespValid, + searchAtomicRespData => searchAtomicRespData, + searchAtomicRespRdEn => searchAtomicRespGetEn, + clearEn => dupCacheClearAll); + end generate GEN_DUP_CACHE; + + ------------------------------------------------------------------------------ + -- U_PayloadConsumer : mkPayloadConsumer(statusRQ, dmaWriteCntrl, reqPktPipeIn.payload) + ------------------------------------------------------------------------------ + U_PayloadConsumer : entity surf.PayloadConsumerConAndGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + isReset => isReset, + isNonErr => isNonErr, + isErr => isERR, + -- request : from U_ReqHandleRq + reqInValid => payloadConReqValid, + reqInData => payloadConReqData, + reqInReady => payloadConReqReady, + -- response : to U_WorkCompGenRq + respOutReady => payloadConRespGetEn, + respOutValid => payloadConRespValid, + respOutData => payloadConRespData, + -- payloadPipeIn : reqPktPipeIn.payload (external) + payloadPipeInValid => payloadPipeInValid, + payloadPipeInData => payloadPipeInData, + payloadPipeInReady => payloadPipeInReady, + -- dmaWriteSrv : dmaWriteCntrl (external CLIENT) + dmaWriteReqValid => dmaWriteReqValid, + dmaWriteReqData => dmaWriteReqData, + dmaWriteReqReady => dmaWriteReqReady, + dmaWriteRespValid => dmaWriteRespValid, + dmaWriteRespData => dmaWriteRespData, + dmaWriteRespReady => dmaWriteRespReady); + + ------------------------------------------------------------------------------ + -- U_ReqHandleRq : mkReqHandleRQ(contextRQ, payloadGenerator, permCheckSrv, + -- dupReadAtomicCache, recvReqBuf, reqPktPipeIn.pktMetaData, payloadConsumer.request) + ------------------------------------------------------------------------------ + U_ReqHandleRq : entity surf.ReqHandleRq + generic map ( + TPD_G => TPD_G, + EN_READ_G => EN_READ_G) + port map ( + clk => clk, + rst => rst, + -- contextRQ.statusRQ.comm status + isReset => isReset, + isNonErr => isNonErr, + isERR => isERR, + getTypeQP => getTypeQP, + getPMTU => getPMTU, + getPKEY => getPKEY, + getSQPN => getSQPN, + getDQPN => getDQPN, + getMinRnrTimer => getMinRnrTimer, + getAccessFlags => getAccessFlags, + getPendingWorkReqNum => getPendingWorkReqNum, + getPendingDestReadAtomicReqNum => getPendingDestReadAtomicReqNum, + -- contextRQ shared registers + getEpoch => getEpoch, + incEpoch => incEpoch, + getEPSN => getEPSN, + getRespPktNum => getRespPktNum, + setRespPktNumValid => setRespPktNumValid, + setRespPktNumData => setRespPktNumData, + getIsRespPktNumZero => getIsRespPktNumZero, + setEPSNValid => setEPSNValid, + setEPSNData => setEPSNData, + getPreReqOpCode => getPreReqOpCode, + setPreReqOpCodeValid => setPreReqOpCodeValid, + setPreReqOpCodeData => setPreReqOpCodeData, + restoreValid => restoreValid, + restorePreOpCodeData => restorePreOpCodeData, + restorePsnData => restorePsnData, + getPermCheckReq => getPermCheckReq, + setPermCheckReqValid => setPermCheckReqValid, + setPermCheckReqData => setPermCheckReqData, + getNextDmaWriteAddr => getNextDmaWriteAddr, + setNextDmaWriteAddrValid => setNextDmaWriteAddrValid, + setNextDmaWriteAddrData => setNextDmaWriteAddrData, + getSendWriteReqPktNum => getSendWriteReqPktNum, + setSendWriteReqPktNumValid => setSendWriteReqPktNumValid, + setSendWriteReqPktNumData => setSendWriteReqPktNumData, + getRemainingDmaWriteLen => getRemainingDmaWriteLen, + setRemainingDmaWriteLenValid => setRemainingDmaWriteLenValid, + setRemainingDmaWriteLenData => setRemainingDmaWriteLenData, + getTotalDmaWriteLen => getTotalDmaWriteLen, + setTotalDmaWriteLenValid => setTotalDmaWriteLenValid, + setTotalDmaWriteLenData => setTotalDmaWriteLenData, + getCurRespPSN => getCurRespPSN, + setCurRespPSNValid => setCurRespPSNValid, + setCurRespPSNData => setCurRespPSNData, + getMSN => getMSN, + setMSNValid => setMSNValid, + setMSNData => setMSNData, + -- pktMetaDataPipeIn : reqPktPipeIn.pktMetaData (external) + pktMetaValid => pktMetaValid, + pktMetaData => pktMetaData, + pktMetaDeq => pktMetaDeq, + -- recvReqBuf (external) + recvReqValid => recvReqValid, + recvReqData => recvReqData, + recvReqDeq => recvReqDeq, + -- payloadConReqPort : to U_PayloadConsumer.request + payloadConReqValid => payloadConReqValid, + payloadConReqData => payloadConReqData, + payloadConReqReady => payloadConReqReady, + -- permCheckSrv (external) + permReqValid => permReqValid, + permReqData => permReqData, + permReqReady => permReqReady, + permRespValid => permRespValid, + permRespData => permRespData, + permRespGetEn => permRespGetEn, + -- payloadGenerator (external) + payloadGenReqValid => payloadGenReqValid, + payloadGenReqData => payloadGenReqData, + payloadGenReqReady => payloadGenReqReady, + payloadGenRespValid => payloadGenRespValid, + payloadGenRespData => payloadGenRespData, + payloadGenRespGetEn => payloadGenRespGetEn, + payloadDataStreamValid => payloadDataStreamValid, + payloadDataStreamData => payloadDataStreamData, + payloadDataStreamRdEn => payloadDataStreamRdEn, + -- dupReadAtomicCache : to U_DupReadAtomicCache + insertReadValid => insertReadValid, + insertReadData => insertReadData, + insertReadReady => insertReadReady, + searchReadReqValid => searchReadReqValid, + searchReadReqData => searchReadReqData, + searchReadReqReady => searchReadReqReady, + searchReadRespValid => searchReadRespValid, + searchReadRespData => searchReadRespData, + searchReadRespGetEn => searchReadRespGetEn, + insertAtomicValid => insertAtomicValid, + insertAtomicData => insertAtomicData, + insertAtomicReady => insertAtomicReady, + searchAtomicReqValid => searchAtomicReqValid, + searchAtomicReqData => searchAtomicReqData, + searchAtomicReqReady => searchAtomicReqReady, + searchAtomicRespValid => searchAtomicRespValid, + searchAtomicRespData => searchAtomicRespData, + searchAtomicRespGetEn => searchAtomicRespGetEn, + dupCacheClear => dupCacheClear, + -- outputs + rdmaRespDataStreamValid => rdmaRespDataStreamValid, + rdmaRespDataStreamData => rdmaRespDataStreamData, + rdmaRespDataStreamRdEn => rdmaRespDataStreamRdEn, + workCompGenReqValid => workCompGenReqValid, + workCompGenReqData => workCompGenReqData, + workCompGenReqRdEn => workCompGenReqDeq, + respHeaderOutNotEmpty => respHeaderOutNotEmpty); + + ------------------------------------------------------------------------------ + -- U_WorkCompGenRq : mkWorkCompGenRQ(statusRQ, payloadConsumer.response, + -- reqHandlerRQ.workCompGenReqPipeOut) + ------------------------------------------------------------------------------ + U_WorkCompGenRq : entity surf.WorkCompGenRq + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + -- statusRQ.comm status + isReset_i => isReset, + isNonErr_i => isNonErr, + isERR_i => isERR, + getPKEY_i => getPKEY, + getSQPN_i => getSQPN, + -- payloadConRespPort : from U_PayloadConsumer.response + payloadConRespValid_i => payloadConRespValid, + payloadConRespData_i => payloadConRespData, + payloadConRespGetEn_o => payloadConRespGetEn, + -- wcGenReqPipeInFromRQ : from U_ReqHandleRq.workCompGenReqPipeOut + reqValid_i => workCompGenReqValid, + reqData_i => workCompGenReqData, + reqDeq_o => workCompGenReqDeq, + -- workCompPipeOut : forwarded to RQ.workCompRQ + workCompValid_o => workCompValid, + workCompData_o => workCompData, + workCompRdEn_i => workCompRdEn, + hasErr_o => workCompHasErr); + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ScanFifoF.vhd b/ethernet/RoCEv2/rtl/ScanFifoF.vhd new file mode 100644 index 0000000000..2fee4d3591 --- /dev/null +++ b/ethernet/RoCEv2/rtl/ScanFifoF.vhd @@ -0,0 +1,504 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Register-array FIFO with non-destructive sequential scan. +-- A bespoke FIFO (NOT a surf.Fifo instance: OQ-PART-05/OQ-02) built on a +-- register array dataVec[Q_SZ_G] indexed by three independent pointers +-- (enqPtr, deqPtr, scanPtr). Three top-level modes encoded in scanStateReg: +-- FIFO_S - normal enqueue/dequeue FIFO operation +-- PRE_SCAN_S - snapshot deqPtr->scanPtr and itemCnt->scanCnt; getHead / +-- modifyHead available; array is write-frozen (enq blocked) +-- SCAN_S - one entry per cycle is read from the array and pushed into +-- U_ScanOutQ; external consumer drains it via a PipeOut +-- handshake (scanOut{Valid,Data,Ready}). +-- +-- All control requests (enq/deq/clear/preScanStart/scanStart/scanStop/ +-- preScanRestart) are BSV CReg(2) pulse registers used as INTRA-CYCLE +-- forwarding: the method writes port-0 and the consuming rule reads port-1 +-- IN THE SAME CYCLE (BSV CReg ordering: write[0] SB read[1]), then writes +-- port-1 False. The registered value is therefore always False across clock +-- edges, and the pulses collapse to pure combinational strobes here — the +-- same conclusion OQ-FSM-02 reached for CountCF's writeReg/incrReg/decrReg. +-- +-- BUGFIX 2026-07-08 (SQ pendingCnt underflow under RoCE retry): a previous +-- revision registered these pulses and consumed them one cycle later, which +-- delayed every method effect (pop/push/clear/scan transitions) by one cycle +-- relative to BSV. fifoNotEmpty/fifoFirst then lagged a deq by one extra +-- cycle, letting RespHandleSq classify a back-to-back (duplicate) response +-- against an already-dequeued WorkReq and issue a second deq — an extra +-- deqPulse/decrement that underflowed NewPendingWorkReqPipeOut's pendingCnt. +-- With same-cycle semantics, deqPulse == deqEn (BSV: deqPulse() = popReg[1], +-- which sees the same-cycle deq() port-0 write) and all status outputs +-- update on the cycle AFTER the method strobe, exactly as in BSV. +-- +-- DELIBERATE DEVIATION (same bugfix, OQ-FSM-03 class): BSV exits scan mode +-- on the same cycle scanNext emits the last snapshot entry (scanDoneReg CReg +-- forwarding), relying on mkFIFOF's 1-cycle enq->deq latency for the +-- consumer to grab the tail element before fifoMode's every-cycle +-- scanOutQ.clear destroys it. surf.Fifo (FWFT) has ~2-cycle enq->valid +-- latency, so a cycle-exact exit would ALWAYS lose the last scanned entry +-- (a lost retransmit WR). Instead the FSM holds SCAN_S until the scan +-- output queue has fully drained (tracked by the outQOcc occupancy counter, +-- since the Fifo's own empty/valid flags lag writes). isScanDone therefore +-- asserts only after every scanned element has been delivered — a strictly +-- stronger contract than BSV that the retry protocol relies on anyway. +-- scanStop/preScanRestart still abort immediately and flush the queue. +-- +-- Generated from: +-- BSV source : src-bsv/SpecialFIFOF.bsv (module mkScanFIFOF, lines 43-330) +-- FSM spec : out/03-fsm/ScanFifoF.fsm.md +-- Mapping : out/02-partition/mapping.json (entity ScanFifoF) +-- +-- SURF components instantiated: +-- surf.Fifo (base/fifo/rtl/Fifo.vhd) x1 -> U_ScanOutQ (scan output queue) +-- +-- BSV FIFOF.clear on the scan output queue is modelled per OQ-FSM-01 / +-- OQ-FSM-06 (out/03-fsm/RESOLVED.md): surf.Fifo has no flush port, so clear +-- is a synchronous rst assertion (sync config, active-high rst). OQ-FSM-06 +-- confirms a HELD (level) assertion over FIFO_S is safe with the sync wrapper +-- (FifoSync wires rst straight through; release is next-cycle). +-- +-- OQ-FSM-05 applied: scanNext is suppressed when scanCnt = 0, so the single- +-- entry-scan underflow (reading dataVec beyond the snapshot) cannot occur. +-- +-- mkRegU fields (no BSV reset value): dataVec, scanPtrReg, headReg. +-- Initialised to all-'0' in REG_INIT_C; each is always written before it is +-- read. Don't-care at reset (mirrors OQ-FSM-04). BSV's scanAlmostDoneReg / +-- scanDoneReg pair is superseded by the drain-gated scanDone above. +------------------------------------------------------------------------------- +-- This file is part of the BSV->VHDL transpilation output. It targets the SURF +-- VHDL library and follows the SURF coding standard (style/vhdl-style-rules.md). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ScanFifoF is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset + RST_ASYNC_G : boolean := false; + MEMORY_TYPE_G : string := "distributed"; -- scan output queue backend + Q_SZ_G : positive := 4; -- FIFO depth (power of 2) + T_SZ_G : positive := 32); -- data width per entry + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- FIFOF enqueue side (fifof.enq) + enqEn : in sl; -- enq strobe + enqData : in slv(T_SZ_G-1 downto 0); -- data to enqueue + -- FIFOF dequeue / status side + deqEn : in sl; -- deq strobe + fifoFirst : out slv(T_SZ_G-1 downto 0); -- first() (comb read) + fifoNotEmpty : out sl; -- notEmpty() + fifoNotFull : out sl; -- notFull() + deqPulse : out sl; -- deqPulse() + fifoSize : out slv(log2(Q_SZ_G) downto 0); -- size() (itemCnt) + -- clear() method (either interface) + clearEn : in sl; + -- scan control (scanCntrl) + scanHead : out slv(T_SZ_G-1 downto 0); -- getHead() (PRE_SCAN) + modifyHeadEn : in sl; -- modifyHead strobe + modifyHeadData : in slv(T_SZ_G-1 downto 0); -- modifyHead value + preScanStartEn : in sl; -- preScanStart() + scanStartEn : in sl; -- scanStart() + scanStopEn : in sl; -- scanStop() + preScanRestartEn : in sl; -- preScanRestart() + hasScanOut : out sl; -- hasScanOut() + isScanDone : out sl; -- isScanDone() + -- scan output PipeOut (read side of U_ScanOutQ) + scanOutValid : out sl; -- scanOutQ valid + scanOutData : out slv(T_SZ_G-1 downto 0); -- scanOutQ dout + scanOutReady : in sl); -- -> scanOutQ rd_en +end ScanFifoF; + +architecture rtl of ScanFifoF is + + ----------------------------------------------------------------------------- + -- Constants (widths traced from BSV provisos) + -- ptrSz = TLog(qSz) ; cntSz = TLog(qSz+1) = ptrSz + 1 (qSz pow2) + -- headReg / pushReg width = 1 + tSz (Maybe#(a): MSB = valid bit) + ----------------------------------------------------------------------------- + constant PTR_SZ_C : integer := log2(Q_SZ_G); -- pointer width + constant CNT_SZ_C : integer := PTR_SZ_C + 1; -- item/scan count width + constant MAYBE_SZ_C : integer := T_SZ_G + 1; -- {valid, data} + + -- almostFull = all itemCnt bits except the MSB are '1' (itemCnt = Q_SZ_G-1) + constant ALMOST_FULL_C : slv(CNT_SZ_C-2 downto 0) := (others => '1'); + + constant FIFO_ADDR_WIDTH_C : integer := 4; -- surf.Fifo minimum + + ----------------------------------------------------------------------------- + -- Types + ----------------------------------------------------------------------------- + type ScanStateType is ( + FIFO_S, -- SCAN_Q_FIFOF_MODE = 0 + PRE_SCAN_S, -- SCAN_Q_PRE_SCAN_MODE = 1 + SCAN_S); -- SCAN_Q_SCAN_MODE = 2 + + type DataVecType is array (0 to Q_SZ_G-1) of slv(T_SZ_G-1 downto 0); + + type RegType is record + scanStateReg : ScanStateType; -- mkReg(FIFO mode) + dataVec : DataVecType; -- mkRegU (no reset) + enqPtrReg : slv(PTR_SZ_C-1 downto 0); -- mkReg(0) + deqPtrReg : slv(PTR_SZ_C-1 downto 0); -- mkReg(0) + scanPtrReg : slv(PTR_SZ_C-1 downto 0); -- mkRegU + fullReg : sl; -- mkReg(False) + emptyReg : sl; -- mkReg(True) + headReg : slv(MAYBE_SZ_C-1 downto 0); -- mkRegU {valid,data} + itemCnt : slv(CNT_SZ_C-1 downto 0); -- mkCount(0) + scanCnt : slv(CNT_SZ_C-1 downto 0); -- mkCount(0) + -- U_ScanOutQ occupancy (writes minus completed reads); gates the + -- drain-based scanDone exit (see header DEVIATION note). No BSV + -- counterpart — the Fifo's own empty/valid flags lag a write by 1-2 + -- cycles and cannot signal "truly drained" safely. + outQOcc : slv(FIFO_ADDR_WIDTH_C downto 0); + -- NOTE: the BSV CReg(2) control pulses (pushReg/popReg/clearReg/ + -- preScanStartReg/scanStartReg/scanStopReg/preScanRestartReg/ + -- scanDoneReg) are intra-cycle forwarding only (registered value is + -- always False) and are therefore NOT registered state — the input + -- strobes are consumed combinationally in the same cycle. + end record RegType; + + constant REG_INIT_C : RegType := ( + scanStateReg => FIFO_S, + dataVec => (others => (others => '0')), -- mkRegU: don't-care + enqPtrReg => (others => '0'), + deqPtrReg => (others => '0'), + scanPtrReg => (others => '0'), -- mkRegU: don't-care + fullReg => '0', + emptyReg => '1', + headReg => (others => '0'), -- mkRegU: Invalid + itemCnt => (others => '0'), + scanCnt => (others => '0'), + outQOcc => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_ScanOutQ (surf.Fifo) interface signals + signal scanOutQValid : sl; -- valid + signal scanOutQDout : slv(T_SZ_G-1 downto 0); -- dout + signal scanOutQNotFull : sl; -- not_full (enq guard) + signal scanOutQWrEn : sl; -- wr_en (scanNext enq) + signal scanOutQDin : slv(T_SZ_G-1 downto 0); -- din + signal scanOutQRdEn : sl; -- rd_en (consumer) + signal scanOutQClr : sl; -- clear strobe/level + + -- Clear / reset plumbing (OQ-FSM-01 / OQ-FSM-06) + signal scanOutQRst : sl; -- rst OR scanOutQClr + signal rstActiveHigh : sl; + +begin + + ----------------------------------------------------------------------------- + -- Scan output queue (BSV scanOutQ : FIFOF#(a)) + -- FSM (scanNext) drives the write side; external consumer drains the read + -- side via the PipeOut handshake. FWFT so dout/valid present without an + -- rd_en pulse (BSV first/deq peek semantics). + ----------------------------------------------------------------------------- + U_ScanOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', -- active-high (clear-via-rst, OQ-FSM-01) + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, -- single clock; next-cycle release + FWFT_EN_G => true, -- first/deq peek semantics + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => T_SZ_G, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C) + port map ( + rst => scanOutQRst, + wr_clk => clk, + wr_en => scanOutQWrEn, -- scanNext enq + din => scanOutQDin, + not_full => scanOutQNotFull, -- scanNext implicit guard + rd_clk => clk, + rd_en => scanOutQRdEn, -- external consumer + dout => scanOutQDout, + valid => scanOutQValid); + + -- Active-high reset for the FIFO clear mechanism (OQ-FSM-01 / OQ-FSM-06): + -- scanOutQClr is asserted as a LEVEL over FIFO_S and as a pulse on + -- scanStop / preScanRestart / clearAll; OR-ed with the global reset. + rstActiveHigh <= rst when RST_POLARITY_G = '1' else not rst; + scanOutQRst <= rstActiveHigh or scanOutQClr; + + ----------------------------------------------------------------------------- + -- Combinatorial process (two-process FSM): next state + outputs into v. + ----------------------------------------------------------------------------- + comb : process (r, rst, enqEn, enqData, deqEn, clearEn, preScanStartEn, + scanStartEn, scanStopEn, preScanRestartEn, modifyHeadEn, + modifyHeadData, scanOutQValid, scanOutQNotFull, + scanOutReady) is + variable v : RegType; + -- canonicalize helpers (decoded from the registered CReg pulses) + variable hasPush : sl; + variable hasPop : sl; + variable pushData : slv(T_SZ_G-1 downto 0); + variable isAlmostFull : sl; + variable isAlmostEmpty : sl; + -- scanNext datapath + variable scanOutElem : slv(T_SZ_G-1 downto 0); + -- Mealy outputs to U_ScanOutQ + variable vScanOutQWrEn : sl; + variable vScanOutQDin : slv(T_SZ_G-1 downto 0); + variable vScanOutQClr : sl; + begin + v := r; + + -- Defaults for Mealy outputs (deasserted unless a branch drives them) + vScanOutQWrEn := '0'; + vScanOutQDin := (others => '0'); + vScanOutQClr := '0'; + scanOutElem := (others => '0'); + + -- CReg intra-cycle forwarding: the method (port-0) strobes of THIS cycle + -- are what the rules (port-1 reads) consume — no registration (see the + -- header BUGFIX note; matches BSV write[0] SB read[1] ordering). + hasPush := enqEn; + hasPop := deqEn; + pushData := enqData; + + -- Saturating-count status helpers over the current item count + if (r.itemCnt(CNT_SZ_C-2 downto 0) = ALMOST_FULL_C) then + isAlmostFull := '1'; -- itemCnt = Q_SZ_G-1 (full after push) + else + isAlmostFull := '0'; + end if; + if (unsigned(r.itemCnt) = 1) then + isAlmostEmpty := '1'; -- itemCnt = 1 (empty after pop) + else + isAlmostEmpty := '0'; + end if; + + ----------------------------------------------------------------------- + -- Rule priority (FSM spec lines 364-371): + -- 1. clearAll (overrides everything) + -- 2. scanModeStateChange (SCAN; suppresses scanNext on stop/restart) + -- 3. canonicalize (always, disjoint write set) + -- 4. scanNext (SCAN, not suppressed, scanOutQ not full) + -- 5. fifoMode / preScanMode (per state) + -- clearAll / canonicalize / the state rules consume the SAME-CYCLE input + -- strobes (BSV CReg port-1 reads see the port-0 method writes of the + -- current cycle); a same-cycle clear discards any concurrent push/pop + -- (BSV: clearAll's port-1 False writes are the last writes committed). + ----------------------------------------------------------------------- + if (clearEn = '1') then + -- rule clearAll : reset pointers/counts/flags/state and flush scanOutQ + v.enqPtrReg := (others => '0'); + v.deqPtrReg := (others => '0'); + v.itemCnt := (others => '0'); + v.fullReg := '0'; + v.emptyReg := '1'; + v.scanStateReg := FIFO_S; + vScanOutQClr := '1'; -- U_ScanOutQ.clear + + else + --------------------------------------------------------------------- + -- canonicalize : commit the pending push/pop every cycle (all states) + --------------------------------------------------------------------- + if (hasPush = '1') then + v.dataVec(to_integer(unsigned(r.enqPtrReg))) := pushData; + v.enqPtrReg := slv(unsigned(r.enqPtrReg) + 1); + end if; + if (hasPop = '1') then + v.deqPtrReg := slv(unsigned(r.deqPtrReg) + 1); + end if; + if (hasPush = '0') and (hasPop = '1') then + v.itemCnt := slv(unsigned(r.itemCnt) - 1); + v.emptyReg := isAlmostEmpty; -- empty iff itemCnt was 1 + v.fullReg := '0'; + elsif (hasPush = '1') and (hasPop = '0') then + v.itemCnt := slv(unsigned(r.itemCnt) + 1); + v.fullReg := isAlmostFull; -- full iff itemCnt was Q_SZ_G-1 + v.emptyReg := '0'; + end if; + -- both / neither: itemCnt and flags unchanged + + --------------------------------------------------------------------- + -- State rules (mutually exclusive by scanStateReg) + --------------------------------------------------------------------- + case r.scanStateReg is + + when FIFO_S => + -- rule fifoMode : optional transition into PRE_SCAN; hold + -- scanOutQ cleared (level) and head invalidated while idle. + vScanOutQClr := '1'; + v.headReg := (others => '0'); -- Invalid + if (preScanStartEn = '1') and (r.emptyReg = '0') then + v.scanStateReg := PRE_SCAN_S; + end if; + + when PRE_SCAN_S => + -- rule preScanMode : snapshot deqPtr->scanPtr, itemCnt->scanCnt; + -- optional transition into SCAN. (enq/deq blocked here by guards.) + -- DEVIATION: scanStop is honoured here too (BSV guards scanStop + -- to inScanMode and relies on the caller's implicit conditions + -- to defer the whole ERR flush; the port-level VHDL cannot, so + -- an abort while pre-scanning must not strand the FSM here — + -- otherwise RespHandleSq's ERR flush deqs against PRE_SCAN). + v.scanPtrReg := r.deqPtrReg; + v.scanCnt := r.itemCnt; + if (scanStopEn = '1') then + v.scanStateReg := FIFO_S; + elsif (scanStartEn = '1') then + v.scanStateReg := SCAN_S; + end if; + + when SCAN_S => + -- rule scanModeStateChange (stop > restart > done) + scanNext. + if (scanStopEn = '1') then + -- abort scan; scanNext SUPPRESSED (no emit, no advance) + v.scanStateReg := FIFO_S; + vScanOutQClr := '1'; -- U_ScanOutQ.clear + + elsif (preScanRestartEn = '1') then + -- restart snapshot; scanNext SUPPRESSED + v.scanStateReg := PRE_SCAN_S; + vScanOutQClr := '1'; -- U_ScanOutQ.clear + + else + -- rule scanNext : emit one entry per cycle. + -- implicit guard : scanOutQ not full + -- OQ-FSM-05 : suppress when scanCnt = 0 (nothing left) + if (scanOutQNotFull = '1') and (unsigned(r.scanCnt) /= 0) then + -- first scan output may use the modified head + if (r.headReg(MAYBE_SZ_C-1) = '1') then + scanOutElem := r.headReg(T_SZ_G-1 downto 0); + else + scanOutElem := r.dataVec(to_integer(unsigned(r.scanPtrReg))); + end if; + v.scanCnt := slv(unsigned(r.scanCnt) - 1); + v.scanPtrReg := slv(unsigned(r.scanPtrReg) + 1); + v.headReg := (others => '0'); -- consume modified head + vScanOutQWrEn := '1'; + vScanOutQDin := scanOutElem; + end if; + + -- scanDone: all snapshot entries emitted AND the scan output + -- queue fully drained (drain-gated exit; header DEVIATION + -- note). Mutually exclusive with scanNext (scanCnt = 0). + if (unsigned(r.scanCnt) = 0) and (unsigned(r.outQOcc) = 0) then + v.scanStateReg := FIFO_S; + end if; + end if; + + -- pragma translate_off + -- check rule: dequeue must not overtake the scan pointer, and + -- occupancy must never drop below the remaining scan count. + assert (deqEn = '0') or + (unsigned(r.deqPtrReg) /= unsigned(r.scanPtrReg) + 1) + report "deq overtakes scanPtr @ ScanFifoF" severity error; + assert (unsigned(r.itemCnt) >= unsigned(r.scanCnt)) + report "itemCnt < scanCnt @ ScanFifoF" severity error; + -- pragma translate_on + + end case; + end if; + + ----------------------------------------------------------------------- + -- modifyHead (BSV: plain mkRegU headReg, method write lands next cycle). + -- Method guards are enforced by the caller; most immAssert checks in the + -- BSV source are runtime-only and are not re-encoded here (OQ-FSM-07). + ----------------------------------------------------------------------- + if (modifyHeadEn = '1') then + v.headReg := '1' & modifyHeadData; -- Valid modified head + end if; + + ----------------------------------------------------------------------- + -- U_ScanOutQ occupancy bookkeeping: any clear (level or pulse) empties + -- the queue; otherwise count writes minus completed reads (a read + -- completes only when rd_en meets a presented word, i.e. valid = '1'). + ----------------------------------------------------------------------- + if (vScanOutQClr = '1') then + v.outQOcc := (others => '0'); + elsif (vScanOutQWrEn = '1') and + not ((scanOutReady = '1') and (scanOutQValid = '1')) then + v.outQOcc := slv(unsigned(r.outQOcc) + 1); + elsif (vScanOutQWrEn = '0') and + (scanOutReady = '1') and (scanOutQValid = '1') then + v.outQOcc := slv(unsigned(r.outQOcc) - 1); + end if; + + -- pragma translate_off + -- BSV mkScanFIFOF immAsserts guarding the deq/scan interplay: a deq + -- strobe must never coincide with a scan(-re)start or land in PRE_SCAN. + -- Any violation here means the PARENT is producing the spurious pop + -- that unbalances the SQ pending-request counter. + assert not (deqEn = '1' and preScanStartEn = '1') + report "deq coincides with preScanStart @ ScanFifoF" severity error; + assert not (deqEn = '1' and scanStartEn = '1') + report "deq coincides with scanStart @ ScanFifoF" severity error; + assert not (deqEn = '1' and preScanRestartEn = '1') + report "deq coincides with preScanRestart @ ScanFifoF" severity error; + assert not (deqEn = '1' and r.scanStateReg = PRE_SCAN_S) + report "deq while in PRE_SCAN mode @ ScanFifoF" severity error; + -- pragma translate_on + + -- Synchronous reset + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + + -- Mealy outputs to U_ScanOutQ (combinational from this cycle's firing). + -- Left ungated under reset: scanOutQRst forces the FIFO's synchronous + -- reset, which dominates a concurrent wr_en (OQ-FSM-01 RESOLVED). + scanOutQWrEn <= vScanOutQWrEn; + scanOutQDin <= vScanOutQDin; + scanOutQClr <= vScanOutQClr; + + end process comb; + + ----------------------------------------------------------------------------- + -- Sequential process: register update + async reset option. + ----------------------------------------------------------------------------- + seq : process (clk, rst) is + begin + if (RST_ASYNC_G and rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + + ----------------------------------------------------------------------------- + -- Outputs + ----------------------------------------------------------------------------- + -- Moore (registered state reads) + fifoNotEmpty <= not r.emptyReg; + fifoNotFull <= not r.fullReg; + -- deqPulse: BSV deqPulse() = popReg[1], i.e. the SAME-CYCLE deq() strobe + -- (registered popReg is always False). Mealy passthrough, NOT delayed. + deqPulse <= deqEn; + fifoSize <= r.itemCnt; + isScanDone <= '1' when (r.scanStateReg = FIFO_S) else '0'; + + -- Mealy (combinational array reads; BSV first()/getHead() peek semantics) + fifoFirst <= r.dataVec(to_integer(unsigned(r.deqPtrReg))); + scanHead <= r.dataVec(to_integer(unsigned(r.deqPtrReg))); + + -- hasScanOut = !inFifoMode || scanOutQ.notEmpty (FSM spec line 128/470) + hasScanOut <= '1' when (r.scanStateReg /= FIFO_S) or (scanOutQValid = '1') else '0'; + + -- Scan output PipeOut (read side of U_ScanOutQ) + scanOutValid <= scanOutQValid; + scanOutData <= scanOutQDout; + scanOutQRdEn <= scanOutReady; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/SendQ.vhd b/ethernet/RoCEv2/rtl/SendQ.vhd new file mode 100644 index 0000000000..b204e4b5d3 --- /dev/null +++ b/ethernet/RoCEv2/rtl/SendQ.vhd @@ -0,0 +1,757 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Five-stage dataflow pipeline (recvWQE -> recvTotalMetaData -> updatePSN -> +-- prepareHeader -> genPktHeader), all BSV (* conflict_free *) rules, so each +-- stage fires independently when its input FIFO is non-empty, its output FIFO +-- has room, and (where used) the external payloadGenerator handshake holds. +-- Handoff between stages is FIFO-carried; the only true sequential state is the +-- per-WQE packet loop in updatePSN (curPsnReg, wqeFirstPktReg). +-- +-- 8 pipeline FIFOs (all surf.Fifo, FWFT, sync) + 3 internal children: +-- U_HeaderGenRDMA : work.HeaderGenRDMA (combinational header packer, +-- split out of mkSendQ — see ADDENDUM-HeaderGenRDMA.md; +-- VERIFIED, out/05-verify/HeaderGenRDMA.result.md PASS) +-- U_HeaderDataStream : work.Header2DataStream (mkHeader2DataStream) +-- U_RdmaPktDataStream : work.PrependHeader2PipeOut (mkPrependHeader2PipeOut) +-- +-- Module parameters become ports (OQ-FSM-SQ-02): clearAll -> clearAllI; +-- payloadGenerator -> an external Server + 2 PipeOut port group (NOT an instance). +-- +-- resetAndClear (BSV) : while clearAllI='1' all 8 FIFOs are held cleared +-- (fifoRst = rst OR clearAllI) and wqeFirstPktReg is forced '1'. +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_ReqQ, U_RespQ, U_UdpPktInfoOutQ, U_TotalMetaDataQ, U_PsnUpdateQ, +-- U_HeaderPrepareQ, U_PendingHeaderQ, U_PktHeaderQ. +-- +-- Judgment calls / open questions (see out/04-vhdl/OPEN_QUESTIONS.md): +-- OQ-EMIT-SQ-SPLIT : header datapath moved to work.HeaderGenRDMA. +-- OQ-EMIT-SQ-SENDRESP: SendResp is 0-width; U_RespQ carries a 1-bit token. +-- Refactor: pendingHeaderQ carries the packed HeaderRDMA (from HeaderGenRDMA, +-- run in the prepareHeader stage) + a headerValid tag + hasPayload, instead +-- of the BSV Maybe#(PktHeaderInfo); genPktHeader muxes raw vs non-raw. +-- +-- Composite word layouts (first-field-at-MSB, from BSV deriving(Bits)): +-- WorkQueueElem (1721): id[1720:1657] opcode[1656:1653] flags[1652:1648] +-- qpType[1647:1644] psn[1643:1620] pmtu[1619:1617] dqpIP[1616:1488] +-- macAddr[1487:1440] sgl[1439:400] totalLen[399:368] raddr[367:304] +-- rkey[303:272] sqpn[271:248] dqpn[247:224] comp[223:159] swap[158:94] +-- immDtOrInvRKey[93:60] srqn[59:35] qkey[34:2] isFirst[1] isLast[0] +-- (sgl[0] = wqe[1439:1310]: laddr[1439:1376] len[1375:1344] lkey[1343:1312] +-- isFirst[1311] isLast[1310]; Maybe# tag is the MSB of its field.) +-- HeaderGenInfo (142): remoteAddr[141:78] totalLen[77:46] curPSN[45:22] +-- pktLen[21:9] padCnt[8:7] hasPayload[6] ackReq[5] solicited[4] +-- isFirstPkt[3] isLastPkt[2] isOnlyPkt[1] isRawPkt[0] +-- PayloadGenReqSG (1228): wrID[1227:1164] sqpn[1163:1140] sgl[1139:100] +-- totalLen[99:68] raddr[67:4] pmtu[3:1] addPadding[0] +-- PayloadGenRespSG (81): raddr[80:17] pktLen[16:4] padCnt[3:2] isFirst[1] isLast[0] +-- PayloadGenTotalMetaData (27): totalPktNum[26:2] isOnlyPkt[1] isZeroPayloadLen[0] +-- PktInfo4UDP (191): macAddr[190:143] ipAddr[142:14] pktLen[13:1] isRawPkt[0] +-- HeaderRDMA (593): see HeaderGenRDMA.vhd header. +-- pendingHeaderQ (787): macAddr[786:739] ipAddr[738:610] pktLenWithPadCnt[609:597] +-- isRawPkt[596] isSendDone[595] hasPayload[594] headerValid[593] pktHeaderRdma[592:0] +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity SendQ is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- Software clear (BSV module parameter clearAll : Bool) + clearAllI : in sl; + -- srvPort.request : Server input, WorkQueueElem (toGPServer reqQ) + reqReqValid : in sl; + reqReqData : in slv(1720 downto 0); + reqReqReady : out sl; -- reqQ.notFull + -- srvPort.response : Server output, SendResp token (toGPServer respQ) + respValid : out sl; -- respQ.notEmpty + respData : out slv(0 downto 0); -- SendResp (0-width -> 1-bit token) + respReady : in sl; -- response.get (deq) + -- udpInfoPipeOut : PipeOut#(PktInfo4UDP) + udpInfoValid : out sl; + udpInfoData : out slv(190 downto 0); + udpInfoRdEn : in sl; + -- rdmaDataStreamPipeOut : DataStreamPipeOut (290-bit DataStream) + rdmaDataValid : out sl; + rdmaDataData : out slv(289 downto 0); + rdmaDataRdEn : in sl; + -- payloadGenerator.srvPort.request : PayloadGenReqSG (out / put) + payloadGenReqValid : out sl; + payloadGenReqData : out slv(1227 downto 0); + payloadGenReqReady : in sl; + -- payloadGenerator.srvPort.response : PayloadGenRespSG (in / get) + payloadGenRespValid : in sl; + payloadGenRespData : in slv(80 downto 0); + payloadGenRespReady : out sl; + -- payloadGenerator.totalMetaDataPipeOut : PayloadGenTotalMetaData (in) + payloadTotalMetaValid : in sl; + payloadTotalMetaData : in slv(26 downto 0); + payloadTotalMetaRdEn : out sl; + -- payloadGenerator.payloadDataStreamPipeOut : DataStream (in) + payloadDataStreamValid : in sl; + payloadDataStreamData : in slv(289 downto 0); + payloadDataStreamRdEn : out sl; + -- method Bool isEmpty() (combinational) + isEmpty : out sl); +end entity SendQ; + +architecture rtl of SendQ is + + -- WorkReqOpCode encodings (4 bits) + constant WR_RDMA_WRITE_C : slv(3 downto 0) := x"0"; + constant WR_WRITE_IMM_C : slv(3 downto 0) := x"1"; + constant WR_SEND_C : slv(3 downto 0) := x"2"; + constant WR_SEND_IMM_C : slv(3 downto 0) := x"3"; + constant WR_SEND_INV_C : slv(3 downto 0) := x"9"; + constant WR_READ_RESP_C : slv(3 downto 0) := x"C"; + -- TypeQP RAW encoding + constant QPT_RAW_C : slv(3 downto 0) := x"8"; + + -- FIFO element widths + constant WQE_W_C : integer := 1721; -- WorkQueueElem + constant TMD_W_C : integer := 1723; -- Tuple3(wqe,Bool,Bool) + constant PSNU_W_C : integer := 1782; -- Tuple7(...) + constant HPREP_W_C : integer := 1863; -- Tuple2(wqe,HeaderGenInfo) + constant PEND_W_C : integer := 787; -- refactored pendingHeaderQ + constant HRDMA_W_C : integer := 593; -- HeaderRDMA + constant UDP_W_C : integer := 191; -- PktInfo4UDP + constant DS_W_C : integer := 290; -- DataStream + + type RegType is record + curPsnReg : slv(23 downto 0); -- mkRegU (PSN); no power-on reset + wqeFirstPktReg : sl; -- mkRegU but forced '1' by resetAndClear + end record RegType; + + -- curPsnReg is mkRegU (written before read); given '0' for a defined start. + constant REG_INIT_C : RegType := ( + curPsnReg => (others => '0'), + wqeFirstPktReg => '1'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal fifoRst : sl; + + -- FIFO interconnect signals + signal reqQDout : slv(WQE_W_C-1 downto 0); + signal reqQValid : sl; + signal reqQNotFull : sl; + signal reqQEmpty : sl; + signal reqQRdEn : sl; + + signal tmdDin : slv(TMD_W_C-1 downto 0); + signal tmdWrEn : sl; + signal tmdDout : slv(TMD_W_C-1 downto 0); + signal tmdValid : sl; + signal tmdNotFull : sl; + signal tmdEmpty : sl; + signal tmdRdEn : sl; + + signal psnDin : slv(PSNU_W_C-1 downto 0); + signal psnWrEn : sl; + signal psnDout : slv(PSNU_W_C-1 downto 0); + signal psnValid : sl; + signal psnNotFull : sl; + signal psnEmpty : sl; + signal psnRdEn : sl; + + signal hprepDin : slv(HPREP_W_C-1 downto 0); + signal hprepWrEn : sl; + signal hprepDout : slv(HPREP_W_C-1 downto 0); + signal hprepValid : sl; + signal hprepNotFull : sl; + signal hprepEmpty : sl; + signal hprepRdEn : sl; + + signal pendDin : slv(PEND_W_C-1 downto 0); + signal pendWrEn : sl; + signal pendDout : slv(PEND_W_C-1 downto 0); + signal pendValid : sl; + signal pendNotFull : sl; + signal pendEmpty : sl; + signal pendRdEn : sl; + + signal pktHdrDin : slv(HRDMA_W_C-1 downto 0); + signal pktHdrWrEn : sl; + signal pktHdrDout : slv(HRDMA_W_C-1 downto 0); + signal pktHdrValid : sl; + signal pktHdrNotFull : sl; + signal pktHdrEmpty : sl; + signal pktHdrRdEn : sl; + + signal udpDin : slv(UDP_W_C-1 downto 0); + signal udpWrEn : sl; + signal udpDout : slv(UDP_W_C-1 downto 0); + signal udpValid : sl; + signal udpNotFull : sl; + signal udpEmpty : sl; + + signal respWrEn : sl; + signal respQValid : sl; + signal respQNotFull : sl; + signal respQEmpty : sl; + + -- HeaderGenRDMA interconnect (driven from headerPrepareQ.dout) + signal hpWqe : slv(WQE_W_C-1 downto 0); + signal hgrIsFirstOrOnly : sl; + signal hgrIsOnlyOrLast : sl; + signal hgrSolicited : sl; + signal hgrAckReq : sl; + signal hgrPsn : slv(23 downto 0); + signal hgrPadCnt : slv(1 downto 0); + signal hgrRemoteAddr : slv(63 downto 0); + signal hgrDlen : slv(31 downto 0); + signal hgrHasPayloadIn : sl; + signal hgrHeaderValid : sl; + signal hgrPktHeaderRdma : slv(592 downto 0); + + -- Header2DataStream <-> PrependHeader2PipeOut interconnect + signal hdrDsValid : sl; + signal hdrDsData : slv(289 downto 0); + signal hdrDsRdEn : sl; + signal hdrMetaValid : sl; + signal hdrMetaData : slv(16 downto 0); + signal hdrMetaRdEn : sl; + +begin + + fifoRst <= rst or clearAllI; + + --------------------------------------------------------------------------- + -- 8 pipeline FIFOs (all surf.Fifo, FWFT, synchronous) + --------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => WQE_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqReqValid, + din => reqReqData, + not_full => reqQNotFull, + rd_clk => clk, + rd_en => reqQRdEn, + dout => reqQDout, + valid => reqQValid, + empty => reqQEmpty); + + U_TotalMetaDataQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => TMD_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => tmdWrEn, + din => tmdDin, + not_full => tmdNotFull, + rd_clk => clk, + rd_en => tmdRdEn, + dout => tmdDout, + valid => tmdValid, + empty => tmdEmpty); + + U_PsnUpdateQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PSNU_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => psnWrEn, + din => psnDin, + not_full => psnNotFull, + rd_clk => clk, + rd_en => psnRdEn, + dout => psnDout, + valid => psnValid, + empty => psnEmpty); + + U_HeaderPrepareQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => HPREP_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => hprepWrEn, + din => hprepDin, + not_full => hprepNotFull, + rd_clk => clk, + rd_en => hprepRdEn, + dout => hprepDout, + valid => hprepValid, + empty => hprepEmpty); + + U_PendingHeaderQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => PEND_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pendWrEn, + din => pendDin, + not_full => pendNotFull, + rd_clk => clk, + rd_en => pendRdEn, + dout => pendDout, + valid => pendValid, + empty => pendEmpty); + + U_PktHeaderQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => HRDMA_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => pktHdrWrEn, + din => pktHdrDin, + not_full => pktHdrNotFull, + rd_clk => clk, + rd_en => pktHdrRdEn, + dout => pktHdrDout, + valid => pktHdrValid, + empty => pktHdrEmpty); + + U_UdpPktInfoOutQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => UDP_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => udpWrEn, + din => udpDin, + not_full => udpNotFull, + rd_clk => clk, + rd_en => udpInfoRdEn, + dout => udpDout, + valid => udpValid, + empty => udpEmpty); + + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 1, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => respWrEn, + din => "0", + not_full => respQNotFull, + rd_clk => clk, + rd_en => respReady, + dout => respData, + valid => respQValid, + empty => respQEmpty); + + --------------------------------------------------------------------------- + -- Internal children + --------------------------------------------------------------------------- + -- HeaderGenRDMA is combinational; its inputs are the headerPrepareQ head + -- (wqe + HeaderGenInfo). Driven concurrently below. + hpWqe <= hprepDout(HPREP_W_C-1 downto 142); -- WorkQueueElem slice + + hgrIsFirstOrOnly <= hprepDout(3); -- HeaderGenInfo.isFirstPkt + hgrIsOnlyOrLast <= ite(hprepDout(3) = '1', hprepDout(1), hprepDout(2)); -- isFirst?isOnly:isLast + hgrSolicited <= hprepDout(4); + hgrAckReq <= hprepDout(5); + hgrPsn <= hprepDout(45 downto 22); -- HeaderGenInfo.curPSN + hgrPadCnt <= hprepDout(8 downto 7); + hgrRemoteAddr <= hprepDout(141 downto 78); -- HeaderGenInfo.remoteAddr + hgrDlen <= hprepDout(77 downto 46) when hprepDout(3) = '1' -- first: totalLen + else (31 downto 13 => '0') & hprepDout(21 downto 9); -- last: zeroExt(pktLen) + hgrHasPayloadIn <= hprepDout(6); + + U_HeaderGenRDMA : entity surf.HeaderGenRDMA + port map ( + isFirstOrOnly => hgrIsFirstOrOnly, + isOnlyOrLast => hgrIsOnlyOrLast, + qpType => hpWqe(1647 downto 1644), + opcode => hpWqe(1656 downto 1653), + solicited => hgrSolicited, + ackReq => hgrAckReq, + psn => hgrPsn, + padCnt => hgrPadCnt, + remoteAddr => hgrRemoteAddr, + wqeRaddr => hpWqe(367 downto 304), + dlen => hgrDlen, + hasPayloadIn => hgrHasPayloadIn, + dqpn => hpWqe(247 downto 224), + sqpn => hpWqe(271 downto 248), + srqn => hpWqe(58 downto 35), -- Maybe#(QPN) value (tag=MSB dropped) + qkey => hpWqe(33 downto 2), -- Maybe#(QKEY) value + rkey => hpWqe(303 downto 272), + sgeLaddr => hpWqe(1439 downto 1376), -- sgl[0].laddr + sgeLkey => hpWqe(1343 downto 1312), -- sgl[0].lkey + swapData => hpWqe(157 downto 94), -- Maybe#(Long) value + compData => hpWqe(222 downto 159), -- Maybe#(Long) value + immData => hpWqe(91 downto 60), -- Maybe#(ImmOrRKey) value + headerValid => hgrHeaderValid, + pktHeaderRdma => hgrPktHeaderRdma); + + U_HeaderDataStream : entity surf.Header2DataStream + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAllI => clearAllI, + hdrPipeInValid => pktHdrValid, + hdrPipeInData => pktHdrDout, + hdrPipeInRdEn => pktHdrRdEn, + hdrDataStreamValid => hdrDsValid, + hdrDataStreamDout => hdrDsData, + hdrDataStreamRdEn => hdrDsRdEn, + hdrMetaDataValid => hdrMetaValid, + hdrMetaDataDout => hdrMetaData, + hdrMetaDataRdEn => hdrMetaRdEn); + + U_RdmaPktDataStream : entity surf.PrependHeader2PipeOut + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAllI => clearAllI, + headerMetaPipeInValid => hdrMetaValid, + headerMetaPipeInData => hdrMetaData, + headerMetaPipeInRdEn => hdrMetaRdEn, + headerPipeInValid => hdrDsValid, + headerPipeInData => hdrDsData, + headerPipeInRdEn => hdrDsRdEn, + dataPipeInValid => payloadDataStreamValid, + dataPipeInData => payloadDataStreamData, + dataPipeInRdEn => payloadDataStreamRdEn, + dataStreamOutValid => rdmaDataValid, + dataStreamOutData => rdmaDataData, + dataStreamOutRdEn => rdmaDataRdEn); + + --------------------------------------------------------------------------- + -- Combinational pipeline (5 conflict_free stages + isEmpty) + --------------------------------------------------------------------------- + comb : process (all) is + variable v : RegType; + + -- stage-local variables + variable notClear : sl; + -- recvWQE + variable rwOpcode : slv(3 downto 0); + variable rwQpType : slv(3 downto 0); + variable rwIsRaw : sl; + variable rwAddPad : sl; + variable rwIsSend : sl; + variable rwNeedGen : sl; + variable rwGenPl : sl; + variable rwRemote : slv(63 downto 0); + variable rwFire : sl; + -- recvTotalMetaData + variable rtGenPl : sl; + variable rtIsRaw : sl; + variable rtHasPl : sl; + variable rtIsOnly : sl; + variable rtTotPkt : slv(24 downto 0); + variable rtFire : sl; + -- updatePSN + variable upWqe : slv(WQE_W_C-1 downto 0); + variable upGenPl : sl; + variable upHasPl : sl; + variable upIsOnly : sl; + variable upIsRaw : sl; + variable upTotLen : slv(31 downto 0); + variable upTotPkt : slv(24 downto 0); + variable upCurPsn : slv(23 downto 0); + variable upRemote : slv(63 downto 0); + variable upPktLen : slv(12 downto 0); + variable upPadCnt : slv(1 downto 0); + variable upLastPkt : sl; + variable upFirstPkt : sl; + variable upIsLastPkt : sl; + variable upAckReq : sl; + variable upSolicited : sl; + variable upHgi : slv(141 downto 0); + variable upFire : sl; + -- prepareHeader + variable phRaw : sl; + variable phHasPl : sl; + variable phPktLenPad : slv(12 downto 0); + variable phSendDone : sl; + variable phFire : sl; + -- genPktHeader + variable gpRaw : sl; + variable gpHasPl : sl; + variable gpHdrValid : sl; + variable gpValidEntry : sl; + variable gpHeaderLen : slv(6 downto 0); + variable gpEmptyHdr : slv(592 downto 0); + variable gpPktHdr : slv(592 downto 0); + variable gpUdpPktLen : slv(12 downto 0); + variable gpSendDone : sl; + variable gpFire : sl; + begin + v := r; + notClear := not clearAllI; + + ---------------------------------------------------------------------- + -- Stage 1 : recvWQE + ---------------------------------------------------------------------- + rwOpcode := reqQDout(1656 downto 1653); + rwQpType := reqQDout(1647 downto 1644); + rwIsRaw := ite(rwQpType = QPT_RAW_C, '1', '0'); + rwAddPad := not rwIsRaw; + rwIsSend := ite(rwOpcode = WR_SEND_C or rwOpcode = WR_SEND_IMM_C or + rwOpcode = WR_SEND_INV_C, '1', '0'); + rwNeedGen := ite(rwOpcode = WR_RDMA_WRITE_C or rwOpcode = WR_WRITE_IMM_C or + rwOpcode = WR_SEND_C or rwOpcode = WR_SEND_IMM_C or + rwOpcode = WR_SEND_INV_C or rwOpcode = WR_READ_RESP_C, '1', '0'); + rwGenPl := rwIsRaw or rwNeedGen; + if (rwIsRaw = '1' or rwIsSend = '1') then + rwRemote := (others => '0'); + else + rwRemote := reqQDout(367 downto 304); -- wqe.raddr + end if; + + rwFire := notClear and reqQValid and tmdNotFull and + (not rwGenPl or payloadGenReqReady); + + reqQRdEn <= rwFire; + tmdWrEn <= rwFire; + tmdDin <= reqQDout & rwIsRaw & rwGenPl; -- Tuple3(wqe,isRawPkt,shouldGenPayload) + payloadGenReqValid <= rwFire and rwGenPl; + -- PayloadGenReqSG: wrID & sqpn & sgl & totalLen & raddr & pmtu & addPadding + payloadGenReqData <= reqQDout(1720 downto 1657) & -- wrID (=wqe.id) + reqQDout(271 downto 248) & -- sqpn + reqQDout(1439 downto 400) & -- sgl + reqQDout(399 downto 368) & -- totalLen + rwRemote & -- raddr (remoteAddr) + reqQDout(1619 downto 1617) & -- pmtu + rwAddPad; -- addPadding + + ---------------------------------------------------------------------- + -- Stage 2 : recvTotalMetaData + ---------------------------------------------------------------------- + -- tmdDout = wqe[1722:2] & isRawPkt[1] & shouldGenPayload[0] + rtGenPl := tmdDout(0); + rtIsRaw := tmdDout(1); + if (rtGenPl = '1') then + -- PayloadGenTotalMetaData: totalPktNum[26:2] isOnlyPkt[1] isZeroPayloadLen[0] + rtHasPl := not payloadTotalMetaData(0); + rtIsOnly := payloadTotalMetaData(1); + rtTotPkt := payloadTotalMetaData(26 downto 2); + else + rtHasPl := rtGenPl; -- = '0' + rtIsOnly := not rtGenPl; -- = '1' + rtTotPkt := std_logic_vector(to_unsigned(1, 25)); + end if; + + rtFire := notClear and tmdValid and psnNotFull and + (not rtGenPl or payloadTotalMetaValid); + + tmdRdEn <= rtFire; + payloadTotalMetaRdEn <= rtFire and rtGenPl; + psnWrEn <= rtFire; + -- Tuple7(wqe, totalLen, totalPktNum, shouldGenPayload, hasPayload, isOnlyPkt, isRawPkt) + psnDin <= tmdDout(TMD_W_C-1 downto 2) & -- wqe + tmdDout(399+2 downto 368+2) & -- wqe.totalLen (offset +2 in tmdDout) + rtTotPkt & rtGenPl & rtHasPl & rtIsOnly & rtIsRaw; + + ---------------------------------------------------------------------- + -- Stage 3 : updatePSN (per-WQE packet loop; the only stateful stage) + ---------------------------------------------------------------------- + -- psnDout : wqe[1781:61] totalLen[60:29] totalPktNum[28:4] + -- shouldGenPayload[3] hasPayload[2] isOnlyPkt[1] isRawPkt[0] + upWqe := psnDout(PSNU_W_C-1 downto 61); + upTotLen := psnDout(60 downto 29); + upTotPkt := psnDout(28 downto 4); + upGenPl := psnDout(3); + upHasPl := psnDout(2); + upIsOnly := psnDout(1); + upIsRaw := psnDout(0); + + if (r.wqeFirstPktReg = '1') then + upCurPsn := upWqe(1643 downto 1620); -- wqe.psn + else + upCurPsn := r.curPsnReg; + end if; + + upRemote := upWqe(367 downto 304); -- wqe.raddr (default) + upPktLen := (others => '0'); + upPadCnt := (others => '0'); + upLastPkt := upIsOnly; + if (upGenPl = '1') then + -- PayloadGenRespSG: raddr[80:17] pktLen[16:4] padCnt[3:2] isFirst[1] isLast[0] + upRemote := payloadGenRespData(80 downto 17); + upPktLen := payloadGenRespData(16 downto 4); + upPadCnt := payloadGenRespData(3 downto 2); + upLastPkt := payloadGenRespData(0); + end if; + + upFirstPkt := r.wqeFirstPktReg and upWqe(1); -- wqe.isFirst + upIsLastPkt := upLastPkt and upWqe(0); -- wqe.isLast + upAckReq := upWqe(1649); -- flags(1)=IBV_SEND_SIGNALED + upSolicited := upWqe(1650); -- flags(2)=IBV_SEND_SOLICITED + + upFire := notClear and psnValid and hprepNotFull and + (not upGenPl or payloadGenRespValid); + + -- HeaderGenInfo: remoteAddr totalLen curPSN pktLen padCnt hasPayload + -- ackReq solicited isFirstPkt isLastPkt isOnlyPkt isRawPkt + upHgi := upRemote & upTotLen & upCurPsn & upPktLen & upPadCnt & upHasPl & + upAckReq & upSolicited & upFirstPkt & upIsLastPkt & upIsOnly & upIsRaw; + + psnRdEn <= upFire and upLastPkt; + hprepWrEn <= upFire; + hprepDin <= upWqe & upHgi; + payloadGenRespReady <= upFire and upGenPl; + + -- register updates (only this stage writes curPsnReg / wqeFirstPktReg) + if (upFire = '1') then + v.curPsnReg := slv(unsigned(upCurPsn) + 1); + v.wqeFirstPktReg := upLastPkt; + end if; + + ---------------------------------------------------------------------- + -- Stage 4 : prepareHeader (drives U_HeaderGenRDMA, enq pendingHeaderQ) + ---------------------------------------------------------------------- + phRaw := hprepDout(0); -- HeaderGenInfo.isRawPkt + phHasPl := hprepDout(6); -- HeaderGenInfo.hasPayload + phPktLenPad := slv(unsigned(hprepDout(21 downto 9)) + + resize(unsigned(hprepDout(8 downto 7)), 13)); -- pktLen + padCnt + phSendDone := hprepDout(1) or hprepDout(2); -- isOnlyPkt or isLastPkt + + phFire := notClear and hprepValid and pendNotFull; + + hprepRdEn <= phFire; + pendWrEn <= phFire; + -- pendingHeaderQ: macAddr ipAddr pktLenWithPadCnt isRawPkt isSendDone + -- hasPayload headerValid pktHeaderRdma + pendDin <= hpWqe(1487 downto 1440) & -- macAddr + hpWqe(1616 downto 1488) & -- dqpIP + phPktLenPad & phRaw & phSendDone & phHasPl & + hgrHeaderValid & hgrPktHeaderRdma; + + ---------------------------------------------------------------------- + -- Stage 5 : genPktHeader + ---------------------------------------------------------------------- + gpRaw := pendDout(596); + gpSendDone := pendDout(595); + gpHasPl := pendDout(594); + gpHdrValid := pendDout(593); + gpValidEntry := gpRaw or gpHdrValid; -- Maybe Valid + + -- genEmptyHeaderRDMA(hasPayload): all zero except hasPayload + isEmptyHeader + gpEmptyHdr := (others => '0'); + gpEmptyHdr(1) := gpHasPl; + gpEmptyHdr(0) := '1'; -- isEmptyHeader + + if (gpRaw = '1') then + gpPktHdr := gpEmptyHdr; + gpHeaderLen := (others => '0'); + else + gpPktHdr := pendDout(592 downto 0); + gpHeaderLen := pendDout(16 downto 10); -- HeaderRDMA.headerMetaData.headerLen + end if; + + gpUdpPktLen := slv(unsigned(pendDout(609 downto 597)) + + resize(unsigned(gpHeaderLen), 13)); + + gpFire := notClear and pendValid and pktHdrNotFull and udpNotFull and + (not gpSendDone or respQNotFull); + + pendRdEn <= gpFire; + pktHdrWrEn <= gpFire and gpValidEntry; + pktHdrDin <= gpPktHdr; + udpWrEn <= gpFire and gpValidEntry; + -- PktInfo4UDP: macAddr ipAddr pktLen isRawPkt + udpDin <= pendDout(786 downto 739) & pendDout(738 downto 610) & + gpUdpPktLen & gpRaw; + respWrEn <= gpFire and gpValidEntry and gpSendDone; + + ---------------------------------------------------------------------- + -- resetAndClear : force wqeFirstPktReg = '1' while clearAllI asserted + ---------------------------------------------------------------------- + if (clearAllI = '1') then + v.wqeFirstPktReg := '1'; + end if; + + -- synchronous reset (curPsnReg is mkRegU: not forced; wqeFirstPktReg -> '1') + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + + ---------------------------------------------------------------------- + -- External interface outputs + ---------------------------------------------------------------------- + reqReqReady <= reqQNotFull; + respValid <= respQValid; + udpInfoValid <= udpValid; + udpInfoData <= udpDout; + + isEmpty <= reqQEmpty and respQEmpty and udpEmpty and tmdEmpty and + psnEmpty and hprepEmpty and pendEmpty and pktHdrEmpty; + + end process comb; + + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ServerArbiter.vhd b/ethernet/RoCEv2/rtl/ServerArbiter.vhd new file mode 100644 index 0000000000..11a67fcb06 --- /dev/null +++ b/ethernet/RoCEv2/rtl/ServerArbiter.vhd @@ -0,0 +1,481 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Multiplexes PORT_COUNT_G upstream client request/response streams onto one +-- downstream Server (srv), tagging each request with its origin port index so +-- the matching response is routed back to that port. Exposes PORT_COUNT_G +-- per-port Server faces (reqK/respK) to upstream clients. +-- +-- BSV owns ONE register (shouldSaveGrantIdxReg) and TWO rules +-- (issueArbitratedReq, dispatchResponse), plus three FIFO groups +-- (inputReqWithIdxVec, respVec, preGrantIdxQ) and the arbitration tree +-- (mkLeafBinaryPipeOutArbiterVec -> mkBinaryPipeOutArbiterTree). This is a +-- 1-flag flow-control wrapper around the arbitration tree — no multi-state +-- enum; shouldSaveGrantIdxReg is a burst-boundary flag. +-- +-- PORT_COUNT_G = 2 (OQ-FSM-SRVARB-01, RESOLVED — option 2): +-- Every concrete mkServerArbiter instantiation (mkDmaArbiter4QP, +-- QueuePair.bsv:335/344) uses Vector#(2,...), so portSz = 2 and idxW = 1. +-- For portSz = 2 the BSV arbitration tree degenerates: the leaf-vec yields a +-- single mkBinaryPipeOutArbiter and mkBinaryPipeOutArbiterTree hits its +-- portSz==1 base case, returning that leaf unchanged. So the whole tree is a +-- single BinaryPipeOutArbiter (U_ReqArb) — NOT the fixed-4 PipeOutArbiter the +-- partition wired. A concurrent assertion below enforces PORT_COUNT_G = 2. +-- +-- OQ-FSM-17 (predicate handling) — reqKFinished / srvRespFinished input ports: +-- BSV isReqFinished / isRespFinished are elaboration-time function arguments +-- (isReqFinished(req), isRespFinished(resp)); VHDL has no function-type ports. +-- Per the established resolution the parent (mkDmaArbiter4QP), where the +-- concrete type is known, computes them and feeds them as 1-bit combinational +-- inputs. Concrete values are trivial (isDmaReadReqLast=True, isDmaWriteRespLast +-- =True -> tie '1'; the others are single-field extracts). +-- * REQUEST predicate: computed by the parent on the request being put and +-- carried as a companion THROUGH the per-port input FIFO (element widened +-- to {finished, idx, req}). Because isReqFinished is a pure function of the +-- request, the stored bit at the FIFO head == isReqFinished(head.req), which +-- is exactly what the arbiter's per-channel pipeInKFinished input needs, and +-- (via BinaryPipeOutArbiter's outFinished companion) exactly what +-- issueArbitratedReq needs for shouldSaveGrantIdxReg. So reqKFinished is an +-- INPUT PORT sampled at enqueue — no predicate logic lives in this entity. +-- * RESPONSE predicate: srvRespData is already an entity input, so the parent +-- computes srvRespFinished = isRespFinished(srvRespData) and feeds it as a +-- combinational INPUT PORT. +-- These two ports are NOT in the FSM spec's Ports table verbatim (they are the +-- "predicate/port" inputs it defers to OQ-FSM-17); adding them is the faithful +-- realization. See "Judgment calls" in the emit report. +-- +-- Payload layout (BSV pack(tuple2(reqIdx, inputReq)) = {reqIdx, inputReq}, +-- reqIdx in the HIGH bits): +-- arbiter payload width = IDX_WIDTH_C + REQ_WIDTH_G +-- inputReq = arbDout(REQ_WIDTH_G-1 downto 0) +-- reqIdx = arbDout(IDX_WIDTH_C+REQ_WIDTH_G-1 downto REQ_WIDTH_G) +-- Per-port input FIFO element = {finished(1), idx(IDX_WIDTH_C), req(REQ_WIDTH_G)}. +-- +-- Two independent, conflict-free rules (disjoint registers; different ports of +-- preGrantIdxQ: issue -> enq, dispatch -> first/deq). Both may fire the same +-- cycle -> emitted as two independent `if ...FiresEn then` blocks, no priority. +-- issueArbitratedReq guard : arbNotEmpty AND srvReqReady +-- AND ((NOT shouldSave) OR preGrantNotFull) +-- -- the preGrantIdxQ.enq is conditional on shouldSaveGrantIdxReg, so the +-- rule can still fire when the flag is '0' even if preGrantIdxQ is full +-- (BSV conditional-method implicit condition). MUST NOT gate issue +-- unconditionally on notFull. +-- dispatchResponse guard : preGrantNotEmpty AND srvRespValid +-- AND U_RespQ(preGrantIdx).notFull +-- +-- Mealy: all strobes/data are combinational functions of FIFO/handshake status, +-- arbDout and r.shouldSaveGrantIdxReg. Only shouldSaveGrantIdxReg is registered. +-- Data persistence lives in the surf.Fifo instances, not FSM regs. +-- +-- Child entity instantiated: +-- * U_ReqArb : work.BinaryPipeOutArbiter (degenerate PORT_COUNT_G=2 tree) +-- source: out/04-vhdl/BinaryPipeOutArbiter.vhd +-- +-- SURF components instantiated (all BSV mkFIFOF -> surf.Fifo): +-- * U_InReqQ0/1 : surf.Fifo <- inputReqWithIdxVec[k] ({finished,idx,req}) +-- * U_RespQ0/1 : surf.Fifo <- respVec[k] (respType) +-- * U_PreGrantQ : surf.Fifo <- preGrantIdxQ (Bit#(idxW)) +-- source: surf/base/fifo/rtl/Fifo.vhd +-- FWFT_EN_G => true so `valid` = head-present = BSV notEmpty. BSV mkFIFOF is +-- depth 2; surf.Fifo minimum ADDR_WIDTH is 4 (depth 16). Functionally a +-- buffering FIFO; depth differs and there is an inherent ~1-cycle write->valid +-- read latency vs BSV mkFIFOF — functionally equivalent, NOT cycle-accurate. +-- +-- NOTE: emitting does not prove equivalence — simulate this entity (cocotb) +-- against the BSV behaviour before trusting it. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ServerArbiter is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW + RST_ASYNC_G : boolean := false; + PORT_COUNT_G : positive := 2; -- number of upstream ports; MUST be 2 (OQ-FSM-SRVARB-01) + REQ_WIDTH_G : positive := 8; -- Bits#(reqType) + RESP_WIDTH_G : positive := 8; -- Bits#(respType) + MEMORY_TYPE_G : string := "distributed"; -- FIFO RAM style + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- FIFO depth = 2**ADDR (BSV mkFIFOF depth 2; SURF min 4) + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- Per-port client-facing Server 0 (resultSrvVec[0]) + req0Valid : in sl; -- client 0 request.put valid + req0Data : in slv(REQ_WIDTH_G-1 downto 0); -- client 0 request payload + req0Finished : in sl; -- isReqFinished(req0Data) (OQ-FSM-17), sampled at enqueue + req0Ready : out sl; -- port 0 ready = U_InReqQ0 not_full + resp0Valid : out sl; -- response 0 first valid (U_RespQ0 notEmpty) + resp0Data : out slv(RESP_WIDTH_G-1 downto 0); -- response 0 first (U_RespQ0 dout) + resp0Rd : in sl; -- client 0 response.get (U_RespQ0 deq) + -- Per-port client-facing Server 1 (resultSrvVec[1]) + req1Valid : in sl; -- client 1 request.put valid + req1Data : in slv(REQ_WIDTH_G-1 downto 0); -- client 1 request payload + req1Finished : in sl; -- isReqFinished(req1Data) (OQ-FSM-17), sampled at enqueue + req1Ready : out sl; -- port 1 ready = U_InReqQ1 not_full + resp1Valid : out sl; -- response 1 first valid (U_RespQ1 notEmpty) + resp1Data : out slv(RESP_WIDTH_G-1 downto 0); -- response 1 first (U_RespQ1 dout) + resp1Rd : in sl; -- client 1 response.get (U_RespQ1 deq) + -- Downstream shared Server (srv, module argument) + srvReqValid : out sl; -- srv.request.put fired + srvReqData : out slv(REQ_WIDTH_G-1 downto 0); -- request payload to srv (= inputReq) + srvReqReady : in sl; -- srv.request can accept (CAN_PUT) + srvRespValid : in sl; -- srv.response available (Get ready) + srvRespData : in slv(RESP_WIDTH_G-1 downto 0); -- srv.response payload + srvRespFinished : in sl; -- isRespFinished(srvRespData) (OQ-FSM-17) + srvRespRd : out sl); -- srv.response.get fired +end entity ServerArbiter; + +architecture rtl of ServerArbiter is + + -- idxW = TLog#(PORT_COUNT_G); for PORT_COUNT_G=2 -> 1 (OQ-FSM-SRVARB-01). + constant IDX_WIDTH_C : positive := log2(PORT_COUNT_G); + -- Arbiter payload = {reqIdx, inputReq} (reqIdx in the HIGH bits). + constant REQIDX_WIDTH_C : positive := IDX_WIDTH_C + REQ_WIDTH_G; + -- Per-port input FIFO element = {finished, idx, req}. + constant INREQ_WIDTH_C : positive := 1 + REQIDX_WIDTH_C; + + -- Only registered state (BSV mkReg(True)). Burst-boundary flag, not a state + -- selector: '1' => next issued request starts a new burst (record its grant + -- index in preGrantIdxQ); '0' => mid-burst continuation (index already saved). + type RegType is record + shouldSaveGrantIdxReg : sl; + end record RegType; + + constant REG_INIT_C : RegType := ( + shouldSaveGrantIdxReg => '1'); -- BSV mkReg(True) + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- U_InReqQ(k) (surf.Fifo, element {finished,idx,req}) status/handshake. + signal inReqQ0NotFull : sl; + signal inReqQ0Valid : sl; + signal inReqQ0Dout : slv(INREQ_WIDTH_C-1 downto 0); + signal inReqQ0WrEn : sl; + signal inReqQ0Din : slv(INREQ_WIDTH_C-1 downto 0); + signal inReqQ0Rd : sl; + signal inReqQ1NotFull : sl; + signal inReqQ1Valid : sl; + signal inReqQ1Dout : slv(INREQ_WIDTH_C-1 downto 0); + signal inReqQ1WrEn : sl; + signal inReqQ1Din : slv(INREQ_WIDTH_C-1 downto 0); + signal inReqQ1Rd : sl; + + -- U_ReqArb (BinaryPipeOutArbiter) arbitrated PipeOut output. + signal arbNotEmpty : sl; + signal arbDout : slv(REQIDX_WIDTH_C-1 downto 0); -- {reqIdx, inputReq} + signal arbFinished : sl; -- isReqFinished(inputReq), buffered head bit + signal arbDeq : sl; + + -- U_PreGrantQ (surf.Fifo, element Bit#(idxW)) status/handshake. + signal preGrantNotFull : sl; + signal preGrantNotEmpty : sl; + signal preGrantDout : slv(IDX_WIDTH_C-1 downto 0); + signal preGrantWrEn : sl; + signal preGrantDin : slv(IDX_WIDTH_C-1 downto 0); + signal preGrantRdEn : sl; + + -- U_RespQ(k) (surf.Fifo, element respType) status/handshake. + signal respQ0NotFull : sl; + signal respQ0Valid : sl; + signal respQ0Dout : slv(RESP_WIDTH_G-1 downto 0); + signal respQ0WrEn : sl; + signal respQ1NotFull : sl; + signal respQ1Valid : sl; + signal respQ1Dout : slv(RESP_WIDTH_G-1 downto 0); + signal respQ1WrEn : sl; + +begin + + -- Degenerate-tree emit is only valid for PORT_COUNT_G = 2 (OQ-FSM-SRVARB-01). + assert (PORT_COUNT_G = 2) + report "ServerArbiter: emitted for the degenerate PORT_COUNT_G=2 tree only " & + "(single BinaryPipeOutArbiter child); wider portSz needs a real " & + "PORT_COUNT_G-sized arbitration tree (see OQ-FSM-SRVARB-01)." + severity failure; + + -------------------------------------------------------------------------- + -- Per-port request input FIFOs (BSV inputReqWithIdxVec[k] = mkFIFOF). + -- Write side = pure interface wiring of resultSrvVec[k].request.put: + -- on reqKValid & not_full enqueue {reqKFinished, idx=k, reqKData}. + -- Read side feeds the arbiter's pipeInK channel. + -------------------------------------------------------------------------- + U_InReqQ0 : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => INREQ_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => inReqQ0WrEn, + din => inReqQ0Din, + not_full => inReqQ0NotFull, + rd_clk => clk, + rd_en => inReqQ0Rd, + dout => inReqQ0Dout, + valid => inReqQ0Valid); + + U_InReqQ1 : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => INREQ_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => inReqQ1WrEn, + din => inReqQ1Din, + not_full => inReqQ1NotFull, + rd_clk => clk, + rd_en => inReqQ1Rd, + dout => inReqQ1Dout, + valid => inReqQ1Valid); + + -- Interface wiring (per-port request.put): enqueue on valid & room; port ready + -- = FIFO not_full. Element = {finished, idx=const k, req}; idx in HIGH-of-payload + -- bits (below the finished companion), req in the low bits. + req0Ready <= inReqQ0NotFull; + inReqQ0WrEn <= req0Valid and inReqQ0NotFull; + inReqQ0Din <= req0Finished & toSlv(0, IDX_WIDTH_C) & req0Data; + req1Ready <= inReqQ1NotFull; + inReqQ1WrEn <= req1Valid and inReqQ1NotFull; + inReqQ1Din <= req1Finished & toSlv(1, IDX_WIDTH_C) & req1Data; + + -------------------------------------------------------------------------- + -- U_ReqArb : degenerate PORT_COUNT_G=2 arbitration tree = single + -- BinaryPipeOutArbiter (OQ-FSM-SRVARB-01). Its two PipeOut inputs are the + -- two input request FIFO heads; the stored finished companion (top bit of + -- the FIFO element) is the per-channel finish predicate (OQ-FSM-17). Its + -- outFinished companion = isReqFinished(inputReq) drives shouldSaveGrantIdxReg. + -------------------------------------------------------------------------- + U_ReqArb : entity surf.BinaryPipeOutArbiter + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DATA_WIDTH_G => REQIDX_WIDTH_C, -- payload = {idx, req} + MEMORY_TYPE_G => MEMORY_TYPE_G, + FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + clk => clk, + rst => rst, + -- pipeIn1 <- U_InReqQ0 + pipeIn1Valid => inReqQ0Valid, + pipeIn1Dout => inReqQ0Dout(REQIDX_WIDTH_C-1 downto 0), + pipeIn1Finished => inReqQ0Dout(REQIDX_WIDTH_C), -- stored finished companion + pipeIn1Rd => inReqQ0Rd, + -- pipeIn2 <- U_InReqQ1 + pipeIn2Valid => inReqQ1Valid, + pipeIn2Dout => inReqQ1Dout(REQIDX_WIDTH_C-1 downto 0), + pipeIn2Finished => inReqQ1Dout(REQIDX_WIDTH_C), -- stored finished companion + pipeIn2Rd => inReqQ1Rd, + -- arbitrated PipeOut output + outNotEmpty => arbNotEmpty, + outDout => arbDout, + outFinished => arbFinished, + outDeq => arbDeq); + + -------------------------------------------------------------------------- + -- U_PreGrantQ : BSV preGrantIdxQ (mkFIFOF Bit#(idxW)). Written by + -- issueArbitratedReq (conditional on shouldSaveGrantIdxReg), read by + -- dispatchResponse (first each cycle; deq only at response-burst end). + -------------------------------------------------------------------------- + U_PreGrantQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => IDX_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => preGrantWrEn, + din => preGrantDin, + not_full => preGrantNotFull, + rd_clk => clk, + rd_en => preGrantRdEn, + dout => preGrantDout, + valid => preGrantNotEmpty); + + -------------------------------------------------------------------------- + -- Per-port response FIFOs (BSV respVec[k] = mkFIFOF). Written by + -- dispatchResponse into queue preGrantIdx; read side = pure interface + -- wiring of resultSrvVec[k].response (toGet). + -------------------------------------------------------------------------- + U_RespQ0 : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => RESP_WIDTH_G, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => respQ0WrEn, + din => srvRespData, -- broadcast; wr_en selects queue + not_full => respQ0NotFull, + rd_clk => clk, + rd_en => resp0Rd, + dout => respQ0Dout, + valid => respQ0Valid); + + U_RespQ1 : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => RESP_WIDTH_G, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) + port map ( + rst => rst, + wr_clk => clk, + wr_en => respQ1WrEn, + din => srvRespData, -- broadcast; wr_en selects queue + not_full => respQ1NotFull, + rd_clk => clk, + rd_en => resp1Rd, + dout => respQ1Dout, + valid => respQ1Valid); + + -- Interface wiring (per-port response.get / toGet): expose FIFO head. + resp0Valid <= respQ0Valid; + resp0Data <= respQ0Dout; + resp1Valid <= respQ1Valid; + resp1Data <= respQ1Dout; + + -------------------------------------------------------------------------- + -- Combinatorial : the two always-enabled BSV rules (issueArbitratedReq, + -- dispatchResponse). Conflict-free -> two independent `if ...FiresEn` blocks. + -- See ServerArbiter.fsm.md transition table. + -------------------------------------------------------------------------- + comb : process (r, rst, arbNotEmpty, arbDout, arbFinished, srvReqReady, + srvRespValid, srvRespFinished, preGrantNotEmpty, + preGrantNotFull, preGrantDout, respQ0NotFull, respQ1NotFull) is + variable v : RegType; + variable inputReq : slv(REQ_WIDTH_G-1 downto 0); + variable reqIdx : slv(IDX_WIDTH_C-1 downto 0); + variable issueFiresEn : sl; + variable preGrantIdx : natural range 0 to PORT_COUNT_G-1; + variable selRespNotFull : sl; + variable dispatchFiresEn : sl; + begin + -- Latch current state + v := r; + + -- Default Mealy outputs / strobes (no rule firing). + srvReqValid <= '0'; + srvReqData <= (others => '0'); + arbDeq <= '0'; + preGrantWrEn <= '0'; + preGrantDin <= (others => '0'); + srvRespRd <= '0'; + preGrantRdEn <= '0'; + respQ0WrEn <= '0'; + respQ1WrEn <= '0'; + + ---------------------------------------------------------------------- + -- rule issueArbitratedReq + -- {reqIdx, inputReq} = arbDout; reqIdx in the HIGH bits. + -- enq to preGrantIdxQ is CONDITIONAL on shouldSaveGrantIdxReg, so the + -- rule may fire when the flag is '0' even if preGrantIdxQ is full. + ---------------------------------------------------------------------- + inputReq := arbDout(REQ_WIDTH_G-1 downto 0); + reqIdx := arbDout(REQIDX_WIDTH_C-1 downto REQ_WIDTH_G); + + issueFiresEn := arbNotEmpty and srvReqReady and + ((not r.shouldSaveGrantIdxReg) or preGrantNotFull); + + if (issueFiresEn = '1') then + arbDeq <= '1'; -- dequeue arbitrated request + srvReqValid <= '1'; -- srv.request.put(inputReq) + srvReqData <= inputReq; + preGrantWrEn <= r.shouldSaveGrantIdxReg; -- conditional preGrantIdxQ.enq + preGrantDin <= reqIdx; + -- next burst-start = this request was the last of its burst + v.shouldSaveGrantIdxReg := arbFinished; -- = isReqFinished(inputReq) + end if; + + ---------------------------------------------------------------------- + -- rule dispatchResponse + -- route srv.response into respVec[preGrantIdx]; release preGrantIdx only + -- at response-burst end (respFinished). + ---------------------------------------------------------------------- + preGrantIdx := to_integer(unsigned(preGrantDout)); + + if (preGrantIdx = 0) then + selRespNotFull := respQ0NotFull; + else + selRespNotFull := respQ1NotFull; + end if; + + dispatchFiresEn := preGrantNotEmpty and srvRespValid and selRespNotFull; + + if (dispatchFiresEn = '1') then + srvRespRd <= '1'; -- srv.response.get + if (preGrantIdx = 0) then -- respVec[preGrantIdx].enq(resp) + respQ0WrEn <= '1'; + else + respQ1WrEn <= '1'; + end if; + preGrantRdEn <= srvRespFinished; -- deq preGrantIdxQ at burst end + end if; + + -- Synchronous reset + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + end process comb; + + -------------------------------------------------------------------------- + -- Sequential + -------------------------------------------------------------------------- + seq : process (clk, rst) is + begin + if (RST_ASYNC_G) and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/ServerProxy.vhd b/ethernet/RoCEv2/rtl/ServerProxy.vhd new file mode 100644 index 0000000000..b5a998159d --- /dev/null +++ b/ethernet/RoCEv2/rtl/ServerProxy.vhd @@ -0,0 +1,179 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Purpose: Generic server proxy -- buffers requests from srvPort through +-- U_ReqQ to cltPort, and buffers responses from cltPort through +-- U_RespQ to srvPort. No FSM state; purely structural pass-through. +-- OQ-FSM-18: REQ_WIDTH_G / RESP_WIDTH_G are generics; concrete widths for +-- DmaReadProxy / DmaWriteProxy / PermCheckProxy are resolved at +-- the instantiation sites in QueuePair.bsv (QueuePair.vhd Stage 4). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity ServerProxy is + generic ( + TPD_G : time := 1 ns; + REQ_WIDTH_G : natural := 16; -- Bits#(reqType, reqSz) from BSV proviso + RESP_WIDTH_G : natural := 16); -- Bits#(respType, respSz) from BSV proviso + port ( + -- Clock and synchronous active-high reset + clk : in sl; + rst : in sl; + -- srvPort side: upstream caller drives requests and accepts responses + srvReqValid : in sl; + srvReqData : in slv(REQ_WIDTH_G-1 downto 0); + srvReqReady : out sl; -- = U_ReqQ.not_full + srvRespValid : out sl; -- = U_RespQ.valid + srvRespData : out slv(RESP_WIDTH_G-1 downto 0); -- = U_RespQ.dout + srvRespReady : in sl; + -- cltPort side: entity presents requests to and accepts responses from downstream + cltReqValid : out sl; -- = U_ReqQ.valid + cltReqData : out slv(REQ_WIDTH_G-1 downto 0); -- = U_ReqQ.dout + cltReqReady : in sl; + cltRespValid : in sl; + cltRespData : in slv(RESP_WIDTH_G-1 downto 0); + cltRespReady : out sl); -- = U_RespQ.not_full +end entity ServerProxy; + +architecture rtl of ServerProxy is + + -- No live FSM state: mkServerProxy has no mkReg / mkRegU. + -- Placeholder keeps the two-process template structurally complete. + type RegType is record + placeholder : sl; + end record RegType; + + constant REG_INIT_C : RegType := (placeholder => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Outputs from U_ReqQ (request FIFO) + signal reqQNotFull : sl; + signal reqQValid : sl; + signal reqQDout : slv(REQ_WIDTH_G-1 downto 0); + + -- Control inputs to U_ReqQ + signal reqQWrEn : sl; + signal reqQRdEn : sl; + + -- Outputs from U_RespQ (response FIFO) + signal respQNotFull : sl; + signal respQValid : sl; + signal respQDout : slv(RESP_WIDTH_G-1 downto 0); + + -- Control inputs to U_RespQ + signal respQWrEn : sl; + signal respQRdEn : sl; + +begin + + --------------------------------------------------------------------------- + -- Request FIFO: srvPort.request.put -> cltPort.request.get + -- FWFT_EN_G=true: valid/dout map directly to BSV mkFIFOF !empty / first. + -- ADDR_WIDTH_G=4 (depth=16) is the SURF minimum; BSV mkFIFOF is depth-2. + --------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + SYNTH_MODE_G => "inferred", + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => REQ_WIDTH_G, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => reqQWrEn, + din => srvReqData, + not_full => reqQNotFull, + rd_clk => clk, + rd_en => reqQRdEn, + dout => reqQDout, + valid => reqQValid); + + --------------------------------------------------------------------------- + -- Response FIFO: cltPort.response.put -> srvPort.response.get + --------------------------------------------------------------------------- + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + SYNTH_MODE_G => "inferred", + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => RESP_WIDTH_G, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => respQWrEn, + din => cltRespData, + not_full => respQNotFull, + rd_clk => clk, + rd_en => respQRdEn, + dout => respQDout, + valid => respQValid); + + --------------------------------------------------------------------------- + -- Combinatorial process: six BSV SURF-drive wire assignments. + -- All outputs are purely combinatorial (Mealy-degenerate); no r fields + -- contribute to any output. + --------------------------------------------------------------------------- + comb : process (r, srvReqValid, srvRespReady, cltReqReady, cltRespValid, + reqQNotFull, reqQValid, reqQDout, + respQNotFull, respQValid, respQDout) is + variable v : RegType; + begin + v := r; + + -- FIFO write/read enables: BSV mkFIFOF enq/deq with implicit !full / !empty guards + reqQWrEn <= srvReqValid and reqQNotFull; + reqQRdEn <= cltReqReady and reqQValid; + respQWrEn <= cltRespValid and respQNotFull; + respQRdEn <= srvRespReady and respQValid; + + -- srvPort outputs (wired from FIFO status / data) + srvReqReady <= reqQNotFull; + srvRespValid <= respQValid; + srvRespData <= respQDout; + + -- cltPort outputs (wired from FIFO status / data) + cltReqValid <= reqQValid; + cltReqData <= reqQDout; + cltRespReady <= respQNotFull; + + -- Synchronous reset (no-op for placeholder; FIFOs reset via their own rst port) + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/SqQueuePair.vhd b/ethernet/RoCEv2/rtl/SqQueuePair.vhd new file mode 100644 index 0000000000..d47f9a38da --- /dev/null +++ b/ethernet/RoCEv2/rtl/SqQueuePair.vhd @@ -0,0 +1,654 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Structural wiring container for the RDMA Send Queue. `mkSQ` owns NO +-- registered state and NO control FSM: it instantiates the eight Send-Queue +-- sub-blocks, threads their interfaces together, forwards the module-argument +-- interfaces (contextSQ, payloadGenerator, dmaWriteCntrl, permCheckSrv, +-- workReqPipeIn, respPktPipeOut) down to the children, and re-exports a few +-- child interfaces/methods on the SQ interface. The only rule in the BSV body +-- (resetAndClear, QueuePair.bsv:220-225, no_implicit_conditions + +-- fire_when_enabled) is a one-line combinational reset fan-out that asserts the +-- scan buffer's clear whenever contextSQ.statusSQ.comm.isReset is high. +-- +-- Because there is no state to translate, this architecture is emitted as pure +-- structural VHDL (component instances + port map + a handful of concurrent +-- glue assignments) rather than the SURF two-process comb/seq template. There +-- is no RegType / REG_INIT_C — there are zero mkReg/mkRegU/counter/CReg fields +-- in mkSQ. (See FSM spec §"State register": NONE.) +-- +-- Child entity instances (each separately emitted; wiring per FSM spec table): +-- U_ScanFifoF : work.ScanFifoF (mkScanFIFOF — register-array +-- scan FIFO; NOT a surf.Fifo). T_SZ_G=679 (PendingWorkReq), +-- Q_SZ_G=32 (MAX_QP_WR, Settings.bsv:15). +-- U_RetryHandleSq : work.RetryHandleSq (mkRetryHandleSQ) +-- U_NewPending : work.NewPendingWorkReqPipeOut(mkNewPendingWorkReqPipeOut) +-- U_PipeOutMux : work.PipeOutMux (mkPipeOutMux; DATA_WIDTH_G=679) +-- U_PayloadCon : work.PayloadConsumerConAndGen(mkPayloadConsumer) +-- U_ReqGenSq : work.ReqGenSq (mkReqGenSQ) +-- U_RespHandleSq : work.RespHandleSq (mkRespHandleSQ) +-- U_WorkCompGenSq : work.WorkCompGenSq (mkWorkCompGenSQ) +-- +-- SURF components instantiated DIRECTLY by this entity: NONE (mapping.json +-- surf_instances = []). Every FIFO/RAM used by the Send Queue lives inside a +-- child entity; this container only wires children together. +-- +-- mkConnection lowering — pendingWorkReq2Q (QueuePair.bsv:198-200): +-- toGet(reqGenSQ.pendingWorkReqPipeOut) -> toPut(pendingWorkReqBuf.fifof). +-- Lowered to a one-cycle handshake: enqueue fires when the producer PipeOut +-- is valid AND the scan-FIFO fifof side has room; the same strobe deqs the +-- producer. All other links are direct interface-argument passing. +-- +-- Composite word widths (traced from child port declarations / DataTypes.bsv): +-- PendingWorkReq = 679 WorkReq = 601 RdmaPktMetaData = 649 +-- DataStream = 290 WorkComp = 222 WorkCompGenReqSQ= 633 +-- PayloadConReq = 203 PayloadConResp= 53 DmaWriteReq = 419 +-- DmaWriteResp = 53 PayloadGenReq = 199 PayloadGenResp = 2 +-- PermCheckReq = 267 RetryReq = 97 +-- +-- Open questions (out/04-vhdl/OPEN_QUESTIONS.md): OQ-EMIT-SQQP-01 (structural, +-- no two-process template), OQ-EMIT-SQQP-02 (contextSQ flattened to a status +-- port bundle), OQ-EMIT-SQQP-03 (PipeOutMux dependency now emitted+verified), +-- OQ-EMIT-SQQP-04 (level vs pulse clear, inherited from ScanFifoF OQ-FSM-06). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; + +entity SqQueuePair is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active-HIGH reset + RST_ASYNC_G : boolean := false; + -- false = no RDMA READ/atomic support on the requester: U_PayloadCon + -- (read-response landing -> DMA write) is not generated and RespHandleSq + -- treats read/atomic responses as unknown (contract: software never + -- posts READ/atomic work requests). + EN_READ_G : boolean := true); + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; -- FPGA async/sync reset (active-high) + + ----------------------------------------------------------------------- + -- contextSQ.statusSQ status bundle (combinational inputs, fanned out to + -- the children — see OQ-EMIT-SQQP-02). contextSQ.comm.* + the shared + -- next-PSN register read/write. + ----------------------------------------------------------------------- + isReset : in sl; -- comm.isReset (soft clear) + isNonErr : in sl; -- comm.isNonErr + isStableRTS : in sl; -- comm.isStableRTS + isRTS : in sl; -- comm.isRTS + isERR : in sl; -- comm.isERR + isSQD : in sl; -- comm.isSQD + isRTR2RTS : in sl; -- comm.isRTR2RTS + qpType : in slv(3 downto 0); -- getTypeQP + sqpn : in slv(23 downto 0); -- getSQPN + pmtu : in slv(2 downto 0); -- getPMTU + pkey : in slv(15 downto 0); -- getPKEY + dqpn : in slv(23 downto 0); -- getDQPN + sigAll : in sl; -- getSigAll + getMaxRetryCnt : in slv(2 downto 0); -- comm.getMaxRetryCnt + getMaxRnrCnt : in slv(2 downto 0); -- comm.getMaxRnrCnt + getMaxTimeOut : in slv(4 downto 0); -- comm.getMaxTimeOut + getMinRnrTimer : in slv(4 downto 0); -- comm.getMinRnrTimer + getPendingWorkReqNum : in slv(7 downto 0); -- comm.getPendingWorkReqNum + -- contextSQ shared next-PSN register (read + write-back, both in mkSQ) + npsnIn : in slv(23 downto 0); -- contextSQ.getNPSN + npsnOut : out slv(23 downto 0); -- contextSQ.setNPSN value + npsnWrEn : out sl; -- contextSQ.setNPSN write-enable + + ----------------------------------------------------------------------- + -- payloadGenerator : external Server + payload DataStream (module arg, + -- forwarded to U_ReqGenSq). NOT instantiated here (it is payloadGenerator4SQ + -- inside mkQP). + ----------------------------------------------------------------------- + payloadGenReqValid : out sl; -- srvPort.request (put) + payloadGenReqData : out slv(198 downto 0); -- PayloadGenReq + payloadGenReqReady : in sl; + payloadGenRespValid : in sl; -- srvPort.response (get) + payloadGenRespData : in slv(1 downto 0); -- PayloadGenResp + payloadGenRespReady : out sl; + payloadGenDataValid : in sl; -- payloadDataStreamPipeOut + payloadGenDataData : in slv(289 downto 0); -- DataStream + payloadGenDataRdEn : out sl; + + ----------------------------------------------------------------------- + -- dmaWriteCntrl : external Server client (module arg -> U_PayloadCon) + ----------------------------------------------------------------------- + dmaWriteReqValid : out sl; -- request (put) + dmaWriteReqData : out slv(418 downto 0); -- DmaWriteReq + dmaWriteReqReady : in sl; + dmaWriteRespValid : in sl; -- response (get) + dmaWriteRespData : in slv(52 downto 0); -- DmaWriteResp + dmaWriteRespReady : out sl; + + ----------------------------------------------------------------------- + -- permCheckSrv : external Server client (module arg -> U_RespHandleSq) + ----------------------------------------------------------------------- + permReqValid : out sl; -- request (put) + permReqData : out slv(266 downto 0); -- PermCheckReq + permReqReady : in sl; + permRespValid : in sl; -- response (get) + permRespData : in sl; -- Bool (mrCheckResult) + permRespGetEn : out sl; + + ----------------------------------------------------------------------- + -- workReqPipeIn : PipeOut#(WorkReq) (module arg -> U_NewPending) + ----------------------------------------------------------------------- + workReqInValid : in sl; -- notEmpty + workReqInData : in slv(600 downto 0); -- first (WorkReq) + workReqInRdEn : out sl; -- deq + + ----------------------------------------------------------------------- + -- respPktPipeOut : RdmaPktMetaDataAndPayloadPipeOut (module arg). + -- .payload -> U_PayloadCon (payloadPipeIn) + -- .pktMetaData -> U_RespHandleSq (pktMetaDataPipeIn) + ----------------------------------------------------------------------- + respPayloadValid : in sl; -- .payload notEmpty + respPayloadData : in slv(289 downto 0); -- DataStream + respPayloadRdEn : out sl; -- .payload deq + respPktMetaValid : in sl; -- .pktMetaData notEmpty + respPktMetaData : in slv(648 downto 0); -- RdmaPktMetaData + respPktMetaRdEn : out sl; -- .pktMetaData deq + + ----------------------------------------------------------------------- + -- SQ interface (re-exported outputs) + ----------------------------------------------------------------------- + -- rdmaReqDataStreamPipeOut = reqGenSQ.rdmaReqDataStreamPipeOut + rdmaReqDataValid : out sl; + rdmaReqDataData : out slv(289 downto 0); -- DataStream + rdmaReqDataRdEn : in sl; + -- workCompSQ = workCompGenSQ (WorkCompGen interface) + workCompValid : out sl; + workCompData : out slv(221 downto 0); -- WorkComp + workCompRdEn : in sl; + workCompHasErr : out sl; -- workCompGenSQ.hasErr + -- method Bool reqHeaderOutNotEmpty() = reqGenSQ.reqHeaderOutNotEmpty + reqHeaderOutNotEmpty : out sl; + -- method Bool pendingWorkReqNotEmpty() = pendingWorkReqBuf.fifof.notEmpty + pendingWorkReqNotEmpty : out sl); +end entity SqQueuePair; + +architecture rtl of SqQueuePair is + + ----------------------------------------------------------------------------- + -- Word widths (traced from child ports / DataTypes.bsv) + ----------------------------------------------------------------------------- + constant PENDING_WR_C : positive := 679; -- PendingWorkReq + constant MAX_QP_WR_C : positive := 32; -- Settings.bsv MAX_QP_WR (scan depth) + + ----------------------------------------------------------------------------- + -- Inter-child signals + ----------------------------------------------------------------------------- + -- U_ScanFifoF (pendingWorkReqBuf) -------------------------------------------- + signal scanEnqEn : sl; + signal scanEnqData : slv(PENDING_WR_C-1 downto 0); + signal scanDeqEn : sl; + signal scanFifoFirst : slv(PENDING_WR_C-1 downto 0); + signal scanFifoNotEmpty : sl; + signal scanFifoNotFull : sl; + signal scanDeqPulse : sl; + signal scanClearEn : sl; + signal scanHead : slv(PENDING_WR_C-1 downto 0); + signal scanModifyHeadEn : sl; + signal scanModifyHeadData : slv(PENDING_WR_C-1 downto 0); + signal scanPreScanStartEn : sl; + signal scanStartEn : sl; + signal scanStopEn : sl; + signal scanPreScanRestartEn : sl; + signal scanHasScanOut : sl; + signal scanIsScanDone : sl; + signal scanOutValid : sl; + signal scanOutData : slv(PENDING_WR_C-1 downto 0); + signal scanOutReady : sl; + + -- U_RetryHandleSq (retryHandler) --------------------------------------------- + signal retryScanClearInt : sl; -- retryHandler scanCntrl.clear drive + signal retryHasRetryErr : sl; + signal retryIsRetryDone : sl; + signal retryIsRetrying : sl; + signal retryResetReqValid : sl; + signal retryResetReqData : sl; + signal retryResetReqReady : sl; + signal retryTimeOutValid : sl; + signal retryTimeOutData : sl; + signal retryTimeOutGetEn : sl; + signal retrySrvReqValid : sl; + signal retrySrvReqData : slv(96 downto 0); + signal retrySrvReqReady : sl; + signal retrySrvRespValid : sl; + signal retrySrvRespData : sl; + signal retrySrvRespGetEn : sl; + + -- U_NewPending (newPendingWorkReqPiptOut) ------------------------------------ + signal newPendOutValid : sl; + signal newPendOutData : slv(PENDING_WR_C-1 downto 0); + signal newPendOutRdEn : sl; + + -- U_PipeOutMux (pendingWorkReqPipeOut, into reqGenSQ) ------------------------ + signal muxOutValid : sl; + signal muxOutData : slv(PENDING_WR_C-1 downto 0); + signal muxOutRdEn : sl; + + -- U_ReqGenSq (reqGenSQ) ------------------------------------------------------ + signal reqGenPendingOutValid : sl; + signal reqGenPendingOutData : slv(PENDING_WR_C-1 downto 0); + signal reqGenPendingOutRdEn : sl; + signal reqGenWorkCompValid : sl; + signal reqGenWorkCompData : slv(632 downto 0); + signal reqGenWorkCompRdEn : sl; + + -- U_RespHandleSq (respHandleSQ) ---------------------------------------------- + signal respPayloadConReqValid : sl; + signal respPayloadConReqData : slv(202 downto 0); + signal respPayloadConReqReady : sl; + signal respWorkCompValid : sl; + signal respWorkCompData : slv(632 downto 0); + signal respWorkCompRdEn : sl; + + -- U_PayloadCon (payloadConsumer) --------------------------------------------- + signal pcRespOutValid : sl; + signal pcRespOutData : slv(52 downto 0); + signal pcRespOutReady : sl; + + -- pendingWorkReq2Q connection strobe ----------------------------------------- + signal pendingWr2QFire : sl; + +begin + + ----------------------------------------------------------------------------- + -- resetAndClear (QueuePair.bsv:220-225): forward the isReset LEVEL to the scan + -- buffer's clear, OR-ed with any scan-clear the retry handler drives. + -- fire_when_enabled + no_implicit_conditions -> unconditional, ungated. + -- LEVEL-asserted clear, same class as ScanFifoF OQ-FSM-06 (see OQ-EMIT-SQQP-04). + ----------------------------------------------------------------------------- + scanClearEn <= isReset or retryScanClearInt; + + ----------------------------------------------------------------------------- + -- pendingWorkReq2Q (mkConnection): reqGenSQ.pendingWorkReqPipeOut (Get) -> + -- pendingWorkReqBuf.fifof (Put). One-cycle handshake: enqueue when producer + -- valid AND fifof has room; same strobe deqs the producer. + ----------------------------------------------------------------------------- + pendingWr2QFire <= reqGenPendingOutValid and scanFifoNotFull; + scanEnqEn <= pendingWr2QFire; + scanEnqData <= reqGenPendingOutData; + reqGenPendingOutRdEn <= pendingWr2QFire; + + ----------------------------------------------------------------------------- + -- U_ScanFifoF : pendingWorkReqBuf (mkScanFIFOF; register-array scan FIFO). + -- fifof side : enq from reqGenSQ (above), deq by respHandleSQ (toPipeOut). + -- scanCntrl : driven by retryHandler + resetAndClear; head read by retry. + -- scanPipeOut : feeds PipeOutMux.pipeIn1. + ----------------------------------------------------------------------------- + U_ScanFifoF : entity surf.ScanFifoF + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + MEMORY_TYPE_G => "block", -- 679b scan-output queue -> block RAM + Q_SZ_G => MAX_QP_WR_C, -- MAX_QP_WR = 32 + T_SZ_G => PENDING_WR_C) -- PendingWorkReq = 679b + port map ( + clk => clk, + rst => rst, + -- fifof enqueue side + enqEn => scanEnqEn, + enqData => scanEnqData, + -- fifof dequeue / status side + deqEn => scanDeqEn, + fifoFirst => scanFifoFirst, + fifoNotEmpty => scanFifoNotEmpty, + fifoNotFull => scanFifoNotFull, + deqPulse => scanDeqPulse, + fifoSize => open, + -- clear() method + clearEn => scanClearEn, + -- scanCntrl + scanHead => scanHead, + modifyHeadEn => scanModifyHeadEn, + modifyHeadData => scanModifyHeadData, + preScanStartEn => scanPreScanStartEn, + scanStartEn => scanStartEn, + scanStopEn => scanStopEn, + preScanRestartEn => scanPreScanRestartEn, + hasScanOut => scanHasScanOut, + isScanDone => scanIsScanDone, + -- scanPipeOut + scanOutValid => scanOutValid, + scanOutData => scanOutData, + scanOutReady => scanOutReady); + + ----------------------------------------------------------------------------- + -- U_RetryHandleSq : retryHandler + -- mkRetryHandleSQ(contextSQ.statusSQ, pendingWorkReqBuf.fifof.notEmpty, + -- pendingWorkReqBuf.scanCntrl) + ----------------------------------------------------------------------------- + U_RetryHandleSq : entity surf.RetryHandleSq + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + -- comm status + isReset => isReset, + isERR => isERR, + isStableRTS => isStableRTS, + isRTR2RTS => isRTR2RTS, + getMaxRetryCnt => getMaxRetryCnt, + getMaxRnrCnt => getMaxRnrCnt, + getMaxTimeOut => getMaxTimeOut, + getMinRnrTimer => getMinRnrTimer, + getPMTU => pmtu, + -- pending-WR scan status + pendingWorkReqNotEmpty => scanFifoNotEmpty, + scanGetHead => scanHead, + scanIsScanDone => scanIsScanDone, + -- scanCntrl drives + scanClear => retryScanClearInt, + scanStop => scanStopEn, + scanStart => scanStartEn, + scanPreScanStart => scanPreScanStartEn, + scanPreScanRestart => scanPreScanRestartEn, + scanModifyHeadValid => scanModifyHeadEn, + scanModifyHeadData => scanModifyHeadData, + -- status methods + hasRetryErr => retryHasRetryErr, + isRetryDone => retryIsRetryDone, + isRetrying => retryIsRetrying, + -- resetRetryCntAndTimeOutBySQ (driven by respHandleSQ) + resetReqValid => retryResetReqValid, + resetReqData => retryResetReqData, + resetReqReady => retryResetReqReady, + -- notifyTimeOut2SQ (consumed by respHandleSQ) + timeOutNotifValid => retryTimeOutValid, + timeOutNotifData => retryTimeOutData, + timeOutNotifGetEn => retryTimeOutGetEn, + -- srvPort.request (from respHandleSQ) + srvReqValid => retrySrvReqValid, + srvReqData => retrySrvReqData, + srvReqReady => retrySrvReqReady, + -- srvPort.response (to respHandleSQ) + srvRespValid => retrySrvRespValid, + srvRespData => retrySrvRespData, + srvRespGetEn => retrySrvRespGetEn); + + ----------------------------------------------------------------------------- + -- U_NewPending : newPendingWorkReqPiptOut + -- mkNewPendingWorkReqPipeOut(contextSQ.statusSQ, + -- pendingWorkReqBuf.scanCntrl.deqPulse, workReqPipeIn) + ----------------------------------------------------------------------------- + U_NewPending : entity surf.NewPendingWorkReqPipeOut + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + MAX_QP_WR_G => MAX_QP_WR_C) + port map ( + clk => clk, + rst => rst, + isReset_i => isReset, + isERR_i => isERR, + isRTS_i => isRTS, + getPendingWorkReqNum_i => getPendingWorkReqNum, + decrPendingReqCntPulse_i => scanDeqPulse, + workReqValid_i => workReqInValid, + workReqData_i => workReqInData, + workReqRdy_o => workReqInRdEn, + outQValid_o => newPendOutValid, + outQDout_o => newPendOutData, + outQRdEn_i => newPendOutRdEn); + + ----------------------------------------------------------------------------- + -- U_PipeOutMux : pendingWorkReqPipeOut + -- mkPipeOutMux(sel = scanCntrl.hasScanOut, + -- pipeIn1 = scanPipeOut, pipeIn2 = newPendingWorkReqPiptOut) + -- sel='1' -> pipeIn1 (scan output); sel='0' -> pipeIn2 (new pending WRs). + ----------------------------------------------------------------------------- + U_PipeOutMux : entity surf.PipeOutMux + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + DATA_WIDTH_G => PENDING_WR_C) + port map ( + clk => clk, + rst => rst, + sel => scanHasScanOut, + -- pipeIn1 = scanPipeOut + pipeIn1Valid => scanOutValid, + pipeIn1Dout => scanOutData, + pipeIn1RdEn => scanOutReady, + -- pipeIn2 = newPendingWorkReqPiptOut + pipeIn2Valid => newPendOutValid, + pipeIn2Dout => newPendOutData, + pipeIn2RdEn => newPendOutRdEn, + -- output -> reqGenSQ.pendingWorkReqPipeIn + pipeOutValid => muxOutValid, + pipeOutDout => muxOutData, + pipeOutRdEn => muxOutRdEn); + + ----------------------------------------------------------------------------- + -- U_ReqGenSq : reqGenSQ + -- mkReqGenSQ(contextSQ, payloadGenerator, pendingWorkReqPipeOut, + -- pendingWorkReqBuf.fifof.notEmpty) + ----------------------------------------------------------------------------- + U_ReqGenSq : entity surf.ReqGenSq + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + -- contextSQ.statusSQ bundle + isReset => isReset, + isStableRTS => isStableRTS, + isRTS => isRTS, + isERR => isERR, + isSQD => isSQD, + qpType => qpType, + sqpn => sqpn, + pmtu => pmtu, + pkey => pkey, + dqpn => dqpn, + sigAll => sigAll, + npsnIn => npsnIn, + npsnOut => npsnOut, + npsnWrEn => npsnWrEn, + -- pendingWorkReqPipeIn = PipeOutMux output + pendingWorkReqInValid => muxOutValid, + pendingWorkReqInData => muxOutData, + pendingWorkReqInRdEn => muxOutRdEn, + pendingWorkReqBufNotEmpty => scanFifoNotEmpty, + -- payloadGenerator server + payload stream + payloadGenReqValid => payloadGenReqValid, + payloadGenReqData => payloadGenReqData, + payloadGenReqReady => payloadGenReqReady, + payloadGenRespValid => payloadGenRespValid, + payloadGenRespData => payloadGenRespData, + payloadGenRespReady => payloadGenRespReady, + payloadDataStreamValid => payloadGenDataValid, + payloadDataStreamData => payloadGenDataData, + payloadDataStreamRdEn => payloadGenDataRdEn, + -- pendingWorkReqPipeOut -> back into scan buffer fifof (pendingWorkReq2Q) + pendingWorkReqOutValid => reqGenPendingOutValid, + pendingWorkReqOutData => reqGenPendingOutData, + pendingWorkReqOutRdEn => reqGenPendingOutRdEn, + -- workCompGenReqPipeOut -> workCompGenSQ + workCompGenReqValid => reqGenWorkCompValid, + workCompGenReqData => reqGenWorkCompData, + workCompGenReqRdEn => reqGenWorkCompRdEn, + -- rdmaReqDataStreamPipeOut -> SQ interface + rdmaReqDataValid => rdmaReqDataValid, + rdmaReqDataData => rdmaReqDataData, + rdmaReqDataRdEn => rdmaReqDataRdEn, + -- method reqHeaderOutNotEmpty + reqHeaderOutNotEmpty => reqHeaderOutNotEmpty); + + ----------------------------------------------------------------------------- + -- U_PayloadCon : payloadConsumer + -- mkPayloadConsumer(contextSQ.statusSQ, dmaWriteCntrl, respPktPipeOut.payload) + -- .request <- respHandleSQ ; .response -> workCompGenSQ + ----------------------------------------------------------------------------- + -- Pruned when EN_READ_G=false: RespHandleSq's forced classifiers keep + -- payloadConReq requests to the discard arm only (drained by the tied + -- ready), the response face never produces (WorkCompGenSq never waits on + -- it, wcWaitDma is constant '0'), and the resp-pipe payload leg is drained. + GEN_NO_PAYLOAD_CON : if not EN_READ_G generate + respPayloadRdEn <= '1'; + respPayloadConReqReady <= '1'; + pcRespOutValid <= '0'; + pcRespOutData <= (others => '0'); + dmaWriteReqValid <= '0'; + dmaWriteReqData <= (others => '0'); + dmaWriteRespReady <= '1'; + end generate GEN_NO_PAYLOAD_CON; + + GEN_PAYLOAD_CON : if EN_READ_G generate + U_PayloadCon : entity surf.PayloadConsumerConAndGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + isReset => isReset, + isNonErr => isNonErr, + isErr => isERR, + -- srvPort.request (from respHandleSQ.payloadConReqPort) + reqInValid => respPayloadConReqValid, + reqInData => respPayloadConReqData, + reqInReady => respPayloadConReqReady, + -- srvPort.response (to workCompGenSQ) + respOutReady => pcRespOutReady, + respOutValid => pcRespOutValid, + respOutData => pcRespOutData, + -- payloadPipeIn = respPktPipeOut.payload + payloadPipeInValid => respPayloadValid, + payloadPipeInData => respPayloadData, + payloadPipeInReady => respPayloadRdEn, + -- dmaWriteSrv client -> dmaWriteCntrl ports + dmaWriteReqValid => dmaWriteReqValid, + dmaWriteReqData => dmaWriteReqData, + dmaWriteReqReady => dmaWriteReqReady, + dmaWriteRespValid => dmaWriteRespValid, + dmaWriteRespData => dmaWriteRespData, + dmaWriteRespReady => dmaWriteRespReady); + end generate GEN_PAYLOAD_CON; + + ----------------------------------------------------------------------------- + -- U_RespHandleSq : respHandleSQ + -- mkRespHandleSQ(contextSQ, retryHandler, permCheckSrv, + -- toPipeOut(pendingWorkReqBuf.fifof), respPktPipeOut.pktMetaData, + -- payloadConsumer.request) + ----------------------------------------------------------------------------- + U_RespHandleSq : entity surf.RespHandleSq + generic map ( + TPD_G => TPD_G, + EN_READ_G => EN_READ_G) + port map ( + clk => clk, + rst => rst, + -- comm status + isReset => isReset, + isRTS => isRTS, + isERR => isERR, + isStableRTS => isStableRTS, + getPMTU => pmtu, + getSQPN => sqpn, + getNPSN => npsnIn, + -- pendingWorkReqPipeIn = toPipeOut(pendingWorkReqBuf.fifof) + pendingWrValid => scanFifoNotEmpty, + pendingWrData => scanFifoFirst, + pendingWrDeq => scanDeqEn, + -- pktMetaDataPipeIn = respPktPipeOut.pktMetaData + pktMetaValid => respPktMetaValid, + pktMetaData => respPktMetaData, + pktMetaDeq => respPktMetaRdEn, + -- payloadConReqPort -> payloadConsumer.request + payloadConReqValid => respPayloadConReqValid, + payloadConReqData => respPayloadConReqData, + payloadConReqReady => respPayloadConReqReady, + -- retryHandler.resetRetryCntAndTimeOutBySQ + retryResetValid => retryResetReqValid, + retryResetData => retryResetReqData, + retryResetReady => retryResetReqReady, + -- retryHandler.srvPort.request + retryReqValid => retrySrvReqValid, + retryReqData => retrySrvReqData, + retryReqReady => retrySrvReqReady, + -- retryHandler.srvPort.response + retryRespValid => retrySrvRespValid, + retryRespData => retrySrvRespData, + retryRespGetEn => retrySrvRespGetEn, + -- retryHandler.notifyTimeOut2SQ + timeOutValid => retryTimeOutValid, + timeOutData => retryTimeOutData, + timeOutGetEn => retryTimeOutGetEn, + -- retryHandler.isRetrying + isRetrying => retryIsRetrying, + -- permCheckSrv client + permReqValid => permReqValid, + permReqData => permReqData, + permReqReady => permReqReady, + permRespValid => permRespValid, + permRespData => permRespData, + permRespGetEn => permRespGetEn, + -- workCompGenReqPipeOut -> workCompGenSQ + wcGenReqValid => respWorkCompValid, + wcGenReqData => respWorkCompData, + wcGenReqRdEn => respWorkCompRdEn); + + ----------------------------------------------------------------------------- + -- U_WorkCompGenSq : workCompGenSQ + -- mkWorkCompGenSQ(contextSQ.statusSQ, payloadConsumer.response, + -- reqGenSQ.workCompGenReqPipeOut, respHandleSQ.workCompGenReqPipeOut) + ----------------------------------------------------------------------------- + U_WorkCompGenSq : entity surf.WorkCompGenSq + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + -- comm status + isReset_i => isReset, + isRTS_i => isRTS, + isStableRTS_i => isStableRTS, + isERR_i => isERR, + getSigAll_i => sigAll, + getPKEY_i => pkey, + getSQPN_i => sqpn, + -- payloadConRespPort <- payloadConsumer.response + payloadConRespValid_i => pcRespOutValid, + payloadConRespData_i => pcRespOutData, + payloadConRespGetEn_o => pcRespOutReady, + -- wcGenReqPipeInFromReqGenInSQ <- reqGenSQ.workCompGenReqPipeOut + reqGenInValid_i => reqGenWorkCompValid, + reqGenInData_i => reqGenWorkCompData, + reqGenInDeq_o => reqGenWorkCompRdEn, + -- wcGenReqPipeInFromRespHandleInSQ <- respHandleSQ.workCompGenReqPipeOut + respHandleInValid_i => respWorkCompValid, + respHandleInData_i => respWorkCompData, + respHandleInDeq_o => respWorkCompRdEn, + -- workCompPipeOut -> SQ interface (workCompSQ) + workCompValid_o => workCompValid, + workCompData_o => workCompData, + workCompRdEn_i => workCompRdEn, + -- hasErr() + hasErr_o => workCompHasErr); + + ----------------------------------------------------------------------------- + -- pendingWorkReqNotEmpty method = pendingWorkReqBuf.fifof.notEmpty + ----------------------------------------------------------------------------- + pendingWorkReqNotEmpty <= scanFifoNotEmpty; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/SqSendQ.vhd b/ethernet/RoCEv2/rtl/SqSendQ.vhd new file mode 100644 index 0000000000..8bee9eadb9 --- /dev/null +++ b/ethernet/RoCEv2/rtl/SqSendQ.vhd @@ -0,0 +1,385 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Pure structural wiring entity: wires three child entities +-- (DmaReadCntrlGen -> PayloadGeneratorGen -> SendQ, BSV module-parameter +-- chain) and two DMA-read FIFOs (the dmaReadClt boundary) together. The only +-- local sequential behavior is a one-cycle clearReg pulse (BSV rule +-- resetAndClear), broadcast as `clear` to all three children's clear input. +-- +-- Module-parameter chaining (all BSV constructor args, NOT method calls): +-- dmaReadSrv = toGPServer(dmaReadReqQ, dmaReadRespQ) -- U_DmaReadCntrl's external server +-- dmaReadCntrl <- mkDmaReadCntrl(clearReg, dmaReadSrv) -- U_DmaReadCntrl +-- payloadGenerator <- mkPayloadGenerator(clearReg, dmaReadCntrl) -- U_PayloadGenerator +-- sq <- mkSendQ(clearReg, payloadGenerator) -- U_SendQ +-- +-- U_DmaReadCntrl.cancelEn is never driven at this level: mkSQ does not call +-- dmaReadCntrl.cancel() (grep-verified against PayloadGen.bsv/SendQ.bsv), and +-- SQ's top-level interface exposes no cancel method. Tied to '0' (judgment +-- call, see out/04-vhdl/OPEN_QUESTIONS.md OQ-EMIT-SQSQ-01). +-- U_DmaReadCntrl.isIdle and U_PayloadGenerator.payloadNotEmpty are likewise +-- never read by mkPayloadGenerator/mkSendQ (grep-verified) and are not part +-- of the SQ interface; left open, mirroring DmaReadCntrlGen.vhd's own +-- U_AddrChunkSrv.isIdle => open precedent. +-- +-- SQ interface (BSV) -> ports: +-- dmaReadClt (Client#(DmaReadReq,DmaReadResp), via toGPClient(dmaReadReqQ, +-- dmaReadRespQ)): request is a Get (external side dequeues the FIFO) -> +-- dmaReadReq{Valid,Data,RdEn}; response is a Put (external side enqueues +-- the FIFO) -> dmaReadResp{Valid,Data,Ready}. +-- sendQ (SendQ interface, re-exported straight from U_SendQ): srvPort -> +-- wqeReq{Valid,Data,Ready} / sendResp{Valid,Data,Ready}; udpInfoPipeOut -> +-- udpInfo{Valid,Data,RdEn}; rdmaDataStreamPipeOut -> rdmaData{Valid,Data, +-- RdEn}; isEmpty -> isEmpty (fsm.md's Notes section omitted this method; +-- it is a real part of the SQ.sendQ sub-interface so it is exposed here, +-- see OQ-EMIT-SQSQ-02). +-- clearAll() Action method -> clearAllEn (in) / clearAllReady (out, = +-- !clearReg, the method's implicit condition). +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_DmaReadReqQ : surf.Fifo DATA_WIDTH_G=176 (DmaReadReq) +-- U_DmaReadRespQ : surf.Fifo DATA_WIDTH_G=383 (DmaReadResp) +-- Both are pure plumbing between U_DmaReadCntrl and the external dmaReadClt +-- port (not driven by the local clearReg FSM; their rst is the global reset +-- only per fsm.md, since the BSV resetAndClear rule body has no .clear()). +-- +-- Child entities instantiated (out/04-vhdl/): +-- U_DmaReadCntrl : DmaReadCntrlGen (from mkDmaReadCntrl_Gen) +-- U_PayloadGenerator: PayloadGeneratorGen (from mkPayloadGenerator_Gen) +-- U_SendQ : SendQ (from mkSendQ) +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity SqSendQ is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + + -- clearAll() Action method (guard !clearReg) + clearAllEn : in sl; + clearAllReady : out sl; -- = not clearReg (implicit condition) + + -- sendQ.srvPort : Server#(WorkQueueElem, SendResp) (re-exported from U_SendQ) + wqeReqValid : in sl; + wqeReqData : in slv(1720 downto 0); -- WorkQueueElem packed + wqeReqReady : out sl; + sendRespValid : out sl; + sendRespData : out slv(0 downto 0); -- SendResp (0-width -> 1-bit token) + sendRespReady : in sl; + + -- sendQ.udpInfoPipeOut : PipeOut#(PktInfo4UDP) (re-exported from U_SendQ) + udpInfoValid : out sl; + udpInfoData : out slv(190 downto 0); + udpInfoRdEn : in sl; + + -- sendQ.rdmaDataStreamPipeOut : DataStreamPipeOut (re-exported from U_SendQ) + rdmaDataValid : out sl; + rdmaDataData : out slv(289 downto 0); + rdmaDataRdEn : in sl; + + -- sendQ.isEmpty() method result (re-exported from U_SendQ) + isEmpty : out sl; + + -- dmaReadClt : Client#(DmaReadReq, DmaReadResp) (via toGPClient(U_DmaReadReqQ, U_DmaReadRespQ)) + -- request side is a Get: external consumer dequeues U_DmaReadReqQ + dmaReadReqValid : out sl; + dmaReadReqData : out slv(175 downto 0); -- DmaReadReq packed + dmaReadReqRdEn : in sl; + -- response side is a Put: external producer enqueues U_DmaReadRespQ + dmaReadRespValid : in sl; + dmaReadRespData : in slv(382 downto 0); -- DmaReadResp packed + dmaReadRespReady : out sl); +end entity SqSendQ; + +architecture rtl of SqSendQ is + + -- Local FSM state: the entire clearReg pulse (mkReg(False)) + type RegType is record + clearReg : sl; + end record RegType; + + constant REG_INIT_C : RegType := ( + clearReg => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- Registered clear broadcast to all three children (Moore; fsm.md §Output style) + signal clear : sl; + + -- U_DmaReadReqQ (DmaReadReq, 176b): wr = U_DmaReadCntrl (client Put), rd = external dmaReadClt.request (Get) + signal dmaReadReqQWrEn : sl; + signal dmaReadReqQDin : slv(175 downto 0); + signal dmaReadReqQNotFull : sl; + signal dmaReadReqQValid : sl; + signal dmaReadReqQDout : slv(175 downto 0); + + -- U_DmaReadRespQ (DmaReadResp, 383b): wr = external dmaReadClt.response (Put), rd = U_DmaReadCntrl (client Get) + signal dmaReadRespQNotFull : sl; + signal dmaReadRespQValid : sl; + signal dmaReadRespQDout : slv(382 downto 0); + signal dmaReadRespQRdEn : sl; + + -- U_DmaReadCntrl <-> U_PayloadGenerator (dmaReadCntrl module parameter) + signal dmaCntrlReqValid : sl; + signal dmaCntrlReqData : slv(1162 downto 0); + signal dmaCntrlReqReady : sl; + signal dmaCntrlRespValid : sl; + signal dmaCntrlRespData : slv(384 downto 0); + signal dmaCntrlRespReady : sl; + signal sgePktMetaValid : sl; + signal sgePktMetaData : slv(53 downto 0); + signal sgePktMetaRdEn : sl; + signal sgeMergedValid : sl; + signal sgeMergedData : slv(7 downto 0); + signal sgeMergedRdEn : sl; + + -- U_PayloadGenerator <-> U_SendQ (payloadGenerator module parameter) + signal payloadGenReqValid : sl; + signal payloadGenReqData : slv(1227 downto 0); + signal payloadGenReqReady : sl; + signal payloadGenRespValid : sl; + signal payloadGenRespData : slv(80 downto 0); + signal payloadGenRespReady : sl; + signal payloadTotalMetaValid : sl; + signal payloadTotalMetaData : slv(26 downto 0); + signal payloadTotalMetaRdEn : sl; + signal payloadDataStreamValid : sl; + signal payloadDataStreamData : slv(289 downto 0); + signal payloadDataStreamRdEn : sl; + +begin + + -- clearAll() method's implicit condition (combinational from r, not v) + clearAllReady <= not r.clearReg; + + -- Registered clear broadcast (Moore) to all three children's clear input + clear <= r.clearReg; + + --------------------------------------------------------------------------- + -- U_DmaReadReqQ : surf.Fifo + -- Plumbing between U_DmaReadCntrl (producer) and the external dmaReadClt + -- request Get (consumer). NOT cleared by clearReg (fsm.md: rule body has + -- no .clear()); rst is the global reset only. + --------------------------------------------------------------------------- + U_DmaReadReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 176, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => dmaReadReqQWrEn, -- U_DmaReadCntrl client Put + din => dmaReadReqQDin, + not_full => dmaReadReqQNotFull, + rd_clk => clk, + rd_en => dmaReadReqRdEn, -- external dmaReadClt.request Get + dout => dmaReadReqQDout, + valid => dmaReadReqQValid); + + dmaReadReqValid <= dmaReadReqQValid; + dmaReadReqData <= dmaReadReqQDout; + + --------------------------------------------------------------------------- + -- U_DmaReadRespQ : surf.Fifo + -- Plumbing between the external dmaReadClt response Put (producer) and + -- U_DmaReadCntrl (consumer). NOT cleared by clearReg; rst is the global + -- reset only. + --------------------------------------------------------------------------- + U_DmaReadRespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 383, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => dmaReadRespValid, -- external dmaReadClt.response Put + din => dmaReadRespData, + not_full => dmaReadRespQNotFull, + rd_clk => clk, + rd_en => dmaReadRespQRdEn, -- U_DmaReadCntrl client Get + dout => dmaReadRespQDout, + valid => dmaReadRespQValid); + + dmaReadRespReady <= dmaReadRespQNotFull; + + --------------------------------------------------------------------------- + -- U_DmaReadCntrl : DmaReadCntrlGen (child entity, not SURF) + -- BSV: dmaReadCntrl <- mkDmaReadCntrl(clearReg, dmaReadSrv). clearAll port + -- takes the registered clearReg broadcast. cancelEn tied '0' (never called + -- at this level, OQ-EMIT-SQSQ-01); isIdle left open (never read). + --------------------------------------------------------------------------- + U_DmaReadCntrl : entity surf.DmaReadCntrlGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAll => clear, + cancelEn => '0', + reqInValid => dmaCntrlReqValid, -- from U_PayloadGenerator + reqInData => dmaCntrlReqData, + reqInReady => dmaCntrlReqReady, + respOutReady => dmaCntrlRespReady, -- from U_PayloadGenerator + respOutValid => dmaCntrlRespValid, + respOutData => dmaCntrlRespData, + sgeMergedRdEn => sgeMergedRdEn, -- from U_PayloadGenerator + sgeMergedValid => sgeMergedValid, + sgeMergedData => sgeMergedData, + sgePktMetaRdEn => sgePktMetaRdEn, -- from U_PayloadGenerator + sgePktMetaValid => sgePktMetaValid, + sgePktMetaData => sgePktMetaData, + dmaReqValid => dmaReadReqQWrEn, -- to U_DmaReadReqQ + dmaReqOut => dmaReadReqQDin, + dmaReqReady => dmaReadReqQNotFull, + dmaRespValid => dmaReadRespQValid, -- from U_DmaReadRespQ + dmaRespIn => dmaReadRespQDout, + dmaRespReady => dmaReadRespQRdEn, + isIdle => open); + + --------------------------------------------------------------------------- + -- U_PayloadGenerator : PayloadGeneratorGen (child entity, not SURF) + -- BSV: payloadGenerator <- mkPayloadGenerator(clearReg, dmaReadCntrl). + -- clearAllI port takes the registered clearReg broadcast. dmaReadCntrl + -- module parameter fully wired to U_DmaReadCntrl above. payloadNotEmpty + -- left open (never read by mkSendQ, OQ-EMIT-SQSQ-01). + --------------------------------------------------------------------------- + U_PayloadGenerator : entity surf.PayloadGeneratorGen + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAllI => clear, + reqInValid => payloadGenReqValid, -- from U_SendQ + reqInData => payloadGenReqData, + reqInReady => payloadGenReqReady, + respOutReady => payloadGenRespReady, -- from U_SendQ + respOutValid => payloadGenRespValid, + respOutData => payloadGenRespData, + totalMetaDataDeq => payloadTotalMetaRdEn, -- from U_SendQ + totalMetaDataFirst => payloadTotalMetaData, + totalMetaDataNotEmpty => payloadTotalMetaValid, + payloadDataStreamDeq => payloadDataStreamRdEn, -- from U_SendQ + payloadDataStreamFirst => payloadDataStreamData, + payloadDataStreamNotEmpty => payloadDataStreamValid, + payloadNotEmpty => open, + dmaReadCntrlReqValid => dmaCntrlReqValid, -- to U_DmaReadCntrl + dmaReadCntrlReqData => dmaCntrlReqData, + dmaReadCntrlReqReady => dmaCntrlReqReady, + dmaReadCntrlRespValid => dmaCntrlRespValid, -- from U_DmaReadCntrl + dmaReadCntrlRespData => dmaCntrlRespData, + dmaReadCntrlRespReady => dmaCntrlRespReady, + sgePktMetaValid => sgePktMetaValid, -- from U_DmaReadCntrl + sgePktMetaData => sgePktMetaData, + sgePktMetaRdEn => sgePktMetaRdEn, + sgeMergedMetaValid => sgeMergedValid, -- from U_DmaReadCntrl + sgeMergedMetaData => sgeMergedData, + sgeMergedMetaRdEn => sgeMergedRdEn); + + --------------------------------------------------------------------------- + -- U_SendQ : SendQ (child entity, not SURF) + -- BSV: sq <- mkSendQ(clearReg, payloadGenerator). clearAllI port takes the + -- registered clearReg broadcast. payloadGenerator module parameter fully + -- wired to U_PayloadGenerator above. srvPort/udpInfoPipeOut/ + -- rdmaDataStreamPipeOut/isEmpty are re-exported straight to this entity's + -- top-level ports. + --------------------------------------------------------------------------- + U_SendQ : entity surf.SendQ + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + clearAllI => clear, + reqReqValid => wqeReqValid, -- re-export: srvPort.request + reqReqData => wqeReqData, + reqReqReady => wqeReqReady, + respValid => sendRespValid, -- re-export: srvPort.response + respData => sendRespData, + respReady => sendRespReady, + udpInfoValid => udpInfoValid, -- re-export: udpInfoPipeOut + udpInfoData => udpInfoData, + udpInfoRdEn => udpInfoRdEn, + rdmaDataValid => rdmaDataValid, -- re-export: rdmaDataStreamPipeOut + rdmaDataData => rdmaDataData, + rdmaDataRdEn => rdmaDataRdEn, + payloadGenReqValid => payloadGenReqValid, -- to U_PayloadGenerator + payloadGenReqData => payloadGenReqData, + payloadGenReqReady => payloadGenReqReady, + payloadGenRespValid => payloadGenRespValid, -- from U_PayloadGenerator + payloadGenRespData => payloadGenRespData, + payloadGenRespReady => payloadGenRespReady, + payloadTotalMetaValid => payloadTotalMetaValid, -- from U_PayloadGenerator + payloadTotalMetaData => payloadTotalMetaData, + payloadTotalMetaRdEn => payloadTotalMetaRdEn, + payloadDataStreamValid => payloadDataStreamValid, -- from U_PayloadGenerator + payloadDataStreamData => payloadDataStreamData, + payloadDataStreamRdEn => payloadDataStreamRdEn, + isEmpty => isEmpty); -- re-export: sendQ.isEmpty() + + --------------------------------------------------------------------------- + -- Combinatorial process: the entire local FSM is the clearReg pulse. + --------------------------------------------------------------------------- + comb : process (r, rst, clearAllEn) is + variable v : RegType; + begin + v := r; + + -- resetAndClear (fire_when_enabled, no_implicit_conditions) dominates; + -- clearAll() method write is mutually exclusive by guard (fsm.md + -- §Conflicts/scheduling) so the if/elsif order is redundant-safe. + if r.clearReg = '1' then + v.clearReg := '0'; -- rule resetAndClear + elsif clearAllEn = '1' then + v.clearReg := '1'; -- clearAll() method (guard !clearReg) + end if; + + -- Synchronous reset (matches BSV mkReg(False)) + if rst = '1' then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/TagVecSrv.vhd b/ethernet/RoCEv2/rtl/TagVecSrv.vhd new file mode 100644 index 0000000000..2acf2dbf07 --- /dev/null +++ b/ethernet/RoCEv2/rtl/TagVecSrv.vhd @@ -0,0 +1,383 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Tag-vector allocation server. +-- Maintains a register array of V_SZ_G tagged data entries. Clients issue +-- insert (find a free slot, write data) or remove (look up by index, clear +-- tag) requests through the request FIFO and receive results through the +-- response FIFO. One request is in flight at a time; each insert/remove takes +-- exactly two clock cycles (RECV_REQ -> RESP_*). A clear() pulse flushes both +-- FIFOs and resets all tags. +-- +-- Generated from: +-- BSV source : src-bsv/MetaData.bsv (module mkTagVecSrv, lines 35-151) +-- FSM spec : out/03-fsm/TagVecSrv.fsm.md +-- Mapping : out/02-partition/mapping.json (entity TagVecSrv) +-- +-- SURF components instantiated: +-- surf.Fifo (base/fifo/rtl/Fifo.vhd) x2 -> U_ReqQ, U_RespQ +-- +-- BSV FIFOF.clear is modelled per OQ-FSM-01 (out/03-fsm/RESOLVED.md): the +-- surf.Fifo has no flush port, so clear is a one-cycle synchronous rst pulse +-- asserted on both FIFOs simultaneously (sync config, active-high rst). +-- +-- mkRegU fields (no BSV reset value): dataVec, maybeInsertIdxReg, +-- respSuccessReg. Initialised to all-'0' in REG_INIT_C; each is always written +-- before it is read (see OQ-FSM-04). Don't-care at reset. +-- +-- REVISION (RESOLVED OQ-FSM-MDSRV-01 sec.4.2): added `tagValid` output — the +-- full tag-valid vector (= registered tagVec), so a parent with several +-- concurrent isValid-style readers (MetaDataPDs: PermCheckSrv's mrLkup vs +-- MetaDataSrv's isValidPD/getMRs4PD-valid) reads validity without contending +-- for the single muxed getItem port. Purely additive; existing users map it +-- to `open`. +------------------------------------------------------------------------------- +-- This file is part of the BSV->VHDL transpilation output. It targets the SURF +-- VHDL library and follows the SURF coding standard (style/vhdl-style-rules.md). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity TagVecSrv is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset + RST_ASYNC_G : boolean := false; + MEMORY_TYPE_G : string := "distributed"; -- small FIFOs + V_SZ_G : positive := 4; -- number of tag entries (power of 2, >= 1) + T_SZ_G : positive := 32); -- data width per entry + port ( + clk : in sl; + rst : in sl := not RST_POLARITY_G; + -- Request input (srvPort.request -> reqQ write side) + reqValid : in sl; -- parent enqueues a request + reqData : in slv(T_SZ_G + log2(V_SZ_G) downto 0); -- {insOrRem,insVal,remIdx} + reqReady : out sl; -- reqQ not_full (backpressure) + -- Response output (respQ read side -> srvPort.response) + respValid : out sl; -- respQ has a response + respData : out slv(T_SZ_G + log2(V_SZ_G) downto 0); -- {success,idx,value} + respReady : in sl; -- parent dequeues a response + -- getItem() combinational lookup + getItemIdx : in slv(log2(V_SZ_G)-1 downto 0); + getItemOut : out slv(T_SZ_G downto 0); -- {valid, dataVec(idx)} + -- Full tag-valid vector export (combinational = r.tagVec). Added per + -- RESOLVED OQ-FSM-MDSRV-01 sec.4.2 so parents with multiple concurrent + -- isValid-style readers need not arbitrate the single getItem port. + -- Leave open where unused. + tagValid : out slv(V_SZ_G-1 downto 0); + -- Status methods + notEmpty : out sl; + notFull : out sl; + -- clear() method + clearEn : in sl); +end TagVecSrv; + +architecture rtl of TagVecSrv is + + ----------------------------------------------------------------------------- + -- Constants (widths traced from BSV provisos) + -- vLogSz = TLog(vSz) ; cntSz = TAdd(1, vLogSz) + -- reqQ/respQ width = 1 + tSz + vLogSz (Tuple3 packing) + ----------------------------------------------------------------------------- + constant V_LOG_SZ_C : integer := log2(V_SZ_G); -- index bit width + constant CNT_SZ_C : integer := V_LOG_SZ_C + 1; -- item-count width + constant FIFO_WIDTH_C : integer := 1 + T_SZ_G + V_LOG_SZ_C; + constant FIFO_ADDR_WIDTH_C : integer := 4; -- surf.Fifo minimum + + + ----------------------------------------------------------------------------- + -- Types + ----------------------------------------------------------------------------- + type TagVecStateType is ( + RECV_REQ_S, -- TAG_VEC_RECV_REQ = 0 + RESP_INSERT_S, -- TAG_VEC_RESP_INSERT = 1 + RESP_REMOVE_S); -- TAG_VEC_RESP_REMOVE = 2 + + type DataVecType is array (0 to V_SZ_G-1) of slv(T_SZ_G-1 downto 0); + + type RegType is record + tagVecStateReg : TagVecStateType; + dataVec : DataVecType; -- mkRegU (no reset) + tagVec : slv(V_SZ_G-1 downto 0); -- mkReg(False) + maybeInsertIdxReg : slv(V_LOG_SZ_C downto 0); -- {valid, index}, mkRegU + respSuccessReg : sl; -- mkRegU + emptyReg : sl; -- mkReg(True) + fullReg : sl; -- mkReg(False) + clearReg : sl; -- mkCReg(2,False) collapsed + itemCnt : slv(CNT_SZ_C-1 downto 0); -- mkCount(0) + end record RegType; + + constant REG_INIT_C : RegType := ( + tagVecStateReg => RECV_REQ_S, + dataVec => (others => (others => '0')), -- mkRegU: don't-care + tagVec => (others => '0'), + maybeInsertIdxReg => (others => '0'), -- mkRegU: don't-care + respSuccessReg => '0', -- mkRegU: don't-care + emptyReg => '1', + fullReg => '0', + clearReg => '0', + itemCnt => (others => '0')); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- SURF Fifo interface signals + signal reqQValid : sl; -- U_ReqQ.valid + signal reqQDout : slv(FIFO_WIDTH_C-1 downto 0); -- U_ReqQ.dout + signal reqQRdEn : sl; -- U_ReqQ.rd_en (deq) + signal respQNotFull : sl; -- U_RespQ.not_full + signal respQWrEn : sl; -- U_RespQ.wr_en (enq) + signal respQDin : slv(FIFO_WIDTH_C-1 downto 0); -- U_RespQ.din + + -- Clear / reset plumbing + signal clrFifos : sl; -- clearAll flush strobe + signal fifoRst : sl; -- rst (active high) OR clrFifos + signal rstActiveHigh : sl; + +begin + + ----------------------------------------------------------------------------- + -- Request FIFO (BSV reqQ : FIFOF#(Tuple3#(Bool, a, UInt#(vLogSz)))) + -- wr side driven by parent; rd side (deq) driven by the FSM. + ----------------------------------------------------------------------------- + U_ReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', -- active-high (clear-via-rst, OQ-FSM-01) + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, -- BSV first/deq peek semantics + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => FIFO_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => reqValid, -- parent enqueue + din => reqData, + not_full => reqReady, -- backpressure to parent + rd_clk => clk, + rd_en => reqQRdEn, -- FSM dequeue + dout => reqQDout, + valid => reqQValid); + + ----------------------------------------------------------------------------- + -- Response FIFO (BSV respQ : FIFOF#(Tuple3#(Bool, UInt#(vLogSz), a))) + -- wr side (enq) driven by the FSM; rd side driven by parent. + ----------------------------------------------------------------------------- + U_RespQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => MEMORY_TYPE_G, + DATA_WIDTH_G => FIFO_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C) + port map ( + rst => fifoRst, + wr_clk => clk, + wr_en => respQWrEn, -- FSM enqueue + din => respQDin, + not_full => respQNotFull, -- FSM reads (enqueue guard) + rd_clk => clk, + rd_en => respReady, -- parent dequeue + dout => respData, + valid => respValid); + + -- Active-high reset for the FIFO clear mechanism (OQ-FSM-01 RESOLVED): + -- a one-cycle clrFifos pulse is OR-ed with the global reset into both FIFOs. + rstActiveHigh <= rst when RST_POLARITY_G = '1' else not rst; + fifoRst <= rstActiveHigh or clrFifos; + + ----------------------------------------------------------------------------- + -- Combinatorial process (two-process FSM): next state + outputs into v. + ----------------------------------------------------------------------------- + comb : process (r, rst, clearEn, reqQValid, reqQDout, respQNotFull) is + variable v : RegType; + -- Request tuple fields (peeked from reqQ head) + variable insertOrRemove : sl; + variable insertVal : slv(T_SZ_G-1 downto 0); + variable removeIdx : slv(V_LOG_SZ_C-1 downto 0); + variable removeIdxInt : natural; + -- Combinational helpers + variable almostFull : sl; + variable almostEmpty : sl; + variable freeIdx : slv(V_LOG_SZ_C-1 downto 0); + variable freeValid : sl; + variable removeTag : sl; + variable insertIdx : slv(V_LOG_SZ_C-1 downto 0); + variable removeVal : slv(T_SZ_G-1 downto 0); + -- Mealy strobes / datapath to the FIFOs + variable vReqDeq : sl; + variable vRespEnq : sl; + variable vClrFifos : sl; + variable vRespDin : slv(FIFO_WIDTH_C-1 downto 0); + begin + v := r; + + -- Defaults for Mealy outputs (deasserted unless a branch fires) + vReqDeq := '0'; + vRespEnq := '0'; + vClrFifos := '0'; + vRespDin := (others => '0'); + + -- Decode the peeked request tuple (Tuple3 packs first element in the MSBs) + insertOrRemove := reqQDout(FIFO_WIDTH_C-1); + insertVal := reqQDout(FIFO_WIDTH_C-2 downto V_LOG_SZ_C); + removeIdx := reqQDout(V_LOG_SZ_C-1 downto 0); + removeIdxInt := to_integer(unsigned(removeIdx)); + + -- Status helpers over the current item count. + -- Explicit integer compare (itemCnt = V_SZ_G-1): equivalent to the BSV + -- all-low-bits-set trick for V_SZ_G >= 2 (itemCnt <= V_SZ_G), and still + -- correct at V_SZ_G=1 where SURF log2(1)=1 pads itemCnt to 2 bits and + -- desynchronizes the bit trick (it would detect 1 instead of 0). + almostFull := toSl(to_integer(unsigned(r.itemCnt)) = V_SZ_G-1); + if (unsigned(r.itemCnt) = 1) then + almostEmpty := '1'; + else + almostEmpty := '0'; + end if; + + -- Priority encoder: lowest-index free slot (tagVec(i) = '0'), LSB priority + freeIdx := (others => '0'); + freeValid := '0'; + for i in V_SZ_G-1 downto 0 loop + if (r.tagVec(i) = '0') then + freeIdx := toSlv(i, V_LOG_SZ_C); + freeValid := '1'; + end if; + end loop; + + -- clear() method: set the clear pulse (may be overridden by clearAll below, + -- matching the CReg port-ordering where the rule's deassert wins, OQ-FSM-03) + if (clearEn = '1') then + v.clearReg := '1'; + end if; + + ----------------------------------------------------------------------- + -- Rule priority (clearAll wins; the three normal rules are mutually + -- exclusive by tagVecStateReg). clearAll reads the registered clearReg + -- (previous-cycle pulse, OQ-FSM-03). + ----------------------------------------------------------------------- + if (r.clearReg = '1') then + -- rule clearAll + v.tagVec := (others => '0'); + vClrFifos := '1'; + v.tagVecStateReg := RECV_REQ_S; + v.emptyReg := '1'; + v.fullReg := '0'; + v.clearReg := '0'; + v.itemCnt := (others => '0'); + + elsif (r.tagVecStateReg = RECV_REQ_S) then + -- rule recvReq (peek only; reqQ is dequeued in the response state) + if (reqQValid = '1') then + if (insertOrRemove = '1') then + -- Insert: record the free slot found this cycle + v.maybeInsertIdxReg := freeValid & freeIdx; + if (r.fullReg = '0') then + v.itemCnt := slv(unsigned(r.itemCnt) + 1); + v.emptyReg := '0'; + v.fullReg := almostFull; + end if; + v.respSuccessReg := not r.fullReg; + v.tagVecStateReg := RESP_INSERT_S; + else + -- Remove: success iff the addressed slot is currently tagged + removeTag := r.tagVec(removeIdxInt); + if (removeTag = '1') then + v.itemCnt := slv(unsigned(r.itemCnt) - 1); + v.emptyReg := almostEmpty; + v.fullReg := '0'; + end if; + v.respSuccessReg := removeTag; + v.tagVecStateReg := RESP_REMOVE_S; + end if; + end if; + + elsif (r.tagVecStateReg = RESP_INSERT_S) then + -- rule genInsertResp + if (reqQValid = '1') and (respQNotFull = '1') then + vReqDeq := '1'; + insertIdx := r.maybeInsertIdxReg(V_LOG_SZ_C-1 downto 0); + if (r.respSuccessReg = '1') then + -- pragma translate_off + assert (r.maybeInsertIdxReg(V_LOG_SZ_C) = '1') + report "maybeInsertIdxReg should be valid @ TagVecSrv" + severity error; + -- pragma translate_on + v.tagVec(to_integer(unsigned(insertIdx))) := '1'; + v.dataVec(to_integer(unsigned(insertIdx))) := insertVal; + end if; + vRespEnq := '1'; + vRespDin := r.respSuccessReg & insertIdx & insertVal; + v.tagVecStateReg := RECV_REQ_S; + end if; + + else + -- rule genRemoveResp (RESP_REMOVE_S) + if (reqQValid = '1') and (respQNotFull = '1') then + vReqDeq := '1'; + removeVal := r.dataVec(removeIdxInt); + v.tagVec(removeIdxInt) := '0'; + vRespEnq := '1'; + vRespDin := r.respSuccessReg & removeIdx & removeVal; + v.tagVecStateReg := RECV_REQ_S; + end if; + end if; + + -- Synchronous reset + if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + + -- Mealy outputs to the FIFOs (combinational from this cycle's firing). + -- Left ungated under reset: fifoRst forces both FIFOs' synchronous reset, + -- which dominates any concurrent wr_en/rd_en (OQ-FSM-01 RESOLVED). + reqQRdEn <= vReqDeq; + respQWrEn <= vRespEnq; + respQDin <= vRespDin; + clrFifos <= vClrFifos; + + end process comb; + + ----------------------------------------------------------------------------- + -- Sequential process: register update + async reset option. + ----------------------------------------------------------------------------- + seq : process (clk, rst) is + begin + if (RST_ASYNC_G and rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + + ----------------------------------------------------------------------------- + -- Moore outputs (combinational reads of the registered state). + ----------------------------------------------------------------------------- + notEmpty <= not r.emptyReg; + notFull <= not r.fullReg; + getItemOut <= r.tagVec(to_integer(unsigned(getItemIdx))) & + r.dataVec(to_integer(unsigned(getItemIdx))); + tagValid <= r.tagVec; + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd b/ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd new file mode 100644 index 0000000000..12916c9191 --- /dev/null +++ b/ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd @@ -0,0 +1,359 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Self-checking testbench for TagVecSrv (out/04-vhdl/TagVecSrv.vhd). +-- +-- Configuration under test: V_SZ_G = 4, T_SZ_G = 32 (the mkMetaDataQPs / +-- HandlerPD instantiation). Directed scenarios: +-- 1. Reset state : empty, not full. +-- 2. Inserts 0..3 : sequential free-slot allocation (LSB priority). +-- 3. Fill to full : notFull deasserts after the 4th insert. +-- 4. Insert while full : response success = 0, count unchanged. +-- 5. Remove : success = 1, slot freed, notFull re-asserts. +-- 6. Remove empty slot : success = 0. +-- 7. Free-slot reuse : next insert reuses the lowest freed index. +-- 8. getItem lookup : valid + data for tagged / untagged slots. +-- 9. clear() + recovery : both FIFOs flushed, tags reset, then re-usable. +-- +-- Drives the request/response valid-ready handshakes (srvPort) and the +-- getItem / notEmpty / notFull / clear method ports. Inputs are driven and +-- outputs sampled on the FALLING edge so combinational FWFT outputs are fully +-- settled; the DUT and SURF FIFOs latch on the rising edge. +-- +-- NOTE: TagVecSrv instantiates surf.Fifo, so the SURF library must be +-- compiled to elaborate/run this testbench (see the run notes at end of file). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity TagVecSrv_tb is +end entity TagVecSrv_tb; + +architecture sim of TagVecSrv_tb is + + -- DUT configuration + constant T_SZ_C : positive := 32; + constant V_SZ_C : positive := 4; + constant V_LOG_SZ_C : integer := log2(V_SZ_C); -- 2 + constant FIFO_WIDTH_C : integer := 1 + T_SZ_C + V_LOG_SZ_C; -- 35 + + constant CLK_PERIOD_C : time := 10 ns; + constant SETTLE_C : time := 1 ns; -- delta-settle delay for comb reads + + -- Clock / reset + signal clk : sl := '0'; + signal rst : sl := '1'; + signal simDone : boolean := false; + + -- Request side (TB -> DUT) + signal reqValid : sl := '0'; + signal reqData : slv(FIFO_WIDTH_C-1 downto 0) := (others => '0'); + signal reqReady : sl; + + -- Response side (DUT -> TB) + signal respValid : sl; + signal respData : slv(FIFO_WIDTH_C-1 downto 0); + signal respReady : sl := '0'; + + -- Method ports + signal getItemIdx : slv(V_LOG_SZ_C-1 downto 0) := (others => '0'); + signal getItemOut : slv(T_SZ_C downto 0); + signal notEmpty : sl; + signal notFull : sl; + signal clearEn : sl := '0'; + + -- Convenience constants + constant INSERT_C : sl := '1'; + constant REMOVE_C : sl := '0'; + +begin + + ----------------------------------------------------------------------------- + -- Clock / reset generation + ----------------------------------------------------------------------------- + clk <= not clk after CLK_PERIOD_C/2 when not simDone else '0'; + + rst_proc : process is + begin + rst <= '1'; + wait for 4*CLK_PERIOD_C; + wait until falling_edge(clk); + rst <= '0'; + wait; + end process rst_proc; + + ----------------------------------------------------------------------------- + -- Device under test + ----------------------------------------------------------------------------- + U_DUT : entity surf.TagVecSrv + generic map ( + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + MEMORY_TYPE_G => "distributed", + V_SZ_G => V_SZ_C, + T_SZ_G => T_SZ_C) + port map ( + clk => clk, + rst => rst, + reqValid => reqValid, + reqData => reqData, + reqReady => reqReady, + respValid => respValid, + respData => respData, + respReady => respReady, + getItemIdx => getItemIdx, + getItemOut => getItemOut, + notEmpty => notEmpty, + notFull => notFull, + clearEn => clearEn); + + ----------------------------------------------------------------------------- + -- Stimulus + checking + ----------------------------------------------------------------------------- + stim : process is + variable errCnt : natural := 0; + + -- advance one clock (sample/drive on falling edge -> settled values) + procedure step is + begin + wait until falling_edge(clk); + end procedure step; + + procedure check(cond : boolean; msg : string) is + begin + if not cond then + report "FAIL: " & msg severity error; + errCnt := errCnt + 1; + else + report "pass: " & msg severity note; + end if; + end procedure check; + + -- Enqueue one request word into reqQ (held for exactly one rising edge) + procedure enqReq(insOrRem : sl; + iVal : slv(T_SZ_C-1 downto 0); + rIdx : slv(V_LOG_SZ_C-1 downto 0)) is + begin + -- wait for space (reqReady = reqQ.not_full) + while reqReady /= '1' loop + step; + end loop; + reqValid <= '1'; + reqData <= insOrRem & iVal & rIdx; + step; + reqValid <= '0'; + reqData <= (others => '0'); + end procedure enqReq; + + -- Pop one response from respQ + procedure popResp(success : out sl; + idx : out slv(V_LOG_SZ_C-1 downto 0); + val : out slv(T_SZ_C-1 downto 0)) is + begin + respReady <= '1'; + -- wait until the response is available (FWFT valid) + while respValid /= '1' loop + step; + end loop; + -- capture head (registered/FWFT data, valid this cycle) + success := respData(FIFO_WIDTH_C-1); + idx := respData(FIFO_WIDTH_C-2 downto T_SZ_C); + val := respData(T_SZ_C-1 downto 0); + step; -- rising edge pops the entry + respReady <= '0'; + end procedure popResp; + + -- Issue an insert and check the response + procedure doInsert(iVal : slv(T_SZ_C-1 downto 0); + expSucc : sl; + expIdx : slv(V_LOG_SZ_C-1 downto 0); + chkIdx : boolean; + tag : string) is + variable s : sl; + variable i : slv(V_LOG_SZ_C-1 downto 0); + variable v : slv(T_SZ_C-1 downto 0); + begin + enqReq(INSERT_C, iVal, (others => '0')); + popResp(s, i, v); + check(s = expSucc, tag & " success"); + if expSucc = '1' then + check(v = iVal, tag & " value echoed"); + if chkIdx then + check(i = expIdx, tag & " index"); + end if; + end if; + end procedure doInsert; + + -- Issue a remove and check the response + procedure doRemove(rIdx : slv(V_LOG_SZ_C-1 downto 0); + expSucc : sl; + expVal : slv(T_SZ_C-1 downto 0); + chkVal : boolean; + tag : string) is + variable s : sl; + variable i : slv(V_LOG_SZ_C-1 downto 0); + variable v : slv(T_SZ_C-1 downto 0); + begin + enqReq(REMOVE_C, (others => '0'), rIdx); + popResp(s, i, v); + check(s = expSucc, tag & " success"); + if expSucc = '1' then + check(i = rIdx, tag & " index echoed"); + if chkVal then + check(v = expVal, tag & " value"); + end if; + end if; + end procedure doRemove; + + procedure checkItem(idx : slv(V_LOG_SZ_C-1 downto 0); + expV : sl; + expData : slv(T_SZ_C-1 downto 0); + chkData : boolean; + tag : string) is + begin + getItemIdx <= idx; + wait for SETTLE_C; + check(getItemOut(T_SZ_C) = expV, tag & " valid"); + if expV = '1' and chkData then + check(getItemOut(T_SZ_C-1 downto 0) = expData, tag & " data"); + end if; + end procedure checkItem; + + -- Slot data used through the test + constant A_C : slv(T_SZ_C-1 downto 0) := x"AAAA0001"; + constant B_C : slv(T_SZ_C-1 downto 0) := x"BBBB0002"; + constant C_C : slv(T_SZ_C-1 downto 0) := x"CCCC0003"; + constant D_C : slv(T_SZ_C-1 downto 0) := x"DDDD0004"; + constant E_C : slv(T_SZ_C-1 downto 0) := x"EEEE0005"; + constant F_C : slv(T_SZ_C-1 downto 0) := x"12345678"; + constant G_C : slv(T_SZ_C-1 downto 0) := x"0BADF00D"; + + constant IDX0_C : slv(V_LOG_SZ_C-1 downto 0) := "00"; + constant IDX1_C : slv(V_LOG_SZ_C-1 downto 0) := "01"; + constant IDX2_C : slv(V_LOG_SZ_C-1 downto 0) := "10"; + constant IDX3_C : slv(V_LOG_SZ_C-1 downto 0) := "11"; + + variable s : sl; + variable i : slv(V_LOG_SZ_C-1 downto 0); + variable v : slv(T_SZ_C-1 downto 0); + begin + ------------------------------------------------------------------------- + -- 1. Reset state + ------------------------------------------------------------------------- + wait until rst = '0'; + step; + wait for SETTLE_C; + check(notEmpty = '0', "T1 reset: notEmpty = 0 (empty)"); + check(notFull = '1', "T1 reset: notFull = 1"); + checkItem(IDX0_C, '0', (others => '0'), false, "T1 getItem(0)"); + + ------------------------------------------------------------------------- + -- 2/3. Sequential inserts -> indices 0,1,2,3 (LSB-priority free slot) + ------------------------------------------------------------------------- + doInsert(A_C, '1', IDX0_C, true, "T2 insert A"); + wait for SETTLE_C; + check(notEmpty = '1', "T2 after A: notEmpty = 1"); + check(notFull = '1', "T2 after A: notFull = 1"); + checkItem(IDX0_C, '1', A_C, true, "T2 getItem(0)=A"); + checkItem(IDX1_C, '0', (others => '0'), false, "T2 getItem(1) invalid"); + + doInsert(B_C, '1', IDX1_C, true, "T3 insert B"); + doInsert(C_C, '1', IDX2_C, true, "T3 insert C"); + doInsert(D_C, '1', IDX3_C, true, "T3 insert D"); + wait for SETTLE_C; + check(notFull = '0', "T3 after 4 inserts: notFull = 0 (full)"); + check(notEmpty = '1', "T3 after 4 inserts: notEmpty = 1"); + checkItem(IDX3_C, '1', D_C, true, "T3 getItem(3)=D"); + + ------------------------------------------------------------------------- + -- 4. Insert while full -> success = 0, count unchanged + ------------------------------------------------------------------------- + doInsert(E_C, '0', IDX0_C, false, "T4 insert while full"); + wait for SETTLE_C; + check(notFull = '0', "T4 still full after rejected insert"); + + ------------------------------------------------------------------------- + -- 5. Remove idx 1 -> success, slot freed + ------------------------------------------------------------------------- + doRemove(IDX1_C, '1', B_C, true, "T5 remove idx1"); + wait for SETTLE_C; + check(notFull = '1', "T5 after remove: notFull = 1"); + checkItem(IDX1_C, '0', (others => '0'), false, "T5 getItem(1) invalid"); + checkItem(IDX0_C, '1', A_C, true, "T5 getItem(0) still A"); + + ------------------------------------------------------------------------- + -- 6. Remove an already-empty slot -> success = 0 + ------------------------------------------------------------------------- + doRemove(IDX1_C, '0', (others => '0'), false, "T6 remove empty idx1"); + + ------------------------------------------------------------------------- + -- 7. Free-slot reuse -> next insert takes the lowest free index (1) + ------------------------------------------------------------------------- + doInsert(F_C, '1', IDX1_C, true, "T7 insert F reuses idx1"); + wait for SETTLE_C; + checkItem(IDX1_C, '1', F_C, true, "T7 getItem(1)=F"); + check(notFull = '0', "T7 full again after reuse"); + + ------------------------------------------------------------------------- + -- 8. clear() -> flush both FIFOs, reset all tags, then recover + ------------------------------------------------------------------------- + clearEn <= '1'; + step; + clearEn <= '0'; + -- allow clearAll + FIFO synchronous flush to settle + for k in 0 to 4 loop + step; + end loop; + wait for SETTLE_C; + check(notEmpty = '0', "T8 after clear: notEmpty = 0"); + check(notFull = '1', "T8 after clear: notFull = 1"); + checkItem(IDX0_C, '0', (others => '0'), false, "T8 getItem(0) invalid"); + checkItem(IDX3_C, '0', (others => '0'), false, "T8 getItem(3) invalid"); + + -- 9. Recovery: insert after clear -> idx 0, success + doInsert(G_C, '1', IDX0_C, true, "T9 insert after clear"); + wait for SETTLE_C; + check(notEmpty = '1', "T9 after recovery insert: notEmpty = 1"); + checkItem(IDX0_C, '1', G_C, true, "T9 getItem(0)=G"); + + ------------------------------------------------------------------------- + -- Final report + ------------------------------------------------------------------------- + step; + if errCnt = 0 then + report "==== TagVecSrv_tb: ALL CHECKS PASSED ====" severity note; + else + report "==== TagVecSrv_tb: " & integer'image(errCnt) & + " CHECK(S) FAILED ====" severity failure; + end if; + + simDone <= true; + wait; + end process stim; + +end architecture sim; + +------------------------------------------------------------------------------- +-- Run notes (GHDL example; requires the SURF library compiled into lib 'surf'): +-- # analyze surf sources (StdRtlPkg, Fifo + its FifoSync/FifoAsync deps, ...) +-- ghdl -a --std=08 --work=surf +-- # analyze the DUT and this testbench +-- ghdl -a --std=08 --work=surf out/04-vhdl/TagVecSrv.vhd +-- ghdl -a --std=08 out/04-vhdl/TagVecSrv_tb.vhd +-- ghdl --elab-run --std=08 TagVecSrv_tb --assert-level=error +-- A failing check stops the run with severity failure; otherwise the final +-- "ALL CHECKS PASSED" note is printed. +------------------------------------------------------------------------------- diff --git a/ethernet/RoCEv2/rtl/TransportLayer.vhd b/ethernet/RoCEv2/rtl/TransportLayer.vhd new file mode 100644 index 0000000000..c51853332c --- /dev/null +++ b/ethernet/RoCEv2/rtl/TransportLayer.vhd @@ -0,0 +1,1024 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Pure STRUCTURAL top-level of the blue-rdma transport layer. mkTransportLayer +-- owns zero state registers and zero behavioural rules (mapping.json +-- rule_count = 0): everything it does is elaboration — instantiate children, +-- wire them, and re-export faces. Accordingly this file contains NO RegType / +-- two-process FSM; only instances plus the combinational glue mandated by the +-- FSM spec (transfer strobes, the QP-status mux, and constant ties). +-- +-- Child entity instances (all separately emitted and Stage-5 verified): +-- U_MetaDataPDs : work.MetaDataPDs (mkMetaDataPDs) +-- U_PermCheckSrv : work.PermCheckSrv (mkPermCheckSrv) +-- U_MetaDataQPs : work.MetaDataQPs (mkMetaDataQPs) +-- U_MetaDataSrv : work.MetaDataSrv (mkMetaDataSrv) +-- U_Dispatcher : work.WorkReqAndRecvReqDispatcher (mkWorkReqAndRecvReqDispatcher) +-- U_ExtractHeader : work.ExtractHeaderFromRdmaPktPipeOut (mkExtractHeaderFromRdmaPktPipeOut) +-- U_PktBuf : work.InputRdmaPktBufAndHeaderValidation (mkInputRdmaPktBufAndHeaderValidation) +-- GEN_QP(i).U_Qp : work.Qp x MAX_QP_G (mkQP, HOISTED from MetaDataQPs +-- per RESOLVED OQ-FSM-MDQPS-01: the BSV per-QP wiring +-- loop indexes getQueuePairByIndexQP with a +-- compile-time constant -> for..generate here) +-- U_PermCheckCltArb : work.PermCheckCltArbiter (mkPermCheckCltArbiter) +-- U_DmaReadCltArb : work.DmaReadCltArbiter (mkDmaReadCltArbiter) +-- U_DmaWriteCltArb : work.DmaWriteCltArbiter (mkDmaWriteCltArbiter) +-- U_DataStreamArb : work.PipeOutArbiter (PORT_COUNT_G=2*MAX_QP_G, 290 b) +-- U_RecvWcArb : work.PipeOutArbiter (PORT_COUNT_G=MAX_QP_G, 222 b) +-- U_SendWcArb : work.PipeOutArbiter (PORT_COUNT_G=MAX_QP_G, 222 b) +-- +-- SURF components instantiated DIRECTLY by this entity (BSV mkFIFOF -> sync +-- FWFT surf.Fifo, 16 deep, project convention OQ-EMIT-PCS-02): +-- U_InputDataStreamQ : surf.Fifo (290 b) <- inputDataStreamQ (TransportLayer.bsv:82) +-- U_InputWorkReqQ : surf.Fifo (601 b) <- inputWorkReqQ (TransportLayer.bsv:85) +-- U_InputRecvReqQ : surf.Fifo (216 b) <- inputRecvReqQ (TransportLayer.bsv:86) +-- +-- Arbiter slot convention (TransportLayer.bsv:135-144): even slot k = 2i is +-- QP i's RQ/resp face, odd slot k = 2i+1 is QP i's SQ/req face. +-- +-- QP-status mux (glue G5, replaces the BSV dynamic getQueuePairByQPN, +-- RESOLVED OQ-FSM-MDQPS-01 sec.2.3): statusIdx = getIndexQP(U_PktBuf.getQpQpn) +-- = truncateLSB, i.e. qpn(23 downto 24-log2(MAX_QP_G)); U_PktBuf's sq* and +-- rq* status inputs are fed from the SAME per-QP comm bundle (only TypeQP +-- differs) because Qp exports ONE shared comm* group for SQ+RQ +-- (OQ-EMIT-QP-01) — identical to the BSV, where statusSQ.comm and +-- statusRQ.comm read the same mkCntrlQP registers. +-- +-- CNP is unsupported upstream (BSV TODO, TransportLayer.bsv:146-151): +-- U_PktBuf.cnpRdEn is tied '0' and a translate_off assertion reproduces the +-- BSV genEmptyPipeOutRule simulation check. +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity TransportLayer is + generic ( + TPD_G : time := 1 ns; + MAX_QP_G : positive := 4; -- MAX_QP (Settings.bsv:14); any power of 2, >= 2 + -- Pruning generics (all true = full engine, identical to the verified + -- netlist; at least one of EN_TX_G/EN_RX_G must be true): + -- EN_TX_G=false : no requester — SQ subtree, workReq input path and + -- SQ work-completion arbiter are not generated + -- (workReqInReady tied '0'). + -- EN_RX_G=false : no responder — RQ subtree, recvReq input path and + -- RQ work-completion arbiter are not generated + -- (recvReqInReady tied '0'); incoming request packets + -- are dropped in U_PktBuf. ACK/NAK reception (SQ + -- side) is NOT affected. + -- EN_READ_G=false : no RDMA READ/atomic — requester read-response + -- landing and responder read/atomic serving pruned. + -- Software contract: never post READ/atomic WRs. + EN_TX_G : boolean := true; + EN_RX_G : boolean := true; + EN_READ_G : boolean := true); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + + -- rdmaDataStreamInput : Put#(DataStream 290b) + dataStreamInValid : in sl; + dataStreamInData : in slv(289 downto 0); + dataStreamInReady : out sl; + + -- workReqInput : Put#(WorkReq 601b) + workReqInValid : in sl; + workReqInData : in slv(600 downto 0); + workReqInReady : out sl; + + -- recvReqInput : Put#(RecvReq 216b) + recvReqInValid : in sl; + recvReqInData : in slv(215 downto 0); + recvReqInReady : out sl; + + -- rdmaDataStreamPipeOut : DataStreamPipeOut (290b) + dataStreamOutValid : out sl; + dataStreamOutData : out slv(289 downto 0); + dataStreamOutRdEn : in sl; + + -- workCompPipeOutRQ / workCompPipeOutSQ : PipeOut#(WorkComp 222b) + workCompRqValid : out sl; + workCompRqData : out slv(221 downto 0); + workCompRqRdEn : in sl; + workCompSqValid : out sl; + workCompSqData : out slv(221 downto 0); + workCompSqRdEn : in sl; + + -- srvPortMetaData : Server#(MetaDataReq 303b, MetaDataResp 276b) + -- (re-export of U_MetaDataSrv.srv*) + mdSrvReqValid : in sl; + mdSrvReqData : in slv(302 downto 0); + mdSrvReqReady : out sl; + mdSrvRespValid : out sl; + mdSrvRespData : out slv(275 downto 0); + mdSrvRespReady : in sl; + + -- dmaReadClt : Client#(DmaReadReq 176b, DmaReadResp 383b) + -- (re-export of U_DmaReadCltArb.out*) + dmaReadReqValid : out sl; + dmaReadReqData : out slv(175 downto 0); + dmaReadReqRd : in sl; + dmaReadRespValid : in sl; + dmaReadRespData : in slv(382 downto 0); + dmaReadRespReady : out sl; + + -- dmaWriteClt : Client#(DmaWriteReq 419b, DmaWriteResp 53b) + -- (re-export of U_DmaWriteCltArb.out*) + dmaWriteReqValid : out sl; + dmaWriteReqData : out slv(418 downto 0); + dmaWriteReqRd : in sl; + dmaWriteRespValid : in sl; + dmaWriteRespData : in slv(52 downto 0); + dmaWriteRespReady : out sl); +end entity TransportLayer; + +architecture rtl of TransportLayer is + + -- Payload widths, traced from the emitted child entities (FSM spec table) + constant DATA_STREAM_W_C : positive := 290; -- DataStream + constant WORK_REQ_W_C : positive := 601; -- WorkReq + constant RECV_REQ_W_C : positive := 216; -- RecvReq + constant WORK_COMP_W_C : positive := 222; -- WorkComp + constant PKT_META_W_C : positive := 649; -- RdmaPktMetaData + constant RESP_QP_W_C : positive := 274; -- RespQP + constant PERM_REQ_W_C : positive := 267; -- PermCheckReq + constant DMA_RD_REQ_W_C : positive := 176; -- DmaReadReq + constant DMA_RD_RESP_W_C : positive := 383; -- DmaReadResp + constant DMA_WR_REQ_W_C : positive := 419; -- DmaWriteReq + constant DMA_WR_RESP_W_C : positive := 53; -- DmaWriteResp + + -- MAX_PD (Settings.bsv:20); BSV proviso MAX_QP >= MAX_PD (MetaData.bsv:679-682) + -- forces MAX_PD = 1 at MAX_QP_G = 1 + constant MAX_PD_C : positive := ite(MAX_QP_G < 2, 1, 2); + constant QP_IDX_WIDTH_C : positive := log2(MAX_QP_G); -- IndexQP width + + -- isWorkCompFinished = constant True in BSV (TransportLayer.bsv:164-166) + constant WC_FINISHED_C : slv(MAX_QP_G-1 downto 0) := (others => '1'); + -- CNP unsupported: never dequeue (TransportLayer.bsv:146) + constant CNP_TIE_C : slv(MAX_QP_G-1 downto 0) := (others => '0'); + + -- G1: input FIFO faces (surf.Fifo x3) + signal dataStreamQWrEn : sl; + signal dataStreamQNotFull : sl; + signal dataStreamQValid : sl; + signal dataStreamQDout : slv(DATA_STREAM_W_C-1 downto 0); + signal dataStreamQRdEn : sl; + signal workReqQWrEn : sl; + signal workReqQNotFull : sl; + signal workReqQValid : sl; + signal workReqQDout : slv(WORK_REQ_W_C-1 downto 0); + signal workReqQRdEn : sl; + signal recvReqQWrEn : sl; + signal recvReqQNotFull : sl; + signal recvReqQValid : sl; + signal recvReqQDout : slv(RECV_REQ_W_C-1 downto 0); + signal recvReqQRdEn : sl; + + -- W2: dispatcher per-QP read faces -> Qp Put faces (G2 strobes) + signal dispWorkReqOutValid : slv(MAX_QP_G-1 downto 0); + signal dispWorkReqOutData : slv(MAX_QP_G*WORK_REQ_W_C-1 downto 0); + signal dispRecvReqOutValid : slv(MAX_QP_G-1 downto 0); + signal dispRecvReqOutData : slv(MAX_QP_G*RECV_REQ_W_C-1 downto 0); + signal workReqXfer : slv(MAX_QP_G-1 downto 0); + signal recvReqXfer : slv(MAX_QP_G-1 downto 0); + signal qpWorkReqInReady : slv(MAX_QP_G-1 downto 0); + signal qpRecvReqInReady : slv(MAX_QP_G-1 downto 0); + + -- W3: header extraction -> packet buffer (1:1) + signal extHeaderDataStreamValid : sl; + signal extHeaderDataStreamData : slv(DATA_STREAM_W_C-1 downto 0); + signal extHeaderDataStreamRdEn : sl; + signal extHeaderMetaDataValid : sl; + signal extHeaderMetaDataData : slv(16 downto 0); + signal extHeaderMetaDataRdEn : sl; + signal extPayloadValid : sl; + signal extPayloadData : slv(DATA_STREAM_W_C-1 downto 0); + signal extPayloadRdEn : sl; + + -- W4: packet buffer per-QP pipes -> Qp pkt Put faces (G2 strobes) + signal pktBufReqPktMetaValid : slv(MAX_QP_G-1 downto 0); + signal pktBufReqPktMetaDout : slv(MAX_QP_G*PKT_META_W_C-1 downto 0); + signal pktBufReqPayloadValid : slv(MAX_QP_G-1 downto 0); + signal pktBufReqPayloadDout : slv(MAX_QP_G*DATA_STREAM_W_C-1 downto 0); + signal pktBufRespPktMetaValid : slv(MAX_QP_G-1 downto 0); + signal pktBufRespPktMetaDout : slv(MAX_QP_G*PKT_META_W_C-1 downto 0); + signal pktBufRespPayloadValid : slv(MAX_QP_G-1 downto 0); + signal pktBufRespPayloadDout : slv(MAX_QP_G*DATA_STREAM_W_C-1 downto 0); + signal reqPktMetaXfer : slv(MAX_QP_G-1 downto 0); + signal reqPktPayloadXfer : slv(MAX_QP_G-1 downto 0); + signal respPktMetaXfer : slv(MAX_QP_G-1 downto 0); + signal respPktPayloadXfer : slv(MAX_QP_G-1 downto 0); + signal qpReqPktMetaReady : slv(MAX_QP_G-1 downto 0); + signal qpReqPktPayloadReady : slv(MAX_QP_G-1 downto 0); + signal qpRespPktMetaReady : slv(MAX_QP_G-1 downto 0); + signal qpRespPktPayloadReady : slv(MAX_QP_G-1 downto 0); + signal cnpValid : slv(MAX_QP_G-1 downto 0); + + -- W5: RDMA DataStream output arbiter (even slot 2i = resp/RQ, odd = req/SQ) + signal dataStreamArbInValid : slv(2*MAX_QP_G-1 downto 0); + signal dataStreamArbInDout : slv(2*MAX_QP_G*DATA_STREAM_W_C-1 downto 0); + signal dataStreamArbInFinished : slv(2*MAX_QP_G-1 downto 0); + signal dataStreamArbInRd : slv(2*MAX_QP_G-1 downto 0); + + -- W6: work-completion arbiters + signal recvWcArbInValid : slv(MAX_QP_G-1 downto 0); + signal recvWcArbInDout : slv(MAX_QP_G*WORK_COMP_W_C-1 downto 0); + signal recvWcArbInRd : slv(MAX_QP_G-1 downto 0); + signal sendWcArbInValid : slv(MAX_QP_G-1 downto 0); + signal sendWcArbInDout : slv(MAX_QP_G*WORK_COMP_W_C-1 downto 0); + signal sendWcArbInRd : slv(MAX_QP_G-1 downto 0); + + -- W7: MetaData cluster (MetaDataSrv <-> MetaDataPDs / MetaDataQPs / PermCheckSrv) + signal mdSrvPdReqValid : sl; + signal mdSrvPdReqData : slv(63 downto 0); -- ReqPD + signal mdSrvPdReqReady : sl; + signal mdSrvPdRespValid : sl; + signal mdSrvPdRespData : slv(63 downto 0); -- RespPD + signal mdSrvPdRespReady : sl; + signal mdSrvIsValidPdHandler : slv(31 downto 0); + signal mdSrvIsValidPd : sl; + signal mrSrvPdHandler : slv(31 downto 0); + signal mrSrvPdValid : sl; + signal mrSrvReqValid : sl; + signal mrSrvReqData : slv(251 downto 0); -- ReqMR + signal mrSrvReqReady : sl; + signal mrSrvRespValid : sl; + signal mrSrvRespData : slv(250 downto 0); -- RespMR + signal mrSrvRespReady : sl; + -- mdSrvQp* naming is MANDATED (RESOLVED OQ-FSM-MDSRV-01 sec.5) to avoid + -- colliding with MetaDataQPs' own per-QP qpReq*/qpResp* bundle (W8 below). + signal mdSrvQpReqValid : sl; + signal mdSrvQpReqData : slv(300 downto 0); -- ReqQP + signal mdSrvQpReqReady : sl; + signal mdSrvQpRespValid : sl; + signal mdSrvQpRespData : slv(273 downto 0); -- RespQP + signal mdSrvQpRespReady : sl; + signal mrLkupPdHandler : slv(31 downto 0); + signal mrLkupKey : slv(31 downto 0); + signal mrLkupByLocal : sl; + signal mrLkupReqValid : sl; + signal mrLkupValid : sl; + signal mrLkupData : slv(185 downto 0); -- MemRegion + + -- W8: MetaDataQPs per-QP srvPortQP client bundle -> GEN_QP(i).U_Qp.srvPort* + signal qpCtrlReqValid : slv(MAX_QP_G-1 downto 0); -- one-hot request put + signal qpCtrlReqData : slv(300 downto 0); -- shared ReqQP payload + signal qpCtrlReqReady : slv(MAX_QP_G-1 downto 0); + signal qpCtrlRespValid : slv(MAX_QP_G-1 downto 0); + signal qpCtrlRespData : slv(MAX_QP_G*RESP_QP_W_C-1 downto 0); + signal qpCtrlRespReady : slv(MAX_QP_G-1 downto 0); + + -- W9: getPD(qpn) combinational lookup (U_PktBuf -> U_MetaDataQPs) + signal pktBufGetPdQpn : slv(23 downto 0); + signal pktBufGetPdMaybeValid : sl; + signal pktBufGetPdHandler : slv(31 downto 0); + + -- W10: PermCheck arbitration (2*MAX_QP_G client slots + downstream server) + signal permSrvReqValid : slv(2*MAX_QP_G-1 downto 0); + signal permSrvReqData : slv(2*MAX_QP_G*PERM_REQ_W_C-1 downto 0); + signal permSrvReqGet : slv(2*MAX_QP_G-1 downto 0); + signal permSrvRespValid : slv(2*MAX_QP_G-1 downto 0); + signal permSrvRespData : slv(2*MAX_QP_G-1 downto 0); -- PERM_RESP_WIDTH_G = 1 + signal permSrvRespReady : slv(2*MAX_QP_G-1 downto 0); + signal permCltReqValid : sl; + signal permCltReqData : slv(PERM_REQ_W_C-1 downto 0); + signal permCltReqRd : sl; + signal permCltRespValid : sl; + signal permCltRespData : slv(0 downto 0); + signal permCltRespReady : sl; + signal permReqPutReady : sl; + signal permRespGetValid : sl; + signal permRespGetData : sl; + signal permRespGetRdEn : sl; + + -- W11: DMA read/write arbitration (2*MAX_QP_G client slots each) + signal dmaRdCltReqValid : slv(2*MAX_QP_G-1 downto 0); + signal dmaRdCltReqData : slv(2*MAX_QP_G*DMA_RD_REQ_W_C-1 downto 0); + signal dmaRdCltReqGet : slv(2*MAX_QP_G-1 downto 0); + signal dmaRdCltRespValid : slv(2*MAX_QP_G-1 downto 0); + signal dmaRdCltRespData : slv(2*MAX_QP_G*DMA_RD_RESP_W_C-1 downto 0); + signal dmaRdCltRespReady : slv(2*MAX_QP_G-1 downto 0); + signal dmaWrCltReqValid : slv(2*MAX_QP_G-1 downto 0); + signal dmaWrCltReqData : slv(2*MAX_QP_G*DMA_WR_REQ_W_C-1 downto 0); + signal dmaWrCltReqGet : slv(2*MAX_QP_G-1 downto 0); + signal dmaWrCltRespValid : slv(2*MAX_QP_G-1 downto 0); + signal dmaWrCltRespData : slv(2*MAX_QP_G*DMA_WR_RESP_W_C-1 downto 0); + signal dmaWrCltRespReady : slv(2*MAX_QP_G-1 downto 0); + + -- W12 / G5: per-QP status bundles + the getQueuePairByQPN replacement mux + signal qpStatusTypeSq : Slv4Array(MAX_QP_G-1 downto 0); + signal qpStatusTypeRq : Slv4Array(MAX_QP_G-1 downto 0); + signal qpCommIsErr : slv(MAX_QP_G-1 downto 0); + signal qpCommIsRts : slv(MAX_QP_G-1 downto 0); + signal qpCommIsNonErr : slv(MAX_QP_G-1 downto 0); + signal qpCommQkey : Slv32Array(MAX_QP_G-1 downto 0); + signal qpCommPmtu : Slv3Array(MAX_QP_G-1 downto 0); + signal pktBufGetQpQpn : slv(23 downto 0); + signal statusIdx : natural range 0 to MAX_QP_G-1; + signal statusTypeSqMux : slv(3 downto 0); + signal statusTypeRqMux : slv(3 downto 0); + signal statusIsErrMux : sl; + signal statusIsRtsMux : sl; + signal statusIsNonErrMux : sl; + signal statusQkeyMux : slv(31 downto 0); + signal statusPmtuMux : slv(2 downto 0); + +begin + + -- Static generic legality check (kept outside the translate pragmas: it + -- must also fail synthesis elaboration on an all-disabled configuration). + assert (EN_TX_G or EN_RX_G) + report "TransportLayer: at least one of EN_TX_G / EN_RX_G must be true" + severity failure; + + -- pragma translate_off + assert isPowerOf2(MAX_QP_G) + report "MAX_QP_G must be a power of 2, >= 1 @ TransportLayer" + severity failure; + assert (MAX_QP_G mod MAX_PD_C = 0) + report "MAX_QP_G must be divisible by MAX_PD_G (BSV proviso, MetaData.bsv) @ TransportLayer" + severity failure; + -- pragma translate_on + + ----------------------------------------------------------------------------- + -- G1 — Input FIFOs (BSV inputDataStreamQ / inputWorkReqQ / inputRecvReqQ, + -- TransportLayer.bsv:82-86). Put face: ready = not_full, wr_en = valid&ready. + ----------------------------------------------------------------------------- + dataStreamInReady <= dataStreamQNotFull; + dataStreamQWrEn <= dataStreamInValid and dataStreamQNotFull; + + U_InputDataStreamQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => DATA_STREAM_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => dataStreamQWrEn, + din => dataStreamInData, + wr_data_count => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + not_full => dataStreamQNotFull, + rd_clk => clk, + rd_en => dataStreamQRdEn, + dout => dataStreamQDout, + rd_data_count => open, + valid => dataStreamQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open); + + -- workReq input path: pruned when EN_TX_G=false (input refused). + GEN_NO_WORKREQ_Q : if not EN_TX_G generate + workReqInReady <= '0'; + workReqQValid <= '0'; + workReqQDout <= (others => '0'); + end generate GEN_NO_WORKREQ_Q; + + GEN_WORKREQ_Q : if EN_TX_G generate + workReqInReady <= workReqQNotFull; + workReqQWrEn <= workReqInValid and workReqQNotFull; + + U_InputWorkReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => WORK_REQ_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => workReqQWrEn, + din => workReqInData, + wr_data_count => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + not_full => workReqQNotFull, + rd_clk => clk, + rd_en => workReqQRdEn, + dout => workReqQDout, + rd_data_count => open, + valid => workReqQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open); + end generate GEN_WORKREQ_Q; + + -- recvReq input path: pruned when EN_RX_G=false (input refused). + GEN_NO_RECVREQ_Q : if not EN_RX_G generate + recvReqInReady <= '0'; + recvReqQValid <= '0'; + recvReqQDout <= (others => '0'); + end generate GEN_NO_RECVREQ_Q; + + GEN_RECVREQ_Q : if EN_RX_G generate + recvReqInReady <= recvReqQNotFull; + recvReqQWrEn <= recvReqInValid and recvReqQNotFull; + + U_InputRecvReqQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => RECV_REQ_W_C, + ADDR_WIDTH_G => 4) + port map ( + rst => rst, + wr_clk => clk, + wr_en => recvReqQWrEn, + din => recvReqInData, + wr_data_count => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + full => open, + not_full => recvReqQNotFull, + rd_clk => clk, + rd_en => recvReqQRdEn, + dout => recvReqQDout, + rd_data_count => open, + valid => recvReqQValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open); + end generate GEN_RECVREQ_Q; + + ----------------------------------------------------------------------------- + -- W1/W2 — Work-request / receive-request dispatcher (TransportLayer.bsv:93-94) + -- G2 strobes: WrEn/Valid to the Qp Put face AND RdEn back to the source are + -- BOTH valid&ready (NOT valid alone — would overflow under back-pressure). + ----------------------------------------------------------------------------- + workReqXfer <= dispWorkReqOutValid and qpWorkReqInReady; + recvReqXfer <= dispRecvReqOutValid and qpRecvReqInReady; + + U_Dispatcher : entity surf.WorkReqAndRecvReqDispatcher + generic map ( + TPD_G => TPD_G, + MAX_QP_G => MAX_QP_G, + EN_TX_G => EN_TX_G, + EN_RX_G => EN_RX_G) + port map ( + clk => clk, + rst => rst, + workReqValid_i => workReqQValid, + workReqData_i => workReqQDout, + workReqDeq_o => workReqQRdEn, + recvReqValid_i => recvReqQValid, + recvReqData_i => recvReqQDout, + recvReqDeq_o => recvReqQRdEn, + workReqOutValid_o => dispWorkReqOutValid, + workReqOutData_o => dispWorkReqOutData, + workReqOutRdEn_i => workReqXfer, + recvReqOutValid_o => dispRecvReqOutValid, + recvReqOutData_o => dispRecvReqOutData, + recvReqOutRdEn_i => recvReqXfer); + + ----------------------------------------------------------------------------- + -- W3 — Header extraction (TransportLayer.bsv:100-105); all three output + -- pipes feed U_PktBuf 1:1 (same names). + ----------------------------------------------------------------------------- + U_ExtractHeader : entity surf.ExtractHeaderFromRdmaPktPipeOut + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + rdmaPktPipeInValid => dataStreamQValid, + rdmaPktPipeInData => dataStreamQDout, + rdmaPktPipeInRdEn => dataStreamQRdEn, + headerDataStreamValid => extHeaderDataStreamValid, + headerDataStreamData => extHeaderDataStreamData, + headerDataStreamRdEn => extHeaderDataStreamRdEn, + headerMetaDataValid => extHeaderMetaDataValid, + headerMetaDataData => extHeaderMetaDataData, + headerMetaDataRdEn => extHeaderMetaDataRdEn, + payloadValid => extPayloadValid, + payloadData => extPayloadData, + payloadRdEn => extPayloadRdEn); + + ----------------------------------------------------------------------------- + -- W4/W9/W12 — Input packet buffer + header validation + -- (TransportLayer.bsv:103-105, 122-129). sq*/rq* status inputs share the + -- same muxed comm bundle (OQ-EMIT-QP-01); G5 mux below. + ----------------------------------------------------------------------------- + reqPktMetaXfer <= pktBufReqPktMetaValid and qpReqPktMetaReady; + reqPktPayloadXfer <= pktBufReqPayloadValid and qpReqPktPayloadReady; + respPktMetaXfer <= pktBufRespPktMetaValid and qpRespPktMetaReady; + respPktPayloadXfer <= pktBufRespPayloadValid and qpRespPktPayloadReady; + + U_PktBuf : entity surf.InputRdmaPktBufAndHeaderValidation + generic map ( + TPD_G => TPD_G, + MAX_QP_G => MAX_QP_G, + EN_TX_G => EN_TX_G, + EN_RX_G => EN_RX_G) + port map ( + clk => clk, + rst => rst, + payloadPipeInValid => extPayloadValid, + payloadPipeInData => extPayloadData, + payloadPipeInRdEn => extPayloadRdEn, + headerDataStreamValid => extHeaderDataStreamValid, + headerDataStreamData => extHeaderDataStreamData, + headerDataStreamRdEn => extHeaderDataStreamRdEn, + headerMetaDataValid => extHeaderMetaDataValid, + headerMetaDataData => extHeaderMetaDataData, + headerMetaDataRdEn => extHeaderMetaDataRdEn, + getPdQpn => pktBufGetPdQpn, + getPdMaybeValid => pktBufGetPdMaybeValid, + getPdHandler => pktBufGetPdHandler, + getQpQpn => pktBufGetQpQpn, + sqTypeQP => statusTypeSqMux, + sqIsERR => statusIsErrMux, + sqIsRTS => statusIsRtsMux, + sqIsNonErr => statusIsNonErrMux, + sqQKEY => statusQkeyMux, + sqPMTU => statusPmtuMux, + rqTypeQP => statusTypeRqMux, + rqIsERR => statusIsErrMux, + rqIsRTS => statusIsRtsMux, + rqIsNonErr => statusIsNonErrMux, + rqQKEY => statusQkeyMux, + reqPktMetaDataValid => pktBufReqPktMetaValid, + reqPktMetaDataDout => pktBufReqPktMetaDout, + reqPktMetaDataRdEn => reqPktMetaXfer, + reqPayloadValid => pktBufReqPayloadValid, + reqPayloadDout => pktBufReqPayloadDout, + reqPayloadRdEn => reqPktPayloadXfer, + respPktMetaDataValid => pktBufRespPktMetaValid, + respPktMetaDataDout => pktBufRespPktMetaDout, + respPktMetaDataRdEn => respPktMetaXfer, + respPayloadValid => pktBufRespPayloadValid, + respPayloadDout => pktBufRespPayloadDout, + respPayloadRdEn => respPktPayloadXfer, + cnpValid => cnpValid, + cnpDout => open, + cnpRdEn => CNP_TIE_C); + + ----------------------------------------------------------------------------- + -- G5 — QP-status mux (replaces BSV getQueuePairByQPN, RESOLVED + -- OQ-FSM-MDQPS-01 sec.2.3): index = getIndexQP(dqpn) = truncateLSB(qpn). + -- At MAX_QP_G=1 the BSV index is 0 bits wide, i.e. the constant 0 + -- (MetaData.bsv:349) - force 0 instead of reading a live QPN bit. + ----------------------------------------------------------------------------- + statusIdx <= ite(MAX_QP_G > 1, + to_integer(unsigned(pktBufGetQpQpn(23 downto 24-QP_IDX_WIDTH_C))), + 0); + + statusTypeSqMux <= qpStatusTypeSq(statusIdx); + statusTypeRqMux <= qpStatusTypeRq(statusIdx); + statusIsErrMux <= qpCommIsErr(statusIdx); + statusIsRtsMux <= qpCommIsRts(statusIdx); + statusIsNonErrMux <= qpCommIsNonErr(statusIdx); + statusQkeyMux <= qpCommQkey(statusIdx); + statusPmtuMux <= qpCommPmtu(statusIdx); + + ----------------------------------------------------------------------------- + -- GEN_QP — the MAX_QP_G queue pairs (BSV qpVec, HOISTED here per RESOLVED + -- OQ-FSM-MDQPS-01; per-QP wiring loop TransportLayer.bsv:116-152). + -- Arbiter slots: even 2i = RQ/resp face, odd 2i+1 = SQ/req face. + ----------------------------------------------------------------------------- + GEN_QP : for i in 0 to MAX_QP_G-1 generate + U_Qp : entity surf.Qp + generic map ( + TPD_G => TPD_G, + EN_TX_G => EN_TX_G, + EN_RX_G => EN_RX_G, + EN_READ_G => EN_READ_G) + port map ( + clk => clk, + rst => rst, + -- W8: srvPortQP <- MetaDataQPs per-QP client bundle + srvPortReqValid => qpCtrlReqValid(i), + srvPortReqData => qpCtrlReqData, + srvPortReqReady => qpCtrlReqReady(i), + srvPortRespValid => qpCtrlRespValid(i), + srvPortRespData => qpCtrlRespData((i+1)*RESP_QP_W_C-1 downto i*RESP_QP_W_C), + srvPortRespReady => qpCtrlRespReady(i), + -- W2: dispatcher per-QP outputs (G2 qualified strobes) + recvReqInValid => recvReqXfer(i), + recvReqInData => dispRecvReqOutData((i+1)*RECV_REQ_W_C-1 downto i*RECV_REQ_W_C), + recvReqInReady => qpRecvReqInReady(i), + workReqInValid => workReqXfer(i), + workReqInData => dispWorkReqOutData((i+1)*WORK_REQ_W_C-1 downto i*WORK_REQ_W_C), + workReqInReady => qpWorkReqInReady(i), + -- W11: DMA read/write clients -> arbiter slots 2i (RQ) / 2i+1 (SQ) + dmaReadClt4RqReqValid => dmaRdCltReqValid(2*i), + dmaReadClt4RqReqData => dmaRdCltReqData((2*i+1)*DMA_RD_REQ_W_C-1 downto (2*i)*DMA_RD_REQ_W_C), + dmaReadClt4RqReqReady => dmaRdCltReqGet(2*i), + dmaReadClt4RqRespValid => dmaRdCltRespValid(2*i), + dmaReadClt4RqRespData => dmaRdCltRespData((2*i+1)*DMA_RD_RESP_W_C-1 downto (2*i)*DMA_RD_RESP_W_C), + dmaReadClt4RqRespReady => dmaRdCltRespReady(2*i), + dmaWriteClt4RqReqValid => dmaWrCltReqValid(2*i), + dmaWriteClt4RqReqData => dmaWrCltReqData((2*i+1)*DMA_WR_REQ_W_C-1 downto (2*i)*DMA_WR_REQ_W_C), + dmaWriteClt4RqReqReady => dmaWrCltReqGet(2*i), + dmaWriteClt4RqRespValid => dmaWrCltRespValid(2*i), + dmaWriteClt4RqRespData => dmaWrCltRespData((2*i+1)*DMA_WR_RESP_W_C-1 downto (2*i)*DMA_WR_RESP_W_C), + dmaWriteClt4RqRespReady => dmaWrCltRespReady(2*i), + dmaReadClt4SqReqValid => dmaRdCltReqValid(2*i+1), + dmaReadClt4SqReqData => dmaRdCltReqData((2*i+2)*DMA_RD_REQ_W_C-1 downto (2*i+1)*DMA_RD_REQ_W_C), + dmaReadClt4SqReqReady => dmaRdCltReqGet(2*i+1), + dmaReadClt4SqRespValid => dmaRdCltRespValid(2*i+1), + dmaReadClt4SqRespData => dmaRdCltRespData((2*i+2)*DMA_RD_RESP_W_C-1 downto (2*i+1)*DMA_RD_RESP_W_C), + dmaReadClt4SqRespReady => dmaRdCltRespReady(2*i+1), + dmaWriteClt4SqReqValid => dmaWrCltReqValid(2*i+1), + dmaWriteClt4SqReqData => dmaWrCltReqData((2*i+2)*DMA_WR_REQ_W_C-1 downto (2*i+1)*DMA_WR_REQ_W_C), + dmaWriteClt4SqReqReady => dmaWrCltReqGet(2*i+1), + dmaWriteClt4SqRespValid => dmaWrCltRespValid(2*i+1), + dmaWriteClt4SqRespData => dmaWrCltRespData((2*i+2)*DMA_WR_RESP_W_C-1 downto (2*i+1)*DMA_WR_RESP_W_C), + dmaWriteClt4SqRespReady => dmaWrCltRespReady(2*i+1), + -- W10: PermCheck clients -> arbiter slots 2i (RQ) / 2i+1 (SQ) + permCheckClt4RqReqValid => permSrvReqValid(2*i), + permCheckClt4RqReqData => permSrvReqData((2*i+1)*PERM_REQ_W_C-1 downto (2*i)*PERM_REQ_W_C), + permCheckClt4RqReqReady => permSrvReqGet(2*i), + permCheckClt4RqRespValid => permSrvRespValid(2*i), + permCheckClt4RqRespData => permSrvRespData(2*i), + permCheckClt4RqRespReady => permSrvRespReady(2*i), + permCheckClt4SqReqValid => permSrvReqValid(2*i+1), + permCheckClt4SqReqData => permSrvReqData((2*i+2)*PERM_REQ_W_C-1 downto (2*i+1)*PERM_REQ_W_C), + permCheckClt4SqReqReady => permSrvReqGet(2*i+1), + permCheckClt4SqRespValid => permSrvRespValid(2*i+1), + permCheckClt4SqRespData => permSrvRespData(2*i+1), + permCheckClt4SqRespReady => permSrvRespReady(2*i+1), + -- W4: packet buffer per-QP pipes (G2 qualified strobes) + reqPktMetaWrEn => reqPktMetaXfer(i), + reqPktMetaData => pktBufReqPktMetaDout((i+1)*PKT_META_W_C-1 downto i*PKT_META_W_C), + reqPktMetaReady => qpReqPktMetaReady(i), + reqPktPayloadWrEn => reqPktPayloadXfer(i), + reqPktPayloadData => pktBufReqPayloadDout((i+1)*DATA_STREAM_W_C-1 downto i*DATA_STREAM_W_C), + reqPktPayloadReady => qpReqPktPayloadReady(i), + respPktMetaWrEn => respPktMetaXfer(i), + respPktMetaData => pktBufRespPktMetaDout((i+1)*PKT_META_W_C-1 downto i*PKT_META_W_C), + respPktMetaReady => qpRespPktMetaReady(i), + respPktPayloadWrEn => respPktPayloadXfer(i), + respPktPayloadData => pktBufRespPayloadDout((i+1)*DATA_STREAM_W_C-1 downto i*DATA_STREAM_W_C), + respPktPayloadReady => qpRespPktPayloadReady(i), + -- W12: status bundle (only the members read by validateHeader are + -- used; the rest of the shared comm* group is left open) + commIsCreate => open, + commIsErr => qpCommIsErr(i), + commIsInit => open, + commIsNonErr => qpCommIsNonErr(i), + commIsReset => open, + commIsRTR => open, + commIsRTS => qpCommIsRts(i), + commIsSQD => open, + commIsUnknown => open, + commIsRTR2RTS => open, + commIsStableRTS => open, + commGetAccessFlags => open, + commGetMaxRnrCnt => open, + commGetMaxRetryCnt => open, + commGetMinRnrTimer => open, + commGetMaxTimeOut => open, + commGetPendingWorkReqNum => open, + commGetPendingRecvReqNum => open, + commGetPendingReadAtomicReqNum => open, + commGetPendingDestReadAtomicReqNum => open, + commGetSigAll => open, + commGetSQPN => open, + commGetDQPN => open, + commGetPKEY => open, + commGetQKEY => qpCommQkey(i), + commGetPMTU => qpCommPmtu(i), + statusGetTypeSq => qpStatusTypeSq(i), + statusGetTypeRq => qpStatusTypeRq(i), + statusSqIsSQ => open, + statusRqIsSQ => open, + -- W5: RDMA output streams -> U_DataStreamArb slots 2i (resp) / 2i+1 (req) + rdmaReqValid => dataStreamArbInValid(2*i+1), + rdmaReqData => dataStreamArbInDout((2*i+2)*DATA_STREAM_W_C-1 downto (2*i+1)*DATA_STREAM_W_C), + rdmaReqRdEn => dataStreamArbInRd(2*i+1), + rdmaRespValid => dataStreamArbInValid(2*i), + rdmaRespData => dataStreamArbInDout((2*i+1)*DATA_STREAM_W_C-1 downto (2*i)*DATA_STREAM_W_C), + rdmaRespRdEn => dataStreamArbInRd(2*i), + -- W6: work completions -> WC arbiters slot i + workCompRqValid => recvWcArbInValid(i), + workCompRqData => recvWcArbInDout((i+1)*WORK_COMP_W_C-1 downto i*WORK_COMP_W_C), + workCompRqRdEn => recvWcArbInRd(i), + workCompSqValid => sendWcArbInValid(i), + workCompSqData => sendWcArbInDout((i+1)*WORK_COMP_W_C-1 downto i*WORK_COMP_W_C), + workCompSqRdEn => sendWcArbInRd(i)); + end generate GEN_QP; + + ----------------------------------------------------------------------------- + -- W5 — RDMA DataStream output arbiter (TransportLayer.bsv:135-138,160-162). + -- inFinished(k) = head isLast bit (isDataStreamFinished), = bit 0 of slice k. + ----------------------------------------------------------------------------- + GEN_DS_FINISHED : for k in 0 to 2*MAX_QP_G-1 generate + dataStreamArbInFinished(k) <= dataStreamArbInDout(k*DATA_STREAM_W_C); + end generate GEN_DS_FINISHED; + + U_DataStreamArb : entity surf.PipeOutArbiter + generic map ( + TPD_G => TPD_G, + PORT_COUNT_G => 2*MAX_QP_G, + DATA_WIDTH_G => DATA_STREAM_W_C) + port map ( + clk => clk, + rst => rst, + inValid => dataStreamArbInValid, + inDout => dataStreamArbInDout, + inFinished => dataStreamArbInFinished, + inRd => dataStreamArbInRd, + outNotEmpty => dataStreamOutValid, + outDout => dataStreamOutData, + outFinished => open, + outDeq => dataStreamOutRdEn); + + ----------------------------------------------------------------------------- + -- W6 — Work-completion arbiters (TransportLayer.bsv:164-166,176-177); + -- isWorkCompFinished = constant True -> inFinished tied all-ones. + ----------------------------------------------------------------------------- + -- RQ work-completion arbiter: pruned when EN_RX_G=false (the per-QP + -- workCompRq faces are tied invalid inside Qp). + GEN_NO_RECV_WC : if not EN_RX_G generate + workCompRqValid <= '0'; + workCompRqData <= (others => '0'); + recvWcArbInRd <= (others => '0'); + end generate GEN_NO_RECV_WC; + + GEN_RECV_WC : if EN_RX_G generate + U_RecvWcArb : entity surf.PipeOutArbiter + generic map ( + TPD_G => TPD_G, + PORT_COUNT_G => MAX_QP_G, + DATA_WIDTH_G => WORK_COMP_W_C) + port map ( + clk => clk, + rst => rst, + inValid => recvWcArbInValid, + inDout => recvWcArbInDout, + inFinished => WC_FINISHED_C, + inRd => recvWcArbInRd, + outNotEmpty => workCompRqValid, + outDout => workCompRqData, + outFinished => open, + outDeq => workCompRqRdEn); + end generate GEN_RECV_WC; + + -- SQ work-completion arbiter: pruned when EN_TX_G=false. + GEN_NO_SEND_WC : if not EN_TX_G generate + workCompSqValid <= '0'; + workCompSqData <= (others => '0'); + sendWcArbInRd <= (others => '0'); + end generate GEN_NO_SEND_WC; + + GEN_SEND_WC : if EN_TX_G generate + U_SendWcArb : entity surf.PipeOutArbiter + generic map ( + TPD_G => TPD_G, + PORT_COUNT_G => MAX_QP_G, + DATA_WIDTH_G => WORK_COMP_W_C) + port map ( + clk => clk, + rst => rst, + inValid => sendWcArbInValid, + inDout => sendWcArbInDout, + inFinished => WC_FINISHED_C, + inRd => sendWcArbInRd, + outNotEmpty => workCompSqValid, + outDout => workCompSqData, + outFinished => open, + outDeq => workCompSqRdEn); + end generate GEN_SEND_WC; + + ----------------------------------------------------------------------------- + -- W7 — MetaData cluster (TransportLayer.bsv:88-91,179). srv* face is the + -- top-level re-export; qp-side nets are mdSrvQp* (RESOLVED MDSRV-01 sec.5). + ----------------------------------------------------------------------------- + U_MetaDataSrv : entity surf.MetaDataSrv + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + srvReqValid => mdSrvReqValid, + srvReqData => mdSrvReqData, + srvReqReady => mdSrvReqReady, + srvRespValid => mdSrvRespValid, + srvRespData => mdSrvRespData, + srvRespReady => mdSrvRespReady, + pdReqValid => mdSrvPdReqValid, + pdReqData => mdSrvPdReqData, + pdReqReady => mdSrvPdReqReady, + pdRespValid => mdSrvPdRespValid, + pdRespData => mdSrvPdRespData, + pdRespReady => mdSrvPdRespReady, + isValidPdHandler => mdSrvIsValidPdHandler, + isValidPd => mdSrvIsValidPd, + mrSrvPdHandler => mrSrvPdHandler, + mrSrvPdValid => mrSrvPdValid, + mrSrvReqValid => mrSrvReqValid, + mrSrvReqData => mrSrvReqData, + mrSrvReqReady => mrSrvReqReady, + mrSrvRespValid => mrSrvRespValid, + mrSrvRespData => mrSrvRespData, + mrSrvRespReady => mrSrvRespReady, + qpReqValid => mdSrvQpReqValid, + qpReqData => mdSrvQpReqData, + qpReqReady => mdSrvQpReqReady, + qpRespValid => mdSrvQpRespValid, + qpRespData => mdSrvQpRespData, + qpRespReady => mdSrvQpRespReady); + + U_MetaDataPDs : entity surf.MetaDataPDs + generic map ( + TPD_G => TPD_G, + MAX_PD_G => MAX_PD_C) + port map ( + clk => clk, + rst => rst, + srvReqValid => mdSrvPdReqValid, + srvReqData => mdSrvPdReqData, + srvReqReady => mdSrvPdReqReady, + srvRespValid => mdSrvPdRespValid, + srvRespData => mdSrvPdRespData, + srvRespReady => mdSrvPdRespReady, + isValidPdHandler => mdSrvIsValidPdHandler, + isValidPd => mdSrvIsValidPd, + mrLkupPdHandler => mrLkupPdHandler, + mrLkupKey => mrLkupKey, + mrLkupByLocal => mrLkupByLocal, + mrLkupReqValid => mrLkupReqValid, + mrLkupValid => mrLkupValid, + mrLkupData => mrLkupData, + mrSrvPdHandler => mrSrvPdHandler, + mrSrvPdValid => mrSrvPdValid, + mrSrvReqValid => mrSrvReqValid, + mrSrvReqData => mrSrvReqData, + mrSrvReqReady => mrSrvReqReady, + mrSrvRespValid => mrSrvRespValid, + mrSrvRespData => mrSrvRespData, + mrSrvRespReady => mrSrvRespReady, + clearEn => '0', -- no clear() caller in mkTransportLayer + notEmpty => open, + notFull => open); + + U_MetaDataQPs : entity surf.MetaDataQPs + generic map ( + TPD_G => TPD_G, + MAX_QP_G => MAX_QP_G) + port map ( + clk => clk, + rst => rst, + srvReqValid => mdSrvQpReqValid, + srvReqData => mdSrvQpReqData, + srvReqReady => mdSrvQpReqReady, + srvRespValid => mdSrvQpRespValid, + srvRespData => mdSrvQpRespData, + srvRespReady => mdSrvQpRespReady, + qpReqValid => qpCtrlReqValid, + qpReqData => qpCtrlReqData, + qpReqReady => qpCtrlReqReady, + qpRespValid => qpCtrlRespValid, + qpRespData => qpCtrlRespData, + qpRespReady => qpCtrlRespReady, + getPdQpn => pktBufGetPdQpn, + getPdMaybeValid => pktBufGetPdMaybeValid, + getPdHandler => pktBufGetPdHandler, + notEmpty => open, + notFull => open); + + ----------------------------------------------------------------------------- + -- W10/G4 — PermCheck arbitration + downstream server (TransportLayer.bsv: + -- 139-140,154,158). G4 = mkConnection(arbitratedPermCheckClt, permCheckSrv). + ----------------------------------------------------------------------------- + U_PermCheckCltArb : entity surf.PermCheckCltArbiter + generic map ( + TPD_G => TPD_G, + MAX_QP_G => MAX_QP_G) + port map ( + clk => clk, + rst => rst, + permSrvReqValid => permSrvReqValid, + permSrvReqData => permSrvReqData, + permSrvReqGet => permSrvReqGet, + permSrvRespValid => permSrvRespValid, + permSrvRespData => permSrvRespData, + permSrvRespReady => permSrvRespReady, + permCltReqValid => permCltReqValid, + permCltReqData => permCltReqData, + permCltReqRd => permCltReqRd, + permCltRespValid => permCltRespValid, + permCltRespData => permCltRespData, + permCltRespReady => permCltRespReady); + + U_PermCheckSrv : entity surf.PermCheckSrv + generic map ( + TPD_G => TPD_G) + port map ( + clk => clk, + rst => rst, + reqPutValid => permCltReqValid, + reqPutData => permCltReqData, + reqPutReady => permReqPutReady, + respGetValid => permRespGetValid, + respGetData => permRespGetData, + respGetRdEn => permRespGetRdEn, + mrLkupPdHandler => mrLkupPdHandler, + mrLkupKey => mrLkupKey, + mrLkupByLocal => mrLkupByLocal, + mrLkupReqValid => mrLkupReqValid, + mrLkupValid => mrLkupValid, + mrLkupData => mrLkupData); + + -- G4 Get<->Put transfer strobes + permCltReqRd <= permCltReqValid and permReqPutReady; + permCltRespValid <= permRespGetValid and permCltRespReady; + permCltRespData(0) <= permRespGetData; + permRespGetRdEn <= permRespGetValid and permCltRespReady; + + ----------------------------------------------------------------------------- + -- W11 — DMA read/write client arbitration (TransportLayer.bsv:141-144, + -- 155-156); downstream faces re-exported on the top-level (180-181). + ----------------------------------------------------------------------------- + U_DmaReadCltArb : entity surf.DmaReadCltArbiter + generic map ( + TPD_G => TPD_G, + MAX_QP_G => MAX_QP_G) + port map ( + clk => clk, + rst => rst, + cltReqValid => dmaRdCltReqValid, + cltReqData => dmaRdCltReqData, + cltReqGet => dmaRdCltReqGet, + cltRespValid => dmaRdCltRespValid, + cltRespData => dmaRdCltRespData, + cltRespReady => dmaRdCltRespReady, + outReqValid => dmaReadReqValid, + outReqData => dmaReadReqData, + outReqRd => dmaReadReqRd, + outRespValid => dmaReadRespValid, + outRespData => dmaReadRespData, + outRespReady => dmaReadRespReady); + + U_DmaWriteCltArb : entity surf.DmaWriteCltArbiter + generic map ( + TPD_G => TPD_G, + MAX_QP_G => MAX_QP_G) + port map ( + clk => clk, + rst => rst, + cltReqValid => dmaWrCltReqValid, + cltReqData => dmaWrCltReqData, + cltReqGet => dmaWrCltReqGet, + cltRespValid => dmaWrCltRespValid, + cltRespData => dmaWrCltRespData, + cltRespReady => dmaWrCltRespReady, + outReqValid => dmaWriteReqValid, + outReqData => dmaWriteReqData, + outReqRd => dmaWriteReqRd, + outRespValid => dmaWriteRespValid, + outRespData => dmaWriteRespData, + outRespReady => dmaWriteRespReady); + + ----------------------------------------------------------------------------- + -- CNP empty-pipe assertion (BSV genEmptyPipeOutRule, TransportLayer.bsv: + -- 147-151) — simulation-only reproduction of the BSV error rule. + ----------------------------------------------------------------------------- + -- pragma translate_off + cnpCheck : process (clk) is + begin + if rising_edge(clk) then + if (rst = '0') then + assert (cnpValid = CNP_TIE_C) + report "cnpPipeOutVec must be empty - TODO: support CNP (TransportLayer.bsv:147-151)" + severity failure; + end if; + end if; + end process cnpCheck; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/WorkCompGenRq.vhd b/ethernet/RoCEv2/rtl/WorkCompGenRq.vhd new file mode 100644 index 0000000000..61fd7885fa --- /dev/null +++ b/ethernet/RoCEv2/rtl/WorkCompGenRq.vhd @@ -0,0 +1,778 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Receive-queue sibling of WorkCompGenSq. A 3-state control FSM +-- (workCompGenState) wrapped around a 2-stage SURF Fifo pipeline (one stage +-- shorter than SQ — there is no pendingWorkCompQ4* input-buffer stage; the +-- input PipeOut feeds dmaWaitingQ directly). +-- +-- Token flow (each FIFO is a surf.Fifo, FWFT, sync): +-- input PipeOut (wcGenReqPipeInFromRQ) +-- --recvWorkCompReqRQ--> U_DmaWaitingQ +-- --waitDmaDoneRQ (NORMAL) / noDmaWaitRQ (ERR)--> U_GenWorkCompQ +-- --genWorkCompRQ (NORMAL) / errFlushRQ (ERR)--> U_WorkCompOutQ4RQ +-- --> workCompPipeOut +-- \--(waitDmaDoneRQ error path)--> U_WcStatusQ4SQ (DEAD) +-- +-- FSM states (BSV workCompGenStateReg, mkReg(WC_GEN_ST_STOP)): +-- WC_GEN_ST_STOP_S — idle; no pipeline rule active +-- WC_GEN_ST_NORMAL_S — normal completion generation +-- WC_GEN_ST_ERR_FLUSH_S — flushing pending WCs as IBV_WC_WR_FLUSH_ERR +-- +-- Derived mode signals (combinational, recomputed every cycle): +-- inNormalState = isNonErr AND state=NORMAL +-- inErrorState = isERR OR state=ERR_FLUSH +-- (Note vs SQ: RQ's mode/start guards use cntrlStatus.comm.isNonErr, not +-- isStableRTS/isRTS. start fires on isNonErr && state==STOP.) +-- +-- State-register writers (guard-mutually-exclusive; emit priority +-- reset > start > genWorkCompRQ): +-- resetAndClear (isReset) -> STOP_S, clear all 4 FIFOs +-- start (isNonErr && STOP) -> NORMAL_S +-- genWorkCompRQ (NORMAL, !success) -> ERR_FLUSH_S +-- The six pipeline rules are conflict_free, operate on disjoint FIFOs and are +-- emitted as concurrent combinational datapaths (no priority among them). +-- NORMAL/ERROR stage pairs (waitDmaDoneRQ/noDmaWaitRQ on dmaWaitingQ; +-- genWorkCompRQ/errFlushRQ on genWorkCompQ) share a FIFO rd/wr enable but are +-- mutually exclusive by mode, so each shared enable is driven by exactly one +-- path per cycle. +-- +-- FIFO clear (OQ-FSM-01 carry-forward, RESOLVED in out/03-fsm/RESOLVED.md): +-- BSV FIFOF.clear under resetAndClear maps to asserting each Fifo's rst, +-- OR'd with the structural reset: fifoClr = rst OR isReset. surf.FifoSync +-- holds logically empty for the whole asserted window (level-safe); no pulse +-- generator needed. Requires GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, +-- RST_POLARITY_G='1'. +-- +-- Mapping note (OQ-FSM-WCGRQ-01, RESOLVED): mapping.json owns.state_registers +-- is empty and owns.rules carries fabricated aliases for this entity; the +-- FSM spec (and this file) are authoritative for state and rules. RQ has +-- exactly ONE registered field (workCompGenState); all per-token context +-- rides inside the PendingWorkCompRQ struct through the FIFOs (no mkRegU +-- context registers, unlike the SQ twin). The four surf_instances FIFOs in +-- mapping.json are correct by name. +-- +-- Dead output (OQ-FSM-WCGRQ-02, RESOLVED option (a) — keep for fidelity): +-- U_WcStatusQ4SQ is written by waitDmaDoneRQ's error (!success) path but is +-- NEVER dequeued and NEVER exported — the WorkCompGen interface exposes only +-- workCompPipeOut + hasErr, and the would-be workCompStatusPipeOutRQ line is +-- commented out in the BSV (WorkCompGen.bsv:700). It is kept instantiated +-- here for source fidelity: it preserves BSV back-pressure (after MAX error +-- tokens, wcsNotFull='0' back-pressures the error path of waitDmaDoneRQ). +-- TODO: this RQ->SQ WC-status pipe has no consumer in the current source — +-- wire up workCompStatusPipeOutRQ or drop the FIFO once the consumer exists. +-- +-- Excluded by design (OQ-FSM-WCGRQ-03): the BSV source's commented-out +-- err-flush helper functions (genErrFlushWorkComp4WorkCompGenReqRQ / +-- genErrFlushWorkComp4RecvReq), CQ-full back-pressure handling +-- (isCompQueueFull), and the workCompStatusPipeOutRQ interface are NOT +-- implemented — they are commented out in the source. errFlushRQ instead +-- reuses the carried pendingWorkCompRQ.maybeWorkComp and overrides +-- flags/status (NO_FLAGS / WR_FLUSH_ERR). +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_DmaWaitingQ : surf.Fifo DATA_WIDTH_G=428 ADDR_WIDTH_G=4 +-- PendingWorkCompRQ ; mkFIFOF (default depth) +-- U_GenWorkCompQ : surf.Fifo DATA_WIDTH_G=428 ADDR_WIDTH_G=4 +-- PendingWorkCompRQ ; mkFIFOF (default depth) +-- U_WorkCompOutQ4RQ : surf.Fifo DATA_WIDTH_G=222 ADDR_WIDTH_G=5 (depth 32) +-- WorkComp ; mkSizedFIFOF MAX_CQE. rd side exported as +-- workCompPipeOut (downstream drives rd_en). +-- U_WcStatusQ4SQ : surf.Fifo DATA_WIDTH_G=5 ADDR_WIDTH_G=4 +-- WorkCompStatus ; mkFIFOF. DEAD (no reader) — see above. +-- Block-RAM FWFT cold latency is 2 cycles (DOB reg) — see tb-spec §8. +-- +-- Type widths (BSV deriving(Bits), first-field-at-MSB; traced from +-- DataTypes.bsv/Headers.bsv/Settings.bsv — see OQ-FSM-H2DS-04 packing rule): +-- WorkComp = 222 b (id 64 | opcode 8 | flags 7 | status 5 | len 32 | +-- pkey 16 | qpn 24 | immDt 33 | rkey2Inv 33) +-- WorkCompGenReqRQ = 198 b (rrID Maybe#(WorkReqID) 65 | len 32 | reqPSN 24 | +-- isZeroDmaLen 1 | wcStatus 5 | reqOpCode 5 | +-- immDt Maybe#(IMM) 33 | rkey2Inv Maybe#(RKEY) 33) +-- PendingWorkCompRQ = 428 b (wcGenReqRQ 198 | maybeWorkComp Maybe#(WorkComp) 223 | +-- isSendReq 1 | isWriteReq 1 | isWriteImmReq 1 | +-- isFirstOrOnlyReq 1 | isLastOrOnlyReq 1 | +-- isWorkCompSuccess 1 | needWaitDmaWriteResp 1) +-- WorkCompStatus = 5 b (24 enum values) +-- RdmaOpCode = 5 b (24 enum values, encodings 0x00..0x17) +-- PayloadConResp = 53 b (= DmaWriteResp: initiator 4 | sqpn 24 | psn 24 | +-- isRespErr 1) ; dmaWriteResp.psn = [24:1] +-- +-- WorkCompGenReqRQ field slices (in reqData_i, 198-bit input word): +-- rrID.tag=[197] rrID.id=[196:133] len=[132:101] reqPSN=[100:77] +-- isZeroDmaLen=[76] wcStatus=[75:71] reqOpCode=[70:66] +-- immDt=[65:33] (tag [65], val [64:33]) rkey2Inv=[32:0] (tag [32], val [31:0]) +-- PendingWorkCompRQ field slices (in dmaDout/genDout, 428-bit word): +-- wcGenReqRQ=[427:230] (wcStatus within = [305:301], reqPSN = [330:307]) +-- maybeWorkComp.tag=[229] maybeWorkComp.workComp=[228:7] +-- (id|opcode=[228:157] flags=[156:150] status=[149:145] rest=[144:7]) +-- isSendReq=[6] isWriteReq=[5] isWriteImmReq=[4] isFirstOrOnlyReq=[3] +-- isLastOrOnlyReq=[2] isWorkCompSuccess=[1] needWaitDmaWriteResp=[0] +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity WorkCompGenRq is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- cntrlStatus.comm status methods (combinational inputs) + isReset_i : in sl; -- isReset -> resetAndClear + isNonErr_i : in sl; -- isNonErr -> start / inNormalState + isERR_i : in sl; -- isERR (inErrorState) + getPKEY_i : in slv(15 downto 0); -- getPKEY -> WorkComp.pkey + getSQPN_i : in slv(23 downto 0); -- getSQPN -> WorkComp.qpn + -- payloadConRespPort : Get#(PayloadConResp) (entity deqs) + payloadConRespValid_i : in sl; -- response available + payloadConRespData_i : in slv(52 downto 0); -- PayloadConResp packed (sim-only use) + payloadConRespGetEn_o : out sl; -- .get handshake (deq) + -- wcGenReqPipeInFromRQ : PipeOut#(WorkCompGenReqRQ) + reqValid_i : in sl; -- notEmpty + reqData_i : in slv(197 downto 0); -- first (WorkCompGenReqRQ) + reqDeq_o : out sl; -- deq + -- workCompPipeOut : PipeOut#(WorkComp) (= U_WorkCompOutQ4RQ read face) + workCompValid_o : out sl; -- notEmpty + workCompData_o : out slv(221 downto 0); -- first (WorkComp) + workCompRdEn_i : in sl; -- deq (downstream drives) + -- hasErr() method + hasErr_o : out sl); -- state = ERR_FLUSH_S +end entity WorkCompGenRq; + +architecture rtl of WorkCompGenRq is + + -- FSM control state (BSV WorkCompGenState / workCompGenStateReg) + type StateType is (WC_GEN_ST_STOP_S, WC_GEN_ST_NORMAL_S, WC_GEN_ST_ERR_FLUSH_S); + + type RegType is record + state : StateType; -- workCompGenStateReg (mkReg STOP) + end record RegType; + + constant REG_INIT_C : RegType := ( + state => WC_GEN_ST_STOP_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- WorkComp enum constants (DataTypes.bsv) + constant WC_RECV_C : slv(7 downto 0) := x"80"; -- IBV_WC_RECV = 128 + constant WC_RECV_RDMA_W_IMM_C : slv(7 downto 0) := x"81"; -- IBV_WC_RECV_RDMA_WITH_IMM = 129 + constant WC_NO_FLAGS_C : slv(6 downto 0) := "0000000"; -- IBV_WC_NO_FLAGS = 0 + constant WC_WITH_IMM_C : slv(6 downto 0) := "0000010"; -- IBV_WC_WITH_IMM = 2 + constant WC_WITH_INV_C : slv(6 downto 0) := "0001000"; -- IBV_WC_WITH_INV = 8 + constant WC_SUCCESS_C : slv(4 downto 0) := "00000"; -- IBV_WC_SUCCESS = 0 + constant WC_WR_FLUSH_ERR_C : slv(4 downto 0) := "00101"; -- IBV_WC_WR_FLUSH_ERR = 5 + + -- U_DmaWaitingQ (PendingWorkCompRQ, 428b) + signal dmaWrEn : sl; + signal dmaDin : slv(427 downto 0); + signal dmaRdEn : sl; + signal dmaDout : slv(427 downto 0); + signal dmaValid : sl; + signal dmaNotFull : sl; + + -- U_GenWorkCompQ (PendingWorkCompRQ, 428b) + signal genWrEn : sl; + signal genDin : slv(427 downto 0); + signal genRdEn : sl; + signal genDout : slv(427 downto 0); + signal genValid : sl; + signal genNotFull : sl; + + -- U_WorkCompOutQ4RQ (WorkComp, 222b) + signal outWrEn : sl; + signal outDin : slv(221 downto 0); + signal outDout : slv(221 downto 0); + signal outValid : sl; + signal outNotFull : sl; + + -- U_WcStatusQ4SQ (WorkCompStatus, 5b) — DEAD output (written, never read) + signal wcsWrEn : sl; + signal wcsDin : slv(4 downto 0); + signal wcsNotFull : sl; + + -- FIFO clear line: level = rst OR isReset (see FIFO clear note above) + signal fifoClr : sl; + +begin + + -- FIFO clear: level-sensitive (OQ-FSM-01 carry-forward, RESOLVED) + fifoClr <= rst or isReset_i; + + -- hasErr() : Moore decode of registered state + hasErr_o <= '1' when (r.state = WC_GEN_ST_ERR_FLUSH_S) else '0'; + + -- workCompPipeOut read face (pass-through; downstream drives rd_en) + workCompValid_o <= outValid; + workCompData_o <= outDout; + + --------------------------------------------------------------------------- + -- U_DmaWaitingQ : surf.Fifo + -- mkFIFOF carrying PendingWorkCompRQ. + -- wr: recvWorkCompReqRQ ; rd: waitDmaDoneRQ (NORMAL) / noDmaWaitRQ (ERR). + --------------------------------------------------------------------------- + U_DmaWaitingQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 428, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => dmaWrEn, + din => dmaDin, + not_full => dmaNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => dmaRdEn, + dout => dmaDout, + valid => dmaValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_GenWorkCompQ : surf.Fifo + -- mkFIFOF carrying PendingWorkCompRQ. + -- wr: waitDmaDoneRQ (NORMAL) / noDmaWaitRQ (ERR) ; + -- rd: genWorkCompRQ (NORMAL) / errFlushRQ (ERR). + --------------------------------------------------------------------------- + U_GenWorkCompQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 428, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => genWrEn, + din => genDin, + not_full => genNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => genRdEn, + dout => genDout, + valid => genValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_WorkCompOutQ4RQ : surf.Fifo + -- mkSizedFIFOF(MAX_CQE=32) carrying WorkComp. + -- wr: genWorkCompRQ (NORMAL) / errFlushRQ (ERR) ; + -- rd side = workCompPipeOut (downstream consumer drives rd_en). + --------------------------------------------------------------------------- + U_WorkCompOutQ4RQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 222, + ADDR_WIDTH_G => 5) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => outWrEn, + din => outDin, + not_full => outNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => workCompRdEn_i, -- downstream drives (PipeOut deq) + dout => outDout, + valid => outValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_WcStatusQ4SQ : surf.Fifo (DEAD OUTPUT — kept for source fidelity) + -- mkFIFOF carrying WorkCompStatus (5b). + -- wr: waitDmaDoneRQ error (!success) path ; + -- rd: NONE — there is no reader/consumer in this source (see header / + -- OQ-FSM-WCGRQ-02). rd_en is tied off and dout/valid left open; the + -- FIFO can saturate and back-pressure the error path via wcsNotFull, + -- exactly as the BSV mkFIFOF does. + -- TODO: wire up workCompStatusPipeOutRQ consumer or drop this instance. + --------------------------------------------------------------------------- + U_WcStatusQ4SQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 5, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => wcsWrEn, + din => wcsDin, + not_full => wcsNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => '0', -- DEAD: no reader + dout => open, + valid => open, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, isReset_i, isNonErr_i, isERR_i, getPKEY_i, getSQPN_i, + payloadConRespValid_i, reqValid_i, reqData_i, + dmaValid, dmaNotFull, dmaDout, + genValid, genNotFull, genDout, outNotFull, wcsNotFull) is + variable v : RegType; + -- derived mode signals + variable inNormalState : boolean; + variable inErrorState : boolean; + -- recvWorkCompReqRQ datapath temporaries (from reqData_i : WorkCompGenReqRQ) + variable reqOpCode : slv(4 downto 0); + variable wcStatus : slv(4 downto 0); + variable wcOpcode : slv(7 downto 0); + variable wcOpcodeValid : sl; + variable wcFlags : slv(6 downto 0); + variable isSendReq : sl; + variable isWriteReq : sl; + variable isWriteImmReq : sl; + variable isFirstReq : sl; + variable isLastReq : sl; + variable isOnlyReq : sl; + variable isFirstOrOnly : sl; + variable isLastOrOnly : sl; + variable isSuccess : sl; + variable needWaitDma : sl; + variable maybeWcTag : sl; + variable workCompBuilt : slv(221 downto 0); + variable pendToken : slv(427 downto 0); + -- waitDmaDoneRQ guard helpers (from dmaDout : PendingWorkCompRQ) + variable dmaIsSuccess : sl; + variable dmaNeedWaitDma : sl; + variable dmaIsLastOnly : sl; + variable dmaIsSend : sl; + variable dmaIsWriteImm : sl; + variable waitGenEnq : sl; -- success path enqueues genWorkCompQ? + variable waitStatEnq : sl; -- error path enqueues wcStatusQ4SQ? + variable waitGetWanted : sl; -- success path deqs payloadConResp? + variable waitFire : sl; + -- genWorkCompRQ / errFlushRQ helpers (from genDout : PendingWorkCompRQ) + variable genIsSuccess : sl; + variable genMaybeTag : sl; + variable genWorkComp : slv(221 downto 0); + variable genEnqWanted : sl; + variable errFlushWC : slv(221 downto 0); + variable errEnqWanted : sl; + begin + v := r; + + -- default (deasserted) outputs / FIFO controls + dmaWrEn <= '0'; + dmaDin <= (others => '0'); + dmaRdEn <= '0'; + genWrEn <= '0'; + genDin <= (others => '0'); + genRdEn <= '0'; + outWrEn <= '0'; + outDin <= (others => '0'); + wcsWrEn <= '0'; + wcsDin <= (others => '0'); + payloadConRespGetEn_o <= '0'; + reqDeq_o <= '0'; + + -- derived mode signals (combinational from registered state + inputs) + inNormalState := (isNonErr_i = '1') and (r.state = WC_GEN_ST_NORMAL_S); + inErrorState := (isERR_i = '1') or (r.state = WC_GEN_ST_ERR_FLUSH_S); + + ---------------------------------------------------------------------- + -- recvWorkCompReqRQ datapath: decode reqOpCode and build the + -- PendingWorkCompRQ token from the input WorkCompGenReqRQ word. + ---------------------------------------------------------------------- + reqOpCode := reqData_i(70 downto 66); + wcStatus := reqData_i(75 downto 71); + + -- RdmaOpCode classification + WorkComp opcode/flags mapping + -- (Utils.bsv isSendReqRdmaOpCode/isWriteReqRdmaOpCode/isWriteImmReq*, + -- isFirst/isLast/isOnlyRdmaOpCode, rdmaOpCode2WorkCompOpCode4RQ, + -- rdmaOpCode2WorkCompFlagsRQ). reqOpCode encodings 0x00..0x17. + isSendReq := '0'; + isWriteReq := '0'; + isWriteImmReq := '0'; + isFirstReq := '0'; + isLastReq := '0'; + isOnlyReq := '0'; + wcOpcode := WC_RECV_C; + wcOpcodeValid := '0'; + wcFlags := WC_NO_FLAGS_C; + case reqOpCode is + when "00000" => -- SEND_FIRST + isSendReq := '1'; isFirstReq := '1'; + wcOpcode := WC_RECV_C; wcOpcodeValid := '1'; wcFlags := WC_NO_FLAGS_C; + when "00001" => -- SEND_MIDDLE + isSendReq := '1'; + wcOpcode := WC_RECV_C; wcOpcodeValid := '1'; wcFlags := WC_NO_FLAGS_C; + when "00010" => -- SEND_LAST + isSendReq := '1'; isLastReq := '1'; + wcOpcode := WC_RECV_C; wcOpcodeValid := '1'; wcFlags := WC_NO_FLAGS_C; + when "00011" => -- SEND_LAST_WITH_IMMEDIATE + isSendReq := '1'; isLastReq := '1'; + wcOpcode := WC_RECV_C; wcOpcodeValid := '1'; wcFlags := WC_WITH_IMM_C; + when "00100" => -- SEND_ONLY + isSendReq := '1'; isOnlyReq := '1'; + wcOpcode := WC_RECV_C; wcOpcodeValid := '1'; wcFlags := WC_NO_FLAGS_C; + when "00101" => -- SEND_ONLY_WITH_IMMEDIATE + isSendReq := '1'; isOnlyReq := '1'; + wcOpcode := WC_RECV_C; wcOpcodeValid := '1'; wcFlags := WC_WITH_IMM_C; + when "00110" => -- RDMA_WRITE_FIRST + isWriteReq := '1'; isFirstReq := '1'; + wcOpcodeValid := '0'; + when "00111" => -- RDMA_WRITE_MIDDLE + isWriteReq := '1'; + wcOpcodeValid := '0'; + when "01000" => -- RDMA_WRITE_LAST + isWriteReq := '1'; isLastReq := '1'; + wcOpcodeValid := '0'; + when "01001" => -- RDMA_WRITE_LAST_WITH_IMMEDIATE + isWriteReq := '1'; isWriteImmReq := '1'; isLastReq := '1'; + wcOpcode := WC_RECV_RDMA_W_IMM_C; wcOpcodeValid := '1'; wcFlags := WC_WITH_IMM_C; + when "01010" => -- RDMA_WRITE_ONLY + isWriteReq := '1'; isOnlyReq := '1'; + wcOpcodeValid := '0'; + when "01011" => -- RDMA_WRITE_ONLY_WITH_IMMEDIATE + isWriteReq := '1'; isWriteImmReq := '1'; isOnlyReq := '1'; + wcOpcode := WC_RECV_RDMA_W_IMM_C; wcOpcodeValid := '1'; wcFlags := WC_WITH_IMM_C; + when "01100" => -- RDMA_READ_REQUEST + isOnlyReq := '1'; wcOpcodeValid := '0'; + when "01101" => -- RDMA_READ_RESPONSE_FIRST + isFirstReq := '1'; wcOpcodeValid := '0'; + when "01110" => -- RDMA_READ_RESPONSE_MIDDLE + wcOpcodeValid := '0'; + when "01111" => -- RDMA_READ_RESPONSE_LAST + isLastReq := '1'; wcOpcodeValid := '0'; + when "10000" => -- RDMA_READ_RESPONSE_ONLY + isOnlyReq := '1'; wcOpcodeValid := '0'; + when "10001" => -- ACKNOWLEDGE + isOnlyReq := '1'; wcOpcodeValid := '0'; + when "10010" => -- ATOMIC_ACKNOWLEDGE + isOnlyReq := '1'; wcOpcodeValid := '0'; + when "10011" => -- COMPARE_SWAP + isOnlyReq := '1'; wcOpcodeValid := '0'; + when "10100" => -- FETCH_ADD + isOnlyReq := '1'; wcOpcodeValid := '0'; + when "10101" => -- RESYNC + wcOpcodeValid := '0'; + when "10110" => -- SEND_LAST_WITH_INVALIDATE + isSendReq := '1'; isLastReq := '1'; + wcOpcode := WC_RECV_C; wcOpcodeValid := '1'; wcFlags := WC_WITH_INV_C; + when "10111" => -- SEND_ONLY_WITH_INVALIDATE + isSendReq := '1'; isOnlyReq := '1'; + wcOpcode := WC_RECV_C; wcOpcodeValid := '1'; wcFlags := WC_WITH_INV_C; + when others => -- 0x18..0x1f unused + wcOpcodeValid := '0'; + end case; + + isFirstOrOnly := isFirstReq or isOnlyReq; + isLastOrOnly := isLastReq or isOnlyReq; + + -- isWorkCompSuccess = wcStatus == IBV_WC_SUCCESS + if (wcStatus = WC_SUCCESS_C) then + isSuccess := '1'; + else + isSuccess := '0'; + end if; + + -- needWaitDmaWriteResp = !isZeroDmaLen && (isSendReq || isWriteReq) + if (reqData_i(76) = '0') and ((isSendReq = '1') or (isWriteReq = '1')) then + needWaitDma := '1'; + else + needWaitDma := '0'; + end if; + + -- maybeWorkComp = genWorkComp4RecvReq(cntrlStatus, first): + -- Valid iff (mapped WC opcode Valid) && (rrID Valid). + maybeWcTag := wcOpcodeValid and reqData_i(197); -- rrID.tag = reqData_i(197) + -- WorkComp { id=rrID.id, opcode=wcOpcode, flags=wcFlags, status=wcStatus, + -- len=wr.len, pkey=getPKEY, qpn=getSQPN, immDt, rkey2Inv } + workCompBuilt := reqData_i(196 downto 133) -- id (64) = rrID.id + & wcOpcode -- opcode (8) + & wcFlags -- flags (7) + & wcStatus -- status (5) + & reqData_i(132 downto 101) -- len (32) + & getPKEY_i -- pkey (16) + & getSQPN_i -- qpn (24) + & reqData_i(65 downto 33) -- immDt (33, Maybe passthrough) + & reqData_i(32 downto 0); -- rkey2Inv(33, Maybe passthrough) + + -- PendingWorkCompRQ = wcGenReqRQ(198) & maybeWcTag & workComp(222) & 7 bools + pendToken := reqData_i -- wcGenReqRQ (198) + & maybeWcTag -- maybeWorkComp.tag (1) + & workCompBuilt -- maybeWorkComp.workComp (222) + & isSendReq & isWriteReq & isWriteImmReq + & isFirstOrOnly & isLastOrOnly + & isSuccess & needWaitDma; + dmaDin <= pendToken; + + ---------------------------------------------------------------------- + -- waitDmaDoneRQ guard helpers (from dmaDout : PendingWorkCompRQ) + ---------------------------------------------------------------------- + dmaIsSuccess := dmaDout(1); + dmaNeedWaitDma := dmaDout(0); + dmaIsLastOnly := dmaDout(2); + dmaIsSend := dmaDout(6); + dmaIsWriteImm := dmaDout(4); + -- success path enqueues genWorkCompQ only if isLastOrOnly && (isSend||isWriteImm) + if (dmaIsSuccess = '1') then + if (dmaIsLastOnly = '1') and ((dmaIsSend = '1') or (dmaIsWriteImm = '1')) then + waitGenEnq := '1'; + else + waitGenEnq := '0'; + end if; + waitStatEnq := '0'; + waitGetWanted := dmaNeedWaitDma; -- conditional .get + else + -- error path: enqueue genWorkCompQ AND wcStatusQ4SQ unconditionally + waitGenEnq := '1'; + waitStatEnq := '1'; + waitGetWanted := '0'; + end if; + + ---------------------------------------------------------------------- + -- genWorkCompRQ / errFlushRQ helpers (from genDout : PendingWorkCompRQ) + ---------------------------------------------------------------------- + genIsSuccess := genDout(1); + genMaybeTag := genDout(229); + genWorkComp := genDout(228 downto 7); -- maybeWorkComp.workComp + -- genWorkCompRQ enq: success -> always enq unwrapped WC; error -> enq only if Valid + if (genIsSuccess = '1') then + genEnqWanted := '1'; + else + genEnqWanted := genMaybeTag; + end if; + -- errFlushRQ: override flags->NO_FLAGS, status->WR_FLUSH_ERR; enq only on Valid + -- and ((isSend && isFirstOrOnly) || isWriteImm) + errFlushWC := genDout(228 downto 157) -- id|opcode (72) + & WC_NO_FLAGS_C -- flags (7) + & WC_WR_FLUSH_ERR_C -- status (5) + & genDout(144 downto 7); -- len..rkey2Inv (138) + if (genMaybeTag = '1') and + (((genDout(6) = '1') and (genDout(3) = '1')) or (genDout(4) = '1')) then + errEnqWanted := '1'; + else + errEnqWanted := '0'; + end if; + + ---------------------------------------------------------------------- + -- Pipeline rules (conflict_free; concurrent datapaths). All gated off + -- while isReset (resetAndClear dominates, clearing the FIFOs). + ---------------------------------------------------------------------- + if (isReset_i = '0') then + + -- recvWorkCompReqRQ (row 3): input PipeOut -> U_DmaWaitingQ + if ((inNormalState or inErrorState) and reqValid_i = '1' and dmaNotFull = '1') then + reqDeq_o <= '1'; + dmaWrEn <= '1'; + -- dmaDin already built above (pendToken) + end if; + + -- U_DmaWaitingQ -> U_GenWorkCompQ : waitDmaDoneRQ (NORMAL) / noDmaWaitRQ (ERR) + -- (mutually exclusive by mode; share dmaRdEn / genWrEn / genDin) + if (inNormalState and dmaValid = '1') then + -- waitDmaDoneRQ: conditional implicit conditions — + -- genNotFull gates only when waitGenEnq; wcsNotFull only when waitStatEnq; + -- payloadConRespValid only when waitGetWanted. + waitFire := '1'; + if (waitGenEnq = '1' and genNotFull = '0') then + waitFire := '0'; + end if; + if (waitStatEnq = '1' and wcsNotFull = '0') then + waitFire := '0'; + end if; + if (waitGetWanted = '1' and payloadConRespValid_i = '0') then + waitFire := '0'; + end if; + if (waitFire = '1') then + dmaRdEn <= '1'; -- deq dmaWaitingQ + if (waitGenEnq = '1') then + genWrEn <= '1'; + genDin <= dmaDout; -- PendingWorkCompRQ pass-through + end if; + if (waitStatEnq = '1') then + wcsWrEn <= '1'; + wcsDin <= dmaDout(305 downto 301); -- wcGenReqRQ.wcStatus + end if; + if (waitGetWanted = '1') then + payloadConRespGetEn_o <= '1'; -- conditional .get (deq DMA resp) + end if; + end if; + elsif (inErrorState and dmaValid = '1' and genNotFull = '1') then + -- noDmaWaitRQ (no DMA wait / no status enq in error) + dmaRdEn <= '1'; + genWrEn <= '1'; + genDin <= dmaDout; + end if; + + -- U_GenWorkCompQ -> U_WorkCompOutQ4RQ : genWorkCompRQ (NORMAL) / errFlushRQ (ERR) + if (inNormalState and genValid = '1') then + -- genWorkCompRQ: outNotFull gates firing only on the enqueuing branch. + if (genEnqWanted = '0' or outNotFull = '1') then + genRdEn <= '1'; -- deq genWorkCompQ + if (genIsSuccess = '1') then + -- success: emit the unwrapped WorkComp (sim-assert Valid below) + outWrEn <= '1'; + outDin <= genWorkComp; + else + -- error: enter ERR_FLUSH; emit the carried WC if Valid + v.state := WC_GEN_ST_ERR_FLUSH_S; + if (genMaybeTag = '1') then + outWrEn <= '1'; + outDin <= genWorkComp; + end if; + end if; + end if; + + elsif (inErrorState and genValid = '1') then + -- errFlushRQ: deq always; emit flush-overridden WC when enq wanted. + if (errEnqWanted = '0' or outNotFull = '1') then + genRdEn <= '1'; -- deq genWorkCompQ + if (errEnqWanted = '1') then + outWrEn <= '1'; + outDin <= errFlushWC; + end if; + end if; + end if; + + -- discardPayloadConRespRQ (row 8, ERR): drain payloadConRespPort. + -- Mutually exclusive with waitDmaDoneRQ's getEn by mode. + if (inErrorState and payloadConRespValid_i = '1') then + payloadConRespGetEn_o <= '1'; + end if; + + -- start (row 2): STOP -> NORMAL on isNonErr + if (isNonErr_i = '1' and r.state = WC_GEN_ST_STOP_S) then + v.state := WC_GEN_ST_NORMAL_S; + end if; + + end if; + + -- resetAndClear (row 1, highest priority): force STOP; FIFOs cleared via fifoClr + if (isReset_i = '1') then + v.state := WC_GEN_ST_STOP_S; + end if; + + -- structural synchronous reset (dominates; matches mkReg STOP power-on) + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + --------------------------------------------------------------------------- + -- Simulation-only assertions (no synthesizable effect; BSV immAssert): + -- 1. genWorkCompRQ success: maybeWorkComp must be Valid (genDout(229)='1'). + -- 2. waitDmaDoneRQ: when getting a DMA resp, its psn must match reqPSN. + -- 3. errFlushRQ: token must be a SEND or WRITE_IMM request when emitting. + --------------------------------------------------------------------------- + -- pragma translate_off + chk : process (clk) is + begin + if rising_edge(clk) then + if (rst = '0' and isReset_i = '0') then + -- (1) genWorkCompRQ success path: carried WC must be Valid + if (isNonErr_i = '1' and r.state = WC_GEN_ST_NORMAL_S and + genValid = '1' and genDout(1) = '1') then + assert (genDout(229) = '1') + report "WorkCompGenRq: genWorkCompRQ maybeWorkComp must be Valid on success" + severity warning; + end if; + -- (2) waitDmaDoneRQ DMA-response PSN match (NORMAL, conditional get) + if (isNonErr_i = '1' and r.state = WC_GEN_ST_NORMAL_S and + dmaValid = '1' and dmaDout(1) = '1' and dmaDout(0) = '1' and + payloadConRespValid_i = '1') then + assert (payloadConRespData_i(24 downto 1) = dmaDout(330 downto 307)) + report "WorkCompGenRq: waitDmaDoneRQ dmaWriteResp.psn /= wcGenReqRQ.reqPSN" + severity error; + end if; + -- (3) errFlushRQ: emitted WC must be SEND or WRITE_IMM + if ((isERR_i = '1' or r.state = WC_GEN_ST_ERR_FLUSH_S) and genValid = '1' and + genDout(229) = '1') then + assert (genDout(6) = '1' or genDout(4) = '1') + report "WorkCompGenRq: errFlushRQ token must be SEND or WRITE_IMM" + severity error; + end if; + end if; + end if; + end process chk; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/WorkCompGenSq.vhd b/ethernet/RoCEv2/rtl/WorkCompGenSq.vhd new file mode 100644 index 0000000000..62c84d74d3 --- /dev/null +++ b/ethernet/RoCEv2/rtl/WorkCompGenSq.vhd @@ -0,0 +1,692 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- 3-state control FSM (workCompGenState) wrapped around a 4-stage SURF Fifo +-- pipeline that turns SQ work-completion-generation requests into WorkComp +-- tokens exposed on workCompPipeOut. +-- +-- Token flow (each FIFO is a surf.Fifo, FWFT, sync): +-- 2 PipeIns --recvWorkCompGenReqSQ--> U_PendingWorkCompQ4SQ +-- --genPendingWorkCompSQ--> U_DmaWaitingQ +-- --waitDmaDoneSQ (NORMAL) / noDmaWaitSQ (ERR)--> U_GenWorkCompQ +-- --genWorkCompSQ (NORMAL) / errFlushSQ (ERR)--> U_WorkCompOutQ4SQ +-- --> workCompPipeOut +-- +-- FSM states (BSV workCompGenStateReg, mkReg(WC_GEN_ST_STOP)): +-- WC_GEN_ST_STOP_S — idle; no pipeline rule active +-- WC_GEN_ST_NORMAL_S — normal completion generation +-- WC_GEN_ST_ERR_FLUSH_S — flushing pending WCs as IBV_WC_WR_FLUSH_ERR +-- +-- Derived mode signals (combinational, recomputed every cycle): +-- inNormalState = isStableRTS AND state=NORMAL +-- inErrorState = isERR OR state=ERR_FLUSH +-- +-- State-register writers (guard-mutually-exclusive; emit priority +-- reset > start > genWorkCompSQ): +-- resetAndClear (isReset) -> STOP_S, clear all 4 FIFOs +-- start (isRTS && STOP) -> NORMAL_S +-- genWorkCompSQ (NORMAL, !success) -> ERR_FLUSH_S +-- The seven pipeline rules are conflict_free, operate on disjoint FIFOs and +-- are emitted as concurrent combinational datapaths (no priority among them). +-- NORMAL/ERROR stage pairs share a FIFO rd/wr enable but are mutually +-- exclusive by mode, so the shared enable is driven by exactly one path/cycle. +-- +-- FIFO clear (OQ-FSM-01 carry-forward, RESOLVED in out/03-fsm/RESOLVED.md): +-- BSV FIFOF.clear under resetAndClear maps to asserting each Fifo's rst, +-- OR'd with the structural reset: fifoClr = rst OR isReset. surf.FifoSync +-- holds logically empty for the whole asserted window (level-safe); no pulse +-- generator needed. Requires GEN_SYNC_FIFO_G=true, RST_ASYNC_G=false, +-- RST_POLARITY_G='1'. +-- +-- Mapping note (OQ-FSM-WCGSQ-01, RESOLVED): mapping.json owns.state_registers +-- is empty and owns.rules carries fabricated aliases for this entity; the +-- FSM spec (and this file) are authoritative for state and rules. The four +-- surf_instances FIFOs in mapping.json are correct. +-- +-- Excluded by design (OQ-FSM-WCGSQ-02): the BSV source's commented-out +-- RQ-error propagation (recvWorkCompStatusRQ / rqHasErrReg) and CQ-full +-- back-pressure handling (isCompQueueFull) are NOT implemented — they are +-- stubbed/absent in the source. +-- +-- mkRegU fields (OQ-FSM-WCGSQ-02): isFirstErrPartialAckWorkReq and +-- firstErrPartialAckWorkReqId are BSV mkRegU (no power-on reset). They are +-- written by genWorkCompSQ on ERR entry strictly before errFlushSQ reads +-- them, so the undefined power-on value is never observed. Emitted in +-- REG_INIT_C with zero init for determinism; the no-reset origin is noted. +-- +-- Conditional implicit condition (OQ-FSM-WCGSQ-03): waitDmaDoneSQ deqs +-- payloadConRespPort only inside (isWorkCompSuccess && wcWaitDmaResp); the +-- port's readiness gates the dmaWaitingQ->genWorkCompQ move only then. +-- +-- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): +-- U_PendingWorkCompQ4SQ : surf.Fifo DATA_WIDTH_G=633 ADDR_WIDTH_G=6 (depth 64) +-- WorkCompGenReqSQ ; mkSizedFIFOF MAX_PENDING_WORK_COMP_NUM +-- U_DmaWaitingQ : surf.Fifo DATA_WIDTH_G=857 ADDR_WIDTH_G=4 +-- PendingWorkCompSQ ; mkFIFOF (default depth) +-- U_GenWorkCompQ : surf.Fifo DATA_WIDTH_G=857 ADDR_WIDTH_G=4 +-- PendingWorkCompSQ ; mkFIFOF (default depth) +-- U_WorkCompOutQ4SQ : surf.Fifo DATA_WIDTH_G=222 ADDR_WIDTH_G=5 (depth 32) +-- WorkComp ; mkSizedFIFOF MAX_CQE. rd side exported +-- as workCompPipeOut (downstream drives rd_en). +-- Block-RAM FWFT cold latency is 2 cycles (DOB reg) — see tb-spec §8. +-- +-- Type widths (BSV deriving(Bits), first-field-at-MSB; traced from +-- DataTypes.bsv/Headers.bsv/Settings.bsv): +-- WorkReq = 601 b (id 64 | opcode 4 | flags 5 | raddr 64 | rkey 32 | +-- len 32 | laddr 64 | lkey 32 | sqpn 24 | solicited 1 | +-- comp 65 | swap 65 | immDt 33 | rkey2Inv 33 | +-- srqn 25 | dqpn 25 | qkey 33) +-- WorkComp = 222 b (id 64 | opcode 8 | flags 7 | status 5 | len 32 | +-- pkey 16 | qpn 24 | immDt 33 | rkey2Inv 33) +-- WorkCompGenReqSQ = 633 b (wr 601 | wcWaitDmaResp 1 | wcReqType 2 | +-- triggerPSN 24 | wcStatus 5) +-- PendingWorkCompSQ= 857 b (wcGenReqSQ 633 | workComp 222 | +-- isWorkCompSuccess 1 | needWorkCompWhenNormal 1) +-- PayloadConResp = 53 b (= DmaWriteResp: initiator 4 | sqpn 24 | psn 24 | +-- isRespErr 1) ; dmaWriteResp.psn = [24:1] +-- +-- WorkCompGenReqSQ field slices (in pendDout / wcGenReqSQ at +224 in dmaDout/genDout): +-- wr.id = [632:569] wr.opcode = [568:565] wr.flags = [564:560] +-- wr.len = [463:432] wcWaitDmaResp = [31] wcReqType = [30:29] +-- triggerPSN = [28:5] wcStatus = [4:0] +-- WorkComp field slices (within the 222-bit token): +-- id=[221:158] opcode=[157:150] flags=[149:143] status=[142:138] +-- len=[137:106] pkey=[105:90] qpn=[89:66] immDt=[65:33] rkey2Inv=[32:0] +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity WorkCompGenSq is + generic ( + TPD_G : time := 1 ns); + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + -- cntrlStatus.comm status methods (combinational inputs) + isReset_i : in sl; -- isReset -> resetAndClear + isRTS_i : in sl; -- isRTS -> start + isStableRTS_i : in sl; -- isStableRTS (inNormalState) + isERR_i : in sl; -- isERR (inErrorState) + getSigAll_i : in sl; -- getSigAll + getPKEY_i : in slv(15 downto 0); -- getPKEY -> WorkComp.pkey + getSQPN_i : in slv(23 downto 0); -- getSQPN -> WorkComp.qpn + -- payloadConRespPort : Get#(PayloadConResp) (entity deqs) + payloadConRespValid_i : in sl; -- response available + payloadConRespData_i : in slv(52 downto 0); -- PayloadConResp packed (sim-only use) + payloadConRespGetEn_o : out sl; -- .get handshake (deq) + -- wcGenReqPipeInFromReqGenInSQ : PipeOut#(WorkCompGenReqSQ) + reqGenInValid_i : in sl; -- notEmpty + reqGenInData_i : in slv(632 downto 0); -- first (WorkCompGenReqSQ) + reqGenInDeq_o : out sl; -- deq + -- wcGenReqPipeInFromRespHandleInSQ : PipeOut#(WorkCompGenReqSQ) + respHandleInValid_i : in sl; -- notEmpty + respHandleInData_i : in slv(632 downto 0); -- first (WorkCompGenReqSQ) + respHandleInDeq_o : out sl; -- deq + -- workCompPipeOut : PipeOut#(WorkComp) (= U_WorkCompOutQ4SQ read face) + workCompValid_o : out sl; -- notEmpty + workCompData_o : out slv(221 downto 0); -- first (WorkComp) + workCompRdEn_i : in sl; -- deq (downstream drives) + -- hasErr() method + hasErr_o : out sl); -- state = ERR_FLUSH_S +end entity WorkCompGenSq; + +architecture rtl of WorkCompGenSq is + + -- FSM control state (BSV WorkCompGenState / workCompGenStateReg) + type StateType is (WC_GEN_ST_STOP_S, WC_GEN_ST_NORMAL_S, WC_GEN_ST_ERR_FLUSH_S); + + type RegType is record + state : StateType; -- workCompGenStateReg (mkReg STOP) + isFirstErrPartialAckWorkReq : sl; -- mkRegU (no reset) — see header + firstErrPartialAckWorkReqId : slv(63 downto 0); -- mkRegU (no reset) — WorkReqID + end record RegType; + + constant REG_INIT_C : RegType := ( + state => WC_GEN_ST_STOP_S, + isFirstErrPartialAckWorkReq => '0', -- mkRegU: zero init for determinism + firstErrPartialAckWorkReqId => (others => '0')); -- mkRegU: zero init for determinism + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + -- WorkComp enum constants (DataTypes.bsv) + constant WC_NO_FLAGS_C : slv(6 downto 0) := "0000000"; -- IBV_WC_NO_FLAGS = 0 + constant WC_WR_FLUSH_ERR_C : slv(4 downto 0) := "00101"; -- IBV_WC_WR_FLUSH_ERR = 5 + constant WC_SUCCESS_C : slv(4 downto 0) := "00000"; -- IBV_WC_SUCCESS = 0 + constant WC_REQ_FULL_ACK_C : slv(1 downto 0) := "00"; -- WC_REQ_TYPE_FULL_ACK = 0 + constant WC_REQ_PART_ACK_C : slv(1 downto 0) := "01"; -- WC_REQ_TYPE_PARTIAL_ACK = 1 + -- immDt (Maybe#(IMM)=33) + rkey2Inv (Maybe#(RKEY)=33) = 66 Invalid bits + constant WC_MAYBE_PAD_C : slv(65 downto 0) := (others => '0'); + + -- U_PendingWorkCompQ4SQ (WorkCompGenReqSQ, 633b) + signal pendWrEn : sl; + signal pendDin : slv(632 downto 0); + signal pendRdEn : sl; + signal pendDout : slv(632 downto 0); + signal pendValid : sl; + signal pendNotFull : sl; + + -- U_DmaWaitingQ (PendingWorkCompSQ, 857b) + signal dmaWrEn : sl; + signal dmaDin : slv(856 downto 0); + signal dmaRdEn : sl; + signal dmaDout : slv(856 downto 0); + signal dmaValid : sl; + signal dmaNotFull : sl; + + -- U_GenWorkCompQ (PendingWorkCompSQ, 857b) + signal genWrEn : sl; + signal genDin : slv(856 downto 0); + signal genRdEn : sl; + signal genDout : slv(856 downto 0); + signal genValid : sl; + signal genNotFull : sl; + + -- U_WorkCompOutQ4SQ (WorkComp, 222b) + signal outWrEn : sl; + signal outDin : slv(221 downto 0); + signal outDout : slv(221 downto 0); + signal outValid : sl; + signal outNotFull : sl; + + -- FIFO clear line: level = rst OR isReset (see FIFO clear note above) + signal fifoClr : sl; + +begin + + -- FIFO clear: level-sensitive (OQ-FSM-01 carry-forward, RESOLVED) + fifoClr <= rst or isReset_i; + + -- hasErr() : Moore decode of registered state + hasErr_o <= '1' when (r.state = WC_GEN_ST_ERR_FLUSH_S) else '0'; + + -- workCompPipeOut read face (pass-through; downstream drives rd_en) + workCompValid_o <= outValid; + workCompData_o <= outDout; + + --------------------------------------------------------------------------- + -- U_PendingWorkCompQ4SQ : surf.Fifo + -- mkSizedFIFOF(MAX_PENDING_WORK_COMP_NUM=64) carrying WorkCompGenReqSQ. + -- wr: recvWorkCompGenReqSQ ; rd: genPendingWorkCompSQ. + --------------------------------------------------------------------------- + U_PendingWorkCompQ4SQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 633, + ADDR_WIDTH_G => 6) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => pendWrEn, + din => pendDin, + not_full => pendNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => pendRdEn, + dout => pendDout, + valid => pendValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_DmaWaitingQ : surf.Fifo + -- mkFIFOF carrying PendingWorkCompSQ. + -- wr: genPendingWorkCompSQ ; rd: waitDmaDoneSQ (NORMAL) / noDmaWaitSQ (ERR). + --------------------------------------------------------------------------- + U_DmaWaitingQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 857, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => dmaWrEn, + din => dmaDin, + not_full => dmaNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => dmaRdEn, + dout => dmaDout, + valid => dmaValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_GenWorkCompQ : surf.Fifo + -- mkFIFOF carrying PendingWorkCompSQ. + -- wr: waitDmaDoneSQ (NORMAL) / noDmaWaitSQ (ERR) ; + -- rd: genWorkCompSQ (NORMAL) / errFlushSQ (ERR). + --------------------------------------------------------------------------- + U_GenWorkCompQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 857, + ADDR_WIDTH_G => 4) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => genWrEn, + din => genDin, + not_full => genNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => genRdEn, + dout => genDout, + valid => genValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- U_WorkCompOutQ4SQ : surf.Fifo + -- mkSizedFIFOF(MAX_CQE=32) carrying WorkComp. + -- wr: genWorkCompSQ (NORMAL) / errFlushSQ (ERR) ; + -- rd side = workCompPipeOut (downstream consumer drives rd_en). + --------------------------------------------------------------------------- + U_WorkCompOutQ4SQ : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => 222, + ADDR_WIDTH_G => 5) + port map ( + rst => fifoClr, + wr_clk => clk, + wr_en => outWrEn, + din => outDin, + not_full => outNotFull, + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => workCompRdEn_i, -- downstream drives (PipeOut deq) + dout => outDout, + valid => outValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + + --------------------------------------------------------------------------- + -- Combinatorial process + --------------------------------------------------------------------------- + comb : process (r, rst, isReset_i, isRTS_i, isStableRTS_i, isERR_i, + getSigAll_i, getPKEY_i, getSQPN_i, + payloadConRespValid_i, reqGenInValid_i, reqGenInData_i, + respHandleInValid_i, respHandleInData_i, + pendValid, pendNotFull, pendDout, + dmaValid, dmaNotFull, dmaDout, + genValid, genNotFull, genDout, outNotFull) is + variable v : RegType; + -- derived mode signals + variable inNormalState : boolean; + variable inErrorState : boolean; + -- genPendingWorkCompSQ datapath temporaries (from pendDout) + variable wrOpcode : slv(3 downto 0); + variable wcOpcode : slv(7 downto 0); + variable wcOpcodeValid : sl; + variable isReadOrAtom : sl; + variable wcStatus : slv(4 downto 0); + variable wcReqType : slv(1 downto 0); + variable isSuccess : sl; + variable needNormal : sl; + variable workCompBuilt : slv(221 downto 0); + -- genWorkCompSQ / errFlushSQ datapath temporaries (from genDout) + variable genIsSuccess : sl; + variable genNeedNormal : sl; + variable genWorkComp : slv(221 downto 0); + variable errFlushWC : slv(221 downto 0); + variable genEnqWanted : sl; + -- waitDmaDoneSQ datapath temporaries (from dmaDout) + variable dmaIsSuccess : sl; + variable dmaWaitResp : sl; + variable waitDmaCond : sl; + begin + v := r; + + -- default (deasserted) outputs / FIFO controls + pendWrEn <= '0'; + pendDin <= (others => '0'); + pendRdEn <= '0'; + dmaWrEn <= '0'; + dmaDin <= (others => '0'); + dmaRdEn <= '0'; + genWrEn <= '0'; + genDin <= (others => '0'); + genRdEn <= '0'; + outWrEn <= '0'; + outDin <= (others => '0'); + payloadConRespGetEn_o <= '0'; + reqGenInDeq_o <= '0'; + respHandleInDeq_o <= '0'; + + -- derived mode signals (combinational from registered state + inputs) + inNormalState := (isStableRTS_i = '1') and (r.state = WC_GEN_ST_NORMAL_S); + inErrorState := (isERR_i = '1') or (r.state = WC_GEN_ST_ERR_FLUSH_S); + + ---------------------------------------------------------------------- + -- genPendingWorkCompSQ datapath (build PendingWorkCompSQ from pendDout) + -- WorkCompGenReqSQ slices: wr.opcode=[568:565] wr.flags=[564:560] + -- wr.id=[632:569] wr.len=[463:432] wcReqType=[30:29] wcStatus=[4:0] + ---------------------------------------------------------------------- + wrOpcode := pendDout(568 downto 565); + wcStatus := pendDout(4 downto 0); + wcReqType := pendDout(30 downto 29); + + -- workReqOpCode2WorkCompOpCode4SQ (Utils.bsv:1518) + case wrOpcode is + when "0000" => wcOpcode := x"01"; wcOpcodeValid := '1'; -- RDMA_WRITE -> WC_RDMA_WRITE(1) + when "0001" => wcOpcode := x"01"; wcOpcodeValid := '1'; -- RDMA_WRITE_WITH_IMM -> WC_RDMA_WRITE(1) + when "0010" => wcOpcode := x"00"; wcOpcodeValid := '1'; -- SEND -> WC_SEND(0) + when "0011" => wcOpcode := x"00"; wcOpcodeValid := '1'; -- SEND_WITH_IMM -> WC_SEND(0) + when "0100" => wcOpcode := x"02"; wcOpcodeValid := '1'; -- RDMA_READ -> WC_RDMA_READ(2) + when "0101" => wcOpcode := x"03"; wcOpcodeValid := '1'; -- ATOMIC_CMP_AND_SWP -> WC_COMP_SWAP(3) + when "0110" => wcOpcode := x"04"; wcOpcodeValid := '1'; -- ATOMIC_FETCH_AND_ADD-> WC_FETCH_ADD(4) + when "0111" => wcOpcode := x"06"; wcOpcodeValid := '1'; -- LOCAL_INV -> WC_LOCAL_INV(6) + when "1000" => wcOpcode := x"05"; wcOpcodeValid := '1'; -- BIND_MW -> WC_BIND_MW(5) + when "1001" => wcOpcode := x"00"; wcOpcodeValid := '1'; -- SEND_WITH_INV -> WC_SEND(0) + when "1010" => wcOpcode := x"07"; wcOpcodeValid := '1'; -- TSO -> WC_TSO(7) + when others => wcOpcode := x"00"; wcOpcodeValid := '0'; -- tagged Invalid + end case; + + -- isReadOrAtomicWorkReq (Utils.bsv:1443): RDMA_READ / CMP_AND_SWP / FETCH_AND_ADD + if (wrOpcode = "0100" or wrOpcode = "0101" or wrOpcode = "0110") then + isReadOrAtom := '1'; + else + isReadOrAtom := '0'; + end if; + + -- isWorkCompSuccess = wcStatus == IBV_WC_SUCCESS + if (wcStatus = WC_SUCCESS_C) then + isSuccess := '1'; + else + isSuccess := '0'; + end if; + + -- needWorkCompWhenNormal = wcReqType==FULL_ACK && + -- (workReqNeedWorkCompSQ(wr) || getSigAll) + -- workReqNeedWorkCompSQ = containWorkReqFlag(flags, IBV_SEND_SIGNALED=2 => bit1) + -- || isReadOrAtomicWorkReq(opcode) + if (wcReqType = WC_REQ_FULL_ACK_C) and + ((pendDout(561) = '1') or (isReadOrAtom = '1') or (getSigAll_i = '1')) then + needNormal := '1'; + else + needNormal := '0'; + end if; + + -- genWorkComp4WorkReq(cntrlStatus, wcGenReqSQ): WorkComp token + -- id=wr.id, opcode=wcOpcode, flags=NO_FLAGS, status=wcStatus, len=wr.len, + -- pkey=getPKEY, qpn=getSQPN, immDt=Invalid, rkey2Inv=Invalid + workCompBuilt := pendDout(632 downto 569) -- id (64) + & wcOpcode -- opcode (8) + & WC_NO_FLAGS_C -- flags (7) + & wcStatus -- status (5) + & pendDout(463 downto 432) -- len (32) + & getPKEY_i -- pkey (16) + & getSQPN_i -- qpn (24) + & WC_MAYBE_PAD_C; -- immDt+rkey2Inv (66) + + -- PendingWorkCompSQ = wcGenReqSQ(633) & workComp(222) & isSuccess & needNormal + dmaDin <= pendDout & workCompBuilt & isSuccess & needNormal; + + ---------------------------------------------------------------------- + -- waitDmaDoneSQ guard helpers (from dmaDout : PendingWorkCompSQ) + -- isWorkCompSuccess=[1] wcWaitDmaResp = wcGenReqSQ[31] = [255] + ---------------------------------------------------------------------- + dmaIsSuccess := dmaDout(1); + dmaWaitResp := dmaDout(255); + if (dmaIsSuccess = '1' and dmaWaitResp = '1') then + waitDmaCond := '1'; + else + waitDmaCond := '0'; + end if; + + ---------------------------------------------------------------------- + -- genWorkCompSQ / errFlushSQ datapath (from genDout : PendingWorkCompSQ) + -- workComp=[223:2] isWorkCompSuccess=[1] needWorkCompWhenNormal=[0] + ---------------------------------------------------------------------- + genWorkComp := genDout(223 downto 2); + genIsSuccess := genDout(1); + genNeedNormal := genDout(0); + -- errFlushWC = workComp with flags->NO_FLAGS, status->WR_FLUSH_ERR + -- workComp slice: [221:150]=id|opcode, [149:143]=flags, [142:138]=status, + -- [137:0]=len|pkey|qpn|immDt|rkey2Inv + errFlushWC := genWorkComp(221 downto 150) + & WC_NO_FLAGS_C + & WC_WR_FLUSH_ERR_C + & genWorkComp(137 downto 0); + + ---------------------------------------------------------------------- + -- Pipeline rules (conflict_free; concurrent datapaths). All gated off + -- while isReset (resetAndClear dominates, clearing the FIFOs). + ---------------------------------------------------------------------- + if (isReset_i = '0') then + + -- recvWorkCompGenReqSQ (rows 3-4): input mux into U_PendingWorkCompQ4SQ + if ((inNormalState or inErrorState) and pendNotFull = '1') then + if (reqGenInValid_i = '1') then + reqGenInDeq_o <= '1'; + pendWrEn <= '1'; + pendDin <= reqGenInData_i; + elsif (respHandleInValid_i = '1') then + respHandleInDeq_o <= '1'; + pendWrEn <= '1'; + pendDin <= respHandleInData_i; + end if; + end if; + + -- genPendingWorkCompSQ (row 5): U_PendingWorkCompQ4SQ -> U_DmaWaitingQ + if ((inNormalState or inErrorState) and pendValid = '1' and dmaNotFull = '1') then + pendRdEn <= '1'; + dmaWrEn <= '1'; + -- dmaDin already built above + end if; + + -- U_DmaWaitingQ -> U_GenWorkCompQ : waitDmaDoneSQ (NORMAL) / noDmaWaitSQ (ERR) + -- (mutually exclusive by mode; share dmaRdEn / genWrEn / genDin) + if (inNormalState and dmaValid = '1' and genNotFull = '1' and + (waitDmaCond = '0' or payloadConRespValid_i = '1')) then + -- waitDmaDoneSQ + dmaRdEn <= '1'; + genWrEn <= '1'; + genDin <= dmaDout; -- PendingWorkCompSQ pass-through + if (waitDmaCond = '1') then + payloadConRespGetEn_o <= '1'; -- conditional .get (deq DMA resp) + end if; + elsif (inErrorState and dmaValid = '1' and genNotFull = '1') then + -- noDmaWaitSQ (no DMA wait in error) + dmaRdEn <= '1'; + genWrEn <= '1'; + genDin <= dmaDout; + end if; + + -- U_GenWorkCompQ -> U_WorkCompOutQ4SQ : genWorkCompSQ (NORMAL) / errFlushSQ (ERR) + if (inNormalState and genValid = '1') then + -- genWorkCompSQ: enq wanted when (success && needNormal) || !success + if (genIsSuccess = '1') then + genEnqWanted := genNeedNormal; + else + genEnqWanted := '1'; + end if; + + if (genEnqWanted = '0' or outNotFull = '1') then + genRdEn <= '1'; -- deq genWorkCompQ + if (genEnqWanted = '1') then + outWrEn <= '1'; + outDin <= genWorkComp; -- WorkComp as-is + end if; + if (genIsSuccess = '0') then + -- enter ERR_FLUSH; latch first-partial-ACK context + v.state := WC_GEN_ST_ERR_FLUSH_S; + if (genDout(254 downto 253) = WC_REQ_PART_ACK_C) then + v.isFirstErrPartialAckWorkReq := '1'; + else + v.isFirstErrPartialAckWorkReq := '0'; + end if; + v.firstErrPartialAckWorkReqId := genDout(856 downto 793); -- wr.id + end if; + end if; + + elsif (inErrorState and genValid = '1') then + -- errFlushSQ: drop the first full-ACK after a partial-ACK error; + -- otherwise emit errFlushWC. enq wanted = NOT isFirstErrPartialAck. + genEnqWanted := not r.isFirstErrPartialAckWorkReq; + if (genEnqWanted = '0' or outNotFull = '1') then + genRdEn <= '1'; -- deq genWorkCompQ + if (r.isFirstErrPartialAckWorkReq = '1') then + v.isFirstErrPartialAckWorkReq := '0'; -- skip enq, clear flag + else + outWrEn <= '1'; + outDin <= errFlushWC; + end if; + end if; + end if; + + -- discardPayloadConRespSQ (row 10, ERR): drain payloadConRespPort. + -- Mutually exclusive with waitDmaDoneSQ's getEn by mode. + if (inErrorState and payloadConRespValid_i = '1') then + payloadConRespGetEn_o <= '1'; + end if; + + -- start (row 2): STOP -> NORMAL on isRTS + if (isRTS_i = '1' and r.state = WC_GEN_ST_STOP_S) then + v.state := WC_GEN_ST_NORMAL_S; + end if; + + end if; + + -- resetAndClear (row 1, highest priority): force STOP; FIFOs cleared via fifoClr + if (isReset_i = '1') then + v.state := WC_GEN_ST_STOP_S; + end if; + + -- structural synchronous reset (dominates; matches mkReg STOP power-on) + if (rst = '1') then + v := REG_INIT_C; + end if; + + rin <= v; + end process comb; + + --------------------------------------------------------------------------- + -- Sequential process + --------------------------------------------------------------------------- + seq : process (clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process seq; + + --------------------------------------------------------------------------- + -- Simulation-only assertions (no synthesizable effect; BSV immAssert): + -- 1. genPendingWorkCompSQ: maybeWorkComp must be Valid (mapped opcode). + -- 2. waitDmaDoneSQ: when getting a DMA resp, its psn must match triggerPSN. + -- 3. errFlushSQ: wcReqType must be FULL_ACK; when dropping the first + -- partial-ACK WC, wr.id must match firstErrPartialAckWorkReqId. + -- (cf. OQ-FSM-WCGSQ-03 / OQ-FSM-APS-03 translate_off treatment.) + --------------------------------------------------------------------------- + -- pragma translate_off + chk : process (clk) is + begin + if rising_edge(clk) then + if (rst = '0' and isReset_i = '0') then + -- (1) genPendingWorkCompSQ opcode mapping must be Valid + if (((isStableRTS_i = '1' and r.state = WC_GEN_ST_NORMAL_S) or + (isERR_i = '1' or r.state = WC_GEN_ST_ERR_FLUSH_S)) and + pendValid = '1' and dmaNotFull = '1') then + assert (pendDout(568 downto 565) /= "1011" and -- DRIVER1 + pendDout(568 downto 565) /= "1100" and -- RDMA_READ_RESP + pendDout(568 downto 565) /= "1101" and -- (reserved 13) + pendDout(568 downto 565) /= "1110" and -- FLUSH + pendDout(568 downto 565) /= "1111") -- ATOMIC_WRITE + report "WorkCompGenSq: genPendingWorkCompSQ maybeWorkComp must be Valid" + severity warning; + end if; + -- (2) waitDmaDoneSQ DMA-response PSN match (NORMAL, conditional get) + if (isStableRTS_i = '1' and r.state = WC_GEN_ST_NORMAL_S and + dmaValid = '1' and genNotFull = '1' and + dmaDout(1) = '1' and dmaDout(255) = '1' and + payloadConRespValid_i = '1') then + assert (payloadConRespData_i(24 downto 1) = dmaDout(252 downto 229)) + report "WorkCompGenSq: waitDmaDoneSQ dmaWriteResp.psn /= wcGenReqSQ.triggerPSN" + severity error; + end if; + -- (3) errFlushSQ wcReqType must be FULL_ACK + if ((isERR_i = '1' or r.state = WC_GEN_ST_ERR_FLUSH_S) and genValid = '1') then + assert (genDout(254 downto 253) = "00") -- WC_REQ_TYPE_FULL_ACK + report "WorkCompGenSq: errFlushSQ wcReqType must be FULL_ACK" + severity error; + if (r.isFirstErrPartialAckWorkReq = '1') then + assert (genDout(856 downto 793) = r.firstErrPartialAckWorkReqId) + report "WorkCompGenSq: errFlushSQ wr.id /= firstErrPartialAckWorkReqId" + severity error; + end if; + end if; + end if; + end if; + end process chk; + -- pragma translate_on + +end architecture rtl; diff --git a/ethernet/RoCEv2/rtl/WorkReqAndRecvReqDispatcher.vhd b/ethernet/RoCEv2/rtl/WorkReqAndRecvReqDispatcher.vhd new file mode 100644 index 0000000000..5a4ce02c90 --- /dev/null +++ b/ethernet/RoCEv2/rtl/WorkReqAndRecvReqDispatcher.vhd @@ -0,0 +1,251 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- Stateless per-QP demultiplexer (NO state machine, NO RegType). Two +-- independent, conflict-free BSV rules each dequeue one request from an input +-- PipeOut and enqueue it, unchanged, into one of MAX_QP per-QP output FIFOs +-- selected by the request's sqpn: +-- +-- dispatchWorkReq : workReqPipeIn -> U_WorkReqOutVec[getIndexQP(wr.sqpn)] +-- dispatchRecvReq : recvReqPipeIn -> U_RecvReqOutVec[getIndexQP(rr.sqpn)] +-- +-- getIndexQP(qpn) = unpack(truncateLSB(qpn)) = the top QP_INDEX_WIDTH bits of +-- the 24-bit sqpn (QP_INDEX_WIDTH = TLog#(MAX_QP) = 2 for MAX_QP = 4). +-- +-- Because the module has no mkReg/mkRegU (state_registers: []), there is no +-- sequential FSM state and therefore no RegType / two-process FSM here. All +-- storage lives in the 2*MAX_QP surf.Fifo instances; the routing is pure +-- combinational Mealy logic (deq + one-hot wrEn demux), committed on the next +-- rising edge by each FIFO's own register. This is exactly what the Stage-3 +-- FSM spec directs ("emit combinational routing + the FIFO instances, with an +-- empty/absent RegType"). +-- +-- Struct widths traced from src-bsv (first field at MSB, BSV pack convention): +-- WorkReq = 601 b ; sqpn field occupies bits [303:280] -> route = [303:302] +-- RecvReq = 216 b ; sqpn field occupies bits [23:0] -> route = [23:22] +-- +-- Per-QP output vectors are flattened buses: element i of an N-wide bus +-- occupies ((i+1)*W-1 downto i*W). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library surf; +use surf.StdRtlPkg.all; + +entity WorkReqAndRecvReqDispatcher is + generic ( + TPD_G : time := 1 ns; + MAX_QP_G : positive := 4; -- Settings.bsv: typedef 4 MAX_QP + EN_TX_G : boolean := true; -- false = no requester: skip WorkReq FIFOs + EN_RX_G : boolean := true); -- false = no responder: skip RecvReq FIFOs + port ( + clk : in sl; + rst : in sl; -- active-high synchronous reset + + -- workReqPipeIn : PipeOut#(WorkReq) (WorkReq = 601 b) + workReqValid_i : in sl; -- notEmpty + workReqData_i : in slv(600 downto 0); -- first (WorkReq packed) + workReqDeq_o : out sl; -- deq + + -- recvReqPipeIn : PipeOut#(RecvReq) (RecvReq = 216 b) + recvReqValid_i : in sl; -- notEmpty + recvReqData_i : in slv(215 downto 0); -- first (RecvReq packed) + recvReqDeq_o : out sl; -- deq + + -- workReqPipeOut : Vector#(MAX_QP, PipeOut#(WorkReq)) (read faces) + workReqOutValid_o : out slv(MAX_QP_G-1 downto 0); -- per-QP notEmpty + workReqOutData_o : out slv(MAX_QP_G*601-1 downto 0); -- per-QP first + workReqOutRdEn_i : in slv(MAX_QP_G-1 downto 0); -- per-QP deq (downstream) + + -- recvReqPipeOut : Vector#(MAX_QP, PipeOut#(RecvReq)) (read faces) + recvReqOutValid_o : out slv(MAX_QP_G-1 downto 0); -- per-QP notEmpty + recvReqOutData_o : out slv(MAX_QP_G*216-1 downto 0); -- per-QP first + recvReqOutRdEn_i : in slv(MAX_QP_G-1 downto 0)); -- per-QP deq (downstream) +end entity WorkReqAndRecvReqDispatcher; + +architecture rtl of WorkReqAndRecvReqDispatcher is + + -- Struct widths (Headers.bsv / DataTypes.bsv traced) + constant WORK_REQ_WIDTH_C : integer := 601; + constant RECV_REQ_WIDTH_C : integer := 216; + constant QPN_WIDTH_C : integer := 24; -- Headers.bsv QPN_WIDTH + + -- getIndexQP = top TLog#(MAX_QP) bits of sqpn (UInt#(QP_INDEX_WIDTH)) + constant QP_INDEX_WIDTH_C : integer := log2(MAX_QP_G); + + -- sqpn field LSB position within each packed struct word + constant WR_SQPN_LOW_C : integer := 280; -- WorkReq.sqpn = [303:280] + constant RR_SQPN_LOW_C : integer := 0; -- RecvReq.sqpn = [23:0] + + -- surf.Fifo geometry (match project convention: FWFT sync block, min depth) + constant FIFO_ADDR_WIDTH_C : integer := 4; -- depth = 16 entries + + -- WorkReq routing / FIFO write-side nets + signal wrQpIdx : unsigned(QP_INDEX_WIDTH_C-1 downto 0); + signal workReqAccept : sl; -- rule dispatchWorkReq fires + signal workReqWrEn : slv(MAX_QP_G-1 downto 0); + signal workReqNotFull : slv(MAX_QP_G-1 downto 0); + + -- RecvReq routing / FIFO write-side nets + signal rrQpIdx : unsigned(QP_INDEX_WIDTH_C-1 downto 0); + signal recvReqAccept : sl; -- rule dispatchRecvReq fires + signal recvReqWrEn : slv(MAX_QP_G-1 downto 0); + signal recvReqNotFull : slv(MAX_QP_G-1 downto 0); + +begin + + --------------------------------------------------------------------------- + -- Compile-time guard: getIndexQP indexing assumes MAX_QP is a power of two + -- so that QP_INDEX_WIDTH = TLog#(MAX_QP) addresses exactly MAX_QP FIFOs. + -- isPowerOf2 (not 2**QP_INDEX_WIDTH_C = MAX_QP_G): SURF log2(1)=1 makes the + -- power form fail at MAX_QP_G=1, where the index is forced to 0 instead. + --------------------------------------------------------------------------- + assert isPowerOf2(MAX_QP_G) + report "WorkReqAndRecvReqDispatcher: MAX_QP_G must be a power of two" + severity failure; + + --------------------------------------------------------------------------- + -- dispatchWorkReq : combinational QP-index demux (Mealy) + -- qpIndex = top QP_INDEX_WIDTH bits of WorkReq.sqpn + -- accept (deq) = input notEmpty AND selected output FIFO not_full + -- wrEn[i] = accept AND (qpIndex = i) (one-hot enq) + --------------------------------------------------------------------------- + -- forced to 0 at MAX_QP_G=1 (0-bit BSV index, MetaData.bsv:349) + wrQpIdx <= unsigned(ite(MAX_QP_G > 1, + workReqData_i(WR_SQPN_LOW_C + QPN_WIDTH_C - 1 downto + WR_SQPN_LOW_C + QPN_WIDTH_C - QP_INDEX_WIDTH_C), + "0")); + + workReqAccept <= workReqValid_i and workReqNotFull(to_integer(wrQpIdx)); + workReqDeq_o <= workReqAccept; + + GEN_WR : for i in 0 to MAX_QP_G-1 generate + workReqWrEn(i) <= workReqAccept when (to_integer(wrQpIdx) = i) else '0'; + end generate GEN_WR; + + --------------------------------------------------------------------------- + -- dispatchRecvReq : independent, conflict-free with dispatchWorkReq + --------------------------------------------------------------------------- + -- forced to 0 at MAX_QP_G=1 (0-bit BSV index, MetaData.bsv:349) + rrQpIdx <= unsigned(ite(MAX_QP_G > 1, + recvReqData_i(RR_SQPN_LOW_C + QPN_WIDTH_C - 1 downto + RR_SQPN_LOW_C + QPN_WIDTH_C - QP_INDEX_WIDTH_C), + "0")); + + recvReqAccept <= recvReqValid_i and recvReqNotFull(to_integer(rrQpIdx)); + recvReqDeq_o <= recvReqAccept; + + GEN_RR : for i in 0 to MAX_QP_G-1 generate + recvReqWrEn(i) <= recvReqAccept when (to_integer(rrQpIdx) = i) else '0'; + end generate GEN_RR; + + --------------------------------------------------------------------------- + -- U_WorkReqOutVec[i] : surf.Fifo (BSV replicateM(mkFIFOF) of WorkReq) + -- src : base/fifo/rtl/Fifo.vhd + -- wr : dispatchWorkReq (one-hot) rd : exported PipeOut read face + --------------------------------------------------------------------------- + -- Pruned when EN_TX_G=false (upstream ties workReqValid_i='0', so the + -- routing glue above constant-folds; notFull tied '1' keeps it inert). + GEN_NO_WORK_FIFO : if not EN_TX_G generate + workReqOutValid_o <= (others => '0'); + workReqOutData_o <= (others => '0'); + workReqNotFull <= (others => '1'); + end generate GEN_NO_WORK_FIFO; + + GEN_WORK_FIFO : if EN_TX_G generate + GEN_WORK_FIFO_VEC : for i in 0 to MAX_QP_G-1 generate + U_WorkReqOutVec : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => WORK_REQ_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C) + port map ( + rst => rst, + wr_clk => clk, + wr_en => workReqWrEn(i), + din => workReqData_i, + not_full => workReqNotFull(i), + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => workReqOutRdEn_i(i), + dout => workReqOutData_o((i+1)*WORK_REQ_WIDTH_C-1 downto i*WORK_REQ_WIDTH_C), + valid => workReqOutValid_o(i), + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + end generate GEN_WORK_FIFO_VEC; + end generate GEN_WORK_FIFO; + + --------------------------------------------------------------------------- + -- U_RecvReqOutVec[i] : surf.Fifo (BSV replicateM(mkFIFOF) of RecvReq) + -- src : base/fifo/rtl/Fifo.vhd + -- wr : dispatchRecvReq (one-hot) rd : exported PipeOut read face + --------------------------------------------------------------------------- + -- Pruned when EN_RX_G=false (upstream ties recvReqValid_i='0'). + GEN_NO_RECV_FIFO : if not EN_RX_G generate + recvReqOutValid_o <= (others => '0'); + recvReqOutData_o <= (others => '0'); + recvReqNotFull <= (others => '1'); + end generate GEN_NO_RECV_FIFO; + + GEN_RECV_FIFO : if EN_RX_G generate + GEN_RECV_FIFO_VEC : for i in 0 to MAX_QP_G-1 generate + U_RecvReqOutVec : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', + RST_ASYNC_G => false, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "block", + DATA_WIDTH_G => RECV_REQ_WIDTH_C, + ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C) + port map ( + rst => rst, + wr_clk => clk, + wr_en => recvReqWrEn(i), + din => recvReqData_i, + not_full => recvReqNotFull(i), + full => open, + wr_ack => open, + overflow => open, + prog_full => open, + almost_full => open, + wr_data_count => open, + rd_clk => clk, + rd_en => recvReqOutRdEn_i(i), + dout => recvReqOutData_o((i+1)*RECV_REQ_WIDTH_C-1 downto i*RECV_REQ_WIDTH_C), + valid => recvReqOutValid_o(i), + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open, + rd_data_count => open); + end generate GEN_RECV_FIFO_VEC; + end generate GEN_RECV_FIFO; + +end architecture rtl; diff --git a/python/surf/ethernet/roce/_RoceEngine.py b/python/surf/ethernet/roce/_RoceEngine.py deleted file mode 100644 index 9ad9a74f32..0000000000 --- a/python/surf/ethernet/roce/_RoceEngine.py +++ /dev/null @@ -1,50 +0,0 @@ -#----------------------------------------------------------------------------- -# This file is part of the 'SLAC Firmware Standard Library'. It is subject to -# the license terms in the LICENSE.txt file found in the top-level directory -# of this distribution and at: -# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -# No part of the 'SLAC Firmware Standard Library', including this file, may be -# copied, modified, propagated, or distributed except according to the terms -# contained in the LICENSE.txt file. -#----------------------------------------------------------------------------- - -import pyrogue as pr - -class RoceEngine(pr.Device): - def __init__( self, - **kwargs): - super().__init__(**kwargs) - - self.add(pr.RemoteVariable( - name = 'SendMetaData', - description = 'Trigger sending RoCE metadata to the remote peer', - offset = 0xF00, - bitSize = 1, - mode = 'RW', - )) - - self.add(pr.RemoteVariable( - name = 'MetaDataTx', - description = 'RoCE transmit metadata payload for queue pair setup', - offset = 0xF04, - bitSize = 303, - mode = 'RW', - )) - - - self.add(pr.RemoteVariable( - name = 'RecvMetaData', - description = 'Indicates received RoCE metadata is available', - offset = 0xF00, - bitSize = 1, - bitOffset = 1, - mode = 'RO', - )) - - self.add(pr.RemoteVariable( - name = 'MetaDataRx', - description = 'RoCE received metadata payload from remote peer', - offset = 0xF2C, - bitSize = 276, - mode = 'RO', - )) diff --git a/python/surf/ethernet/roce/_RoceMetaDataAxil.py b/python/surf/ethernet/roce/_RoceMetaDataAxil.py new file mode 100644 index 0000000000..70597b0d74 --- /dev/null +++ b/python/surf/ethernet/roce/_RoceMetaDataAxil.py @@ -0,0 +1,650 @@ +#----------------------------------------------------------------------------- +# Title : PyRogue RoceMetaDataAxil +#----------------------------------------------------------------------------- +# Description: +# PyRogue register map for out/04-vhdl/RoceMetaDataAxil.vhd — the AXI-Lite +# bridge to the RoCEv2 TransportLayer MetaData server (also instanced inside +# out/04-vhdl/TransportLayerAxi.vhd on its axil* ports). +# +# BSV struct refs: src-bsv/MetaData.bsv (MetaDataReq/Resp, ReqPD/RespPD, +# ReqMR/RespMR), src-bsv/Controller.bsv (ReqQP/RespQP), src-bsv/DataTypes.bsv +# (AttrQP, QpCapacity, QpInitAttr). +# +# Protocol: program the request bank selected by Control.ReqType, then issue +# Go (single write to CONTROL; GO self-clears). Busy rises until the response +# is captured; Done then rises (cleared on the next accepted Go) and +# mdDoneIrq pulses one clock. Go while Busy is ignored and sets the sticky +# Err bit (cleared on the next accepted Go). Poll Done, then check +# RespSuccess and read the Resp* bank. +#----------------------------------------------------------------------------- + +import pyrogue as pr + + +class RoceMetaDataAxil(pr.Device): + def __init__(self, **kwargs): + super().__init__(**kwargs) + + ############################## + # Control / status (0x000) + ############################## + + self.add(pr.RemoteVariable( + name = 'ReqType', + description = 'Request bank issued by Go (CONTROL[2:1])', + offset = 0x000, + bitSize = 2, + bitOffset = 1, + base = pr.UInt, + mode = 'RW', + enum = { + 0: 'PD', + 1: 'MR', + 2: 'QP', + }, + )) + + self.add(pr.RemoteCommand( + name = 'Go', + description = 'Issue the request selected by ReqType (CONTROL[0], self-clearing strobe)', + offset = 0x000, + bitSize = 1, + bitOffset = 0, + base = pr.UInt, + function = pr.RemoteCommand.touchOne, + )) + + self.add(pr.RemoteVariable( + name = 'Done', + description = 'Response captured (cleared on the next accepted Go)', + offset = 0x004, + bitSize = 1, + bitOffset = 0, + base = pr.Bool, + mode = 'RO', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'Busy', + description = 'Request in flight', + offset = 0x004, + bitSize = 1, + bitOffset = 1, + base = pr.Bool, + mode = 'RO', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'Err', + description = 'Sticky: Go was issued while Busy (that Go was ignored)', + offset = 0x004, + bitSize = 1, + bitOffset = 2, + base = pr.Bool, + mode = 'RO', + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = 'RespTag', + description = 'Tag of the captured response (STATUS[4:3])', + offset = 0x004, + bitSize = 2, + bitOffset = 3, + base = pr.UInt, + mode = 'RO', + enum = { + 0: 'PD', + 1: 'MR', + 2: 'QP', + }, + )) + + self.add(pr.RemoteVariable( + name = 'RespSuccess', + description = 'Captured response success flag (STATUS[5])', + offset = 0x004, + bitSize = 1, + bitOffset = 5, + base = pr.Bool, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'Version', + description = 'Bridge version (VERSION[7:0])', + offset = 0x008, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'MaxQp', + description = 'MAX_QP_G generic readback (VERSION[15:8])', + offset = 0x008, + bitSize = 8, + bitOffset = 8, + base = pr.UInt, + mode = 'RO', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'Scratch', + description = 'Scratchpad register', + offset = 0x00C, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + ############################## + # PD request bank (ReqPD, 0x100) + ############################## + + self.add(pr.RemoteVariable( + name = 'PdAllocOrNot', + description = 'ReqPD.allocOrNot: 1 = allocate PD, 0 = deallocate', + offset = 0x100, + bitSize = 1, + bitOffset = 0, + base = pr.Bool, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'PdKey', + description = 'ReqPD.pdKey', + offset = 0x104, + bitSize = 31, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'PdHandler', + description = 'ReqPD.pdHandler (for deallocate)', + offset = 0x108, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + ############################## + # MR request bank (ReqMR, 0x200) + ############################## + + self.add(pr.RemoteVariable( + name = 'MrAllocOrNot', + description = 'ReqMR.allocOrNot: 1 = register MR, 0 = deregister', + offset = 0x200, + bitSize = 1, + bitOffset = 0, + base = pr.Bool, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MrLkeyOrNot', + description = 'ReqMR.lkeyOrNot', + offset = 0x200, + bitSize = 1, + bitOffset = 1, + base = pr.Bool, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MrLAddr', + description = 'ReqMR.laddr (64-bit, spans 0x204 LO / 0x208 HI)', + offset = 0x204, + bitSize = 64, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MrLen', + description = 'ReqMR.len', + offset = 0x20C, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MrAccFlags', + description = 'ReqMR.accFlags (IBV access flags)', + offset = 0x210, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MrPdHandler', + description = 'ReqMR.pdHandler', + offset = 0x214, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MrLkeyPart', + description = 'ReqMR.lkeyPart (key material for the allocated lkey)', + offset = 0x218, + bitSize = 25, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MrRkeyPart', + description = 'ReqMR.rkeyPart (key material for the allocated rkey)', + offset = 0x21C, + bitSize = 25, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MrLkey', + description = 'ReqMR.lkey (for deregister)', + offset = 0x220, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'MrRkey', + description = 'ReqMR.rkey (for deregister)', + offset = 0x224, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + ############################## + # QP request bank (ReqQP, 0x300) + ############################## + + self.add(pr.RemoteVariable( + name = 'QpReqType', + description = 'ReqQP.qpReqType (QP_CTRL[1:0])', + offset = 0x300, + bitSize = 2, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + enum = { + 0: 'Create', + 1: 'Destroy', + 2: 'Modify', + 3: 'Query', + }, + )) + + self.add(pr.RemoteVariable( + name = 'QpState', + description = 'AttrQP.qpState, target state for MODIFY (IBV encoding; QP_CTRL[5:2])', + offset = 0x300, + bitSize = 4, + bitOffset = 2, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpPmtu', + description = 'AttrQP.pmtu (IBV encoding; QP_CTRL[8:6])', + offset = 0x300, + bitSize = 3, + bitOffset = 6, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpType', + description = 'QpInitAttr.qpType (IBV encoding, RC=2; QP_CTRL[12:9])', + offset = 0x300, + bitSize = 4, + bitOffset = 9, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpSqSigAll', + description = 'QpInitAttr.sqSigAll (QP_CTRL[13])', + offset = 0x300, + bitSize = 1, + bitOffset = 13, + base = pr.Bool, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpPdHandler', + description = 'ReqQP.pdHandler', + offset = 0x304, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpQpn', + description = 'ReqQP.qpn (queue pair number to operate on)', + offset = 0x308, + bitSize = 24, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpAttrMask', + description = 'ReqQP.qpAttrMask (IBV attribute mask for MODIFY)', + offset = 0x30C, + bitSize = 26, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpQkey', + description = 'AttrQP.qkey', + offset = 0x310, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpRqPsn', + description = 'AttrQP.rqPSN (expected receive PSN)', + offset = 0x314, + bitSize = 24, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpSqPsn', + description = 'AttrQP.sqPSN (send queue PSN)', + offset = 0x318, + bitSize = 24, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpDqpn', + description = 'AttrQP.dqpn (destination QPN)', + offset = 0x31C, + bitSize = 24, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpAccessFlags', + description = 'AttrQP.qpAccessFlags (IBV access flags)', + offset = 0x320, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpPkeyIndex', + description = 'AttrQP.pkeyIndex', + offset = 0x324, + bitSize = 16, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpMaxRdAtomic', + description = 'AttrQP.maxReadAtomic (outstanding as requester)', + offset = 0x328, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'QpMaxDestRdAtomic', + description = 'AttrQP.maxDestReadAtomic (outstanding as responder)', + offset = 0x32C, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'QpMinRnrTimer', + description = 'AttrQP.minRnrTimer (IBV RNR NAK timer encoding)', + offset = 0x330, + bitSize = 5, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpTimeout', + description = 'AttrQP.timeout (IBV local ACK timeout encoding)', + offset = 0x334, + bitSize = 5, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpRetryCnt', + description = 'AttrQP.retryCnt (transport retry count)', + offset = 0x338, + bitSize = 3, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'QpRnrRetry', + description = 'AttrQP.rnrRetry (RNR retry count, 7 = infinite)', + offset = 0x33C, + bitSize = 3, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'QpCurState', + description = 'AttrQP.curQpState (current state hint for MODIFY)', + offset = 0x340, + bitSize = 4, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + )) + + self.add(pr.RemoteVariable( + name = 'QpMaxSendWr', + description = 'QpCapacity.maxSendWR', + offset = 0x344, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'QpMaxRecvWr', + description = 'QpCapacity.maxRecvWR', + offset = 0x348, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'QpMaxSendSge', + description = 'QpCapacity.maxSendSGE', + offset = 0x34C, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'QpMaxRecvSge', + description = 'QpCapacity.maxRecvSGE', + offset = 0x350, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'QpMaxInlineData', + description = 'QpCapacity.maxInlineData', + offset = 0x354, + bitSize = 8, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + disp = '{:d}', + )) + + self.add(pr.RemoteVariable( + name = 'QpSqDraining', + description = 'AttrQP.sqDraining', + offset = 0x358, + bitSize = 1, + bitOffset = 0, + base = pr.Bool, + mode = 'RW', + )) + + ############################## + # Response bank (RO, 0x400; captured on completion) + ############################## + + self.add(pr.RemoteVariable( + name = 'RespStatusSuccess', + description = 'Captured response success (mirrors STATUS[5])', + offset = 0x400, + bitSize = 1, + bitOffset = 0, + base = pr.Bool, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'RespStatusTag', + description = 'Captured response tag (mirrors STATUS[4:3])', + offset = 0x400, + bitSize = 2, + bitOffset = 1, + base = pr.UInt, + mode = 'RO', + enum = { + 0: 'PD', + 1: 'MR', + 2: 'QP', + }, + )) + + self.add(pr.RemoteVariable( + name = 'RespPdHandler', + description = 'RespPD.pdHandler (allocated PD handle)', + offset = 0x404, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'RespPdKey', + description = 'RespPD.pdKey echo', + offset = 0x408, + bitSize = 31, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'RespMrLkey', + description = 'RespMR.lkey (allocated local key)', + offset = 0x40C, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'RespMrRkey', + description = 'RespMR.rkey (allocated remote key)', + offset = 0x410, + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'RespQpQpn', + description = 'RespQP.qpn (created queue pair number)', + offset = 0x414, + bitSize = 24, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) diff --git a/python/surf/ethernet/roce/__init__.py b/python/surf/ethernet/roce/__init__.py index f5209a15ec..19f1d754cb 100644 --- a/python/surf/ethernet/roce/__init__.py +++ b/python/surf/ethernet/roce/__init__.py @@ -1,10 +1 @@ -############################################################################## -## This file is part of 'SLAC Firmware Standard Library'. -## It is subject to the license terms in the LICENSE.txt file found in the -## top-level directory of this distribution and at: -## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -## No part of 'SLAC Firmware Standard Library', including this file, -## may be copied, modified, propagated, or distributed except according to -## the terms contained in the LICENSE.txt file. -############################################################################## -from surf.ethernet.roce._RoceEngine import * +from surf.ethernet.roce._RoceMetaDataAxil import * From ff16124f01aff9a7975b49b0d5d86479ae585150 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Wed, 8 Jul 2026 15:07:23 +0200 Subject: [PATCH 2/8] removing blue-rdma files --- ethernet/RoCEv2/blue-rdma/LICENSE | 340 - .../RoCEv2/blue-rdma/mkAxisTransportLayer.v | 1096 - ethernet/RoCEv2/blue-rdma/mkQP.v | 25463 ---------------- ethernet/RoCEv2/blue-rdma/mkTransportLayer.v | 15640 ---------- 4 files changed, 42539 deletions(-) delete mode 100644 ethernet/RoCEv2/blue-rdma/LICENSE delete mode 100644 ethernet/RoCEv2/blue-rdma/mkAxisTransportLayer.v delete mode 100644 ethernet/RoCEv2/blue-rdma/mkQP.v delete mode 100644 ethernet/RoCEv2/blue-rdma/mkTransportLayer.v diff --git a/ethernet/RoCEv2/blue-rdma/LICENSE b/ethernet/RoCEv2/blue-rdma/LICENSE deleted file mode 100644 index 1f963da0d1..0000000000 --- a/ethernet/RoCEv2/blue-rdma/LICENSE +++ /dev/null @@ -1,340 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc., - 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. 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Of course, the commands you use may -be called something other than `show w' and `show c'; they could even be -mouse-clicks or menu items--whatever suits your program. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the program, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the program - `Gnomovision' (which makes passes at compilers) written by James Hacker. - - , 1 April 1989 - Ty Coon, President of Vice - -This General Public License does not permit incorporating your program into -proprietary programs. If your program is a subroutine library, you may -consider it more useful to permit linking proprietary applications with the -library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. - diff --git a/ethernet/RoCEv2/blue-rdma/mkAxisTransportLayer.v b/ethernet/RoCEv2/blue-rdma/mkAxisTransportLayer.v deleted file mode 100644 index dab26d35f2..0000000000 --- a/ethernet/RoCEv2/blue-rdma/mkAxisTransportLayer.v +++ /dev/null @@ -1,1096 +0,0 @@ -/* - * ------------------------------------------------------------------- - * This Verilog file has been automatically generated from a core originally written - * in Bluespec SystemVerilog (BSV). The original source code can be found at: - * - * Repository: https://github.com/datenlord/blue-rdma - * Author: DatenLord (https://datenlord.github.io/) - * - * Modifications have been made to the original core before compiling the Verilog. - * For any questions or further information regarding the modifications, please - * feel free to contact me. - * - * Modifications by: Filippo Marini - * Email: filippo.marini@pd.infn.it - * ------------------------------------------------------------------- - */ -// -// Generated by Bluespec Compiler, version 2023.01 (build 52adafa) -// -// -// -// Ports: -// Name I/O size props -// s_work_req_ready O 1 reg -// s_data_stream_tready O 1 reg -// m_data_stream_tvalid O 1 reg -// m_data_stream_tdata O 256 reg -// m_data_stream_tkeep O 32 reg -// m_data_stream_tfirst O 1 reg -// m_data_stream_tlast O 1 reg -// m_work_comp_sq_valid O 1 reg -// m_work_comp_sq_id O 64 reg -// m_work_comp_sq_op_code O 8 reg -// m_work_comp_sq_flags O 7 reg -// m_work_comp_sq_status O 5 reg -// m_work_comp_sq_len O 32 reg -// m_work_comp_sq_pkey O 16 reg -// m_work_comp_sq_qpn O 24 reg -// m_work_comp_sq_imm_dt O 33 reg -// m_work_comp_sq_rkey_to_inv O 33 reg -// s_meta_data_tready O 1 reg -// m_meta_data_tvalid O 1 reg -// m_meta_data_tdata O 276 reg -// m_dma_read_valid O 1 reg -// m_dma_read_initiator O 4 reg -// m_dma_read_sqpn O 24 reg -// m_dma_read_wr_id O 64 reg -// m_dma_read_start_addr O 64 reg -// m_dma_read_len O 13 reg -// m_dma_read_mr_idx O 1 reg -// s_dma_read_ready O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// s_work_req_valid I 1 -// s_work_req_id I 64 reg -// s_work_req_op_code I 4 reg -// s_work_req_flags I 5 reg -// s_work_req_raddr I 64 reg -// s_work_req_rkey I 32 reg -// s_work_req_len I 32 reg -// s_work_req_laddr I 64 reg -// s_work_req_lkey I 32 reg -// s_work_req_sqpn I 24 reg -// s_work_req_solicited I 1 reg -// s_work_req_comp I 65 reg -// s_work_req_swap I 65 reg -// s_work_req_imm_dt I 33 reg -// s_work_req_rkey_to_inv I 33 reg -// s_work_req_srqn I 25 reg -// s_work_req_dqpn I 25 reg -// s_work_req_qkey I 33 reg -// s_data_stream_tvalid I 1 -// s_data_stream_tdata I 256 reg -// s_data_stream_tkeep I 32 reg -// s_data_stream_tfirst I 1 reg -// s_data_stream_tlast I 1 reg -// m_data_stream_tready I 1 -// m_work_comp_sq_ready I 1 -// s_meta_data_tvalid I 1 -// s_meta_data_tdata I 303 reg -// m_meta_data_tready I 1 -// m_dma_read_ready I 1 -// s_dma_read_valid I 1 -// s_dma_read_initiator I 4 reg -// s_dma_read_sqpn I 24 reg -// s_dma_read_wr_id I 64 reg -// s_dma_read_is_resp_err I 1 reg -// s_dma_read_data_stream I 290 reg -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkAxiSTransportLayer(CLK, - RST_N, - - s_work_req_valid, - s_work_req_id, - s_work_req_op_code, - s_work_req_flags, - s_work_req_raddr, - s_work_req_rkey, - s_work_req_len, - s_work_req_laddr, - s_work_req_lkey, - s_work_req_sqpn, - s_work_req_solicited, - s_work_req_comp, - s_work_req_swap, - s_work_req_imm_dt, - s_work_req_rkey_to_inv, - s_work_req_srqn, - s_work_req_dqpn, - s_work_req_qkey, - - s_work_req_ready, - - s_data_stream_tvalid, - s_data_stream_tdata, - s_data_stream_tkeep, - s_data_stream_tfirst, - s_data_stream_tlast, - - s_data_stream_tready, - - m_data_stream_tvalid, - - m_data_stream_tdata, - - m_data_stream_tkeep, - - m_data_stream_tfirst, - - m_data_stream_tlast, - - m_data_stream_tready, - - m_work_comp_sq_valid, - - m_work_comp_sq_id, - - m_work_comp_sq_op_code, - - m_work_comp_sq_flags, - - m_work_comp_sq_status, - - m_work_comp_sq_len, - - m_work_comp_sq_pkey, - - m_work_comp_sq_qpn, - - m_work_comp_sq_imm_dt, - - m_work_comp_sq_rkey_to_inv, - - m_work_comp_sq_ready, - - s_meta_data_tvalid, - s_meta_data_tdata, - - s_meta_data_tready, - - m_meta_data_tvalid, - - m_meta_data_tdata, - - m_meta_data_tready, - - m_dma_read_valid, - - m_dma_read_initiator, - - m_dma_read_sqpn, - - m_dma_read_wr_id, - - m_dma_read_start_addr, - - m_dma_read_len, - - m_dma_read_mr_idx, - - m_dma_read_ready, - - s_dma_read_valid, - s_dma_read_initiator, - s_dma_read_sqpn, - s_dma_read_wr_id, - s_dma_read_is_resp_err, - s_dma_read_data_stream, - - s_dma_read_ready); - input CLK; - input RST_N; - - // action method rawWorkReqIn_validData - input s_work_req_valid; - input [63 : 0] s_work_req_id; - input [3 : 0] s_work_req_op_code; - input [4 : 0] s_work_req_flags; - input [63 : 0] s_work_req_raddr; - input [31 : 0] s_work_req_rkey; - input [31 : 0] s_work_req_len; - input [63 : 0] s_work_req_laddr; - input [31 : 0] s_work_req_lkey; - input [23 : 0] s_work_req_sqpn; - input s_work_req_solicited; - input [64 : 0] s_work_req_comp; - input [64 : 0] s_work_req_swap; - input [32 : 0] s_work_req_imm_dt; - input [32 : 0] s_work_req_rkey_to_inv; - input [24 : 0] s_work_req_srqn; - input [24 : 0] s_work_req_dqpn; - input [32 : 0] s_work_req_qkey; - - // value method rawWorkReqIn_ready - output s_work_req_ready; - - // action method rawRdmaDataStreamIn_validData - input s_data_stream_tvalid; - input [255 : 0] s_data_stream_tdata; - input [31 : 0] s_data_stream_tkeep; - input s_data_stream_tfirst; - input s_data_stream_tlast; - - // value method rawRdmaDataStreamIn_ready - output s_data_stream_tready; - - // value method rawRdmaDataStreamOut_valid - output m_data_stream_tvalid; - - // value method rawRdmaDataStreamOut_data - output [255 : 0] m_data_stream_tdata; - - // value method rawRdmaDataStreamOut_byteEn - output [31 : 0] m_data_stream_tkeep; - - // value method rawRdmaDataStreamOut_isFirst - output m_data_stream_tfirst; - - // value method rawRdmaDataStreamOut_isLast - output m_data_stream_tlast; - - // action method rawRdmaDataStreamOut_ready - input m_data_stream_tready; - - // value method rawWorkCompSQOut_valid - output m_work_comp_sq_valid; - - // value method rawWorkCompSQOut_id - output [63 : 0] m_work_comp_sq_id; - - // value method rawWorkCompSQOut_opcode - output [7 : 0] m_work_comp_sq_op_code; - - // value method rawWorkCompSQOut_flags - output [6 : 0] m_work_comp_sq_flags; - - // value method rawWorkCompSQOut_status - output [4 : 0] m_work_comp_sq_status; - - // value method rawWorkCompSQOut_len - output [31 : 0] m_work_comp_sq_len; - - // value method rawWorkCompSQOut_pKey - output [15 : 0] m_work_comp_sq_pkey; - - // value method rawWorkCompSQOut_qpn - output [23 : 0] m_work_comp_sq_qpn; - - // value method rawWorkCompSQOut_immDt - output [32 : 0] m_work_comp_sq_imm_dt; - - // value method rawWorkCompSQOut_rkey2Inv - output [32 : 0] m_work_comp_sq_rkey_to_inv; - - // action method rawWorkCompSQOut_ready - input m_work_comp_sq_ready; - - // action method rawMetaDataStreamIn_validData - input s_meta_data_tvalid; - input [302 : 0] s_meta_data_tdata; - - // value method rawMetaDataStreamIn_ready - output s_meta_data_tready; - - // value method rawMetaDataStreamOut_valid - output m_meta_data_tvalid; - - // value method rawMetaDataStreamOut_metaDataResp - output [275 : 0] m_meta_data_tdata; - - // action method rawMetaDataStreamOut_ready - input m_meta_data_tready; - - // value method rawDmaReadCltStreamOut_valid - output m_dma_read_valid; - - // value method rawDmaReadCltStreamOut_initiator - output [3 : 0] m_dma_read_initiator; - - // value method rawDmaReadCltStreamOut_sqpn - output [23 : 0] m_dma_read_sqpn; - - // value method rawDmaReadCltStreamOut_wrID - output [63 : 0] m_dma_read_wr_id; - - // value method rawDmaReadCltStreamOut_startAddr - output [63 : 0] m_dma_read_start_addr; - - // value method rawDmaReadCltStreamOut_len - output [12 : 0] m_dma_read_len; - - // value method rawDmaReadCltStreamOut_mrIdx - output m_dma_read_mr_idx; - - // action method rawDmaReadCltStreamOut_ready - input m_dma_read_ready; - - // action method rawDmaReadCltStreamIn_validData - input s_dma_read_valid; - input [3 : 0] s_dma_read_initiator; - input [23 : 0] s_dma_read_sqpn; - input [63 : 0] s_dma_read_wr_id; - input s_dma_read_is_resp_err; - input [289 : 0] s_dma_read_data_stream; - - // value method rawDmaReadCltStreamIn_ready - output s_dma_read_ready; - - // signals for module outputs - wire [275 : 0] m_meta_data_tdata; - wire [255 : 0] m_data_stream_tdata; - wire [63 : 0] m_dma_read_start_addr, m_dma_read_wr_id, m_work_comp_sq_id; - wire [32 : 0] m_work_comp_sq_imm_dt, m_work_comp_sq_rkey_to_inv; - wire [31 : 0] m_data_stream_tkeep, m_work_comp_sq_len; - wire [23 : 0] m_dma_read_sqpn, m_work_comp_sq_qpn; - wire [15 : 0] m_work_comp_sq_pkey; - wire [12 : 0] m_dma_read_len; - wire [7 : 0] m_work_comp_sq_op_code; - wire [6 : 0] m_work_comp_sq_flags; - wire [4 : 0] m_work_comp_sq_status; - wire [3 : 0] m_dma_read_initiator; - wire m_data_stream_tfirst, - m_data_stream_tlast, - m_data_stream_tvalid, - m_dma_read_mr_idx, - m_dma_read_valid, - m_meta_data_tvalid, - m_work_comp_sq_valid, - s_data_stream_tready, - s_dma_read_ready, - s_meta_data_tready, - s_work_req_ready; - - // inlined wires - wire [600 : 0] rawWorkReqSlv_rawBus_rawBus_dataW_wget; - wire [382 : 0] rawDmaReadCltStreamSlv_rawBus_rawBus_dataW_wget; - wire [302 : 0] rawMetaDataStreamSlv_rawBus_rawBus_dataW_wget; - wire [289 : 0] rawRdmaDataStreamMst_rawBus_rawBus_dataW_wget, - rawRdmaDataStreamSlv_rawBus_rawBus_dataW_wget; - wire [275 : 0] rawMetaDataStreamMst_rawBus_rawBus_dataW_wget; - wire [221 : 0] rawWorkCompSQMst_rawBus_rawBus_dataW_wget; - wire [169 : 0] rawDmaReadCltStreamMst_rawBus_rawBus_dataW_wget; - wire rawDmaReadCltStreamMst_rawBus_rawBus_dataW_whas, - rawDmaReadCltStreamMst_rawBus_rawBus_readyW_wget, - rawDmaReadCltStreamSlv_rawBus_rawBus_validW_wget, - rawMetaDataStreamMst_rawBus_rawBus_dataW_whas, - rawMetaDataStreamMst_rawBus_rawBus_readyW_wget, - rawMetaDataStreamSlv_rawBus_rawBus_validW_wget, - rawRdmaDataStreamMst_rawBus_rawBus_dataW_whas, - rawRdmaDataStreamMst_rawBus_rawBus_readyW_wget, - rawRdmaDataStreamSlv_rawBus_rawBus_validW_wget, - rawWorkCompSQMst_rawBus_rawBus_dataW_whas, - rawWorkCompSQMst_rawBus_rawBus_readyW_wget, - rawWorkReqSlv_rawBus_rawBus_validW_wget; - - // ports of submodule rawDmaReadCltStreamMst_rawBus_fifo - wire [169 : 0] rawDmaReadCltStreamMst_rawBus_fifo_D_IN, - rawDmaReadCltStreamMst_rawBus_fifo_D_OUT; - wire rawDmaReadCltStreamMst_rawBus_fifo_CLR, - rawDmaReadCltStreamMst_rawBus_fifo_DEQ, - rawDmaReadCltStreamMst_rawBus_fifo_EMPTY_N, - rawDmaReadCltStreamMst_rawBus_fifo_ENQ, - rawDmaReadCltStreamMst_rawBus_fifo_FULL_N; - - // ports of submodule rawDmaReadCltStreamSlv_rawBus_fifo - wire [382 : 0] rawDmaReadCltStreamSlv_rawBus_fifo_D_IN, - rawDmaReadCltStreamSlv_rawBus_fifo_D_OUT; - wire rawDmaReadCltStreamSlv_rawBus_fifo_CLR, - rawDmaReadCltStreamSlv_rawBus_fifo_DEQ, - rawDmaReadCltStreamSlv_rawBus_fifo_EMPTY_N, - rawDmaReadCltStreamSlv_rawBus_fifo_ENQ, - rawDmaReadCltStreamSlv_rawBus_fifo_FULL_N; - - // ports of submodule rawMetaDataStreamMst_rawBus_fifo - reg [275 : 0] rawMetaDataStreamMst_rawBus_fifo_D_IN; - wire [275 : 0] rawMetaDataStreamMst_rawBus_fifo_D_OUT; - wire rawMetaDataStreamMst_rawBus_fifo_CLR, - rawMetaDataStreamMst_rawBus_fifo_DEQ, - rawMetaDataStreamMst_rawBus_fifo_EMPTY_N, - rawMetaDataStreamMst_rawBus_fifo_ENQ, - rawMetaDataStreamMst_rawBus_fifo_FULL_N; - - // ports of submodule rawMetaDataStreamSlv_rawBus_fifo - wire [302 : 0] rawMetaDataStreamSlv_rawBus_fifo_D_IN, - rawMetaDataStreamSlv_rawBus_fifo_D_OUT; - wire rawMetaDataStreamSlv_rawBus_fifo_CLR, - rawMetaDataStreamSlv_rawBus_fifo_DEQ, - rawMetaDataStreamSlv_rawBus_fifo_EMPTY_N, - rawMetaDataStreamSlv_rawBus_fifo_ENQ, - rawMetaDataStreamSlv_rawBus_fifo_FULL_N; - - // ports of submodule rawRdmaDataStreamMst_rawBus_fifo - wire [289 : 0] rawRdmaDataStreamMst_rawBus_fifo_D_IN, - rawRdmaDataStreamMst_rawBus_fifo_D_OUT; - wire rawRdmaDataStreamMst_rawBus_fifo_CLR, - rawRdmaDataStreamMst_rawBus_fifo_DEQ, - rawRdmaDataStreamMst_rawBus_fifo_EMPTY_N, - rawRdmaDataStreamMst_rawBus_fifo_ENQ, - rawRdmaDataStreamMst_rawBus_fifo_FULL_N; - - // ports of submodule rawRdmaDataStreamSlv_rawBus_fifo - wire [289 : 0] rawRdmaDataStreamSlv_rawBus_fifo_D_IN, - rawRdmaDataStreamSlv_rawBus_fifo_D_OUT; - wire rawRdmaDataStreamSlv_rawBus_fifo_CLR, - rawRdmaDataStreamSlv_rawBus_fifo_DEQ, - rawRdmaDataStreamSlv_rawBus_fifo_EMPTY_N, - rawRdmaDataStreamSlv_rawBus_fifo_ENQ, - rawRdmaDataStreamSlv_rawBus_fifo_FULL_N; - - // ports of submodule rawWorkCompSQMst_rawBus_fifo - wire [221 : 0] rawWorkCompSQMst_rawBus_fifo_D_IN, - rawWorkCompSQMst_rawBus_fifo_D_OUT; - wire rawWorkCompSQMst_rawBus_fifo_CLR, - rawWorkCompSQMst_rawBus_fifo_DEQ, - rawWorkCompSQMst_rawBus_fifo_EMPTY_N, - rawWorkCompSQMst_rawBus_fifo_ENQ, - rawWorkCompSQMst_rawBus_fifo_FULL_N; - - // ports of submodule rawWorkReqSlv_rawBus_fifo - wire [600 : 0] rawWorkReqSlv_rawBus_fifo_D_IN, - rawWorkReqSlv_rawBus_fifo_D_OUT; - wire rawWorkReqSlv_rawBus_fifo_CLR, - rawWorkReqSlv_rawBus_fifo_DEQ, - rawWorkReqSlv_rawBus_fifo_EMPTY_N, - rawWorkReqSlv_rawBus_fifo_ENQ, - rawWorkReqSlv_rawBus_fifo_FULL_N; - - // ports of submodule transportLayer - wire [600 : 0] transportLayer_workReqInput_put; - wire [382 : 0] transportLayer_dmaReadClt_response_put; - wire [302 : 0] transportLayer_srvPortMetaData_request_put; - wire [289 : 0] transportLayer_rdmaDataStreamInput_put, - transportLayer_rdmaDataStreamPipeOut_first; - wire [275 : 0] transportLayer_srvPortMetaData_response_get; - wire [221 : 0] transportLayer_workCompPipeOutSQ_first; - wire [169 : 0] transportLayer_dmaReadClt_request_get; - wire transportLayer_EN_dmaReadClt_request_get, - transportLayer_EN_dmaReadClt_response_put, - transportLayer_EN_rdmaDataStreamInput_put, - transportLayer_EN_rdmaDataStreamPipeOut_deq, - transportLayer_EN_srvPortMetaData_request_put, - transportLayer_EN_srvPortMetaData_response_get, - transportLayer_EN_workCompPipeOutSQ_deq, - transportLayer_EN_workReqInput_put, - transportLayer_RDY_dmaReadClt_request_get, - transportLayer_RDY_dmaReadClt_response_put, - transportLayer_RDY_rdmaDataStreamInput_put, - transportLayer_RDY_rdmaDataStreamPipeOut_deq, - transportLayer_RDY_rdmaDataStreamPipeOut_first, - transportLayer_RDY_srvPortMetaData_request_put, - transportLayer_RDY_srvPortMetaData_response_get, - transportLayer_RDY_workCompPipeOutSQ_deq, - transportLayer_RDY_workCompPipeOutSQ_first, - transportLayer_RDY_workReqInput_put; - - // rule scheduling signals - wire CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_mkConnectionGetPut, - CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passReady, - CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passWire, - CAN_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_mkConnectionGetPut, - CAN_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_rawBus_passData, - CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_mkConnectionGetPut, - CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passReady, - CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passWire, - CAN_FIRE_RL_rawMetaDataStreamSlv_rawBus_mkConnectionGetPut, - CAN_FIRE_RL_rawMetaDataStreamSlv_rawBus_rawBus_passData, - CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_mkConnectionGetPut, - CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passReady, - CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passWire, - CAN_FIRE_RL_rawRdmaDataStreamSlv_rawBus_mkConnectionGetPut, - CAN_FIRE_RL_rawRdmaDataStreamSlv_rawBus_rawBus_passData, - CAN_FIRE_RL_rawWorkCompSQMst_rawBus_mkConnectionGetPut, - CAN_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passReady, - CAN_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passWire, - CAN_FIRE_RL_rawWorkReqSlv_rawBus_mkConnectionGetPut, - CAN_FIRE_RL_rawWorkReqSlv_rawBus_rawBus_passData, - CAN_FIRE_rawDmaReadCltStreamIn_validData, - CAN_FIRE_rawDmaReadCltStreamOut_ready, - CAN_FIRE_rawMetaDataStreamIn_validData, - CAN_FIRE_rawMetaDataStreamOut_ready, - CAN_FIRE_rawRdmaDataStreamIn_validData, - CAN_FIRE_rawRdmaDataStreamOut_ready, - CAN_FIRE_rawWorkCompSQOut_ready, - CAN_FIRE_rawWorkReqIn_validData, - WILL_FIRE_RL_rawDmaReadCltStreamMst_rawBus_mkConnectionGetPut, - WILL_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passReady, - WILL_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passWire, - WILL_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_mkConnectionGetPut, - WILL_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_rawBus_passData, - WILL_FIRE_RL_rawMetaDataStreamMst_rawBus_mkConnectionGetPut, - WILL_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passReady, - WILL_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passWire, - WILL_FIRE_RL_rawMetaDataStreamSlv_rawBus_mkConnectionGetPut, - WILL_FIRE_RL_rawMetaDataStreamSlv_rawBus_rawBus_passData, - WILL_FIRE_RL_rawRdmaDataStreamMst_rawBus_mkConnectionGetPut, - WILL_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passReady, - WILL_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passWire, - WILL_FIRE_RL_rawRdmaDataStreamSlv_rawBus_mkConnectionGetPut, - WILL_FIRE_RL_rawRdmaDataStreamSlv_rawBus_rawBus_passData, - WILL_FIRE_RL_rawWorkCompSQMst_rawBus_mkConnectionGetPut, - WILL_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passReady, - WILL_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passWire, - WILL_FIRE_RL_rawWorkReqSlv_rawBus_mkConnectionGetPut, - WILL_FIRE_RL_rawWorkReqSlv_rawBus_rawBus_passData, - WILL_FIRE_rawDmaReadCltStreamIn_validData, - WILL_FIRE_rawDmaReadCltStreamOut_ready, - WILL_FIRE_rawMetaDataStreamIn_validData, - WILL_FIRE_rawMetaDataStreamOut_ready, - WILL_FIRE_rawRdmaDataStreamIn_validData, - WILL_FIRE_rawRdmaDataStreamOut_ready, - WILL_FIRE_rawWorkCompSQOut_ready, - WILL_FIRE_rawWorkReqIn_validData; - - // action method rawWorkReqIn_validData - assign CAN_FIRE_rawWorkReqIn_validData = 1'd1 ; - assign WILL_FIRE_rawWorkReqIn_validData = 1'd1 ; - - // value method rawWorkReqIn_ready - assign s_work_req_ready = rawWorkReqSlv_rawBus_fifo_FULL_N ; - - // action method rawRdmaDataStreamIn_validData - assign CAN_FIRE_rawRdmaDataStreamIn_validData = 1'd1 ; - assign WILL_FIRE_rawRdmaDataStreamIn_validData = 1'd1 ; - - // value method rawRdmaDataStreamIn_ready - assign s_data_stream_tready = rawRdmaDataStreamSlv_rawBus_fifo_FULL_N ; - - // value method rawRdmaDataStreamOut_valid - assign m_data_stream_tvalid = rawRdmaDataStreamMst_rawBus_fifo_EMPTY_N ; - - // value method rawRdmaDataStreamOut_data - assign m_data_stream_tdata = - rawRdmaDataStreamMst_rawBus_fifo_D_OUT[289:34] ; - - // value method rawRdmaDataStreamOut_byteEn - assign m_data_stream_tkeep = rawRdmaDataStreamMst_rawBus_fifo_D_OUT[33:2] ; - - // value method rawRdmaDataStreamOut_isFirst - assign m_data_stream_tfirst = rawRdmaDataStreamMst_rawBus_fifo_D_OUT[1] ; - - // value method rawRdmaDataStreamOut_isLast - assign m_data_stream_tlast = rawRdmaDataStreamMst_rawBus_fifo_D_OUT[0] ; - - // action method rawRdmaDataStreamOut_ready - assign CAN_FIRE_rawRdmaDataStreamOut_ready = 1'd1 ; - assign WILL_FIRE_rawRdmaDataStreamOut_ready = 1'd1 ; - - // value method rawWorkCompSQOut_valid - assign m_work_comp_sq_valid = rawWorkCompSQMst_rawBus_fifo_EMPTY_N ; - - // value method rawWorkCompSQOut_id - assign m_work_comp_sq_id = rawWorkCompSQMst_rawBus_fifo_D_OUT[221:158] ; - - // value method rawWorkCompSQOut_opcode - assign m_work_comp_sq_op_code = - rawWorkCompSQMst_rawBus_fifo_D_OUT[157:150] ; - - // value method rawWorkCompSQOut_flags - assign m_work_comp_sq_flags = rawWorkCompSQMst_rawBus_fifo_D_OUT[149:143] ; - - // value method rawWorkCompSQOut_status - assign m_work_comp_sq_status = rawWorkCompSQMst_rawBus_fifo_D_OUT[142:138] ; - - // value method rawWorkCompSQOut_len - assign m_work_comp_sq_len = rawWorkCompSQMst_rawBus_fifo_D_OUT[137:106] ; - - // value method rawWorkCompSQOut_pKey - assign m_work_comp_sq_pkey = rawWorkCompSQMst_rawBus_fifo_D_OUT[105:90] ; - - // value method rawWorkCompSQOut_qpn - assign m_work_comp_sq_qpn = rawWorkCompSQMst_rawBus_fifo_D_OUT[89:66] ; - - // value method rawWorkCompSQOut_immDt - assign m_work_comp_sq_imm_dt = rawWorkCompSQMst_rawBus_fifo_D_OUT[65:33] ; - - // value method rawWorkCompSQOut_rkey2Inv - assign m_work_comp_sq_rkey_to_inv = - rawWorkCompSQMst_rawBus_fifo_D_OUT[32:0] ; - - // action method rawWorkCompSQOut_ready - assign CAN_FIRE_rawWorkCompSQOut_ready = 1'd1 ; - assign WILL_FIRE_rawWorkCompSQOut_ready = 1'd1 ; - - // action method rawMetaDataStreamIn_validData - assign CAN_FIRE_rawMetaDataStreamIn_validData = 1'd1 ; - assign WILL_FIRE_rawMetaDataStreamIn_validData = 1'd1 ; - - // value method rawMetaDataStreamIn_ready - assign s_meta_data_tready = rawMetaDataStreamSlv_rawBus_fifo_FULL_N ; - - // value method rawMetaDataStreamOut_valid - assign m_meta_data_tvalid = rawMetaDataStreamMst_rawBus_fifo_EMPTY_N ; - - // value method rawMetaDataStreamOut_metaDataResp - assign m_meta_data_tdata = rawMetaDataStreamMst_rawBus_fifo_D_OUT ; - - // action method rawMetaDataStreamOut_ready - assign CAN_FIRE_rawMetaDataStreamOut_ready = 1'd1 ; - assign WILL_FIRE_rawMetaDataStreamOut_ready = 1'd1 ; - - // value method rawDmaReadCltStreamOut_valid - assign m_dma_read_valid = rawDmaReadCltStreamMst_rawBus_fifo_EMPTY_N ; - - // value method rawDmaReadCltStreamOut_initiator - assign m_dma_read_initiator = - rawDmaReadCltStreamMst_rawBus_fifo_D_OUT[169:166] ; - - // value method rawDmaReadCltStreamOut_sqpn - assign m_dma_read_sqpn = rawDmaReadCltStreamMst_rawBus_fifo_D_OUT[165:142] ; - - // value method rawDmaReadCltStreamOut_wrID - assign m_dma_read_wr_id = rawDmaReadCltStreamMst_rawBus_fifo_D_OUT[141:78] ; - - // value method rawDmaReadCltStreamOut_startAddr - assign m_dma_read_start_addr = - rawDmaReadCltStreamMst_rawBus_fifo_D_OUT[77:14] ; - - // value method rawDmaReadCltStreamOut_len - assign m_dma_read_len = rawDmaReadCltStreamMst_rawBus_fifo_D_OUT[13:1] ; - - // value method rawDmaReadCltStreamOut_mrIdx - assign m_dma_read_mr_idx = rawDmaReadCltStreamMst_rawBus_fifo_D_OUT[0] ; - - // action method rawDmaReadCltStreamOut_ready - assign CAN_FIRE_rawDmaReadCltStreamOut_ready = 1'd1 ; - assign WILL_FIRE_rawDmaReadCltStreamOut_ready = 1'd1 ; - - // action method rawDmaReadCltStreamIn_validData - assign CAN_FIRE_rawDmaReadCltStreamIn_validData = 1'd1 ; - assign WILL_FIRE_rawDmaReadCltStreamIn_validData = 1'd1 ; - - // value method rawDmaReadCltStreamIn_ready - assign s_dma_read_ready = rawDmaReadCltStreamSlv_rawBus_fifo_FULL_N ; - - // submodule rawDmaReadCltStreamMst_rawBus_fifo - FIFO2 #(.width(32'd170), - .guarded(1'd1)) rawDmaReadCltStreamMst_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rawDmaReadCltStreamMst_rawBus_fifo_D_IN), - .ENQ(rawDmaReadCltStreamMst_rawBus_fifo_ENQ), - .DEQ(rawDmaReadCltStreamMst_rawBus_fifo_DEQ), - .CLR(rawDmaReadCltStreamMst_rawBus_fifo_CLR), - .D_OUT(rawDmaReadCltStreamMst_rawBus_fifo_D_OUT), - .FULL_N(rawDmaReadCltStreamMst_rawBus_fifo_FULL_N), - .EMPTY_N(rawDmaReadCltStreamMst_rawBus_fifo_EMPTY_N)); - - // submodule rawDmaReadCltStreamSlv_rawBus_fifo - FIFO2 #(.width(32'd383), - .guarded(1'd1)) rawDmaReadCltStreamSlv_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rawDmaReadCltStreamSlv_rawBus_fifo_D_IN), - .ENQ(rawDmaReadCltStreamSlv_rawBus_fifo_ENQ), - .DEQ(rawDmaReadCltStreamSlv_rawBus_fifo_DEQ), - .CLR(rawDmaReadCltStreamSlv_rawBus_fifo_CLR), - .D_OUT(rawDmaReadCltStreamSlv_rawBus_fifo_D_OUT), - .FULL_N(rawDmaReadCltStreamSlv_rawBus_fifo_FULL_N), - .EMPTY_N(rawDmaReadCltStreamSlv_rawBus_fifo_EMPTY_N)); - - // submodule rawMetaDataStreamMst_rawBus_fifo - FIFO2 #(.width(32'd276), - .guarded(1'd1)) rawMetaDataStreamMst_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rawMetaDataStreamMst_rawBus_fifo_D_IN), - .ENQ(rawMetaDataStreamMst_rawBus_fifo_ENQ), - .DEQ(rawMetaDataStreamMst_rawBus_fifo_DEQ), - .CLR(rawMetaDataStreamMst_rawBus_fifo_CLR), - .D_OUT(rawMetaDataStreamMst_rawBus_fifo_D_OUT), - .FULL_N(rawMetaDataStreamMst_rawBus_fifo_FULL_N), - .EMPTY_N(rawMetaDataStreamMst_rawBus_fifo_EMPTY_N)); - - // submodule rawMetaDataStreamSlv_rawBus_fifo - FIFO2 #(.width(32'd303), - .guarded(1'd1)) rawMetaDataStreamSlv_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rawMetaDataStreamSlv_rawBus_fifo_D_IN), - .ENQ(rawMetaDataStreamSlv_rawBus_fifo_ENQ), - .DEQ(rawMetaDataStreamSlv_rawBus_fifo_DEQ), - .CLR(rawMetaDataStreamSlv_rawBus_fifo_CLR), - .D_OUT(rawMetaDataStreamSlv_rawBus_fifo_D_OUT), - .FULL_N(rawMetaDataStreamSlv_rawBus_fifo_FULL_N), - .EMPTY_N(rawMetaDataStreamSlv_rawBus_fifo_EMPTY_N)); - - // submodule rawRdmaDataStreamMst_rawBus_fifo - FIFO2 #(.width(32'd290), - .guarded(1'd1)) rawRdmaDataStreamMst_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rawRdmaDataStreamMst_rawBus_fifo_D_IN), - .ENQ(rawRdmaDataStreamMst_rawBus_fifo_ENQ), - .DEQ(rawRdmaDataStreamMst_rawBus_fifo_DEQ), - .CLR(rawRdmaDataStreamMst_rawBus_fifo_CLR), - .D_OUT(rawRdmaDataStreamMst_rawBus_fifo_D_OUT), - .FULL_N(rawRdmaDataStreamMst_rawBus_fifo_FULL_N), - .EMPTY_N(rawRdmaDataStreamMst_rawBus_fifo_EMPTY_N)); - - // submodule rawRdmaDataStreamSlv_rawBus_fifo - FIFO2 #(.width(32'd290), - .guarded(1'd1)) rawRdmaDataStreamSlv_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rawRdmaDataStreamSlv_rawBus_fifo_D_IN), - .ENQ(rawRdmaDataStreamSlv_rawBus_fifo_ENQ), - .DEQ(rawRdmaDataStreamSlv_rawBus_fifo_DEQ), - .CLR(rawRdmaDataStreamSlv_rawBus_fifo_CLR), - .D_OUT(rawRdmaDataStreamSlv_rawBus_fifo_D_OUT), - .FULL_N(rawRdmaDataStreamSlv_rawBus_fifo_FULL_N), - .EMPTY_N(rawRdmaDataStreamSlv_rawBus_fifo_EMPTY_N)); - - // submodule rawWorkCompSQMst_rawBus_fifo - FIFO2 #(.width(32'd222), - .guarded(1'd1)) rawWorkCompSQMst_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rawWorkCompSQMst_rawBus_fifo_D_IN), - .ENQ(rawWorkCompSQMst_rawBus_fifo_ENQ), - .DEQ(rawWorkCompSQMst_rawBus_fifo_DEQ), - .CLR(rawWorkCompSQMst_rawBus_fifo_CLR), - .D_OUT(rawWorkCompSQMst_rawBus_fifo_D_OUT), - .FULL_N(rawWorkCompSQMst_rawBus_fifo_FULL_N), - .EMPTY_N(rawWorkCompSQMst_rawBus_fifo_EMPTY_N)); - - // submodule rawWorkReqSlv_rawBus_fifo - FIFO2 #(.width(32'd601), - .guarded(1'd1)) rawWorkReqSlv_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(rawWorkReqSlv_rawBus_fifo_D_IN), - .ENQ(rawWorkReqSlv_rawBus_fifo_ENQ), - .DEQ(rawWorkReqSlv_rawBus_fifo_DEQ), - .CLR(rawWorkReqSlv_rawBus_fifo_CLR), - .D_OUT(rawWorkReqSlv_rawBus_fifo_D_OUT), - .FULL_N(rawWorkReqSlv_rawBus_fifo_FULL_N), - .EMPTY_N(rawWorkReqSlv_rawBus_fifo_EMPTY_N)); - - // submodule transportLayer - mkTransportLayer transportLayer(.CLK(CLK), - .RST_N(RST_N), - .dmaReadClt_response_put(transportLayer_dmaReadClt_response_put), - .rdmaDataStreamInput_put(transportLayer_rdmaDataStreamInput_put), - .srvPortMetaData_request_put(transportLayer_srvPortMetaData_request_put), - .workReqInput_put(transportLayer_workReqInput_put), - .EN_workReqInput_put(transportLayer_EN_workReqInput_put), - .EN_rdmaDataStreamInput_put(transportLayer_EN_rdmaDataStreamInput_put), - .EN_rdmaDataStreamPipeOut_deq(transportLayer_EN_rdmaDataStreamPipeOut_deq), - .EN_workCompPipeOutSQ_deq(transportLayer_EN_workCompPipeOutSQ_deq), - .EN_srvPortMetaData_request_put(transportLayer_EN_srvPortMetaData_request_put), - .EN_srvPortMetaData_response_get(transportLayer_EN_srvPortMetaData_response_get), - .EN_dmaReadClt_request_get(transportLayer_EN_dmaReadClt_request_get), - .EN_dmaReadClt_response_put(transportLayer_EN_dmaReadClt_response_put), - .RDY_workReqInput_put(transportLayer_RDY_workReqInput_put), - .RDY_rdmaDataStreamInput_put(transportLayer_RDY_rdmaDataStreamInput_put), - .rdmaDataStreamPipeOut_first(transportLayer_rdmaDataStreamPipeOut_first), - .RDY_rdmaDataStreamPipeOut_first(transportLayer_RDY_rdmaDataStreamPipeOut_first), - .RDY_rdmaDataStreamPipeOut_deq(transportLayer_RDY_rdmaDataStreamPipeOut_deq), - .rdmaDataStreamPipeOut_notEmpty(), - .RDY_rdmaDataStreamPipeOut_notEmpty(), - .workCompPipeOutSQ_first(transportLayer_workCompPipeOutSQ_first), - .RDY_workCompPipeOutSQ_first(transportLayer_RDY_workCompPipeOutSQ_first), - .RDY_workCompPipeOutSQ_deq(transportLayer_RDY_workCompPipeOutSQ_deq), - .workCompPipeOutSQ_notEmpty(), - .RDY_workCompPipeOutSQ_notEmpty(), - .RDY_srvPortMetaData_request_put(transportLayer_RDY_srvPortMetaData_request_put), - .srvPortMetaData_response_get(transportLayer_srvPortMetaData_response_get), - .RDY_srvPortMetaData_response_get(transportLayer_RDY_srvPortMetaData_response_get), - .dmaReadClt_request_get(transportLayer_dmaReadClt_request_get), - .RDY_dmaReadClt_request_get(transportLayer_RDY_dmaReadClt_request_get), - .RDY_dmaReadClt_response_put(transportLayer_RDY_dmaReadClt_response_put)); - - // rule RL_rawWorkReqSlv_rawBus_mkConnectionGetPut - assign CAN_FIRE_RL_rawWorkReqSlv_rawBus_mkConnectionGetPut = - transportLayer_RDY_workReqInput_put && - rawWorkReqSlv_rawBus_fifo_EMPTY_N ; - assign WILL_FIRE_RL_rawWorkReqSlv_rawBus_mkConnectionGetPut = - CAN_FIRE_RL_rawWorkReqSlv_rawBus_mkConnectionGetPut ; - - // rule RL_rawWorkReqSlv_rawBus_rawBus_passData - assign CAN_FIRE_RL_rawWorkReqSlv_rawBus_rawBus_passData = - rawWorkReqSlv_rawBus_fifo_FULL_N && s_work_req_valid ; - assign WILL_FIRE_RL_rawWorkReqSlv_rawBus_rawBus_passData = - CAN_FIRE_RL_rawWorkReqSlv_rawBus_rawBus_passData ; - - // rule RL_rawRdmaDataStreamSlv_rawBus_mkConnectionGetPut - assign CAN_FIRE_RL_rawRdmaDataStreamSlv_rawBus_mkConnectionGetPut = - transportLayer_RDY_rdmaDataStreamInput_put && - rawRdmaDataStreamSlv_rawBus_fifo_EMPTY_N ; - assign WILL_FIRE_RL_rawRdmaDataStreamSlv_rawBus_mkConnectionGetPut = - CAN_FIRE_RL_rawRdmaDataStreamSlv_rawBus_mkConnectionGetPut ; - - // rule RL_rawRdmaDataStreamSlv_rawBus_rawBus_passData - assign CAN_FIRE_RL_rawRdmaDataStreamSlv_rawBus_rawBus_passData = - rawRdmaDataStreamSlv_rawBus_fifo_FULL_N && s_data_stream_tvalid ; - assign WILL_FIRE_RL_rawRdmaDataStreamSlv_rawBus_rawBus_passData = - CAN_FIRE_RL_rawRdmaDataStreamSlv_rawBus_rawBus_passData ; - - // rule RL_rawRdmaDataStreamMst_rawBus_rawBus_passWire - assign CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passWire = - rawRdmaDataStreamMst_rawBus_fifo_EMPTY_N ; - assign WILL_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passWire = - rawRdmaDataStreamMst_rawBus_fifo_EMPTY_N ; - - // rule RL_rawRdmaDataStreamMst_rawBus_rawBus_passReady - assign CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passReady = - rawRdmaDataStreamMst_rawBus_fifo_EMPTY_N && - m_data_stream_tready ; - assign WILL_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passReady = - CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passReady ; - - // rule RL_rawRdmaDataStreamMst_rawBus_mkConnectionGetPut - assign CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_mkConnectionGetPut = - transportLayer_RDY_rdmaDataStreamPipeOut_deq && - transportLayer_RDY_rdmaDataStreamPipeOut_first && - rawRdmaDataStreamMst_rawBus_fifo_FULL_N ; - assign WILL_FIRE_RL_rawRdmaDataStreamMst_rawBus_mkConnectionGetPut = - CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_mkConnectionGetPut ; - - // rule RL_rawWorkCompSQMst_rawBus_rawBus_passWire - assign CAN_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passWire = - rawWorkCompSQMst_rawBus_fifo_EMPTY_N ; - assign WILL_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passWire = - rawWorkCompSQMst_rawBus_fifo_EMPTY_N ; - - // rule RL_rawWorkCompSQMst_rawBus_rawBus_passReady - assign CAN_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passReady = - rawWorkCompSQMst_rawBus_fifo_EMPTY_N && m_work_comp_sq_ready ; - assign WILL_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passReady = - CAN_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passReady ; - - // rule RL_rawWorkCompSQMst_rawBus_mkConnectionGetPut - assign CAN_FIRE_RL_rawWorkCompSQMst_rawBus_mkConnectionGetPut = - transportLayer_RDY_workCompPipeOutSQ_deq && - transportLayer_RDY_workCompPipeOutSQ_first && - rawWorkCompSQMst_rawBus_fifo_FULL_N ; - assign WILL_FIRE_RL_rawWorkCompSQMst_rawBus_mkConnectionGetPut = - CAN_FIRE_RL_rawWorkCompSQMst_rawBus_mkConnectionGetPut ; - - // rule RL_rawMetaDataStreamMst_rawBus_rawBus_passWire - assign CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passWire = - rawMetaDataStreamMst_rawBus_fifo_EMPTY_N ; - assign WILL_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passWire = - rawMetaDataStreamMst_rawBus_fifo_EMPTY_N ; - - // rule RL_rawMetaDataStreamMst_rawBus_rawBus_passReady - assign CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passReady = - rawMetaDataStreamMst_rawBus_fifo_EMPTY_N && m_meta_data_tready ; - assign WILL_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passReady = - CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passReady ; - - // rule RL_rawMetaDataStreamMst_rawBus_mkConnectionGetPut - assign CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_mkConnectionGetPut = - transportLayer_RDY_srvPortMetaData_response_get && - rawMetaDataStreamMst_rawBus_fifo_FULL_N ; - assign WILL_FIRE_RL_rawMetaDataStreamMst_rawBus_mkConnectionGetPut = - CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_mkConnectionGetPut ; - - // rule RL_rawMetaDataStreamSlv_rawBus_mkConnectionGetPut - assign CAN_FIRE_RL_rawMetaDataStreamSlv_rawBus_mkConnectionGetPut = - transportLayer_RDY_srvPortMetaData_request_put && - rawMetaDataStreamSlv_rawBus_fifo_EMPTY_N ; - assign WILL_FIRE_RL_rawMetaDataStreamSlv_rawBus_mkConnectionGetPut = - CAN_FIRE_RL_rawMetaDataStreamSlv_rawBus_mkConnectionGetPut ; - - // rule RL_rawMetaDataStreamSlv_rawBus_rawBus_passData - assign CAN_FIRE_RL_rawMetaDataStreamSlv_rawBus_rawBus_passData = - rawMetaDataStreamSlv_rawBus_fifo_FULL_N && s_meta_data_tvalid ; - assign WILL_FIRE_RL_rawMetaDataStreamSlv_rawBus_rawBus_passData = - CAN_FIRE_RL_rawMetaDataStreamSlv_rawBus_rawBus_passData ; - - // rule RL_rawDmaReadCltStreamMst_rawBus_rawBus_passWire - assign CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passWire = - rawDmaReadCltStreamMst_rawBus_fifo_EMPTY_N ; - assign WILL_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passWire = - rawDmaReadCltStreamMst_rawBus_fifo_EMPTY_N ; - - // rule RL_rawDmaReadCltStreamMst_rawBus_rawBus_passReady - assign CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passReady = - rawDmaReadCltStreamMst_rawBus_fifo_EMPTY_N && m_dma_read_ready ; - assign WILL_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passReady = - CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passReady ; - - // rule RL_rawDmaReadCltStreamMst_rawBus_mkConnectionGetPut - assign CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_mkConnectionGetPut = - transportLayer_RDY_dmaReadClt_request_get && - rawDmaReadCltStreamMst_rawBus_fifo_FULL_N ; - assign WILL_FIRE_RL_rawDmaReadCltStreamMst_rawBus_mkConnectionGetPut = - CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_mkConnectionGetPut ; - - // rule RL_rawDmaReadCltStreamSlv_rawBus_mkConnectionGetPut - assign CAN_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_mkConnectionGetPut = - transportLayer_RDY_dmaReadClt_response_put && - rawDmaReadCltStreamSlv_rawBus_fifo_EMPTY_N ; - assign WILL_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_mkConnectionGetPut = - CAN_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_mkConnectionGetPut ; - - // rule RL_rawDmaReadCltStreamSlv_rawBus_rawBus_passData - assign CAN_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_rawBus_passData = - rawDmaReadCltStreamSlv_rawBus_fifo_FULL_N && s_dma_read_valid ; - assign WILL_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_rawBus_passData = - CAN_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_rawBus_passData ; - - // inlined wires - assign rawRdmaDataStreamMst_rawBus_rawBus_dataW_wget = - rawRdmaDataStreamMst_rawBus_fifo_D_OUT ; - assign rawRdmaDataStreamMst_rawBus_rawBus_dataW_whas = - rawRdmaDataStreamMst_rawBus_fifo_EMPTY_N ; - assign rawWorkCompSQMst_rawBus_rawBus_dataW_wget = - rawWorkCompSQMst_rawBus_fifo_D_OUT ; - assign rawWorkCompSQMst_rawBus_rawBus_dataW_whas = - rawWorkCompSQMst_rawBus_fifo_EMPTY_N ; - assign rawMetaDataStreamMst_rawBus_rawBus_dataW_wget = - rawMetaDataStreamMst_rawBus_fifo_D_OUT ; - assign rawMetaDataStreamMst_rawBus_rawBus_dataW_whas = - rawMetaDataStreamMst_rawBus_fifo_EMPTY_N ; - assign rawDmaReadCltStreamMst_rawBus_rawBus_dataW_wget = - rawDmaReadCltStreamMst_rawBus_fifo_D_OUT ; - assign rawDmaReadCltStreamMst_rawBus_rawBus_dataW_whas = - rawDmaReadCltStreamMst_rawBus_fifo_EMPTY_N ; - assign rawWorkReqSlv_rawBus_rawBus_validW_wget = s_work_req_valid ; - assign rawWorkReqSlv_rawBus_rawBus_dataW_wget = - { s_work_req_id, - s_work_req_op_code, - s_work_req_flags, - s_work_req_raddr, - s_work_req_rkey, - s_work_req_len, - s_work_req_laddr, - s_work_req_lkey, - s_work_req_sqpn, - s_work_req_solicited, - s_work_req_comp, - s_work_req_swap, - s_work_req_imm_dt, - s_work_req_rkey_to_inv, - s_work_req_srqn, - s_work_req_dqpn, - s_work_req_qkey } ; - assign rawRdmaDataStreamSlv_rawBus_rawBus_validW_wget = - s_data_stream_tvalid ; - assign rawRdmaDataStreamSlv_rawBus_rawBus_dataW_wget = - { s_data_stream_tdata, - s_data_stream_tkeep, - s_data_stream_tfirst, - s_data_stream_tlast } ; - assign rawRdmaDataStreamMst_rawBus_rawBus_readyW_wget = - m_data_stream_tready ; - assign rawWorkCompSQMst_rawBus_rawBus_readyW_wget = m_work_comp_sq_ready ; - assign rawMetaDataStreamMst_rawBus_rawBus_readyW_wget = m_meta_data_tready ; - assign rawMetaDataStreamSlv_rawBus_rawBus_validW_wget = s_meta_data_tvalid ; - assign rawMetaDataStreamSlv_rawBus_rawBus_dataW_wget = s_meta_data_tdata ; - assign rawDmaReadCltStreamMst_rawBus_rawBus_readyW_wget = m_dma_read_ready ; - assign rawDmaReadCltStreamSlv_rawBus_rawBus_validW_wget = s_dma_read_valid ; - assign rawDmaReadCltStreamSlv_rawBus_rawBus_dataW_wget = - { s_dma_read_initiator, - s_dma_read_sqpn, - s_dma_read_wr_id, - s_dma_read_is_resp_err, - s_dma_read_data_stream } ; - - // submodule rawDmaReadCltStreamMst_rawBus_fifo - assign rawDmaReadCltStreamMst_rawBus_fifo_D_IN = - transportLayer_dmaReadClt_request_get ; - assign rawDmaReadCltStreamMst_rawBus_fifo_ENQ = - CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_mkConnectionGetPut ; - assign rawDmaReadCltStreamMst_rawBus_fifo_DEQ = - CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_rawBus_passReady ; - assign rawDmaReadCltStreamMst_rawBus_fifo_CLR = 1'b0 ; - - // submodule rawDmaReadCltStreamSlv_rawBus_fifo - assign rawDmaReadCltStreamSlv_rawBus_fifo_D_IN = - rawDmaReadCltStreamSlv_rawBus_rawBus_dataW_wget ; - assign rawDmaReadCltStreamSlv_rawBus_fifo_ENQ = - CAN_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_rawBus_passData ; - assign rawDmaReadCltStreamSlv_rawBus_fifo_DEQ = - CAN_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_mkConnectionGetPut ; - assign rawDmaReadCltStreamSlv_rawBus_fifo_CLR = 1'b0 ; - - // submodule rawMetaDataStreamMst_rawBus_fifo - always@(transportLayer_srvPortMetaData_response_get) - begin - case (transportLayer_srvPortMetaData_response_get[275:274]) - 2'd0, 2'd1, 2'd2: - rawMetaDataStreamMst_rawBus_fifo_D_IN = - transportLayer_srvPortMetaData_response_get; - 2'd3: - rawMetaDataStreamMst_rawBus_fifo_D_IN = - 276'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - endcase - end - assign rawMetaDataStreamMst_rawBus_fifo_ENQ = - CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_mkConnectionGetPut ; - assign rawMetaDataStreamMst_rawBus_fifo_DEQ = - CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_rawBus_passReady ; - assign rawMetaDataStreamMst_rawBus_fifo_CLR = 1'b0 ; - - // submodule rawMetaDataStreamSlv_rawBus_fifo - assign rawMetaDataStreamSlv_rawBus_fifo_D_IN = s_meta_data_tdata ; - assign rawMetaDataStreamSlv_rawBus_fifo_ENQ = - CAN_FIRE_RL_rawMetaDataStreamSlv_rawBus_rawBus_passData ; - assign rawMetaDataStreamSlv_rawBus_fifo_DEQ = - CAN_FIRE_RL_rawMetaDataStreamSlv_rawBus_mkConnectionGetPut ; - assign rawMetaDataStreamSlv_rawBus_fifo_CLR = 1'b0 ; - - // submodule rawRdmaDataStreamMst_rawBus_fifo - assign rawRdmaDataStreamMst_rawBus_fifo_D_IN = - transportLayer_rdmaDataStreamPipeOut_first ; - assign rawRdmaDataStreamMst_rawBus_fifo_ENQ = - CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_mkConnectionGetPut ; - assign rawRdmaDataStreamMst_rawBus_fifo_DEQ = - CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_rawBus_passReady ; - assign rawRdmaDataStreamMst_rawBus_fifo_CLR = 1'b0 ; - - // submodule rawRdmaDataStreamSlv_rawBus_fifo - assign rawRdmaDataStreamSlv_rawBus_fifo_D_IN = - rawRdmaDataStreamSlv_rawBus_rawBus_dataW_wget ; - assign rawRdmaDataStreamSlv_rawBus_fifo_ENQ = - CAN_FIRE_RL_rawRdmaDataStreamSlv_rawBus_rawBus_passData ; - assign rawRdmaDataStreamSlv_rawBus_fifo_DEQ = - CAN_FIRE_RL_rawRdmaDataStreamSlv_rawBus_mkConnectionGetPut ; - assign rawRdmaDataStreamSlv_rawBus_fifo_CLR = 1'b0 ; - - // submodule rawWorkCompSQMst_rawBus_fifo - assign rawWorkCompSQMst_rawBus_fifo_D_IN = - transportLayer_workCompPipeOutSQ_first ; - assign rawWorkCompSQMst_rawBus_fifo_ENQ = - CAN_FIRE_RL_rawWorkCompSQMst_rawBus_mkConnectionGetPut ; - assign rawWorkCompSQMst_rawBus_fifo_DEQ = - CAN_FIRE_RL_rawWorkCompSQMst_rawBus_rawBus_passReady ; - assign rawWorkCompSQMst_rawBus_fifo_CLR = 1'b0 ; - - // submodule rawWorkReqSlv_rawBus_fifo - assign rawWorkReqSlv_rawBus_fifo_D_IN = - rawWorkReqSlv_rawBus_rawBus_dataW_wget ; - assign rawWorkReqSlv_rawBus_fifo_ENQ = - CAN_FIRE_RL_rawWorkReqSlv_rawBus_rawBus_passData ; - assign rawWorkReqSlv_rawBus_fifo_DEQ = - CAN_FIRE_RL_rawWorkReqSlv_rawBus_mkConnectionGetPut ; - assign rawWorkReqSlv_rawBus_fifo_CLR = 1'b0 ; - - // submodule transportLayer - assign transportLayer_dmaReadClt_response_put = - rawDmaReadCltStreamSlv_rawBus_fifo_D_OUT ; - assign transportLayer_rdmaDataStreamInput_put = - rawRdmaDataStreamSlv_rawBus_fifo_D_OUT ; - assign transportLayer_srvPortMetaData_request_put = - rawMetaDataStreamSlv_rawBus_fifo_D_OUT ; - assign transportLayer_workReqInput_put = rawWorkReqSlv_rawBus_fifo_D_OUT ; - assign transportLayer_EN_workReqInput_put = - CAN_FIRE_RL_rawWorkReqSlv_rawBus_mkConnectionGetPut ; - assign transportLayer_EN_rdmaDataStreamInput_put = - CAN_FIRE_RL_rawRdmaDataStreamSlv_rawBus_mkConnectionGetPut ; - assign transportLayer_EN_rdmaDataStreamPipeOut_deq = - CAN_FIRE_RL_rawRdmaDataStreamMst_rawBus_mkConnectionGetPut ; - assign transportLayer_EN_workCompPipeOutSQ_deq = - CAN_FIRE_RL_rawWorkCompSQMst_rawBus_mkConnectionGetPut ; - assign transportLayer_EN_srvPortMetaData_request_put = - CAN_FIRE_RL_rawMetaDataStreamSlv_rawBus_mkConnectionGetPut ; - assign transportLayer_EN_srvPortMetaData_response_get = - CAN_FIRE_RL_rawMetaDataStreamMst_rawBus_mkConnectionGetPut ; - assign transportLayer_EN_dmaReadClt_request_get = - CAN_FIRE_RL_rawDmaReadCltStreamMst_rawBus_mkConnectionGetPut ; - assign transportLayer_EN_dmaReadClt_response_put = - CAN_FIRE_RL_rawDmaReadCltStreamSlv_rawBus_mkConnectionGetPut ; -endmodule // mkAxiSTransportLayer - diff --git a/ethernet/RoCEv2/blue-rdma/mkQP.v b/ethernet/RoCEv2/blue-rdma/mkQP.v deleted file mode 100644 index 4d183e9513..0000000000 --- a/ethernet/RoCEv2/blue-rdma/mkQP.v +++ /dev/null @@ -1,25463 +0,0 @@ -/* - * ------------------------------------------------------------------- - * This Verilog file has been automatically generated from a core originally written - * in Bluespec SystemVerilog (BSV). The original source code can be found at: - * - * Repository: https://github.com/datenlord/blue-rdma - * Author: DatenLord (https://datenlord.github.io/) - * - * Modifications have been made to the original core before compiling the Verilog. - * For any questions or further information regarding the modifications, please - * feel free to contact me. - * - * Modifications by: Filippo Marini - * Email: filippo.marini@pd.infn.it - * ------------------------------------------------------------------- - */ -// -// Generated by Bluespec Compiler, version 2023.01 (build 52adafa) -// -// On Wed Sep 11 15:19:43 CEST 2024 -// -// Ports: -// Name I/O size props -// RDY_srvPortQP_request_put O 1 reg -// srvPortQP_response_get O 274 reg -// RDY_srvPortQP_response_get O 1 reg -// RDY_workReqIn_put O 1 reg -// dmaReadClt4SQ_request_get O 170 reg -// RDY_dmaReadClt4SQ_request_get O 1 reg -// RDY_dmaReadClt4SQ_response_put O 1 reg -// RDY_respPktPipeIn_pktMetaData_put O 1 reg -// RDY_respPktPipeIn_payload_put O 1 reg -// statusSQ_comm_isCreate O 1 -// RDY_statusSQ_comm_isCreate O 1 const -// statusSQ_comm_isERR O 1 -// RDY_statusSQ_comm_isERR O 1 const -// statusSQ_comm_isInit O 1 -// RDY_statusSQ_comm_isInit O 1 const -// statusSQ_comm_isReset O 1 -// RDY_statusSQ_comm_isReset O 1 const -// statusSQ_comm_isRTR O 1 -// RDY_statusSQ_comm_isRTR O 1 const -// statusSQ_comm_isRTS O 1 -// RDY_statusSQ_comm_isRTS O 1 const -// statusSQ_comm_isSQD O 1 -// RDY_statusSQ_comm_isSQD O 1 const -// statusSQ_comm_isNonErr O 1 -// RDY_statusSQ_comm_isNonErr O 1 const -// statusSQ_comm_isUnknown O 1 -// RDY_statusSQ_comm_isUnknown O 1 const -// statusSQ_comm_isRTR2RTS O 1 -// RDY_statusSQ_comm_isRTR2RTS O 1 const -// statusSQ_comm_isStableRTS O 1 -// RDY_statusSQ_comm_isStableRTS O 1 const -// statusSQ_comm_getAccessFlags O 8 reg -// RDY_statusSQ_comm_getAccessFlags O 1 -// statusSQ_comm_getMaxRnrCnt O 3 reg -// RDY_statusSQ_comm_getMaxRnrCnt O 1 -// statusSQ_comm_getMaxRetryCnt O 3 reg -// RDY_statusSQ_comm_getMaxRetryCnt O 1 -// statusSQ_comm_getMinRnrTimer O 5 reg -// RDY_statusSQ_comm_getMinRnrTimer O 1 -// statusSQ_comm_getMaxTimeOut O 5 reg -// RDY_statusSQ_comm_getMaxTimeOut O 1 -// statusSQ_comm_getPendingWorkReqNum O 8 reg -// RDY_statusSQ_comm_getPendingWorkReqNum O 1 -// statusSQ_comm_getPendingRecvReqNum O 8 reg -// RDY_statusSQ_comm_getPendingRecvReqNum O 1 -// statusSQ_comm_getPendingReadAtomicReqNum O 8 reg -// RDY_statusSQ_comm_getPendingReadAtomicReqNum O 1 -// statusSQ_comm_getPendingDestReadAtomicReqNum O 8 reg -// RDY_statusSQ_comm_getPendingDestReadAtomicReqNum O 1 -// statusSQ_comm_getSigAll O 1 reg -// RDY_statusSQ_comm_getSigAll O 1 -// statusSQ_comm_getSQPN O 24 reg -// RDY_statusSQ_comm_getSQPN O 1 -// statusSQ_comm_getDQPN O 24 reg -// RDY_statusSQ_comm_getDQPN O 1 -// statusSQ_comm_getPKEY O 16 reg -// RDY_statusSQ_comm_getPKEY O 1 -// statusSQ_comm_getQKEY O 32 reg -// RDY_statusSQ_comm_getQKEY O 1 -// statusSQ_comm_getPMTU O 3 reg -// RDY_statusSQ_comm_getPMTU O 1 -// statusSQ_getTypeQP O 4 reg -// RDY_statusSQ_getTypeQP O 1 const -// statusSQ_isSQ O 1 const -// RDY_statusSQ_isSQ O 1 const -// rdmaReqPipeOut_first O 290 reg -// RDY_rdmaReqPipeOut_first O 1 reg -// RDY_rdmaReqPipeOut_deq O 1 reg -// rdmaReqPipeOut_notEmpty O 1 reg -// RDY_rdmaReqPipeOut_notEmpty O 1 const -// workCompPipeOutSQ_first O 222 reg -// RDY_workCompPipeOutSQ_first O 1 reg -// RDY_workCompPipeOutSQ_deq O 1 reg -// workCompPipeOutSQ_notEmpty O 1 reg -// RDY_workCompPipeOutSQ_notEmpty O 1 const -// CLK I 1 clock -// RST_N I 1 reset -// srvPortQP_request_put I 301 reg -// workReqIn_put I 601 reg -// dmaReadClt4SQ_response_put I 383 reg -// respPktPipeIn_pktMetaData_put I 649 reg -// respPktPipeIn_payload_put I 290 reg -// EN_srvPortQP_request_put I 1 -// EN_workReqIn_put I 1 -// EN_dmaReadClt4SQ_response_put I 1 -// EN_respPktPipeIn_pktMetaData_put I 1 -// EN_respPktPipeIn_payload_put I 1 -// EN_rdmaReqPipeOut_deq I 1 -// EN_workCompPipeOutSQ_deq I 1 -// EN_srvPortQP_response_get I 1 -// EN_dmaReadClt4SQ_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkQP(CLK, - RST_N, - - srvPortQP_request_put, - EN_srvPortQP_request_put, - RDY_srvPortQP_request_put, - - EN_srvPortQP_response_get, - srvPortQP_response_get, - RDY_srvPortQP_response_get, - - workReqIn_put, - EN_workReqIn_put, - RDY_workReqIn_put, - - EN_dmaReadClt4SQ_request_get, - dmaReadClt4SQ_request_get, - RDY_dmaReadClt4SQ_request_get, - - dmaReadClt4SQ_response_put, - EN_dmaReadClt4SQ_response_put, - RDY_dmaReadClt4SQ_response_put, - - respPktPipeIn_pktMetaData_put, - EN_respPktPipeIn_pktMetaData_put, - RDY_respPktPipeIn_pktMetaData_put, - - respPktPipeIn_payload_put, - EN_respPktPipeIn_payload_put, - RDY_respPktPipeIn_payload_put, - - statusSQ_comm_isCreate, - RDY_statusSQ_comm_isCreate, - - statusSQ_comm_isERR, - RDY_statusSQ_comm_isERR, - - statusSQ_comm_isInit, - RDY_statusSQ_comm_isInit, - - statusSQ_comm_isReset, - RDY_statusSQ_comm_isReset, - - statusSQ_comm_isRTR, - RDY_statusSQ_comm_isRTR, - - statusSQ_comm_isRTS, - RDY_statusSQ_comm_isRTS, - - statusSQ_comm_isSQD, - RDY_statusSQ_comm_isSQD, - - statusSQ_comm_isNonErr, - RDY_statusSQ_comm_isNonErr, - - statusSQ_comm_isUnknown, - RDY_statusSQ_comm_isUnknown, - - statusSQ_comm_isRTR2RTS, - RDY_statusSQ_comm_isRTR2RTS, - - statusSQ_comm_isStableRTS, - RDY_statusSQ_comm_isStableRTS, - - statusSQ_comm_getAccessFlags, - RDY_statusSQ_comm_getAccessFlags, - - statusSQ_comm_getMaxRnrCnt, - RDY_statusSQ_comm_getMaxRnrCnt, - - statusSQ_comm_getMaxRetryCnt, - RDY_statusSQ_comm_getMaxRetryCnt, - - statusSQ_comm_getMinRnrTimer, - RDY_statusSQ_comm_getMinRnrTimer, - - statusSQ_comm_getMaxTimeOut, - RDY_statusSQ_comm_getMaxTimeOut, - - statusSQ_comm_getPendingWorkReqNum, - RDY_statusSQ_comm_getPendingWorkReqNum, - - statusSQ_comm_getPendingRecvReqNum, - RDY_statusSQ_comm_getPendingRecvReqNum, - - statusSQ_comm_getPendingReadAtomicReqNum, - RDY_statusSQ_comm_getPendingReadAtomicReqNum, - - statusSQ_comm_getPendingDestReadAtomicReqNum, - RDY_statusSQ_comm_getPendingDestReadAtomicReqNum, - - statusSQ_comm_getSigAll, - RDY_statusSQ_comm_getSigAll, - - statusSQ_comm_getSQPN, - RDY_statusSQ_comm_getSQPN, - - statusSQ_comm_getDQPN, - RDY_statusSQ_comm_getDQPN, - - statusSQ_comm_getPKEY, - RDY_statusSQ_comm_getPKEY, - - statusSQ_comm_getQKEY, - RDY_statusSQ_comm_getQKEY, - - statusSQ_comm_getPMTU, - RDY_statusSQ_comm_getPMTU, - - statusSQ_getTypeQP, - RDY_statusSQ_getTypeQP, - - statusSQ_isSQ, - RDY_statusSQ_isSQ, - - rdmaReqPipeOut_first, - RDY_rdmaReqPipeOut_first, - - EN_rdmaReqPipeOut_deq, - RDY_rdmaReqPipeOut_deq, - - rdmaReqPipeOut_notEmpty, - RDY_rdmaReqPipeOut_notEmpty, - - workCompPipeOutSQ_first, - RDY_workCompPipeOutSQ_first, - - EN_workCompPipeOutSQ_deq, - RDY_workCompPipeOutSQ_deq, - - workCompPipeOutSQ_notEmpty, - RDY_workCompPipeOutSQ_notEmpty); - input CLK; - input RST_N; - - // action method srvPortQP_request_put - input [300 : 0] srvPortQP_request_put; - input EN_srvPortQP_request_put; - output RDY_srvPortQP_request_put; - - // actionvalue method srvPortQP_response_get - input EN_srvPortQP_response_get; - output [273 : 0] srvPortQP_response_get; - output RDY_srvPortQP_response_get; - - // action method workReqIn_put - input [600 : 0] workReqIn_put; - input EN_workReqIn_put; - output RDY_workReqIn_put; - - // actionvalue method dmaReadClt4SQ_request_get - input EN_dmaReadClt4SQ_request_get; - output [169 : 0] dmaReadClt4SQ_request_get; - output RDY_dmaReadClt4SQ_request_get; - - // action method dmaReadClt4SQ_response_put - input [382 : 0] dmaReadClt4SQ_response_put; - input EN_dmaReadClt4SQ_response_put; - output RDY_dmaReadClt4SQ_response_put; - - // action method respPktPipeIn_pktMetaData_put - input [648 : 0] respPktPipeIn_pktMetaData_put; - input EN_respPktPipeIn_pktMetaData_put; - output RDY_respPktPipeIn_pktMetaData_put; - - // action method respPktPipeIn_payload_put - input [289 : 0] respPktPipeIn_payload_put; - input EN_respPktPipeIn_payload_put; - output RDY_respPktPipeIn_payload_put; - - // value method statusSQ_comm_isCreate - output statusSQ_comm_isCreate; - output RDY_statusSQ_comm_isCreate; - - // value method statusSQ_comm_isERR - output statusSQ_comm_isERR; - output RDY_statusSQ_comm_isERR; - - // value method statusSQ_comm_isInit - output statusSQ_comm_isInit; - output RDY_statusSQ_comm_isInit; - - // value method statusSQ_comm_isReset - output statusSQ_comm_isReset; - output RDY_statusSQ_comm_isReset; - - // value method statusSQ_comm_isRTR - output statusSQ_comm_isRTR; - output RDY_statusSQ_comm_isRTR; - - // value method statusSQ_comm_isRTS - output statusSQ_comm_isRTS; - output RDY_statusSQ_comm_isRTS; - - // value method statusSQ_comm_isSQD - output statusSQ_comm_isSQD; - output RDY_statusSQ_comm_isSQD; - - // value method statusSQ_comm_isNonErr - output statusSQ_comm_isNonErr; - output RDY_statusSQ_comm_isNonErr; - - // value method statusSQ_comm_isUnknown - output statusSQ_comm_isUnknown; - output RDY_statusSQ_comm_isUnknown; - - // value method statusSQ_comm_isRTR2RTS - output statusSQ_comm_isRTR2RTS; - output RDY_statusSQ_comm_isRTR2RTS; - - // value method statusSQ_comm_isStableRTS - output statusSQ_comm_isStableRTS; - output RDY_statusSQ_comm_isStableRTS; - - // value method statusSQ_comm_getAccessFlags - output [7 : 0] statusSQ_comm_getAccessFlags; - output RDY_statusSQ_comm_getAccessFlags; - - // value method statusSQ_comm_getMaxRnrCnt - output [2 : 0] statusSQ_comm_getMaxRnrCnt; - output RDY_statusSQ_comm_getMaxRnrCnt; - - // value method statusSQ_comm_getMaxRetryCnt - output [2 : 0] statusSQ_comm_getMaxRetryCnt; - output RDY_statusSQ_comm_getMaxRetryCnt; - - // value method statusSQ_comm_getMinRnrTimer - output [4 : 0] statusSQ_comm_getMinRnrTimer; - output RDY_statusSQ_comm_getMinRnrTimer; - - // value method statusSQ_comm_getMaxTimeOut - output [4 : 0] statusSQ_comm_getMaxTimeOut; - output RDY_statusSQ_comm_getMaxTimeOut; - - // value method statusSQ_comm_getPendingWorkReqNum - output [7 : 0] statusSQ_comm_getPendingWorkReqNum; - output RDY_statusSQ_comm_getPendingWorkReqNum; - - // value method statusSQ_comm_getPendingRecvReqNum - output [7 : 0] statusSQ_comm_getPendingRecvReqNum; - output RDY_statusSQ_comm_getPendingRecvReqNum; - - // value method statusSQ_comm_getPendingReadAtomicReqNum - output [7 : 0] statusSQ_comm_getPendingReadAtomicReqNum; - output RDY_statusSQ_comm_getPendingReadAtomicReqNum; - - // value method statusSQ_comm_getPendingDestReadAtomicReqNum - output [7 : 0] statusSQ_comm_getPendingDestReadAtomicReqNum; - output RDY_statusSQ_comm_getPendingDestReadAtomicReqNum; - - // value method statusSQ_comm_getSigAll - output statusSQ_comm_getSigAll; - output RDY_statusSQ_comm_getSigAll; - - // value method statusSQ_comm_getSQPN - output [23 : 0] statusSQ_comm_getSQPN; - output RDY_statusSQ_comm_getSQPN; - - // value method statusSQ_comm_getDQPN - output [23 : 0] statusSQ_comm_getDQPN; - output RDY_statusSQ_comm_getDQPN; - - // value method statusSQ_comm_getPKEY - output [15 : 0] statusSQ_comm_getPKEY; - output RDY_statusSQ_comm_getPKEY; - - // value method statusSQ_comm_getQKEY - output [31 : 0] statusSQ_comm_getQKEY; - output RDY_statusSQ_comm_getQKEY; - - // value method statusSQ_comm_getPMTU - output [2 : 0] statusSQ_comm_getPMTU; - output RDY_statusSQ_comm_getPMTU; - - // value method statusSQ_getTypeQP - output [3 : 0] statusSQ_getTypeQP; - output RDY_statusSQ_getTypeQP; - - // value method statusSQ_isSQ - output statusSQ_isSQ; - output RDY_statusSQ_isSQ; - - // value method rdmaReqPipeOut_first - output [289 : 0] rdmaReqPipeOut_first; - output RDY_rdmaReqPipeOut_first; - - // action method rdmaReqPipeOut_deq - input EN_rdmaReqPipeOut_deq; - output RDY_rdmaReqPipeOut_deq; - - // value method rdmaReqPipeOut_notEmpty - output rdmaReqPipeOut_notEmpty; - output RDY_rdmaReqPipeOut_notEmpty; - - // value method workCompPipeOutSQ_first - output [221 : 0] workCompPipeOutSQ_first; - output RDY_workCompPipeOutSQ_first; - - // action method workCompPipeOutSQ_deq - input EN_workCompPipeOutSQ_deq; - output RDY_workCompPipeOutSQ_deq; - - // value method workCompPipeOutSQ_notEmpty - output workCompPipeOutSQ_notEmpty; - output RDY_workCompPipeOutSQ_notEmpty; - - // signals for module outputs - wire [289 : 0] rdmaReqPipeOut_first; - wire [273 : 0] srvPortQP_response_get; - wire [221 : 0] workCompPipeOutSQ_first; - wire [169 : 0] dmaReadClt4SQ_request_get; - wire [31 : 0] statusSQ_comm_getQKEY; - wire [23 : 0] statusSQ_comm_getDQPN, statusSQ_comm_getSQPN; - wire [15 : 0] statusSQ_comm_getPKEY; - wire [7 : 0] statusSQ_comm_getAccessFlags, - statusSQ_comm_getPendingDestReadAtomicReqNum, - statusSQ_comm_getPendingReadAtomicReqNum, - statusSQ_comm_getPendingRecvReqNum, - statusSQ_comm_getPendingWorkReqNum; - wire [4 : 0] statusSQ_comm_getMaxTimeOut, statusSQ_comm_getMinRnrTimer; - wire [3 : 0] statusSQ_getTypeQP; - wire [2 : 0] statusSQ_comm_getMaxRetryCnt, - statusSQ_comm_getMaxRnrCnt, - statusSQ_comm_getPMTU; - wire RDY_dmaReadClt4SQ_request_get, - RDY_dmaReadClt4SQ_response_put, - RDY_rdmaReqPipeOut_deq, - RDY_rdmaReqPipeOut_first, - RDY_rdmaReqPipeOut_notEmpty, - RDY_respPktPipeIn_payload_put, - RDY_respPktPipeIn_pktMetaData_put, - RDY_srvPortQP_request_put, - RDY_srvPortQP_response_get, - RDY_statusSQ_comm_getAccessFlags, - RDY_statusSQ_comm_getDQPN, - RDY_statusSQ_comm_getMaxRetryCnt, - RDY_statusSQ_comm_getMaxRnrCnt, - RDY_statusSQ_comm_getMaxTimeOut, - RDY_statusSQ_comm_getMinRnrTimer, - RDY_statusSQ_comm_getPKEY, - RDY_statusSQ_comm_getPMTU, - RDY_statusSQ_comm_getPendingDestReadAtomicReqNum, - RDY_statusSQ_comm_getPendingReadAtomicReqNum, - RDY_statusSQ_comm_getPendingRecvReqNum, - RDY_statusSQ_comm_getPendingWorkReqNum, - RDY_statusSQ_comm_getQKEY, - RDY_statusSQ_comm_getSQPN, - RDY_statusSQ_comm_getSigAll, - RDY_statusSQ_comm_isCreate, - RDY_statusSQ_comm_isERR, - RDY_statusSQ_comm_isInit, - RDY_statusSQ_comm_isNonErr, - RDY_statusSQ_comm_isRTR, - RDY_statusSQ_comm_isRTR2RTS, - RDY_statusSQ_comm_isRTS, - RDY_statusSQ_comm_isReset, - RDY_statusSQ_comm_isSQD, - RDY_statusSQ_comm_isStableRTS, - RDY_statusSQ_comm_isUnknown, - RDY_statusSQ_getTypeQP, - RDY_statusSQ_isSQ, - RDY_workCompPipeOutSQ_deq, - RDY_workCompPipeOutSQ_first, - RDY_workCompPipeOutSQ_notEmpty, - RDY_workReqIn_put, - rdmaReqPipeOut_notEmpty, - statusSQ_comm_getSigAll, - statusSQ_comm_isCreate, - statusSQ_comm_isERR, - statusSQ_comm_isInit, - statusSQ_comm_isNonErr, - statusSQ_comm_isRTR, - statusSQ_comm_isRTR2RTS, - statusSQ_comm_isRTS, - statusSQ_comm_isReset, - statusSQ_comm_isSQD, - statusSQ_comm_isStableRTS, - statusSQ_comm_isUnknown, - statusSQ_isSQ, - workCompPipeOutSQ_notEmpty; - - // inlined wires - reg [4 : 0] cntrl_nextStateReg_port0__write_1; - wire [679 : 0] sq_pendingWorkReqBuf_pushReg_port0__read, - sq_pendingWorkReqBuf_pushReg_port0__write_1, - sq_pendingWorkReqBuf_pushReg_port1__read, - sq_pendingWorkReqBuf_pushReg_port1__write_1, - sq_pendingWorkReqBuf_pushReg_port2__read, - sq_pendingWorkReqBuf_pushReg_port2__write_1, - sq_pendingWorkReqBuf_pushReg_port3__read, - sq_pendingWorkReqBuf_pushReg_port3__write_1, - sq_pendingWorkReqBuf_pushReg_port4__read, - sq_pendingWorkReqBuf_pushReg_port4__write_1; - wire [289 : 0] payloadGenerator4SQ_payloadBufQ_wDataIn_wget, - payloadGenerator4SQ_payloadBufQ_wDataOut_wget; - wire [23 : 0] cntrl_epsnReg_port0__read, - cntrl_epsnReg_port0__write_1, - cntrl_epsnReg_port1__read, - cntrl_epsnReg_port1__write_1, - cntrl_epsnReg_port2__read, - cntrl_epsnReg_port2__write_1, - cntrl_epsnReg_port3__read, - cntrl_epsnReg_port3__write_1, - cntrl_epsnReg_port4__read, - cntrl_epsnReg_port4__write_1; - wire [8 : 0] sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port0__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port0__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port2__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port2__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port3__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port3__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port4__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port4__write_1; - wire [4 : 0] cntrl_nextStateReg_port0__read, - cntrl_nextStateReg_port1__read, - cntrl_nextStateReg_port1__write_1, - cntrl_nextStateReg_port2__read, - cntrl_nextStateReg_port2__write_1, - cntrl_nextStateReg_port3__read, - cntrl_nextStateReg_port3__write_1, - cntrl_nextStateReg_port4__read, - cntrl_nextStateReg_port4__write_1, - cntrl_preReqOpCodeReg_port0__read, - cntrl_preReqOpCodeReg_port0__write_1, - cntrl_preReqOpCodeReg_port1__read, - cntrl_preReqOpCodeReg_port1__write_1, - cntrl_preReqOpCodeReg_port2__read, - cntrl_preReqOpCodeReg_port2__write_1, - cntrl_preReqOpCodeReg_port3__read, - cntrl_preReqOpCodeReg_port3__write_1, - cntrl_preReqOpCodeReg_port4__read, - cntrl_preReqOpCodeReg_port4__write_1; - wire [1 : 0] sq_retryHandler_retryCntrlStateReg_port0__read, - sq_retryHandler_retryCntrlStateReg_port0__write_1, - sq_retryHandler_retryCntrlStateReg_port1__read, - sq_retryHandler_retryCntrlStateReg_port1__write_1, - sq_retryHandler_retryCntrlStateReg_port2__read, - sq_retryHandler_retryCntrlStateReg_port2__write_1, - sq_retryHandler_retryCntrlStateReg_port3__read, - sq_retryHandler_retryCntrlStateReg_port3__write_1, - sq_retryHandler_retryCntrlStateReg_port4__read, - sq_retryHandler_retryCntrlStateReg_port4__write_1; - wire _deq_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_wget, - _deq_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_whas, - _deq_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget, - _deq_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas, - _deq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget, - _deq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas, - _deq_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_wget, - _deq_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_whas, - _deq_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_wget, - _deq_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_whas, - _deq_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_wget, - _deq_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_whas, - _deq_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_wget, - _deq_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_whas, - _deq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget, - _deq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas, - _deq_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget, - _deq_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas, - _deq_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget, - _deq_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas, - _deq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_wget, - _deq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_whas, - _deq_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_wget, - _deq_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_whas, - _deq_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget, - _deq_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas, - _deq_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_wget, - _deq_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_whas, - _deq_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_wget, - _deq_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_whas, - _deq_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_wget, - _deq_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_whas, - _deq_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_wget, - _deq_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_whas, - _deq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_wget, - _deq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_whas, - _deq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_wget, - _deq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_whas, - _deq_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_wget, - _deq_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_whas, - _deq_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_respPktPipe_metaDataQ_wget, - _deq_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_respPktPipe_metaDataQ_whas, - _deq_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_wget, - _deq_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_whas, - _deq_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_wget, - _deq_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_whas, - _deq_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_wget, - _deq_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_whas, - _deq_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_wget, - _deq_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_whas, - _deq_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_wget, - _deq_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_whas, - _deq_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_wget, - _deq_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_whas, - _deq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_wget, - _deq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_whas, - _deq_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_wget, - _deq_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_whas, - _deq_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget, - _deq_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas, - _deq_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget, - _deq_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas, - _deq_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget, - _deq_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas, - _deq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_wget, - _deq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_whas, - _deq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget, - _deq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas, - _deq_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget, - _deq_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas, - _enq_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget, - _enq_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas, - _enq_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget, - _enq_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas, - _enq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_reqCountQ_wget, - _enq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_reqCountQ_whas, - _enq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget, - _enq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas, - _enq_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget, - _enq_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas, - _enq_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_pendingWorkReqOutQ_wget, - _enq_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_pendingWorkReqOutQ_whas, - _enq_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_reqHeaderGenQ_wget, - _enq_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_reqHeaderGenQ_whas, - _enq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_payloadGenerator4SQ_payloadGenReqQ_wget, - _enq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_payloadGenerator4SQ_payloadGenReqQ_whas, - _enq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPktNumQ_wget, - _enq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPktNumQ_whas, - _enq_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_pendingWorkReqOutQ_wget, - _enq_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_pendingWorkReqOutQ_whas, - _enq_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_pendingReqHeaderQ_wget, - _enq_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_pendingReqHeaderQ_whas, - _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_psnReqOutQ_wget, - _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_psnReqOutQ_whas, - _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderOutQ_wget, - _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderOutQ_whas, - _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_workCompGenReqOutQ_wget, - _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_workCompGenReqOutQ_whas, - _enq_RL_sq_reqGenSQ_recvWorkReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget, - _enq_RL_sq_reqGenSQ_recvWorkReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas, - _enq_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingLenCheckQ_wget, - _enq_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingLenCheckQ_whas, - _enq_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingLenCalcQ_wget, - _enq_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingLenCalcQ_whas, - _enq_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget, - _enq_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas, - _enq_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingAddrCalcQ_wget, - _enq_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingAddrCalcQ_whas, - _enq_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingDmaReqQ_wget, - _enq_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingDmaReqQ_whas, - _enq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingPermCheckQ_wget, - _enq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingPermCheckQ_whas, - _enq_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_incomingRespQ_wget, - _enq_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_incomingRespQ_whas, - _enq_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_incomingRespQ_wget, - _enq_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_incomingRespQ_whas, - _enq_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_incomingRespQ_wget, - _enq_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_incomingRespQ_whas, - _enq_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_incomingRespQ_wget, - _enq_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_incomingRespQ_whas, - _enq_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget, - _enq_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas, - _enq_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingPermQueryQ_wget, - _enq_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingPermQueryQ_whas, - _enq_RL_sq_respHandleSQ_handleRespByType_EN_sq_retryHandler_retryReqQ_wget, - _enq_RL_sq_respHandleSQ_handleRespByType_EN_sq_retryHandler_retryReqQ_whas, - _enq_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingWorkCompQ_wget, - _enq_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingWorkCompQ_whas, - _enq_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingRetryCheckQ_wget, - _enq_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingRetryCheckQ_whas, - _enq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_pendingRespQ_wget, - _enq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_pendingRespQ_whas, - _enq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_retryHandler_resetReqQ_wget, - _enq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_retryHandler_resetReqQ_whas, - _enq_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_incomingRespQ_wget, - _enq_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_incomingRespQ_whas, - _enq_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget, - _enq_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas, - _enq_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompOutQ4SQ_wget, - _enq_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompOutQ4SQ_whas, - _enq_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget, - _enq_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas, - _enq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget, - _enq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas, - _enq_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget, - _enq_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas, - _first_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_wget, - _first_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_whas, - _first_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget, - _first_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas, - _first_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget, - _first_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas, - _first_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_wget, - _first_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_whas, - _first_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_wget, - _first_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_whas, - _first_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_wget, - _first_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_whas, - _first_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_wget, - _first_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_whas, - _first_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget, - _first_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas, - _first_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget, - _first_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas, - _first_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget, - _first_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas, - _first_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_wget, - _first_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_whas, - _first_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_wget, - _first_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_whas, - _first_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget, - _first_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas, - _first_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_wget, - _first_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_whas, - _first_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_wget, - _first_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_whas, - _first_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_wget, - _first_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_whas, - _first_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_wget, - _first_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_whas, - _first_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_wget, - _first_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_whas, - _first_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_wget, - _first_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_whas, - _first_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_wget, - _first_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_whas, - _first_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_wget, - _first_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_whas, - _first_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_wget, - _first_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_whas, - _first_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_wget, - _first_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_whas, - _first_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_wget, - _first_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_whas, - _first_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_wget, - _first_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_whas, - _first_RL_sq_respHandleSQ_preBuildRespInfo_EN_respPktPipe_metaDataQ_wget, - _first_RL_sq_respHandleSQ_preBuildRespInfo_EN_respPktPipe_metaDataQ_whas, - _first_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_wget, - _first_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_whas, - _first_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_wget, - _first_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_whas, - _first_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_wget, - _first_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_whas, - _first_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget, - _first_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas, - _first_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget, - _first_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas, - _first_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget, - _first_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas, - _first_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_wget, - _first_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_whas, - _first_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget, - _first_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas, - _first_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget, - _first_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_whas, - _i_notEmpty_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_wget, - _i_notEmpty_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_respPktPipe_metaDataQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_respPktPipe_metaDataQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_preBuildRespInfo_EN_respPktPipe_metaDataQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_preBuildRespInfo_EN_respPktPipe_metaDataQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_whas, - _i_notEmpty_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_wget, - _i_notEmpty_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_whas, - _i_notEmpty_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget, - _i_notEmpty_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas, - _i_notEmpty_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget, - _i_notEmpty_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas, - _i_notEmpty_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget, - _i_notEmpty_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas, - _i_notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_wget, - _i_notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_whas, - _i_notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget, - _i_notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas, - _i_notEmpty_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget, - _i_notEmpty_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas, - _i_notFull_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget, - _i_notFull_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas, - _i_notFull_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget, - _i_notFull_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas, - _i_notFull_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_reqCountQ_wget, - _i_notFull_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_reqCountQ_whas, - _i_notFull_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget, - _i_notFull_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas, - _i_notFull_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget, - _i_notFull_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas, - _i_notFull_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_pendingWorkReqOutQ_wget, - _i_notFull_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_pendingWorkReqOutQ_whas, - _i_notFull_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_reqHeaderGenQ_wget, - _i_notFull_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_reqHeaderGenQ_whas, - _i_notFull_RL_sq_reqGenSQ_issuePayloadGenReq_EN_payloadGenerator4SQ_payloadGenReqQ_wget, - _i_notFull_RL_sq_reqGenSQ_issuePayloadGenReq_EN_payloadGenerator4SQ_payloadGenReqQ_whas, - _i_notFull_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPktNumQ_wget, - _i_notFull_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPktNumQ_whas, - _i_notFull_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_pendingWorkReqOutQ_wget, - _i_notFull_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_pendingWorkReqOutQ_whas, - _i_notFull_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_pendingReqHeaderQ_wget, - _i_notFull_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_pendingReqHeaderQ_whas, - _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_psnReqOutQ_wget, - _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_psnReqOutQ_whas, - _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderOutQ_wget, - _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderOutQ_whas, - _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_workCompGenReqOutQ_wget, - _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_workCompGenReqOutQ_whas, - _i_notFull_RL_sq_reqGenSQ_recvWorkReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget, - _i_notFull_RL_sq_reqGenSQ_recvWorkReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas, - _i_notFull_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingLenCheckQ_wget, - _i_notFull_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingLenCheckQ_whas, - _i_notFull_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingLenCalcQ_wget, - _i_notFull_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingLenCalcQ_whas, - _i_notFull_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget, - _i_notFull_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas, - _i_notFull_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingAddrCalcQ_wget, - _i_notFull_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingAddrCalcQ_whas, - _i_notFull_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingDmaReqQ_wget, - _i_notFull_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingDmaReqQ_whas, - _i_notFull_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingPermCheckQ_wget, - _i_notFull_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingPermCheckQ_whas, - _i_notFull_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_incomingRespQ_wget, - _i_notFull_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_incomingRespQ_whas, - _i_notFull_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_incomingRespQ_wget, - _i_notFull_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_incomingRespQ_whas, - _i_notFull_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_incomingRespQ_wget, - _i_notFull_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_incomingRespQ_whas, - _i_notFull_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_incomingRespQ_wget, - _i_notFull_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_incomingRespQ_whas, - _i_notFull_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget, - _i_notFull_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas, - _i_notFull_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingPermQueryQ_wget, - _i_notFull_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingPermQueryQ_whas, - _i_notFull_RL_sq_respHandleSQ_handleRespByType_EN_sq_retryHandler_retryReqQ_wget, - _i_notFull_RL_sq_respHandleSQ_handleRespByType_EN_sq_retryHandler_retryReqQ_whas, - _i_notFull_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingWorkCompQ_wget, - _i_notFull_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingWorkCompQ_whas, - _i_notFull_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingRetryCheckQ_wget, - _i_notFull_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingRetryCheckQ_whas, - _i_notFull_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_pendingRespQ_wget, - _i_notFull_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_pendingRespQ_whas, - _i_notFull_RL_sq_respHandleSQ_recvRespHeader_EN_sq_retryHandler_resetReqQ_wget, - _i_notFull_RL_sq_respHandleSQ_recvRespHeader_EN_sq_retryHandler_resetReqQ_whas, - _i_notFull_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_incomingRespQ_wget, - _i_notFull_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_incomingRespQ_whas, - _i_notFull_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget, - _i_notFull_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas, - _i_notFull_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompOutQ4SQ_wget, - _i_notFull_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompOutQ4SQ_whas, - _i_notFull_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget, - _i_notFull_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas, - _i_notFull_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget, - _i_notFull_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas, - _i_notFull_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget, - _i_notFull_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas, - _notEmpty_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_wget, - _notEmpty_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_whas, - _notEmpty_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_wget, - _notEmpty_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_whas, - _notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_wget, - _notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_whas, - _notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget, - _notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas, - _port0__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_hasTimeOutErrReg_wget, - _port0__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_hasTimeOutErrReg_whas, - _port0__write_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_hasTimeOutErrReg_wget, - _port0__write_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_hasTimeOutErrReg_whas, - _port0__write_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_popReg_wget, - _port0__write_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_popReg_whas, - _port0__write_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_popReg_wget, - _port0__write_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_popReg_whas, - _port0__write_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_hasTimeOutErrReg_wget, - _port0__write_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_hasTimeOutErrReg_whas, - _port0__write_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_hasInternalErrReg_wget, - _port0__write_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_hasInternalErrReg_whas, - _port1__read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_preScanRestartReg_wget, - _port1__read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_preScanRestartReg_whas, - _port1__read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_scanStartReg_wget, - _port1__read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_scanStartReg_whas, - _port1__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_preScanRestartReg_wget, - _port1__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_preScanRestartReg_whas, - _port1__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_scanStartReg_wget, - _port1__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_scanStartReg_whas, - _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_npsnReg_wget, - _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_npsnReg_whas, - _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_sqTypeReg_wget, - _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_sqTypeReg_whas, - _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_sqTypeReg_wget, - _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_sqTypeReg_whas, - _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_curPsnReg_wget, - _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_curPsnReg_whas, - _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isFirstOrOnlyReqPktReg_wget, - _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isFirstOrOnlyReqPktReg_whas, - _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_remainingPktNumReg_wget, - _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_remainingPktNumReg_whas, - _read_RL_sq_reqGenSQ_errFlushWR_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_errFlushWR_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_genReqHeader_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_genReqHeader_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_genReqHeader_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_genReqHeader_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_pmtuReg_wget, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_pmtuReg_whas, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_sqpnReg_wget, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_sqpnReg_whas, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_dqpnReg_wget, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_dqpnReg_whas, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_pkeyReg_wget, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_pkeyReg_whas, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqSigAllReg_wget, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqSigAllReg_whas, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqTypeReg_wget, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqTypeReg_whas, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqpnReg_wget, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqpnReg_whas, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_isNormalStateReg_wget, - _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_isNormalStateReg_whas, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_pmtuReg_wget, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_pmtuReg_whas, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_preStateReg_wget, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_preStateReg_whas, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_sqTypeReg_wget, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_sqTypeReg_whas, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_sqpnReg_wget, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_sqpnReg_whas, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_stateReg_wget, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_stateReg_whas, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_wget, - _read_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_whas, - _read_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_calcReadRespAddr_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_calcReadRespAddr_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_nextReadRespWriteAddrReg_wget, - _read_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_nextReadRespWriteAddrReg_whas, - _read_RL_sq_respHandleSQ_calcReadRespLen_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_calcReadRespLen_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_remainingReadRespLenReg_wget, - _read_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_remainingReadRespLenReg_whas, - _read_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_checkReadRespLen_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_checkReadRespLen_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_checkRetryErr_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_checkRetryErr_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_retryFlushReg_wget, - _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_retryFlushReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_0_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_0_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_1_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_1_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_2_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_2_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_3_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_3_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_deqPtrReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_deqPtrReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_scanStateReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_scanStateReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageDeqPendingWorkReqReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageDeqPendingWorkReqReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageDeqPktMetaDataReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageDeqPktMetaDataReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStagePktMetaDataReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStagePktMetaDataReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageReqPktInfoReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageReqPktInfoReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageRespTypeReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageRespTypeReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageStateReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageStateReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageWorkCompReqTypeReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageWorkCompReqTypeReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageWorkReqAckTypeReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageWorkReqAckTypeReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_recvRetryRespReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_recvRetryRespReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_retryFlushReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_retryFlushReg_whas, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_retryResetReqReg_wget, - _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_retryResetReqReg_whas, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_pendingWorkReqBuf_emptyReg_wget, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_pendingWorkReqBuf_emptyReg_whas, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_retryFlushReg_wget, - _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_retryFlushReg_whas, - _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_pendingWorkReqBuf_emptyReg_wget, - _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_pendingWorkReqBuf_emptyReg_whas, - _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_0_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_0_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_1_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_1_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_2_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_2_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_3_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_3_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_deqPtrReg_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_deqPtrReg_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_scanStateReg_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_scanStateReg_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_genWorkCompSQ_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_genWorkCompSQ_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_handleRespByType_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_handleRespByType_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_preRdmaOpCodeReg_wget, - _read_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_preRdmaOpCodeReg_whas, - _read_RL_sq_respHandleSQ_issueDmaReq_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_issueDmaReq_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_cntrl_npsnReg_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_cntrl_npsnReg_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_0_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_0_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_1_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_1_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_2_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_2_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_3_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_3_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_deqPtrReg_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_deqPtrReg_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_emptyReg_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_emptyReg_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageStateReg_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageStateReg_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_retryFlushReg_wget, - _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_retryFlushReg_whas, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_pendingWorkReqBuf_emptyReg_wget, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_pendingWorkReqBuf_emptyReg_whas, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStagePktMetaDataReg_wget, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStagePktMetaDataReg_whas, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageRespAndWorkReqRelationReg_wget, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageRespAndWorkReqRelationReg_whas, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageRespTypeReg_wget, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageRespTypeReg_whas, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageStateReg_wget, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageStateReg_whas, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_retryFlushReg_wget, - _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_retryFlushReg_whas, - _read_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_cntrl_preStateReg_wget, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_cntrl_preStateReg_whas, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_retryFlushReg_wget, - _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_retryFlushReg_whas, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_pendingWorkReqBuf_emptyReg_wget, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_pendingWorkReqBuf_emptyReg_whas, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_retryFlushReg_wget, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_retryFlushReg_whas, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_retryHandler_retryHandleStateReg_wget, - _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_retryHandler_retryHandleStateReg_whas, - _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_cntrl_stateReg_wget, - _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_cntrl_stateReg_whas, - _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_errOccurredReg_wget, - _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_errOccurredReg_whas, - _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_recvErrRespReg_wget, - _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_recvErrRespReg_whas, - _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_retryFlushReg_wget, - _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_retryFlushReg_whas, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_pkeyReg_wget, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_pkeyReg_whas, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_preStateReg_wget, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_preStateReg_whas, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_sqSigAllReg_wget, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_sqSigAllReg_whas, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_sqpnReg_wget, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_sqpnReg_whas, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_stateReg_wget, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_stateReg_whas, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget, - _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas, - _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_cntrl_preStateReg_wget, - _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_cntrl_preStateReg_whas, - _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_cntrl_stateReg_wget, - _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_cntrl_stateReg_whas, - _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget, - _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas, - _read_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_cntrl_stateReg_wget, - _read_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_cntrl_stateReg_whas, - _read_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget, - _read_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas, - _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_cntrl_preStateReg_wget, - _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_cntrl_preStateReg_whas, - _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_cntrl_stateReg_wget, - _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_cntrl_stateReg_whas, - _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget, - _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas, - _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_cntrl_preStateReg_wget, - _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_cntrl_preStateReg_whas, - _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_cntrl_stateReg_wget, - _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_cntrl_stateReg_whas, - _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget, - _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas, - _write_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_npsnReg_wget, - _write_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_npsnReg_whas, - _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_curPsnReg_wget, - _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_curPsnReg_whas, - _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isFirstOrOnlyReqPktReg_wget, - _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isFirstOrOnlyReqPktReg_whas, - _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_remainingPktNumReg_wget, - _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_remainingPktNumReg_whas, - _write_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_isNormalStateReg_wget, - _write_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_isNormalStateReg_whas, - _write_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageStateReg_wget, - _write_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageStateReg_whas, - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_preRdmaOpCodeReg_wget, - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_preRdmaOpCodeReg_whas, - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_wget, - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_whas, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStagePktMetaDataReg_wget, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStagePktMetaDataReg_whas, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageReqPktInfoReg_wget, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageReqPktInfoReg_whas, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageRespAndWorkReqRelationReg_wget, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageRespAndWorkReqRelationReg_whas, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageRespTypeReg_wget, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageRespTypeReg_whas, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageStateReg_wget, - _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageStateReg_whas, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageDeqPendingWorkReqReg_wget, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageDeqPendingWorkReqReg_whas, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageDeqPktMetaDataReg_wget, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageDeqPktMetaDataReg_whas, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageStateReg_wget, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageStateReg_whas, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageWorkCompReqTypeReg_wget, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageWorkCompReqTypeReg_whas, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageWorkReqAckTypeReg_wget, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageWorkReqAckTypeReg_whas, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_retryResetReqReg_wget, - _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_retryResetReqReg_whas, - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget, - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_whas, - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_wget, - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_whas, - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_retryFlushReg_wget, - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_retryFlushReg_whas, - _write_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_recvRetryRespReg_wget, - _write_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_recvRetryRespReg_whas, - _write_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_retryFlushReg_wget, - _write_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_retryFlushReg_whas, - _write_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_preStageStateReg_wget, - _write_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_preStageStateReg_whas, - _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_wget, - _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_whas, - _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_wget, - _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_whas, - _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget, - _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas, - cntrl_epsnReg_EN_port0__write, - cntrl_epsnReg_EN_port1__write, - cntrl_epsnReg_EN_port2__write, - cntrl_epsnReg_EN_port3__write, - cntrl_epsnReg_EN_port4__write, - cntrl_nextStateReg_EN_port0__write, - cntrl_nextStateReg_EN_port1__write, - cntrl_nextStateReg_EN_port2__write, - cntrl_nextStateReg_EN_port3__write, - cntrl_nextStateReg_EN_port4__write, - cntrl_preReqOpCodeReg_EN_port0__write, - cntrl_preReqOpCodeReg_EN_port1__write, - cntrl_preReqOpCodeReg_EN_port2__write, - cntrl_preReqOpCodeReg_EN_port3__write, - cntrl_preReqOpCodeReg_EN_port4__write, - cntrl_qpDestroyReg_EN_port0__write, - cntrl_qpDestroyReg_EN_port1__write, - cntrl_qpDestroyReg_EN_port2__write, - cntrl_qpDestroyReg_EN_port3__write, - cntrl_qpDestroyReg_EN_port4__write, - cntrl_qpDestroyReg_port0__read, - cntrl_qpDestroyReg_port0__write_1, - cntrl_qpDestroyReg_port1__read, - cntrl_qpDestroyReg_port1__write_1, - cntrl_qpDestroyReg_port2__read, - cntrl_qpDestroyReg_port2__write_1, - cntrl_qpDestroyReg_port3__read, - cntrl_qpDestroyReg_port3__write_1, - cntrl_qpDestroyReg_port4__read, - cntrl_qpDestroyReg_port4__write_1, - cntrl_setStateErrReg_EN_port0__write, - cntrl_setStateErrReg_EN_port1__write, - cntrl_setStateErrReg_EN_port2__write, - cntrl_setStateErrReg_EN_port3__write, - cntrl_setStateErrReg_EN_port4__write, - cntrl_setStateErrReg_port0__read, - cntrl_setStateErrReg_port0__write_1, - cntrl_setStateErrReg_port1__read, - cntrl_setStateErrReg_port1__write_1, - cntrl_setStateErrReg_port2__read, - cntrl_setStateErrReg_port2__write_1, - cntrl_setStateErrReg_port3__read, - cntrl_setStateErrReg_port3__write_1, - cntrl_setStateErrReg_port4__read, - cntrl_setStateErrReg_port4__write_1, - dmaReadCntrl4SQ_cancelReg_EN_port0__write, - dmaReadCntrl4SQ_cancelReg_EN_port1__write, - dmaReadCntrl4SQ_cancelReg_EN_port2__write, - dmaReadCntrl4SQ_cancelReg_EN_port3__write, - dmaReadCntrl4SQ_cancelReg_EN_port4__write, - dmaReadCntrl4SQ_cancelReg_port0__read, - dmaReadCntrl4SQ_cancelReg_port0__write_1, - dmaReadCntrl4SQ_cancelReg_port1__read, - dmaReadCntrl4SQ_cancelReg_port1__write_1, - dmaReadCntrl4SQ_cancelReg_port2__read, - dmaReadCntrl4SQ_cancelReg_port2__write_1, - dmaReadCntrl4SQ_cancelReg_port3__read, - dmaReadCntrl4SQ_cancelReg_port3__write_1, - dmaReadCntrl4SQ_cancelReg_port4__read, - dmaReadCntrl4SQ_cancelReg_port4__write_1, - dmaReadCntrl4SQ_gracefulStopReg_EN_port0__write, - dmaReadCntrl4SQ_gracefulStopReg_EN_port1__write, - dmaReadCntrl4SQ_gracefulStopReg_EN_port2__write, - dmaReadCntrl4SQ_gracefulStopReg_EN_port3__write, - dmaReadCntrl4SQ_gracefulStopReg_EN_port4__write, - dmaReadCntrl4SQ_gracefulStopReg_port0__read, - dmaReadCntrl4SQ_gracefulStopReg_port0__write_1, - dmaReadCntrl4SQ_gracefulStopReg_port1__read, - dmaReadCntrl4SQ_gracefulStopReg_port1__write_1, - dmaReadCntrl4SQ_gracefulStopReg_port2__read, - dmaReadCntrl4SQ_gracefulStopReg_port2__write_1, - dmaReadCntrl4SQ_gracefulStopReg_port3__read, - dmaReadCntrl4SQ_gracefulStopReg_port3__write_1, - dmaReadCntrl4SQ_gracefulStopReg_port4__read, - dmaReadCntrl4SQ_gracefulStopReg_port4__write_1, - payloadGenerator4SQ_payloadBufQ_pwClear_whas, - payloadGenerator4SQ_payloadBufQ_pwDequeue_whas, - payloadGenerator4SQ_payloadBufQ_pwEnqueue_whas, - payloadGenerator4SQ_payloadBufQ_wDataIn_whas, - payloadGenerator4SQ_payloadBufQ_wDataOut_whas, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port0__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port1__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port2__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port3__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port4__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port0__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port0__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port2__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port2__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port3__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port3__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port4__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port4__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port0__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port1__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port2__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port3__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port4__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port0__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port0__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port2__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port2__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port3__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port3__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port4__read, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port4__write_1, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port0__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port1__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port2__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port3__write, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port4__write, - sq_pendingWorkReqBuf_clearReg_EN_port0__write, - sq_pendingWorkReqBuf_clearReg_EN_port1__write, - sq_pendingWorkReqBuf_clearReg_EN_port2__write, - sq_pendingWorkReqBuf_clearReg_EN_port3__write, - sq_pendingWorkReqBuf_clearReg_EN_port4__write, - sq_pendingWorkReqBuf_clearReg_port0__read, - sq_pendingWorkReqBuf_clearReg_port0__write_1, - sq_pendingWorkReqBuf_clearReg_port1__read, - sq_pendingWorkReqBuf_clearReg_port1__write_1, - sq_pendingWorkReqBuf_clearReg_port2__read, - sq_pendingWorkReqBuf_clearReg_port2__write_1, - sq_pendingWorkReqBuf_clearReg_port3__read, - sq_pendingWorkReqBuf_clearReg_port3__write_1, - sq_pendingWorkReqBuf_clearReg_port4__read, - sq_pendingWorkReqBuf_clearReg_port4__write_1, - sq_pendingWorkReqBuf_popReg_EN_port0__write, - sq_pendingWorkReqBuf_popReg_EN_port1__write, - sq_pendingWorkReqBuf_popReg_EN_port2__write, - sq_pendingWorkReqBuf_popReg_EN_port3__write, - sq_pendingWorkReqBuf_popReg_EN_port4__write, - sq_pendingWorkReqBuf_popReg_port0__read, - sq_pendingWorkReqBuf_popReg_port0__write_1, - sq_pendingWorkReqBuf_popReg_port1__read, - sq_pendingWorkReqBuf_popReg_port1__write_1, - sq_pendingWorkReqBuf_popReg_port2__read, - sq_pendingWorkReqBuf_popReg_port2__write_1, - sq_pendingWorkReqBuf_popReg_port3__read, - sq_pendingWorkReqBuf_popReg_port3__write_1, - sq_pendingWorkReqBuf_popReg_port4__read, - sq_pendingWorkReqBuf_popReg_port4__write_1, - sq_pendingWorkReqBuf_preScanRestartReg_EN_port0__write, - sq_pendingWorkReqBuf_preScanRestartReg_EN_port1__write, - sq_pendingWorkReqBuf_preScanRestartReg_EN_port2__write, - sq_pendingWorkReqBuf_preScanRestartReg_EN_port3__write, - sq_pendingWorkReqBuf_preScanRestartReg_EN_port4__write, - sq_pendingWorkReqBuf_preScanRestartReg_port0__read, - sq_pendingWorkReqBuf_preScanRestartReg_port0__write_1, - sq_pendingWorkReqBuf_preScanRestartReg_port1__read, - sq_pendingWorkReqBuf_preScanRestartReg_port1__write_1, - sq_pendingWorkReqBuf_preScanRestartReg_port2__read, - sq_pendingWorkReqBuf_preScanRestartReg_port2__write_1, - sq_pendingWorkReqBuf_preScanRestartReg_port3__read, - sq_pendingWorkReqBuf_preScanRestartReg_port3__write_1, - sq_pendingWorkReqBuf_preScanRestartReg_port4__read, - sq_pendingWorkReqBuf_preScanRestartReg_port4__write_1, - sq_pendingWorkReqBuf_preScanStartReg_EN_port0__write, - sq_pendingWorkReqBuf_preScanStartReg_EN_port1__write, - sq_pendingWorkReqBuf_preScanStartReg_EN_port2__write, - sq_pendingWorkReqBuf_preScanStartReg_EN_port3__write, - sq_pendingWorkReqBuf_preScanStartReg_EN_port4__write, - sq_pendingWorkReqBuf_preScanStartReg_port0__read, - sq_pendingWorkReqBuf_preScanStartReg_port0__write_1, - sq_pendingWorkReqBuf_preScanStartReg_port1__read, - sq_pendingWorkReqBuf_preScanStartReg_port1__write_1, - sq_pendingWorkReqBuf_preScanStartReg_port2__read, - sq_pendingWorkReqBuf_preScanStartReg_port2__write_1, - sq_pendingWorkReqBuf_preScanStartReg_port3__read, - sq_pendingWorkReqBuf_preScanStartReg_port3__write_1, - sq_pendingWorkReqBuf_preScanStartReg_port4__read, - sq_pendingWorkReqBuf_preScanStartReg_port4__write_1, - sq_pendingWorkReqBuf_pushReg_EN_port0__write, - sq_pendingWorkReqBuf_pushReg_EN_port1__write, - sq_pendingWorkReqBuf_pushReg_EN_port2__write, - sq_pendingWorkReqBuf_pushReg_EN_port3__write, - sq_pendingWorkReqBuf_pushReg_EN_port4__write, - sq_pendingWorkReqBuf_scanDoneReg_EN_port0__write, - sq_pendingWorkReqBuf_scanDoneReg_EN_port1__write, - sq_pendingWorkReqBuf_scanDoneReg_EN_port2__write, - sq_pendingWorkReqBuf_scanDoneReg_EN_port3__write, - sq_pendingWorkReqBuf_scanDoneReg_EN_port4__write, - sq_pendingWorkReqBuf_scanDoneReg_port0__read, - sq_pendingWorkReqBuf_scanDoneReg_port0__write_1, - sq_pendingWorkReqBuf_scanDoneReg_port1__read, - sq_pendingWorkReqBuf_scanDoneReg_port1__write_1, - sq_pendingWorkReqBuf_scanDoneReg_port2__read, - sq_pendingWorkReqBuf_scanDoneReg_port2__write_1, - sq_pendingWorkReqBuf_scanDoneReg_port3__read, - sq_pendingWorkReqBuf_scanDoneReg_port3__write_1, - sq_pendingWorkReqBuf_scanDoneReg_port4__read, - sq_pendingWorkReqBuf_scanDoneReg_port4__write_1, - sq_pendingWorkReqBuf_scanStartReg_EN_port0__write, - sq_pendingWorkReqBuf_scanStartReg_EN_port1__write, - sq_pendingWorkReqBuf_scanStartReg_EN_port2__write, - sq_pendingWorkReqBuf_scanStartReg_EN_port3__write, - sq_pendingWorkReqBuf_scanStartReg_EN_port4__write, - sq_pendingWorkReqBuf_scanStartReg_port0__read, - sq_pendingWorkReqBuf_scanStartReg_port0__write_1, - sq_pendingWorkReqBuf_scanStartReg_port1__read, - sq_pendingWorkReqBuf_scanStartReg_port1__write_1, - sq_pendingWorkReqBuf_scanStartReg_port2__read, - sq_pendingWorkReqBuf_scanStartReg_port2__write_1, - sq_pendingWorkReqBuf_scanStartReg_port3__read, - sq_pendingWorkReqBuf_scanStartReg_port3__write_1, - sq_pendingWorkReqBuf_scanStartReg_port4__read, - sq_pendingWorkReqBuf_scanStartReg_port4__write_1, - sq_pendingWorkReqBuf_scanStopReg_EN_port0__write, - sq_pendingWorkReqBuf_scanStopReg_EN_port1__write, - sq_pendingWorkReqBuf_scanStopReg_EN_port2__write, - sq_pendingWorkReqBuf_scanStopReg_EN_port3__write, - sq_pendingWorkReqBuf_scanStopReg_EN_port4__write, - sq_pendingWorkReqBuf_scanStopReg_port0__read, - sq_pendingWorkReqBuf_scanStopReg_port0__write_1, - sq_pendingWorkReqBuf_scanStopReg_port1__read, - sq_pendingWorkReqBuf_scanStopReg_port1__write_1, - sq_pendingWorkReqBuf_scanStopReg_port2__read, - sq_pendingWorkReqBuf_scanStopReg_port2__write_1, - sq_pendingWorkReqBuf_scanStopReg_port3__read, - sq_pendingWorkReqBuf_scanStopReg_port3__write_1, - sq_pendingWorkReqBuf_scanStopReg_port4__read, - sq_pendingWorkReqBuf_scanStopReg_port4__write_1, - sq_respHandleSQ_hasInternalErrReg_EN_port0__write, - sq_respHandleSQ_hasInternalErrReg_EN_port1__write, - sq_respHandleSQ_hasInternalErrReg_EN_port2__write, - sq_respHandleSQ_hasInternalErrReg_EN_port3__write, - sq_respHandleSQ_hasInternalErrReg_EN_port4__write, - sq_respHandleSQ_hasInternalErrReg_port0__read, - sq_respHandleSQ_hasInternalErrReg_port0__write_1, - sq_respHandleSQ_hasInternalErrReg_port1__read, - sq_respHandleSQ_hasInternalErrReg_port1__write_1, - sq_respHandleSQ_hasInternalErrReg_port2__read, - sq_respHandleSQ_hasInternalErrReg_port2__write_1, - sq_respHandleSQ_hasInternalErrReg_port3__read, - sq_respHandleSQ_hasInternalErrReg_port3__write_1, - sq_respHandleSQ_hasInternalErrReg_port4__read, - sq_respHandleSQ_hasInternalErrReg_port4__write_1, - sq_respHandleSQ_hasTimeOutErrReg_EN_port0__write, - sq_respHandleSQ_hasTimeOutErrReg_EN_port1__write, - sq_respHandleSQ_hasTimeOutErrReg_EN_port2__write, - sq_respHandleSQ_hasTimeOutErrReg_EN_port3__write, - sq_respHandleSQ_hasTimeOutErrReg_EN_port4__write, - sq_respHandleSQ_hasTimeOutErrReg_port0__read, - sq_respHandleSQ_hasTimeOutErrReg_port0__write_1, - sq_respHandleSQ_hasTimeOutErrReg_port1__read, - sq_respHandleSQ_hasTimeOutErrReg_port1__write_1, - sq_respHandleSQ_hasTimeOutErrReg_port2__read, - sq_respHandleSQ_hasTimeOutErrReg_port2__write_1, - sq_respHandleSQ_hasTimeOutErrReg_port3__read, - sq_respHandleSQ_hasTimeOutErrReg_port3__write_1, - sq_respHandleSQ_hasTimeOutErrReg_port4__read, - sq_respHandleSQ_hasTimeOutErrReg_port4__write_1, - sq_retryHandler_retryCntrlStateReg_EN_port0__write, - sq_retryHandler_retryCntrlStateReg_EN_port1__write, - sq_retryHandler_retryCntrlStateReg_EN_port2__write, - sq_retryHandler_retryCntrlStateReg_EN_port3__write, - sq_retryHandler_retryCntrlStateReg_EN_port4__write; - - // register cntrl_dqpnReg - reg [23 : 0] cntrl_dqpnReg; - wire [23 : 0] cntrl_dqpnReg_D_IN; - wire cntrl_dqpnReg_EN; - - // register cntrl_epsnReg - reg [23 : 0] cntrl_epsnReg; - wire [23 : 0] cntrl_epsnReg_D_IN; - wire cntrl_epsnReg_EN; - - // register cntrl_errFlushDoneReg - reg cntrl_errFlushDoneReg; - wire cntrl_errFlushDoneReg_D_IN, cntrl_errFlushDoneReg_EN; - - // register cntrl_maxRetryCntReg - reg [2 : 0] cntrl_maxRetryCntReg; - wire [2 : 0] cntrl_maxRetryCntReg_D_IN; - wire cntrl_maxRetryCntReg_EN; - - // register cntrl_maxRnrCntReg - reg [2 : 0] cntrl_maxRnrCntReg; - wire [2 : 0] cntrl_maxRnrCntReg_D_IN; - wire cntrl_maxRnrCntReg_EN; - - // register cntrl_maxTimeOutReg - reg [4 : 0] cntrl_maxTimeOutReg; - wire [4 : 0] cntrl_maxTimeOutReg_D_IN; - wire cntrl_maxTimeOutReg_EN; - - // register cntrl_minRnrTimerReg - reg [4 : 0] cntrl_minRnrTimerReg; - wire [4 : 0] cntrl_minRnrTimerReg_D_IN; - wire cntrl_minRnrTimerReg_EN; - - // register cntrl_nextStateReg - reg [4 : 0] cntrl_nextStateReg; - wire [4 : 0] cntrl_nextStateReg_D_IN; - wire cntrl_nextStateReg_EN; - - // register cntrl_npsnReg - reg [23 : 0] cntrl_npsnReg; - wire [23 : 0] cntrl_npsnReg_D_IN; - wire cntrl_npsnReg_EN; - - // register cntrl_pendingDestReadAtomicReqNumReg - reg [7 : 0] cntrl_pendingDestReadAtomicReqNumReg; - wire [7 : 0] cntrl_pendingDestReadAtomicReqNumReg_D_IN; - wire cntrl_pendingDestReadAtomicReqNumReg_EN; - - // register cntrl_pendingReadAtomicReqNumReg - reg [7 : 0] cntrl_pendingReadAtomicReqNumReg; - wire [7 : 0] cntrl_pendingReadAtomicReqNumReg_D_IN; - wire cntrl_pendingReadAtomicReqNumReg_EN; - - // register cntrl_pendingRecvReqNumReg - reg [7 : 0] cntrl_pendingRecvReqNumReg; - wire [7 : 0] cntrl_pendingRecvReqNumReg_D_IN; - wire cntrl_pendingRecvReqNumReg_EN; - - // register cntrl_pendingWorkReqNumReg - reg [7 : 0] cntrl_pendingWorkReqNumReg; - wire [7 : 0] cntrl_pendingWorkReqNumReg_D_IN; - wire cntrl_pendingWorkReqNumReg_EN; - - // register cntrl_pkeyReg - reg [15 : 0] cntrl_pkeyReg; - wire [15 : 0] cntrl_pkeyReg_D_IN; - wire cntrl_pkeyReg_EN; - - // register cntrl_pmtuReg - reg [2 : 0] cntrl_pmtuReg; - wire [2 : 0] cntrl_pmtuReg_D_IN; - wire cntrl_pmtuReg_EN; - - // register cntrl_preReqOpCodeReg - reg [4 : 0] cntrl_preReqOpCodeReg; - wire [4 : 0] cntrl_preReqOpCodeReg_D_IN; - wire cntrl_preReqOpCodeReg_EN; - - // register cntrl_preStateReg - reg [3 : 0] cntrl_preStateReg; - wire [3 : 0] cntrl_preStateReg_D_IN; - wire cntrl_preStateReg_EN; - - // register cntrl_qkeyReg - reg [31 : 0] cntrl_qkeyReg; - wire [31 : 0] cntrl_qkeyReg_D_IN; - wire cntrl_qkeyReg_EN; - - // register cntrl_qpAccessFlagsReg - reg [7 : 0] cntrl_qpAccessFlagsReg; - wire [7 : 0] cntrl_qpAccessFlagsReg_D_IN; - wire cntrl_qpAccessFlagsReg_EN; - - // register cntrl_qpDestroyReg - reg cntrl_qpDestroyReg; - wire cntrl_qpDestroyReg_D_IN, cntrl_qpDestroyReg_EN; - - // register cntrl_setStateErrReg - reg cntrl_setStateErrReg; - wire cntrl_setStateErrReg_D_IN, cntrl_setStateErrReg_EN; - - // register cntrl_sqSigAllReg - reg cntrl_sqSigAllReg; - wire cntrl_sqSigAllReg_D_IN, cntrl_sqSigAllReg_EN; - - // register cntrl_sqTypeReg - reg [3 : 0] cntrl_sqTypeReg; - wire [3 : 0] cntrl_sqTypeReg_D_IN; - wire cntrl_sqTypeReg_EN; - - // register cntrl_sqpnReg - reg [23 : 0] cntrl_sqpnReg; - wire [23 : 0] cntrl_sqpnReg_D_IN; - wire cntrl_sqpnReg_EN; - - // register cntrl_stateReg - reg [3 : 0] cntrl_stateReg; - wire [3 : 0] cntrl_stateReg_D_IN; - wire cntrl_stateReg_EN; - - // register dmaReadCntrl4SQ_addrChunkSrv_busyReg - reg dmaReadCntrl4SQ_addrChunkSrv_busyReg; - reg dmaReadCntrl4SQ_addrChunkSrv_busyReg_D_IN; - wire dmaReadCntrl4SQ_addrChunkSrv_busyReg_EN; - - // register dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg - reg [63 : 0] dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg; - wire [63 : 0] dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_D_IN; - wire dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_EN; - - // register dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg - reg [12 : 0] dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg; - reg [12 : 0] dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_D_IN; - wire dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_EN; - - // register dmaReadCntrl4SQ_addrChunkSrv_isFirstReg - reg dmaReadCntrl4SQ_addrChunkSrv_isFirstReg; - wire dmaReadCntrl4SQ_addrChunkSrv_isFirstReg_D_IN, - dmaReadCntrl4SQ_addrChunkSrv_isFirstReg_EN; - - // register dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg - reg dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg; - wire dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg_D_IN, - dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg_EN; - - // register dmaReadCntrl4SQ_addrChunkSrv_pktNumReg - reg [24 : 0] dmaReadCntrl4SQ_addrChunkSrv_pktNumReg; - wire [24 : 0] dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_D_IN; - wire dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_EN; - - // register dmaReadCntrl4SQ_addrChunkSrv_pmtuReg - reg [2 : 0] dmaReadCntrl4SQ_addrChunkSrv_pmtuReg; - wire [2 : 0] dmaReadCntrl4SQ_addrChunkSrv_pmtuReg_D_IN; - wire dmaReadCntrl4SQ_addrChunkSrv_pmtuReg_EN; - - // register dmaReadCntrl4SQ_addrChunkSrv_residueReg - reg [11 : 0] dmaReadCntrl4SQ_addrChunkSrv_residueReg; - wire [11 : 0] dmaReadCntrl4SQ_addrChunkSrv_residueReg_D_IN; - wire dmaReadCntrl4SQ_addrChunkSrv_residueReg_EN; - - // register dmaReadCntrl4SQ_cancelReg - reg dmaReadCntrl4SQ_cancelReg; - wire dmaReadCntrl4SQ_cancelReg_D_IN, dmaReadCntrl4SQ_cancelReg_EN; - - // register dmaReadCntrl4SQ_gracefulStopReg - reg dmaReadCntrl4SQ_gracefulStopReg; - wire dmaReadCntrl4SQ_gracefulStopReg_D_IN, - dmaReadCntrl4SQ_gracefulStopReg_EN; - - // register payloadGenerator4SQ_isNormalStateReg - reg payloadGenerator4SQ_isNormalStateReg; - wire payloadGenerator4SQ_isNormalStateReg_D_IN, - payloadGenerator4SQ_isNormalStateReg_EN; - - // register payloadGenerator4SQ_payloadBufQ_rCache - reg [300 : 0] payloadGenerator4SQ_payloadBufQ_rCache; - wire [300 : 0] payloadGenerator4SQ_payloadBufQ_rCache_D_IN; - wire payloadGenerator4SQ_payloadBufQ_rCache_EN; - - // register payloadGenerator4SQ_payloadBufQ_rRdPtr - reg [9 : 0] payloadGenerator4SQ_payloadBufQ_rRdPtr; - wire [9 : 0] payloadGenerator4SQ_payloadBufQ_rRdPtr_D_IN; - wire payloadGenerator4SQ_payloadBufQ_rRdPtr_EN; - - // register payloadGenerator4SQ_payloadBufQ_rWrPtr - reg [9 : 0] payloadGenerator4SQ_payloadBufQ_rWrPtr; - wire [9 : 0] payloadGenerator4SQ_payloadBufQ_rWrPtr_D_IN; - wire payloadGenerator4SQ_payloadBufQ_rWrPtr_EN; - - // register rqDmaReadCancelReg - reg rqDmaReadCancelReg; - wire rqDmaReadCancelReg_D_IN, rqDmaReadCancelReg_EN; - - // register rqDmaWriteCancelReg - reg rqDmaWriteCancelReg; - wire rqDmaWriteCancelReg_D_IN, rqDmaWriteCancelReg_EN; - - // register sqDmaReadCancelReg - reg sqDmaReadCancelReg; - wire sqDmaReadCancelReg_D_IN, sqDmaReadCancelReg_EN; - - // register sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg - reg [7 : 0] sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg; - wire [7 : 0] sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_D_IN; - wire sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_EN; - - // register sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg - reg sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg; - wire sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_D_IN, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN; - - // register sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg - reg sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg; - wire sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_D_IN, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN; - - // register sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg - reg [8 : 0] sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg; - wire [8 : 0] sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_D_IN; - wire sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN; - - // register sq_pendingWorkReqBuf_clearReg - reg sq_pendingWorkReqBuf_clearReg; - wire sq_pendingWorkReqBuf_clearReg_D_IN, sq_pendingWorkReqBuf_clearReg_EN; - - // register sq_pendingWorkReqBuf_dataVec_0 - reg [678 : 0] sq_pendingWorkReqBuf_dataVec_0; - wire [678 : 0] sq_pendingWorkReqBuf_dataVec_0_D_IN; - wire sq_pendingWorkReqBuf_dataVec_0_EN; - - // register sq_pendingWorkReqBuf_dataVec_1 - reg [678 : 0] sq_pendingWorkReqBuf_dataVec_1; - wire [678 : 0] sq_pendingWorkReqBuf_dataVec_1_D_IN; - wire sq_pendingWorkReqBuf_dataVec_1_EN; - - // register sq_pendingWorkReqBuf_dataVec_2 - reg [678 : 0] sq_pendingWorkReqBuf_dataVec_2; - wire [678 : 0] sq_pendingWorkReqBuf_dataVec_2_D_IN; - wire sq_pendingWorkReqBuf_dataVec_2_EN; - - // register sq_pendingWorkReqBuf_dataVec_3 - reg [678 : 0] sq_pendingWorkReqBuf_dataVec_3; - wire [678 : 0] sq_pendingWorkReqBuf_dataVec_3_D_IN; - wire sq_pendingWorkReqBuf_dataVec_3_EN; - - // register sq_pendingWorkReqBuf_deqPtrReg - reg [1 : 0] sq_pendingWorkReqBuf_deqPtrReg; - wire [1 : 0] sq_pendingWorkReqBuf_deqPtrReg_D_IN; - wire sq_pendingWorkReqBuf_deqPtrReg_EN; - - // register sq_pendingWorkReqBuf_emptyReg - reg sq_pendingWorkReqBuf_emptyReg; - wire sq_pendingWorkReqBuf_emptyReg_D_IN, sq_pendingWorkReqBuf_emptyReg_EN; - - // register sq_pendingWorkReqBuf_enqPtrReg - reg [1 : 0] sq_pendingWorkReqBuf_enqPtrReg; - wire [1 : 0] sq_pendingWorkReqBuf_enqPtrReg_D_IN; - wire sq_pendingWorkReqBuf_enqPtrReg_EN; - - // register sq_pendingWorkReqBuf_fullReg - reg sq_pendingWorkReqBuf_fullReg; - wire sq_pendingWorkReqBuf_fullReg_D_IN, sq_pendingWorkReqBuf_fullReg_EN; - - // register sq_pendingWorkReqBuf_headReg - reg [679 : 0] sq_pendingWorkReqBuf_headReg; - wire [679 : 0] sq_pendingWorkReqBuf_headReg_D_IN; - wire sq_pendingWorkReqBuf_headReg_EN; - - // register sq_pendingWorkReqBuf_popReg - reg sq_pendingWorkReqBuf_popReg; - wire sq_pendingWorkReqBuf_popReg_D_IN, sq_pendingWorkReqBuf_popReg_EN; - - // register sq_pendingWorkReqBuf_preScanRestartReg - reg sq_pendingWorkReqBuf_preScanRestartReg; - wire sq_pendingWorkReqBuf_preScanRestartReg_D_IN, - sq_pendingWorkReqBuf_preScanRestartReg_EN; - - // register sq_pendingWorkReqBuf_preScanStartReg - reg sq_pendingWorkReqBuf_preScanStartReg; - wire sq_pendingWorkReqBuf_preScanStartReg_D_IN, - sq_pendingWorkReqBuf_preScanStartReg_EN; - - // register sq_pendingWorkReqBuf_pushReg - reg [679 : 0] sq_pendingWorkReqBuf_pushReg; - wire [679 : 0] sq_pendingWorkReqBuf_pushReg_D_IN; - wire sq_pendingWorkReqBuf_pushReg_EN; - - // register sq_pendingWorkReqBuf_scanAlmostDoneReg - reg sq_pendingWorkReqBuf_scanAlmostDoneReg; - wire sq_pendingWorkReqBuf_scanAlmostDoneReg_D_IN, - sq_pendingWorkReqBuf_scanAlmostDoneReg_EN; - - // register sq_pendingWorkReqBuf_scanDoneReg - reg sq_pendingWorkReqBuf_scanDoneReg; - wire sq_pendingWorkReqBuf_scanDoneReg_D_IN, - sq_pendingWorkReqBuf_scanDoneReg_EN; - - // register sq_pendingWorkReqBuf_scanPtrReg - reg [1 : 0] sq_pendingWorkReqBuf_scanPtrReg; - wire [1 : 0] sq_pendingWorkReqBuf_scanPtrReg_D_IN; - wire sq_pendingWorkReqBuf_scanPtrReg_EN; - - // register sq_pendingWorkReqBuf_scanStartReg - reg sq_pendingWorkReqBuf_scanStartReg; - wire sq_pendingWorkReqBuf_scanStartReg_D_IN, - sq_pendingWorkReqBuf_scanStartReg_EN; - - // register sq_pendingWorkReqBuf_scanStateReg - reg [1 : 0] sq_pendingWorkReqBuf_scanStateReg; - reg [1 : 0] sq_pendingWorkReqBuf_scanStateReg_D_IN; - wire sq_pendingWorkReqBuf_scanStateReg_EN; - - // register sq_pendingWorkReqBuf_scanStopReg - reg sq_pendingWorkReqBuf_scanStopReg; - wire sq_pendingWorkReqBuf_scanStopReg_D_IN, - sq_pendingWorkReqBuf_scanStopReg_EN; - - // register sq_reqGenSQ_curPsnReg - reg [23 : 0] sq_reqGenSQ_curPsnReg; - wire [23 : 0] sq_reqGenSQ_curPsnReg_D_IN; - wire sq_reqGenSQ_curPsnReg_EN; - - // register sq_reqGenSQ_isFirstOrOnlyReqPktReg - reg sq_reqGenSQ_isFirstOrOnlyReqPktReg; - wire sq_reqGenSQ_isFirstOrOnlyReqPktReg_D_IN, - sq_reqGenSQ_isFirstOrOnlyReqPktReg_EN; - - // register sq_reqGenSQ_isNormalStateReg - reg sq_reqGenSQ_isNormalStateReg; - wire sq_reqGenSQ_isNormalStateReg_D_IN, sq_reqGenSQ_isNormalStateReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg - reg sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg; - wire sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg_D_IN, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg - reg [592 : 0] sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg; - wire [592 : 0] sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg_D_IN; - wire sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg - reg [1 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg; - wire [1 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_D_IN; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg - reg sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg_D_IN, - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg - reg [8 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg; - wire [8 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg_D_IN; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg - reg [5 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg; - wire [5 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg_D_IN; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg - reg [8 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg; - wire [8 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg_D_IN; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg - reg [5 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg; - wire [5 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg_D_IN; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg - reg sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg_D_IN, - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg - reg [289 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg; - wire [289 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_D_IN; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_EN; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg - reg [1 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg; - reg [1 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_D_IN; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_EN; - - // register sq_reqGenSQ_remainingPktNumReg - reg [24 : 0] sq_reqGenSQ_remainingPktNumReg; - wire [24 : 0] sq_reqGenSQ_remainingPktNumReg_D_IN; - wire sq_reqGenSQ_remainingPktNumReg_EN; - - // register sq_respHandleSQ_errOccurredReg - reg sq_respHandleSQ_errOccurredReg; - wire sq_respHandleSQ_errOccurredReg_D_IN, sq_respHandleSQ_errOccurredReg_EN; - - // register sq_respHandleSQ_hasInternalErrReg - reg sq_respHandleSQ_hasInternalErrReg; - wire sq_respHandleSQ_hasInternalErrReg_D_IN, - sq_respHandleSQ_hasInternalErrReg_EN; - - // register sq_respHandleSQ_hasTimeOutErrReg - reg sq_respHandleSQ_hasTimeOutErrReg; - wire sq_respHandleSQ_hasTimeOutErrReg_D_IN, - sq_respHandleSQ_hasTimeOutErrReg_EN; - - // register sq_respHandleSQ_nextReadRespWriteAddrReg - reg [63 : 0] sq_respHandleSQ_nextReadRespWriteAddrReg; - wire [63 : 0] sq_respHandleSQ_nextReadRespWriteAddrReg_D_IN; - wire sq_respHandleSQ_nextReadRespWriteAddrReg_EN; - - // register sq_respHandleSQ_preRdmaOpCodeReg - reg [4 : 0] sq_respHandleSQ_preRdmaOpCodeReg; - wire [4 : 0] sq_respHandleSQ_preRdmaOpCodeReg_D_IN; - wire sq_respHandleSQ_preRdmaOpCodeReg_EN; - - // register sq_respHandleSQ_preStageDeqPendingWorkReqReg - reg sq_respHandleSQ_preStageDeqPendingWorkReqReg; - wire sq_respHandleSQ_preStageDeqPendingWorkReqReg_D_IN, - sq_respHandleSQ_preStageDeqPendingWorkReqReg_EN; - - // register sq_respHandleSQ_preStageDeqPktMetaDataReg - reg sq_respHandleSQ_preStageDeqPktMetaDataReg; - wire sq_respHandleSQ_preStageDeqPktMetaDataReg_D_IN, - sq_respHandleSQ_preStageDeqPktMetaDataReg_EN; - - // register sq_respHandleSQ_preStagePktMetaDataReg - reg [648 : 0] sq_respHandleSQ_preStagePktMetaDataReg; - wire [648 : 0] sq_respHandleSQ_preStagePktMetaDataReg_D_IN; - wire sq_respHandleSQ_preStagePktMetaDataReg_EN; - - // register sq_respHandleSQ_preStageReqPktInfoReg - reg [134 : 0] sq_respHandleSQ_preStageReqPktInfoReg; - wire [134 : 0] sq_respHandleSQ_preStageReqPktInfoReg_D_IN; - wire sq_respHandleSQ_preStageReqPktInfoReg_EN; - - // register sq_respHandleSQ_preStageRespAndWorkReqRelationReg - reg [4 : 0] sq_respHandleSQ_preStageRespAndWorkReqRelationReg; - wire [4 : 0] sq_respHandleSQ_preStageRespAndWorkReqRelationReg_D_IN; - wire sq_respHandleSQ_preStageRespAndWorkReqRelationReg_EN; - - // register sq_respHandleSQ_preStageRespTypeReg - reg [1 : 0] sq_respHandleSQ_preStageRespTypeReg; - reg [1 : 0] sq_respHandleSQ_preStageRespTypeReg_D_IN; - wire sq_respHandleSQ_preStageRespTypeReg_EN; - - // register sq_respHandleSQ_preStageStateReg - reg [1 : 0] sq_respHandleSQ_preStageStateReg; - reg [1 : 0] sq_respHandleSQ_preStageStateReg_D_IN; - wire sq_respHandleSQ_preStageStateReg_EN; - - // register sq_respHandleSQ_preStageWorkCompReqTypeReg - reg [1 : 0] sq_respHandleSQ_preStageWorkCompReqTypeReg; - wire [1 : 0] sq_respHandleSQ_preStageWorkCompReqTypeReg_D_IN; - wire sq_respHandleSQ_preStageWorkCompReqTypeReg_EN; - - // register sq_respHandleSQ_preStageWorkReqAckTypeReg - reg [3 : 0] sq_respHandleSQ_preStageWorkReqAckTypeReg; - wire [3 : 0] sq_respHandleSQ_preStageWorkReqAckTypeReg_D_IN; - wire sq_respHandleSQ_preStageWorkReqAckTypeReg_EN; - - // register sq_respHandleSQ_recvErrRespReg - reg sq_respHandleSQ_recvErrRespReg; - wire sq_respHandleSQ_recvErrRespReg_D_IN, sq_respHandleSQ_recvErrRespReg_EN; - - // register sq_respHandleSQ_recvRetryRespReg - reg sq_respHandleSQ_recvRetryRespReg; - wire sq_respHandleSQ_recvRetryRespReg_D_IN, - sq_respHandleSQ_recvRetryRespReg_EN; - - // register sq_respHandleSQ_remainingReadRespLenReg - reg [31 : 0] sq_respHandleSQ_remainingReadRespLenReg; - wire [31 : 0] sq_respHandleSQ_remainingReadRespLenReg_D_IN; - wire sq_respHandleSQ_remainingReadRespLenReg_EN; - - // register sq_respHandleSQ_retryFlushReg - reg sq_respHandleSQ_retryFlushReg; - wire sq_respHandleSQ_retryFlushReg_D_IN, sq_respHandleSQ_retryFlushReg_EN; - - // register sq_respHandleSQ_retryResetReqReg - reg sq_respHandleSQ_retryResetReqReg; - wire sq_respHandleSQ_retryResetReqReg_D_IN, - sq_respHandleSQ_retryResetReqReg_EN; - - // register sq_retryHandler_disableRetryCntReg - reg sq_retryHandler_disableRetryCntReg; - wire sq_retryHandler_disableRetryCntReg_D_IN, - sq_retryHandler_disableRetryCntReg_EN; - - // register sq_retryHandler_disableTimeOutReg - reg sq_retryHandler_disableTimeOutReg; - wire sq_retryHandler_disableTimeOutReg_D_IN, - sq_retryHandler_disableTimeOutReg_EN; - - // register sq_retryHandler_isRnrWaitCntZeroReg - reg sq_retryHandler_isRnrWaitCntZeroReg; - wire sq_retryHandler_isRnrWaitCntZeroReg_D_IN, - sq_retryHandler_isRnrWaitCntZeroReg_EN; - - // register sq_retryHandler_isTimeOutCntHighPartZeroReg - reg sq_retryHandler_isTimeOutCntHighPartZeroReg; - wire sq_retryHandler_isTimeOutCntHighPartZeroReg_D_IN, - sq_retryHandler_isTimeOutCntHighPartZeroReg_EN; - - // register sq_retryHandler_isTimeOutCntLowPartZeroReg - reg sq_retryHandler_isTimeOutCntLowPartZeroReg; - wire sq_retryHandler_isTimeOutCntLowPartZeroReg_D_IN, - sq_retryHandler_isTimeOutCntLowPartZeroReg_EN; - - // register sq_retryHandler_pauseRetryHandleReg - reg sq_retryHandler_pauseRetryHandleReg; - wire sq_retryHandler_pauseRetryHandleReg_D_IN, - sq_retryHandler_pauseRetryHandleReg_EN; - - // register sq_retryHandler_psnDiffReg - reg [23 : 0] sq_retryHandler_psnDiffReg; - wire [23 : 0] sq_retryHandler_psnDiffReg_D_IN; - wire sq_retryHandler_psnDiffReg_EN; - - // register sq_retryHandler_retryCntReg - reg [2 : 0] sq_retryHandler_retryCntReg; - wire [2 : 0] sq_retryHandler_retryCntReg_D_IN; - wire sq_retryHandler_retryCntReg_EN; - - // register sq_retryHandler_retryCntrlStateReg - reg [1 : 0] sq_retryHandler_retryCntrlStateReg; - wire [1 : 0] sq_retryHandler_retryCntrlStateReg_D_IN; - wire sq_retryHandler_retryCntrlStateReg_EN; - - // register sq_retryHandler_retryHandleStateReg - reg [2 : 0] sq_retryHandler_retryHandleStateReg; - reg [2 : 0] sq_retryHandler_retryHandleStateReg_D_IN; - wire sq_retryHandler_retryHandleStateReg_EN; - - // register sq_retryHandler_retryReasonReg - reg [2 : 0] sq_retryHandler_retryReasonReg; - wire [2 : 0] sq_retryHandler_retryReasonReg_D_IN; - wire sq_retryHandler_retryReasonReg_EN; - - // register sq_retryHandler_retryRnrTimerReg - reg [4 : 0] sq_retryHandler_retryRnrTimerReg; - wire [4 : 0] sq_retryHandler_retryRnrTimerReg_D_IN; - wire sq_retryHandler_retryRnrTimerReg_EN; - - // register sq_retryHandler_retryStartPsnReg - reg [23 : 0] sq_retryHandler_retryStartPsnReg; - wire [23 : 0] sq_retryHandler_retryStartPsnReg_D_IN; - wire sq_retryHandler_retryStartPsnReg_EN; - - // register sq_retryHandler_retryWorkReqIdReg - reg [63 : 0] sq_retryHandler_retryWorkReqIdReg; - wire [63 : 0] sq_retryHandler_retryWorkReqIdReg_D_IN; - wire sq_retryHandler_retryWorkReqIdReg_EN; - - // register sq_retryHandler_rnrCntReg - reg [2 : 0] sq_retryHandler_rnrCntReg; - wire [2 : 0] sq_retryHandler_rnrCntReg_D_IN; - wire sq_retryHandler_rnrCntReg_EN; - - // register sq_retryHandler_rnrWaitCntReg - reg [26 : 0] sq_retryHandler_rnrWaitCntReg; - wire [26 : 0] sq_retryHandler_rnrWaitCntReg_D_IN; - wire sq_retryHandler_rnrWaitCntReg_EN; - - // register sq_retryHandler_timeOutCntReg - reg [41 : 0] sq_retryHandler_timeOutCntReg; - wire [41 : 0] sq_retryHandler_timeOutCntReg_D_IN; - wire sq_retryHandler_timeOutCntReg_EN; - - // register sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg - reg [63 : 0] sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg; - wire [63 : 0] sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_D_IN; - wire sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_EN; - - // register sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg - reg sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg; - wire sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_D_IN, - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_EN; - - // register sq_workCompGenSQ_workCompGenStateReg - reg [1 : 0] sq_workCompGenSQ_workCompGenStateReg; - reg [1 : 0] sq_workCompGenSQ_workCompGenStateReg_D_IN; - wire sq_workCompGenSQ_workCompGenStateReg_EN; - - // ports of submodule cntrl_reqQ - wire [300 : 0] cntrl_reqQ_D_IN, cntrl_reqQ_D_OUT; - wire cntrl_reqQ_CLR, - cntrl_reqQ_DEQ, - cntrl_reqQ_EMPTY_N, - cntrl_reqQ_ENQ, - cntrl_reqQ_FULL_N; - - // ports of submodule cntrl_respQ - reg [273 : 0] cntrl_respQ_D_IN; - wire [273 : 0] cntrl_respQ_D_OUT; - wire cntrl_respQ_CLR, - cntrl_respQ_DEQ, - cntrl_respQ_EMPTY_N, - cntrl_respQ_ENQ, - cntrl_respQ_FULL_N; - - // ports of submodule cntrl_restoreQ - wire [28 : 0] cntrl_restoreQ_D_IN, cntrl_restoreQ_D_OUT; - wire cntrl_restoreQ_CLR, - cntrl_restoreQ_DEQ, - cntrl_restoreQ_EMPTY_N, - cntrl_restoreQ_ENQ; - - // ports of submodule dmaReadCntrl4SQ_addrChunkSrv_reqQ - wire [98 : 0] dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_IN, - dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT; - wire dmaReadCntrl4SQ_addrChunkSrv_reqQ_CLR, - dmaReadCntrl4SQ_addrChunkSrv_reqQ_DEQ, - dmaReadCntrl4SQ_addrChunkSrv_reqQ_EMPTY_N, - dmaReadCntrl4SQ_addrChunkSrv_reqQ_ENQ, - dmaReadCntrl4SQ_addrChunkSrv_reqQ_FULL_N; - - // ports of submodule dmaReadCntrl4SQ_addrChunkSrv_respQ - wire [78 : 0] dmaReadCntrl4SQ_addrChunkSrv_respQ_D_IN, - dmaReadCntrl4SQ_addrChunkSrv_respQ_D_OUT; - wire dmaReadCntrl4SQ_addrChunkSrv_respQ_CLR, - dmaReadCntrl4SQ_addrChunkSrv_respQ_DEQ, - dmaReadCntrl4SQ_addrChunkSrv_respQ_EMPTY_N, - dmaReadCntrl4SQ_addrChunkSrv_respQ_ENQ, - dmaReadCntrl4SQ_addrChunkSrv_respQ_FULL_N; - - // ports of submodule dmaReadCntrl4SQ_pendingDmaCntrlReqQ - wire [191 : 0] dmaReadCntrl4SQ_pendingDmaCntrlReqQ_D_IN, - dmaReadCntrl4SQ_pendingDmaCntrlReqQ_D_OUT; - wire dmaReadCntrl4SQ_pendingDmaCntrlReqQ_CLR, - dmaReadCntrl4SQ_pendingDmaCntrlReqQ_DEQ, - dmaReadCntrl4SQ_pendingDmaCntrlReqQ_EMPTY_N, - dmaReadCntrl4SQ_pendingDmaCntrlReqQ_ENQ, - dmaReadCntrl4SQ_pendingDmaCntrlReqQ_FULL_N; - - // ports of submodule dmaReadCntrl4SQ_pendingDmaReadReqQ - wire [171 : 0] dmaReadCntrl4SQ_pendingDmaReadReqQ_D_IN, - dmaReadCntrl4SQ_pendingDmaReadReqQ_D_OUT; - wire dmaReadCntrl4SQ_pendingDmaReadReqQ_CLR, - dmaReadCntrl4SQ_pendingDmaReadReqQ_DEQ, - dmaReadCntrl4SQ_pendingDmaReadReqQ_EMPTY_N, - dmaReadCntrl4SQ_pendingDmaReadReqQ_ENQ, - dmaReadCntrl4SQ_pendingDmaReadReqQ_FULL_N; - - // ports of submodule dmaReadCntrl4SQ_reqQ - wire [191 : 0] dmaReadCntrl4SQ_reqQ_D_IN, dmaReadCntrl4SQ_reqQ_D_OUT; - wire dmaReadCntrl4SQ_reqQ_CLR, - dmaReadCntrl4SQ_reqQ_DEQ, - dmaReadCntrl4SQ_reqQ_EMPTY_N, - dmaReadCntrl4SQ_reqQ_ENQ, - dmaReadCntrl4SQ_reqQ_FULL_N; - - // ports of submodule dmaReadCntrl4SQ_respQ - wire [384 : 0] dmaReadCntrl4SQ_respQ_D_IN, dmaReadCntrl4SQ_respQ_D_OUT; - wire dmaReadCntrl4SQ_respQ_CLR, - dmaReadCntrl4SQ_respQ_DEQ, - dmaReadCntrl4SQ_respQ_EMPTY_N, - dmaReadCntrl4SQ_respQ_ENQ, - dmaReadCntrl4SQ_respQ_FULL_N; - - // ports of submodule dmaReadProxy4SQ_reqQ - wire [169 : 0] dmaReadProxy4SQ_reqQ_D_IN, dmaReadProxy4SQ_reqQ_D_OUT; - wire dmaReadProxy4SQ_reqQ_CLR, - dmaReadProxy4SQ_reqQ_DEQ, - dmaReadProxy4SQ_reqQ_EMPTY_N, - dmaReadProxy4SQ_reqQ_ENQ, - dmaReadProxy4SQ_reqQ_FULL_N; - - // ports of submodule dmaReadProxy4SQ_respQ - wire [382 : 0] dmaReadProxy4SQ_respQ_D_IN, dmaReadProxy4SQ_respQ_D_OUT; - wire dmaReadProxy4SQ_respQ_CLR, - dmaReadProxy4SQ_respQ_DEQ, - dmaReadProxy4SQ_respQ_EMPTY_N, - dmaReadProxy4SQ_respQ_ENQ, - dmaReadProxy4SQ_respQ_FULL_N; - - // ports of submodule payloadGenerator4SQ_bramQ2PipeOut_postBramQ - wire [289 : 0] payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_IN, - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_OUT; - wire payloadGenerator4SQ_bramQ2PipeOut_postBramQ_CLR, - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_DEQ, - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_EMPTY_N, - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_ENQ, - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_FULL_N; - - // ports of submodule payloadGenerator4SQ_payloadBufQ_memory - wire [289 : 0] payloadGenerator4SQ_payloadBufQ_memory_DIA, - payloadGenerator4SQ_payloadBufQ_memory_DIB, - payloadGenerator4SQ_payloadBufQ_memory_DOB; - wire [8 : 0] payloadGenerator4SQ_payloadBufQ_memory_ADDRA, - payloadGenerator4SQ_payloadBufQ_memory_ADDRB; - wire payloadGenerator4SQ_payloadBufQ_memory_ENA, - payloadGenerator4SQ_payloadBufQ_memory_ENB, - payloadGenerator4SQ_payloadBufQ_memory_WEA, - payloadGenerator4SQ_payloadBufQ_memory_WEB; - - // ports of submodule payloadGenerator4SQ_payloadGenReqQ - wire [192 : 0] payloadGenerator4SQ_payloadGenReqQ_D_IN, - payloadGenerator4SQ_payloadGenReqQ_D_OUT; - wire payloadGenerator4SQ_payloadGenReqQ_CLR, - payloadGenerator4SQ_payloadGenReqQ_DEQ, - payloadGenerator4SQ_payloadGenReqQ_EMPTY_N, - payloadGenerator4SQ_payloadGenReqQ_ENQ, - payloadGenerator4SQ_payloadGenReqQ_FULL_N; - - // ports of submodule payloadGenerator4SQ_payloadGenRespQ - wire [1 : 0] payloadGenerator4SQ_payloadGenRespQ_D_IN, - payloadGenerator4SQ_payloadGenRespQ_D_OUT; - wire payloadGenerator4SQ_payloadGenRespQ_CLR, - payloadGenerator4SQ_payloadGenRespQ_DEQ, - payloadGenerator4SQ_payloadGenRespQ_EMPTY_N, - payloadGenerator4SQ_payloadGenRespQ_ENQ, - payloadGenerator4SQ_payloadGenRespQ_FULL_N; - - // ports of submodule payloadGenerator4SQ_pendingGenReqQ - wire [232 : 0] payloadGenerator4SQ_pendingGenReqQ_D_IN, - payloadGenerator4SQ_pendingGenReqQ_D_OUT; - wire payloadGenerator4SQ_pendingGenReqQ_CLR, - payloadGenerator4SQ_pendingGenReqQ_DEQ, - payloadGenerator4SQ_pendingGenReqQ_EMPTY_N, - payloadGenerator4SQ_pendingGenReqQ_ENQ, - payloadGenerator4SQ_pendingGenReqQ_FULL_N; - - // ports of submodule respPktPipe_metaDataQ - wire [648 : 0] respPktPipe_metaDataQ_D_IN, respPktPipe_metaDataQ_D_OUT; - wire respPktPipe_metaDataQ_CLR, - respPktPipe_metaDataQ_DEQ, - respPktPipe_metaDataQ_EMPTY_N, - respPktPipe_metaDataQ_ENQ, - respPktPipe_metaDataQ_FULL_N; - - // ports of submodule respPktPipe_payloadQ - wire [289 : 0] respPktPipe_payloadQ_D_IN; - wire respPktPipe_payloadQ_CLR, - respPktPipe_payloadQ_DEQ, - respPktPipe_payloadQ_ENQ, - respPktPipe_payloadQ_FULL_N; - - // ports of submodule sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ - wire [678 : 0] sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_D_IN, - sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_D_OUT; - wire sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_CLR, - sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_DEQ, - sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_EMPTY_N, - sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_ENQ, - sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_FULL_N; - - // ports of submodule sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ - wire sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_CLR, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_DEQ, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_D_IN, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_EMPTY_N, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_ENQ, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_FULL_N; - - // ports of submodule sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ - wire sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_CLR, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_DEQ, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_D_IN, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_EMPTY_N, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_ENQ, - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_FULL_N; - - // ports of submodule sq_pendingWorkReqBuf_itemCnt - wire [2 : 0] sq_pendingWorkReqBuf_itemCnt_DATA_A, - sq_pendingWorkReqBuf_itemCnt_DATA_B, - sq_pendingWorkReqBuf_itemCnt_DATA_C, - sq_pendingWorkReqBuf_itemCnt_DATA_F, - sq_pendingWorkReqBuf_itemCnt_Q_OUT; - wire sq_pendingWorkReqBuf_itemCnt_ADDA, - sq_pendingWorkReqBuf_itemCnt_ADDB, - sq_pendingWorkReqBuf_itemCnt_SETC, - sq_pendingWorkReqBuf_itemCnt_SETF; - - // ports of submodule sq_pendingWorkReqBuf_scanCnt - wire [2 : 0] sq_pendingWorkReqBuf_scanCnt_DATA_A, - sq_pendingWorkReqBuf_scanCnt_DATA_B, - sq_pendingWorkReqBuf_scanCnt_DATA_C, - sq_pendingWorkReqBuf_scanCnt_DATA_F, - sq_pendingWorkReqBuf_scanCnt_Q_OUT; - wire sq_pendingWorkReqBuf_scanCnt_ADDA, - sq_pendingWorkReqBuf_scanCnt_ADDB, - sq_pendingWorkReqBuf_scanCnt_SETC, - sq_pendingWorkReqBuf_scanCnt_SETF; - - // ports of submodule sq_pendingWorkReqBuf_scanOutQ - wire [678 : 0] sq_pendingWorkReqBuf_scanOutQ_D_IN, - sq_pendingWorkReqBuf_scanOutQ_D_OUT; - wire sq_pendingWorkReqBuf_scanOutQ_CLR, - sq_pendingWorkReqBuf_scanOutQ_DEQ, - sq_pendingWorkReqBuf_scanOutQ_EMPTY_N, - sq_pendingWorkReqBuf_scanOutQ_ENQ, - sq_pendingWorkReqBuf_scanOutQ_FULL_N; - - // ports of submodule sq_pendingWorkReqPipeOut_pipeMuxOutQ - wire [678 : 0] sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_IN, - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT; - wire sq_pendingWorkReqPipeOut_pipeMuxOutQ_CLR, - sq_pendingWorkReqPipeOut_pipeMuxOutQ_DEQ, - sq_pendingWorkReqPipeOut_pipeMuxOutQ_EMPTY_N, - sq_pendingWorkReqPipeOut_pipeMuxOutQ_ENQ, - sq_pendingWorkReqPipeOut_pipeMuxOutQ_FULL_N; - - // ports of submodule sq_reqGenSQ_pendingReqHeaderQ - wire [1228 : 0] sq_reqGenSQ_pendingReqHeaderQ_D_IN, - sq_reqGenSQ_pendingReqHeaderQ_D_OUT; - wire sq_reqGenSQ_pendingReqHeaderQ_CLR, - sq_reqGenSQ_pendingReqHeaderQ_DEQ, - sq_reqGenSQ_pendingReqHeaderQ_EMPTY_N, - sq_reqGenSQ_pendingReqHeaderQ_ENQ, - sq_reqGenSQ_pendingReqHeaderQ_FULL_N; - - // ports of submodule sq_reqGenSQ_pendingWorkReqOutQ - wire [678 : 0] sq_reqGenSQ_pendingWorkReqOutQ_D_IN, - sq_reqGenSQ_pendingWorkReqOutQ_D_OUT; - wire sq_reqGenSQ_pendingWorkReqOutQ_CLR, - sq_reqGenSQ_pendingWorkReqOutQ_DEQ, - sq_reqGenSQ_pendingWorkReqOutQ_EMPTY_N, - sq_reqGenSQ_pendingWorkReqOutQ_ENQ, - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N; - - // ports of submodule sq_reqGenSQ_psnReqOutQ - wire [23 : 0] sq_reqGenSQ_psnReqOutQ_D_IN; - wire sq_reqGenSQ_psnReqOutQ_CLR, - sq_reqGenSQ_psnReqOutQ_DEQ, - sq_reqGenSQ_psnReqOutQ_EMPTY_N, - sq_reqGenSQ_psnReqOutQ_ENQ, - sq_reqGenSQ_psnReqOutQ_FULL_N; - - // ports of submodule sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ - wire [289 : 0] sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_IN, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT; - wire sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_CLR, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_DEQ, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_EMPTY_N, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_ENQ, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_FULL_N; - - // ports of submodule sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ - wire [16 : 0] sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_IN, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT; - wire sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_CLR, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_DEQ, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_EMPTY_N, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_ENQ, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_FULL_N; - - // ports of submodule sq_reqGenSQ_rdmaReqPipeOut_outputQ - wire [289 : 0] sq_reqGenSQ_rdmaReqPipeOut_outputQ_D_IN, - sq_reqGenSQ_rdmaReqPipeOut_outputQ_D_OUT; - wire sq_reqGenSQ_rdmaReqPipeOut_outputQ_CLR, - sq_reqGenSQ_rdmaReqPipeOut_outputQ_DEQ, - sq_reqGenSQ_rdmaReqPipeOut_outputQ_EMPTY_N, - sq_reqGenSQ_rdmaReqPipeOut_outputQ_ENQ, - sq_reqGenSQ_rdmaReqPipeOut_outputQ_FULL_N; - - // ports of submodule sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ - reg [289 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_IN; - wire [289 : 0] sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_OUT; - wire sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_CLR, - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_DEQ, - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_EMPTY_N, - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_ENQ, - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_FULL_N; - - // ports of submodule sq_reqGenSQ_reqCountQ - wire [683 : 0] sq_reqGenSQ_reqCountQ_D_IN, sq_reqGenSQ_reqCountQ_D_OUT; - wire sq_reqGenSQ_reqCountQ_CLR, - sq_reqGenSQ_reqCountQ_DEQ, - sq_reqGenSQ_reqCountQ_EMPTY_N, - sq_reqGenSQ_reqCountQ_ENQ, - sq_reqGenSQ_reqCountQ_FULL_N; - - // ports of submodule sq_reqGenSQ_reqHeaderGenQ - wire [1299 : 0] sq_reqGenSQ_reqHeaderGenQ_D_IN, - sq_reqGenSQ_reqHeaderGenQ_D_OUT; - wire sq_reqGenSQ_reqHeaderGenQ_CLR, - sq_reqGenSQ_reqHeaderGenQ_DEQ, - sq_reqGenSQ_reqHeaderGenQ_EMPTY_N, - sq_reqGenSQ_reqHeaderGenQ_ENQ, - sq_reqGenSQ_reqHeaderGenQ_FULL_N; - - // ports of submodule sq_reqGenSQ_reqHeaderOutQ - wire [592 : 0] sq_reqGenSQ_reqHeaderOutQ_D_IN, - sq_reqGenSQ_reqHeaderOutQ_D_OUT; - wire sq_reqGenSQ_reqHeaderOutQ_CLR, - sq_reqGenSQ_reqHeaderOutQ_DEQ, - sq_reqGenSQ_reqHeaderOutQ_EMPTY_N, - sq_reqGenSQ_reqHeaderOutQ_ENQ, - sq_reqGenSQ_reqHeaderOutQ_FULL_N; - - // ports of submodule sq_reqGenSQ_reqHeaderPrepareQ - wire [709 : 0] sq_reqGenSQ_reqHeaderPrepareQ_D_IN, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT; - wire sq_reqGenSQ_reqHeaderPrepareQ_CLR, - sq_reqGenSQ_reqHeaderPrepareQ_DEQ, - sq_reqGenSQ_reqHeaderPrepareQ_EMPTY_N, - sq_reqGenSQ_reqHeaderPrepareQ_ENQ, - sq_reqGenSQ_reqHeaderPrepareQ_FULL_N; - - // ports of submodule sq_reqGenSQ_workCompGenReqOutQ - wire [632 : 0] sq_reqGenSQ_workCompGenReqOutQ_D_IN, - sq_reqGenSQ_workCompGenReqOutQ_D_OUT; - wire sq_reqGenSQ_workCompGenReqOutQ_CLR, - sq_reqGenSQ_workCompGenReqOutQ_DEQ, - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N, - sq_reqGenSQ_workCompGenReqOutQ_ENQ, - sq_reqGenSQ_workCompGenReqOutQ_FULL_N; - - // ports of submodule sq_reqGenSQ_workReqCheckQ - wire [683 : 0] sq_reqGenSQ_workReqCheckQ_D_IN, - sq_reqGenSQ_workReqCheckQ_D_OUT; - wire sq_reqGenSQ_workReqCheckQ_CLR, - sq_reqGenSQ_workReqCheckQ_DEQ, - sq_reqGenSQ_workReqCheckQ_EMPTY_N, - sq_reqGenSQ_workReqCheckQ_ENQ, - sq_reqGenSQ_workReqCheckQ_FULL_N; - - // ports of submodule sq_reqGenSQ_workReqOutQ - wire [683 : 0] sq_reqGenSQ_workReqOutQ_D_IN, sq_reqGenSQ_workReqOutQ_D_OUT; - wire sq_reqGenSQ_workReqOutQ_CLR, - sq_reqGenSQ_workReqOutQ_DEQ, - sq_reqGenSQ_workReqOutQ_EMPTY_N, - sq_reqGenSQ_workReqOutQ_ENQ, - sq_reqGenSQ_workReqOutQ_FULL_N; - - // ports of submodule sq_reqGenSQ_workReqPayloadGenQ - wire [719 : 0] sq_reqGenSQ_workReqPayloadGenQ_D_IN, - sq_reqGenSQ_workReqPayloadGenQ_D_OUT; - wire sq_reqGenSQ_workReqPayloadGenQ_CLR, - sq_reqGenSQ_workReqPayloadGenQ_DEQ, - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N, - sq_reqGenSQ_workReqPayloadGenQ_ENQ, - sq_reqGenSQ_workReqPayloadGenQ_FULL_N; - - // ports of submodule sq_reqGenSQ_workReqPktNumQ - wire [708 : 0] sq_reqGenSQ_workReqPktNumQ_D_IN, - sq_reqGenSQ_workReqPktNumQ_D_OUT; - wire sq_reqGenSQ_workReqPktNumQ_CLR, - sq_reqGenSQ_workReqPktNumQ_DEQ, - sq_reqGenSQ_workReqPktNumQ_EMPTY_N, - sq_reqGenSQ_workReqPktNumQ_ENQ, - sq_reqGenSQ_workReqPktNumQ_FULL_N; - - // ports of submodule sq_reqGenSQ_workReqPsnQ - wire [683 : 0] sq_reqGenSQ_workReqPsnQ_D_IN, sq_reqGenSQ_workReqPsnQ_D_OUT; - wire sq_reqGenSQ_workReqPsnQ_CLR, - sq_reqGenSQ_workReqPsnQ_DEQ, - sq_reqGenSQ_workReqPsnQ_EMPTY_N, - sq_reqGenSQ_workReqPsnQ_ENQ, - sq_reqGenSQ_workReqPsnQ_FULL_N; - - // ports of submodule sq_respHandleSQ_incomingRespQ - reg [1469 : 0] sq_respHandleSQ_incomingRespQ_D_IN; - wire [1469 : 0] sq_respHandleSQ_incomingRespQ_D_OUT; - wire sq_respHandleSQ_incomingRespQ_CLR, - sq_respHandleSQ_incomingRespQ_DEQ, - sq_respHandleSQ_incomingRespQ_EMPTY_N, - sq_respHandleSQ_incomingRespQ_ENQ, - sq_respHandleSQ_incomingRespQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingAddrCalcQ - wire [1474 : 0] sq_respHandleSQ_pendingAddrCalcQ_D_IN, - sq_respHandleSQ_pendingAddrCalcQ_D_OUT; - wire sq_respHandleSQ_pendingAddrCalcQ_CLR, - sq_respHandleSQ_pendingAddrCalcQ_DEQ, - sq_respHandleSQ_pendingAddrCalcQ_EMPTY_N, - sq_respHandleSQ_pendingAddrCalcQ_ENQ, - sq_respHandleSQ_pendingAddrCalcQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingDmaReqQ - wire [1538 : 0] sq_respHandleSQ_pendingDmaReqQ_D_IN, - sq_respHandleSQ_pendingDmaReqQ_D_OUT; - wire sq_respHandleSQ_pendingDmaReqQ_CLR, - sq_respHandleSQ_pendingDmaReqQ_DEQ, - sq_respHandleSQ_pendingDmaReqQ_EMPTY_N, - sq_respHandleSQ_pendingDmaReqQ_ENQ, - sq_respHandleSQ_pendingDmaReqQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingLenCalcQ - wire [1538 : 0] sq_respHandleSQ_pendingLenCalcQ_D_IN, - sq_respHandleSQ_pendingLenCalcQ_D_OUT; - wire sq_respHandleSQ_pendingLenCalcQ_CLR, - sq_respHandleSQ_pendingLenCalcQ_DEQ, - sq_respHandleSQ_pendingLenCalcQ_EMPTY_N, - sq_respHandleSQ_pendingLenCalcQ_ENQ, - sq_respHandleSQ_pendingLenCalcQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingLenCheckQ - wire [1572 : 0] sq_respHandleSQ_pendingLenCheckQ_D_IN, - sq_respHandleSQ_pendingLenCheckQ_D_OUT; - wire sq_respHandleSQ_pendingLenCheckQ_CLR, - sq_respHandleSQ_pendingLenCheckQ_DEQ, - sq_respHandleSQ_pendingLenCheckQ_EMPTY_N, - sq_respHandleSQ_pendingLenCheckQ_ENQ, - sq_respHandleSQ_pendingLenCheckQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingPermCheckQ - wire [1475 : 0] sq_respHandleSQ_pendingPermCheckQ_D_IN, - sq_respHandleSQ_pendingPermCheckQ_D_OUT; - wire sq_respHandleSQ_pendingPermCheckQ_CLR, - sq_respHandleSQ_pendingPermCheckQ_DEQ, - sq_respHandleSQ_pendingPermCheckQ_EMPTY_N, - sq_respHandleSQ_pendingPermCheckQ_ENQ, - sq_respHandleSQ_pendingPermCheckQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingPermQueryQ - wire [1468 : 0] sq_respHandleSQ_pendingPermQueryQ_D_IN, - sq_respHandleSQ_pendingPermQueryQ_D_OUT; - wire sq_respHandleSQ_pendingPermQueryQ_CLR, - sq_respHandleSQ_pendingPermQueryQ_DEQ, - sq_respHandleSQ_pendingPermQueryQ_EMPTY_N, - sq_respHandleSQ_pendingPermQueryQ_ENQ, - sq_respHandleSQ_pendingPermQueryQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingRespQ - wire [1472 : 0] sq_respHandleSQ_pendingRespQ_D_IN, - sq_respHandleSQ_pendingRespQ_D_OUT; - wire sq_respHandleSQ_pendingRespQ_CLR, - sq_respHandleSQ_pendingRespQ_DEQ, - sq_respHandleSQ_pendingRespQ_EMPTY_N, - sq_respHandleSQ_pendingRespQ_ENQ, - sq_respHandleSQ_pendingRespQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingRetryCheckQ - wire [1469 : 0] sq_respHandleSQ_pendingRetryCheckQ_D_IN, - sq_respHandleSQ_pendingRetryCheckQ_D_OUT; - wire sq_respHandleSQ_pendingRetryCheckQ_CLR, - sq_respHandleSQ_pendingRetryCheckQ_DEQ, - sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N, - sq_respHandleSQ_pendingRetryCheckQ_ENQ, - sq_respHandleSQ_pendingRetryCheckQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingSpaceCalcQ - wire [1604 : 0] sq_respHandleSQ_pendingSpaceCalcQ_D_IN, - sq_respHandleSQ_pendingSpaceCalcQ_D_OUT; - wire sq_respHandleSQ_pendingSpaceCalcQ_CLR, - sq_respHandleSQ_pendingSpaceCalcQ_DEQ, - sq_respHandleSQ_pendingSpaceCalcQ_EMPTY_N, - sq_respHandleSQ_pendingSpaceCalcQ_ENQ, - sq_respHandleSQ_pendingSpaceCalcQ_FULL_N; - - // ports of submodule sq_respHandleSQ_pendingWorkCompQ - wire [767 : 0] sq_respHandleSQ_pendingWorkCompQ_D_IN, - sq_respHandleSQ_pendingWorkCompQ_D_OUT; - wire sq_respHandleSQ_pendingWorkCompQ_CLR, - sq_respHandleSQ_pendingWorkCompQ_DEQ, - sq_respHandleSQ_pendingWorkCompQ_EMPTY_N, - sq_respHandleSQ_pendingWorkCompQ_ENQ, - sq_respHandleSQ_pendingWorkCompQ_FULL_N; - - // ports of submodule sq_respHandleSQ_workCompGenReqOutQ - wire [632 : 0] sq_respHandleSQ_workCompGenReqOutQ_D_IN, - sq_respHandleSQ_workCompGenReqOutQ_D_OUT; - wire sq_respHandleSQ_workCompGenReqOutQ_CLR, - sq_respHandleSQ_workCompGenReqOutQ_DEQ, - sq_respHandleSQ_workCompGenReqOutQ_EMPTY_N, - sq_respHandleSQ_workCompGenReqOutQ_ENQ, - sq_respHandleSQ_workCompGenReqOutQ_FULL_N; - - // ports of submodule sq_retryHandler_prepareRetryRespQ - wire [3 : 0] sq_retryHandler_prepareRetryRespQ_D_IN, - sq_retryHandler_prepareRetryRespQ_D_OUT; - wire sq_retryHandler_prepareRetryRespQ_CLR, - sq_retryHandler_prepareRetryRespQ_DEQ, - sq_retryHandler_prepareRetryRespQ_EMPTY_N, - sq_retryHandler_prepareRetryRespQ_ENQ, - sq_retryHandler_prepareRetryRespQ_FULL_N; - - // ports of submodule sq_retryHandler_resetReqQ - wire sq_retryHandler_resetReqQ_CLR, - sq_retryHandler_resetReqQ_DEQ, - sq_retryHandler_resetReqQ_D_IN, - sq_retryHandler_resetReqQ_D_OUT, - sq_retryHandler_resetReqQ_EMPTY_N, - sq_retryHandler_resetReqQ_ENQ, - sq_retryHandler_resetReqQ_FULL_N; - - // ports of submodule sq_retryHandler_resetRetryCntQ - wire sq_retryHandler_resetRetryCntQ_CLR, - sq_retryHandler_resetRetryCntQ_DEQ, - sq_retryHandler_resetRetryCntQ_D_IN, - sq_retryHandler_resetRetryCntQ_EMPTY_N, - sq_retryHandler_resetRetryCntQ_ENQ, - sq_retryHandler_resetRetryCntQ_FULL_N; - - // ports of submodule sq_retryHandler_resetTimeOutQ - wire sq_retryHandler_resetTimeOutQ_CLR, - sq_retryHandler_resetTimeOutQ_DEQ, - sq_retryHandler_resetTimeOutQ_D_IN, - sq_retryHandler_resetTimeOutQ_EMPTY_N, - sq_retryHandler_resetTimeOutQ_ENQ, - sq_retryHandler_resetTimeOutQ_FULL_N; - - // ports of submodule sq_retryHandler_retryActionQ - wire [97 : 0] sq_retryHandler_retryActionQ_D_IN, - sq_retryHandler_retryActionQ_D_OUT; - wire sq_retryHandler_retryActionQ_CLR, - sq_retryHandler_retryActionQ_DEQ, - sq_retryHandler_retryActionQ_EMPTY_N, - sq_retryHandler_retryActionQ_ENQ, - sq_retryHandler_retryActionQ_FULL_N; - - // ports of submodule sq_retryHandler_retryNotificationQ - wire [97 : 0] sq_retryHandler_retryNotificationQ_D_IN, - sq_retryHandler_retryNotificationQ_D_OUT; - wire sq_retryHandler_retryNotificationQ_CLR, - sq_retryHandler_retryNotificationQ_DEQ, - sq_retryHandler_retryNotificationQ_EMPTY_N, - sq_retryHandler_retryNotificationQ_ENQ, - sq_retryHandler_retryNotificationQ_FULL_N; - - // ports of submodule sq_retryHandler_retryReqQ - wire [96 : 0] sq_retryHandler_retryReqQ_D_IN, - sq_retryHandler_retryReqQ_D_OUT; - wire sq_retryHandler_retryReqQ_CLR, - sq_retryHandler_retryReqQ_DEQ, - sq_retryHandler_retryReqQ_EMPTY_N, - sq_retryHandler_retryReqQ_ENQ, - sq_retryHandler_retryReqQ_FULL_N; - - // ports of submodule sq_retryHandler_retryRespQ - wire sq_retryHandler_retryRespQ_CLR, - sq_retryHandler_retryRespQ_DEQ, - sq_retryHandler_retryRespQ_D_IN, - sq_retryHandler_retryRespQ_D_OUT, - sq_retryHandler_retryRespQ_EMPTY_N, - sq_retryHandler_retryRespQ_ENQ, - sq_retryHandler_retryRespQ_FULL_N; - - // ports of submodule sq_retryHandler_timeOutNotificationQ - wire sq_retryHandler_timeOutNotificationQ_CLR, - sq_retryHandler_timeOutNotificationQ_DEQ, - sq_retryHandler_timeOutNotificationQ_D_IN, - sq_retryHandler_timeOutNotificationQ_D_OUT, - sq_retryHandler_timeOutNotificationQ_EMPTY_N, - sq_retryHandler_timeOutNotificationQ_ENQ, - sq_retryHandler_timeOutNotificationQ_FULL_N; - - // ports of submodule sq_retryHandler_timeOutTriggerQ - wire sq_retryHandler_timeOutTriggerQ_CLR, - sq_retryHandler_timeOutTriggerQ_DEQ, - sq_retryHandler_timeOutTriggerQ_D_IN, - sq_retryHandler_timeOutTriggerQ_EMPTY_N, - sq_retryHandler_timeOutTriggerQ_ENQ, - sq_retryHandler_timeOutTriggerQ_FULL_N; - - // ports of submodule sq_retryHandler_updateRetryCntQ - wire [3 : 0] sq_retryHandler_updateRetryCntQ_D_IN, - sq_retryHandler_updateRetryCntQ_D_OUT; - wire sq_retryHandler_updateRetryCntQ_CLR, - sq_retryHandler_updateRetryCntQ_DEQ, - sq_retryHandler_updateRetryCntQ_EMPTY_N, - sq_retryHandler_updateRetryCntQ_ENQ, - sq_retryHandler_updateRetryCntQ_FULL_N; - - // ports of submodule sq_workCompGenSQ_dmaWaitingQ - wire [856 : 0] sq_workCompGenSQ_dmaWaitingQ_D_IN, - sq_workCompGenSQ_dmaWaitingQ_D_OUT; - wire sq_workCompGenSQ_dmaWaitingQ_CLR, - sq_workCompGenSQ_dmaWaitingQ_DEQ, - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N, - sq_workCompGenSQ_dmaWaitingQ_ENQ, - sq_workCompGenSQ_dmaWaitingQ_FULL_N; - - // ports of submodule sq_workCompGenSQ_genWorkCompQ - wire [856 : 0] sq_workCompGenSQ_genWorkCompQ_D_IN, - sq_workCompGenSQ_genWorkCompQ_D_OUT; - wire sq_workCompGenSQ_genWorkCompQ_CLR, - sq_workCompGenSQ_genWorkCompQ_DEQ, - sq_workCompGenSQ_genWorkCompQ_EMPTY_N, - sq_workCompGenSQ_genWorkCompQ_ENQ, - sq_workCompGenSQ_genWorkCompQ_FULL_N; - - // ports of submodule sq_workCompGenSQ_pendingWorkCompQ4SQ - wire [632 : 0] sq_workCompGenSQ_pendingWorkCompQ4SQ_D_IN, - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT; - wire sq_workCompGenSQ_pendingWorkCompQ4SQ_CLR, - sq_workCompGenSQ_pendingWorkCompQ4SQ_DEQ, - sq_workCompGenSQ_pendingWorkCompQ4SQ_EMPTY_N, - sq_workCompGenSQ_pendingWorkCompQ4SQ_ENQ, - sq_workCompGenSQ_pendingWorkCompQ4SQ_FULL_N; - - // ports of submodule sq_workCompGenSQ_workCompOutQ4SQ - wire [221 : 0] sq_workCompGenSQ_workCompOutQ4SQ_D_IN, - sq_workCompGenSQ_workCompOutQ4SQ_D_OUT; - wire sq_workCompGenSQ_workCompOutQ4SQ_CLR, - sq_workCompGenSQ_workCompOutQ4SQ_DEQ, - sq_workCompGenSQ_workCompOutQ4SQ_EMPTY_N, - sq_workCompGenSQ_workCompOutQ4SQ_ENQ, - sq_workCompGenSQ_workCompOutQ4SQ_FULL_N; - - // ports of submodule workReqQ - wire [600 : 0] workReqQ_D_IN, workReqQ_D_OUT; - wire workReqQ_CLR, - workReqQ_DEQ, - workReqQ_EMPTY_N, - workReqQ_ENQ, - workReqQ_FULL_N; - - // rule scheduling signals - reg CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll; - wire CAN_FIRE_RL_cancelDmaReadSQ, - CAN_FIRE_RL_cntrl_canonicalize, - CAN_FIRE_RL_cntrl_onCreate, - CAN_FIRE_RL_cntrl_onERR, - CAN_FIRE_RL_cntrl_onINIT, - CAN_FIRE_RL_cntrl_onRTR, - CAN_FIRE_RL_cntrl_onRTS, - CAN_FIRE_RL_cntrl_onReset, - CAN_FIRE_RL_cntrl_onSQD, - CAN_FIRE_RL_cntrl_resetAndClear, - CAN_FIRE_RL_cntrl_restore, - CAN_FIRE_RL_cntrl_updatePreState, - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp, - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq, - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear, - CAN_FIRE_RL_dmaReadCntrl4SQ_issueDmaReq, - CAN_FIRE_RL_dmaReadCntrl4SQ_recvDmaResp, - CAN_FIRE_RL_dmaReadCntrl4SQ_recvReq, - CAN_FIRE_RL_dmaReadCntrl4SQ_resetAndClear, - CAN_FIRE_RL_dmaReadCntrl4SQ_setGracefulStop, - CAN_FIRE_RL_errTrigger, - CAN_FIRE_RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut, - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding, - CAN_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portA, - CAN_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portB, - CAN_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portB_read_data, - CAN_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq, - CAN_FIRE_RL_payloadGenerator4SQ_resetAndClear, - CAN_FIRE_RL_resetAndClear, - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_checkPendingNewWorkReqCnt, - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt, - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_flushWR, - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_genPendingWR, - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrement, - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr, - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_increment, - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_write, - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_resetAndClear, - CAN_FIRE_RL_sq_pendingWorkReq2Q_mkConnectionGetPut, - CAN_FIRE_RL_sq_pendingWorkReqBuf_canonicalize, - CAN_FIRE_RL_sq_pendingWorkReqBuf_check, - CAN_FIRE_RL_sq_pendingWorkReqBuf_fifoMode, - CAN_FIRE_RL_sq_pendingWorkReqBuf_preScanMode, - CAN_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange, - CAN_FIRE_RL_sq_pendingWorkReqBuf_scanNext, - CAN_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn1, - CAN_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn2, - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq, - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq, - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq, - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt, - CAN_FIRE_RL_sq_reqGenSQ_errFlushWR, - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader, - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq, - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq, - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen, - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_connect, - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader, - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_resetAndClear, - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag, - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData, - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader, - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData, - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_resetAndClear, - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp, - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq, - CAN_FIRE_RL_sq_reqGenSQ_resetAndClear, - CAN_FIRE_RL_sq_resetAndClear, - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace, - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr, - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen, - CAN_FIRE_RL_sq_respHandleSQ_canonicalize, - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp, - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen, - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr, - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr, - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq, - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp, - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp, - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq, - CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ, - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType, - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq, - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo, - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo, - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp, - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader, - CAN_FIRE_RL_sq_respHandleSQ_resetAndClear, - CAN_FIRE_RL_sq_respHandleSQ_retryFlushDone, - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload, - CAN_FIRE_RL_sq_retryHandler_checkPartialRetry, - CAN_FIRE_RL_sq_retryHandler_checkTimeOut, - CAN_FIRE_RL_sq_retryHandler_handleNotifiedRetryAndTimeOut, - CAN_FIRE_RL_sq_retryHandler_handleRetryAction, - CAN_FIRE_RL_sq_retryHandler_handleRetryCntUpdate, - CAN_FIRE_RL_sq_retryHandler_initRetry, - CAN_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer, - CAN_FIRE_RL_sq_retryHandler_modifyPartialRetryWR, - CAN_FIRE_RL_sq_retryHandler_recvResetReq, - CAN_FIRE_RL_sq_retryHandler_recvRetryReq, - CAN_FIRE_RL_sq_retryHandler_resetAndClear, - CAN_FIRE_RL_sq_retryHandler_rnrCheck, - CAN_FIRE_RL_sq_retryHandler_rnrWait, - CAN_FIRE_RL_sq_retryHandler_sendRetryResp, - CAN_FIRE_RL_sq_retryHandler_startPreRetry, - CAN_FIRE_RL_sq_retryHandler_startRetry, - CAN_FIRE_RL_sq_retryHandler_stopScanQ, - CAN_FIRE_RL_sq_retryHandler_waitRetryDone, - CAN_FIRE_RL_sq_retryHandler_waitRetryFinish, - CAN_FIRE_RL_sq_workCompGenSQ_errFlushSQ, - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ, - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ, - CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ, - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ, - CAN_FIRE_RL_sq_workCompGenSQ_resetAndClear, - CAN_FIRE_RL_sq_workCompGenSQ_start, - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ, - CAN_FIRE_RL_waitGracefulStop, - CAN_FIRE_dmaReadClt4SQ_request_get, - CAN_FIRE_dmaReadClt4SQ_response_put, - CAN_FIRE_rdmaReqPipeOut_deq, - CAN_FIRE_respPktPipeIn_payload_put, - CAN_FIRE_respPktPipeIn_pktMetaData_put, - CAN_FIRE_srvPortQP_request_put, - CAN_FIRE_srvPortQP_response_get, - CAN_FIRE_workCompPipeOutSQ_deq, - CAN_FIRE_workReqIn_put, - WILL_FIRE_RL_cancelDmaReadSQ, - WILL_FIRE_RL_cntrl_canonicalize, - WILL_FIRE_RL_cntrl_onCreate, - WILL_FIRE_RL_cntrl_onERR, - WILL_FIRE_RL_cntrl_onINIT, - WILL_FIRE_RL_cntrl_onRTR, - WILL_FIRE_RL_cntrl_onRTS, - WILL_FIRE_RL_cntrl_onReset, - WILL_FIRE_RL_cntrl_onSQD, - WILL_FIRE_RL_cntrl_resetAndClear, - WILL_FIRE_RL_cntrl_restore, - WILL_FIRE_RL_cntrl_updatePreState, - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp, - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq, - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear, - WILL_FIRE_RL_dmaReadCntrl4SQ_issueDmaReq, - WILL_FIRE_RL_dmaReadCntrl4SQ_recvDmaResp, - WILL_FIRE_RL_dmaReadCntrl4SQ_recvReq, - WILL_FIRE_RL_dmaReadCntrl4SQ_resetAndClear, - WILL_FIRE_RL_dmaReadCntrl4SQ_setGracefulStop, - WILL_FIRE_RL_errTrigger, - WILL_FIRE_RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut, - WILL_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding, - WILL_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portA, - WILL_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portB, - WILL_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portB_read_data, - WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq, - WILL_FIRE_RL_payloadGenerator4SQ_resetAndClear, - WILL_FIRE_RL_resetAndClear, - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_checkPendingNewWorkReqCnt, - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt, - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_flushWR, - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_genPendingWR, - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrement, - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr, - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_increment, - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_write, - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_resetAndClear, - WILL_FIRE_RL_sq_pendingWorkReq2Q_mkConnectionGetPut, - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize, - WILL_FIRE_RL_sq_pendingWorkReqBuf_check, - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll, - WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode, - WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode, - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange, - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanNext, - WILL_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn1, - WILL_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn2, - WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq, - WILL_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq, - WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq, - WILL_FIRE_RL_sq_reqGenSQ_countReqPkt, - WILL_FIRE_RL_sq_reqGenSQ_errFlushWR, - WILL_FIRE_RL_sq_reqGenSQ_genReqHeader, - WILL_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq, - WILL_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq, - WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen, - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_connect, - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader, - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_resetAndClear, - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag, - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData, - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader, - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData, - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_resetAndClear, - WILL_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp, - WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq, - WILL_FIRE_RL_sq_reqGenSQ_resetAndClear, - WILL_FIRE_RL_sq_resetAndClear, - WILL_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace, - WILL_FIRE_RL_sq_respHandleSQ_calcReadRespAddr, - WILL_FIRE_RL_sq_respHandleSQ_calcReadRespLen, - WILL_FIRE_RL_sq_respHandleSQ_canonicalize, - WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp, - WILL_FIRE_RL_sq_respHandleSQ_checkReadRespLen, - WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr, - WILL_FIRE_RL_sq_respHandleSQ_checkTimeOutErr, - WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq, - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp, - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp, - WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq, - WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ, - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType, - WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq, - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo, - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo, - WILL_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp, - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader, - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear, - WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone, - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload, - WILL_FIRE_RL_sq_retryHandler_checkPartialRetry, - WILL_FIRE_RL_sq_retryHandler_checkTimeOut, - WILL_FIRE_RL_sq_retryHandler_handleNotifiedRetryAndTimeOut, - WILL_FIRE_RL_sq_retryHandler_handleRetryAction, - WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate, - WILL_FIRE_RL_sq_retryHandler_initRetry, - WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer, - WILL_FIRE_RL_sq_retryHandler_modifyPartialRetryWR, - WILL_FIRE_RL_sq_retryHandler_recvResetReq, - WILL_FIRE_RL_sq_retryHandler_recvRetryReq, - WILL_FIRE_RL_sq_retryHandler_resetAndClear, - WILL_FIRE_RL_sq_retryHandler_rnrCheck, - WILL_FIRE_RL_sq_retryHandler_rnrWait, - WILL_FIRE_RL_sq_retryHandler_sendRetryResp, - WILL_FIRE_RL_sq_retryHandler_startPreRetry, - WILL_FIRE_RL_sq_retryHandler_startRetry, - WILL_FIRE_RL_sq_retryHandler_stopScanQ, - WILL_FIRE_RL_sq_retryHandler_waitRetryDone, - WILL_FIRE_RL_sq_retryHandler_waitRetryFinish, - WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ, - WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ, - WILL_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ, - WILL_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ, - WILL_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ, - WILL_FIRE_RL_sq_workCompGenSQ_resetAndClear, - WILL_FIRE_RL_sq_workCompGenSQ_start, - WILL_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ, - WILL_FIRE_RL_waitGracefulStop, - WILL_FIRE_dmaReadClt4SQ_request_get, - WILL_FIRE_dmaReadClt4SQ_response_put, - WILL_FIRE_rdmaReqPipeOut_deq, - WILL_FIRE_respPktPipeIn_payload_put, - WILL_FIRE_respPktPipeIn_pktMetaData_put, - WILL_FIRE_srvPortQP_request_put, - WILL_FIRE_srvPortQP_response_get, - WILL_FIRE_workCompPipeOutSQ_deq, - WILL_FIRE_workReqIn_put; - - // inputs to muxes for submodule ports - reg [63 : 0] MUX_dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_write_1__VAL_2; - reg [26 : 0] MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2; - wire [1469 : 0] MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_1, - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_3, - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_4, - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_5; - wire [679 : 0] MUX_sq_pendingWorkReqBuf_headReg_write_1__VAL_2; - wire [289 : 0] MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__VAL_2, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__VAL_3, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_write_1__VAL_1; - wire [273 : 0] MUX_cntrl_respQ_enq_1__VAL_1, - MUX_cntrl_respQ_enq_1__VAL_2, - MUX_cntrl_respQ_enq_1__VAL_3, - MUX_cntrl_respQ_enq_1__VAL_4, - MUX_cntrl_respQ_enq_1__VAL_5, - MUX_cntrl_respQ_enq_1__VAL_6, - MUX_cntrl_respQ_enq_1__VAL_7; - wire [221 : 0] MUX_sq_workCompGenSQ_workCompOutQ4SQ_enq_1__VAL_2; - wire [41 : 0] MUX_sq_retryHandler_timeOutCntReg_write_1__VAL_1; - wire [26 : 0] MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_1; - wire [24 : 0] MUX_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_write_1__VAL_1, - MUX_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_write_1__VAL_2; - wire [7 : 0] MUX_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_write_1__VAL_1; - wire [4 : 0] MUX_cntrl_nextStateReg_port0__write_1__VAL_2, - MUX_cntrl_nextStateReg_port0__write_1__VAL_7; - wire [2 : 0] MUX_sq_retryHandler_retryCntReg_write_1__VAL_1, - MUX_sq_retryHandler_retryHandleStateReg_write_1__VAL_3, - MUX_sq_retryHandler_rnrCntReg_write_1__VAL_1; - wire [1 : 0] MUX_sq_pendingWorkReqBuf_deqPtrReg_write_1__VAL_1, - MUX_sq_pendingWorkReqBuf_enqPtrReg_write_1__VAL_1, - MUX_sq_pendingWorkReqBuf_scanPtrReg_write_1__VAL_2, - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__VAL_3, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__VAL_1, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__VAL_2, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_1, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_2, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_3; - wire MUX_cntrl_nextStateReg_port0__write_1__SEL_1, - MUX_cntrl_nextStateReg_port0__write_1__SEL_2, - MUX_cntrl_nextStateReg_port0__write_1__SEL_3, - MUX_cntrl_nextStateReg_port0__write_1__SEL_4, - MUX_cntrl_nextStateReg_port0__write_1__SEL_5, - MUX_cntrl_nextStateReg_port0__write_1__SEL_6, - MUX_cntrl_nextStateReg_port0__write_1__SEL_7, - MUX_cntrl_npsnReg_write_1__SEL_1, - MUX_dmaReadCntrl4SQ_addrChunkSrv_busyReg_write_1__VAL_1, - MUX_dmaReadCntrl4SQ_addrChunkSrv_isFirstReg_write_1__SEL_1, - MUX_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_write_1__SEL_1, - MUX_sq_pendingWorkReqBuf_emptyReg_write_1__VAL_1, - MUX_sq_pendingWorkReqBuf_fullReg_write_1__VAL_1, - MUX_sq_pendingWorkReqBuf_headReg_write_1__SEL_1, - MUX_sq_pendingWorkReqBuf_scanAlmostDoneReg_write_1__VAL_1, - MUX_sq_pendingWorkReqBuf_scanAlmostDoneReg_write_1__VAL_2, - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_1, - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_2, - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_3, - MUX_sq_reqGenSQ_isFirstOrOnlyReqPktReg_write_1__VAL_1, - MUX_sq_reqGenSQ_isNormalStateReg_write_1__SEL_1, - MUX_sq_reqGenSQ_pendingWorkReqOutQ_enq_1__SEL_1, - MUX_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg_write_1__VAL_1, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__SEL_1, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__SEL_1, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_write_1__SEL_1, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__SEL_2, - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__SEL_4, - MUX_sq_respHandleSQ_hasInternalErrReg_port0__write_1__SEL_1, - MUX_sq_respHandleSQ_hasTimeOutErrReg_port0__write_1__SEL_1, - MUX_sq_respHandleSQ_incomingRespQ_enq_1__SEL_1, - MUX_sq_respHandleSQ_preRdmaOpCodeReg_write_1__SEL_1, - MUX_sq_respHandleSQ_preStageStateReg_write_1__SEL_1, - MUX_sq_respHandleSQ_recvRetryRespReg_write_1__SEL_2, - MUX_sq_retryHandler_disableRetryCntReg_write_1__SEL_1, - MUX_sq_retryHandler_disableTimeOutReg_write_1__SEL_1, - MUX_sq_retryHandler_isRnrWaitCntZeroReg_write_1__SEL_1, - MUX_sq_retryHandler_isRnrWaitCntZeroReg_write_1__VAL_1, - MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__SEL_1, - MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__VAL_1, - MUX_sq_retryHandler_isTimeOutCntLowPartZeroReg_write_1__VAL_1, - MUX_sq_retryHandler_pauseRetryHandleReg_write_1__SEL_1, - MUX_sq_retryHandler_retryCntReg_write_1__SEL_1, - MUX_sq_retryHandler_retryCntrlStateReg_port0__write_1__SEL_1, - MUX_sq_retryHandler_retryHandleStateReg_write_1__SEL_1, - MUX_sq_retryHandler_retryHandleStateReg_write_1__SEL_2, - MUX_sq_retryHandler_rnrCntReg_write_1__SEL_1, - MUX_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_write_1__SEL_1, - MUX_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_write_1__SEL_2, - MUX_sq_workCompGenSQ_workCompOutQ4SQ_enq_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [63 : 0] v__h3884; - reg [63 : 0] v__h4313; - reg [63 : 0] v__h4717; - reg [63 : 0] v__h5169; - reg [63 : 0] v__h5606; - reg [63 : 0] v__h5829; - reg [63 : 0] v__h6391; - reg [63 : 0] v__h6614; - reg [63 : 0] v__h7317; - reg [63 : 0] v__h9162; - reg [63 : 0] v__h13758; - reg [63 : 0] v__h14296; - reg [63 : 0] v__h43308; - reg [63 : 0] v__h50137; - reg [63 : 0] v__h50289; - reg [63 : 0] v__h50515; - reg [63 : 0] v__h50628; - reg [63 : 0] v__h50773; - reg [63 : 0] v__h54300; - reg [63 : 0] v__h58741; - reg [63 : 0] v__h61335; - reg [63 : 0] v__h63194; - reg [63 : 0] v__h69848; - reg [63 : 0] v__h73012; - reg [63 : 0] v__h48088; - reg [63 : 0] v__h48212; - reg [63 : 0] v__h48664; - reg [63 : 0] v__h93157; - reg [63 : 0] v__h93514; - reg [63 : 0] v__h93774; - reg [63 : 0] v__h57516; - reg [63 : 0] v__h97761; - reg [63 : 0] v__h97941; - reg [63 : 0] v__h98281; - reg [63 : 0] v__h98457; - reg [63 : 0] v__h101559; - reg [63 : 0] v__h101795; - reg [63 : 0] v__h101959; - reg [63 : 0] v__h103981; - reg [63 : 0] v__h104178; - reg [63 : 0] v__h106970; - reg [63 : 0] v__h107194; - reg [63 : 0] v__h107798; - reg [63 : 0] v__h109873; - reg [63 : 0] v__h117067; - reg [63 : 0] v__h117291; - reg [63 : 0] v__h117643; - reg [63 : 0] v__h122840; - reg [63 : 0] v__h36446; - reg [63 : 0] v__h36711; - reg [63 : 0] v__h37491; - reg [63 : 0] v__h38910; - reg [63 : 0] v__h35350; - reg [63 : 0] v__h35692; - reg [63 : 0] v__h35995; - reg [63 : 0] v__h34459; - reg [63 : 0] v__h34954; - reg [63 : 0] v__h98868; - reg [63 : 0] v__h99106; - reg [63 : 0] v__h120515; - reg [63 : 0] v__h29295; - reg [63 : 0] v__h29442; - reg [63 : 0] v__h29608; - reg [63 : 0] v__h29763; - reg [63 : 0] v__h29891; - reg [63 : 0] v__h30076; - reg [63 : 0] v__h30289; - reg [63 : 0] v__h30463; - reg [63 : 0] v__h30613; - reg [63 : 0] v__h24390; - reg [63 : 0] v__h24503; - reg [63 : 0] v__h24769; - reg [63 : 0] v__h24880; - reg [63 : 0] v__h25249; - reg [63 : 0] v__h25475; - reg [63 : 0] v__h43204; - reg [63 : 0] v__h118758; - reg [63 : 0] v__h126312; - reg [63 : 0] v__h3196; - reg [63 : 0] v__h3517; - reg [63 : 0] v__h129863; - reg [63 : 0] v__h130013; - reg [63 : 0] v__h7672; - // synopsys translate_on - - // remaining internal signals - reg [511 : 0] CASE_cntrl_sqTypeReg_2_a3239_3_a3239_a3241__q6, - CASE_cntrl_sqTypeReg_2_a3243_3_a3243_a3245__q7, - CASE_cntrl_sqTypeReg_2_a3247_3_a3247_4_a3249_a_ETC__q8, - CASE_cntrl_sqTypeReg_2_a3253_3_a3253_4_a3255_a_ETC__q9, - value__h63238, - value__h69886; - reg [63 : 0] SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d838, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d855, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d768, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d786, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d804, - value__h99740, - value__h99767, - x__h39125, - x__h39664; - reg [41 : 0] x__h32835; - reg [31 : 0] CASE_payloadGenerator4SQ_payloadGenReqQD_OUT__ETC__q1, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d871, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d888, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d937, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d792, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d798, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d810, - value__h99797, - value__h99824, - value__h99908, - x__h39399; - reg [24 : 0] SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d994, - tmpPktNum__h9229, - x__h52242; - reg [23 : 0] SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d904, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d921, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d961, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d978, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d816, - value__h99854, - value__h99881, - value__h99939, - value__h99966, - x__h6205, - x__h63485; - reg [15 : 0] IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d99; - reg [11 : 0] pmtuResidue__h9230, x__h52371; - reg [10 : 0] IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d155; - reg [7 : 0] CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34, - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d95, - x__h6243; - reg [6 : 0] CASE_cntrl_sqTypeReg_2_12_3_12_4_20_16__q4, - CASE_cntrl_sqTypeReg_2_28_3_28_32__q2, - CASE_cntrl_sqTypeReg_2_b3244_3_b3244_b3246__q3, - CASE_cntrl_sqTypeReg_2_b3254_3_b3254_4_24_b3258__q5, - value__h68654, - value__h72405; - reg [4 : 0] CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q22, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q23, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d780, - enumBits__h93928; - reg [3 : 0] CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28, - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q32, - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d60, - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4298, - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4302, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d774; - reg [2 : 0] CASE_sq_respHandleSQ_pendingRespQD_OUT_BITS_4_ETC__q33, - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208; - reg [1 : 0] CASE_respPktPipe_metaDataQD_OUT_BITS_527_TO_5_ETC__q29, - CASE_respPktPipe_metaDataQD_OUT_BITS_529_TO_5_ETC__q30, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q24, - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q31, - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4308, - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4312; - reg CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q18, - CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q19, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q15, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q16, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q17, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q20, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q21, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q25, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q26, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q27, - CASE_sq_respHandleSQ_preRdmaOpCodeReg_13_NOT_s_ETC__q14, - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q10, - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q11, - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q12, - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q13, - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q35, - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q36, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2711, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2722, - IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4824, - IF_sq_respHandleSQ_pendingRetryCheckQ_first__9_ETC___d4989, - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4271, - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4275, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074, - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3935, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1001, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1007, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1620, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1621, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1624, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1626, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1629, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1631, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1634, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1636, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1653, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d822, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d828, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d845, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d861, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d878, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d894, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d911, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d927, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d951, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d968, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d984; - wire [520 : 0] IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3420; - wire [511 : 0] IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_cntrl__ETC___d3311, - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_sq_req_ETC___d3316, - a__h63239, - a__h63241, - a__h63243, - a__h63245, - a__h63247, - a__h63249, - a__h63251, - a__h63253, - a__h63255, - a__h63257, - a__h63259, - a__h63261, - a__h63269, - a__h63272, - a__h69887, - a__h69889, - a__h69891, - a__h69893, - a__h69903, - a__h69905, - leftShiftHeaderData__h47318, - tmpData__h49087, - x__h47525, - x__h74169; - wire [255 : 0] leftShiftData__h49541, - rightShiftHeaderLastFragData__h48757, - x__read_data__h12578; - wire [77 : 0] NOT_sq_retryHandler_retryReasonReg_431_EQ_4_46_ETC___d1656, - sq_reqGenSQ_workReqPsnQ_first__498_BIT_4_499_O_ETC___d2558; - wire [63 : 0] _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443, - leftShiftHeaderByteEn__h47319, - tmpByteEn__h49088, - x__h47528; - wire [41 : 0] x__h33715; - wire [31 : 0] _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577, - leftShiftByteEn__h49542, - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_fi_ETC___d1852, - rightShiftHeaderLastFragByteEn__h48758, - x__h14424, - x__read_byteEn__h12579, - y_avValue_byteEn__h17055; - wire [24 : 0] _theResult___snd__h61670, - a__h52253, - a__h52263, - a__h52273, - a__h52283, - a__h52293, - a__h9345, - a__h9355, - a__h9365, - a__h9375, - a__h9385, - remainingPktNum___1__h61681, - remainingPktNum___1__h61739, - totalPktNum__h55209, - x__h37628, - x__h56223; - wire [23 : 0] curPSN__h61636, - endPktSeqNum__h56057, - nextPktSeqNum__h56056, - startPlusOne__h56122, - v__h37423, - x__h56104; - wire [16 : 0] IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1770, - sq_reqGenSQ_pendingReqHeaderQ_first__424_BITS__ETC___d3563; - wire [12 : 0] addrChunkResp_chunkLen__h10586, - sq_respHandleSQ_pendingRetryCheckQ_first__949__ETC___d5187; - wire [11 : 0] b__h52254, - b__h52264, - b__h52274, - b__h52284, - b__h9346, - b__h9356, - b__h9366, - b__h9376; - wire [9 : 0] x__h12662, x__h12913; - wire [8 : 0] headerLastFragValidBitNum__h47980; - wire [7 : 0] x__h16825, x__h41815, x__h41903, y__h42773; - wire [6 : 0] IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_12_ELSE_16___d3346, - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_sq_req_ETC___d3349, - b__h63244, - b__h63246, - b__h63254, - b__h63258, - b__h69892, - b__h69894, - remainingHeaderLen__h47316, - x__h81436; - wire [5 : 0] headerLastFragInvalidByteNum__h47982, - lastFragValidByteNumWithPadding__h13828, - lastFragValidByteNum__h13827, - lastFragValidByteNum__h13849, - lastFragValidByteNum__h87658; - wire [4 : 0] rnrTimer__h36783; - wire [2 : 0] x__h35617, x__h35647; - wire [1 : 0] IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1737, - IF_sq_retryHandler_retryRespQ_first__023_THEN__ETC___d5182, - bits__h49179, - bth_padCnt__h63283, - bth_padCnt__h69915, - padCnt__h13826, - padCnt__h63476, - remainingHeaderFragNum__h47317; - wire IF_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_ETC___d1515, - IF_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_ETC___d4106, - IF_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_ETC___d4116, - IF_IF_sq_retryHandler_updateRetryCntQ_first__3_ETC___d1388, - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d1501, - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4097, - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4105, - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4108, - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4115, - IF_cntrl_npsnReg_41_BIT_23_518_EQ_IF_IF_sq_req_ETC___d2534, - IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d1880, - IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d2074, - IF_sq_pendingWorkReqBuf_pushReg_port1__read__7_ETC___d702, - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1734, - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1742, - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1745, - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_24_ETC___d3578, - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_26_ETC___d3579, - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_62_ETC___d3580, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2724, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2730, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2734, - IF_sq_reqGenSQ_workCompGenReqOutQ_notEmpty__69_ETC___d5707, - IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844, - IF_sq_respHandleSQ_pendingRetryCheckQ_first__9_ETC___d5037, - IF_sq_retryHandler_resetTimeOutQ_notEmpty__176_ETC___d1197, - IF_sq_retryHandler_updateRetryCntQ_first__309__ETC___d1340, - IF_sq_workCompGenSQ_genWorkCompQ_first__802_BI_ETC___d5808, - NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2524, - NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2536, - NOT_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVe_ETC___d1503, - NOT_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVe_ETC___d1514, - NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1505, - NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1516, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3783, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3794, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3806, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3822, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3836, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3851, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3867, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3870, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3884, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3887, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3902, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3905, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3921, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3927, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3941, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3947, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3956, - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3962, - NOT_cntrl_npsnReg_41_ULT_IF_IF_sq_reqGenSQ_wor_ETC___d2522, - NOT_cntrl_npsnReg_41_ULT_IF_IF_sq_reqGenSQ_wor_ETC___d2533, - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712, - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2723, - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742, - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2882, - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2889, - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2902, - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2973, - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2978, - NOT_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_77__ETC___d376, - NOT_sq_newPendingWorkReqPiptOut_pendingNewWork_ETC___d1707, - NOT_sq_pendingWorkReqPipeOut_pipeMuxOutQ_first_ETC___d1919, - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992, - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352, - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4479, - NOT_sq_respHandleSQ_retryFlushReg_616_617_OR_s_ETC___d4756, - NOT_sq_retryHandler_resetTimeOutQ_notEmpty__17_ETC___d1219, - __duses1049, - __duses1054, - __duses727, - __duses732, - __duses737, - __duses742, - __duses747, - __duses752, - __duses753, - __duses757, - __duses762, - __duses767, - __duses772, - __duses777, - __duses782, - __duses783, - __duses787, - __duses792, - __duses795, - __duses806, - __duses810, - __duses815, - __duses819, - __duses824, - __duses828, - __duses833, - __duses837, - __duses842, - __duses847, - __duses852, - __duses863, - __duses874, - __duses885, - __duses896, - __duses907, - __duses918, - __duses929, - __duses940, - __duses953, - __duses964, - __duses975, - __duses986, - __duses988, - __duses991, - __duses996, - __duses999, - cntrl_stateReg_EQ_3_AND_NOT_sq_respHandleSQ_re_ETC___d5647, - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_preSta_ETC___d3624, - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_preSta_ETC___d4329, - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_recvEr_ETC___d5683, - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690, - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_77_BITS_ETC___d366, - dmaReadCntrl4SQ_respQ_i_notEmpty__42_AND_NOT_d_ETC___d657, - payloadGenerator4SQ_payloadBufQ_rRdPtr_read__7_ETC___d487, - respPktPipe_metaDataQ_first__626_BITS_554_TO_5_ETC___d4098, - respPktPipe_metaDataQ_first__626_BITS_554_TO_5_ETC___d4109, - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAnd_ETC___d1747, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAnd_ETC___d1808, - sq_reqGenSQ_workReqCheckQ_i_notEmpty__561_AND__ETC___d2573, - sq_respHandleSQ_pendingRetryCheckQ_first__949__ETC___d5046, - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4187, - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4200, - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203, - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4208, - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4214, - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4220, - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4267, - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4697, - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4716, - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4746, - sq_retryHandler_prepareRetryRespQ_i_notEmpty___ETC___d1411, - sq_retryHandler_resetReqQ_i_notEmpty__149_AND__ETC___d1155, - sq_retryHandler_resetTimeOutQ_notEmpty__176_OR_ETC___d1209, - sq_retryHandler_updateRetryCntQ_i_notEmpty__30_ETC___d1313, - sq_workCompGenSQ_dmaWaitingQ_i_notFull__721_AN_ETC___d5767, - x__h87589; - - // action method srvPortQP_request_put - assign RDY_srvPortQP_request_put = cntrl_reqQ_FULL_N ; - assign CAN_FIRE_srvPortQP_request_put = cntrl_reqQ_FULL_N ; - assign WILL_FIRE_srvPortQP_request_put = EN_srvPortQP_request_put ; - - // actionvalue method srvPortQP_response_get - assign srvPortQP_response_get = cntrl_respQ_D_OUT ; - assign RDY_srvPortQP_response_get = cntrl_respQ_EMPTY_N ; - assign CAN_FIRE_srvPortQP_response_get = cntrl_respQ_EMPTY_N ; - assign WILL_FIRE_srvPortQP_response_get = EN_srvPortQP_response_get ; - - // action method workReqIn_put - assign RDY_workReqIn_put = workReqQ_FULL_N ; - assign CAN_FIRE_workReqIn_put = workReqQ_FULL_N ; - assign WILL_FIRE_workReqIn_put = EN_workReqIn_put ; - - // actionvalue method dmaReadClt4SQ_request_get - assign dmaReadClt4SQ_request_get = dmaReadProxy4SQ_reqQ_D_OUT ; - assign RDY_dmaReadClt4SQ_request_get = dmaReadProxy4SQ_reqQ_EMPTY_N ; - assign CAN_FIRE_dmaReadClt4SQ_request_get = dmaReadProxy4SQ_reqQ_EMPTY_N ; - assign WILL_FIRE_dmaReadClt4SQ_request_get = EN_dmaReadClt4SQ_request_get ; - - // action method dmaReadClt4SQ_response_put - assign RDY_dmaReadClt4SQ_response_put = dmaReadProxy4SQ_respQ_FULL_N ; - assign CAN_FIRE_dmaReadClt4SQ_response_put = dmaReadProxy4SQ_respQ_FULL_N ; - assign WILL_FIRE_dmaReadClt4SQ_response_put = - EN_dmaReadClt4SQ_response_put ; - - // action method respPktPipeIn_pktMetaData_put - assign RDY_respPktPipeIn_pktMetaData_put = respPktPipe_metaDataQ_FULL_N ; - assign CAN_FIRE_respPktPipeIn_pktMetaData_put = - respPktPipe_metaDataQ_FULL_N ; - assign WILL_FIRE_respPktPipeIn_pktMetaData_put = - EN_respPktPipeIn_pktMetaData_put ; - - // action method respPktPipeIn_payload_put - assign RDY_respPktPipeIn_payload_put = respPktPipe_payloadQ_FULL_N ; - assign CAN_FIRE_respPktPipeIn_payload_put = respPktPipe_payloadQ_FULL_N ; - assign WILL_FIRE_respPktPipeIn_payload_put = EN_respPktPipeIn_payload_put ; - - // value method statusSQ_comm_isCreate - assign statusSQ_comm_isCreate = cntrl_stateReg == 4'd8 ; - assign RDY_statusSQ_comm_isCreate = 1'd1 ; - - // value method statusSQ_comm_isERR - assign statusSQ_comm_isERR = cntrl_stateReg == 4'd6 ; - assign RDY_statusSQ_comm_isERR = 1'd1 ; - - // value method statusSQ_comm_isInit - assign statusSQ_comm_isInit = cntrl_stateReg == 4'd1 ; - assign RDY_statusSQ_comm_isInit = 1'd1 ; - - // value method statusSQ_comm_isReset - assign statusSQ_comm_isReset = cntrl_stateReg == 4'd0 ; - assign RDY_statusSQ_comm_isReset = 1'd1 ; - - // value method statusSQ_comm_isRTR - assign statusSQ_comm_isRTR = cntrl_stateReg == 4'd2 ; - assign RDY_statusSQ_comm_isRTR = 1'd1 ; - - // value method statusSQ_comm_isRTS - assign statusSQ_comm_isRTS = cntrl_stateReg == 4'd3 ; - assign RDY_statusSQ_comm_isRTS = 1'd1 ; - - // value method statusSQ_comm_isSQD - assign statusSQ_comm_isSQD = cntrl_stateReg == 4'd4 ; - assign RDY_statusSQ_comm_isSQD = 1'd1 ; - - // value method statusSQ_comm_isNonErr - assign statusSQ_comm_isNonErr = - cntrl_stateReg == 4'd2 || cntrl_stateReg == 4'd3 || - cntrl_stateReg == 4'd4 ; - assign RDY_statusSQ_comm_isNonErr = 1'd1 ; - - // value method statusSQ_comm_isUnknown - assign statusSQ_comm_isUnknown = cntrl_stateReg == 4'd7 ; - assign RDY_statusSQ_comm_isUnknown = 1'd1 ; - - // value method statusSQ_comm_isRTR2RTS - assign statusSQ_comm_isRTR2RTS = - cntrl_preStateReg == 4'd2 && cntrl_stateReg == 4'd3 ; - assign RDY_statusSQ_comm_isRTR2RTS = 1'd1 ; - - // value method statusSQ_comm_isStableRTS - assign statusSQ_comm_isStableRTS = - cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 ; - assign RDY_statusSQ_comm_isStableRTS = 1'd1 ; - - // value method statusSQ_comm_getAccessFlags - assign statusSQ_comm_getAccessFlags = cntrl_qpAccessFlagsReg ; - assign RDY_statusSQ_comm_getAccessFlags = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getMaxRnrCnt - assign statusSQ_comm_getMaxRnrCnt = cntrl_maxRnrCntReg ; - assign RDY_statusSQ_comm_getMaxRnrCnt = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getMaxRetryCnt - assign statusSQ_comm_getMaxRetryCnt = cntrl_maxRetryCntReg ; - assign RDY_statusSQ_comm_getMaxRetryCnt = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getMinRnrTimer - assign statusSQ_comm_getMinRnrTimer = cntrl_minRnrTimerReg ; - assign RDY_statusSQ_comm_getMinRnrTimer = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getMaxTimeOut - assign statusSQ_comm_getMaxTimeOut = cntrl_maxTimeOutReg ; - assign RDY_statusSQ_comm_getMaxTimeOut = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getPendingWorkReqNum - assign statusSQ_comm_getPendingWorkReqNum = cntrl_pendingWorkReqNumReg ; - assign RDY_statusSQ_comm_getPendingWorkReqNum = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getPendingRecvReqNum - assign statusSQ_comm_getPendingRecvReqNum = cntrl_pendingRecvReqNumReg ; - assign RDY_statusSQ_comm_getPendingRecvReqNum = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getPendingReadAtomicReqNum - assign statusSQ_comm_getPendingReadAtomicReqNum = - cntrl_pendingReadAtomicReqNumReg ; - assign RDY_statusSQ_comm_getPendingReadAtomicReqNum = - RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getPendingDestReadAtomicReqNum - assign statusSQ_comm_getPendingDestReadAtomicReqNum = - cntrl_pendingDestReadAtomicReqNumReg ; - assign RDY_statusSQ_comm_getPendingDestReadAtomicReqNum = - RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getSigAll - assign statusSQ_comm_getSigAll = cntrl_sqSigAllReg ; - assign RDY_statusSQ_comm_getSigAll = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getSQPN - assign statusSQ_comm_getSQPN = cntrl_sqpnReg ; - assign RDY_statusSQ_comm_getSQPN = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getDQPN - assign statusSQ_comm_getDQPN = cntrl_dqpnReg ; - assign RDY_statusSQ_comm_getDQPN = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getPKEY - assign statusSQ_comm_getPKEY = cntrl_pkeyReg ; - assign RDY_statusSQ_comm_getPKEY = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getQKEY - assign statusSQ_comm_getQKEY = cntrl_qkeyReg ; - assign RDY_statusSQ_comm_getQKEY = RDY_statusSQ_comm_getPMTU ; - - // value method statusSQ_comm_getPMTU - assign statusSQ_comm_getPMTU = cntrl_pmtuReg ; - assign RDY_statusSQ_comm_getPMTU = - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7 ; - - // value method statusSQ_getTypeQP - assign statusSQ_getTypeQP = cntrl_sqTypeReg ; - assign RDY_statusSQ_getTypeQP = 1'd1 ; - - // value method statusSQ_isSQ - assign statusSQ_isSQ = 1'd1 ; - assign RDY_statusSQ_isSQ = 1'd1 ; - - // value method rdmaReqPipeOut_first - assign rdmaReqPipeOut_first = sq_reqGenSQ_rdmaReqPipeOut_outputQ_D_OUT ; - assign RDY_rdmaReqPipeOut_first = - sq_reqGenSQ_rdmaReqPipeOut_outputQ_EMPTY_N ; - - // action method rdmaReqPipeOut_deq - assign RDY_rdmaReqPipeOut_deq = sq_reqGenSQ_rdmaReqPipeOut_outputQ_EMPTY_N ; - assign CAN_FIRE_rdmaReqPipeOut_deq = - sq_reqGenSQ_rdmaReqPipeOut_outputQ_EMPTY_N ; - assign WILL_FIRE_rdmaReqPipeOut_deq = EN_rdmaReqPipeOut_deq ; - - // value method rdmaReqPipeOut_notEmpty - assign rdmaReqPipeOut_notEmpty = - sq_reqGenSQ_rdmaReqPipeOut_outputQ_EMPTY_N ; - assign RDY_rdmaReqPipeOut_notEmpty = 1'd1 ; - - // value method workCompPipeOutSQ_first - assign workCompPipeOutSQ_first = sq_workCompGenSQ_workCompOutQ4SQ_D_OUT ; - assign RDY_workCompPipeOutSQ_first = - sq_workCompGenSQ_workCompOutQ4SQ_EMPTY_N ; - - // action method workCompPipeOutSQ_deq - assign RDY_workCompPipeOutSQ_deq = - sq_workCompGenSQ_workCompOutQ4SQ_EMPTY_N ; - assign CAN_FIRE_workCompPipeOutSQ_deq = - sq_workCompGenSQ_workCompOutQ4SQ_EMPTY_N ; - assign WILL_FIRE_workCompPipeOutSQ_deq = EN_workCompPipeOutSQ_deq ; - - // value method workCompPipeOutSQ_notEmpty - assign workCompPipeOutSQ_notEmpty = - sq_workCompGenSQ_workCompOutQ4SQ_EMPTY_N ; - assign RDY_workCompPipeOutSQ_notEmpty = 1'd1 ; - - // submodule cntrl_reqQ - FIFO2 #(.width(32'd301), .guarded(1'd1)) cntrl_reqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(cntrl_reqQ_D_IN), - .ENQ(cntrl_reqQ_ENQ), - .DEQ(cntrl_reqQ_DEQ), - .CLR(cntrl_reqQ_CLR), - .D_OUT(cntrl_reqQ_D_OUT), - .FULL_N(cntrl_reqQ_FULL_N), - .EMPTY_N(cntrl_reqQ_EMPTY_N)); - - // submodule cntrl_respQ - FIFO2 #(.width(32'd274), .guarded(1'd1)) cntrl_respQ(.RST(RST_N), - .CLK(CLK), - .D_IN(cntrl_respQ_D_IN), - .ENQ(cntrl_respQ_ENQ), - .DEQ(cntrl_respQ_DEQ), - .CLR(cntrl_respQ_CLR), - .D_OUT(cntrl_respQ_D_OUT), - .FULL_N(cntrl_respQ_FULL_N), - .EMPTY_N(cntrl_respQ_EMPTY_N)); - - // submodule cntrl_restoreQ - FIFO2 #(.width(32'd29), .guarded(1'd1)) cntrl_restoreQ(.RST(RST_N), - .CLK(CLK), - .D_IN(cntrl_restoreQ_D_IN), - .ENQ(cntrl_restoreQ_ENQ), - .DEQ(cntrl_restoreQ_DEQ), - .CLR(cntrl_restoreQ_CLR), - .D_OUT(cntrl_restoreQ_D_OUT), - .FULL_N(), - .EMPTY_N(cntrl_restoreQ_EMPTY_N)); - - // submodule dmaReadCntrl4SQ_addrChunkSrv_reqQ - FIFO2 #(.width(32'd99), - .guarded(1'd1)) dmaReadCntrl4SQ_addrChunkSrv_reqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_IN), - .ENQ(dmaReadCntrl4SQ_addrChunkSrv_reqQ_ENQ), - .DEQ(dmaReadCntrl4SQ_addrChunkSrv_reqQ_DEQ), - .CLR(dmaReadCntrl4SQ_addrChunkSrv_reqQ_CLR), - .D_OUT(dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT), - .FULL_N(dmaReadCntrl4SQ_addrChunkSrv_reqQ_FULL_N), - .EMPTY_N(dmaReadCntrl4SQ_addrChunkSrv_reqQ_EMPTY_N)); - - // submodule dmaReadCntrl4SQ_addrChunkSrv_respQ - FIFO2 #(.width(32'd79), - .guarded(1'd1)) dmaReadCntrl4SQ_addrChunkSrv_respQ(.RST(RST_N), - .CLK(CLK), - .D_IN(dmaReadCntrl4SQ_addrChunkSrv_respQ_D_IN), - .ENQ(dmaReadCntrl4SQ_addrChunkSrv_respQ_ENQ), - .DEQ(dmaReadCntrl4SQ_addrChunkSrv_respQ_DEQ), - .CLR(dmaReadCntrl4SQ_addrChunkSrv_respQ_CLR), - .D_OUT(dmaReadCntrl4SQ_addrChunkSrv_respQ_D_OUT), - .FULL_N(dmaReadCntrl4SQ_addrChunkSrv_respQ_FULL_N), - .EMPTY_N(dmaReadCntrl4SQ_addrChunkSrv_respQ_EMPTY_N)); - - // submodule dmaReadCntrl4SQ_pendingDmaCntrlReqQ - FIFO2 #(.width(32'd192), - .guarded(1'd1)) dmaReadCntrl4SQ_pendingDmaCntrlReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(dmaReadCntrl4SQ_pendingDmaCntrlReqQ_D_IN), - .ENQ(dmaReadCntrl4SQ_pendingDmaCntrlReqQ_ENQ), - .DEQ(dmaReadCntrl4SQ_pendingDmaCntrlReqQ_DEQ), - .CLR(dmaReadCntrl4SQ_pendingDmaCntrlReqQ_CLR), - .D_OUT(dmaReadCntrl4SQ_pendingDmaCntrlReqQ_D_OUT), - .FULL_N(dmaReadCntrl4SQ_pendingDmaCntrlReqQ_FULL_N), - .EMPTY_N(dmaReadCntrl4SQ_pendingDmaCntrlReqQ_EMPTY_N)); - - // submodule dmaReadCntrl4SQ_pendingDmaReadReqQ - FIFO2 #(.width(32'd172), - .guarded(1'd1)) dmaReadCntrl4SQ_pendingDmaReadReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(dmaReadCntrl4SQ_pendingDmaReadReqQ_D_IN), - .ENQ(dmaReadCntrl4SQ_pendingDmaReadReqQ_ENQ), - .DEQ(dmaReadCntrl4SQ_pendingDmaReadReqQ_DEQ), - .CLR(dmaReadCntrl4SQ_pendingDmaReadReqQ_CLR), - .D_OUT(dmaReadCntrl4SQ_pendingDmaReadReqQ_D_OUT), - .FULL_N(dmaReadCntrl4SQ_pendingDmaReadReqQ_FULL_N), - .EMPTY_N(dmaReadCntrl4SQ_pendingDmaReadReqQ_EMPTY_N)); - - // submodule dmaReadCntrl4SQ_reqQ - FIFO2 #(.width(32'd192), .guarded(1'd1)) dmaReadCntrl4SQ_reqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(dmaReadCntrl4SQ_reqQ_D_IN), - .ENQ(dmaReadCntrl4SQ_reqQ_ENQ), - .DEQ(dmaReadCntrl4SQ_reqQ_DEQ), - .CLR(dmaReadCntrl4SQ_reqQ_CLR), - .D_OUT(dmaReadCntrl4SQ_reqQ_D_OUT), - .FULL_N(dmaReadCntrl4SQ_reqQ_FULL_N), - .EMPTY_N(dmaReadCntrl4SQ_reqQ_EMPTY_N)); - - // submodule dmaReadCntrl4SQ_respQ - FIFO2 #(.width(32'd385), .guarded(1'd1)) dmaReadCntrl4SQ_respQ(.RST(RST_N), - .CLK(CLK), - .D_IN(dmaReadCntrl4SQ_respQ_D_IN), - .ENQ(dmaReadCntrl4SQ_respQ_ENQ), - .DEQ(dmaReadCntrl4SQ_respQ_DEQ), - .CLR(dmaReadCntrl4SQ_respQ_CLR), - .D_OUT(dmaReadCntrl4SQ_respQ_D_OUT), - .FULL_N(dmaReadCntrl4SQ_respQ_FULL_N), - .EMPTY_N(dmaReadCntrl4SQ_respQ_EMPTY_N)); - - // submodule dmaReadProxy4SQ_reqQ - FIFO2 #(.width(32'd170), .guarded(1'd1)) dmaReadProxy4SQ_reqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(dmaReadProxy4SQ_reqQ_D_IN), - .ENQ(dmaReadProxy4SQ_reqQ_ENQ), - .DEQ(dmaReadProxy4SQ_reqQ_DEQ), - .CLR(dmaReadProxy4SQ_reqQ_CLR), - .D_OUT(dmaReadProxy4SQ_reqQ_D_OUT), - .FULL_N(dmaReadProxy4SQ_reqQ_FULL_N), - .EMPTY_N(dmaReadProxy4SQ_reqQ_EMPTY_N)); - - // submodule dmaReadProxy4SQ_respQ - FIFO2 #(.width(32'd383), .guarded(1'd1)) dmaReadProxy4SQ_respQ(.RST(RST_N), - .CLK(CLK), - .D_IN(dmaReadProxy4SQ_respQ_D_IN), - .ENQ(dmaReadProxy4SQ_respQ_ENQ), - .DEQ(dmaReadProxy4SQ_respQ_DEQ), - .CLR(dmaReadProxy4SQ_respQ_CLR), - .D_OUT(dmaReadProxy4SQ_respQ_D_OUT), - .FULL_N(dmaReadProxy4SQ_respQ_FULL_N), - .EMPTY_N(dmaReadProxy4SQ_respQ_EMPTY_N)); - - // submodule payloadGenerator4SQ_bramQ2PipeOut_postBramQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) payloadGenerator4SQ_bramQ2PipeOut_postBramQ(.RST(RST_N), - .CLK(CLK), - .D_IN(payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_IN), - .ENQ(payloadGenerator4SQ_bramQ2PipeOut_postBramQ_ENQ), - .DEQ(payloadGenerator4SQ_bramQ2PipeOut_postBramQ_DEQ), - .CLR(payloadGenerator4SQ_bramQ2PipeOut_postBramQ_CLR), - .D_OUT(payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_OUT), - .FULL_N(payloadGenerator4SQ_bramQ2PipeOut_postBramQ_FULL_N), - .EMPTY_N(payloadGenerator4SQ_bramQ2PipeOut_postBramQ_EMPTY_N)); - - // submodule payloadGenerator4SQ_payloadBufQ_memory - BRAM2 #(.PIPELINED(1'd0), - .ADDR_WIDTH(32'd9), - .DATA_WIDTH(32'd290), - .MEMSIZE(10'd512)) payloadGenerator4SQ_payloadBufQ_memory(.CLKA(CLK), - .CLKB(CLK), - .ADDRA(payloadGenerator4SQ_payloadBufQ_memory_ADDRA), - .ADDRB(payloadGenerator4SQ_payloadBufQ_memory_ADDRB), - .DIA(payloadGenerator4SQ_payloadBufQ_memory_DIA), - .DIB(payloadGenerator4SQ_payloadBufQ_memory_DIB), - .WEA(payloadGenerator4SQ_payloadBufQ_memory_WEA), - .WEB(payloadGenerator4SQ_payloadBufQ_memory_WEB), - .ENA(payloadGenerator4SQ_payloadBufQ_memory_ENA), - .ENB(payloadGenerator4SQ_payloadBufQ_memory_ENB), - .DOA(), - .DOB(payloadGenerator4SQ_payloadBufQ_memory_DOB)); - - // submodule payloadGenerator4SQ_payloadGenReqQ - FIFO2 #(.width(32'd193), - .guarded(1'd1)) payloadGenerator4SQ_payloadGenReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(payloadGenerator4SQ_payloadGenReqQ_D_IN), - .ENQ(payloadGenerator4SQ_payloadGenReqQ_ENQ), - .DEQ(payloadGenerator4SQ_payloadGenReqQ_DEQ), - .CLR(payloadGenerator4SQ_payloadGenReqQ_CLR), - .D_OUT(payloadGenerator4SQ_payloadGenReqQ_D_OUT), - .FULL_N(payloadGenerator4SQ_payloadGenReqQ_FULL_N), - .EMPTY_N(payloadGenerator4SQ_payloadGenReqQ_EMPTY_N)); - - // submodule payloadGenerator4SQ_payloadGenRespQ - FIFO2 #(.width(32'd2), - .guarded(1'd1)) payloadGenerator4SQ_payloadGenRespQ(.RST(RST_N), - .CLK(CLK), - .D_IN(payloadGenerator4SQ_payloadGenRespQ_D_IN), - .ENQ(payloadGenerator4SQ_payloadGenRespQ_ENQ), - .DEQ(payloadGenerator4SQ_payloadGenRespQ_DEQ), - .CLR(payloadGenerator4SQ_payloadGenRespQ_CLR), - .D_OUT(payloadGenerator4SQ_payloadGenRespQ_D_OUT), - .FULL_N(payloadGenerator4SQ_payloadGenRespQ_FULL_N), - .EMPTY_N(payloadGenerator4SQ_payloadGenRespQ_EMPTY_N)); - - // submodule payloadGenerator4SQ_pendingGenReqQ - FIFO2 #(.width(32'd233), - .guarded(1'd1)) payloadGenerator4SQ_pendingGenReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(payloadGenerator4SQ_pendingGenReqQ_D_IN), - .ENQ(payloadGenerator4SQ_pendingGenReqQ_ENQ), - .DEQ(payloadGenerator4SQ_pendingGenReqQ_DEQ), - .CLR(payloadGenerator4SQ_pendingGenReqQ_CLR), - .D_OUT(payloadGenerator4SQ_pendingGenReqQ_D_OUT), - .FULL_N(payloadGenerator4SQ_pendingGenReqQ_FULL_N), - .EMPTY_N(payloadGenerator4SQ_pendingGenReqQ_EMPTY_N)); - - // submodule respPktPipe_metaDataQ - FIFO2 #(.width(32'd649), .guarded(1'd1)) respPktPipe_metaDataQ(.RST(RST_N), - .CLK(CLK), - .D_IN(respPktPipe_metaDataQ_D_IN), - .ENQ(respPktPipe_metaDataQ_ENQ), - .DEQ(respPktPipe_metaDataQ_DEQ), - .CLR(respPktPipe_metaDataQ_CLR), - .D_OUT(respPktPipe_metaDataQ_D_OUT), - .FULL_N(respPktPipe_metaDataQ_FULL_N), - .EMPTY_N(respPktPipe_metaDataQ_EMPTY_N)); - - // submodule respPktPipe_payloadQ - FIFO2 #(.width(32'd290), .guarded(1'd1)) respPktPipe_payloadQ(.RST(RST_N), - .CLK(CLK), - .D_IN(respPktPipe_payloadQ_D_IN), - .ENQ(respPktPipe_payloadQ_ENQ), - .DEQ(respPktPipe_payloadQ_DEQ), - .CLR(respPktPipe_payloadQ_CLR), - .D_OUT(), - .FULL_N(respPktPipe_payloadQ_FULL_N), - .EMPTY_N()); - - // submodule sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ - FIFO2 #(.width(32'd679), - .guarded(1'd1)) sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_D_IN), - .ENQ(sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_ENQ), - .DEQ(sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_DEQ), - .CLR(sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_CLR), - .D_OUT(sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_D_OUT), - .FULL_N(sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_FULL_N), - .EMPTY_N(sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_EMPTY_N)); - - // submodule sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ - FIFO2 #(.width(32'd1), - .guarded(1'd1)) sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_D_IN), - .ENQ(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_ENQ), - .DEQ(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_DEQ), - .CLR(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_CLR), - .D_OUT(), - .FULL_N(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_FULL_N), - .EMPTY_N(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_EMPTY_N)); - - // submodule sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ - FIFO2 #(.width(32'd1), - .guarded(1'd1)) sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_D_IN), - .ENQ(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_ENQ), - .DEQ(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_DEQ), - .CLR(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_CLR), - .D_OUT(), - .FULL_N(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_FULL_N), - .EMPTY_N(sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_EMPTY_N)); - - // submodule sq_pendingWorkReqBuf_itemCnt - Counter #(.width(32'd3), - .init(3'd0)) sq_pendingWorkReqBuf_itemCnt(.CLK(CLK), - .RST(RST_N), - .DATA_A(sq_pendingWorkReqBuf_itemCnt_DATA_A), - .DATA_B(sq_pendingWorkReqBuf_itemCnt_DATA_B), - .DATA_C(sq_pendingWorkReqBuf_itemCnt_DATA_C), - .DATA_F(sq_pendingWorkReqBuf_itemCnt_DATA_F), - .ADDA(sq_pendingWorkReqBuf_itemCnt_ADDA), - .ADDB(sq_pendingWorkReqBuf_itemCnt_ADDB), - .SETC(sq_pendingWorkReqBuf_itemCnt_SETC), - .SETF(sq_pendingWorkReqBuf_itemCnt_SETF), - .Q_OUT(sq_pendingWorkReqBuf_itemCnt_Q_OUT)); - - // submodule sq_pendingWorkReqBuf_scanCnt - Counter #(.width(32'd3), - .init(3'd0)) sq_pendingWorkReqBuf_scanCnt(.CLK(CLK), - .RST(RST_N), - .DATA_A(sq_pendingWorkReqBuf_scanCnt_DATA_A), - .DATA_B(sq_pendingWorkReqBuf_scanCnt_DATA_B), - .DATA_C(sq_pendingWorkReqBuf_scanCnt_DATA_C), - .DATA_F(sq_pendingWorkReqBuf_scanCnt_DATA_F), - .ADDA(sq_pendingWorkReqBuf_scanCnt_ADDA), - .ADDB(sq_pendingWorkReqBuf_scanCnt_ADDB), - .SETC(sq_pendingWorkReqBuf_scanCnt_SETC), - .SETF(sq_pendingWorkReqBuf_scanCnt_SETF), - .Q_OUT(sq_pendingWorkReqBuf_scanCnt_Q_OUT)); - - // submodule sq_pendingWorkReqBuf_scanOutQ - FIFO2 #(.width(32'd679), - .guarded(1'd1)) sq_pendingWorkReqBuf_scanOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_pendingWorkReqBuf_scanOutQ_D_IN), - .ENQ(sq_pendingWorkReqBuf_scanOutQ_ENQ), - .DEQ(sq_pendingWorkReqBuf_scanOutQ_DEQ), - .CLR(sq_pendingWorkReqBuf_scanOutQ_CLR), - .D_OUT(sq_pendingWorkReqBuf_scanOutQ_D_OUT), - .FULL_N(sq_pendingWorkReqBuf_scanOutQ_FULL_N), - .EMPTY_N(sq_pendingWorkReqBuf_scanOutQ_EMPTY_N)); - - // submodule sq_pendingWorkReqPipeOut_pipeMuxOutQ - FIFO2 #(.width(32'd679), - .guarded(1'd1)) sq_pendingWorkReqPipeOut_pipeMuxOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_IN), - .ENQ(sq_pendingWorkReqPipeOut_pipeMuxOutQ_ENQ), - .DEQ(sq_pendingWorkReqPipeOut_pipeMuxOutQ_DEQ), - .CLR(sq_pendingWorkReqPipeOut_pipeMuxOutQ_CLR), - .D_OUT(sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT), - .FULL_N(sq_pendingWorkReqPipeOut_pipeMuxOutQ_FULL_N), - .EMPTY_N(sq_pendingWorkReqPipeOut_pipeMuxOutQ_EMPTY_N)); - - // submodule sq_reqGenSQ_pendingReqHeaderQ - FIFO2 #(.width(32'd1229), - .guarded(1'd1)) sq_reqGenSQ_pendingReqHeaderQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_pendingReqHeaderQ_D_IN), - .ENQ(sq_reqGenSQ_pendingReqHeaderQ_ENQ), - .DEQ(sq_reqGenSQ_pendingReqHeaderQ_DEQ), - .CLR(sq_reqGenSQ_pendingReqHeaderQ_CLR), - .D_OUT(sq_reqGenSQ_pendingReqHeaderQ_D_OUT), - .FULL_N(sq_reqGenSQ_pendingReqHeaderQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_pendingReqHeaderQ_EMPTY_N)); - - // submodule sq_reqGenSQ_pendingWorkReqOutQ - FIFO2 #(.width(32'd679), - .guarded(1'd1)) sq_reqGenSQ_pendingWorkReqOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_pendingWorkReqOutQ_D_IN), - .ENQ(sq_reqGenSQ_pendingWorkReqOutQ_ENQ), - .DEQ(sq_reqGenSQ_pendingWorkReqOutQ_DEQ), - .CLR(sq_reqGenSQ_pendingWorkReqOutQ_CLR), - .D_OUT(sq_reqGenSQ_pendingWorkReqOutQ_D_OUT), - .FULL_N(sq_reqGenSQ_pendingWorkReqOutQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_pendingWorkReqOutQ_EMPTY_N)); - - // submodule sq_reqGenSQ_psnReqOutQ - FIFO2 #(.width(32'd24), .guarded(1'd1)) sq_reqGenSQ_psnReqOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_psnReqOutQ_D_IN), - .ENQ(sq_reqGenSQ_psnReqOutQ_ENQ), - .DEQ(sq_reqGenSQ_psnReqOutQ_DEQ), - .CLR(sq_reqGenSQ_psnReqOutQ_CLR), - .D_OUT(), - .FULL_N(sq_reqGenSQ_psnReqOutQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_psnReqOutQ_EMPTY_N)); - - // submodule sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_IN), - .ENQ(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_ENQ), - .DEQ(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_DEQ), - .CLR(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_CLR), - .D_OUT(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT), - .FULL_N(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_EMPTY_N)); - - // submodule sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ - FIFO2 #(.width(32'd17), - .guarded(1'd1)) sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_IN), - .ENQ(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_ENQ), - .DEQ(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_DEQ), - .CLR(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_CLR), - .D_OUT(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT), - .FULL_N(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_EMPTY_N)); - - // submodule sq_reqGenSQ_rdmaReqPipeOut_outputQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) sq_reqGenSQ_rdmaReqPipeOut_outputQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_rdmaReqPipeOut_outputQ_D_IN), - .ENQ(sq_reqGenSQ_rdmaReqPipeOut_outputQ_ENQ), - .DEQ(sq_reqGenSQ_rdmaReqPipeOut_outputQ_DEQ), - .CLR(sq_reqGenSQ_rdmaReqPipeOut_outputQ_CLR), - .D_OUT(sq_reqGenSQ_rdmaReqPipeOut_outputQ_D_OUT), - .FULL_N(sq_reqGenSQ_rdmaReqPipeOut_outputQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_rdmaReqPipeOut_outputQ_EMPTY_N)); - - // submodule sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_IN), - .ENQ(sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_ENQ), - .DEQ(sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_DEQ), - .CLR(sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_CLR), - .D_OUT(sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_OUT), - .FULL_N(sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_EMPTY_N)); - - // submodule sq_reqGenSQ_reqCountQ - FIFO2 #(.width(32'd684), .guarded(1'd1)) sq_reqGenSQ_reqCountQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_reqCountQ_D_IN), - .ENQ(sq_reqGenSQ_reqCountQ_ENQ), - .DEQ(sq_reqGenSQ_reqCountQ_DEQ), - .CLR(sq_reqGenSQ_reqCountQ_CLR), - .D_OUT(sq_reqGenSQ_reqCountQ_D_OUT), - .FULL_N(sq_reqGenSQ_reqCountQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_reqCountQ_EMPTY_N)); - - // submodule sq_reqGenSQ_reqHeaderGenQ - FIFO2 #(.width(32'd1300), - .guarded(1'd1)) sq_reqGenSQ_reqHeaderGenQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_reqHeaderGenQ_D_IN), - .ENQ(sq_reqGenSQ_reqHeaderGenQ_ENQ), - .DEQ(sq_reqGenSQ_reqHeaderGenQ_DEQ), - .CLR(sq_reqGenSQ_reqHeaderGenQ_CLR), - .D_OUT(sq_reqGenSQ_reqHeaderGenQ_D_OUT), - .FULL_N(sq_reqGenSQ_reqHeaderGenQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_reqHeaderGenQ_EMPTY_N)); - - // submodule sq_reqGenSQ_reqHeaderOutQ - FIFO2 #(.width(32'd593), - .guarded(1'd1)) sq_reqGenSQ_reqHeaderOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_reqHeaderOutQ_D_IN), - .ENQ(sq_reqGenSQ_reqHeaderOutQ_ENQ), - .DEQ(sq_reqGenSQ_reqHeaderOutQ_DEQ), - .CLR(sq_reqGenSQ_reqHeaderOutQ_CLR), - .D_OUT(sq_reqGenSQ_reqHeaderOutQ_D_OUT), - .FULL_N(sq_reqGenSQ_reqHeaderOutQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_reqHeaderOutQ_EMPTY_N)); - - // submodule sq_reqGenSQ_reqHeaderPrepareQ - FIFO2 #(.width(32'd710), - .guarded(1'd1)) sq_reqGenSQ_reqHeaderPrepareQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_reqHeaderPrepareQ_D_IN), - .ENQ(sq_reqGenSQ_reqHeaderPrepareQ_ENQ), - .DEQ(sq_reqGenSQ_reqHeaderPrepareQ_DEQ), - .CLR(sq_reqGenSQ_reqHeaderPrepareQ_CLR), - .D_OUT(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT), - .FULL_N(sq_reqGenSQ_reqHeaderPrepareQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_reqHeaderPrepareQ_EMPTY_N)); - - // submodule sq_reqGenSQ_workCompGenReqOutQ - FIFO2 #(.width(32'd633), - .guarded(1'd1)) sq_reqGenSQ_workCompGenReqOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_workCompGenReqOutQ_D_IN), - .ENQ(sq_reqGenSQ_workCompGenReqOutQ_ENQ), - .DEQ(sq_reqGenSQ_workCompGenReqOutQ_DEQ), - .CLR(sq_reqGenSQ_workCompGenReqOutQ_CLR), - .D_OUT(sq_reqGenSQ_workCompGenReqOutQ_D_OUT), - .FULL_N(sq_reqGenSQ_workCompGenReqOutQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N)); - - // submodule sq_reqGenSQ_workReqCheckQ - FIFO2 #(.width(32'd684), - .guarded(1'd1)) sq_reqGenSQ_workReqCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_workReqCheckQ_D_IN), - .ENQ(sq_reqGenSQ_workReqCheckQ_ENQ), - .DEQ(sq_reqGenSQ_workReqCheckQ_DEQ), - .CLR(sq_reqGenSQ_workReqCheckQ_CLR), - .D_OUT(sq_reqGenSQ_workReqCheckQ_D_OUT), - .FULL_N(sq_reqGenSQ_workReqCheckQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_workReqCheckQ_EMPTY_N)); - - // submodule sq_reqGenSQ_workReqOutQ - FIFO2 #(.width(32'd684), - .guarded(1'd1)) sq_reqGenSQ_workReqOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_workReqOutQ_D_IN), - .ENQ(sq_reqGenSQ_workReqOutQ_ENQ), - .DEQ(sq_reqGenSQ_workReqOutQ_DEQ), - .CLR(sq_reqGenSQ_workReqOutQ_CLR), - .D_OUT(sq_reqGenSQ_workReqOutQ_D_OUT), - .FULL_N(sq_reqGenSQ_workReqOutQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_workReqOutQ_EMPTY_N)); - - // submodule sq_reqGenSQ_workReqPayloadGenQ - FIFO2 #(.width(32'd720), - .guarded(1'd1)) sq_reqGenSQ_workReqPayloadGenQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_workReqPayloadGenQ_D_IN), - .ENQ(sq_reqGenSQ_workReqPayloadGenQ_ENQ), - .DEQ(sq_reqGenSQ_workReqPayloadGenQ_DEQ), - .CLR(sq_reqGenSQ_workReqPayloadGenQ_CLR), - .D_OUT(sq_reqGenSQ_workReqPayloadGenQ_D_OUT), - .FULL_N(sq_reqGenSQ_workReqPayloadGenQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N)); - - // submodule sq_reqGenSQ_workReqPktNumQ - FIFO2 #(.width(32'd709), - .guarded(1'd1)) sq_reqGenSQ_workReqPktNumQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_workReqPktNumQ_D_IN), - .ENQ(sq_reqGenSQ_workReqPktNumQ_ENQ), - .DEQ(sq_reqGenSQ_workReqPktNumQ_DEQ), - .CLR(sq_reqGenSQ_workReqPktNumQ_CLR), - .D_OUT(sq_reqGenSQ_workReqPktNumQ_D_OUT), - .FULL_N(sq_reqGenSQ_workReqPktNumQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_workReqPktNumQ_EMPTY_N)); - - // submodule sq_reqGenSQ_workReqPsnQ - FIFO2 #(.width(32'd684), - .guarded(1'd1)) sq_reqGenSQ_workReqPsnQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_reqGenSQ_workReqPsnQ_D_IN), - .ENQ(sq_reqGenSQ_workReqPsnQ_ENQ), - .DEQ(sq_reqGenSQ_workReqPsnQ_DEQ), - .CLR(sq_reqGenSQ_workReqPsnQ_CLR), - .D_OUT(sq_reqGenSQ_workReqPsnQ_D_OUT), - .FULL_N(sq_reqGenSQ_workReqPsnQ_FULL_N), - .EMPTY_N(sq_reqGenSQ_workReqPsnQ_EMPTY_N)); - - // submodule sq_respHandleSQ_incomingRespQ - FIFO2 #(.width(32'd1470), - .guarded(1'd1)) sq_respHandleSQ_incomingRespQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_incomingRespQ_D_IN), - .ENQ(sq_respHandleSQ_incomingRespQ_ENQ), - .DEQ(sq_respHandleSQ_incomingRespQ_DEQ), - .CLR(sq_respHandleSQ_incomingRespQ_CLR), - .D_OUT(sq_respHandleSQ_incomingRespQ_D_OUT), - .FULL_N(sq_respHandleSQ_incomingRespQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_incomingRespQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingAddrCalcQ - FIFO2 #(.width(32'd1475), - .guarded(1'd1)) sq_respHandleSQ_pendingAddrCalcQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingAddrCalcQ_D_IN), - .ENQ(sq_respHandleSQ_pendingAddrCalcQ_ENQ), - .DEQ(sq_respHandleSQ_pendingAddrCalcQ_DEQ), - .CLR(sq_respHandleSQ_pendingAddrCalcQ_CLR), - .D_OUT(sq_respHandleSQ_pendingAddrCalcQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingAddrCalcQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingAddrCalcQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingDmaReqQ - FIFO2 #(.width(32'd1539), - .guarded(1'd1)) sq_respHandleSQ_pendingDmaReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingDmaReqQ_D_IN), - .ENQ(sq_respHandleSQ_pendingDmaReqQ_ENQ), - .DEQ(sq_respHandleSQ_pendingDmaReqQ_DEQ), - .CLR(sq_respHandleSQ_pendingDmaReqQ_CLR), - .D_OUT(sq_respHandleSQ_pendingDmaReqQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingDmaReqQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingDmaReqQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingLenCalcQ - FIFO2 #(.width(32'd1539), - .guarded(1'd1)) sq_respHandleSQ_pendingLenCalcQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingLenCalcQ_D_IN), - .ENQ(sq_respHandleSQ_pendingLenCalcQ_ENQ), - .DEQ(sq_respHandleSQ_pendingLenCalcQ_DEQ), - .CLR(sq_respHandleSQ_pendingLenCalcQ_CLR), - .D_OUT(sq_respHandleSQ_pendingLenCalcQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingLenCalcQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingLenCalcQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingLenCheckQ - FIFO2 #(.width(32'd1573), - .guarded(1'd1)) sq_respHandleSQ_pendingLenCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingLenCheckQ_D_IN), - .ENQ(sq_respHandleSQ_pendingLenCheckQ_ENQ), - .DEQ(sq_respHandleSQ_pendingLenCheckQ_DEQ), - .CLR(sq_respHandleSQ_pendingLenCheckQ_CLR), - .D_OUT(sq_respHandleSQ_pendingLenCheckQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingLenCheckQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingLenCheckQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingPermCheckQ - FIFO2 #(.width(32'd1476), - .guarded(1'd1)) sq_respHandleSQ_pendingPermCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingPermCheckQ_D_IN), - .ENQ(sq_respHandleSQ_pendingPermCheckQ_ENQ), - .DEQ(sq_respHandleSQ_pendingPermCheckQ_DEQ), - .CLR(sq_respHandleSQ_pendingPermCheckQ_CLR), - .D_OUT(sq_respHandleSQ_pendingPermCheckQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingPermCheckQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingPermCheckQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingPermQueryQ - FIFO2 #(.width(32'd1469), - .guarded(1'd1)) sq_respHandleSQ_pendingPermQueryQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingPermQueryQ_D_IN), - .ENQ(sq_respHandleSQ_pendingPermQueryQ_ENQ), - .DEQ(sq_respHandleSQ_pendingPermQueryQ_DEQ), - .CLR(sq_respHandleSQ_pendingPermQueryQ_CLR), - .D_OUT(sq_respHandleSQ_pendingPermQueryQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingPermQueryQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingPermQueryQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingRespQ - FIFO2 #(.width(32'd1473), - .guarded(1'd1)) sq_respHandleSQ_pendingRespQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingRespQ_D_IN), - .ENQ(sq_respHandleSQ_pendingRespQ_ENQ), - .DEQ(sq_respHandleSQ_pendingRespQ_DEQ), - .CLR(sq_respHandleSQ_pendingRespQ_CLR), - .D_OUT(sq_respHandleSQ_pendingRespQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingRespQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingRespQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingRetryCheckQ - FIFO2 #(.width(32'd1470), - .guarded(1'd1)) sq_respHandleSQ_pendingRetryCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingRetryCheckQ_D_IN), - .ENQ(sq_respHandleSQ_pendingRetryCheckQ_ENQ), - .DEQ(sq_respHandleSQ_pendingRetryCheckQ_DEQ), - .CLR(sq_respHandleSQ_pendingRetryCheckQ_CLR), - .D_OUT(sq_respHandleSQ_pendingRetryCheckQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingRetryCheckQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingSpaceCalcQ - FIFO2 #(.width(32'd1605), - .guarded(1'd1)) sq_respHandleSQ_pendingSpaceCalcQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingSpaceCalcQ_D_IN), - .ENQ(sq_respHandleSQ_pendingSpaceCalcQ_ENQ), - .DEQ(sq_respHandleSQ_pendingSpaceCalcQ_DEQ), - .CLR(sq_respHandleSQ_pendingSpaceCalcQ_CLR), - .D_OUT(sq_respHandleSQ_pendingSpaceCalcQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingSpaceCalcQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingSpaceCalcQ_EMPTY_N)); - - // submodule sq_respHandleSQ_pendingWorkCompQ - FIFO2 #(.width(32'd768), - .guarded(1'd1)) sq_respHandleSQ_pendingWorkCompQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_pendingWorkCompQ_D_IN), - .ENQ(sq_respHandleSQ_pendingWorkCompQ_ENQ), - .DEQ(sq_respHandleSQ_pendingWorkCompQ_DEQ), - .CLR(sq_respHandleSQ_pendingWorkCompQ_CLR), - .D_OUT(sq_respHandleSQ_pendingWorkCompQ_D_OUT), - .FULL_N(sq_respHandleSQ_pendingWorkCompQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_pendingWorkCompQ_EMPTY_N)); - - // submodule sq_respHandleSQ_workCompGenReqOutQ - FIFO2 #(.width(32'd633), - .guarded(1'd1)) sq_respHandleSQ_workCompGenReqOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_respHandleSQ_workCompGenReqOutQ_D_IN), - .ENQ(sq_respHandleSQ_workCompGenReqOutQ_ENQ), - .DEQ(sq_respHandleSQ_workCompGenReqOutQ_DEQ), - .CLR(sq_respHandleSQ_workCompGenReqOutQ_CLR), - .D_OUT(sq_respHandleSQ_workCompGenReqOutQ_D_OUT), - .FULL_N(sq_respHandleSQ_workCompGenReqOutQ_FULL_N), - .EMPTY_N(sq_respHandleSQ_workCompGenReqOutQ_EMPTY_N)); - - // submodule sq_retryHandler_prepareRetryRespQ - FIFO2 #(.width(32'd4), - .guarded(1'd1)) sq_retryHandler_prepareRetryRespQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_prepareRetryRespQ_D_IN), - .ENQ(sq_retryHandler_prepareRetryRespQ_ENQ), - .DEQ(sq_retryHandler_prepareRetryRespQ_DEQ), - .CLR(sq_retryHandler_prepareRetryRespQ_CLR), - .D_OUT(sq_retryHandler_prepareRetryRespQ_D_OUT), - .FULL_N(sq_retryHandler_prepareRetryRespQ_FULL_N), - .EMPTY_N(sq_retryHandler_prepareRetryRespQ_EMPTY_N)); - - // submodule sq_retryHandler_resetReqQ - FIFO2 #(.width(32'd1), - .guarded(1'd1)) sq_retryHandler_resetReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_resetReqQ_D_IN), - .ENQ(sq_retryHandler_resetReqQ_ENQ), - .DEQ(sq_retryHandler_resetReqQ_DEQ), - .CLR(sq_retryHandler_resetReqQ_CLR), - .D_OUT(sq_retryHandler_resetReqQ_D_OUT), - .FULL_N(sq_retryHandler_resetReqQ_FULL_N), - .EMPTY_N(sq_retryHandler_resetReqQ_EMPTY_N)); - - // submodule sq_retryHandler_resetRetryCntQ - FIFO2 #(.width(32'd1), - .guarded(1'd1)) sq_retryHandler_resetRetryCntQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_resetRetryCntQ_D_IN), - .ENQ(sq_retryHandler_resetRetryCntQ_ENQ), - .DEQ(sq_retryHandler_resetRetryCntQ_DEQ), - .CLR(sq_retryHandler_resetRetryCntQ_CLR), - .D_OUT(), - .FULL_N(sq_retryHandler_resetRetryCntQ_FULL_N), - .EMPTY_N(sq_retryHandler_resetRetryCntQ_EMPTY_N)); - - // submodule sq_retryHandler_resetTimeOutQ - FIFO2 #(.width(32'd1), - .guarded(1'd1)) sq_retryHandler_resetTimeOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_resetTimeOutQ_D_IN), - .ENQ(sq_retryHandler_resetTimeOutQ_ENQ), - .DEQ(sq_retryHandler_resetTimeOutQ_DEQ), - .CLR(sq_retryHandler_resetTimeOutQ_CLR), - .D_OUT(), - .FULL_N(sq_retryHandler_resetTimeOutQ_FULL_N), - .EMPTY_N(sq_retryHandler_resetTimeOutQ_EMPTY_N)); - - // submodule sq_retryHandler_retryActionQ - FIFO2 #(.width(32'd98), - .guarded(1'd1)) sq_retryHandler_retryActionQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_retryActionQ_D_IN), - .ENQ(sq_retryHandler_retryActionQ_ENQ), - .DEQ(sq_retryHandler_retryActionQ_DEQ), - .CLR(sq_retryHandler_retryActionQ_CLR), - .D_OUT(sq_retryHandler_retryActionQ_D_OUT), - .FULL_N(sq_retryHandler_retryActionQ_FULL_N), - .EMPTY_N(sq_retryHandler_retryActionQ_EMPTY_N)); - - // submodule sq_retryHandler_retryNotificationQ - FIFO2 #(.width(32'd98), - .guarded(1'd1)) sq_retryHandler_retryNotificationQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_retryNotificationQ_D_IN), - .ENQ(sq_retryHandler_retryNotificationQ_ENQ), - .DEQ(sq_retryHandler_retryNotificationQ_DEQ), - .CLR(sq_retryHandler_retryNotificationQ_CLR), - .D_OUT(sq_retryHandler_retryNotificationQ_D_OUT), - .FULL_N(sq_retryHandler_retryNotificationQ_FULL_N), - .EMPTY_N(sq_retryHandler_retryNotificationQ_EMPTY_N)); - - // submodule sq_retryHandler_retryReqQ - FIFO2 #(.width(32'd97), - .guarded(1'd1)) sq_retryHandler_retryReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_retryReqQ_D_IN), - .ENQ(sq_retryHandler_retryReqQ_ENQ), - .DEQ(sq_retryHandler_retryReqQ_DEQ), - .CLR(sq_retryHandler_retryReqQ_CLR), - .D_OUT(sq_retryHandler_retryReqQ_D_OUT), - .FULL_N(sq_retryHandler_retryReqQ_FULL_N), - .EMPTY_N(sq_retryHandler_retryReqQ_EMPTY_N)); - - // submodule sq_retryHandler_retryRespQ - FIFO2 #(.width(32'd1), - .guarded(1'd1)) sq_retryHandler_retryRespQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_retryRespQ_D_IN), - .ENQ(sq_retryHandler_retryRespQ_ENQ), - .DEQ(sq_retryHandler_retryRespQ_DEQ), - .CLR(sq_retryHandler_retryRespQ_CLR), - .D_OUT(sq_retryHandler_retryRespQ_D_OUT), - .FULL_N(sq_retryHandler_retryRespQ_FULL_N), - .EMPTY_N(sq_retryHandler_retryRespQ_EMPTY_N)); - - // submodule sq_retryHandler_timeOutNotificationQ - FIFO2 #(.width(32'd1), - .guarded(1'd1)) sq_retryHandler_timeOutNotificationQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_timeOutNotificationQ_D_IN), - .ENQ(sq_retryHandler_timeOutNotificationQ_ENQ), - .DEQ(sq_retryHandler_timeOutNotificationQ_DEQ), - .CLR(sq_retryHandler_timeOutNotificationQ_CLR), - .D_OUT(sq_retryHandler_timeOutNotificationQ_D_OUT), - .FULL_N(sq_retryHandler_timeOutNotificationQ_FULL_N), - .EMPTY_N(sq_retryHandler_timeOutNotificationQ_EMPTY_N)); - - // submodule sq_retryHandler_timeOutTriggerQ - FIFO2 #(.width(32'd1), - .guarded(1'd1)) sq_retryHandler_timeOutTriggerQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_timeOutTriggerQ_D_IN), - .ENQ(sq_retryHandler_timeOutTriggerQ_ENQ), - .DEQ(sq_retryHandler_timeOutTriggerQ_DEQ), - .CLR(sq_retryHandler_timeOutTriggerQ_CLR), - .D_OUT(), - .FULL_N(sq_retryHandler_timeOutTriggerQ_FULL_N), - .EMPTY_N(sq_retryHandler_timeOutTriggerQ_EMPTY_N)); - - // submodule sq_retryHandler_updateRetryCntQ - FIFO2 #(.width(32'd4), - .guarded(1'd1)) sq_retryHandler_updateRetryCntQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_retryHandler_updateRetryCntQ_D_IN), - .ENQ(sq_retryHandler_updateRetryCntQ_ENQ), - .DEQ(sq_retryHandler_updateRetryCntQ_DEQ), - .CLR(sq_retryHandler_updateRetryCntQ_CLR), - .D_OUT(sq_retryHandler_updateRetryCntQ_D_OUT), - .FULL_N(sq_retryHandler_updateRetryCntQ_FULL_N), - .EMPTY_N(sq_retryHandler_updateRetryCntQ_EMPTY_N)); - - // submodule sq_workCompGenSQ_dmaWaitingQ - FIFO2 #(.width(32'd857), - .guarded(1'd1)) sq_workCompGenSQ_dmaWaitingQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_workCompGenSQ_dmaWaitingQ_D_IN), - .ENQ(sq_workCompGenSQ_dmaWaitingQ_ENQ), - .DEQ(sq_workCompGenSQ_dmaWaitingQ_DEQ), - .CLR(sq_workCompGenSQ_dmaWaitingQ_CLR), - .D_OUT(sq_workCompGenSQ_dmaWaitingQ_D_OUT), - .FULL_N(sq_workCompGenSQ_dmaWaitingQ_FULL_N), - .EMPTY_N(sq_workCompGenSQ_dmaWaitingQ_EMPTY_N)); - - // submodule sq_workCompGenSQ_genWorkCompQ - FIFO2 #(.width(32'd857), - .guarded(1'd1)) sq_workCompGenSQ_genWorkCompQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_workCompGenSQ_genWorkCompQ_D_IN), - .ENQ(sq_workCompGenSQ_genWorkCompQ_ENQ), - .DEQ(sq_workCompGenSQ_genWorkCompQ_DEQ), - .CLR(sq_workCompGenSQ_genWorkCompQ_CLR), - .D_OUT(sq_workCompGenSQ_genWorkCompQ_D_OUT), - .FULL_N(sq_workCompGenSQ_genWorkCompQ_FULL_N), - .EMPTY_N(sq_workCompGenSQ_genWorkCompQ_EMPTY_N)); - - // submodule sq_workCompGenSQ_pendingWorkCompQ4SQ - SizedFIFO #(.p1width(32'd633), - .p2depth(32'd8), - .p3cntr_width(32'd3), - .guarded(1'd1)) sq_workCompGenSQ_pendingWorkCompQ4SQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_workCompGenSQ_pendingWorkCompQ4SQ_D_IN), - .ENQ(sq_workCompGenSQ_pendingWorkCompQ4SQ_ENQ), - .DEQ(sq_workCompGenSQ_pendingWorkCompQ4SQ_DEQ), - .CLR(sq_workCompGenSQ_pendingWorkCompQ4SQ_CLR), - .D_OUT(sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT), - .FULL_N(sq_workCompGenSQ_pendingWorkCompQ4SQ_FULL_N), - .EMPTY_N(sq_workCompGenSQ_pendingWorkCompQ4SQ_EMPTY_N)); - - // submodule sq_workCompGenSQ_workCompOutQ4SQ - SizedFIFO #(.p1width(32'd222), - .p2depth(32'd4), - .p3cntr_width(32'd2), - .guarded(1'd1)) sq_workCompGenSQ_workCompOutQ4SQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sq_workCompGenSQ_workCompOutQ4SQ_D_IN), - .ENQ(sq_workCompGenSQ_workCompOutQ4SQ_ENQ), - .DEQ(sq_workCompGenSQ_workCompOutQ4SQ_DEQ), - .CLR(sq_workCompGenSQ_workCompOutQ4SQ_CLR), - .D_OUT(sq_workCompGenSQ_workCompOutQ4SQ_D_OUT), - .FULL_N(sq_workCompGenSQ_workCompOutQ4SQ_FULL_N), - .EMPTY_N(sq_workCompGenSQ_workCompOutQ4SQ_EMPTY_N)); - - // submodule workReqQ - FIFO2 #(.width(32'd601), .guarded(1'd1)) workReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(workReqQ_D_IN), - .ENQ(workReqQ_ENQ), - .DEQ(workReqQ_DEQ), - .CLR(workReqQ_CLR), - .D_OUT(workReqQ_D_OUT), - .FULL_N(workReqQ_FULL_N), - .EMPTY_N(workReqQ_EMPTY_N)); - - // rule RL_errTrigger - assign CAN_FIRE_RL_errTrigger = - (cntrl_stateReg == 4'd2 || cntrl_stateReg == 4'd3 || - cntrl_stateReg == 4'd4) && - sq_workCompGenSQ_workCompGenStateReg == 2'd2 ; - assign WILL_FIRE_RL_errTrigger = CAN_FIRE_RL_errTrigger ; - - // rule RL_cancelDmaReadSQ - assign CAN_FIRE_RL_cancelDmaReadSQ = - !sqDmaReadCancelReg && cntrl_stateReg == 4'd6 && - (!sq_reqGenSQ_psnReqOutQ_EMPTY_N || - payloadGenerator4SQ_payloadBufQ_rRdPtr_read__7_ETC___d487 || - !payloadGenerator4SQ_bramQ2PipeOut_postBramQ_EMPTY_N) ; - assign WILL_FIRE_RL_cancelDmaReadSQ = CAN_FIRE_RL_cancelDmaReadSQ ; - - // rule RL_waitGracefulStop - assign CAN_FIRE_RL_waitGracefulStop = - cntrl_stateReg == 4'd6 && !cntrl_errFlushDoneReg && - !workReqQ_EMPTY_N && - sq_pendingWorkReqBuf_emptyReg && - rqDmaReadCancelReg && - rqDmaWriteCancelReg && - sqDmaReadCancelReg && - dmaReadCntrl4SQ_gracefulStopReg ; - assign WILL_FIRE_RL_waitGracefulStop = CAN_FIRE_RL_waitGracefulStop ; - - // rule RL_cntrl_resetAndClear - assign CAN_FIRE_RL_cntrl_resetAndClear = cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_cntrl_resetAndClear = cntrl_stateReg == 4'd0 ; - - // rule RL_cntrl_restore - assign CAN_FIRE_RL_cntrl_restore = - cntrl_restoreQ_EMPTY_N && - (cntrl_stateReg == 4'd2 || cntrl_stateReg == 4'd3 || - cntrl_stateReg == 4'd4) ; - assign WILL_FIRE_RL_cntrl_restore = CAN_FIRE_RL_cntrl_restore ; - - // rule RL_cntrl_onINIT - assign CAN_FIRE_RL_cntrl_onINIT = - cntrl_reqQ_EMPTY_N && cntrl_respQ_FULL_N && - cntrl_stateReg == 4'd1 ; - assign WILL_FIRE_RL_cntrl_onINIT = CAN_FIRE_RL_cntrl_onINIT ; - - // rule RL_cntrl_onRTR - assign CAN_FIRE_RL_cntrl_onRTR = - cntrl_reqQ_EMPTY_N && cntrl_respQ_FULL_N && - cntrl_stateReg == 4'd2 ; - assign WILL_FIRE_RL_cntrl_onRTR = CAN_FIRE_RL_cntrl_onRTR ; - - // rule RL_cntrl_onRTS - assign CAN_FIRE_RL_cntrl_onRTS = - cntrl_reqQ_EMPTY_N && cntrl_respQ_FULL_N && - cntrl_stateReg == 4'd3 ; - assign WILL_FIRE_RL_cntrl_onRTS = CAN_FIRE_RL_cntrl_onRTS ; - - // rule RL_cntrl_onSQD - assign CAN_FIRE_RL_cntrl_onSQD = - cntrl_reqQ_EMPTY_N && cntrl_respQ_FULL_N && - cntrl_stateReg == 4'd4 ; - assign WILL_FIRE_RL_cntrl_onSQD = CAN_FIRE_RL_cntrl_onSQD ; - - // rule RL_cntrl_onERR - assign CAN_FIRE_RL_cntrl_onERR = - cntrl_reqQ_EMPTY_N && cntrl_respQ_FULL_N && - cntrl_stateReg == 4'd6 && - cntrl_errFlushDoneReg ; - assign WILL_FIRE_RL_cntrl_onERR = CAN_FIRE_RL_cntrl_onERR ; - - // rule RL_dmaReadCntrl4SQ_resetAndClear - assign CAN_FIRE_RL_dmaReadCntrl4SQ_resetAndClear = cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_dmaReadCntrl4SQ_resetAndClear = cntrl_stateReg == 4'd0 ; - - // rule RL_dmaReadCntrl4SQ_recvReq - assign CAN_FIRE_RL_dmaReadCntrl4SQ_recvReq = - dmaReadCntrl4SQ_reqQ_EMPTY_N && - dmaReadCntrl4SQ_pendingDmaCntrlReqQ_FULL_N && - dmaReadCntrl4SQ_addrChunkSrv_reqQ_FULL_N && - cntrl_stateReg != 4'd0 && - !dmaReadCntrl4SQ_cancelReg_port1__read ; - assign WILL_FIRE_RL_dmaReadCntrl4SQ_recvReq = - CAN_FIRE_RL_dmaReadCntrl4SQ_recvReq ; - - // rule RL_dmaReadCntrl4SQ_issueDmaReq - assign CAN_FIRE_RL_dmaReadCntrl4SQ_issueDmaReq = - dmaReadCntrl4SQ_addrChunkSrv_respQ_EMPTY_N && - dmaReadProxy4SQ_reqQ_FULL_N && - dmaReadCntrl4SQ_pendingDmaCntrlReqQ_EMPTY_N && - dmaReadCntrl4SQ_pendingDmaReadReqQ_FULL_N && - cntrl_stateReg != 4'd0 && - !dmaReadCntrl4SQ_cancelReg_port1__read ; - assign WILL_FIRE_RL_dmaReadCntrl4SQ_issueDmaReq = - CAN_FIRE_RL_dmaReadCntrl4SQ_issueDmaReq ; - - // rule RL_dmaReadCntrl4SQ_setGracefulStop - assign CAN_FIRE_RL_dmaReadCntrl4SQ_setGracefulStop = - dmaReadCntrl4SQ_cancelReg_port1__read && - !dmaReadCntrl4SQ_gracefulStopReg_port1__read && - !dmaReadCntrl4SQ_respQ_EMPTY_N && - !dmaReadCntrl4SQ_pendingDmaReadReqQ_EMPTY_N && - cntrl_stateReg != 4'd0 ; - assign WILL_FIRE_RL_dmaReadCntrl4SQ_setGracefulStop = - CAN_FIRE_RL_dmaReadCntrl4SQ_setGracefulStop ; - - // rule RL_dmaReadCntrl4SQ_recvDmaResp - assign CAN_FIRE_RL_dmaReadCntrl4SQ_recvDmaResp = - dmaReadProxy4SQ_respQ_EMPTY_N && dmaReadCntrl4SQ_respQ_FULL_N && - (!dmaReadProxy4SQ_respQ_D_OUT[1] || - dmaReadCntrl4SQ_pendingDmaReadReqQ_EMPTY_N) && - (!dmaReadProxy4SQ_respQ_D_OUT[0] || - dmaReadCntrl4SQ_pendingDmaReadReqQ_EMPTY_N) && - cntrl_stateReg != 4'd0 ; - assign WILL_FIRE_RL_dmaReadCntrl4SQ_recvDmaResp = - CAN_FIRE_RL_dmaReadCntrl4SQ_recvDmaResp ; - - // rule RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear - assign CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear = - cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear = - cntrl_stateReg == 4'd0 ; - - // rule RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq - assign CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq = - dmaReadCntrl4SQ_addrChunkSrv_reqQ_EMPTY_N && - cntrl_stateReg != 4'd0 && - !dmaReadCntrl4SQ_addrChunkSrv_busyReg ; - assign WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq = - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ; - - // rule RL_dmaReadCntrl4SQ_addrChunkSrv_genResp - assign CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp = - dmaReadCntrl4SQ_addrChunkSrv_respQ_FULL_N && - cntrl_stateReg != 4'd0 && - dmaReadCntrl4SQ_addrChunkSrv_busyReg ; - assign WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp = - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp ; - - // rule RL_payloadGenerator4SQ_recvPayloadGenReq - assign CAN_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq = - payloadGenerator4SQ_payloadGenReqQ_EMPTY_N && - payloadGenerator4SQ_pendingGenReqQ_FULL_N && - dmaReadCntrl4SQ_reqQ_FULL_N && - (cntrl_stateReg == 4'd2 || cntrl_stateReg == 4'd3 || - cntrl_stateReg == 4'd4) && - payloadGenerator4SQ_isNormalStateReg ; - assign WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq = - CAN_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq ; - - // rule RL_payloadGenerator4SQ_lastFragAddPadding - assign CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding = - payloadGenerator4SQ_payloadBufQ_rRdPtr + 10'd256 != - payloadGenerator4SQ_payloadBufQ_rWrPtr && - dmaReadCntrl4SQ_respQ_i_notEmpty__42_AND_NOT_d_ETC___d657 && - (cntrl_stateReg == 4'd2 || cntrl_stateReg == 4'd3 || - cntrl_stateReg == 4'd4 || - cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding = - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding ; - - // rule RL_payloadGenerator4SQ_payloadBufQ_portB_read_data - assign CAN_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portB_read_data = 1'd1 ; - assign WILL_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portB_read_data = 1'd1 ; - - // rule RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut - assign CAN_FIRE_RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut = - !payloadGenerator4SQ_payloadBufQ_rRdPtr_read__7_ETC___d487 && - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_FULL_N ; - assign WILL_FIRE_RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut = - CAN_FIRE_RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut ; - - // rule RL_payloadGenerator4SQ_resetAndClear - assign CAN_FIRE_RL_payloadGenerator4SQ_resetAndClear = - cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_payloadGenerator4SQ_resetAndClear = - cntrl_stateReg == 4'd0 ; - - // rule RL_payloadGenerator4SQ_payloadBufQ_portA - assign CAN_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portA = 1'd1 ; - assign WILL_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portA = 1'd1 ; - - // rule RL_payloadGenerator4SQ_payloadBufQ_portB - assign CAN_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portB = 1'd1 ; - assign WILL_FIRE_RL_payloadGenerator4SQ_payloadBufQ_portB = 1'd1 ; - - // rule RL_sq_resetAndClear - assign CAN_FIRE_RL_sq_resetAndClear = cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_sq_resetAndClear = cntrl_stateReg == 4'd0 ; - - // rule RL_sq_retryHandler_handleNotifiedRetryAndTimeOut - assign CAN_FIRE_RL_sq_retryHandler_handleNotifiedRetryAndTimeOut = - (!sq_retryHandler_timeOutTriggerQ_EMPTY_N && - !sq_retryHandler_retryNotificationQ_EMPTY_N || - sq_retryHandler_retryActionQ_FULL_N) && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 ; - assign WILL_FIRE_RL_sq_retryHandler_handleNotifiedRetryAndTimeOut = - CAN_FIRE_RL_sq_retryHandler_handleNotifiedRetryAndTimeOut ; - - // rule RL_sq_retryHandler_recvRetryReq - assign CAN_FIRE_RL_sq_retryHandler_recvRetryReq = - (!sq_retryHandler_retryReqQ_EMPTY_N && - !sq_retryHandler_resetRetryCntQ_EMPTY_N || - sq_retryHandler_retryNotificationQ_FULL_N) && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 ; - assign WILL_FIRE_RL_sq_retryHandler_recvRetryReq = - CAN_FIRE_RL_sq_retryHandler_recvRetryReq ; - - // rule RL_sq_retryHandler_checkTimeOut - assign CAN_FIRE_RL_sq_retryHandler_checkTimeOut = - IF_sq_retryHandler_resetTimeOutQ_notEmpty__176_ETC___d1197 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 ; - assign WILL_FIRE_RL_sq_retryHandler_checkTimeOut = - CAN_FIRE_RL_sq_retryHandler_checkTimeOut ; - - // rule RL_sq_retryHandler_recvResetReq - assign CAN_FIRE_RL_sq_retryHandler_recvResetReq = - sq_retryHandler_resetReqQ_i_notEmpty__149_AND__ETC___d1155 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 ; - assign WILL_FIRE_RL_sq_retryHandler_recvResetReq = - CAN_FIRE_RL_sq_retryHandler_recvResetReq ; - - // rule RL_sq_retryHandler_sendRetryResp - assign CAN_FIRE_RL_sq_retryHandler_sendRetryResp = - sq_retryHandler_prepareRetryRespQ_i_notEmpty___ETC___d1411 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 ; - assign WILL_FIRE_RL_sq_retryHandler_sendRetryResp = - CAN_FIRE_RL_sq_retryHandler_sendRetryResp ; - - // rule RL_sq_retryHandler_waitRetryFinish - assign CAN_FIRE_RL_sq_retryHandler_waitRetryFinish = - cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - sq_retryHandler_retryCntrlStateReg == 2'd3 && - sq_retryHandler_retryHandleStateReg == 3'd7 ; - assign WILL_FIRE_RL_sq_retryHandler_waitRetryFinish = - CAN_FIRE_RL_sq_retryHandler_waitRetryFinish ; - - // rule RL_sq_retryHandler_stopScanQ - assign CAN_FIRE_RL_sq_retryHandler_stopScanQ = - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - (cntrl_stateReg == 4'd6 || - sq_retryHandler_pauseRetryHandleReg && - sq_retryHandler_retryCntrlStateReg == 2'd1) ; - assign WILL_FIRE_RL_sq_retryHandler_stopScanQ = - CAN_FIRE_RL_sq_retryHandler_stopScanQ ; - - // rule RL_sq_retryHandler_resetAndClear - assign CAN_FIRE_RL_sq_retryHandler_resetAndClear = cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_sq_retryHandler_resetAndClear = cntrl_stateReg == 4'd0 ; - - // rule RL_sq_newPendingWorkReqPiptOut_flushWR - assign CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_flushWR = - workReqQ_EMPTY_N && - sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_FULL_N && - cntrl_stateReg == 4'd6 ; - assign WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_flushWR = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_flushWR ; - - // rule RL_sq_newPendingWorkReqPiptOut_genPendingWR - assign CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_genPendingWR = - workReqQ_EMPTY_N && - sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_FULL_N && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_FULL_N && - cntrl_stateReg == 4'd3 && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg < - y__h42773 ; - assign WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_genPendingWR = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_genPendingWR ; - - // rule RL_sq_newPendingWorkReqPiptOut_checkPendingNewWorkReqCnt - assign CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_checkPendingNewWorkReqCnt = - 1'd1 ; - assign WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_checkPendingNewWorkReqCnt = - 1'd1 ; - - // rule RL_sq_pendingWorkReqPipeOut_outputPipeIn1 - assign CAN_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn1 = - sq_pendingWorkReqPipeOut_pipeMuxOutQ_FULL_N && - sq_pendingWorkReqBuf_scanOutQ_EMPTY_N ; - assign WILL_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn1 = - CAN_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn1 ; - - // rule RL_sq_pendingWorkReqPipeOut_outputPipeIn2 - assign CAN_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn2 = - sq_pendingWorkReqPipeOut_pipeMuxOutQ_FULL_N && - sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_EMPTY_N && - sq_pendingWorkReqBuf_scanStateReg == 2'd0 && - !sq_pendingWorkReqBuf_scanOutQ_EMPTY_N ; - assign WILL_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn2 = - CAN_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn2 ; - - // rule RL_sq_newPendingWorkReqPiptOut_resetAndClear - assign CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_resetAndClear = - cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_resetAndClear = - cntrl_stateReg == 4'd0 ; - - // rule RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_increment - assign CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_increment = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_EMPTY_N && - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read[8] ; - assign WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_increment = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_increment ; - - // rule RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrement - assign CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrement = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_EMPTY_N && - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read[8] ; - assign WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrement = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrement ; - - // rule RL_sq_reqGenSQ_recvWorkReq - assign CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq = - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_EMPTY_N && - (IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d1880 || - sq_reqGenSQ_workReqPayloadGenQ_FULL_N) && - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 || - cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - - // rule RL_sq_reqGenSQ_issuePayloadGenReq - assign CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq = - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N && - sq_reqGenSQ_workReqPktNumQ_FULL_N && - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] || - payloadGenerator4SQ_payloadGenReqQ_FULL_N) && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg ; - assign WILL_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - - // rule RL_sq_reqGenSQ_calcPktNum4NewWorkReq - assign CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq = - sq_reqGenSQ_workReqPktNumQ_EMPTY_N && - sq_reqGenSQ_workReqPsnQ_FULL_N && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg ; - assign WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - - // rule RL_sq_reqGenSQ_checkPendingWorkReq - assign CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq = - sq_reqGenSQ_workReqCheckQ_i_notEmpty__561_AND__ETC___d2573 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg ; - assign WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - - // rule RL_sq_reqGenSQ_outputNewPendingWorkReq - assign CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq = - sq_reqGenSQ_workReqOutQ_EMPTY_N && - (!sq_reqGenSQ_workReqOutQ_D_OUT[4] || - !sq_reqGenSQ_workReqOutQ_D_OUT[2] || - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N) && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg ; - assign WILL_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - - // rule RL_sq_reqGenSQ_countReqPkt - assign CAN_FIRE_RL_sq_reqGenSQ_countReqPkt = - sq_reqGenSQ_reqCountQ_EMPTY_N && - sq_reqGenSQ_reqHeaderPrepareQ_FULL_N && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg ; - assign WILL_FIRE_RL_sq_reqGenSQ_countReqPkt = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - - // rule RL_sq_reqGenSQ_prepareReqHeaderGen - assign CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen = - sq_reqGenSQ_reqHeaderPrepareQ_EMPTY_N && - sq_reqGenSQ_pendingReqHeaderQ_FULL_N && - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2734 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg ; - assign WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - - // rule RL_sq_reqGenSQ_genReqHeader - assign CAN_FIRE_RL_sq_reqGenSQ_genReqHeader = - sq_reqGenSQ_pendingReqHeaderQ_EMPTY_N && - sq_reqGenSQ_reqHeaderGenQ_FULL_N && - (!sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] || - !sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545] || - payloadGenerator4SQ_payloadGenRespQ_EMPTY_N) && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg ; - assign WILL_FIRE_RL_sq_reqGenSQ_genReqHeader = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - - // rule RL_sq_reqGenSQ_errFlushWR - assign CAN_FIRE_RL_sq_reqGenSQ_errFlushWR = - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N && - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[2] || - !sq_reqGenSQ_workReqPayloadGenQ_D_OUT[1] || - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N) && - (cntrl_stateReg == 4'd6 || - cntrl_stateReg == 4'd3 && !sq_reqGenSQ_isNormalStateReg) ; - assign WILL_FIRE_RL_sq_reqGenSQ_errFlushWR = - CAN_FIRE_RL_sq_reqGenSQ_errFlushWR ; - - // rule RL_sq_reqGenSQ_rdmaReqPipeOut_connect - assign CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_connect = - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_EMPTY_N && - sq_reqGenSQ_rdmaReqPipeOut_outputQ_FULL_N && - (!sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_OUT[0] || - sq_reqGenSQ_psnReqOutQ_EMPTY_N) ; - assign WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_connect = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_connect ; - - // rule RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_resetAndClear - assign CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_resetAndClear = - cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_resetAndClear = - cntrl_stateReg == 4'd0 ; - - // rule RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader - assign CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAnd_ETC___d1747 && - cntrl_stateReg != 4'd0 ; - assign WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader ; - - // rule RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_resetAndClear - assign CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_resetAndClear = - cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_resetAndClear = - cntrl_stateReg == 4'd0 ; - - // rule RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData - assign CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_EMPTY_N && - cntrl_stateReg != 4'd0 && - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg == - 2'd0 ; - assign WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData ; - - // rule RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader - assign CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAnd_ETC___d1808 && - cntrl_stateReg != 4'd0 && - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg == - 2'd1 ; - assign WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader ; - - // rule RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData - assign CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData = - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_FULL_N && - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_EMPTY_N && - cntrl_stateReg != 4'd0 && - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg == - 2'd2 ; - assign WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData ; - - // rule RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag - assign CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag = - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_FULL_N && - cntrl_stateReg != 4'd0 && - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg == - 2'd3 ; - assign WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag ; - - // rule RL_sq_pendingWorkReq2Q_mkConnectionGetPut - assign CAN_FIRE_RL_sq_pendingWorkReq2Q_mkConnectionGetPut = - !sq_pendingWorkReqBuf_fullReg && - sq_pendingWorkReqBuf_scanStateReg == 2'd0 && - sq_reqGenSQ_pendingWorkReqOutQ_EMPTY_N ; - assign WILL_FIRE_RL_sq_pendingWorkReq2Q_mkConnectionGetPut = - CAN_FIRE_RL_sq_pendingWorkReq2Q_mkConnectionGetPut ; - - // rule RL_sq_respHandleSQ_preBuildRespInfo - assign CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo = - !sq_pendingWorkReqBuf_emptyReg && - respPktPipe_metaDataQ_EMPTY_N && - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_preSta_ETC___d3624 ; - assign WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - - // rule RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq - assign CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq = - sq_reqGenSQ_workReqPsnQ_EMPTY_N && - sq_reqGenSQ_workReqCheckQ_FULL_N && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg ; - assign WILL_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - - // rule RL_sq_respHandleSQ_preProcRespInfo - assign CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo = - cntrl_stateReg == 4'd3 && !sq_pendingWorkReqBuf_emptyReg && - sq_respHandleSQ_preStageStateReg == 2'd1 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg ; - assign WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - - // rule RL_sq_respHandleSQ_recvRespHeader - assign CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader = - sq_respHandleSQ_incomingRespQ_EMPTY_N && - sq_respHandleSQ_pendingRespQ_FULL_N && - (cntrl_preStateReg != 4'd3 || cntrl_stateReg != 4'd3 || - sq_retryHandler_resetReqQ_FULL_N) && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - - // rule RL_sq_respHandleSQ_handleRespByType - assign CAN_FIRE_RL_sq_respHandleSQ_handleRespByType = - sq_respHandleSQ_pendingRespQ_EMPTY_N && - sq_respHandleSQ_pendingPermQueryQ_FULL_N && - (sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd9 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 || - sq_retryHandler_retryReqQ_FULL_N) && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_handleRespByType = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - - // rule RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp - assign CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp = - sq_respHandleSQ_pendingPermQueryQ_EMPTY_N && - sq_respHandleSQ_pendingRetryCheckQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp = - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp ; - - // rule RL_sq_respHandleSQ_checkRetryErr - assign CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr = - sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N && - sq_respHandleSQ_pendingPermCheckQ_FULL_N && - sq_respHandleSQ_pendingRetryCheckQ_first__949__ETC___d5046 && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - - // rule RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp - assign CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp = - sq_respHandleSQ_pendingPermCheckQ_EMPTY_N && - sq_respHandleSQ_pendingAddrCalcQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp = - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp ; - - // rule RL_sq_respHandleSQ_calcReadRespAddr - assign CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr = - sq_respHandleSQ_pendingAddrCalcQ_EMPTY_N && - sq_respHandleSQ_pendingLenCalcQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_calcReadRespAddr = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - - // rule RL_sq_respHandleSQ_calcReadRespLen - assign CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen = - sq_respHandleSQ_pendingLenCalcQ_EMPTY_N && - sq_respHandleSQ_pendingSpaceCalcQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_calcReadRespLen = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - - // rule RL_sq_respHandleSQ_calcEnoughDmaSpace - assign CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace = - sq_respHandleSQ_pendingSpaceCalcQ_EMPTY_N && - sq_respHandleSQ_pendingLenCheckQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace = - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace ; - - // rule RL_sq_respHandleSQ_checkReadRespLen - assign CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen = - sq_respHandleSQ_pendingLenCheckQ_EMPTY_N && - sq_respHandleSQ_pendingDmaReqQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_checkReadRespLen = - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen ; - - // rule RL_sq_respHandleSQ_issueDmaReq - assign CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq = - sq_respHandleSQ_pendingDmaReqQ_EMPTY_N && - sq_respHandleSQ_pendingWorkCompQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - - // rule RL_sq_respHandleSQ_discardGhostResp - assign CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp = - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N && - cntrl_stateReg_EQ_3_AND_NOT_sq_respHandleSQ_re_ETC___d5647 && - sq_pendingWorkReqBuf_emptyReg ; - assign WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - - // rule RL_sq_respHandleSQ_checkTimeOutErr - assign CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr = - sq_retryHandler_timeOutNotificationQ_EMPTY_N && - cntrl_stateReg_EQ_3_AND_NOT_sq_respHandleSQ_re_ETC___d5647 ; - assign WILL_FIRE_RL_sq_respHandleSQ_checkTimeOutErr = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - - // rule RL_sq_retryHandler_initRetryCntAndTimeOutTimer - assign CAN_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer = - statusSQ_comm_isRTR2RTS ; - assign WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer = - statusSQ_comm_isRTR2RTS ; - - // rule RL_sq_respHandleSQ_errFlushIncomingResp - assign CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp = - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N && - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_recvEr_ETC___d5683 ; - assign WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - - // rule RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload - assign CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload = - (!respPktPipe_metaDataQ_EMPTY_N || - sq_respHandleSQ_incomingRespQ_FULL_N) && - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - - // rule RL_resetAndClear - assign CAN_FIRE_RL_resetAndClear = cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_resetAndClear = cntrl_stateReg == 4'd0 ; - - // rule RL_sq_respHandleSQ_retryFlushDone - assign CAN_FIRE_RL_sq_respHandleSQ_retryFlushDone = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - - // rule RL_sq_retryHandler_initRetry - assign CAN_FIRE_RL_sq_retryHandler_initRetry = - cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - sq_retryHandler_pauseRetryHandleReg && - sq_retryHandler_retryCntrlStateReg == 2'd2 ; - assign WILL_FIRE_RL_sq_retryHandler_initRetry = - CAN_FIRE_RL_sq_retryHandler_initRetry ; - - // rule RL_sq_retryHandler_startPreRetry - assign CAN_FIRE_RL_sq_retryHandler_startPreRetry = - (sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - !sq_retryHandler_pauseRetryHandleReg && - sq_retryHandler_retryHandleStateReg == 3'd1 ; - assign WILL_FIRE_RL_sq_retryHandler_startPreRetry = - CAN_FIRE_RL_sq_retryHandler_startPreRetry ; - - // rule RL_sq_retryHandler_rnrCheck - assign CAN_FIRE_RL_sq_retryHandler_rnrCheck = - cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - !sq_retryHandler_pauseRetryHandleReg && - sq_retryHandler_retryHandleStateReg == 3'd2 ; - assign WILL_FIRE_RL_sq_retryHandler_rnrCheck = - CAN_FIRE_RL_sq_retryHandler_rnrCheck ; - - // rule RL_sq_retryHandler_rnrWait - assign CAN_FIRE_RL_sq_retryHandler_rnrWait = - cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - !sq_retryHandler_pauseRetryHandleReg && - sq_retryHandler_retryHandleStateReg == 3'd3 ; - assign WILL_FIRE_RL_sq_retryHandler_rnrWait = - CAN_FIRE_RL_sq_retryHandler_rnrWait ; - - // rule RL_sq_retryHandler_checkPartialRetry - assign CAN_FIRE_RL_sq_retryHandler_checkPartialRetry = - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - !sq_retryHandler_pauseRetryHandleReg && - sq_retryHandler_retryHandleStateReg == 3'd4 ; - assign WILL_FIRE_RL_sq_retryHandler_checkPartialRetry = - CAN_FIRE_RL_sq_retryHandler_checkPartialRetry ; - - // rule RL_sq_retryHandler_modifyPartialRetryWR - assign CAN_FIRE_RL_sq_retryHandler_modifyPartialRetryWR = - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - !sq_retryHandler_pauseRetryHandleReg && - sq_retryHandler_retryHandleStateReg == 3'd5 ; - assign WILL_FIRE_RL_sq_retryHandler_modifyPartialRetryWR = - CAN_FIRE_RL_sq_retryHandler_modifyPartialRetryWR ; - - // rule RL_sq_retryHandler_startRetry - assign CAN_FIRE_RL_sq_retryHandler_startRetry = - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - !sq_retryHandler_pauseRetryHandleReg && - sq_retryHandler_retryHandleStateReg == 3'd6 ; - assign WILL_FIRE_RL_sq_retryHandler_startRetry = - CAN_FIRE_RL_sq_retryHandler_startRetry ; - - // rule RL_sq_retryHandler_waitRetryDone - assign CAN_FIRE_RL_sq_retryHandler_waitRetryDone = - cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - !sq_retryHandler_pauseRetryHandleReg && - sq_retryHandler_retryHandleStateReg == 3'd7 ; - assign WILL_FIRE_RL_sq_retryHandler_waitRetryDone = - CAN_FIRE_RL_sq_retryHandler_waitRetryDone ; - - // rule RL_sq_retryHandler_handleRetryCntUpdate - assign CAN_FIRE_RL_sq_retryHandler_handleRetryCntUpdate = - sq_retryHandler_updateRetryCntQ_i_notEmpty__30_ETC___d1313 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - !sq_retryHandler_pauseRetryHandleReg ; - assign WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate = - CAN_FIRE_RL_sq_retryHandler_handleRetryCntUpdate ; - - // rule RL_sq_retryHandler_handleRetryAction - assign CAN_FIRE_RL_sq_retryHandler_handleRetryAction = - sq_retryHandler_retryActionQ_EMPTY_N && - sq_retryHandler_updateRetryCntQ_FULL_N && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 ; - assign WILL_FIRE_RL_sq_retryHandler_handleRetryAction = - CAN_FIRE_RL_sq_retryHandler_handleRetryAction ; - - // rule RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq - assign CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq = - !sq_pendingWorkReqBuf_emptyReg && - sq_respHandleSQ_incomingRespQ_FULL_N && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_preSta_ETC___d4329 ; - assign WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - - // rule RL_sq_respHandleSQ_errFlushWorkReq - assign CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq = - !sq_pendingWorkReqBuf_emptyReg && - (sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - sq_respHandleSQ_incomingRespQ_FULL_N && - (cntrl_stateReg == 4'd3 && - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) || - cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - - // rule RL_sq_pendingWorkReqBuf_check - assign CAN_FIRE_RL_sq_pendingWorkReqBuf_check = - CAN_FIRE_RL_sq_pendingWorkReqBuf_canonicalize ; - assign WILL_FIRE_RL_sq_pendingWorkReqBuf_check = - CAN_FIRE_RL_sq_pendingWorkReqBuf_canonicalize ; - - // rule RL_sq_pendingWorkReqBuf_fifoMode - assign CAN_FIRE_RL_sq_pendingWorkReqBuf_fifoMode = - !CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll && - sq_pendingWorkReqBuf_scanStateReg == 2'd0 ; - assign WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode = - CAN_FIRE_RL_sq_pendingWorkReqBuf_fifoMode ; - - // rule RL_sq_pendingWorkReqBuf_preScanMode - assign CAN_FIRE_RL_sq_pendingWorkReqBuf_preScanMode = - !CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll && - sq_pendingWorkReqBuf_scanStateReg == 2'd1 ; - assign WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode = - CAN_FIRE_RL_sq_pendingWorkReqBuf_preScanMode ; - - // rule RL_sq_pendingWorkReqBuf_scanNext - assign CAN_FIRE_RL_sq_pendingWorkReqBuf_scanNext = - sq_pendingWorkReqBuf_scanOutQ_FULL_N && - !CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 ; - assign WILL_FIRE_RL_sq_pendingWorkReqBuf_scanNext = - CAN_FIRE_RL_sq_pendingWorkReqBuf_scanNext ; - - // rule RL_sq_pendingWorkReqBuf_scanModeStateChange - assign CAN_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange = - !CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 ; - assign WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange = - CAN_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange ; - - // rule RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt - assign CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_FULL_N && - cntrl_stateReg == 4'd3 && - sq_pendingWorkReqBuf_popReg_port1__read ; - assign WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt ; - - // rule RL_sq_pendingWorkReqBuf_clearAll - always@(cntrl_stateReg or sq_pendingWorkReqBuf_clearReg) - begin - case (cntrl_stateReg) - 4'd0: CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll = 1'd1; - default: CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll = - sq_pendingWorkReqBuf_clearReg; - endcase - end - assign WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll = - CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - - // rule RL_sq_pendingWorkReqBuf_canonicalize - assign CAN_FIRE_RL_sq_pendingWorkReqBuf_canonicalize = - !CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize = - CAN_FIRE_RL_sq_pendingWorkReqBuf_canonicalize ; - - // rule RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_write - assign CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_write = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read[8] ; - assign WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_write = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_write ; - - // rule RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr - assign CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr = - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read[8] ; - assign WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr ; - - // rule RL_sq_workCompGenSQ_start - assign CAN_FIRE_RL_sq_workCompGenSQ_start = - cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd0 ; - assign WILL_FIRE_RL_sq_workCompGenSQ_start = - CAN_FIRE_RL_sq_workCompGenSQ_start ; - - // rule RL_sq_workCompGenSQ_recvWorkCompGenReqSQ - assign CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ = - IF_sq_reqGenSQ_workCompGenReqOutQ_notEmpty__69_ETC___d5707 && - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 || - cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) ; - assign WILL_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - - // rule RL_sq_reqGenSQ_resetAndClear - assign CAN_FIRE_RL_sq_reqGenSQ_resetAndClear = cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_sq_reqGenSQ_resetAndClear = cntrl_stateReg == 4'd0 ; - - // rule RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp - assign CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp = - sq_reqGenSQ_reqHeaderGenQ_EMPTY_N && - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_62_ETC___d3580 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg ; - assign WILL_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - - // rule RL_sq_respHandleSQ_resetAndClear - assign CAN_FIRE_RL_sq_respHandleSQ_resetAndClear = cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_sq_respHandleSQ_resetAndClear = cntrl_stateReg == 4'd0 ; - - // rule RL_sq_respHandleSQ_genWorkCompSQ - assign CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ = - sq_respHandleSQ_pendingWorkCompQ_EMPTY_N && - (!sq_respHandleSQ_pendingWorkCompQ_D_OUT[633] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[31] || - sq_respHandleSQ_workCompGenReqOutQ_FULL_N) && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ = - CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ ; - - // rule RL_sq_respHandleSQ_canonicalize - assign CAN_FIRE_RL_sq_respHandleSQ_canonicalize = - cntrl_stateReg == 4'd3 && - (sq_respHandleSQ_hasInternalErrReg_port1__read || - sq_respHandleSQ_hasTimeOutErrReg_port1__read) ; - assign WILL_FIRE_RL_sq_respHandleSQ_canonicalize = - CAN_FIRE_RL_sq_respHandleSQ_canonicalize ; - - // rule RL_sq_workCompGenSQ_genPendingWorkCompSQ - assign CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ = - sq_workCompGenSQ_pendingWorkCompQ4SQ_EMPTY_N && - sq_workCompGenSQ_dmaWaitingQ_i_notFull__721_AN_ETC___d5767 && - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 || - cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) ; - assign WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - - // rule RL_cntrl_onReset - assign CAN_FIRE_RL_cntrl_onReset = - cntrl_reqQ_EMPTY_N && cntrl_respQ_FULL_N && - cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_cntrl_onReset = CAN_FIRE_RL_cntrl_onReset ; - - // rule RL_cntrl_onCreate - assign CAN_FIRE_RL_cntrl_onCreate = - cntrl_reqQ_EMPTY_N && cntrl_respQ_FULL_N && - cntrl_stateReg == 4'd8 ; - assign WILL_FIRE_RL_cntrl_onCreate = CAN_FIRE_RL_cntrl_onCreate ; - - // rule RL_sq_workCompGenSQ_waitDmaDoneSQ - assign CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ = - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N && - sq_workCompGenSQ_genWorkCompQ_FULL_N && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 ; - assign WILL_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ = - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - - // rule RL_sq_workCompGenSQ_genWorkCompSQ - assign CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ = - sq_workCompGenSQ_genWorkCompQ_EMPTY_N && - IF_sq_workCompGenSQ_genWorkCompQ_first__802_BI_ETC___d5808 && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 ; - assign WILL_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - - // rule RL_cntrl_updatePreState - assign CAN_FIRE_RL_cntrl_updatePreState = 1'd1 ; - assign WILL_FIRE_RL_cntrl_updatePreState = 1'd1 ; - - // rule RL_sq_workCompGenSQ_noDmaWaitSQ - assign CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ = - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N && - sq_workCompGenSQ_genWorkCompQ_FULL_N && - (cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) ; - assign WILL_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ = - CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ ; - - // rule RL_sq_workCompGenSQ_errFlushSQ - assign CAN_FIRE_RL_sq_workCompGenSQ_errFlushSQ = - sq_workCompGenSQ_genWorkCompQ_EMPTY_N && - (sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg || - sq_workCompGenSQ_workCompOutQ4SQ_FULL_N) && - (cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) ; - assign WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ = - CAN_FIRE_RL_sq_workCompGenSQ_errFlushSQ ; - - // rule RL_sq_workCompGenSQ_resetAndClear - assign CAN_FIRE_RL_sq_workCompGenSQ_resetAndClear = cntrl_stateReg == 4'd0 ; - assign WILL_FIRE_RL_sq_workCompGenSQ_resetAndClear = - cntrl_stateReg == 4'd0 ; - - // rule RL_cntrl_canonicalize - assign CAN_FIRE_RL_cntrl_canonicalize = 1'd1 ; - assign WILL_FIRE_RL_cntrl_canonicalize = 1'd1 ; - - // inputs to muxes for submodule ports - assign MUX_cntrl_nextStateReg_port0__write_1__SEL_1 = - WILL_FIRE_RL_cntrl_onReset && cntrl_reqQ_D_OUT[300:299] == 2'd0 ; - assign MUX_cntrl_nextStateReg_port0__write_1__SEL_2 = - WILL_FIRE_RL_cntrl_onCreate && - cntrl_reqQ_D_OUT[300:299] == 2'd2 && - cntrl_reqQ_D_OUT[216:213] == 4'd1 && - { 21'd0, - cntrl_reqQ_D_OUT[221:220], - 2'd0, - cntrl_reqQ_D_OUT[217] } == - 26'd25 ; - assign MUX_cntrl_nextStateReg_port0__write_1__SEL_3 = - WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd2 && - cntrl_reqQ_D_OUT[216:213] == 4'd2 && - { 5'd0, - cntrl_reqQ_D_OUT[237], - 2'd0, - cntrl_reqQ_D_OUT[234], - 1'd0, - cntrl_reqQ_D_OUT[232], - 2'd0, - cntrl_reqQ_D_OUT[229], - 3'd0, - cntrl_reqQ_D_OUT[225], - 7'd0, - cntrl_reqQ_D_OUT[217] } == - 26'd1216769 ; - assign MUX_cntrl_nextStateReg_port0__write_1__SEL_4 = - WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd2 && - (cntrl_reqQ_D_OUT[216:213] == 4'd6 && cntrl_reqQ_D_OUT[217] || - cntrl_reqQ_D_OUT[216:213] == 4'd3 && - { 9'd0, - cntrl_reqQ_D_OUT[233], - 2'd0, - cntrl_reqQ_D_OUT[230], - 1'd0, - cntrl_reqQ_D_OUT[228:226], - 8'd0, - cntrl_reqQ_D_OUT[217] } == - 26'd77313) ; - assign MUX_cntrl_nextStateReg_port0__write_1__SEL_5 = - WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] == 2'd2 && - (cntrl_reqQ_D_OUT[216:213] == 4'd4 || - cntrl_reqQ_D_OUT[216:213] == 4'd6) && - cntrl_reqQ_D_OUT[217] ; - assign MUX_cntrl_nextStateReg_port0__write_1__SEL_6 = - WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] == 2'd2 && - (cntrl_reqQ_D_OUT[216:213] == 4'd6 || - cntrl_reqQ_D_OUT[216:213] == 4'd3) && - cntrl_reqQ_D_OUT[217] ; - assign MUX_cntrl_nextStateReg_port0__write_1__SEL_7 = - WILL_FIRE_RL_cntrl_onERR && - (cntrl_reqQ_D_OUT[300:299] == 2'd1 || - cntrl_reqQ_D_OUT[300:299] == 2'd2 && - cntrl_reqQ_D_OUT[216:213] == 4'd0 && - cntrl_reqQ_D_OUT[217]) ; - assign MUX_cntrl_npsnReg_write_1__SEL_1 = - WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd2 ; - assign MUX_dmaReadCntrl4SQ_addrChunkSrv_isFirstReg_write_1__SEL_1 = - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp || - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear ; - assign MUX_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr && - (sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__read && - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__read || - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__read && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__read) ; - assign MUX_sq_pendingWorkReqBuf_headReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanNext || - WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode ; - assign MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read ; - assign MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_2 = - WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_scanStartReg_port1__read ; - assign MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_3 = - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - (sq_pendingWorkReqBuf_scanStopReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read || - sq_pendingWorkReqBuf_scanDoneReg_port1__read) ; - assign MUX_sq_reqGenSQ_isNormalStateReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp && - (sq_reqGenSQ_reqHeaderGenQ_D_OUT[26] && - sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] || - !sq_reqGenSQ_reqHeaderGenQ_D_OUT[620]) ; - assign MUX_sq_reqGenSQ_pendingWorkReqOutQ_enq_1__SEL_1 = - WILL_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq && - sq_reqGenSQ_workReqOutQ_D_OUT[4] && - sq_reqGenSQ_workReqOutQ_D_OUT[2] ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__SEL_1 = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - (!sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg || - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0]) ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__SEL_2 = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData && - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_OUT[0] ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__SEL_4 = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_resetAndClear ; - assign MUX_sq_respHandleSQ_hasInternalErrReg_port0__write_1__SEL_1 = - WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 ; - assign MUX_sq_respHandleSQ_hasTimeOutErrReg_port0__write_1__SEL_1 = - WILL_FIRE_RL_sq_respHandleSQ_checkTimeOutErr && - sq_retryHandler_timeOutNotificationQ_D_OUT ; - assign MUX_sq_respHandleSQ_incomingRespQ_enq_1__SEL_1 = - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - respPktPipe_metaDataQ_EMPTY_N ; - assign MUX_sq_respHandleSQ_preRdmaOpCodeReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - cntrl_stateReg != 4'd6 ; - assign MUX_sq_respHandleSQ_preStageStateReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear || - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload || - WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign MUX_sq_respHandleSQ_recvRetryRespReg_write_1__SEL_2 = - WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_retryHandler_retryHandleStateReg == 3'd7 ; - assign MUX_sq_retryHandler_disableRetryCntReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - !sq_retryHandler_updateRetryCntQ_D_OUT[3] ; - assign MUX_sq_retryHandler_disableTimeOutReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_retryHandler_checkTimeOut && - sq_retryHandler_resetTimeOutQ_notEmpty__176_OR_ETC___d1209 ; - assign MUX_sq_retryHandler_isRnrWaitCntZeroReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_retryHandler_rnrWait && - !sq_retryHandler_isRnrWaitCntZeroReg ; - assign MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_retryHandler_checkTimeOut && - (sq_retryHandler_resetTimeOutQ_EMPTY_N || - sq_retryHandler_retryCntrlStateReg != 2'd0 || - !sq_retryHandler_disableTimeOutReg && - !sq_pendingWorkReqBuf_emptyReg) ; - assign MUX_sq_retryHandler_pauseRetryHandleReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] ; - assign MUX_sq_retryHandler_retryCntReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - IF_sq_retryHandler_updateRetryCntQ_first__309__ETC___d1340 ; - assign MUX_sq_retryHandler_retryCntrlStateReg_port0__write_1__SEL_1 = - WILL_FIRE_RL_sq_retryHandler_waitRetryFinish && - sq_pendingWorkReqBuf_scanStateReg == 2'd0 ; - assign MUX_sq_retryHandler_retryHandleStateReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_retryHandler_rnrWait && - sq_retryHandler_isRnrWaitCntZeroReg ; - assign MUX_sq_retryHandler_retryHandleStateReg_write_1__SEL_2 = - WILL_FIRE_RL_sq_retryHandler_waitRetryDone && - sq_pendingWorkReqBuf_scanStateReg == 2'd0 ; - assign MUX_sq_retryHandler_rnrCntReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - (sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd1 && - !sq_retryHandler_disableRetryCntReg && - sq_retryHandler_rnrCntReg != 3'd0 || - !sq_retryHandler_updateRetryCntQ_D_OUT[3]) ; - assign MUX_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_write_1__SEL_1 = - WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg ; - assign MUX_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_write_1__SEL_2 = - WILL_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ && - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1] ; - assign MUX_sq_workCompGenSQ_workCompOutQ4SQ_enq_1__SEL_1 = - WILL_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ && - (sq_workCompGenSQ_genWorkCompQ_D_OUT[0] || - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1]) ; - assign MUX_cntrl_nextStateReg_port0__write_1__VAL_2 = - { 1'd1, cntrl_reqQ_D_OUT[216:213] } ; - assign MUX_cntrl_nextStateReg_port0__write_1__VAL_7 = - (cntrl_reqQ_D_OUT[300:299] == 2'd1) ? - 5'd16 : - { 1'd1, cntrl_reqQ_D_OUT[216:213] } ; - assign MUX_cntrl_respQ_enq_1__VAL_1 = - { cntrl_reqQ_D_OUT[300:299] == 2'd0, - cntrl_reqQ_D_OUT[266:243], - cntrl_reqQ_D_OUT[298:267], - cntrl_reqQ_D_OUT[216:0] } ; - assign MUX_cntrl_respQ_enq_1__VAL_2 = - { cntrl_reqQ_D_OUT[300:299] != 2'd2 || - cntrl_reqQ_D_OUT[216:213] == 4'd1 && - { 21'd0, - cntrl_reqQ_D_OUT[221:220], - 2'd0, - cntrl_reqQ_D_OUT[217] } == - 26'd25, - cntrl_reqQ_D_OUT[266:243], - cntrl_reqQ_D_OUT[298:267], - cntrl_reqQ_D_OUT[216:213], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d60, - cntrl_reqQ_D_OUT[208:0] } ; - assign MUX_cntrl_respQ_enq_1__VAL_3 = - { cntrl_reqQ_D_OUT[300:299] != 2'd2 || - cntrl_reqQ_D_OUT[216:213] == 4'd2 && - { 5'd0, - cntrl_reqQ_D_OUT[237], - 2'd0, - cntrl_reqQ_D_OUT[234], - 1'd0, - cntrl_reqQ_D_OUT[232], - 2'd0, - cntrl_reqQ_D_OUT[229], - 3'd0, - cntrl_reqQ_D_OUT[225], - 7'd0, - cntrl_reqQ_D_OUT[217] } == - 26'd1216769, - cntrl_reqQ_D_OUT[266:243], - cntrl_reqQ_D_OUT[298:267], - cntrl_reqQ_D_OUT[216:213], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d60, - cntrl_reqQ_D_OUT[208:102], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d95, - cntrl_reqQ_D_OUT[93:54], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d99, - cntrl_reqQ_D_OUT[37:0] } ; - assign MUX_cntrl_respQ_enq_1__VAL_4 = - { cntrl_reqQ_D_OUT[300:299] != 2'd2 || - cntrl_reqQ_D_OUT[216:213] == 4'd6 && cntrl_reqQ_D_OUT[217] || - cntrl_reqQ_D_OUT[216:213] == 4'd3 && - { 9'd0, - cntrl_reqQ_D_OUT[233], - 2'd0, - cntrl_reqQ_D_OUT[230], - 1'd0, - cntrl_reqQ_D_OUT[228:226], - 8'd0, - cntrl_reqQ_D_OUT[217] } == - 26'd77313, - cntrl_reqQ_D_OUT[266:243], - cntrl_reqQ_D_OUT[298:267], - cntrl_reqQ_D_OUT[216:213], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d60, - cntrl_reqQ_D_OUT[208:102], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d95, - cntrl_reqQ_D_OUT[93:54], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d99, - cntrl_reqQ_D_OUT[37:0] } ; - assign MUX_cntrl_respQ_enq_1__VAL_5 = - { cntrl_reqQ_D_OUT[300:299] != 2'd2 || - (cntrl_reqQ_D_OUT[216:213] == 4'd4 || - cntrl_reqQ_D_OUT[216:213] == 4'd6) && - cntrl_reqQ_D_OUT[217], - cntrl_reqQ_D_OUT[266:243], - cntrl_reqQ_D_OUT[298:267], - cntrl_reqQ_D_OUT[216:213], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d60, - cntrl_reqQ_D_OUT[208:150], - x__h6205, - cntrl_reqQ_D_OUT[125:102], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d95, - cntrl_reqQ_D_OUT[93:54], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d99, - cntrl_reqQ_D_OUT[37], - x__h6243, - cntrl_reqQ_D_OUT[28:16], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d155, - cntrl_reqQ_D_OUT[4:0] } ; - assign MUX_cntrl_respQ_enq_1__VAL_6 = - { cntrl_reqQ_D_OUT[300:299] != 2'd2 || - (cntrl_reqQ_D_OUT[216:213] == 4'd6 || - cntrl_reqQ_D_OUT[216:213] == 4'd3) && - cntrl_reqQ_D_OUT[217], - cntrl_reqQ_D_OUT[266:243], - cntrl_reqQ_D_OUT[298:267], - cntrl_reqQ_D_OUT[216:213], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d60, - cntrl_reqQ_D_OUT[208:150], - x__h6205, - cntrl_reqQ_D_OUT[125:102], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d95, - cntrl_reqQ_D_OUT[93:54], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d99, - cntrl_reqQ_D_OUT[37], - x__h6243, - cntrl_reqQ_D_OUT[28:16], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d155, - cntrl_reqQ_D_OUT[4:0] } ; - assign MUX_cntrl_respQ_enq_1__VAL_7 = - { cntrl_reqQ_D_OUT[300:299] != 2'd2 || - cntrl_reqQ_D_OUT[216:213] == 4'd0 && cntrl_reqQ_D_OUT[217], - cntrl_reqQ_D_OUT[266:243], - cntrl_reqQ_D_OUT[298:267], - cntrl_reqQ_D_OUT[216:213], - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d60, - cntrl_reqQ_D_OUT[208:0] } ; - assign MUX_dmaReadCntrl4SQ_addrChunkSrv_busyReg_write_1__VAL_1 = - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[24:23] != 2'd0 || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[22] || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[21:20] != 2'd0 || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[19] || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[18:17] != 2'd0 || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[16] || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[15:14] != 2'd0 || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[13] || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[12:11] != 2'd0 || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[10] || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[9:8] != 2'd0 || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[7] || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[6:5] != 2'd0 || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[4:3] != 2'd0 || - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[2:1] != 2'd0 ; - always@(dmaReadCntrl4SQ_addrChunkSrv_pmtuReg or - dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg) - begin - case (dmaReadCntrl4SQ_addrChunkSrv_pmtuReg) - 3'd1: - MUX_dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_write_1__VAL_2 = - { dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[63:8] + 56'd1, - dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[7:0] }; - 3'd2: - MUX_dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_write_1__VAL_2 = - { dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[63:9] + 55'd1, - dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[8:0] }; - 3'd3: - MUX_dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_write_1__VAL_2 = - { dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[63:10] + 54'd1, - dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[9:0] }; - 3'd4: - MUX_dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_write_1__VAL_2 = - { dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[63:11] + 53'd1, - dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[10:0] }; - default: MUX_dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_write_1__VAL_2 = - { dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[63:12] + 52'd1, - dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg[11:0] }; - endcase - end - assign MUX_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_write_1__VAL_1 = - tmpPktNum__h9229 + - ((!pmtuResidue__h9230[11] && pmtuResidue__h9230[10:9] == 2'd0 && - !pmtuResidue__h9230[8] && - pmtuResidue__h9230[7:6] == 2'd0 && - !pmtuResidue__h9230[5] && - pmtuResidue__h9230[4:3] == 2'd0 && - !pmtuResidue__h9230[2] && - pmtuResidue__h9230[1:0] == 2'd0) ? - 25'd0 : - 25'd1) ; - assign MUX_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_write_1__VAL_2 = - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg - 25'd1 ; - assign MUX_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_write_1__VAL_1 = - (sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__read && - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__read) ? - x__h41815 : - x__h41903 ; - assign MUX_sq_pendingWorkReqBuf_deqPtrReg_write_1__VAL_1 = - sq_pendingWorkReqBuf_popReg_port1__read ? - sq_pendingWorkReqBuf_deqPtrReg + 2'd1 : - sq_pendingWorkReqBuf_deqPtrReg ; - assign MUX_sq_pendingWorkReqBuf_emptyReg_write_1__VAL_1 = - (!sq_pendingWorkReqBuf_pushReg_port1__read[679] && - sq_pendingWorkReqBuf_popReg_port1__read) ? - sq_pendingWorkReqBuf_itemCnt_Q_OUT[2:1] == 2'd0 && - sq_pendingWorkReqBuf_itemCnt_Q_OUT[0] : - (!sq_pendingWorkReqBuf_pushReg_port1__read[679] || - sq_pendingWorkReqBuf_popReg_port1__read) && - sq_pendingWorkReqBuf_emptyReg ; - assign MUX_sq_pendingWorkReqBuf_enqPtrReg_write_1__VAL_1 = - sq_pendingWorkReqBuf_pushReg_port1__read[679] ? - sq_pendingWorkReqBuf_enqPtrReg + 2'd1 : - sq_pendingWorkReqBuf_enqPtrReg ; - assign MUX_sq_pendingWorkReqBuf_fullReg_write_1__VAL_1 = - (sq_pendingWorkReqBuf_pushReg_port1__read[679] || - !sq_pendingWorkReqBuf_popReg_port1__read) && - IF_sq_pendingWorkReqBuf_pushReg_port1__read__7_ETC___d702 ; - assign MUX_sq_pendingWorkReqBuf_headReg_write_1__VAL_2 = - { 1'd1, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521, - enumBits__h93928, - x__h39125, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561, - x__h39399, - x__h39664, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1620, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1621, - value__h99740, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1624, - value__h99767, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1626, - value__h99797, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1629, - value__h99824, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1631, - value__h99854, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1634, - value__h99881, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1636, - value__h99908, - NOT_sq_retryHandler_retryReasonReg_431_EQ_4_46_ETC___d1656 } ; - assign MUX_sq_pendingWorkReqBuf_scanAlmostDoneReg_write_1__VAL_1 = - sq_pendingWorkReqBuf_itemCnt_Q_OUT[2:1] == 2'd0 && - sq_pendingWorkReqBuf_itemCnt_Q_OUT[0] ; - assign MUX_sq_pendingWorkReqBuf_scanAlmostDoneReg_write_1__VAL_2 = - !sq_pendingWorkReqBuf_scanCnt_Q_OUT[2] && - sq_pendingWorkReqBuf_scanCnt_Q_OUT[1] && - !sq_pendingWorkReqBuf_scanCnt_Q_OUT[0] ; - assign MUX_sq_pendingWorkReqBuf_scanPtrReg_write_1__VAL_2 = - sq_pendingWorkReqBuf_scanPtrReg + 2'd1 ; - assign MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__VAL_3 = - sq_pendingWorkReqBuf_scanStopReg_port1__read ? - 2'd0 : - (sq_pendingWorkReqBuf_preScanRestartReg_port1__read ? - 2'd1 : - 2'd0) ; - assign MUX_sq_reqGenSQ_isFirstOrOnlyReqPktReg_write_1__VAL_1 = - sq_reqGenSQ_reqCountQ_D_OUT[5] || - !sq_reqGenSQ_isFirstOrOnlyReqPktReg && - sq_reqGenSQ_remainingPktNumReg == 25'd0 ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg_write_1__VAL_1 = - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1734 && - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1737 != - 2'd1 ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__VAL_2 = - { tmpData__h49087[255:0], - tmpByteEn__h49088[31:0], - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg, - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_OUT[0] && - bits__h49179 == 2'd0 } ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__VAL_3 = - { leftShiftData__h49541, leftShiftByteEn__h49542, 2'd1 } ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__VAL_1 = - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg - - 2'd1 ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__VAL_2 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] ? - 2'd0 : - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[9:8] - - 2'd1 ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_write_1__VAL_1 = - { rightShiftHeaderLastFragData__h48757, - rightShiftHeaderLastFragByteEn__h48758, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[1], - !sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg } ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_1 = - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg ? - 2'd2 : - 2'd0 ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_2 = - (bits__h49179 == 2'd0) ? bits__h49179 : 2'd3 ; - assign MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_3 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] ? - 2'd2 : - 2'd1 ; - assign MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_1 = - { 679'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - respPktPipe_metaDataQ_D_OUT, - respPktPipe_metaDataQ_D_OUT[626:618], - 1'd0, - respPktPipe_metaDataQ_D_OUT[616:615], - 4'd0, - respPktPipe_metaDataQ_D_OUT[610:595], - 8'd0, - respPktPipe_metaDataQ_D_OUT[586:562], - 7'd0, - respPktPipe_metaDataQ_D_OUT[554:531], - 1'd0, - respPktPipe_metaDataQ_D_OUT[529:499], - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd0 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd6 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd13 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd4 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd5 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd23 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd10 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd11 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd12 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd19 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd20 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd16 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd17 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd18, - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd2 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd3 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd22 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd8 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd9 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd15 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd4 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd5 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd23 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd10 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd11 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd12 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd19 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd20 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd16 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd17 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd18, - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd13 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd14 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd15 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd16, - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd18, - 10'd299 } ; - assign MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_3 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521, - enumBits__h93928, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1620, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1621, - value__h99740, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1624, - value__h99767, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1626, - value__h99797, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1629, - value__h99824, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1631, - value__h99854, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1634, - value__h99881, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1636, - value__h99908, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474, - value__h99939, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492, - value__h99966, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1653, - sq_respHandleSQ_preStagePktMetaDataReg, - sq_respHandleSQ_preStageReqPktInfoReg[134:126], - 1'd0, - sq_respHandleSQ_preStageReqPktInfoReg[124:123], - 4'd0, - sq_respHandleSQ_preStageReqPktInfoReg[118:103], - 8'd0, - sq_respHandleSQ_preStageReqPktInfoReg[94:70], - 7'd0, - sq_respHandleSQ_preStageReqPktInfoReg[62:39], - 1'd0, - sq_respHandleSQ_preStageReqPktInfoReg[37:0], - sq_respHandleSQ_retryResetReqReg, - sq_respHandleSQ_preStageWorkCompReqTypeReg, - sq_respHandleSQ_preStageWorkReqAckTypeReg } ; - assign MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_4 = - { 679'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - respPktPipe_metaDataQ_D_OUT, - respPktPipe_metaDataQ_D_OUT[626:618], - 1'd0, - respPktPipe_metaDataQ_D_OUT[616:615], - 4'd0, - respPktPipe_metaDataQ_D_OUT[610:595], - 8'd0, - respPktPipe_metaDataQ_D_OUT[586:562], - 7'd0, - respPktPipe_metaDataQ_D_OUT[554:531], - 46'h0AAAAAAAB129 } ; - assign MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_5 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521, - enumBits__h93928, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1620, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1621, - value__h99740, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1624, - value__h99767, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1626, - value__h99797, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1629, - value__h99824, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1631, - value__h99854, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1634, - value__h99881, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1636, - value__h99908, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474, - value__h99939, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492, - value__h99966, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1653, - 787'h000002AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA12882AAA802AAAAA802AAAAA8AAAAAAAB38, - sq_respHandleSQ_hasTimeOutErrReg ? 4'd13 : 4'd12 } ; - assign MUX_sq_retryHandler_isRnrWaitCntZeroReg_write_1__VAL_1 = - sq_retryHandler_rnrWaitCntReg[26:1] == 26'd0 && - sq_retryHandler_rnrWaitCntReg[0] ; - assign MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__VAL_1 = - !sq_retryHandler_resetTimeOutQ_EMPTY_N && - sq_retryHandler_retryCntrlStateReg == 2'd0 && - (!sq_retryHandler_isTimeOutCntHighPartZeroReg || - !sq_retryHandler_isTimeOutCntLowPartZeroReg) && - sq_retryHandler_timeOutCntReg[41:21] == 21'd0 ; - assign MUX_sq_retryHandler_isTimeOutCntLowPartZeroReg_write_1__VAL_1 = - !sq_retryHandler_resetTimeOutQ_EMPTY_N && - sq_retryHandler_retryCntrlStateReg == 2'd0 && - (!sq_retryHandler_isTimeOutCntHighPartZeroReg || - !sq_retryHandler_isTimeOutCntLowPartZeroReg) && - sq_retryHandler_timeOutCntReg[20:0] == 21'd0 ; - assign MUX_sq_retryHandler_retryCntReg_write_1__VAL_1 = - sq_retryHandler_updateRetryCntQ_D_OUT[3] ? - x__h35617 : - cntrl_maxRetryCntReg ; - assign MUX_sq_retryHandler_retryHandleStateReg_write_1__VAL_3 = - (sq_retryHandler_retryReasonReg == 3'd1) ? 3'd2 : 3'd4 ; - assign MUX_sq_retryHandler_rnrCntReg_write_1__VAL_1 = - sq_retryHandler_updateRetryCntQ_D_OUT[3] ? - x__h35647 : - cntrl_maxRnrCntReg ; - assign MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_1 = - sq_retryHandler_rnrWaitCntReg - 27'd1 ; - always@(rnrTimer__h36783) - begin - case (rnrTimer__h36783) - 5'd0: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd109226667; - 5'd1: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd1667; - 5'd2: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd3334; - 5'd3: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd5000; - 5'd4: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd6667; - 5'd5: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd10000; - 5'd6: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd13334; - 5'd7: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd20000; - 5'd8: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd26667; - 5'd9: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd40000; - 5'd10: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd53334; - 5'd11: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd80000; - 5'd12: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd106667; - 5'd13: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd160000; - 5'd14: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd213334; - 5'd15: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd320000; - 5'd16: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd426667; - 5'd17: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd640000; - 5'd18: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd853334; - 5'd19: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd1280000; - 5'd20: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd1706667; - 5'd21: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd2560000; - 5'd22: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd3413334; - 5'd23: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd5120000; - 5'd24: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd6826667; - 5'd25: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd10240000; - 5'd26: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd13653334; - 5'd27: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd20480000; - 5'd28: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd27306667; - 5'd29: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd40960000; - 5'd30: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd54613334; - 5'd31: MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 = 27'd81920000; - endcase - end - assign MUX_sq_retryHandler_timeOutCntReg_write_1__VAL_1 = - (sq_retryHandler_resetTimeOutQ_EMPTY_N || - sq_retryHandler_retryCntrlStateReg != 2'd0 || - sq_retryHandler_isTimeOutCntHighPartZeroReg && - sq_retryHandler_isTimeOutCntLowPartZeroReg) ? - x__h32835 : - x__h33715 ; - assign MUX_sq_workCompGenSQ_workCompOutQ4SQ_enq_1__VAL_2 = - { sq_workCompGenSQ_genWorkCompQ_D_OUT[223:152], - 12'd5, - sq_workCompGenSQ_genWorkCompQ_D_OUT[139:2] } ; - - // inlined wires - assign payloadGenerator4SQ_payloadBufQ_wDataIn_wget = - { dmaReadCntrl4SQ_respQ_D_OUT[291:36], - dmaReadCntrl4SQ_respQ_D_OUT[0] ? - y_avValue_byteEn__h17055 : - dmaReadCntrl4SQ_respQ_D_OUT[35:4], - dmaReadCntrl4SQ_respQ_D_OUT[3:2] } ; - assign payloadGenerator4SQ_payloadBufQ_wDataIn_whas = - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding ; - assign payloadGenerator4SQ_payloadBufQ_wDataOut_wget = - (payloadGenerator4SQ_payloadBufQ_rCache[300] && - payloadGenerator4SQ_payloadBufQ_rCache[299:290] == - payloadGenerator4SQ_payloadBufQ_rRdPtr) ? - payloadGenerator4SQ_payloadBufQ_rCache[289:0] : - payloadGenerator4SQ_payloadBufQ_memory_DOB ; - assign payloadGenerator4SQ_payloadBufQ_wDataOut_whas = 1'd1 ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_EMPTY_N && - (IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d1880 || - sq_reqGenSQ_workReqPayloadGenQ_FULL_N) ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_stateReg_wget = 1'b1 ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_sqTypeReg_wget = 1'b1 ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_sqTypeReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_sqpnReg_wget = 1'b1 ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_sqpnReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_pmtuReg_wget = - IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d2074 ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_cntrl_pmtuReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_wget = - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606] && - cntrl_stateReg == 4'd3 ; - assign _read_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _first_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _deq_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_wget = - IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d2074 ; - assign _deq_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _i_notEmpty_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_wget = - (IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d1880 || - sq_reqGenSQ_workReqPayloadGenQ_FULL_N) && - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 || - cntrl_stateReg == 4'd6) ; - assign _i_notEmpty_RL_sq_reqGenSQ_recvWorkReq_EN_sq_pendingWorkReqPipeOut_pipeMuxOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _enq_RL_sq_reqGenSQ_recvWorkReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget = - IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d2074 ; - assign _enq_RL_sq_reqGenSQ_recvWorkReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _i_notFull_RL_sq_reqGenSQ_recvWorkReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget = - !IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d1880 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_EMPTY_N && - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 || - cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_reqGenSQ_recvWorkReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvWorkReq ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] || - payloadGenerator4SQ_payloadGenReqQ_FULL_N) && - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPktNumQ_FULL_N ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] || - payloadGenerator4SQ_payloadGenReqQ_FULL_N) && - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPktNumQ_FULL_N ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_sqpnReg_wget = - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_sqpnReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_pmtuReg_wget = - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_cntrl_pmtuReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _enq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_payloadGenerator4SQ_payloadGenReqQ_wget = - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] ; - assign _enq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_payloadGenerator4SQ_payloadGenReqQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _i_notFull_RL_sq_reqGenSQ_issuePayloadGenReq_EN_payloadGenerator4SQ_payloadGenReqQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] && - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPktNumQ_FULL_N ; - assign _i_notFull_RL_sq_reqGenSQ_issuePayloadGenReq_EN_payloadGenerator4SQ_payloadGenReqQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _first_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _deq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget = - 1'd1 ; - assign _deq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _i_notEmpty_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] || - payloadGenerator4SQ_payloadGenReqQ_FULL_N) && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPktNumQ_FULL_N ; - assign _i_notEmpty_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPayloadGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _enq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPktNumQ_wget = - 1'd1 ; - assign _enq_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPktNumQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _i_notFull_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPktNumQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] || - payloadGenerator4SQ_payloadGenReqQ_FULL_N) && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N ; - assign _i_notFull_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_workReqPktNumQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] || - payloadGenerator4SQ_payloadGenReqQ_FULL_N) && - sq_reqGenSQ_workReqPktNumQ_FULL_N && - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_issuePayloadGenReq_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && sq_reqGenSQ_workReqPsnQ_FULL_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPktNumQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && sq_reqGenSQ_workReqPsnQ_FULL_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPktNumQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign _first_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign _deq_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_wget = - 1'd1 ; - assign _deq_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign _i_notEmpty_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPsnQ_FULL_N ; - assign _i_notEmpty_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPktNumQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign _enq_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget = - 1'd1 ; - assign _enq_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign _i_notFull_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPktNumQ_EMPTY_N ; - assign _i_notFull_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_workReqPktNumQ_EMPTY_N && - sq_reqGenSQ_workReqPsnQ_FULL_N ; - assign _read_RL_sq_reqGenSQ_calcPktNum4NewWorkReq_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && sq_reqGenSQ_workReqCheckQ_FULL_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPsnQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && sq_reqGenSQ_workReqCheckQ_FULL_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPsnQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_npsnReg_wget = - sq_reqGenSQ_workReqPsnQ_D_OUT[4] ; - assign _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_npsnReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _write_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_npsnReg_wget = - sq_reqGenSQ_workReqPsnQ_D_OUT[4] ; - assign _write_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_cntrl_npsnReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _first_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _deq_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget = - 1'd1 ; - assign _deq_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _i_notEmpty_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqCheckQ_FULL_N ; - assign _i_notEmpty_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqPsnQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _enq_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget = - 1'd1 ; - assign _enq_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _i_notFull_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqPsnQ_EMPTY_N ; - assign _i_notFull_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_workReqPsnQ_EMPTY_N && - sq_reqGenSQ_workReqCheckQ_FULL_N ; - assign _read_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - (sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] || - sq_reqGenSQ_reqCountQ_FULL_N) && - sq_reqGenSQ_workReqCheckQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqOutQ_FULL_N ; - assign _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && - (sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] || - sq_reqGenSQ_reqCountQ_FULL_N) && - sq_reqGenSQ_workReqCheckQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqOutQ_FULL_N ; - assign _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_sqTypeReg_wget = - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] ; - assign _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_cntrl_sqTypeReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _enq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget = - 1'd1 ; - assign _enq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _i_notFull_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] || - sq_reqGenSQ_reqCountQ_FULL_N) && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqCheckQ_EMPTY_N ; - assign _i_notFull_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _first_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _deq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget = - 1'd1 ; - assign _deq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _i_notEmpty_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] || - sq_reqGenSQ_reqCountQ_FULL_N) && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqOutQ_FULL_N ; - assign _i_notEmpty_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_workReqCheckQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _enq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_reqCountQ_wget = - !sq_reqGenSQ_workReqCheckQ_D_OUT[1] || - sq_reqGenSQ_workReqCheckQ_D_OUT[5] ; - assign _enq_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_reqCountQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _i_notFull_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_reqCountQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_workReqCheckQ_D_OUT[1] || - sq_reqGenSQ_workReqCheckQ_D_OUT[5]) && - sq_reqGenSQ_workReqCheckQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqOutQ_FULL_N ; - assign _i_notFull_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_reqCountQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] || - sq_reqGenSQ_reqCountQ_FULL_N) && - sq_reqGenSQ_workReqOutQ_FULL_N && - sq_reqGenSQ_workReqCheckQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_checkPendingWorkReq_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - (!sq_reqGenSQ_workReqOutQ_D_OUT[4] || - !sq_reqGenSQ_workReqOutQ_D_OUT[2] || - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N) && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqOutQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - assign _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_workReqOutQ_D_OUT[4] || - !sq_reqGenSQ_workReqOutQ_D_OUT[2] || - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N) && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqOutQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - assign _enq_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_pendingWorkReqOutQ_wget = - sq_reqGenSQ_workReqOutQ_D_OUT[4] && - sq_reqGenSQ_workReqOutQ_D_OUT[2] ; - assign _enq_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_pendingWorkReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - assign _i_notFull_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_pendingWorkReqOutQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_workReqOutQ_D_OUT[4] && - sq_reqGenSQ_workReqOutQ_D_OUT[2] && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_workReqOutQ_EMPTY_N ; - assign _i_notFull_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_pendingWorkReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - assign _first_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - assign _deq_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget = - 1'd1 ; - assign _deq_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - assign _i_notEmpty_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg && - (!sq_reqGenSQ_workReqOutQ_D_OUT[4] || - !sq_reqGenSQ_workReqOutQ_D_OUT[2] || - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N) ; - assign _i_notEmpty_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_workReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - assign _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_workReqOutQ_EMPTY_N && - (!sq_reqGenSQ_workReqOutQ_D_OUT[4] || - !sq_reqGenSQ_workReqOutQ_D_OUT[2] || - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N) ; - assign _read_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && sq_reqGenSQ_reqHeaderPrepareQ_FULL_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqCountQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_reqHeaderPrepareQ_FULL_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqCountQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_sqTypeReg_wget = - !sq_reqGenSQ_reqCountQ_D_OUT[5] ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_cntrl_sqTypeReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _first_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _deq_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_wget = - MUX_sq_reqGenSQ_isFirstOrOnlyReqPktReg_write_1__VAL_1 ; - assign _deq_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _i_notEmpty_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqHeaderPrepareQ_FULL_N ; - assign _i_notEmpty_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqCountQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _enq_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget = - 1'd1 ; - assign _enq_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _i_notFull_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqCountQ_EMPTY_N ; - assign _i_notFull_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_remainingPktNumReg_wget = - !sq_reqGenSQ_isFirstOrOnlyReqPktReg ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_remainingPktNumReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_remainingPktNumReg_wget = - 1'd1 ; - assign _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_remainingPktNumReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_curPsnReg_wget = - !sq_reqGenSQ_isFirstOrOnlyReqPktReg ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_curPsnReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_curPsnReg_wget = - 1'd1 ; - assign _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_curPsnReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_reqCountQ_EMPTY_N && - sq_reqGenSQ_reqHeaderPrepareQ_FULL_N ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isFirstOrOnlyReqPktReg_wget = - 1'b1 ; - assign _read_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isFirstOrOnlyReqPktReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isFirstOrOnlyReqPktReg_wget = - 1'd1 ; - assign _write_RL_sq_reqGenSQ_countReqPkt_EN_sq_reqGenSQ_isFirstOrOnlyReqPktReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2734 && - sq_reqGenSQ_reqHeaderPrepareQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_pendingReqHeaderQ_FULL_N ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_stateReg_wget = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd1 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd0 && - !IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2724 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - cntrl_sqTypeReg == 4'd4 && - sq_reqGenSQ_pendingReqHeaderQ_FULL_N && - sq_reqGenSQ_reqHeaderPrepareQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqTypeReg_wget = - 1'b1 ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqTypeReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqSigAllReg_wget = - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] || - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd4 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd5 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd6 ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqSigAllReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqpnReg_wget = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd1 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd0 && - cntrl_sqTypeReg == 4'd4 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd3 ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_sqpnReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_dqpnReg_wget = - cntrl_sqTypeReg == 4'd2 || cntrl_sqTypeReg == 4'd3 || - cntrl_sqTypeReg == 4'd9 ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_dqpnReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_pkeyReg_wget = - 1'b1 ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_cntrl_pkeyReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _first_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _deq_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget = - 1'd1 ; - assign _deq_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _i_notEmpty_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2734 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_pendingReqHeaderQ_FULL_N ; - assign _i_notEmpty_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_reqHeaderPrepareQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _enq_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_pendingReqHeaderQ_wget = - 1'd1 ; - assign _enq_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_pendingReqHeaderQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _i_notFull_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_pendingReqHeaderQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2734 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqHeaderPrepareQ_EMPTY_N ; - assign _i_notFull_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_pendingReqHeaderQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2734 && - sq_reqGenSQ_pendingReqHeaderQ_FULL_N && - sq_reqGenSQ_reqHeaderPrepareQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_prepareReqHeaderGen_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign _read_RL_sq_reqGenSQ_genReqHeader_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - (!sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] || - !sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545] || - payloadGenerator4SQ_payloadGenRespQ_EMPTY_N) && - sq_reqGenSQ_pendingReqHeaderQ_EMPTY_N && - sq_reqGenSQ_reqHeaderGenQ_FULL_N && - sq_reqGenSQ_isNormalStateReg ; - assign _read_RL_sq_reqGenSQ_genReqHeader_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _read_RL_sq_reqGenSQ_genReqHeader_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] || - !sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545] || - payloadGenerator4SQ_payloadGenRespQ_EMPTY_N) && - sq_reqGenSQ_pendingReqHeaderQ_EMPTY_N && - sq_reqGenSQ_reqHeaderGenQ_FULL_N && - sq_reqGenSQ_isNormalStateReg ; - assign _read_RL_sq_reqGenSQ_genReqHeader_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _first_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _deq_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_wget = - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] && - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545] ; - assign _deq_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _i_notEmpty_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] && - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545] && - sq_reqGenSQ_pendingReqHeaderQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqHeaderGenQ_FULL_N ; - assign _i_notEmpty_RL_sq_reqGenSQ_genReqHeader_EN_payloadGenerator4SQ_payloadGenRespQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _first_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _deq_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_wget = - 1'd1 ; - assign _deq_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _i_notEmpty_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] || - !sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545] || - payloadGenerator4SQ_payloadGenRespQ_EMPTY_N) && - sq_reqGenSQ_reqHeaderGenQ_FULL_N && - sq_reqGenSQ_isNormalStateReg ; - assign _i_notEmpty_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_pendingReqHeaderQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _enq_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_reqHeaderGenQ_wget = - 1'd1 ; - assign _enq_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_reqHeaderGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _i_notFull_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_reqHeaderGenQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] || - !sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545] || - payloadGenerator4SQ_payloadGenRespQ_EMPTY_N) && - sq_reqGenSQ_pendingReqHeaderQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg ; - assign _i_notFull_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_reqHeaderGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _read_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (!sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] || - !sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545] || - payloadGenerator4SQ_payloadGenRespQ_EMPTY_N) && - sq_reqGenSQ_pendingReqHeaderQ_EMPTY_N && - sq_reqGenSQ_reqHeaderGenQ_FULL_N ; - assign _read_RL_sq_reqGenSQ_genReqHeader_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_62_ETC___d3580 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqHeaderGenQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_62_ETC___d3580 && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqHeaderGenQ_EMPTY_N ; - assign _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_workCompGenReqOutQ_wget = - sq_reqGenSQ_reqHeaderGenQ_D_OUT[26] && - sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] || - !sq_reqGenSQ_reqHeaderGenQ_D_OUT[620] ; - assign _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_workCompGenReqOutQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_reqHeaderGenQ_EMPTY_N && - sq_reqGenSQ_reqHeaderGenQ_D_OUT[26] && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] ; - assign _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _first_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _deq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_wget = - 1'd1 ; - assign _deq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _i_notEmpty_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_isNormalStateReg && - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_62_ETC___d3580 ; - assign _i_notEmpty_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderOutQ_wget = - sq_reqGenSQ_reqHeaderGenQ_D_OUT[620] && - (!sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] || - !sq_reqGenSQ_reqHeaderGenQ_D_OUT[26]) ; - assign _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderOutQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - !sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] && - sq_reqGenSQ_psnReqOutQ_FULL_N && - sq_reqGenSQ_reqHeaderGenQ_EMPTY_N && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqHeaderGenQ_D_OUT[620] ; - assign _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_psnReqOutQ_wget = - _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_reqHeaderOutQ_wget ; - assign _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_psnReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_psnReqOutQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - !sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] && - sq_reqGenSQ_reqHeaderGenQ_EMPTY_N && - sq_reqGenSQ_reqHeaderGenQ_D_OUT[620] && - sq_reqGenSQ_isNormalStateReg && - sq_reqGenSQ_reqHeaderOutQ_FULL_N ; - assign _i_notFull_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_psnReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_reqGenSQ_reqHeaderGenQ_EMPTY_N && - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_62_ETC___d3580 ; - assign _read_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _write_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_isNormalStateReg_wget = - _enq_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_workCompGenReqOutQ_wget ; - assign _write_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign _read_RL_sq_reqGenSQ_errFlushWR_EN_cntrl_stateReg_wget = - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N && - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[2] || - !sq_reqGenSQ_workReqPayloadGenQ_D_OUT[1] || - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N) ; - assign _read_RL_sq_reqGenSQ_errFlushWR_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_errFlushWR ; - assign _enq_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_pendingWorkReqOutQ_wget = - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[2] && - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[1] ; - assign _enq_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_pendingWorkReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_errFlushWR ; - assign _i_notFull_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_pendingWorkReqOutQ_wget = - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[2] && - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[1] && - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N && - (cntrl_stateReg == 4'd6 || - cntrl_stateReg == 4'd3 && !sq_reqGenSQ_isNormalStateReg) ; - assign _i_notFull_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_pendingWorkReqOutQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_errFlushWR ; - assign _first_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_wget = - 1'b1 ; - assign _first_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_errFlushWR ; - assign _deq_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_wget = - 1'd1 ; - assign _deq_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_errFlushWR ; - assign _i_notEmpty_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_wget = - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[2] || - !sq_reqGenSQ_workReqPayloadGenQ_D_OUT[1] || - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N) && - (cntrl_stateReg == 4'd6 || - cntrl_stateReg == 4'd3 && !sq_reqGenSQ_isNormalStateReg) ; - assign _i_notEmpty_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_workReqPayloadGenQ_whas = - CAN_FIRE_RL_sq_reqGenSQ_errFlushWR ; - assign _read_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_isNormalStateReg_wget = - cntrl_stateReg == 4'd3 && - sq_reqGenSQ_workReqPayloadGenQ_EMPTY_N && - (!sq_reqGenSQ_workReqPayloadGenQ_D_OUT[2] || - !sq_reqGenSQ_workReqPayloadGenQ_D_OUT[1] || - sq_reqGenSQ_pendingWorkReqOutQ_FULL_N) ; - assign _read_RL_sq_reqGenSQ_errFlushWR_EN_sq_reqGenSQ_isNormalStateReg_whas = - CAN_FIRE_RL_sq_reqGenSQ_errFlushWR ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_cntrl_stateReg_wget = - sq_respHandleSQ_preStageStateReg == 2'd0 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - !sq_pendingWorkReqBuf_emptyReg ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_cntrl_npsnReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_cntrl_npsnReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _first_RL_sq_respHandleSQ_preBuildRespInfo_EN_respPktPipe_metaDataQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_preBuildRespInfo_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _i_notEmpty_RL_sq_respHandleSQ_preBuildRespInfo_EN_respPktPipe_metaDataQ_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd0 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - !sq_respHandleSQ_recvErrRespReg ; - assign _i_notEmpty_RL_sq_respHandleSQ_preBuildRespInfo_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_0_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd0 ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_0_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_1_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd1 ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_1_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_2_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd2 ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_2_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_3_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd3 ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_dataVec_3_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_deqPtrReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_deqPtrReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_emptyReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd0 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - respPktPipe_metaDataQ_EMPTY_N && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_pendingWorkReqBuf_emptyReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageRespAndWorkReqRelationReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageRespAndWorkReqRelationReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStagePktMetaDataReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStagePktMetaDataReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageReqPktInfoReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageReqPktInfoReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageRespTypeReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageRespTypeReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageStateReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - !sq_pendingWorkReqBuf_emptyReg ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageStateReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_preStageStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_recvErrRespReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd0 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - respPktPipe_metaDataQ_EMPTY_N && - !sq_pendingWorkReqBuf_emptyReg ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_errOccurredReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd0 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - !sq_pendingWorkReqBuf_emptyReg ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_retryFlushReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd0 && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - !sq_pendingWorkReqBuf_emptyReg ; - assign _read_RL_sq_respHandleSQ_preBuildRespInfo_EN_sq_respHandleSQ_retryFlushReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_cntrl_stateReg_wget = - sq_respHandleSQ_preStageStateReg == 2'd1 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_pendingWorkReqBuf_emptyReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd1 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_respHandleSQ_errOccurredReg ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_pendingWorkReqBuf_emptyReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageRespAndWorkReqRelationReg_wget = - sq_respHandleSQ_preStagePktMetaDataReg[1] ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageRespAndWorkReqRelationReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStagePktMetaDataReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStagePktMetaDataReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageRespTypeReg_wget = - sq_respHandleSQ_preStagePktMetaDataReg[1] ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageRespTypeReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageDeqPktMetaDataReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageDeqPktMetaDataReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageDeqPendingWorkReqReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageDeqPendingWorkReqReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageWorkReqAckTypeReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageWorkReqAckTypeReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageWorkCompReqTypeReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageWorkCompReqTypeReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_retryResetReqReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_retryResetReqReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageStateReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageStateReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_preStageStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_recvErrRespReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd1 && - !sq_respHandleSQ_retryFlushReg && - !sq_pendingWorkReqBuf_emptyReg && - !sq_respHandleSQ_errOccurredReg ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_errOccurredReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd1 && - !sq_respHandleSQ_retryFlushReg && - !sq_pendingWorkReqBuf_emptyReg && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_retryFlushReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd1 && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_preProcRespInfo_EN_sq_respHandleSQ_retryFlushReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_cntrl_stateReg_wget = - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _deq_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_respPktPipe_metaDataQ_wget = - sq_respHandleSQ_preStageDeqPktMetaDataReg ; - assign _deq_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _i_notEmpty_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_respPktPipe_metaDataQ_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - sq_respHandleSQ_preStageDeqPktMetaDataReg && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - sq_respHandleSQ_incomingRespQ_FULL_N && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) ; - assign _i_notEmpty_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_0_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd0 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_0_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_1_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd1 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_1_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_2_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd2 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_2_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_3_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd3 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_dataVec_3_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_deqPtrReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_deqPtrReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_scanStateReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_scanStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _port0__write_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_popReg_wget = - sq_respHandleSQ_preStageDeqPendingWorkReqReg ; - assign _port0__write_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_popReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _port1__read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_scanStartReg_wget = - sq_respHandleSQ_preStageDeqPendingWorkReqReg ; - assign _port1__read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_scanStartReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _port1__read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_preScanRestartReg_wget = - sq_respHandleSQ_preStageDeqPendingWorkReqReg ; - assign _port1__read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_pendingWorkReqBuf_preScanRestartReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _enq_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_incomingRespQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _i_notFull_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_incomingRespQ_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) ; - assign _i_notFull_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStagePktMetaDataReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStagePktMetaDataReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageReqPktInfoReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageReqPktInfoReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageRespTypeReg_wget = - sq_respHandleSQ_preStageWorkReqAckTypeReg != 4'd8 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !sq_respHandleSQ_recvRetryRespReg ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageRespTypeReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageDeqPktMetaDataReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageDeqPktMetaDataReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageDeqPendingWorkReqReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageDeqPendingWorkReqReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageWorkReqAckTypeReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageWorkReqAckTypeReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageWorkCompReqTypeReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageWorkCompReqTypeReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_retryResetReqReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_retryResetReqReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageStateReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _write_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageStateReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_preStageStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_recvErrRespReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_recvRetryRespReg_wget = - sq_respHandleSQ_preStageWorkReqAckTypeReg != 4'd8 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses999) && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_recvRetryRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_errOccurredReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_retryFlushReg_wget = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq_EN_sq_respHandleSQ_retryFlushReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _enq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_retryHandler_resetReqQ_wget = - cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 ; - assign _enq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_retryHandler_resetReqQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _i_notFull_RL_sq_respHandleSQ_recvRespHeader_EN_sq_retryHandler_resetReqQ_wget = - cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) && - sq_respHandleSQ_pendingRespQ_FULL_N && - sq_respHandleSQ_incomingRespQ_EMPTY_N ; - assign _i_notFull_RL_sq_respHandleSQ_recvRespHeader_EN_sq_retryHandler_resetReqQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _first_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _deq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _i_notEmpty_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_wget = - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) && - sq_respHandleSQ_pendingRespQ_FULL_N && - (cntrl_preStateReg != 4'd3 || cntrl_stateReg != 4'd3 || - sq_retryHandler_resetReqQ_FULL_N) ; - assign _i_notEmpty_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _enq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_pendingRespQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_pendingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _i_notFull_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_pendingRespQ_wget = - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) && - sq_respHandleSQ_incomingRespQ_EMPTY_N && - (cntrl_preStateReg != 4'd3 || cntrl_stateReg != 4'd3 || - sq_retryHandler_resetReqQ_FULL_N) ; - assign _i_notFull_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_pendingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget = - __duses1049 || - !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_retryFlushReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget = - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd2 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd5 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd10 ; - assign _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_wget = - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd1 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd4 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd7 ; - assign _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_errOccurredReg_wget = - (__duses1054 || __duses1054 || - sq_respHandleSQ_retryFlushReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9) && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_retryFlushReg_wget = - !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_retryFlushReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_retryFlushReg_wget = - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_wget ; - assign _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_retryFlushReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign _read_RL_sq_respHandleSQ_handleRespByType_EN_cntrl_stateReg_wget = - !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3 || - (sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd9 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 || - sq_retryHandler_retryReqQ_FULL_N) && - sq_respHandleSQ_pendingPermQueryQ_FULL_N && - sq_respHandleSQ_pendingRespQ_EMPTY_N ; - assign _read_RL_sq_respHandleSQ_handleRespByType_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _enq_RL_sq_respHandleSQ_handleRespByType_EN_sq_retryHandler_retryReqQ_wget = - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd9 || - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd10 ; - assign _enq_RL_sq_respHandleSQ_handleRespByType_EN_sq_retryHandler_retryReqQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _i_notFull_RL_sq_respHandleSQ_handleRespByType_EN_sq_retryHandler_retryReqQ_wget = - (sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd9 || - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd10) && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) && - sq_respHandleSQ_pendingPermQueryQ_FULL_N && - sq_respHandleSQ_pendingRespQ_EMPTY_N ; - assign _i_notFull_RL_sq_respHandleSQ_handleRespByType_EN_sq_retryHandler_retryReqQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _first_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _deq_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _i_notEmpty_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_wget = - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) && - sq_respHandleSQ_pendingPermQueryQ_FULL_N && - (sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd9 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 || - sq_retryHandler_retryReqQ_FULL_N) ; - assign _i_notEmpty_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _enq_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingPermQueryQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingPermQueryQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _i_notFull_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingPermQueryQ_wget = - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) && - sq_respHandleSQ_pendingRespQ_EMPTY_N && - (sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd9 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 || - sq_retryHandler_retryReqQ_FULL_N) ; - assign _i_notFull_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_pendingPermQueryQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _read_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_preRdmaOpCodeReg_wget = - !IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4824 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3 ; - assign _read_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_preRdmaOpCodeReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_preRdmaOpCodeReg_wget = - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - cntrl_stateReg != 4'd6 ; - assign _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_preRdmaOpCodeReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_wget = - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3 && - IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 ; - assign _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _read_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_errOccurredReg_wget = - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3 && - cntrl_stateReg != 4'd6 ; - assign _read_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign _read_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_cntrl_stateReg_wget = - sq_respHandleSQ_pendingPermQueryQ_EMPTY_N && - sq_respHandleSQ_pendingRetryCheckQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp ; - assign _first_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp ; - assign _deq_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp ; - assign _i_notEmpty_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_wget = - sq_respHandleSQ_pendingRetryCheckQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notEmpty_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermQueryQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp ; - assign _enq_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingRetryCheckQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingRetryCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp ; - assign _i_notFull_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingRetryCheckQ_wget = - sq_respHandleSQ_pendingPermQueryQ_EMPTY_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingRetryCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp ; - assign _read_RL_sq_respHandleSQ_checkRetryErr_EN_cntrl_stateReg_wget = - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 || - sq_retryHandler_retryRespQ_EMPTY_N) && - sq_respHandleSQ_pendingPermCheckQ_FULL_N && - sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N && - IF_sq_respHandleSQ_pendingRetryCheckQ_first__9_ETC___d5037 ; - assign _read_RL_sq_respHandleSQ_checkRetryErr_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign _first_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_wget = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd9 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd10 ; - assign _first_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign _deq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_wget = - _first_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_wget ; - assign _deq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_wget = - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd9 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd10) && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) && - sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N && - sq_respHandleSQ_pendingPermCheckQ_FULL_N ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkRetryErr_EN_sq_retryHandler_retryRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign _first_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign _deq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_wget = - cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6 ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingRetryCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign _enq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingPermCheckQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingPermCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign _i_notFull_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingPermCheckQ_wget = - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 || - sq_retryHandler_retryRespQ_EMPTY_N) && - sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N && - IF_sq_respHandleSQ_pendingRetryCheckQ_first__9_ETC___d5037 ; - assign _i_notFull_RL_sq_respHandleSQ_checkRetryErr_EN_sq_respHandleSQ_pendingPermCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign _read_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_cntrl_stateReg_wget = - sq_respHandleSQ_pendingPermCheckQ_EMPTY_N && - sq_respHandleSQ_pendingAddrCalcQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp ; - assign _first_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp ; - assign _deq_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_wget = - sq_respHandleSQ_pendingAddrCalcQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingPermCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp ; - assign _enq_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingAddrCalcQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingAddrCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp ; - assign _i_notFull_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingAddrCalcQ_wget = - sq_respHandleSQ_pendingPermCheckQ_EMPTY_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp_EN_sq_respHandleSQ_pendingAddrCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp ; - assign _read_RL_sq_respHandleSQ_calcReadRespAddr_EN_cntrl_stateReg_wget = - sq_respHandleSQ_pendingAddrCalcQ_EMPTY_N && - sq_respHandleSQ_pendingLenCalcQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_calcReadRespAddr_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - assign _first_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - assign _deq_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - assign _i_notEmpty_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_wget = - sq_respHandleSQ_pendingLenCalcQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notEmpty_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingAddrCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - assign _enq_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingLenCalcQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingLenCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - assign _i_notFull_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingLenCalcQ_wget = - sq_respHandleSQ_pendingAddrCalcQ_EMPTY_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_pendingLenCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - assign _read_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_nextReadRespWriteAddrReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_calcReadRespAddr_EN_sq_respHandleSQ_nextReadRespWriteAddrReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - assign _read_RL_sq_respHandleSQ_calcReadRespLen_EN_cntrl_stateReg_wget = - sq_respHandleSQ_pendingLenCalcQ_EMPTY_N && - sq_respHandleSQ_pendingSpaceCalcQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_calcReadRespLen_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - assign _first_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - assign _deq_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - assign _i_notEmpty_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_wget = - sq_respHandleSQ_pendingSpaceCalcQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notEmpty_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingLenCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - assign _enq_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - assign _i_notFull_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget = - sq_respHandleSQ_pendingLenCalcQ_EMPTY_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - assign _read_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_remainingReadRespLenReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_calcReadRespLen_EN_sq_respHandleSQ_remainingReadRespLenReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - assign _read_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_cntrl_stateReg_wget = - sq_respHandleSQ_pendingSpaceCalcQ_EMPTY_N && - sq_respHandleSQ_pendingLenCheckQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace ; - assign _first_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace ; - assign _deq_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace ; - assign _i_notEmpty_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_wget = - sq_respHandleSQ_pendingLenCheckQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notEmpty_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingSpaceCalcQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace ; - assign _enq_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingLenCheckQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingLenCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace ; - assign _i_notFull_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingLenCheckQ_wget = - sq_respHandleSQ_pendingSpaceCalcQ_EMPTY_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_respHandleSQ_calcEnoughDmaSpace_EN_sq_respHandleSQ_pendingLenCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace ; - assign _read_RL_sq_respHandleSQ_checkReadRespLen_EN_cntrl_stateReg_wget = - sq_respHandleSQ_pendingLenCheckQ_EMPTY_N && - sq_respHandleSQ_pendingDmaReqQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_checkReadRespLen_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen ; - assign _first_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen ; - assign _deq_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_wget = - sq_respHandleSQ_pendingDmaReqQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingLenCheckQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen ; - assign _enq_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingDmaReqQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingDmaReqQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen ; - assign _i_notFull_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingDmaReqQ_wget = - sq_respHandleSQ_pendingLenCheckQ_EMPTY_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_respHandleSQ_checkReadRespLen_EN_sq_respHandleSQ_pendingDmaReqQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen ; - assign _read_RL_sq_respHandleSQ_issueDmaReq_EN_cntrl_stateReg_wget = - sq_respHandleSQ_pendingDmaReqQ_EMPTY_N && - sq_respHandleSQ_pendingWorkCompQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_issueDmaReq_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - assign _first_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - assign _deq_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - assign _i_notEmpty_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_wget = - sq_respHandleSQ_pendingWorkCompQ_FULL_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notEmpty_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingDmaReqQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - assign _enq_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingWorkCompQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingWorkCompQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - assign _i_notFull_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingWorkCompQ_wget = - sq_respHandleSQ_pendingDmaReqQ_EMPTY_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_pendingWorkCompQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - assign _port0__write_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_hasInternalErrReg_wget = - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 ; - assign _port0__write_RL_sq_respHandleSQ_issueDmaReq_EN_sq_respHandleSQ_hasInternalErrReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - assign _read_RL_sq_respHandleSQ_genWorkCompSQ_EN_cntrl_stateReg_wget = - sq_respHandleSQ_pendingWorkCompQ_EMPTY_N && - (!sq_respHandleSQ_pendingWorkCompQ_D_OUT[633] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[31] || - sq_respHandleSQ_workCompGenReqOutQ_FULL_N) ; - assign _read_RL_sq_respHandleSQ_genWorkCompSQ_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ ; - assign _enq_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget = - sq_respHandleSQ_pendingWorkCompQ_D_OUT[633] || - sq_respHandleSQ_pendingWorkCompQ_D_OUT[31] ; - assign _enq_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ ; - assign _i_notFull_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget = - (sq_respHandleSQ_pendingWorkCompQ_D_OUT[633] || - sq_respHandleSQ_pendingWorkCompQ_D_OUT[31]) && - sq_respHandleSQ_pendingWorkCompQ_EMPTY_N && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ ; - assign _first_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ ; - assign _deq_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ ; - assign _i_notEmpty_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_wget = - (!sq_respHandleSQ_pendingWorkCompQ_D_OUT[633] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[31] || - sq_respHandleSQ_workCompGenReqOutQ_FULL_N) && - (cntrl_stateReg == 4'd3 || cntrl_stateReg == 4'd6) ; - assign _i_notEmpty_RL_sq_respHandleSQ_genWorkCompSQ_EN_sq_respHandleSQ_pendingWorkCompQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_cntrl_stateReg_wget = - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _first_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _deq_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _notEmpty_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg && - respPktPipe_metaDataQ_EMPTY_N ; - assign _notEmpty_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _i_notEmpty_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_pendingWorkReqBuf_emptyReg && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _i_notEmpty_RL_sq_respHandleSQ_discardGhostResp_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_pendingWorkReqBuf_emptyReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_pendingWorkReqBuf_emptyReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _enq_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_incomingRespQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _i_notFull_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_incomingRespQ_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_pendingWorkReqBuf_emptyReg ; - assign _i_notFull_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_recvErrRespReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_errOccurredReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_retryFlushReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg ; - assign _read_RL_sq_respHandleSQ_discardGhostResp_EN_sq_respHandleSQ_retryFlushReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_cntrl_stateReg_wget = - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - sq_retryHandler_timeOutNotificationQ_EMPTY_N && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - assign _first_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - assign _deq_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_respHandleSQ_errOccurredReg ; - assign _i_notEmpty_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_retryHandler_timeOutNotificationQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - assign _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_recvErrRespReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - sq_retryHandler_timeOutNotificationQ_EMPTY_N && - !sq_respHandleSQ_errOccurredReg ; - assign _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - assign _port0__write_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_hasTimeOutErrReg_wget = - sq_retryHandler_timeOutNotificationQ_D_OUT ; - assign _port0__write_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_hasTimeOutErrReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - assign _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_errOccurredReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - sq_retryHandler_timeOutNotificationQ_EMPTY_N && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - assign _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_retryFlushReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_errOccurredReg && - sq_retryHandler_timeOutNotificationQ_EMPTY_N && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_checkTimeOutErr_EN_sq_respHandleSQ_retryFlushReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_cntrl_stateReg_wget = - !sq_pendingWorkReqBuf_emptyReg && - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) && - (sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_0_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd0 ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_0_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_1_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd1 ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_1_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_2_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd2 ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_2_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_3_wget = - sq_pendingWorkReqBuf_deqPtrReg == 2'd3 ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_dataVec_3_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_deqPtrReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_deqPtrReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_scanStateReg_wget = - !sq_pendingWorkReqBuf_emptyReg && - sq_respHandleSQ_incomingRespQ_FULL_N && - (cntrl_stateReg == 4'd3 && - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) || - cntrl_stateReg == 4'd6) ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_scanStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_wget = - (cntrl_stateReg == 4'd3 && - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) || - cntrl_stateReg == 4'd6) && - (sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_emptyReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _port0__write_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_popReg_wget = - 1'd1 ; - assign _port0__write_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_popReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _port1__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_scanStartReg_wget = - 1'b1 ; - assign _port1__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_scanStartReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _port1__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_preScanRestartReg_wget = - 1'b1 ; - assign _port1__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_pendingWorkReqBuf_preScanRestartReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _enq_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_incomingRespQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _i_notFull_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_incomingRespQ_wget = - !sq_pendingWorkReqBuf_emptyReg && - (sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (cntrl_stateReg == 4'd3 && - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) || - cntrl_stateReg == 4'd6) ; - assign _i_notFull_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_recvErrRespReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - (sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _port0__write_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_hasTimeOutErrReg_wget = - 1'd1 ; - assign _port0__write_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_hasTimeOutErrReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _port0__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_hasTimeOutErrReg_wget = - 1'b1 ; - assign _port0__read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_hasTimeOutErrReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_errOccurredReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_errFlushWorkReq_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_cntrl_stateReg_wget = - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg && - respPktPipe_metaDataQ_EMPTY_N ; - assign _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - assign _first_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_wget = - 1'b1 ; - assign _first_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - assign _deq_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_wget = - 1'd1 ; - assign _deq_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - assign _i_notEmpty_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_wget = - (cntrl_stateReg == 4'd3 && - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) || - cntrl_stateReg == 4'd6) && - sq_pendingWorkReqBuf_emptyReg && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _i_notEmpty_RL_sq_respHandleSQ_errFlushIncomingResp_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - assign _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_pendingWorkReqBuf_emptyReg_wget = - (cntrl_stateReg == 4'd3 && - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) || - cntrl_stateReg == 4'd6) && - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_pendingWorkReqBuf_emptyReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - assign _enq_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_incomingRespQ_wget = - 1'd1 ; - assign _enq_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - assign _i_notFull_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_incomingRespQ_wget = - (cntrl_stateReg == 4'd3 && - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) || - cntrl_stateReg == 4'd6) && - sq_pendingWorkReqBuf_emptyReg && - respPktPipe_metaDataQ_EMPTY_N ; - assign _i_notFull_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - assign _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_recvErrRespReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg && - respPktPipe_metaDataQ_EMPTY_N ; - assign _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - assign _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_errOccurredReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg && - respPktPipe_metaDataQ_EMPTY_N ; - assign _read_RL_sq_respHandleSQ_errFlushIncomingResp_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_cntrl_stateReg_wget = - !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_cntrl_stateReg_whas = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_pendingWorkReqBuf_emptyReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_pendingWorkReqBuf_emptyReg_whas = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_retryHandler_retryHandleStateReg_wget = - 1'b1 ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_retryHandler_retryHandleStateReg_whas = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_recvErrRespReg_wget = - cntrl_stateReg == 4'd3 && sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_recvErrRespReg_whas = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign _write_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_recvRetryRespReg_wget = - sq_retryHandler_retryHandleStateReg == 3'd7 ; - assign _write_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_recvRetryRespReg_whas = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_errOccurredReg_wget = - cntrl_stateReg == 4'd3 && sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_errOccurredReg_whas = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_retryFlushReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_recvErrRespReg && - !sq_respHandleSQ_errOccurredReg ; - assign _read_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_retryFlushReg_whas = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign _write_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_retryFlushReg_wget = - sq_retryHandler_retryHandleStateReg == 3'd7 ; - assign _write_RL_sq_respHandleSQ_retryFlushDone_EN_sq_respHandleSQ_retryFlushReg_whas = - cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 ; - assign _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_cntrl_stateReg_wget = - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_retryFlushReg && - (!respPktPipe_metaDataQ_EMPTY_N || - sq_respHandleSQ_incomingRespQ_FULL_N) ; - assign _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _first_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_wget = - respPktPipe_metaDataQ_EMPTY_N ; - assign _first_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _deq_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_wget = - respPktPipe_metaDataQ_EMPTY_N ; - assign _deq_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _notEmpty_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_wget = - 1'b1 ; - assign _notEmpty_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _i_notEmpty_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_wget = - cntrl_stateReg == 4'd3 && respPktPipe_metaDataQ_EMPTY_N && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_retryFlushReg && - sq_respHandleSQ_incomingRespQ_FULL_N ; - assign _i_notEmpty_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_respPktPipe_metaDataQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _enq_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_incomingRespQ_wget = - respPktPipe_metaDataQ_EMPTY_N ; - assign _enq_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _i_notFull_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_incomingRespQ_wget = - cntrl_stateReg == 4'd3 && respPktPipe_metaDataQ_EMPTY_N && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_retryFlushReg ; - assign _i_notFull_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_incomingRespQ_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _write_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_preStageStateReg_wget = - 1'd1 ; - assign _write_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_preStageStateReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_recvErrRespReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_retryFlushReg && - (!respPktPipe_metaDataQ_EMPTY_N || - sq_respHandleSQ_incomingRespQ_FULL_N) ; - assign _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_recvErrRespReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_errOccurredReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_retryFlushReg && - (!respPktPipe_metaDataQ_EMPTY_N || - sq_respHandleSQ_incomingRespQ_FULL_N) ; - assign _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_errOccurredReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_retryFlushReg_wget = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_errOccurredReg && - (!respPktPipe_metaDataQ_EMPTY_N || - sq_respHandleSQ_incomingRespQ_FULL_N) && - !sq_respHandleSQ_recvErrRespReg ; - assign _read_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload_EN_sq_respHandleSQ_retryFlushReg_whas = - CAN_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload ; - assign _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 && - IF_sq_reqGenSQ_workCompGenReqOutQ_notEmpty__69_ETC___d5707 && - cntrl_stateReg != 4'd6 && - sq_workCompGenSQ_workCompGenStateReg != 2'd2 ; - assign _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && - IF_sq_reqGenSQ_workCompGenReqOutQ_notEmpty__69_ETC___d5707 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 ; - assign _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _first_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_wget = - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N ; - assign _first_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _deq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_wget = - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N ; - assign _deq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_wget = - 1'b1 ; - assign _notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _i_notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_wget = - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 || - cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) && - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N && - sq_workCompGenSQ_pendingWorkCompQ4SQ_FULL_N ; - assign _i_notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_reqGenSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _first_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget = - sq_respHandleSQ_workCompGenReqOutQ_EMPTY_N && - !sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N ; - assign _first_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _deq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget = - !sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N && - sq_respHandleSQ_workCompGenReqOutQ_EMPTY_N ; - assign _deq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget = - !sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N ; - assign _notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _i_notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_wget = - !sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N && - sq_respHandleSQ_workCompGenReqOutQ_EMPTY_N && - sq_workCompGenSQ_pendingWorkCompQ4SQ_FULL_N && - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 || - cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) ; - assign _i_notEmpty_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_respHandleSQ_workCompGenReqOutQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _enq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget = - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N || - sq_respHandleSQ_workCompGenReqOutQ_EMPTY_N ; - assign _enq_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _i_notFull_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget = - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N && - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 || - cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) ; - assign _i_notFull_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget = - cntrl_stateReg == 4'd3 && - IF_sq_reqGenSQ_workCompGenReqOutQ_notEmpty__69_ETC___d5707 && - cntrl_preStateReg == 4'd3 ; - assign _read_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 && - cntrl_stateReg != 4'd6 && - sq_workCompGenSQ_workCompGenStateReg != 2'd2 && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[30:29] != 2'd0 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[561] || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd4 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd5 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd6 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) && - sq_workCompGenSQ_pendingWorkCompQ4SQ_EMPTY_N && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) && - sq_workCompGenSQ_dmaWaitingQ_FULL_N ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_stateReg_wget = - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd0 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd1 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd2 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd3 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd4 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd5 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd6 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd7 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd8 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd9 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd10) && - sq_workCompGenSQ_dmaWaitingQ_FULL_N && - sq_workCompGenSQ_pendingWorkCompQ4SQ_EMPTY_N ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_sqSigAllReg_wget = - !sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[561] && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[30:29] == 2'd0 ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_sqSigAllReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_sqpnReg_wget = - 1'b1 ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_sqpnReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_pkeyReg_wget = - 1'b1 ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_cntrl_pkeyReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _enq_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget = - 1'd1 ; - assign _enq_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _i_notFull_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget = - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 || - cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[30:29] != 2'd0 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[561] || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd4 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd5 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd6 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) && - sq_workCompGenSQ_pendingWorkCompQ4SQ_EMPTY_N ; - assign _i_notFull_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _first_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget = - 1'b1 ; - assign _first_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _deq_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget = - 1'd1 ; - assign _deq_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _i_notEmpty_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_wget = - (cntrl_preStateReg == 4'd3 && cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 || - cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[30:29] != 2'd0 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[561] || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd4 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd5 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd6 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) && - sq_workCompGenSQ_dmaWaitingQ_FULL_N ; - assign _i_notEmpty_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_pendingWorkCompQ4SQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[30:29] != 2'd0 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[561] || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd4 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd5 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd6 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) && - sq_workCompGenSQ_pendingWorkCompQ4SQ_EMPTY_N && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) && - sq_workCompGenSQ_dmaWaitingQ_FULL_N ; - assign _read_RL_sq_workCompGenSQ_genPendingWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 && - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N && - sq_workCompGenSQ_genWorkCompQ_FULL_N ; - assign _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 && - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N && - sq_workCompGenSQ_genWorkCompQ_FULL_N ; - assign _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign _first_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget = - 1'b1 ; - assign _first_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign _deq_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget = - 1'd1 ; - assign _deq_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign _i_notEmpty_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_workCompGenSQ_genWorkCompQ_FULL_N && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 ; - assign _i_notEmpty_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign _enq_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget = - 1'd1 ; - assign _enq_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign _i_notFull_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 ; - assign _i_notFull_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N && - sq_workCompGenSQ_genWorkCompQ_FULL_N ; - assign _read_RL_sq_workCompGenSQ_waitDmaDoneSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_cntrl_preStateReg_wget = - cntrl_stateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 && - sq_workCompGenSQ_genWorkCompQ_EMPTY_N && - IF_sq_workCompGenSQ_genWorkCompQ_first__802_BI_ETC___d5808 ; - assign _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_cntrl_preStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_cntrl_stateReg_wget = - cntrl_preStateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 && - sq_workCompGenSQ_genWorkCompQ_EMPTY_N && - IF_sq_workCompGenSQ_genWorkCompQ_first__802_BI_ETC___d5808 ; - assign _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _enq_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompOutQ4SQ_wget = - sq_workCompGenSQ_genWorkCompQ_D_OUT[0] || - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1] ; - assign _enq_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompOutQ4SQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _i_notFull_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompOutQ4SQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 && - sq_workCompGenSQ_genWorkCompQ_EMPTY_N && - sq_workCompGenSQ_genWorkCompQ_D_OUT[0] ; - assign _i_notFull_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompOutQ4SQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _first_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget = - 1'b1 ; - assign _first_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _deq_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget = - 1'd1 ; - assign _deq_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _i_notEmpty_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - IF_sq_workCompGenSQ_genWorkCompQ_first__802_BI_ETC___d5808 && - sq_workCompGenSQ_workCompGenStateReg == 2'd1 ; - assign _i_notEmpty_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget = - cntrl_stateReg == 4'd3 && cntrl_preStateReg == 4'd3 && - sq_workCompGenSQ_genWorkCompQ_EMPTY_N && - IF_sq_workCompGenSQ_genWorkCompQ_first__802_BI_ETC___d5808 ; - assign _read_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget = - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1] ; - assign _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_wget = - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1] ; - assign _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_wget = - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1] ; - assign _write_RL_sq_workCompGenSQ_genWorkCompSQ_EN_sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign _read_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_cntrl_stateReg_wget = - sq_workCompGenSQ_workCompGenStateReg != 2'd2 && - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N && - sq_workCompGenSQ_genWorkCompQ_FULL_N ; - assign _read_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_cntrl_stateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ ; - assign _first_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget = - 1'b1 ; - assign _first_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ ; - assign _deq_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget = - 1'd1 ; - assign _deq_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ ; - assign _i_notEmpty_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_wget = - (cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) && - sq_workCompGenSQ_genWorkCompQ_FULL_N ; - assign _i_notEmpty_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_dmaWaitingQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ ; - assign _enq_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget = - 1'd1 ; - assign _enq_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ ; - assign _i_notFull_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_genWorkCompQ_wget = - (cntrl_stateReg == 4'd6 || - sq_workCompGenSQ_workCompGenStateReg == 2'd2) && - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N ; - assign _i_notFull_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_genWorkCompQ_whas = - CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ ; - assign _read_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_workCompGenStateReg_wget = - cntrl_stateReg != 4'd6 && sq_workCompGenSQ_dmaWaitingQ_EMPTY_N && - sq_workCompGenSQ_genWorkCompQ_FULL_N ; - assign _read_RL_sq_workCompGenSQ_noDmaWaitSQ_EN_sq_workCompGenSQ_workCompGenStateReg_whas = - CAN_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ ; - assign payloadGenerator4SQ_payloadBufQ_pwDequeue_whas = - CAN_FIRE_RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut ; - assign payloadGenerator4SQ_payloadBufQ_pwEnqueue_whas = - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding ; - assign payloadGenerator4SQ_payloadBufQ_pwClear_whas = - cntrl_stateReg == 4'd0 ; - assign cntrl_setStateErrReg_port0__read = cntrl_setStateErrReg ; - assign cntrl_setStateErrReg_EN_port0__write = CAN_FIRE_RL_errTrigger ; - assign cntrl_setStateErrReg_port0__write_1 = 1'd1 ; - assign cntrl_setStateErrReg_port1__read = - CAN_FIRE_RL_errTrigger || cntrl_setStateErrReg ; - assign cntrl_setStateErrReg_EN_port1__write = 1'd1 ; - assign cntrl_setStateErrReg_port1__write_1 = 1'd0 ; - assign cntrl_setStateErrReg_port2__read = 1'd0 ; - assign cntrl_setStateErrReg_EN_port2__write = 1'b0 ; - assign cntrl_setStateErrReg_port2__write_1 = 1'b0 ; - assign cntrl_setStateErrReg_port3__read = 1'd0 ; - assign cntrl_setStateErrReg_EN_port3__write = 1'b0 ; - assign cntrl_setStateErrReg_port3__write_1 = 1'b0 ; - assign cntrl_setStateErrReg_port4__read = 1'd0 ; - assign cntrl_setStateErrReg_EN_port4__write = 1'b0 ; - assign cntrl_setStateErrReg_port4__write_1 = 1'b0 ; - assign cntrl_qpDestroyReg_port0__read = cntrl_qpDestroyReg ; - assign cntrl_qpDestroyReg_EN_port0__write = 1'b0 ; - assign cntrl_qpDestroyReg_port0__write_1 = 1'b0 ; - assign cntrl_qpDestroyReg_port1__read = cntrl_qpDestroyReg ; - assign cntrl_qpDestroyReg_EN_port1__write = 1'b0 ; - assign cntrl_qpDestroyReg_port1__write_1 = 1'b0 ; - assign cntrl_qpDestroyReg_port2__read = cntrl_qpDestroyReg ; - assign cntrl_qpDestroyReg_EN_port2__write = 1'b0 ; - assign cntrl_qpDestroyReg_port2__write_1 = 1'b0 ; - assign cntrl_qpDestroyReg_port3__read = cntrl_qpDestroyReg ; - assign cntrl_qpDestroyReg_EN_port3__write = 1'b0 ; - assign cntrl_qpDestroyReg_port3__write_1 = 1'b0 ; - assign cntrl_qpDestroyReg_port4__read = cntrl_qpDestroyReg ; - assign cntrl_qpDestroyReg_EN_port4__write = 1'b0 ; - assign cntrl_qpDestroyReg_port4__write_1 = 1'b0 ; - assign cntrl_nextStateReg_port0__read = cntrl_nextStateReg ; - assign cntrl_nextStateReg_EN_port0__write = - WILL_FIRE_RL_cntrl_onReset && - cntrl_reqQ_D_OUT[300:299] == 2'd0 || - WILL_FIRE_RL_cntrl_onCreate && - cntrl_reqQ_D_OUT[300:299] == 2'd2 && - cntrl_reqQ_D_OUT[216:213] == 4'd1 && - { 21'd0, - cntrl_reqQ_D_OUT[221:220], - 2'd0, - cntrl_reqQ_D_OUT[217] } == - 26'd25 || - WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd2 && - cntrl_reqQ_D_OUT[216:213] == 4'd2 && - { 5'd0, - cntrl_reqQ_D_OUT[237], - 2'd0, - cntrl_reqQ_D_OUT[234], - 1'd0, - cntrl_reqQ_D_OUT[232], - 2'd0, - cntrl_reqQ_D_OUT[229], - 3'd0, - cntrl_reqQ_D_OUT[225], - 7'd0, - cntrl_reqQ_D_OUT[217] } == - 26'd1216769 || - WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd2 && - (cntrl_reqQ_D_OUT[216:213] == 4'd6 && cntrl_reqQ_D_OUT[217] || - cntrl_reqQ_D_OUT[216:213] == 4'd3 && - { 9'd0, - cntrl_reqQ_D_OUT[233], - 2'd0, - cntrl_reqQ_D_OUT[230], - 1'd0, - cntrl_reqQ_D_OUT[228:226], - 8'd0, - cntrl_reqQ_D_OUT[217] } == - 26'd77313) || - WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] == 2'd2 && - (cntrl_reqQ_D_OUT[216:213] == 4'd4 || - cntrl_reqQ_D_OUT[216:213] == 4'd6) && - cntrl_reqQ_D_OUT[217] || - WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] == 2'd2 && - (cntrl_reqQ_D_OUT[216:213] == 4'd6 || - cntrl_reqQ_D_OUT[216:213] == 4'd3) && - cntrl_reqQ_D_OUT[217] || - WILL_FIRE_RL_cntrl_onERR && - (cntrl_reqQ_D_OUT[300:299] == 2'd1 || - cntrl_reqQ_D_OUT[300:299] == 2'd2 && - cntrl_reqQ_D_OUT[216:213] == 4'd0 && - cntrl_reqQ_D_OUT[217]) ; - always@(MUX_cntrl_nextStateReg_port0__write_1__SEL_1 or - MUX_cntrl_nextStateReg_port0__write_1__SEL_2 or - MUX_cntrl_nextStateReg_port0__write_1__VAL_2 or - MUX_cntrl_nextStateReg_port0__write_1__SEL_3 or - MUX_cntrl_nextStateReg_port0__write_1__SEL_4 or - MUX_cntrl_nextStateReg_port0__write_1__SEL_5 or - MUX_cntrl_nextStateReg_port0__write_1__SEL_6 or - MUX_cntrl_nextStateReg_port0__write_1__SEL_7 or - MUX_cntrl_nextStateReg_port0__write_1__VAL_7) - begin - case (1'b1) // synopsys parallel_case - MUX_cntrl_nextStateReg_port0__write_1__SEL_1: - cntrl_nextStateReg_port0__write_1 = 5'd24; - MUX_cntrl_nextStateReg_port0__write_1__SEL_2: - cntrl_nextStateReg_port0__write_1 = - MUX_cntrl_nextStateReg_port0__write_1__VAL_2; - MUX_cntrl_nextStateReg_port0__write_1__SEL_3: - cntrl_nextStateReg_port0__write_1 = - MUX_cntrl_nextStateReg_port0__write_1__VAL_2; - MUX_cntrl_nextStateReg_port0__write_1__SEL_4: - cntrl_nextStateReg_port0__write_1 = - MUX_cntrl_nextStateReg_port0__write_1__VAL_2; - MUX_cntrl_nextStateReg_port0__write_1__SEL_5: - cntrl_nextStateReg_port0__write_1 = - MUX_cntrl_nextStateReg_port0__write_1__VAL_2; - MUX_cntrl_nextStateReg_port0__write_1__SEL_6: - cntrl_nextStateReg_port0__write_1 = - MUX_cntrl_nextStateReg_port0__write_1__VAL_2; - MUX_cntrl_nextStateReg_port0__write_1__SEL_7: - cntrl_nextStateReg_port0__write_1 = - MUX_cntrl_nextStateReg_port0__write_1__VAL_7; - default: cntrl_nextStateReg_port0__write_1 = - 5'b01010 /* unspecified value */ ; - endcase - end - assign cntrl_nextStateReg_port1__read = - cntrl_nextStateReg_EN_port0__write ? - cntrl_nextStateReg_port0__write_1 : - cntrl_nextStateReg ; - assign cntrl_nextStateReg_EN_port1__write = 1'd1 ; - assign cntrl_nextStateReg_port1__write_1 = 5'd10 ; - assign cntrl_nextStateReg_port2__read = 5'd10 ; - assign cntrl_nextStateReg_EN_port2__write = 1'b0 ; - assign cntrl_nextStateReg_port2__write_1 = 5'h0 ; - assign cntrl_nextStateReg_port3__read = 5'd10 ; - assign cntrl_nextStateReg_EN_port3__write = 1'b0 ; - assign cntrl_nextStateReg_port3__write_1 = 5'h0 ; - assign cntrl_nextStateReg_port4__read = 5'd10 ; - assign cntrl_nextStateReg_EN_port4__write = 1'b0 ; - assign cntrl_nextStateReg_port4__write_1 = 5'h0 ; - assign cntrl_preReqOpCodeReg_port0__read = cntrl_preReqOpCodeReg ; - assign cntrl_preReqOpCodeReg_EN_port0__write = cntrl_stateReg == 4'd0 ; - assign cntrl_preReqOpCodeReg_port0__write_1 = 5'd4 ; - assign cntrl_preReqOpCodeReg_port1__read = - (cntrl_stateReg == 4'd0) ? 5'd4 : cntrl_preReqOpCodeReg ; - assign cntrl_preReqOpCodeReg_EN_port1__write = CAN_FIRE_RL_cntrl_restore ; - assign cntrl_preReqOpCodeReg_port1__write_1 = cntrl_restoreQ_D_OUT[28:24] ; - assign cntrl_preReqOpCodeReg_port2__read = - CAN_FIRE_RL_cntrl_restore ? - cntrl_restoreQ_D_OUT[28:24] : - cntrl_preReqOpCodeReg_port1__read ; - assign cntrl_preReqOpCodeReg_EN_port2__write = 1'b0 ; - assign cntrl_preReqOpCodeReg_port2__write_1 = 5'h0 ; - assign cntrl_preReqOpCodeReg_port3__read = - cntrl_preReqOpCodeReg_port2__read ; - assign cntrl_preReqOpCodeReg_EN_port3__write = 1'b0 ; - assign cntrl_preReqOpCodeReg_port3__write_1 = 5'h0 ; - assign cntrl_preReqOpCodeReg_port4__read = - cntrl_preReqOpCodeReg_port2__read ; - assign cntrl_preReqOpCodeReg_EN_port4__write = 1'b0 ; - assign cntrl_preReqOpCodeReg_port4__write_1 = 5'h0 ; - assign cntrl_epsnReg_port0__read = cntrl_epsnReg ; - assign cntrl_epsnReg_EN_port0__write = - WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd2 ; - assign cntrl_epsnReg_port0__write_1 = cntrl_reqQ_D_OUT[173:150] ; - assign cntrl_epsnReg_port1__read = - cntrl_epsnReg_EN_port0__write ? - cntrl_reqQ_D_OUT[173:150] : - cntrl_epsnReg ; - assign cntrl_epsnReg_EN_port1__write = CAN_FIRE_RL_cntrl_restore ; - assign cntrl_epsnReg_port1__write_1 = cntrl_restoreQ_D_OUT[23:0] ; - assign cntrl_epsnReg_port2__read = - CAN_FIRE_RL_cntrl_restore ? - cntrl_restoreQ_D_OUT[23:0] : - cntrl_epsnReg_port1__read ; - assign cntrl_epsnReg_EN_port2__write = 1'b0 ; - assign cntrl_epsnReg_port2__write_1 = 24'h0 ; - assign cntrl_epsnReg_port3__read = cntrl_epsnReg_port2__read ; - assign cntrl_epsnReg_EN_port3__write = 1'b0 ; - assign cntrl_epsnReg_port3__write_1 = 24'h0 ; - assign cntrl_epsnReg_port4__read = cntrl_epsnReg_port2__read ; - assign cntrl_epsnReg_EN_port4__write = 1'b0 ; - assign cntrl_epsnReg_port4__write_1 = 24'h0 ; - assign dmaReadCntrl4SQ_gracefulStopReg_port0__read = - dmaReadCntrl4SQ_gracefulStopReg ; - assign dmaReadCntrl4SQ_gracefulStopReg_EN_port0__write = - CAN_FIRE_RL_cancelDmaReadSQ ; - assign dmaReadCntrl4SQ_gracefulStopReg_port0__write_1 = 1'd0 ; - assign dmaReadCntrl4SQ_gracefulStopReg_port1__read = - !CAN_FIRE_RL_cancelDmaReadSQ && dmaReadCntrl4SQ_gracefulStopReg ; - assign dmaReadCntrl4SQ_gracefulStopReg_EN_port1__write = - WILL_FIRE_RL_dmaReadCntrl4SQ_resetAndClear || - WILL_FIRE_RL_dmaReadCntrl4SQ_setGracefulStop ; - assign dmaReadCntrl4SQ_gracefulStopReg_port1__write_1 = - !WILL_FIRE_RL_dmaReadCntrl4SQ_resetAndClear ; - assign dmaReadCntrl4SQ_gracefulStopReg_port2__read = - dmaReadCntrl4SQ_gracefulStopReg_EN_port1__write ? - !WILL_FIRE_RL_dmaReadCntrl4SQ_resetAndClear : - dmaReadCntrl4SQ_gracefulStopReg_port1__read ; - assign dmaReadCntrl4SQ_gracefulStopReg_EN_port2__write = 1'b0 ; - assign dmaReadCntrl4SQ_gracefulStopReg_port2__write_1 = 1'b0 ; - assign dmaReadCntrl4SQ_gracefulStopReg_port3__read = - dmaReadCntrl4SQ_gracefulStopReg_port2__read ; - assign dmaReadCntrl4SQ_gracefulStopReg_EN_port3__write = 1'b0 ; - assign dmaReadCntrl4SQ_gracefulStopReg_port3__write_1 = 1'b0 ; - assign dmaReadCntrl4SQ_gracefulStopReg_port4__read = - dmaReadCntrl4SQ_gracefulStopReg_port2__read ; - assign dmaReadCntrl4SQ_gracefulStopReg_EN_port4__write = 1'b0 ; - assign dmaReadCntrl4SQ_gracefulStopReg_port4__write_1 = 1'b0 ; - assign dmaReadCntrl4SQ_cancelReg_port0__read = dmaReadCntrl4SQ_cancelReg ; - assign dmaReadCntrl4SQ_cancelReg_EN_port0__write = - CAN_FIRE_RL_cancelDmaReadSQ ; - assign dmaReadCntrl4SQ_cancelReg_port0__write_1 = 1'd1 ; - assign dmaReadCntrl4SQ_cancelReg_port1__read = - CAN_FIRE_RL_cancelDmaReadSQ || dmaReadCntrl4SQ_cancelReg ; - assign dmaReadCntrl4SQ_cancelReg_EN_port1__write = cntrl_stateReg == 4'd0 ; - assign dmaReadCntrl4SQ_cancelReg_port1__write_1 = 1'd0 ; - assign dmaReadCntrl4SQ_cancelReg_port2__read = - cntrl_stateReg != 4'd0 && dmaReadCntrl4SQ_cancelReg_port1__read ; - assign dmaReadCntrl4SQ_cancelReg_EN_port2__write = 1'b0 ; - assign dmaReadCntrl4SQ_cancelReg_port2__write_1 = 1'b0 ; - assign dmaReadCntrl4SQ_cancelReg_port3__read = - dmaReadCntrl4SQ_cancelReg_port2__read ; - assign dmaReadCntrl4SQ_cancelReg_EN_port3__write = 1'b0 ; - assign dmaReadCntrl4SQ_cancelReg_port3__write_1 = 1'b0 ; - assign dmaReadCntrl4SQ_cancelReg_port4__read = - dmaReadCntrl4SQ_cancelReg_port2__read ; - assign dmaReadCntrl4SQ_cancelReg_EN_port4__write = 1'b0 ; - assign dmaReadCntrl4SQ_cancelReg_port4__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_pushReg_port0__read = - sq_pendingWorkReqBuf_pushReg ; - assign sq_pendingWorkReqBuf_pushReg_EN_port0__write = - CAN_FIRE_RL_sq_pendingWorkReq2Q_mkConnectionGetPut ; - assign sq_pendingWorkReqBuf_pushReg_port0__write_1 = - { 1'd1, sq_reqGenSQ_pendingWorkReqOutQ_D_OUT } ; - assign sq_pendingWorkReqBuf_pushReg_port1__read = - CAN_FIRE_RL_sq_pendingWorkReq2Q_mkConnectionGetPut ? - sq_pendingWorkReqBuf_pushReg_port0__write_1 : - sq_pendingWorkReqBuf_pushReg ; - assign sq_pendingWorkReqBuf_pushReg_EN_port1__write = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_pushReg_port1__write_1 = - 680'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; - assign sq_pendingWorkReqBuf_pushReg_port2__read = - sq_pendingWorkReqBuf_pushReg_EN_port1__write ? - 680'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - sq_pendingWorkReqBuf_pushReg_port1__read ; - assign sq_pendingWorkReqBuf_pushReg_EN_port2__write = 1'b0 ; - assign sq_pendingWorkReqBuf_pushReg_port2__write_1 = 680'h0 ; - assign sq_pendingWorkReqBuf_pushReg_port3__read = - sq_pendingWorkReqBuf_pushReg_port2__read ; - assign sq_pendingWorkReqBuf_pushReg_EN_port3__write = 1'b0 ; - assign sq_pendingWorkReqBuf_pushReg_port3__write_1 = 680'h0 ; - assign sq_pendingWorkReqBuf_pushReg_port4__read = - sq_pendingWorkReqBuf_pushReg_port2__read ; - assign sq_pendingWorkReqBuf_pushReg_EN_port4__write = 1'b0 ; - assign sq_pendingWorkReqBuf_pushReg_port4__write_1 = 680'h0 ; - assign sq_pendingWorkReqBuf_popReg_port0__read = - sq_pendingWorkReqBuf_popReg ; - assign sq_pendingWorkReqBuf_popReg_EN_port0__write = - WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg || - WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign sq_pendingWorkReqBuf_popReg_port0__write_1 = 1'd1 ; - assign sq_pendingWorkReqBuf_popReg_port1__read = - sq_pendingWorkReqBuf_popReg_EN_port0__write ? - 1'd1 : - sq_pendingWorkReqBuf_popReg ; - assign sq_pendingWorkReqBuf_popReg_EN_port1__write = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_popReg_port1__write_1 = 1'd0 ; - assign sq_pendingWorkReqBuf_popReg_port2__read = - !sq_pendingWorkReqBuf_popReg_EN_port1__write && - sq_pendingWorkReqBuf_popReg_port1__read ; - assign sq_pendingWorkReqBuf_popReg_EN_port2__write = 1'b0 ; - assign sq_pendingWorkReqBuf_popReg_port2__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_popReg_port3__read = - sq_pendingWorkReqBuf_popReg_port2__read ; - assign sq_pendingWorkReqBuf_popReg_EN_port3__write = 1'b0 ; - assign sq_pendingWorkReqBuf_popReg_port3__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_popReg_port4__read = - sq_pendingWorkReqBuf_popReg_port2__read ; - assign sq_pendingWorkReqBuf_popReg_EN_port4__write = 1'b0 ; - assign sq_pendingWorkReqBuf_popReg_port4__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_clearReg_port0__read = - sq_pendingWorkReqBuf_clearReg ; - assign sq_pendingWorkReqBuf_clearReg_EN_port0__write = - WILL_FIRE_RL_sq_resetAndClear || - WILL_FIRE_RL_sq_retryHandler_resetAndClear ; - assign sq_pendingWorkReqBuf_clearReg_port0__write_1 = 1'd1 ; - assign sq_pendingWorkReqBuf_clearReg_port1__read = - CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_clearReg_EN_port1__write = - CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_clearReg_port1__write_1 = 1'd0 ; - assign sq_pendingWorkReqBuf_clearReg_port2__read = - !CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll && - CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_clearReg_EN_port2__write = 1'b0 ; - assign sq_pendingWorkReqBuf_clearReg_port2__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_clearReg_port3__read = - sq_pendingWorkReqBuf_clearReg_port2__read ; - assign sq_pendingWorkReqBuf_clearReg_EN_port3__write = 1'b0 ; - assign sq_pendingWorkReqBuf_clearReg_port3__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_clearReg_port4__read = - sq_pendingWorkReqBuf_clearReg_port2__read ; - assign sq_pendingWorkReqBuf_clearReg_EN_port4__write = 1'b0 ; - assign sq_pendingWorkReqBuf_clearReg_port4__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanStartReg_port0__read = - sq_pendingWorkReqBuf_preScanStartReg ; - assign sq_pendingWorkReqBuf_preScanStartReg_EN_port0__write = - WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_pendingWorkReqBuf_scanStateReg == 2'd0 ; - assign sq_pendingWorkReqBuf_preScanStartReg_port0__write_1 = 1'd1 ; - assign sq_pendingWorkReqBuf_preScanStartReg_port1__read = - sq_pendingWorkReqBuf_preScanStartReg_EN_port0__write || - sq_pendingWorkReqBuf_preScanStartReg ; - assign sq_pendingWorkReqBuf_preScanStartReg_EN_port1__write = - WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_preScanStartReg_port1__write_1 = 1'd0 ; - assign sq_pendingWorkReqBuf_preScanStartReg_port2__read = - !sq_pendingWorkReqBuf_preScanStartReg_EN_port1__write && - sq_pendingWorkReqBuf_preScanStartReg_port1__read ; - assign sq_pendingWorkReqBuf_preScanStartReg_EN_port2__write = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanStartReg_port2__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanStartReg_port3__read = - sq_pendingWorkReqBuf_preScanStartReg_port2__read ; - assign sq_pendingWorkReqBuf_preScanStartReg_EN_port3__write = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanStartReg_port3__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanStartReg_port4__read = - sq_pendingWorkReqBuf_preScanStartReg_port2__read ; - assign sq_pendingWorkReqBuf_preScanStartReg_EN_port4__write = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanStartReg_port4__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStartReg_port0__read = - sq_pendingWorkReqBuf_scanStartReg ; - assign sq_pendingWorkReqBuf_scanStartReg_EN_port0__write = - CAN_FIRE_RL_sq_retryHandler_startRetry ; - assign sq_pendingWorkReqBuf_scanStartReg_port0__write_1 = 1'd1 ; - assign sq_pendingWorkReqBuf_scanStartReg_port1__read = - CAN_FIRE_RL_sq_retryHandler_startRetry || - sq_pendingWorkReqBuf_scanStartReg ; - assign sq_pendingWorkReqBuf_scanStartReg_EN_port1__write = - WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_scanStartReg_port1__write_1 = 1'd0 ; - assign sq_pendingWorkReqBuf_scanStartReg_port2__read = - !sq_pendingWorkReqBuf_scanStartReg_EN_port1__write && - sq_pendingWorkReqBuf_scanStartReg_port1__read ; - assign sq_pendingWorkReqBuf_scanStartReg_EN_port2__write = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStartReg_port2__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStartReg_port3__read = - sq_pendingWorkReqBuf_scanStartReg_port2__read ; - assign sq_pendingWorkReqBuf_scanStartReg_EN_port3__write = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStartReg_port3__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStartReg_port4__read = - sq_pendingWorkReqBuf_scanStartReg_port2__read ; - assign sq_pendingWorkReqBuf_scanStartReg_EN_port4__write = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStartReg_port4__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStopReg_port0__read = - sq_pendingWorkReqBuf_scanStopReg ; - assign sq_pendingWorkReqBuf_scanStopReg_EN_port0__write = - CAN_FIRE_RL_sq_retryHandler_stopScanQ ; - assign sq_pendingWorkReqBuf_scanStopReg_port0__write_1 = 1'd1 ; - assign sq_pendingWorkReqBuf_scanStopReg_port1__read = - CAN_FIRE_RL_sq_retryHandler_stopScanQ || - sq_pendingWorkReqBuf_scanStopReg ; - assign sq_pendingWorkReqBuf_scanStopReg_EN_port1__write = - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_scanStopReg_port1__write_1 = 1'd0 ; - assign sq_pendingWorkReqBuf_scanStopReg_port2__read = - !sq_pendingWorkReqBuf_scanStopReg_EN_port1__write && - sq_pendingWorkReqBuf_scanStopReg_port1__read ; - assign sq_pendingWorkReqBuf_scanStopReg_EN_port2__write = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStopReg_port2__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStopReg_port3__read = - sq_pendingWorkReqBuf_scanStopReg_port2__read ; - assign sq_pendingWorkReqBuf_scanStopReg_EN_port3__write = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStopReg_port3__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStopReg_port4__read = - sq_pendingWorkReqBuf_scanStopReg_port2__read ; - assign sq_pendingWorkReqBuf_scanStopReg_EN_port4__write = 1'b0 ; - assign sq_pendingWorkReqBuf_scanStopReg_port4__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port0__read = - sq_pendingWorkReqBuf_preScanRestartReg ; - assign sq_pendingWorkReqBuf_preScanRestartReg_EN_port0__write = - WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_pendingWorkReqBuf_scanStateReg != 2'd0 ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port0__write_1 = 1'd1 ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port1__read = - sq_pendingWorkReqBuf_preScanRestartReg_EN_port0__write || - sq_pendingWorkReqBuf_preScanRestartReg ; - assign sq_pendingWorkReqBuf_preScanRestartReg_EN_port1__write = - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port1__write_1 = 1'd0 ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port2__read = - !sq_pendingWorkReqBuf_preScanRestartReg_EN_port1__write && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read ; - assign sq_pendingWorkReqBuf_preScanRestartReg_EN_port2__write = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port2__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port3__read = - sq_pendingWorkReqBuf_preScanRestartReg_port2__read ; - assign sq_pendingWorkReqBuf_preScanRestartReg_EN_port3__write = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port3__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port4__read = - sq_pendingWorkReqBuf_preScanRestartReg_port2__read ; - assign sq_pendingWorkReqBuf_preScanRestartReg_EN_port4__write = 1'b0 ; - assign sq_pendingWorkReqBuf_preScanRestartReg_port4__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_scanDoneReg_port0__read = - sq_pendingWorkReqBuf_scanDoneReg ; - assign sq_pendingWorkReqBuf_scanDoneReg_EN_port0__write = - CAN_FIRE_RL_sq_pendingWorkReqBuf_scanNext ; - assign sq_pendingWorkReqBuf_scanDoneReg_port0__write_1 = - sq_pendingWorkReqBuf_scanAlmostDoneReg ; - assign sq_pendingWorkReqBuf_scanDoneReg_port1__read = - CAN_FIRE_RL_sq_pendingWorkReqBuf_scanNext ? - sq_pendingWorkReqBuf_scanAlmostDoneReg : - sq_pendingWorkReqBuf_scanDoneReg ; - assign sq_pendingWorkReqBuf_scanDoneReg_EN_port1__write = - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - assign sq_pendingWorkReqBuf_scanDoneReg_port1__write_1 = 1'd0 ; - assign sq_pendingWorkReqBuf_scanDoneReg_port2__read = - !sq_pendingWorkReqBuf_scanDoneReg_EN_port1__write && - sq_pendingWorkReqBuf_scanDoneReg_port1__read ; - assign sq_pendingWorkReqBuf_scanDoneReg_EN_port2__write = 1'b0 ; - assign sq_pendingWorkReqBuf_scanDoneReg_port2__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_scanDoneReg_port3__read = - sq_pendingWorkReqBuf_scanDoneReg_port2__read ; - assign sq_pendingWorkReqBuf_scanDoneReg_EN_port3__write = 1'b0 ; - assign sq_pendingWorkReqBuf_scanDoneReg_port3__write_1 = 1'b0 ; - assign sq_pendingWorkReqBuf_scanDoneReg_port4__read = - sq_pendingWorkReqBuf_scanDoneReg_port2__read ; - assign sq_pendingWorkReqBuf_scanDoneReg_EN_port4__write = 1'b0 ; - assign sq_pendingWorkReqBuf_scanDoneReg_port4__write_1 = 1'b0 ; - assign sq_retryHandler_retryCntrlStateReg_port0__read = - sq_retryHandler_retryCntrlStateReg ; - assign sq_retryHandler_retryCntrlStateReg_EN_port0__write = - WILL_FIRE_RL_sq_retryHandler_waitRetryFinish && - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - WILL_FIRE_RL_sq_retryHandler_resetAndClear || - WILL_FIRE_RL_sq_retryHandler_initRetry ; - assign sq_retryHandler_retryCntrlStateReg_port0__write_1 = - (MUX_sq_retryHandler_retryCntrlStateReg_port0__write_1__SEL_1 || - WILL_FIRE_RL_sq_retryHandler_resetAndClear) ? - 2'd0 : - 2'd3 ; - assign sq_retryHandler_retryCntrlStateReg_port1__read = - sq_retryHandler_retryCntrlStateReg_EN_port0__write ? - sq_retryHandler_retryCntrlStateReg_port0__write_1 : - sq_retryHandler_retryCntrlStateReg ; - assign sq_retryHandler_retryCntrlStateReg_EN_port1__write = - MUX_sq_retryHandler_pauseRetryHandleReg_write_1__SEL_1 ; - assign sq_retryHandler_retryCntrlStateReg_port1__write_1 = - IF_IF_sq_retryHandler_updateRetryCntQ_first__3_ETC___d1388 ? - 2'd1 : - 2'd2 ; - assign sq_retryHandler_retryCntrlStateReg_port2__read = - MUX_sq_retryHandler_pauseRetryHandleReg_write_1__SEL_1 ? - sq_retryHandler_retryCntrlStateReg_port1__write_1 : - sq_retryHandler_retryCntrlStateReg_port1__read ; - assign sq_retryHandler_retryCntrlStateReg_EN_port2__write = 1'b0 ; - assign sq_retryHandler_retryCntrlStateReg_port2__write_1 = 2'h0 ; - assign sq_retryHandler_retryCntrlStateReg_port3__read = - sq_retryHandler_retryCntrlStateReg_port2__read ; - assign sq_retryHandler_retryCntrlStateReg_EN_port3__write = 1'b0 ; - assign sq_retryHandler_retryCntrlStateReg_port3__write_1 = 2'h0 ; - assign sq_retryHandler_retryCntrlStateReg_port4__read = - sq_retryHandler_retryCntrlStateReg_port2__read ; - assign sq_retryHandler_retryCntrlStateReg_EN_port4__write = 1'b0 ; - assign sq_retryHandler_retryCntrlStateReg_port4__write_1 = 2'h0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port0__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port0__write = - cntrl_stateReg == 4'd0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port0__write_1 = - 9'd256 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read = - (cntrl_stateReg == 4'd0) ? - 9'd256 : - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port1__write = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_write ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__write_1 = - 9'd170 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port2__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read[8] ? - 9'd170 : - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port2__write = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port2__write_1 = - 9'h0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port3__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port2__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port3__write = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port3__write_1 = - 9'h0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port4__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port2__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN_port4__write = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port4__write_1 = - 9'h0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port0__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port0__write = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_increment ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port0__write_1 = - 1'd1 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__read = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_increment || - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port1__write = - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr || - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read[8] ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__write_1 = - 1'd0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port2__read = - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port1__write && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port2__write = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port2__write_1 = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port3__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port2__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port3__write = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port3__write_1 = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port4__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port2__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN_port4__write = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port4__write_1 = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port0__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port0__write = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrement ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port0__write_1 = - 1'd1 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__read = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrement || - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port1__write = - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr || - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read[8] ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__write_1 = - 1'd0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port2__read = - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port1__write && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port2__write = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port2__write_1 = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port3__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port2__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port3__write = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port3__write_1 = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port4__read = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port2__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN_port4__write = - 1'b0 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port4__write_1 = - 1'b0 ; - assign sq_respHandleSQ_hasInternalErrReg_port0__read = - sq_respHandleSQ_hasInternalErrReg ; - assign sq_respHandleSQ_hasInternalErrReg_EN_port0__write = - WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 || - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear ; - assign sq_respHandleSQ_hasInternalErrReg_port0__write_1 = - MUX_sq_respHandleSQ_hasInternalErrReg_port0__write_1__SEL_1 ; - assign sq_respHandleSQ_hasInternalErrReg_port1__read = - sq_respHandleSQ_hasInternalErrReg_EN_port0__write ? - MUX_sq_respHandleSQ_hasInternalErrReg_port0__write_1__SEL_1 : - sq_respHandleSQ_hasInternalErrReg ; - assign sq_respHandleSQ_hasInternalErrReg_EN_port1__write = - CAN_FIRE_RL_sq_respHandleSQ_canonicalize ; - assign sq_respHandleSQ_hasInternalErrReg_port1__write_1 = 1'd0 ; - assign sq_respHandleSQ_hasInternalErrReg_port2__read = - !CAN_FIRE_RL_sq_respHandleSQ_canonicalize && - sq_respHandleSQ_hasInternalErrReg_port1__read ; - assign sq_respHandleSQ_hasInternalErrReg_EN_port2__write = 1'b0 ; - assign sq_respHandleSQ_hasInternalErrReg_port2__write_1 = 1'b0 ; - assign sq_respHandleSQ_hasInternalErrReg_port3__read = - sq_respHandleSQ_hasInternalErrReg_port2__read ; - assign sq_respHandleSQ_hasInternalErrReg_EN_port3__write = 1'b0 ; - assign sq_respHandleSQ_hasInternalErrReg_port3__write_1 = 1'b0 ; - assign sq_respHandleSQ_hasInternalErrReg_port4__read = - sq_respHandleSQ_hasInternalErrReg_port2__read ; - assign sq_respHandleSQ_hasInternalErrReg_EN_port4__write = 1'b0 ; - assign sq_respHandleSQ_hasInternalErrReg_port4__write_1 = 1'b0 ; - assign sq_respHandleSQ_hasTimeOutErrReg_port0__read = - sq_respHandleSQ_hasTimeOutErrReg ; - assign sq_respHandleSQ_hasTimeOutErrReg_EN_port0__write = - WILL_FIRE_RL_sq_respHandleSQ_checkTimeOutErr && - sq_retryHandler_timeOutNotificationQ_D_OUT || - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear || - WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign sq_respHandleSQ_hasTimeOutErrReg_port0__write_1 = - MUX_sq_respHandleSQ_hasTimeOutErrReg_port0__write_1__SEL_1 ; - assign sq_respHandleSQ_hasTimeOutErrReg_port1__read = - sq_respHandleSQ_hasTimeOutErrReg_EN_port0__write ? - MUX_sq_respHandleSQ_hasTimeOutErrReg_port0__write_1__SEL_1 : - sq_respHandleSQ_hasTimeOutErrReg ; - assign sq_respHandleSQ_hasTimeOutErrReg_EN_port1__write = 1'b0 ; - assign sq_respHandleSQ_hasTimeOutErrReg_port1__write_1 = 1'b0 ; - assign sq_respHandleSQ_hasTimeOutErrReg_port2__read = - sq_respHandleSQ_hasTimeOutErrReg_port1__read ; - assign sq_respHandleSQ_hasTimeOutErrReg_EN_port2__write = 1'b0 ; - assign sq_respHandleSQ_hasTimeOutErrReg_port2__write_1 = 1'b0 ; - assign sq_respHandleSQ_hasTimeOutErrReg_port3__read = - sq_respHandleSQ_hasTimeOutErrReg_port1__read ; - assign sq_respHandleSQ_hasTimeOutErrReg_EN_port3__write = 1'b0 ; - assign sq_respHandleSQ_hasTimeOutErrReg_port3__write_1 = 1'b0 ; - assign sq_respHandleSQ_hasTimeOutErrReg_port4__read = - sq_respHandleSQ_hasTimeOutErrReg_port1__read ; - assign sq_respHandleSQ_hasTimeOutErrReg_EN_port4__write = 1'b0 ; - assign sq_respHandleSQ_hasTimeOutErrReg_port4__write_1 = 1'b0 ; - - // register cntrl_dqpnReg - assign cntrl_dqpnReg_D_IN = cntrl_reqQ_D_OUT[125:102] ; - assign cntrl_dqpnReg_EN = - WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd2 ; - - // register cntrl_epsnReg - assign cntrl_epsnReg_D_IN = cntrl_epsnReg_port2__read ; - assign cntrl_epsnReg_EN = 1'b1 ; - - // register cntrl_errFlushDoneReg - assign cntrl_errFlushDoneReg_D_IN = !WILL_FIRE_RL_errTrigger ; - assign cntrl_errFlushDoneReg_EN = - WILL_FIRE_RL_errTrigger || WILL_FIRE_RL_waitGracefulStop ; - - // register cntrl_maxRetryCntReg - assign cntrl_maxRetryCntReg_D_IN = cntrl_reqQ_D_OUT[10:8] ; - assign cntrl_maxRetryCntReg_EN = MUX_cntrl_npsnReg_write_1__SEL_1 ; - - // register cntrl_maxRnrCntReg - assign cntrl_maxRnrCntReg_D_IN = cntrl_reqQ_D_OUT[7:5] ; - assign cntrl_maxRnrCntReg_EN = MUX_cntrl_npsnReg_write_1__SEL_1 ; - - // register cntrl_maxTimeOutReg - assign cntrl_maxTimeOutReg_D_IN = cntrl_reqQ_D_OUT[15:11] ; - assign cntrl_maxTimeOutReg_EN = MUX_cntrl_npsnReg_write_1__SEL_1 ; - - // register cntrl_minRnrTimerReg - assign cntrl_minRnrTimerReg_D_IN = cntrl_reqQ_D_OUT[20:16] ; - assign cntrl_minRnrTimerReg_EN = - WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd2 ; - - // register cntrl_nextStateReg - assign cntrl_nextStateReg_D_IN = 5'd10 ; - assign cntrl_nextStateReg_EN = 1'b1 ; - - // register cntrl_npsnReg - assign cntrl_npsnReg_D_IN = - MUX_cntrl_npsnReg_write_1__SEL_1 ? - cntrl_reqQ_D_OUT[149:126] : - nextPktSeqNum__h56056 ; - assign cntrl_npsnReg_EN = - WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd2 || - WILL_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq && - sq_reqGenSQ_workReqPsnQ_D_OUT[4] ; - - // register cntrl_pendingDestReadAtomicReqNumReg - assign cntrl_pendingDestReadAtomicReqNumReg_D_IN = cntrl_reqQ_D_OUT[28:21] ; - assign cntrl_pendingDestReadAtomicReqNumReg_EN = - WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd2 ; - - // register cntrl_pendingReadAtomicReqNumReg - assign cntrl_pendingReadAtomicReqNumReg_D_IN = cntrl_reqQ_D_OUT[36:29] ; - assign cntrl_pendingReadAtomicReqNumReg_EN = - MUX_cntrl_npsnReg_write_1__SEL_1 ; - - // register cntrl_pendingRecvReqNumReg - assign cntrl_pendingRecvReqNumReg_D_IN = 8'd4 ; - assign cntrl_pendingRecvReqNumReg_EN = cntrl_stateReg == 4'd0 ; - - // register cntrl_pendingWorkReqNumReg - assign cntrl_pendingWorkReqNumReg_D_IN = 8'd4 ; - assign cntrl_pendingWorkReqNumReg_EN = cntrl_stateReg == 4'd0 ; - - // register cntrl_pkeyReg - assign cntrl_pkeyReg_D_IN = cntrl_reqQ_D_OUT[53:38] ; - assign cntrl_pkeyReg_EN = - WILL_FIRE_RL_cntrl_onCreate && - cntrl_reqQ_D_OUT[300:299] == 2'd2 ; - - // register cntrl_pmtuReg - assign cntrl_pmtuReg_D_IN = cntrl_reqQ_D_OUT[208:206] ; - assign cntrl_pmtuReg_EN = - WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd2 ; - - // register cntrl_preReqOpCodeReg - assign cntrl_preReqOpCodeReg_D_IN = cntrl_preReqOpCodeReg_port2__read ; - assign cntrl_preReqOpCodeReg_EN = 1'b1 ; - - // register cntrl_preStateReg - assign cntrl_preStateReg_D_IN = cntrl_stateReg ; - assign cntrl_preStateReg_EN = 1'd1 ; - - // register cntrl_qkeyReg - assign cntrl_qkeyReg_D_IN = 32'h0 ; - assign cntrl_qkeyReg_EN = 1'b0 ; - - // register cntrl_qpAccessFlagsReg - assign cntrl_qpAccessFlagsReg_D_IN = cntrl_reqQ_D_OUT[101:94] ; - assign cntrl_qpAccessFlagsReg_EN = - WILL_FIRE_RL_cntrl_onCreate && - cntrl_reqQ_D_OUT[300:299] == 2'd2 ; - - // register cntrl_qpDestroyReg - assign cntrl_qpDestroyReg_D_IN = cntrl_qpDestroyReg ; - assign cntrl_qpDestroyReg_EN = 1'b1 ; - - // register cntrl_setStateErrReg - assign cntrl_setStateErrReg_D_IN = 1'd0 ; - assign cntrl_setStateErrReg_EN = 1'b1 ; - - // register cntrl_sqSigAllReg - assign cntrl_sqSigAllReg_D_IN = cntrl_reqQ_D_OUT[0] ; - assign cntrl_sqSigAllReg_EN = CAN_FIRE_RL_cntrl_onReset ; - - // register cntrl_sqTypeReg - assign cntrl_sqTypeReg_D_IN = - (cntrl_reqQ_D_OUT[4:1] == 4'd10) ? 4'd9 : cntrl_reqQ_D_OUT[4:1] ; - assign cntrl_sqTypeReg_EN = CAN_FIRE_RL_cntrl_onReset ; - - // register cntrl_sqpnReg - assign cntrl_sqpnReg_D_IN = cntrl_reqQ_D_OUT[266:243] ; - assign cntrl_sqpnReg_EN = CAN_FIRE_RL_cntrl_onReset ; - - // register cntrl_stateReg - assign cntrl_stateReg_D_IN = - cntrl_setStateErrReg_port1__read ? - 4'd6 : - (cntrl_nextStateReg_port1__read[4] ? - cntrl_nextStateReg_port1__read[3:0] : - cntrl_stateReg) ; - assign cntrl_stateReg_EN = 1'd1 ; - - // register dmaReadCntrl4SQ_addrChunkSrv_busyReg - always@(WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp or - MUX_dmaReadCntrl4SQ_addrChunkSrv_busyReg_write_1__VAL_1 or - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear or - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp: - dmaReadCntrl4SQ_addrChunkSrv_busyReg_D_IN = - MUX_dmaReadCntrl4SQ_addrChunkSrv_busyReg_write_1__VAL_1; - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear: - dmaReadCntrl4SQ_addrChunkSrv_busyReg_D_IN = 1'd0; - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq: - dmaReadCntrl4SQ_addrChunkSrv_busyReg_D_IN = 1'd1; - default: dmaReadCntrl4SQ_addrChunkSrv_busyReg_D_IN = - 1'b0 /* unspecified value */ ; - endcase - end - assign dmaReadCntrl4SQ_addrChunkSrv_busyReg_EN = - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp || - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear || - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ; - - // register dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg - assign dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_D_IN = - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ? - dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[98:35] : - MUX_dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_write_1__VAL_2 ; - assign dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_EN = - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq || - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp ; - - // register dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg - always@(dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT) - begin - case (dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[2:0]) - 3'd1: dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_D_IN = 13'd256; - 3'd2: dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_D_IN = 13'd512; - 3'd3: dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_D_IN = 13'd1024; - 3'd4: dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_D_IN = 13'd2048; - default: dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_D_IN = 13'd4096; - endcase - end - assign dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_EN = - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ; - - // register dmaReadCntrl4SQ_addrChunkSrv_isFirstReg - assign dmaReadCntrl4SQ_addrChunkSrv_isFirstReg_D_IN = - !MUX_dmaReadCntrl4SQ_addrChunkSrv_isFirstReg_write_1__SEL_1 ; - assign dmaReadCntrl4SQ_addrChunkSrv_isFirstReg_EN = - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp || - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_resetAndClear || - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ; - - // register dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg - assign dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg_D_IN = - !pmtuResidue__h9230[11] && pmtuResidue__h9230[10:9] == 2'd0 && - !pmtuResidue__h9230[8] && - pmtuResidue__h9230[7:6] == 2'd0 && - !pmtuResidue__h9230[5] && - pmtuResidue__h9230[4:3] == 2'd0 && - !pmtuResidue__h9230[2] && - pmtuResidue__h9230[1:0] == 2'd0 ; - assign dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg_EN = - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ; - - // register dmaReadCntrl4SQ_addrChunkSrv_pktNumReg - assign dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_D_IN = - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ? - MUX_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_write_1__VAL_1 : - MUX_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_write_1__VAL_2 ; - assign dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_EN = - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq || - WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp ; - - // register dmaReadCntrl4SQ_addrChunkSrv_pmtuReg - assign dmaReadCntrl4SQ_addrChunkSrv_pmtuReg_D_IN = - dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[2:0] ; - assign dmaReadCntrl4SQ_addrChunkSrv_pmtuReg_EN = - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ; - - // register dmaReadCntrl4SQ_addrChunkSrv_residueReg - assign dmaReadCntrl4SQ_addrChunkSrv_residueReg_D_IN = pmtuResidue__h9230 ; - assign dmaReadCntrl4SQ_addrChunkSrv_residueReg_EN = - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ; - - // register dmaReadCntrl4SQ_cancelReg - assign dmaReadCntrl4SQ_cancelReg_D_IN = - dmaReadCntrl4SQ_cancelReg_port2__read ; - assign dmaReadCntrl4SQ_cancelReg_EN = 1'b1 ; - - // register dmaReadCntrl4SQ_gracefulStopReg - assign dmaReadCntrl4SQ_gracefulStopReg_D_IN = - dmaReadCntrl4SQ_gracefulStopReg_port2__read ; - assign dmaReadCntrl4SQ_gracefulStopReg_EN = 1'b1 ; - - // register payloadGenerator4SQ_isNormalStateReg - assign payloadGenerator4SQ_isNormalStateReg_D_IN = - !WILL_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding || - !dmaReadCntrl4SQ_respQ_D_OUT[292] ; - assign payloadGenerator4SQ_isNormalStateReg_EN = - WILL_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding || - WILL_FIRE_RL_payloadGenerator4SQ_resetAndClear ; - - // register payloadGenerator4SQ_payloadBufQ_rCache - assign payloadGenerator4SQ_payloadBufQ_rCache_D_IN = - { 1'd1, - payloadGenerator4SQ_payloadBufQ_rWrPtr, - x__read_data__h12578, - x__read_byteEn__h12579, - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding && - payloadGenerator4SQ_payloadBufQ_wDataIn_wget[1], - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding && - payloadGenerator4SQ_payloadBufQ_wDataIn_wget[0] } ; - assign payloadGenerator4SQ_payloadBufQ_rCache_EN = - cntrl_stateReg != 4'd0 && - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding ; - - // register payloadGenerator4SQ_payloadBufQ_rRdPtr - assign payloadGenerator4SQ_payloadBufQ_rRdPtr_D_IN = - (cntrl_stateReg == 4'd0) ? 10'd0 : x__h12913 ; - assign payloadGenerator4SQ_payloadBufQ_rRdPtr_EN = - cntrl_stateReg == 4'd0 || - CAN_FIRE_RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut ; - - // register payloadGenerator4SQ_payloadBufQ_rWrPtr - assign payloadGenerator4SQ_payloadBufQ_rWrPtr_D_IN = - (cntrl_stateReg == 4'd0) ? 10'd0 : x__h12662 ; - assign payloadGenerator4SQ_payloadBufQ_rWrPtr_EN = - cntrl_stateReg == 4'd0 || - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding ; - - // register rqDmaReadCancelReg - assign rqDmaReadCancelReg_D_IN = 1'd0 ; - assign rqDmaReadCancelReg_EN = cntrl_stateReg == 4'd0 ; - - // register rqDmaWriteCancelReg - assign rqDmaWriteCancelReg_D_IN = 1'd0 ; - assign rqDmaWriteCancelReg_EN = cntrl_stateReg == 4'd0 ; - - // register sqDmaReadCancelReg - assign sqDmaReadCancelReg_D_IN = !WILL_FIRE_RL_resetAndClear ; - assign sqDmaReadCancelReg_EN = - WILL_FIRE_RL_resetAndClear || WILL_FIRE_RL_cancelDmaReadSQ ; - - // register sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_D_IN = - MUX_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_write_1__SEL_1 ? - MUX_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_write_1__VAL_1 : - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read[7:0] ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_EN = - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrAndDecr && - (sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__read && - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__read || - !sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port1__read && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port1__read) || - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port1__read[8] ; - - // register sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_D_IN = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_port2__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN = 1'b1 ; - - // register sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_D_IN = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_port2__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN = 1'b1 ; - - // register sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_D_IN = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_port2__read ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN = 1'b1 ; - - // register sq_pendingWorkReqBuf_clearReg - assign sq_pendingWorkReqBuf_clearReg_D_IN = - sq_pendingWorkReqBuf_clearReg_port2__read ; - assign sq_pendingWorkReqBuf_clearReg_EN = 1'b1 ; - - // register sq_pendingWorkReqBuf_dataVec_0 - assign sq_pendingWorkReqBuf_dataVec_0_D_IN = - sq_pendingWorkReqBuf_pushReg_port1__read[678:0] ; - assign sq_pendingWorkReqBuf_dataVec_0_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize && - sq_pendingWorkReqBuf_enqPtrReg == 2'd0 && - sq_pendingWorkReqBuf_pushReg_port1__read[679] ; - - // register sq_pendingWorkReqBuf_dataVec_1 - assign sq_pendingWorkReqBuf_dataVec_1_D_IN = - sq_pendingWorkReqBuf_pushReg_port1__read[678:0] ; - assign sq_pendingWorkReqBuf_dataVec_1_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize && - sq_pendingWorkReqBuf_enqPtrReg == 2'd1 && - sq_pendingWorkReqBuf_pushReg_port1__read[679] ; - - // register sq_pendingWorkReqBuf_dataVec_2 - assign sq_pendingWorkReqBuf_dataVec_2_D_IN = - sq_pendingWorkReqBuf_pushReg_port1__read[678:0] ; - assign sq_pendingWorkReqBuf_dataVec_2_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize && - sq_pendingWorkReqBuf_enqPtrReg == 2'd2 && - sq_pendingWorkReqBuf_pushReg_port1__read[679] ; - - // register sq_pendingWorkReqBuf_dataVec_3 - assign sq_pendingWorkReqBuf_dataVec_3_D_IN = - sq_pendingWorkReqBuf_pushReg_port1__read[678:0] ; - assign sq_pendingWorkReqBuf_dataVec_3_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize && - sq_pendingWorkReqBuf_enqPtrReg == 2'd3 && - sq_pendingWorkReqBuf_pushReg_port1__read[679] ; - - // register sq_pendingWorkReqBuf_deqPtrReg - assign sq_pendingWorkReqBuf_deqPtrReg_D_IN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize ? - MUX_sq_pendingWorkReqBuf_deqPtrReg_write_1__VAL_1 : - 2'd0 ; - assign sq_pendingWorkReqBuf_deqPtrReg_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - - // register sq_pendingWorkReqBuf_emptyReg - assign sq_pendingWorkReqBuf_emptyReg_D_IN = - !WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize || - MUX_sq_pendingWorkReqBuf_emptyReg_write_1__VAL_1 ; - assign sq_pendingWorkReqBuf_emptyReg_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - - // register sq_pendingWorkReqBuf_enqPtrReg - assign sq_pendingWorkReqBuf_enqPtrReg_D_IN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize ? - MUX_sq_pendingWorkReqBuf_enqPtrReg_write_1__VAL_1 : - 2'd0 ; - assign sq_pendingWorkReqBuf_enqPtrReg_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - - // register sq_pendingWorkReqBuf_fullReg - assign sq_pendingWorkReqBuf_fullReg_D_IN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize && - MUX_sq_pendingWorkReqBuf_fullReg_write_1__VAL_1 ; - assign sq_pendingWorkReqBuf_fullReg_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - - // register sq_pendingWorkReqBuf_headReg - assign sq_pendingWorkReqBuf_headReg_D_IN = - MUX_sq_pendingWorkReqBuf_headReg_write_1__SEL_1 ? - 680'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - MUX_sq_pendingWorkReqBuf_headReg_write_1__VAL_2 ; - assign sq_pendingWorkReqBuf_headReg_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanNext || - WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode || - WILL_FIRE_RL_sq_retryHandler_modifyPartialRetryWR ; - - // register sq_pendingWorkReqBuf_popReg - assign sq_pendingWorkReqBuf_popReg_D_IN = - sq_pendingWorkReqBuf_popReg_port2__read ; - assign sq_pendingWorkReqBuf_popReg_EN = 1'b1 ; - - // register sq_pendingWorkReqBuf_preScanRestartReg - assign sq_pendingWorkReqBuf_preScanRestartReg_D_IN = - sq_pendingWorkReqBuf_preScanRestartReg_port2__read ; - assign sq_pendingWorkReqBuf_preScanRestartReg_EN = 1'b1 ; - - // register sq_pendingWorkReqBuf_preScanStartReg - assign sq_pendingWorkReqBuf_preScanStartReg_D_IN = - sq_pendingWorkReqBuf_preScanStartReg_port2__read ; - assign sq_pendingWorkReqBuf_preScanStartReg_EN = 1'b1 ; - - // register sq_pendingWorkReqBuf_pushReg - assign sq_pendingWorkReqBuf_pushReg_D_IN = - sq_pendingWorkReqBuf_pushReg_port2__read ; - assign sq_pendingWorkReqBuf_pushReg_EN = 1'b1 ; - - // register sq_pendingWorkReqBuf_scanAlmostDoneReg - assign sq_pendingWorkReqBuf_scanAlmostDoneReg_D_IN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode ? - MUX_sq_pendingWorkReqBuf_scanAlmostDoneReg_write_1__VAL_1 : - MUX_sq_pendingWorkReqBuf_scanAlmostDoneReg_write_1__VAL_2 ; - assign sq_pendingWorkReqBuf_scanAlmostDoneReg_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode || - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanNext ; - - // register sq_pendingWorkReqBuf_scanDoneReg - assign sq_pendingWorkReqBuf_scanDoneReg_D_IN = - sq_pendingWorkReqBuf_scanDoneReg_port2__read ; - assign sq_pendingWorkReqBuf_scanDoneReg_EN = 1'b1 ; - - // register sq_pendingWorkReqBuf_scanPtrReg - assign sq_pendingWorkReqBuf_scanPtrReg_D_IN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode ? - sq_pendingWorkReqBuf_deqPtrReg : - MUX_sq_pendingWorkReqBuf_scanPtrReg_write_1__VAL_2 ; - assign sq_pendingWorkReqBuf_scanPtrReg_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode || - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanNext ; - - // register sq_pendingWorkReqBuf_scanStartReg - assign sq_pendingWorkReqBuf_scanStartReg_D_IN = - sq_pendingWorkReqBuf_scanStartReg_port2__read ; - assign sq_pendingWorkReqBuf_scanStartReg_EN = 1'b1 ; - - // register sq_pendingWorkReqBuf_scanStateReg - always@(MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_1 or - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_2 or - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_3 or - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__VAL_3 or - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll) - begin - case (1'b1) // synopsys parallel_case - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_1: - sq_pendingWorkReqBuf_scanStateReg_D_IN = 2'd1; - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_2: - sq_pendingWorkReqBuf_scanStateReg_D_IN = 2'd2; - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__SEL_3: - sq_pendingWorkReqBuf_scanStateReg_D_IN = - MUX_sq_pendingWorkReqBuf_scanStateReg_write_1__VAL_3; - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll: - sq_pendingWorkReqBuf_scanStateReg_D_IN = 2'd0; - default: sq_pendingWorkReqBuf_scanStateReg_D_IN = - 2'b10 /* unspecified value */ ; - endcase - end - assign sq_pendingWorkReqBuf_scanStateReg_EN = - WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read || - WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_scanStartReg_port1__read || - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - (sq_pendingWorkReqBuf_scanStopReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read || - sq_pendingWorkReqBuf_scanDoneReg_port1__read) || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - - // register sq_pendingWorkReqBuf_scanStopReg - assign sq_pendingWorkReqBuf_scanStopReg_D_IN = - sq_pendingWorkReqBuf_scanStopReg_port2__read ; - assign sq_pendingWorkReqBuf_scanStopReg_EN = 1'b1 ; - - // register sq_reqGenSQ_curPsnReg - assign sq_reqGenSQ_curPsnReg_D_IN = curPSN__h61636 + 24'd1 ; - assign sq_reqGenSQ_curPsnReg_EN = CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - - // register sq_reqGenSQ_isFirstOrOnlyReqPktReg - assign sq_reqGenSQ_isFirstOrOnlyReqPktReg_D_IN = - !WILL_FIRE_RL_sq_reqGenSQ_countReqPkt || - MUX_sq_reqGenSQ_isFirstOrOnlyReqPktReg_write_1__VAL_1 ; - assign sq_reqGenSQ_isFirstOrOnlyReqPktReg_EN = - WILL_FIRE_RL_sq_reqGenSQ_countReqPkt || - WILL_FIRE_RL_sq_reqGenSQ_resetAndClear ; - - // register sq_reqGenSQ_isNormalStateReg - assign sq_reqGenSQ_isNormalStateReg_D_IN = - !MUX_sq_reqGenSQ_isNormalStateReg_write_1__SEL_1 ; - assign sq_reqGenSQ_isNormalStateReg_EN = - WILL_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp && - (sq_reqGenSQ_reqHeaderGenQ_D_OUT[26] && - sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] || - !sq_reqGenSQ_reqHeaderGenQ_D_OUT[620]) || - WILL_FIRE_RL_sq_reqGenSQ_resetAndClear ; - - // register sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg_D_IN = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader && - MUX_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg_write_1__VAL_1 ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg_EN = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_resetAndClear ; - - // register sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg_D_IN = - { leftShiftHeaderData__h47318, - leftShiftHeaderByteEn__h47319, - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1770 } ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg_EN = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader && - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1734 && - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1737 != - 2'd1 ; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_D_IN = - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__SEL_1 ? - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__VAL_1 : - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__VAL_2 ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_EN = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData ; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg_D_IN = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[1] ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg_EN = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData ; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg_D_IN = - { headerLastFragInvalidByteNum__h47982, 3'd0 } ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg_EN = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData ; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg_D_IN = - headerLastFragInvalidByteNum__h47982 ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg_EN = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData ; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg_D_IN = - headerLastFragValidBitNum__h47980 ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg_EN = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData ; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg_D_IN = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[7:2] ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg_EN = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData ; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg_D_IN = - !MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_write_1__SEL_1 && - !WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg_EN = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData ; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_D_IN = - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_write_1__SEL_1 ? - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_write_1__VAL_1 : - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_OUT ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_EN = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData ; - - // register sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg - always@(MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_write_1__SEL_1 or - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_1 or - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__SEL_2 or - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_2 or - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData or - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_3 or - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__SEL_4) - begin - case (1'b1) // synopsys parallel_case - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_write_1__SEL_1: - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_D_IN = - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_1; - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__SEL_2: - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_D_IN = - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_2; - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData: - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_D_IN = - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__VAL_3; - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_write_1__SEL_4: - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_D_IN = - 2'd0; - default: sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_D_IN = - 2'b10 /* unspecified value */ ; - endcase - end - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_EN = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData && - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_OUT[0] || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_resetAndClear ; - - // register sq_reqGenSQ_remainingPktNumReg - assign sq_reqGenSQ_remainingPktNumReg_D_IN = - sq_reqGenSQ_isFirstOrOnlyReqPktReg ? - _theResult___snd__h61670 : - ((!sq_reqGenSQ_reqCountQ_D_OUT[5] && - sq_reqGenSQ_remainingPktNumReg != 25'd0) ? - remainingPktNum___1__h61739 : - sq_reqGenSQ_remainingPktNumReg) ; - assign sq_reqGenSQ_remainingPktNumReg_EN = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - - // register sq_respHandleSQ_errOccurredReg - assign sq_respHandleSQ_errOccurredReg_D_IN = - !WILL_FIRE_RL_sq_respHandleSQ_resetAndClear ; - assign sq_respHandleSQ_errOccurredReg_EN = - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear || - WILL_FIRE_RL_sq_respHandleSQ_canonicalize ; - - // register sq_respHandleSQ_hasInternalErrReg - assign sq_respHandleSQ_hasInternalErrReg_D_IN = - sq_respHandleSQ_hasInternalErrReg_port2__read ; - assign sq_respHandleSQ_hasInternalErrReg_EN = 1'b1 ; - - // register sq_respHandleSQ_hasTimeOutErrReg - assign sq_respHandleSQ_hasTimeOutErrReg_D_IN = - sq_respHandleSQ_hasTimeOutErrReg_port1__read ; - assign sq_respHandleSQ_hasTimeOutErrReg_EN = 1'b1 ; - - // register sq_respHandleSQ_nextReadRespWriteAddrReg - assign sq_respHandleSQ_nextReadRespWriteAddrReg_D_IN = 64'h0 ; - assign sq_respHandleSQ_nextReadRespWriteAddrReg_EN = 1'b0 ; - - // register sq_respHandleSQ_preRdmaOpCodeReg - assign sq_respHandleSQ_preRdmaOpCodeReg_D_IN = - MUX_sq_respHandleSQ_preRdmaOpCodeReg_write_1__SEL_1 ? - sq_respHandleSQ_pendingRespQ_D_OUT[141:137] : - 5'd17 ; - assign sq_respHandleSQ_preRdmaOpCodeReg_EN = - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - cntrl_stateReg != 4'd6 || - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear ; - - // register sq_respHandleSQ_preStageDeqPendingWorkReqReg - assign sq_respHandleSQ_preStageDeqPendingWorkReqReg_D_IN = - sq_respHandleSQ_preStagePktMetaDataReg[1] && - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4271 ; - assign sq_respHandleSQ_preStageDeqPendingWorkReqReg_EN = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - - // register sq_respHandleSQ_preStageDeqPktMetaDataReg - assign sq_respHandleSQ_preStageDeqPktMetaDataReg_D_IN = - !sq_respHandleSQ_preStagePktMetaDataReg[1] || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0100 ; - assign sq_respHandleSQ_preStageDeqPktMetaDataReg_EN = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - - // register sq_respHandleSQ_preStagePktMetaDataReg - assign sq_respHandleSQ_preStagePktMetaDataReg_D_IN = - respPktPipe_metaDataQ_D_OUT ; - assign sq_respHandleSQ_preStagePktMetaDataReg_EN = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - - // register sq_respHandleSQ_preStageReqPktInfoReg - assign sq_respHandleSQ_preStageReqPktInfoReg_D_IN = - { respPktPipe_metaDataQ_D_OUT[626:618], - 1'd0, - respPktPipe_metaDataQ_D_OUT[616:615], - 4'd0, - respPktPipe_metaDataQ_D_OUT[610:595], - 8'd0, - respPktPipe_metaDataQ_D_OUT[586:562], - 7'd0, - respPktPipe_metaDataQ_D_OUT[554:531], - 1'd0, - respPktPipe_metaDataQ_D_OUT[529:499], - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd0 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd6 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd13 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd4 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd5 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd23 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd10 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd11 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd12 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd19 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd20 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd16 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd17 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd18, - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd2 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd3 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd22 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd8 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd9 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd15 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd4 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd5 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd23 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd10 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd11 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd12 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd19 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd20 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd16 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd17 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd18, - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd13 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd14 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd15 || - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd16, - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd18, - 3'd0 } ; - assign sq_respHandleSQ_preStageReqPktInfoReg_EN = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - - // register sq_respHandleSQ_preStageRespAndWorkReqRelationReg - assign sq_respHandleSQ_preStageRespAndWorkReqRelationReg_D_IN = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521 == - 4'd4 || - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521 == - 4'd5 || - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521 == - 4'd6, - respPktPipe_metaDataQ_D_OUT[554:531] == value__h99966, - IF_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_ETC___d4106, - respPktPipe_metaDataQ_D_OUT[554:531] == value__h99939, - IF_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_ETC___d4116 } ; - assign sq_respHandleSQ_preStageRespAndWorkReqRelationReg_EN = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - - // register sq_respHandleSQ_preStageRespTypeReg - always@(respPktPipe_metaDataQ_D_OUT or - CASE_respPktPipe_metaDataQD_OUT_BITS_529_TO_5_ETC__q30) - begin - case (respPktPipe_metaDataQ_D_OUT[623:619]) - 5'd13, 5'd14, 5'd15, 5'd16, 5'd18: - sq_respHandleSQ_preStageRespTypeReg_D_IN = 2'd0; - 5'd17: - sq_respHandleSQ_preStageRespTypeReg_D_IN = - CASE_respPktPipe_metaDataQD_OUT_BITS_529_TO_5_ETC__q30; - default: sq_respHandleSQ_preStageRespTypeReg_D_IN = 2'd3; - endcase - end - assign sq_respHandleSQ_preStageRespTypeReg_EN = - CAN_FIRE_RL_sq_respHandleSQ_preBuildRespInfo ; - - // register sq_respHandleSQ_preStageStateReg - always@(MUX_sq_respHandleSQ_preStageStateReg_write_1__SEL_1 or - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo or - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo) - begin - case (1'b1) // synopsys parallel_case - MUX_sq_respHandleSQ_preStageStateReg_write_1__SEL_1: - sq_respHandleSQ_preStageStateReg_D_IN = 2'd0; - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo: - sq_respHandleSQ_preStageStateReg_D_IN = 2'd1; - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo: - sq_respHandleSQ_preStageStateReg_D_IN = 2'd2; - default: sq_respHandleSQ_preStageStateReg_D_IN = - 2'b10 /* unspecified value */ ; - endcase - end - assign sq_respHandleSQ_preStageStateReg_EN = - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear || - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload || - WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq || - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo || - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - - // register sq_respHandleSQ_preStageWorkCompReqTypeReg - assign sq_respHandleSQ_preStageWorkCompReqTypeReg_D_IN = - sq_respHandleSQ_preStagePktMetaDataReg[1] ? - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q31 : - 2'd0 ; - assign sq_respHandleSQ_preStageWorkCompReqTypeReg_EN = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - - // register sq_respHandleSQ_preStageWorkReqAckTypeReg - assign sq_respHandleSQ_preStageWorkReqAckTypeReg_D_IN = - sq_respHandleSQ_preStagePktMetaDataReg[1] ? - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q32 : - 4'd10 ; - assign sq_respHandleSQ_preStageWorkReqAckTypeReg_EN = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - - // register sq_respHandleSQ_recvErrRespReg - assign sq_respHandleSQ_recvErrRespReg_D_IN = - !WILL_FIRE_RL_sq_respHandleSQ_resetAndClear ; - assign sq_respHandleSQ_recvErrRespReg_EN = - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - (sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd2 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd5 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd10) || - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3 && - IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 || - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear ; - - // register sq_respHandleSQ_recvRetryRespReg - assign sq_respHandleSQ_recvRetryRespReg_D_IN = - !WILL_FIRE_RL_sq_respHandleSQ_resetAndClear && - !MUX_sq_respHandleSQ_recvRetryRespReg_write_1__SEL_2 ; - assign sq_respHandleSQ_recvRetryRespReg_EN = - WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_retryHandler_retryHandleStateReg == 3'd7 || - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - (sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd1 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd4 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd7) || - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear ; - - // register sq_respHandleSQ_remainingReadRespLenReg - assign sq_respHandleSQ_remainingReadRespLenReg_D_IN = 32'h0 ; - assign sq_respHandleSQ_remainingReadRespLenReg_EN = 1'b0 ; - - // register sq_respHandleSQ_retryFlushReg - assign sq_respHandleSQ_retryFlushReg_D_IN = - !WILL_FIRE_RL_sq_respHandleSQ_resetAndClear && - !MUX_sq_respHandleSQ_recvRetryRespReg_write_1__SEL_2 ; - assign sq_respHandleSQ_retryFlushReg_EN = - WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_retryHandler_retryHandleStateReg == 3'd7 || - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - (sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd1 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd4 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd7) || - WILL_FIRE_RL_sq_respHandleSQ_resetAndClear ; - - // register sq_respHandleSQ_retryResetReqReg - assign sq_respHandleSQ_retryResetReqReg_D_IN = - sq_respHandleSQ_preStagePktMetaDataReg[1] && - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4271 ; - assign sq_respHandleSQ_retryResetReqReg_EN = - CAN_FIRE_RL_sq_respHandleSQ_preProcRespInfo ; - - // register sq_retryHandler_disableRetryCntReg - assign sq_retryHandler_disableRetryCntReg_D_IN = - MUX_sq_retryHandler_disableRetryCntReg_write_1__SEL_1 ? - cntrl_maxRetryCntReg == 3'd7 : - cntrl_maxRetryCntReg == 3'd7 ; - assign sq_retryHandler_disableRetryCntReg_EN = - WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - !sq_retryHandler_updateRetryCntQ_D_OUT[3] || - WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer ; - - // register sq_retryHandler_disableTimeOutReg - assign sq_retryHandler_disableTimeOutReg_D_IN = - MUX_sq_retryHandler_disableTimeOutReg_write_1__SEL_1 ? - cntrl_maxTimeOutReg == 5'd0 : - cntrl_maxTimeOutReg == 5'd0 ; - assign sq_retryHandler_disableTimeOutReg_EN = - WILL_FIRE_RL_sq_retryHandler_checkTimeOut && - sq_retryHandler_resetTimeOutQ_notEmpty__176_OR_ETC___d1209 || - WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer ; - - // register sq_retryHandler_isRnrWaitCntZeroReg - assign sq_retryHandler_isRnrWaitCntZeroReg_D_IN = - MUX_sq_retryHandler_isRnrWaitCntZeroReg_write_1__SEL_1 && - MUX_sq_retryHandler_isRnrWaitCntZeroReg_write_1__VAL_1 ; - assign sq_retryHandler_isRnrWaitCntZeroReg_EN = - WILL_FIRE_RL_sq_retryHandler_rnrWait && - !sq_retryHandler_isRnrWaitCntZeroReg || - WILL_FIRE_RL_sq_retryHandler_rnrCheck ; - - // register sq_retryHandler_isTimeOutCntHighPartZeroReg - assign sq_retryHandler_isTimeOutCntHighPartZeroReg_D_IN = - MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__SEL_1 && - MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__VAL_1 ; - assign sq_retryHandler_isTimeOutCntHighPartZeroReg_EN = - MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__SEL_1 || - WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer ; - - // register sq_retryHandler_isTimeOutCntLowPartZeroReg - assign sq_retryHandler_isTimeOutCntLowPartZeroReg_D_IN = - MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__SEL_1 && - MUX_sq_retryHandler_isTimeOutCntLowPartZeroReg_write_1__VAL_1 ; - assign sq_retryHandler_isTimeOutCntLowPartZeroReg_EN = - MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__SEL_1 || - WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer ; - - // register sq_retryHandler_pauseRetryHandleReg - assign sq_retryHandler_pauseRetryHandleReg_D_IN = - MUX_sq_retryHandler_pauseRetryHandleReg_write_1__SEL_1 ; - assign sq_retryHandler_pauseRetryHandleReg_EN = - WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] || - WILL_FIRE_RL_sq_retryHandler_initRetry || - WILL_FIRE_RL_sq_retryHandler_resetAndClear ; - - // register sq_retryHandler_psnDiffReg - assign sq_retryHandler_psnDiffReg_D_IN = x__h37628[23:0] ; - assign sq_retryHandler_psnDiffReg_EN = - CAN_FIRE_RL_sq_retryHandler_checkPartialRetry ; - - // register sq_retryHandler_retryCntReg - assign sq_retryHandler_retryCntReg_D_IN = - MUX_sq_retryHandler_retryCntReg_write_1__SEL_1 ? - MUX_sq_retryHandler_retryCntReg_write_1__VAL_1 : - cntrl_maxRetryCntReg ; - assign sq_retryHandler_retryCntReg_EN = - WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - IF_sq_retryHandler_updateRetryCntQ_first__309__ETC___d1340 || - WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer ; - - // register sq_retryHandler_retryCntrlStateReg - assign sq_retryHandler_retryCntrlStateReg_D_IN = - sq_retryHandler_retryCntrlStateReg_port2__read ; - assign sq_retryHandler_retryCntrlStateReg_EN = 1'b1 ; - - // register sq_retryHandler_retryHandleStateReg - always@(WILL_FIRE_RL_sq_retryHandler_startPreRetry or - MUX_sq_retryHandler_retryHandleStateReg_write_1__VAL_3 or - MUX_sq_retryHandler_retryHandleStateReg_write_1__SEL_2 or - WILL_FIRE_RL_sq_retryHandler_resetAndClear or - WILL_FIRE_RL_sq_retryHandler_initRetry or - WILL_FIRE_RL_sq_retryHandler_rnrCheck or - MUX_sq_retryHandler_retryHandleStateReg_write_1__SEL_1 or - WILL_FIRE_RL_sq_retryHandler_checkPartialRetry or - WILL_FIRE_RL_sq_retryHandler_modifyPartialRetryWR or - WILL_FIRE_RL_sq_retryHandler_startRetry) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_sq_retryHandler_startPreRetry: - sq_retryHandler_retryHandleStateReg_D_IN = - MUX_sq_retryHandler_retryHandleStateReg_write_1__VAL_3; - MUX_sq_retryHandler_retryHandleStateReg_write_1__SEL_2 || - WILL_FIRE_RL_sq_retryHandler_resetAndClear: - sq_retryHandler_retryHandleStateReg_D_IN = 3'd0; - WILL_FIRE_RL_sq_retryHandler_initRetry: - sq_retryHandler_retryHandleStateReg_D_IN = 3'd1; - WILL_FIRE_RL_sq_retryHandler_rnrCheck: - sq_retryHandler_retryHandleStateReg_D_IN = 3'd3; - MUX_sq_retryHandler_retryHandleStateReg_write_1__SEL_1: - sq_retryHandler_retryHandleStateReg_D_IN = 3'd4; - WILL_FIRE_RL_sq_retryHandler_checkPartialRetry: - sq_retryHandler_retryHandleStateReg_D_IN = 3'd5; - WILL_FIRE_RL_sq_retryHandler_modifyPartialRetryWR: - sq_retryHandler_retryHandleStateReg_D_IN = 3'd6; - WILL_FIRE_RL_sq_retryHandler_startRetry: - sq_retryHandler_retryHandleStateReg_D_IN = 3'd7; - default: sq_retryHandler_retryHandleStateReg_D_IN = - 3'b010 /* unspecified value */ ; - endcase - end - assign sq_retryHandler_retryHandleStateReg_EN = - WILL_FIRE_RL_sq_retryHandler_rnrWait && - sq_retryHandler_isRnrWaitCntZeroReg || - WILL_FIRE_RL_sq_retryHandler_waitRetryDone && - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - WILL_FIRE_RL_sq_retryHandler_startPreRetry || - WILL_FIRE_RL_sq_retryHandler_resetAndClear || - WILL_FIRE_RL_sq_retryHandler_initRetry || - WILL_FIRE_RL_sq_retryHandler_rnrCheck || - WILL_FIRE_RL_sq_retryHandler_checkPartialRetry || - WILL_FIRE_RL_sq_retryHandler_modifyPartialRetryWR || - WILL_FIRE_RL_sq_retryHandler_startRetry ; - - // register sq_retryHandler_retryReasonReg - assign sq_retryHandler_retryReasonReg_D_IN = - sq_retryHandler_retryActionQ_D_OUT[8:6] ; - assign sq_retryHandler_retryReasonReg_EN = - WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] ; - - // register sq_retryHandler_retryRnrTimerReg - assign sq_retryHandler_retryRnrTimerReg_D_IN = - sq_retryHandler_retryActionQ_D_OUT[4:0] ; - assign sq_retryHandler_retryRnrTimerReg_EN = - WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 ; - - // register sq_retryHandler_retryStartPsnReg - assign sq_retryHandler_retryStartPsnReg_D_IN = - sq_retryHandler_retryActionQ_D_OUT[32:9] ; - assign sq_retryHandler_retryStartPsnReg_EN = - WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] != 3'd4 ; - - // register sq_retryHandler_retryWorkReqIdReg - assign sq_retryHandler_retryWorkReqIdReg_D_IN = - sq_retryHandler_retryActionQ_D_OUT[96:33] ; - assign sq_retryHandler_retryWorkReqIdReg_EN = - WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] != 3'd4 ; - - // register sq_retryHandler_rnrCntReg - assign sq_retryHandler_rnrCntReg_D_IN = - MUX_sq_retryHandler_rnrCntReg_write_1__SEL_1 ? - MUX_sq_retryHandler_rnrCntReg_write_1__VAL_1 : - cntrl_maxRnrCntReg ; - assign sq_retryHandler_rnrCntReg_EN = - MUX_sq_retryHandler_rnrCntReg_write_1__SEL_1 || - WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer ; - - // register sq_retryHandler_rnrWaitCntReg - assign sq_retryHandler_rnrWaitCntReg_D_IN = - MUX_sq_retryHandler_isRnrWaitCntZeroReg_write_1__SEL_1 ? - MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_1 : - MUX_sq_retryHandler_rnrWaitCntReg_write_1__VAL_2 ; - assign sq_retryHandler_rnrWaitCntReg_EN = - WILL_FIRE_RL_sq_retryHandler_rnrWait && - !sq_retryHandler_isRnrWaitCntZeroReg || - WILL_FIRE_RL_sq_retryHandler_rnrCheck ; - - // register sq_retryHandler_timeOutCntReg - assign sq_retryHandler_timeOutCntReg_D_IN = - MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__SEL_1 ? - MUX_sq_retryHandler_timeOutCntReg_write_1__VAL_1 : - x__h32835 ; - assign sq_retryHandler_timeOutCntReg_EN = - MUX_sq_retryHandler_isTimeOutCntHighPartZeroReg_write_1__SEL_1 || - WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer ; - - // register sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg - assign sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_D_IN = - sq_workCompGenSQ_genWorkCompQ_D_OUT[856:793] ; - assign sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_EN = - MUX_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_write_1__SEL_2 ; - - // register sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg - assign sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_D_IN = - !MUX_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_write_1__SEL_1 && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] == 2'd1 ; - assign sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_EN = - WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg || - WILL_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ && - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1] ; - - // register sq_workCompGenSQ_workCompGenStateReg - always@(MUX_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_write_1__SEL_2 or - WILL_FIRE_RL_sq_workCompGenSQ_resetAndClear or - WILL_FIRE_RL_sq_workCompGenSQ_start) - begin - case (1'b1) // synopsys parallel_case - MUX_sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_write_1__SEL_2: - sq_workCompGenSQ_workCompGenStateReg_D_IN = 2'd2; - WILL_FIRE_RL_sq_workCompGenSQ_resetAndClear: - sq_workCompGenSQ_workCompGenStateReg_D_IN = 2'd0; - WILL_FIRE_RL_sq_workCompGenSQ_start: - sq_workCompGenSQ_workCompGenStateReg_D_IN = 2'd1; - default: sq_workCompGenSQ_workCompGenStateReg_D_IN = - 2'b10 /* unspecified value */ ; - endcase - end - assign sq_workCompGenSQ_workCompGenStateReg_EN = - WILL_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ && - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1] || - WILL_FIRE_RL_sq_workCompGenSQ_resetAndClear || - WILL_FIRE_RL_sq_workCompGenSQ_start ; - - // submodule cntrl_reqQ - assign cntrl_reqQ_D_IN = srvPortQP_request_put ; - assign cntrl_reqQ_ENQ = EN_srvPortQP_request_put ; - assign cntrl_reqQ_DEQ = - WILL_FIRE_RL_cntrl_onERR || WILL_FIRE_RL_cntrl_onSQD || - WILL_FIRE_RL_cntrl_onRTS || - WILL_FIRE_RL_cntrl_onRTR || - WILL_FIRE_RL_cntrl_onINIT || - WILL_FIRE_RL_cntrl_onCreate || - WILL_FIRE_RL_cntrl_onReset ; - assign cntrl_reqQ_CLR = 1'b0 ; - - // submodule cntrl_respQ - always@(WILL_FIRE_RL_cntrl_onReset or - MUX_cntrl_respQ_enq_1__VAL_1 or - WILL_FIRE_RL_cntrl_onCreate or - MUX_cntrl_respQ_enq_1__VAL_2 or - WILL_FIRE_RL_cntrl_onINIT or - MUX_cntrl_respQ_enq_1__VAL_3 or - WILL_FIRE_RL_cntrl_onRTR or - MUX_cntrl_respQ_enq_1__VAL_4 or - WILL_FIRE_RL_cntrl_onRTS or - MUX_cntrl_respQ_enq_1__VAL_5 or - WILL_FIRE_RL_cntrl_onSQD or - MUX_cntrl_respQ_enq_1__VAL_6 or - WILL_FIRE_RL_cntrl_onERR or MUX_cntrl_respQ_enq_1__VAL_7) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_cntrl_onReset: - cntrl_respQ_D_IN = MUX_cntrl_respQ_enq_1__VAL_1; - WILL_FIRE_RL_cntrl_onCreate: - cntrl_respQ_D_IN = MUX_cntrl_respQ_enq_1__VAL_2; - WILL_FIRE_RL_cntrl_onINIT: - cntrl_respQ_D_IN = MUX_cntrl_respQ_enq_1__VAL_3; - WILL_FIRE_RL_cntrl_onRTR: - cntrl_respQ_D_IN = MUX_cntrl_respQ_enq_1__VAL_4; - WILL_FIRE_RL_cntrl_onRTS: - cntrl_respQ_D_IN = MUX_cntrl_respQ_enq_1__VAL_5; - WILL_FIRE_RL_cntrl_onSQD: - cntrl_respQ_D_IN = MUX_cntrl_respQ_enq_1__VAL_6; - WILL_FIRE_RL_cntrl_onERR: - cntrl_respQ_D_IN = MUX_cntrl_respQ_enq_1__VAL_7; - default: cntrl_respQ_D_IN = - 274'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign cntrl_respQ_ENQ = - WILL_FIRE_RL_cntrl_onReset || WILL_FIRE_RL_cntrl_onCreate || - WILL_FIRE_RL_cntrl_onINIT || - WILL_FIRE_RL_cntrl_onRTR || - WILL_FIRE_RL_cntrl_onRTS || - WILL_FIRE_RL_cntrl_onSQD || - WILL_FIRE_RL_cntrl_onERR ; - assign cntrl_respQ_DEQ = EN_srvPortQP_response_get ; - assign cntrl_respQ_CLR = 1'b0 ; - - // submodule cntrl_restoreQ - assign cntrl_restoreQ_D_IN = 29'h0 ; - assign cntrl_restoreQ_ENQ = 1'b0 ; - assign cntrl_restoreQ_DEQ = CAN_FIRE_RL_cntrl_restore ; - assign cntrl_restoreQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule dmaReadCntrl4SQ_addrChunkSrv_reqQ - assign dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_IN = - { dmaReadCntrl4SQ_reqQ_D_OUT[99:4], - dmaReadCntrl4SQ_reqQ_D_OUT[2:0] } ; - assign dmaReadCntrl4SQ_addrChunkSrv_reqQ_ENQ = - CAN_FIRE_RL_dmaReadCntrl4SQ_recvReq ; - assign dmaReadCntrl4SQ_addrChunkSrv_reqQ_DEQ = - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq ; - assign dmaReadCntrl4SQ_addrChunkSrv_reqQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule dmaReadCntrl4SQ_addrChunkSrv_respQ - assign dmaReadCntrl4SQ_addrChunkSrv_respQ_D_IN = - { dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg, - addrChunkResp_chunkLen__h10586, - dmaReadCntrl4SQ_addrChunkSrv_isFirstReg, - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_77_BITS_ETC___d366 && - NOT_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_77__ETC___d376 } ; - assign dmaReadCntrl4SQ_addrChunkSrv_respQ_ENQ = - CAN_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_genResp ; - assign dmaReadCntrl4SQ_addrChunkSrv_respQ_DEQ = - CAN_FIRE_RL_dmaReadCntrl4SQ_issueDmaReq ; - assign dmaReadCntrl4SQ_addrChunkSrv_respQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule dmaReadCntrl4SQ_pendingDmaCntrlReqQ - assign dmaReadCntrl4SQ_pendingDmaCntrlReqQ_D_IN = - dmaReadCntrl4SQ_reqQ_D_OUT ; - assign dmaReadCntrl4SQ_pendingDmaCntrlReqQ_ENQ = - CAN_FIRE_RL_dmaReadCntrl4SQ_recvReq ; - assign dmaReadCntrl4SQ_pendingDmaCntrlReqQ_DEQ = - WILL_FIRE_RL_dmaReadCntrl4SQ_issueDmaReq && - dmaReadCntrl4SQ_addrChunkSrv_respQ_D_OUT[0] ; - assign dmaReadCntrl4SQ_pendingDmaCntrlReqQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule dmaReadCntrl4SQ_pendingDmaReadReqQ - assign dmaReadCntrl4SQ_pendingDmaReadReqQ_D_IN = - { dmaReadCntrl4SQ_pendingDmaCntrlReqQ_D_OUT[191:100], - dmaReadCntrl4SQ_addrChunkSrv_respQ_D_OUT[78:2], - dmaReadCntrl4SQ_pendingDmaCntrlReqQ_D_OUT[3], - dmaReadCntrl4SQ_addrChunkSrv_respQ_D_OUT[1:0] } ; - assign dmaReadCntrl4SQ_pendingDmaReadReqQ_ENQ = - CAN_FIRE_RL_dmaReadCntrl4SQ_issueDmaReq ; - assign dmaReadCntrl4SQ_pendingDmaReadReqQ_DEQ = - WILL_FIRE_RL_dmaReadCntrl4SQ_recvDmaResp && - dmaReadProxy4SQ_respQ_D_OUT[0] ; - assign dmaReadCntrl4SQ_pendingDmaReadReqQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule dmaReadCntrl4SQ_reqQ - assign dmaReadCntrl4SQ_reqQ_D_IN = - { payloadGenerator4SQ_payloadGenReqQ_D_OUT[192:4], - payloadGenerator4SQ_payloadGenReqQ_D_OUT[2:0] } ; - assign dmaReadCntrl4SQ_reqQ_ENQ = - CAN_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq ; - assign dmaReadCntrl4SQ_reqQ_DEQ = CAN_FIRE_RL_dmaReadCntrl4SQ_recvReq ; - assign dmaReadCntrl4SQ_reqQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule dmaReadCntrl4SQ_respQ - assign dmaReadCntrl4SQ_respQ_D_IN = - { dmaReadProxy4SQ_respQ_D_OUT, - dmaReadProxy4SQ_respQ_D_OUT[1] && - dmaReadCntrl4SQ_pendingDmaReadReqQ_D_OUT[1], - dmaReadProxy4SQ_respQ_D_OUT[0] && - dmaReadCntrl4SQ_pendingDmaReadReqQ_D_OUT[0] } ; - assign dmaReadCntrl4SQ_respQ_ENQ = CAN_FIRE_RL_dmaReadCntrl4SQ_recvDmaResp ; - assign dmaReadCntrl4SQ_respQ_DEQ = - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding ; - assign dmaReadCntrl4SQ_respQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule dmaReadProxy4SQ_reqQ - assign dmaReadProxy4SQ_reqQ_D_IN = - { dmaReadCntrl4SQ_pendingDmaCntrlReqQ_D_OUT[191:100], - dmaReadCntrl4SQ_addrChunkSrv_respQ_D_OUT[78:2], - dmaReadCntrl4SQ_pendingDmaCntrlReqQ_D_OUT[3] } ; - assign dmaReadProxy4SQ_reqQ_ENQ = CAN_FIRE_RL_dmaReadCntrl4SQ_issueDmaReq ; - assign dmaReadProxy4SQ_reqQ_DEQ = EN_dmaReadClt4SQ_request_get ; - assign dmaReadProxy4SQ_reqQ_CLR = 1'b0 ; - - // submodule dmaReadProxy4SQ_respQ - assign dmaReadProxy4SQ_respQ_D_IN = dmaReadClt4SQ_response_put ; - assign dmaReadProxy4SQ_respQ_ENQ = EN_dmaReadClt4SQ_response_put ; - assign dmaReadProxy4SQ_respQ_DEQ = CAN_FIRE_RL_dmaReadCntrl4SQ_recvDmaResp ; - assign dmaReadProxy4SQ_respQ_CLR = 1'b0 ; - - // submodule payloadGenerator4SQ_bramQ2PipeOut_postBramQ - assign payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_IN = - payloadGenerator4SQ_payloadBufQ_wDataOut_wget ; - assign payloadGenerator4SQ_bramQ2PipeOut_postBramQ_ENQ = - CAN_FIRE_RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut ; - assign payloadGenerator4SQ_bramQ2PipeOut_postBramQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData ; - assign payloadGenerator4SQ_bramQ2PipeOut_postBramQ_CLR = - cntrl_stateReg == 4'd0 ; - - // submodule payloadGenerator4SQ_payloadBufQ_memory - assign payloadGenerator4SQ_payloadBufQ_memory_ADDRA = - payloadGenerator4SQ_payloadBufQ_rWrPtr[8:0] ; - assign payloadGenerator4SQ_payloadBufQ_memory_ADDRB = - CAN_FIRE_RL_payloadGenerator4SQ_bramQ2PipeOut_mkConnectionGetPut ? - x__h12913[8:0] : - payloadGenerator4SQ_payloadBufQ_rRdPtr[8:0] ; - assign payloadGenerator4SQ_payloadBufQ_memory_DIA = - { x__read_data__h12578, - x__read_byteEn__h12579, - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding && - payloadGenerator4SQ_payloadBufQ_wDataIn_wget[1], - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding && - payloadGenerator4SQ_payloadBufQ_wDataIn_wget[0] } ; - assign payloadGenerator4SQ_payloadBufQ_memory_DIB = - 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - assign payloadGenerator4SQ_payloadBufQ_memory_WEA = - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding ; - assign payloadGenerator4SQ_payloadBufQ_memory_WEB = 1'd0 ; - assign payloadGenerator4SQ_payloadBufQ_memory_ENA = cntrl_stateReg != 4'd0 ; - assign payloadGenerator4SQ_payloadBufQ_memory_ENB = cntrl_stateReg != 4'd0 ; - - // submodule payloadGenerator4SQ_payloadGenReqQ - assign payloadGenerator4SQ_payloadGenReqQ_D_IN = - { 4'd5, - cntrl_sqpnReg, - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[719:656], - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[518:455], - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[550:519], - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[454], - 1'd1, - cntrl_pmtuReg } ; - assign payloadGenerator4SQ_payloadGenReqQ_ENQ = - WILL_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq && - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] ; - assign payloadGenerator4SQ_payloadGenReqQ_DEQ = - CAN_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq ; - assign payloadGenerator4SQ_payloadGenReqQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule payloadGenerator4SQ_payloadGenRespQ - assign payloadGenerator4SQ_payloadGenRespQ_D_IN = - { payloadGenerator4SQ_pendingGenReqQ_D_OUT[43], - dmaReadCntrl4SQ_respQ_D_OUT[292] } ; - assign payloadGenerator4SQ_payloadGenRespQ_ENQ = - WILL_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding && - (dmaReadCntrl4SQ_respQ_D_OUT[2] || - dmaReadCntrl4SQ_respQ_D_OUT[292]) ; - assign payloadGenerator4SQ_payloadGenRespQ_DEQ = - WILL_FIRE_RL_sq_reqGenSQ_genReqHeader && - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] && - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545] ; - assign payloadGenerator4SQ_payloadGenRespQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule payloadGenerator4SQ_pendingGenReqQ - assign payloadGenerator4SQ_pendingGenReqQ_D_IN = - { payloadGenerator4SQ_payloadGenReqQ_D_OUT, - x__h14424, - x__h16825 } ; - assign payloadGenerator4SQ_pendingGenReqQ_ENQ = - CAN_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq ; - assign payloadGenerator4SQ_pendingGenReqQ_DEQ = - WILL_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding && - dmaReadCntrl4SQ_respQ_D_OUT[0] ; - assign payloadGenerator4SQ_pendingGenReqQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule respPktPipe_metaDataQ - assign respPktPipe_metaDataQ_D_IN = respPktPipeIn_pktMetaData_put ; - assign respPktPipe_metaDataQ_ENQ = EN_respPktPipeIn_pktMetaData_put ; - assign respPktPipe_metaDataQ_DEQ = - WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPktMetaDataReg || - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - respPktPipe_metaDataQ_EMPTY_N || - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp || - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp ; - assign respPktPipe_metaDataQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule respPktPipe_payloadQ - assign respPktPipe_payloadQ_D_IN = respPktPipeIn_payload_put ; - assign respPktPipe_payloadQ_ENQ = EN_respPktPipeIn_payload_put ; - assign respPktPipe_payloadQ_DEQ = 1'b0 ; - assign respPktPipe_payloadQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ - assign sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_D_IN = - { workReqQ_D_OUT, 78'h1555554AAAAAA2AAAAA8 } ; - assign sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_ENQ = - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_genPendingWR || - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_flushWR ; - assign sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_DEQ = - CAN_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn2 ; - assign sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_CLR = - cntrl_stateReg == 4'd0 ; - - // submodule sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_D_IN = 1'd1 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_ENQ = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_DEQ = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrement ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrQ_CLR = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_write ; - - // submodule sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_D_IN = 1'd1 ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_ENQ = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_genPendingWR ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_DEQ = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_increment ; - assign sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrQ_CLR = - CAN_FIRE_RL_sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_write ; - - // submodule sq_pendingWorkReqBuf_itemCnt - assign sq_pendingWorkReqBuf_itemCnt_DATA_A = 3'd1 ; - assign sq_pendingWorkReqBuf_itemCnt_DATA_B = 3'd7 ; - assign sq_pendingWorkReqBuf_itemCnt_DATA_C = 3'h0 ; - assign sq_pendingWorkReqBuf_itemCnt_DATA_F = 3'd0 ; - assign sq_pendingWorkReqBuf_itemCnt_ADDA = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize && - sq_pendingWorkReqBuf_pushReg_port1__read[679] && - !sq_pendingWorkReqBuf_popReg_port1__read ; - assign sq_pendingWorkReqBuf_itemCnt_ADDB = - WILL_FIRE_RL_sq_pendingWorkReqBuf_canonicalize && - !sq_pendingWorkReqBuf_pushReg_port1__read[679] && - sq_pendingWorkReqBuf_popReg_port1__read ; - assign sq_pendingWorkReqBuf_itemCnt_SETC = 1'b0 ; - assign sq_pendingWorkReqBuf_itemCnt_SETF = - CAN_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - - // submodule sq_pendingWorkReqBuf_scanCnt - assign sq_pendingWorkReqBuf_scanCnt_DATA_A = 3'h0 ; - assign sq_pendingWorkReqBuf_scanCnt_DATA_B = 3'd7 ; - assign sq_pendingWorkReqBuf_scanCnt_DATA_C = 3'h0 ; - assign sq_pendingWorkReqBuf_scanCnt_DATA_F = - sq_pendingWorkReqBuf_itemCnt_Q_OUT ; - assign sq_pendingWorkReqBuf_scanCnt_ADDA = 1'b0 ; - assign sq_pendingWorkReqBuf_scanCnt_ADDB = - CAN_FIRE_RL_sq_pendingWorkReqBuf_scanNext ; - assign sq_pendingWorkReqBuf_scanCnt_SETC = 1'b0 ; - assign sq_pendingWorkReqBuf_scanCnt_SETF = - CAN_FIRE_RL_sq_pendingWorkReqBuf_preScanMode ; - - // submodule sq_pendingWorkReqBuf_scanOutQ - assign sq_pendingWorkReqBuf_scanOutQ_D_IN = - sq_pendingWorkReqBuf_headReg[679] ? - sq_pendingWorkReqBuf_headReg[678:0] : - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d768, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d774, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d780, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d786, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d792, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d798, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d804, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d810, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d816, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d822, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d828, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d838, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d845, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d855, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d861, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d871, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d878, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d888, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d894, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d904, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d911, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d921, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d927, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d937, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d951, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d961, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d968, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d978, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d984, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d994, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1001, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1007 } ; - assign sq_pendingWorkReqBuf_scanOutQ_ENQ = - CAN_FIRE_RL_sq_pendingWorkReqBuf_scanNext ; - assign sq_pendingWorkReqBuf_scanOutQ_DEQ = - CAN_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn1 ; - assign sq_pendingWorkReqBuf_scanOutQ_CLR = - WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - (sq_pendingWorkReqBuf_scanStopReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) || - WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode || - WILL_FIRE_RL_sq_pendingWorkReqBuf_clearAll ; - - // submodule sq_pendingWorkReqPipeOut_pipeMuxOutQ - assign sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_IN = - WILL_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn1 ? - sq_pendingWorkReqBuf_scanOutQ_D_OUT : - sq_newPendingWorkReqPiptOut_newPendingWorkReqOutQ_D_OUT ; - assign sq_pendingWorkReqPipeOut_pipeMuxOutQ_ENQ = - WILL_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn1 || - WILL_FIRE_RL_sq_pendingWorkReqPipeOut_outputPipeIn2 ; - assign sq_pendingWorkReqPipeOut_pipeMuxOutQ_DEQ = - WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d2074 ; - assign sq_pendingWorkReqPipeOut_pipeMuxOutQ_CLR = 1'b0 ; - - // submodule sq_reqGenSQ_pendingReqHeaderQ - assign sq_reqGenSQ_pendingReqHeaderQ_D_IN = - { sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[685:7], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[4:0], - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3420, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686] } ; - assign sq_reqGenSQ_pendingReqHeaderQ_ENQ = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign sq_reqGenSQ_pendingReqHeaderQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign sq_reqGenSQ_pendingReqHeaderQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_pendingWorkReqOutQ - assign sq_reqGenSQ_pendingWorkReqOutQ_D_IN = - MUX_sq_reqGenSQ_pendingWorkReqOutQ_enq_1__SEL_1 ? - sq_reqGenSQ_workReqOutQ_D_OUT[683:5] : - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[719:41] ; - assign sq_reqGenSQ_pendingWorkReqOutQ_ENQ = - WILL_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq && - sq_reqGenSQ_workReqOutQ_D_OUT[4] && - sq_reqGenSQ_workReqOutQ_D_OUT[2] || - WILL_FIRE_RL_sq_reqGenSQ_errFlushWR && - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[2] && - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[1] ; - assign sq_reqGenSQ_pendingWorkReqOutQ_DEQ = - CAN_FIRE_RL_sq_pendingWorkReq2Q_mkConnectionGetPut ; - assign sq_reqGenSQ_pendingWorkReqOutQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_psnReqOutQ - assign sq_reqGenSQ_psnReqOutQ_D_IN = sq_reqGenSQ_reqHeaderGenQ_D_OUT[23:0] ; - assign sq_reqGenSQ_psnReqOutQ_ENQ = - WILL_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp && - sq_reqGenSQ_reqHeaderGenQ_D_OUT[620] && - (!sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] || - !sq_reqGenSQ_reqHeaderGenQ_D_OUT[26]) ; - assign sq_reqGenSQ_psnReqOutQ_DEQ = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_connect && - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_OUT[0] ; - assign sq_reqGenSQ_psnReqOutQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_IN = - { x__h47525[511:256], - x__h47528[63:32], - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg, - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1742 || - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1737 == - 2'd1 } ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_ENQ = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader && - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1734 ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_CLR = - cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_IN = - sq_reqGenSQ_reqHeaderOutQ_D_OUT[16:0] ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_ENQ = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader && - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_CLR = - cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_rdmaReqPipeOut_outputQ - assign sq_reqGenSQ_rdmaReqPipeOut_outputQ_D_IN = - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_OUT ; - assign sq_reqGenSQ_rdmaReqPipeOut_outputQ_ENQ = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_connect ; - assign sq_reqGenSQ_rdmaReqPipeOut_outputQ_DEQ = EN_rdmaReqPipeOut_deq ; - assign sq_reqGenSQ_rdmaReqPipeOut_outputQ_CLR = 1'b0 ; - - // submodule sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ - always@(MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__SEL_1 or - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT or - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData or - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__VAL_2 or - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag or - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__SEL_1: - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_IN = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT; - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData: - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_IN = - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__VAL_2; - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag: - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_IN = - MUX_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_enq_1__VAL_3; - default: sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_D_IN = - 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_ENQ = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - (!sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg || - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0]) || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputData || - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_extraLastFrag ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_connect ; - assign sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_CLR = - cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_reqCountQ - assign sq_reqGenSQ_reqCountQ_D_IN = sq_reqGenSQ_workReqCheckQ_D_OUT ; - assign sq_reqGenSQ_reqCountQ_ENQ = - WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - (!sq_reqGenSQ_workReqCheckQ_D_OUT[1] || - sq_reqGenSQ_workReqCheckQ_D_OUT[5]) ; - assign sq_reqGenSQ_reqCountQ_DEQ = - WILL_FIRE_RL_sq_reqGenSQ_countReqPkt && - (sq_reqGenSQ_reqCountQ_D_OUT[5] || - !sq_reqGenSQ_isFirstOrOnlyReqPktReg && - sq_reqGenSQ_remainingPktNumReg == 25'd0) ; - assign sq_reqGenSQ_reqCountQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_reqHeaderGenQ - assign sq_reqGenSQ_reqHeaderGenQ_D_IN = - { sq_reqGenSQ_pendingReqHeaderQ_D_OUT[1228:550], - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544:32], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[0], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[1], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[2], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[3], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[4], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[5], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[6], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[7], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[8], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[9], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[10], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[11], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[12], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[13], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[14], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[15], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[16], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[17], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[18], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[19], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[20], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[21], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[22], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[23], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[24], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[25], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[26], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[27], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[28], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[29], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[30], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[31], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[32], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[33], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[34], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[35], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[36], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[37], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[38], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[39], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[40], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[41], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[42], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[43], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[44], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[45], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[46], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[47], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[48], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[49], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[50], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[51], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[52], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[53], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[54], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[55], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[56], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[57], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[58], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[59], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[60], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[61], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[62], - _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443[63], - sq_reqGenSQ_pendingReqHeaderQ_first__424_BITS__ETC___d3563, - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[544] && - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[545], - payloadGenerator4SQ_payloadGenRespQ_D_OUT, - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[23:0] } ; - assign sq_reqGenSQ_reqHeaderGenQ_ENQ = - CAN_FIRE_RL_sq_reqGenSQ_genReqHeader ; - assign sq_reqGenSQ_reqHeaderGenQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp ; - assign sq_reqGenSQ_reqHeaderGenQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_reqHeaderOutQ - assign sq_reqGenSQ_reqHeaderOutQ_D_IN = - sq_reqGenSQ_reqHeaderGenQ_D_OUT[619:27] ; - assign sq_reqGenSQ_reqHeaderOutQ_ENQ = - WILL_FIRE_RL_sq_reqGenSQ_recvPayloadGenRespAndGenErrWorkComp && - sq_reqGenSQ_reqHeaderGenQ_D_OUT[620] && - (!sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] || - !sq_reqGenSQ_reqHeaderGenQ_D_OUT[26]) ; - assign sq_reqGenSQ_reqHeaderOutQ_DEQ = - WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_outputHeader && - (IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1742 || - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1737 == - 2'd1) ; - assign sq_reqGenSQ_reqHeaderOutQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_reqHeaderPrepareQ - assign sq_reqGenSQ_reqHeaderPrepareQ_D_IN = - { curPSN__h61636, - sq_reqGenSQ_reqCountQ_D_OUT[683:5], - sq_reqGenSQ_isFirstOrOnlyReqPktReg, - sq_reqGenSQ_reqCountQ_D_OUT[5] || - !sq_reqGenSQ_isFirstOrOnlyReqPktReg && - sq_reqGenSQ_remainingPktNumReg == 25'd0, - sq_reqGenSQ_reqCountQ_D_OUT[4:0] } ; - assign sq_reqGenSQ_reqHeaderPrepareQ_ENQ = - CAN_FIRE_RL_sq_reqGenSQ_countReqPkt ; - assign sq_reqGenSQ_reqHeaderPrepareQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen ; - assign sq_reqGenSQ_reqHeaderPrepareQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_workCompGenReqOutQ - assign sq_reqGenSQ_workCompGenReqOutQ_D_IN = - { sq_reqGenSQ_reqHeaderGenQ_D_OUT[1299:699], - 3'd1, - sq_reqGenSQ_reqHeaderGenQ_D_OUT[23:0], - 5'd2 } ; - assign sq_reqGenSQ_workCompGenReqOutQ_ENQ = - MUX_sq_reqGenSQ_isNormalStateReg_write_1__SEL_1 ; - assign sq_reqGenSQ_workCompGenReqOutQ_DEQ = - WILL_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ && - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N ; - assign sq_reqGenSQ_workCompGenReqOutQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_workReqCheckQ - assign sq_reqGenSQ_workReqCheckQ_D_IN = - { sq_reqGenSQ_workReqPsnQ_D_OUT[683:83], - sq_reqGenSQ_workReqPsnQ_first__498_BIT_4_499_O_ETC___d2558, - sq_reqGenSQ_workReqPsnQ_D_OUT[4:0] } ; - assign sq_reqGenSQ_workReqCheckQ_ENQ = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign sq_reqGenSQ_workReqCheckQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign sq_reqGenSQ_workReqCheckQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_workReqOutQ - assign sq_reqGenSQ_workReqOutQ_D_IN = sq_reqGenSQ_workReqCheckQ_D_OUT ; - assign sq_reqGenSQ_workReqOutQ_ENQ = - CAN_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq ; - assign sq_reqGenSQ_workReqOutQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq ; - assign sq_reqGenSQ_workReqOutQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_workReqPayloadGenQ - assign sq_reqGenSQ_workReqPayloadGenQ_D_IN = - { sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT, - x__h52242, - x__h52371, - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd1 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd2 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd3 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == - 4'd9) && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:508] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[507:506] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[505:504] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[503:502] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[501:500] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[499:498] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[497:496] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[495:494] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[493:492] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[491:490] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[489:488] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[487:486] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[485:484] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[483:482] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[481:480] != 2'd0 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[479:478] != 2'd0), - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[1], - cntrl_sqTypeReg == 4'd2 || cntrl_sqTypeReg == 4'd9, - cntrl_sqTypeReg == 4'd4 } ; - assign sq_reqGenSQ_workReqPayloadGenQ_ENQ = - WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d2074 ; - assign sq_reqGenSQ_workReqPayloadGenQ_DEQ = - WILL_FIRE_RL_sq_reqGenSQ_errFlushWR || - WILL_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign sq_reqGenSQ_workReqPayloadGenQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_workReqPktNumQ - assign sq_reqGenSQ_workReqPktNumQ_D_IN = - { sq_reqGenSQ_workReqPayloadGenQ_D_OUT[719:16], - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[2], - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[15:4] == 12'd0, - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[1:0], - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[3] } ; - assign sq_reqGenSQ_workReqPktNumQ_ENQ = - CAN_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq ; - assign sq_reqGenSQ_workReqPktNumQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign sq_reqGenSQ_workReqPktNumQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_reqGenSQ_workReqPsnQ - assign sq_reqGenSQ_workReqPsnQ_D_IN = - { sq_reqGenSQ_workReqPktNumQ_D_OUT[708:58], - sq_reqGenSQ_workReqPktNumQ_D_OUT[4] || - sq_reqGenSQ_workReqPktNumQ_D_OUT[57], - sq_reqGenSQ_workReqPktNumQ_D_OUT[4] ? - totalPktNum__h55209 : - sq_reqGenSQ_workReqPktNumQ_D_OUT[56:32], - sq_reqGenSQ_workReqPktNumQ_D_OUT[4] || - sq_reqGenSQ_workReqPktNumQ_D_OUT[31], - sq_reqGenSQ_workReqPktNumQ_D_OUT[4] ? - totalPktNum__h55209[24:23] == 2'd0 && - !totalPktNum__h55209[22] && - totalPktNum__h55209[21:20] == 2'd0 && - !totalPktNum__h55209[19] && - totalPktNum__h55209[18:17] == 2'd0 && - !totalPktNum__h55209[16] && - totalPktNum__h55209[15:14] == 2'd0 && - !totalPktNum__h55209[13] && - totalPktNum__h55209[12:11] == 2'd0 && - !totalPktNum__h55209[10] && - totalPktNum__h55209[9:8] == 2'd0 && - !totalPktNum__h55209[7] && - totalPktNum__h55209[6:5] == 2'd0 && - totalPktNum__h55209[4:3] == 2'd0 && - totalPktNum__h55209[2:1] == 2'd0 : - sq_reqGenSQ_workReqPktNumQ_D_OUT[30], - sq_reqGenSQ_workReqPktNumQ_D_OUT[4:0] } ; - assign sq_reqGenSQ_workReqPsnQ_ENQ = - CAN_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq ; - assign sq_reqGenSQ_workReqPsnQ_DEQ = - CAN_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq ; - assign sq_reqGenSQ_workReqPsnQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_incomingRespQ - always@(MUX_sq_respHandleSQ_incomingRespQ_enq_1__SEL_1 or - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_1 or - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp or - WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq or - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_3 or - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp or - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_4 or - WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq or - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_5) - begin - case (1'b1) // synopsys parallel_case - MUX_sq_respHandleSQ_incomingRespQ_enq_1__SEL_1: - sq_respHandleSQ_incomingRespQ_D_IN = - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_1; - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp: - sq_respHandleSQ_incomingRespQ_D_IN = - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_1; - WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq: - sq_respHandleSQ_incomingRespQ_D_IN = - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_3; - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp: - sq_respHandleSQ_incomingRespQ_D_IN = - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_4; - WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq: - sq_respHandleSQ_incomingRespQ_D_IN = - MUX_sq_respHandleSQ_incomingRespQ_enq_1__VAL_5; - default: sq_respHandleSQ_incomingRespQ_D_IN = - 1470'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign sq_respHandleSQ_incomingRespQ_ENQ = - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - respPktPipe_metaDataQ_EMPTY_N || - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp || - WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq || - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp || - WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq ; - assign sq_respHandleSQ_incomingRespQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign sq_respHandleSQ_incomingRespQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingAddrCalcQ - assign sq_respHandleSQ_pendingAddrCalcQ_D_IN = - { sq_respHandleSQ_pendingPermCheckQ_D_OUT[1475:139], - 1'd0, - sq_respHandleSQ_pendingPermCheckQ_D_OUT[137:136], - 4'd0, - sq_respHandleSQ_pendingPermCheckQ_D_OUT[131:116], - 8'd0, - sq_respHandleSQ_pendingPermCheckQ_D_OUT[107:83], - 7'd0, - sq_respHandleSQ_pendingPermCheckQ_D_OUT[75:52], - 1'd0, - sq_respHandleSQ_pendingPermCheckQ_D_OUT[50:1] } ; - assign sq_respHandleSQ_pendingAddrCalcQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp ; - assign sq_respHandleSQ_pendingAddrCalcQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - assign sq_respHandleSQ_pendingAddrCalcQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingDmaReqQ - assign sq_respHandleSQ_pendingDmaReqQ_D_IN = - { sq_respHandleSQ_pendingLenCheckQ_D_OUT[1572:236], - 1'd0, - sq_respHandleSQ_pendingLenCheckQ_D_OUT[234:233], - 4'd0, - sq_respHandleSQ_pendingLenCheckQ_D_OUT[228:213], - 8'd0, - sq_respHandleSQ_pendingLenCheckQ_D_OUT[204:180], - 7'd0, - sq_respHandleSQ_pendingLenCheckQ_D_OUT[172:149], - 1'd0, - sq_respHandleSQ_pendingLenCheckQ_D_OUT[147:98], - sq_respHandleSQ_pendingLenCheckQ_D_OUT[95:32] } ; - assign sq_respHandleSQ_pendingDmaReqQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen ; - assign sq_respHandleSQ_pendingDmaReqQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - assign sq_respHandleSQ_pendingDmaReqQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingLenCalcQ - assign sq_respHandleSQ_pendingLenCalcQ_D_IN = - { sq_respHandleSQ_pendingAddrCalcQ_D_OUT[1474:138], - 1'd0, - sq_respHandleSQ_pendingAddrCalcQ_D_OUT[136:135], - 4'd0, - sq_respHandleSQ_pendingAddrCalcQ_D_OUT[130:115], - 8'd0, - sq_respHandleSQ_pendingAddrCalcQ_D_OUT[106:82], - 7'd0, - sq_respHandleSQ_pendingAddrCalcQ_D_OUT[74:51], - 1'd0, - sq_respHandleSQ_pendingAddrCalcQ_D_OUT[49:0], - sq_respHandleSQ_nextReadRespWriteAddrReg } ; - assign sq_respHandleSQ_pendingLenCalcQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespAddr ; - assign sq_respHandleSQ_pendingLenCalcQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - assign sq_respHandleSQ_pendingLenCalcQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingLenCheckQ - assign sq_respHandleSQ_pendingLenCheckQ_D_IN = - { sq_respHandleSQ_pendingSpaceCalcQ_D_OUT[1604:268], - 1'd0, - sq_respHandleSQ_pendingSpaceCalcQ_D_OUT[266:265], - 4'd0, - sq_respHandleSQ_pendingSpaceCalcQ_D_OUT[260:245], - 8'd0, - sq_respHandleSQ_pendingSpaceCalcQ_D_OUT[236:212], - 7'd0, - sq_respHandleSQ_pendingSpaceCalcQ_D_OUT[204:181], - 1'd0, - sq_respHandleSQ_pendingSpaceCalcQ_D_OUT[179:130], - 2'd2, - sq_respHandleSQ_pendingSpaceCalcQ_D_OUT[127:32] } ; - assign sq_respHandleSQ_pendingLenCheckQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace ; - assign sq_respHandleSQ_pendingLenCheckQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_checkReadRespLen ; - assign sq_respHandleSQ_pendingLenCheckQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingPermCheckQ - assign sq_respHandleSQ_pendingPermCheckQ_D_IN = - { sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1469:133], - 1'd0, - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[131:130], - 4'd0, - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[125:110], - 8'd0, - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[101:77], - 7'd0, - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[69:46], - 1'd0, - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:9], - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd0 || - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q25, - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd0 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 || - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q27, - sq_respHandleSQ_pendingRetryCheckQ_first__949__ETC___d5187 } ; - assign sq_respHandleSQ_pendingPermCheckQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign sq_respHandleSQ_pendingPermCheckQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp ; - assign sq_respHandleSQ_pendingPermCheckQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingPermQueryQ - assign sq_respHandleSQ_pendingPermQueryQ_D_IN = - { sq_respHandleSQ_pendingRespQ_D_OUT[1472:136], - 1'd0, - sq_respHandleSQ_pendingRespQ_D_OUT[134:133], - 4'd0, - sq_respHandleSQ_pendingRespQ_D_OUT[128:113], - 8'd0, - sq_respHandleSQ_pendingRespQ_D_OUT[104:80], - 7'd0, - sq_respHandleSQ_pendingRespQ_D_OUT[72:49], - 1'd0, - sq_respHandleSQ_pendingRespQ_D_OUT[47:13], - (sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3) ? - IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 || - sq_respHandleSQ_pendingRespQ_D_OUT[12] : - sq_respHandleSQ_pendingRespQ_D_OUT[12], - sq_respHandleSQ_pendingRespQ_D_OUT[11:10], - (sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3) ? - (IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 ? - { 4'd0, - (sq_respHandleSQ_pendingRespQ_D_OUT[3:0] == 4'd3) ? - 2'd1 : - 2'd0 } : - sq_respHandleSQ_pendingRespQ_D_OUT[9:4]) : - sq_respHandleSQ_pendingRespQ_D_OUT[9:4] } ; - assign sq_respHandleSQ_pendingPermQueryQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign sq_respHandleSQ_pendingPermQueryQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp ; - assign sq_respHandleSQ_pendingPermQueryQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingRespQ - assign sq_respHandleSQ_pendingRespQ_D_IN = - { sq_respHandleSQ_incomingRespQ_D_OUT[1469:133], - 1'd0, - sq_respHandleSQ_incomingRespQ_D_OUT[131:130], - 4'd0, - sq_respHandleSQ_incomingRespQ_D_OUT[125:110], - 8'd0, - sq_respHandleSQ_incomingRespQ_D_OUT[101:77], - 7'd0, - sq_respHandleSQ_incomingRespQ_D_OUT[69:46], - 1'd0, - sq_respHandleSQ_incomingRespQ_D_OUT[44:7], - CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28, - sq_respHandleSQ_incomingRespQ_D_OUT[5:0] } ; - assign sq_respHandleSQ_pendingRespQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_recvRespHeader ; - assign sq_respHandleSQ_pendingRespQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_handleRespByType ; - assign sq_respHandleSQ_pendingRespQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingRetryCheckQ - assign sq_respHandleSQ_pendingRetryCheckQ_D_IN = - { sq_respHandleSQ_pendingPermQueryQ_D_OUT[1468:132], - 1'd0, - sq_respHandleSQ_pendingPermQueryQ_D_OUT[130:129], - 4'd0, - sq_respHandleSQ_pendingPermQueryQ_D_OUT[124:109], - 8'd0, - sq_respHandleSQ_pendingPermQueryQ_D_OUT[100:76], - 7'd0, - sq_respHandleSQ_pendingPermQueryQ_D_OUT[68:45], - 1'd0, - sq_respHandleSQ_pendingPermQueryQ_D_OUT[43:0], - 1'd0 } ; - assign sq_respHandleSQ_pendingRetryCheckQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_queryPerm4NormalReadAtomicResp ; - assign sq_respHandleSQ_pendingRetryCheckQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_checkRetryErr ; - assign sq_respHandleSQ_pendingRetryCheckQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingSpaceCalcQ - assign sq_respHandleSQ_pendingSpaceCalcQ_D_IN = - { sq_respHandleSQ_pendingLenCalcQ_D_OUT[1538:202], - 1'd0, - sq_respHandleSQ_pendingLenCalcQ_D_OUT[200:199], - 4'd0, - sq_respHandleSQ_pendingLenCalcQ_D_OUT[194:179], - 8'd0, - sq_respHandleSQ_pendingLenCalcQ_D_OUT[170:146], - 7'd0, - sq_respHandleSQ_pendingLenCalcQ_D_OUT[138:115], - 1'd0, - sq_respHandleSQ_pendingLenCalcQ_D_OUT[113:64], - 2'd1, - sq_respHandleSQ_pendingLenCalcQ_D_OUT[63:0], - sq_respHandleSQ_remainingReadRespLenReg, - sq_respHandleSQ_remainingReadRespLenReg } ; - assign sq_respHandleSQ_pendingSpaceCalcQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_calcReadRespLen ; - assign sq_respHandleSQ_pendingSpaceCalcQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_calcEnoughDmaSpace ; - assign sq_respHandleSQ_pendingSpaceCalcQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_pendingWorkCompQ - assign sq_respHandleSQ_pendingWorkCompQ_D_IN = - { sq_respHandleSQ_pendingDmaReqQ_D_OUT[210:202], - 1'd0, - sq_respHandleSQ_pendingDmaReqQ_D_OUT[200:199], - 4'd0, - sq_respHandleSQ_pendingDmaReqQ_D_OUT[194:179], - 8'd0, - sq_respHandleSQ_pendingDmaReqQ_D_OUT[170:146], - 7'd0, - sq_respHandleSQ_pendingDmaReqQ_D_OUT[138:115], - 1'd0, - sq_respHandleSQ_pendingDmaReqQ_D_OUT[113:76], - sq_respHandleSQ_pendingDmaReqQ_D_OUT[1538:938], - 1'd0, - sq_respHandleSQ_pendingDmaReqQ_D_OUT[65:64], - sq_respHandleSQ_pendingDmaReqQ_D_OUT[138:115], - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] ? - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] : - 5'd0 } ; - assign sq_respHandleSQ_pendingWorkCompQ_ENQ = - CAN_FIRE_RL_sq_respHandleSQ_issueDmaReq ; - assign sq_respHandleSQ_pendingWorkCompQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_genWorkCompSQ ; - assign sq_respHandleSQ_pendingWorkCompQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_respHandleSQ_workCompGenReqOutQ - assign sq_respHandleSQ_workCompGenReqOutQ_D_IN = - sq_respHandleSQ_pendingWorkCompQ_D_OUT[632:0] ; - assign sq_respHandleSQ_workCompGenReqOutQ_ENQ = - WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ && - (sq_respHandleSQ_pendingWorkCompQ_D_OUT[633] || - sq_respHandleSQ_pendingWorkCompQ_D_OUT[31]) ; - assign sq_respHandleSQ_workCompGenReqOutQ_DEQ = - WILL_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ && - !sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N && - sq_respHandleSQ_workCompGenReqOutQ_EMPTY_N ; - assign sq_respHandleSQ_workCompGenReqOutQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_prepareRetryRespQ - assign sq_retryHandler_prepareRetryRespQ_D_IN = - { IF_IF_sq_retryHandler_updateRetryCntQ_first__3_ETC___d1388 || - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1, - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] } ; - assign sq_retryHandler_prepareRetryRespQ_ENQ = - MUX_sq_retryHandler_pauseRetryHandleReg_write_1__SEL_1 ; - assign sq_retryHandler_prepareRetryRespQ_DEQ = - CAN_FIRE_RL_sq_retryHandler_sendRetryResp ; - assign sq_retryHandler_prepareRetryRespQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_resetReqQ - assign sq_retryHandler_resetReqQ_D_IN = - sq_respHandleSQ_incomingRespQ_D_OUT[6] ; - assign sq_retryHandler_resetReqQ_ENQ = - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_preStateReg == 4'd3 && - cntrl_stateReg == 4'd3 ; - assign sq_retryHandler_resetReqQ_DEQ = - CAN_FIRE_RL_sq_retryHandler_recvResetReq ; - assign sq_retryHandler_resetReqQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_resetRetryCntQ - assign sq_retryHandler_resetRetryCntQ_D_IN = 1'd1 ; - assign sq_retryHandler_resetRetryCntQ_ENQ = - WILL_FIRE_RL_sq_retryHandler_recvResetReq && - sq_retryHandler_resetReqQ_D_OUT ; - assign sq_retryHandler_resetRetryCntQ_DEQ = - WILL_FIRE_RL_sq_retryHandler_recvRetryReq && - sq_retryHandler_resetRetryCntQ_EMPTY_N ; - assign sq_retryHandler_resetRetryCntQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_resetTimeOutQ - assign sq_retryHandler_resetTimeOutQ_D_IN = 1'd1 ; - assign sq_retryHandler_resetTimeOutQ_ENQ = - CAN_FIRE_RL_sq_retryHandler_recvResetReq ; - assign sq_retryHandler_resetTimeOutQ_DEQ = - WILL_FIRE_RL_sq_retryHandler_checkTimeOut && - sq_retryHandler_resetTimeOutQ_EMPTY_N ; - assign sq_retryHandler_resetTimeOutQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_retryActionQ - assign sq_retryHandler_retryActionQ_D_IN = - { sq_retryHandler_retryNotificationQ_EMPTY_N ? - sq_retryHandler_retryNotificationQ_D_OUT[97] : - sq_retryHandler_timeOutTriggerQ_EMPTY_N, - sq_retryHandler_retryNotificationQ_D_OUT[96:9], - sq_retryHandler_retryNotificationQ_EMPTY_N ? - sq_retryHandler_retryNotificationQ_D_OUT[8:6] : - 3'd4, - sq_retryHandler_retryNotificationQ_D_OUT[5:0] } ; - assign sq_retryHandler_retryActionQ_ENQ = - WILL_FIRE_RL_sq_retryHandler_handleNotifiedRetryAndTimeOut && - (sq_retryHandler_timeOutTriggerQ_EMPTY_N || - sq_retryHandler_retryNotificationQ_EMPTY_N) ; - assign sq_retryHandler_retryActionQ_DEQ = - CAN_FIRE_RL_sq_retryHandler_handleRetryAction ; - assign sq_retryHandler_retryActionQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_retryNotificationQ - assign sq_retryHandler_retryNotificationQ_D_IN = - { sq_retryHandler_retryReqQ_EMPTY_N, - sq_retryHandler_retryReqQ_D_OUT } ; - assign sq_retryHandler_retryNotificationQ_ENQ = - WILL_FIRE_RL_sq_retryHandler_recvRetryReq && - (sq_retryHandler_retryReqQ_EMPTY_N || - sq_retryHandler_resetRetryCntQ_EMPTY_N) ; - assign sq_retryHandler_retryNotificationQ_DEQ = - WILL_FIRE_RL_sq_retryHandler_handleNotifiedRetryAndTimeOut && - sq_retryHandler_retryNotificationQ_EMPTY_N ; - assign sq_retryHandler_retryNotificationQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_retryReqQ - assign sq_retryHandler_retryReqQ_D_IN = - { sq_respHandleSQ_pendingRespQ_D_OUT[1472:1409], - sq_respHandleSQ_pendingRespQ_D_OUT[72:49], - (sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd10) ? - 3'd3 : - CASE_sq_respHandleSQ_pendingRespQD_OUT_BITS_4_ETC__q33, - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 && - sq_respHandleSQ_pendingRespQ_D_OUT[47:46] == 2'd1, - sq_respHandleSQ_pendingRespQ_D_OUT[45:41] } ; - assign sq_retryHandler_retryReqQ_ENQ = - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - (sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd9 || - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd10) ; - assign sq_retryHandler_retryReqQ_DEQ = - WILL_FIRE_RL_sq_retryHandler_recvRetryReq && - sq_retryHandler_retryReqQ_EMPTY_N ; - assign sq_retryHandler_retryReqQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_retryRespQ - assign sq_retryHandler_retryRespQ_D_IN = - sq_retryHandler_prepareRetryRespQ_D_OUT[3] ; - assign sq_retryHandler_retryRespQ_ENQ = - WILL_FIRE_RL_sq_retryHandler_sendRetryResp && - sq_retryHandler_prepareRetryRespQ_D_OUT[2:0] != 3'd4 ; - assign sq_retryHandler_retryRespQ_DEQ = - WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd9 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd10) ; - assign sq_retryHandler_retryRespQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_timeOutNotificationQ - assign sq_retryHandler_timeOutNotificationQ_D_IN = - sq_retryHandler_prepareRetryRespQ_D_OUT[3] ; - assign sq_retryHandler_timeOutNotificationQ_ENQ = - WILL_FIRE_RL_sq_retryHandler_sendRetryResp && - sq_retryHandler_prepareRetryRespQ_D_OUT[2:0] == 3'd4 ; - assign sq_retryHandler_timeOutNotificationQ_DEQ = - CAN_FIRE_RL_sq_respHandleSQ_checkTimeOutErr ; - assign sq_retryHandler_timeOutNotificationQ_CLR = - WILL_FIRE_RL_sq_retryHandler_initRetryCntAndTimeOutTimer || - WILL_FIRE_RL_sq_retryHandler_resetAndClear ; - - // submodule sq_retryHandler_timeOutTriggerQ - assign sq_retryHandler_timeOutTriggerQ_D_IN = 1'd1 ; - assign sq_retryHandler_timeOutTriggerQ_ENQ = - WILL_FIRE_RL_sq_retryHandler_checkTimeOut && - NOT_sq_retryHandler_resetTimeOutQ_notEmpty__17_ETC___d1219 ; - assign sq_retryHandler_timeOutTriggerQ_DEQ = - WILL_FIRE_RL_sq_retryHandler_handleNotifiedRetryAndTimeOut && - sq_retryHandler_timeOutTriggerQ_EMPTY_N ; - assign sq_retryHandler_timeOutTriggerQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_retryHandler_updateRetryCntQ - assign sq_retryHandler_updateRetryCntQ_D_IN = - { sq_retryHandler_retryActionQ_D_OUT[97], - sq_retryHandler_retryActionQ_D_OUT[8:6] } ; - assign sq_retryHandler_updateRetryCntQ_ENQ = - CAN_FIRE_RL_sq_retryHandler_handleRetryAction ; - assign sq_retryHandler_updateRetryCntQ_DEQ = - CAN_FIRE_RL_sq_retryHandler_handleRetryCntUpdate ; - assign sq_retryHandler_updateRetryCntQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_workCompGenSQ_dmaWaitingQ - assign sq_workCompGenSQ_dmaWaitingQ_D_IN = - { sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT, - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[632:569], - CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34, - 7'd0, - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[4:0], - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[463:432], - cntrl_pkeyReg, - cntrl_sqpnReg, - 66'h155555554AAAAAAAA, - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[4:0] == 5'd0, - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[30:29] == 2'd0 && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[561] || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd4 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd5 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd6 || - cntrl_sqSigAllReg) } ; - assign sq_workCompGenSQ_dmaWaitingQ_ENQ = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign sq_workCompGenSQ_dmaWaitingQ_DEQ = - WILL_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ || - WILL_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign sq_workCompGenSQ_dmaWaitingQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_workCompGenSQ_genWorkCompQ - assign sq_workCompGenSQ_genWorkCompQ_D_IN = - sq_workCompGenSQ_dmaWaitingQ_D_OUT ; - assign sq_workCompGenSQ_genWorkCompQ_ENQ = - WILL_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ || - WILL_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ ; - assign sq_workCompGenSQ_genWorkCompQ_DEQ = - WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ || - WILL_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ ; - assign sq_workCompGenSQ_genWorkCompQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_workCompGenSQ_pendingWorkCompQ4SQ - assign sq_workCompGenSQ_pendingWorkCompQ4SQ_D_IN = - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N ? - sq_reqGenSQ_workCompGenReqOutQ_D_OUT : - sq_respHandleSQ_workCompGenReqOutQ_D_OUT ; - assign sq_workCompGenSQ_pendingWorkCompQ4SQ_ENQ = - WILL_FIRE_RL_sq_workCompGenSQ_recvWorkCompGenReqSQ && - (sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N || - sq_respHandleSQ_workCompGenReqOutQ_EMPTY_N) ; - assign sq_workCompGenSQ_pendingWorkCompQ4SQ_DEQ = - CAN_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ ; - assign sq_workCompGenSQ_pendingWorkCompQ4SQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule sq_workCompGenSQ_workCompOutQ4SQ - assign sq_workCompGenSQ_workCompOutQ4SQ_D_IN = - MUX_sq_workCompGenSQ_workCompOutQ4SQ_enq_1__SEL_1 ? - sq_workCompGenSQ_genWorkCompQ_D_OUT[223:2] : - MUX_sq_workCompGenSQ_workCompOutQ4SQ_enq_1__VAL_2 ; - assign sq_workCompGenSQ_workCompOutQ4SQ_ENQ = - WILL_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ && - (sq_workCompGenSQ_genWorkCompQ_D_OUT[0] || - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1]) || - WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - !sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg ; - assign sq_workCompGenSQ_workCompOutQ4SQ_DEQ = EN_workCompPipeOutSQ_deq ; - assign sq_workCompGenSQ_workCompOutQ4SQ_CLR = cntrl_stateReg == 4'd0 ; - - // submodule workReqQ - assign workReqQ_D_IN = workReqIn_put ; - assign workReqQ_ENQ = EN_workReqIn_put ; - assign workReqQ_DEQ = - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_genPendingWR || - WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_flushWR ; - assign workReqQ_CLR = cntrl_stateReg == 4'd0 ; - - // remaining internal signals - assign IF_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_ETC___d1515 = - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d1501 ? - NOT_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVe_ETC___d1503 || - NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1505 : - NOT_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVe_ETC___d1514 ; - assign IF_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_ETC___d4106 = - (value__h99966[23] == cntrl_npsnReg[23]) ? - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4097 && - respPktPipe_metaDataQ_first__626_BITS_554_TO_5_ETC___d4098 : - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4105 ; - assign IF_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_ETC___d4116 = - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d1501 ? - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4108 && - respPktPipe_metaDataQ_first__626_BITS_554_TO_5_ETC___d4109 : - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4115 ; - assign IF_IF_sq_retryHandler_updateRetryCntQ_first__3_ETC___d1388 = - (sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd1) ? - sq_retryHandler_rnrCntReg == 3'd0 : - (sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd2 || - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd3 || - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd4) && - sq_retryHandler_retryCntReg == 3'd0 ; - assign IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d1501 = - value__h99939[23] == value__h99966[23] ; - assign IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4097 = - value__h99966 < respPktPipe_metaDataQ_D_OUT[554:531] ; - assign IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4105 = - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4097 && - value__h99966[23] == respPktPipe_metaDataQ_D_OUT[554] || - respPktPipe_metaDataQ_first__626_BITS_554_TO_5_ETC___d4098 && - respPktPipe_metaDataQ_D_OUT[554] == cntrl_npsnReg[23] ; - assign IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4108 = - value__h99939 < respPktPipe_metaDataQ_D_OUT[554:531] ; - assign IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4115 = - IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0__ETC___d4108 && - value__h99939[23] == respPktPipe_metaDataQ_D_OUT[554] || - respPktPipe_metaDataQ_first__626_BITS_554_TO_5_ETC___d4109 && - respPktPipe_metaDataQ_D_OUT[554] == value__h99966[23] ; - assign IF_cntrl_npsnReg_41_BIT_23_518_EQ_IF_IF_sq_req_ETC___d2534 = - (cntrl_npsnReg[23] == nextPktSeqNum__h56056[23]) ? - NOT_cntrl_npsnReg_41_ULT_IF_IF_sq_reqGenSQ_wor_ETC___d2522 || - NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2524 : - NOT_cntrl_npsnReg_41_ULT_IF_IF_sq_reqGenSQ_wor_ETC___d2533 ; - assign IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_12_ELSE_16___d3346 = - (cntrl_sqTypeReg == 4'd2) ? 7'd12 : 7'd16 ; - assign IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_cntrl__ETC___d3311 = - (cntrl_sqTypeReg == 4'd2) ? a__h69887 : a__h69889 ; - assign IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_sq_req_ETC___d3316 = - (cntrl_sqTypeReg == 4'd2) ? a__h69891 : a__h69893 ; - assign IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_sq_req_ETC___d3349 = - (cntrl_sqTypeReg == 4'd2) ? b__h69892 : b__h69894 ; - assign IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d1880 = - (cntrl_stateReg == 4'd3 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606]) ? - !sq_pendingWorkReqBuf_emptyReg : - cntrl_stateReg == 4'd4 ; - assign IF_cntrl_stateReg_EQ_3_AND_sq_pendingWorkReqPi_ETC___d2074 = - (cntrl_stateReg == 4'd3 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606]) ? - sq_pendingWorkReqBuf_emptyReg : - cntrl_stateReg != 4'd4 ; - assign IF_sq_pendingWorkReqBuf_pushReg_port1__read__7_ETC___d702 = - (sq_pendingWorkReqBuf_pushReg_port1__read[679] && - !sq_pendingWorkReqBuf_popReg_port1__read) ? - sq_pendingWorkReqBuf_itemCnt_Q_OUT[1:0] == 2'd3 : - sq_pendingWorkReqBuf_fullReg ; - assign IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1734 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg ? - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg[0] : - !sq_reqGenSQ_reqHeaderOutQ_D_OUT[0] ; - assign IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1737 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg ? - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg[9:8] : - sq_reqGenSQ_reqHeaderOutQ_D_OUT[9:8] ; - assign IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1742 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg ? - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg[0] : - sq_reqGenSQ_reqHeaderOutQ_D_OUT[0] ; - assign IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1745 = - (IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1734 && - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1737 != - 2'd1 || - sq_reqGenSQ_reqHeaderOutQ_EMPTY_N) && - (IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1742 || - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_FULL_N) ; - assign IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1770 = - { remainingHeaderLen__h47316, - remainingHeaderFragNum__h47317, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg ? - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg[7:0] : - sq_reqGenSQ_reqHeaderOutQ_D_OUT[7:0] } ; - assign IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_24_ETC___d3578 = - sq_reqGenSQ_reqHeaderGenQ_D_OUT[24] ? - sq_reqGenSQ_workCompGenReqOutQ_FULL_N : - sq_reqGenSQ_reqHeaderOutQ_FULL_N && - sq_reqGenSQ_psnReqOutQ_FULL_N ; - assign IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_26_ETC___d3579 = - sq_reqGenSQ_reqHeaderGenQ_D_OUT[26] ? - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_24_ETC___d3578 : - sq_reqGenSQ_reqHeaderOutQ_FULL_N && - sq_reqGenSQ_psnReqOutQ_FULL_N ; - assign IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_62_ETC___d3580 = - sq_reqGenSQ_reqHeaderGenQ_D_OUT[620] ? - IF_sq_reqGenSQ_reqHeaderGenQ_first__570_BIT_26_ETC___d3579 : - sq_reqGenSQ_workCompGenReqOutQ_FULL_N ; - assign IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2724 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] ? - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712 : - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2723 ; - assign IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2730 = - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd2) ? - cntrl_sqTypeReg != 4'd4 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7 : - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd3 || - cntrl_sqTypeReg != 4'd4 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7 ; - assign IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2734 = - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2724 || - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd1 || - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2730 ; - assign IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3420 = - { sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] ? - (cntrl_sqTypeReg == 4'd2 || cntrl_sqTypeReg == 4'd3 || - cntrl_sqTypeReg == 4'd9 || - cntrl_sqTypeReg == 4'd4 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[142]) && - CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q18 : - CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q19, - x__h74169, - x__h81436, - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] || - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd1 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd2 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd3 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd9) && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[516:515] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[514:513] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[512:511] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[510:509] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[508:507] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[506:505] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[504:503] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[502:501] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[500:499] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[498:497] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[496:495] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[494:493] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[492:491] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[490:489] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[488:487] != 2'd0 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[486:485] != 2'd0) && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd4 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd5 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd6 } ; - assign IF_sq_reqGenSQ_workCompGenReqOutQ_notEmpty__69_ETC___d5707 = - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N ? - sq_reqGenSQ_workCompGenReqOutQ_EMPTY_N && - sq_workCompGenSQ_pendingWorkCompQ4SQ_FULL_N : - !sq_respHandleSQ_workCompGenReqOutQ_EMPTY_N || - sq_workCompGenSQ_pendingWorkCompQ4SQ_FULL_N ; - assign IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 = - IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4824 || - CASE_sq_respHandleSQ_preRdmaOpCodeReg_13_NOT_s_ETC__q14 ; - assign IF_sq_respHandleSQ_pendingRetryCheckQ_first__9_ETC___d5037 = - IF_sq_respHandleSQ_pendingRetryCheckQ_first__9_ETC___d4989 && - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q17 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 || - sq_retryHandler_retryRespQ_EMPTY_N ; - assign IF_sq_retryHandler_resetTimeOutQ_notEmpty__176_ETC___d1197 = - (sq_retryHandler_resetTimeOutQ_EMPTY_N || - sq_retryHandler_retryCntrlStateReg != 2'd0) ? - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7 : - sq_retryHandler_disableTimeOutReg || - sq_pendingWorkReqBuf_emptyReg || - !sq_retryHandler_isTimeOutCntHighPartZeroReg || - !sq_retryHandler_isTimeOutCntLowPartZeroReg || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7 && - sq_retryHandler_timeOutTriggerQ_FULL_N ; - assign IF_sq_retryHandler_retryRespQ_first__023_THEN__ETC___d5182 = - sq_retryHandler_retryRespQ_D_OUT ? - 2'd1 : - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[2:1] ; - assign IF_sq_retryHandler_updateRetryCntQ_first__309__ETC___d1340 = - (sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd2 || - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd3 || - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd4) && - !sq_retryHandler_disableRetryCntReg && - sq_retryHandler_retryCntReg != 3'd0 || - !sq_retryHandler_updateRetryCntQ_D_OUT[3] ; - assign IF_sq_workCompGenSQ_genWorkCompQ_first__802_BI_ETC___d5808 = - sq_workCompGenSQ_genWorkCompQ_D_OUT[1] ? - !sq_workCompGenSQ_genWorkCompQ_D_OUT[0] || - sq_workCompGenSQ_workCompOutQ4SQ_FULL_N : - sq_workCompGenSQ_workCompOutQ4SQ_FULL_N ; - assign NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2524 = - endPktSeqNum__h56057 >= nextPktSeqNum__h56056 ; - assign NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2536 = - x__h56104 != nextPktSeqNum__h56056 || - endPktSeqNum__h56057 != cntrl_npsnReg && - IF_cntrl_npsnReg_41_BIT_23_518_EQ_IF_IF_sq_req_ETC___d2534 ; - assign NOT_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVe_ETC___d1503 = - value__h99939 >= v__h37423 ; - assign NOT_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVe_ETC___d1514 = - (NOT_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVe_ETC___d1503 || - value__h99939[23] != v__h37423[23]) && - (NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1505 || - v__h37423[23] != value__h99966[23]) ; - assign NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1505 = - v__h37423 >= value__h99966 ; - assign NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1516 = - v__h37423 != value__h99939 && v__h37423 != value__h99966 && - IF_IF_SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_ETC___d1515 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474 || - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492 || - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649 || - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3783 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3794 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3806 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3822 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3836 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3851 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3867 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3870 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3867 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3884 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3887 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3884 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3902 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3905 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3902 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3921 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3927 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3921 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3941 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3935 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3947 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3941 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3956 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3935 ; - assign NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3962 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3956 ; - assign NOT_cntrl_npsnReg_41_ULT_IF_IF_sq_reqGenSQ_wor_ETC___d2522 = - cntrl_npsnReg >= endPktSeqNum__h56057 ; - assign NOT_cntrl_npsnReg_41_ULT_IF_IF_sq_reqGenSQ_wor_ETC___d2533 = - (NOT_cntrl_npsnReg_41_ULT_IF_IF_sq_reqGenSQ_wor_ETC___d2522 || - cntrl_npsnReg[23] != endPktSeqNum__h56057[23]) && - (NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2524 || - endPktSeqNum__h56057[23] != nextPktSeqNum__h56056[23]) ; - assign NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd0 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd1 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd2 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd3 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd9 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd4 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd5 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd6 || - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - (cntrl_sqTypeReg != 4'd4 || - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[142]) || - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2711 ; - assign NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2723 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd0 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd1 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd2 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd3 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd9 || - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - (cntrl_sqTypeReg != 4'd4 || - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[142]) || - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2722 ; - assign NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742 = - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - (cntrl_sqTypeReg != 4'd4 || - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[142]) || - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2711 ; - assign NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2882 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd0 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd1 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd2 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd3 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd9 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd4 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd5 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd6 || - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - cntrl_sqTypeReg != 4'd4 || - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2711 ; - assign NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2889 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd0 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd1 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd2 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd3 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd9 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd4 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd5 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd6 || - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 || - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2711 ; - assign NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2902 = - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - (cntrl_sqTypeReg != 4'd4 || - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[142]) || - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2722 ; - assign NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2973 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd0 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd1 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd2 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd3 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd9 || - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - cntrl_sqTypeReg != 4'd4 || - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2722 ; - assign NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2978 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd0 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd1 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd2 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd3 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd9 || - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 || - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2722 ; - assign NOT_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_77__ETC___d376 = - !dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[13] && - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[12:11] == 2'd0 && - !dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[10] && - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[9:8] == 2'd0 && - !dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[7] && - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[6:5] == 2'd0 && - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[4:3] == 2'd0 && - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[2:1] == 2'd0 ; - assign NOT_sq_newPendingWorkReqPiptOut_pendingNewWork_ETC___d1707 = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg > 8'd4 ; - assign NOT_sq_pendingWorkReqPipeOut_pipeMuxOutQ_first_ETC___d1919 = - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[381:358] != - cntrl_sqpnReg ; - assign NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686] != - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[58:35] ; - assign NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 = - sq_respHandleSQ_preStageWorkReqAckTypeReg != 4'd8 && - !sq_respHandleSQ_recvRetryRespReg && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4479 = - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd1 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd2 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd3 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd4 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd5 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd6 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd7 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd8 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd9 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd10 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd11 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd12 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd13 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd14 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd15 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd16 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd17 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd18 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd19 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd20 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd21 && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] != 5'd22 ; - assign NOT_sq_respHandleSQ_retryFlushReg_616_617_OR_s_ETC___d4756 = - (!sq_respHandleSQ_retryFlushReg || - sq_respHandleSQ_errOccurredReg || - sq_respHandleSQ_recvErrRespReg) && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd0 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd3 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd1 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd4 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd2 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd5 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd6 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd7 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd8 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd12 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd13 ; - assign NOT_sq_retryHandler_resetTimeOutQ_notEmpty__17_ETC___d1219 = - !sq_retryHandler_resetTimeOutQ_EMPTY_N && - sq_retryHandler_retryCntrlStateReg == 2'd0 && - !sq_retryHandler_disableTimeOutReg && - !sq_pendingWorkReqBuf_emptyReg && - sq_retryHandler_isTimeOutCntHighPartZeroReg && - sq_retryHandler_isTimeOutCntLowPartZeroReg ; - assign NOT_sq_retryHandler_retryReasonReg_431_EQ_4_46_ETC___d1656 = - { sq_retryHandler_retryReasonReg != 3'd4 || - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474, - (sq_retryHandler_retryReasonReg == 3'd4) ? - value__h99939 : - sq_retryHandler_retryStartPsnReg, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492, - value__h99966, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649, - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1653 } ; - assign _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577 = - (32'd1 << lastFragValidByteNumWithPadding__h13828) - 32'd1 ; - assign _1_SL_sq_reqGenSQ_pendingReqHeaderQ_first__424__ETC___d3443 = - (64'd1 << sq_reqGenSQ_pendingReqHeaderQ_D_OUT[31:25]) - 64'd1 ; - assign __duses1049 = - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd13 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd12 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd8 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd7 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd6 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd5 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd4 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd3 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd2 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd1 && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd0 ; - assign __duses1054 = - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd13 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd12 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd8 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd7 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd6 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd5 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd4 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd3 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd2 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd1 && - sq_respHandleSQ_retryFlushReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd0 ; - assign __duses727 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses732 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses737 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses742 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses747 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses752 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses753 = - __duses752 || __duses747 || __duses742 || __duses737 || - __duses732 || - __duses727 || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - sq_respHandleSQ_preStageReqPktInfoReg[5] && - sq_respHandleSQ_preStageRespTypeReg == 2'd0 ; - assign __duses757 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses762 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses767 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses772 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses777 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses782 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses783 = - __duses782 || __duses777 || __duses772 || __duses767 || - __duses762 || - __duses757 || - __duses753 ; - assign __duses787 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3935 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses792 = - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3935 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 ; - assign __duses795 = - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses792 || - __duses787 || - __duses783 ; - assign __duses806 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !enumBits__h93928[0] || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses795 ; - assign __duses810 = - enumBits__h93928[1] && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) || - __duses806 ; - assign __duses815 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !enumBits__h93928[1] || - __duses810 ; - assign __duses819 = - enumBits__h93928[2] && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) || - __duses815 ; - assign __duses824 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !enumBits__h93928[2] || - __duses819 ; - assign __duses828 = - enumBits__h93928[3] && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) || - __duses824 ; - assign __duses833 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !enumBits__h93928[3] || - __duses828 ; - assign __duses837 = - enumBits__h93928[4] && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) || - __duses833 ; - assign __duses842 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !enumBits__h93928[4] || - __duses837 ; - assign __duses847 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - enumBits__h93928 == 5'd0 || - __duses842 ; - assign __duses852 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - enumBits__h93928 != 5'd0 || - __duses847 ; - assign __duses863 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses852 ; - assign __duses874 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses863 ; - assign __duses885 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses874 ; - assign __duses896 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses885 ; - assign __duses907 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses896 ; - assign __duses918 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses907 ; - assign __duses929 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses918 ; - assign __duses940 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses929 ; - assign __duses953 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses940 ; - assign __duses964 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses953 ; - assign __duses975 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses964 ; - assign __duses986 = - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses975 ; - assign __duses988 = - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) || - __duses986 ; - assign __duses991 = - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) ; - assign __duses996 = - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2) && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 ; - assign __duses999 = - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses996 || - __duses991 || - __duses988 ; - assign _theResult___snd__h61670 = - sq_reqGenSQ_reqCountQ_D_OUT[5] ? - 25'd0 : - remainingPktNum___1__h61681 ; - assign a__h52253 = - { 1'd0, sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:486] } ; - assign a__h52263 = - { 2'd0, sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:487] } ; - assign a__h52273 = - { 3'd0, sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:488] } ; - assign a__h52283 = - { 4'd0, sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:489] } ; - assign a__h52293 = - { 5'd0, sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:490] } ; - assign a__h63239 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[612:485], - 288'd0 } ; - assign a__h63241 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 8'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[612:485], - 256'd0 } ; - assign a__h63243 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[612:485], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[232:201], - 256'd0 } : - a__h63239 ; - assign a__h63245 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 8'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[612:485], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[232:201], - 224'd0 } : - a__h63241 ; - assign a__h63247 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 416'd0 } ; - assign a__h63249 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[116:85], - 8'd0, - cntrl_sqpnReg, - 352'd0 } ; - assign a__h63251 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 8'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143], - 384'd0 } ; - assign a__h63253 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[232:201], - 384'd0 } : - a__h63247 ; - assign a__h63255 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[116:85], - 8'd0, - cntrl_sqpnReg, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[232:201], - 320'd0 } ; - assign a__h63257 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 8'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[232:201], - 352'd0 } : - a__h63251 ; - assign a__h63259 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[199:168], - 384'd0 } : - a__h63247 ; - assign a__h63261 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 8'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[199:168], - 352'd0 } : - a__h63251 ; - assign a__h63269 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[612:517], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[297:234], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[362:299], - 192'd0 } ; - assign a__h63272 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h63283, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 8'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[612:517], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[297:234], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[362:299], - 160'd0 } ; - assign a__h69887 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h69915, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 416'd0 } ; - assign a__h69889 = - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h69915, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 8'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143], - 384'd0 } ; - assign a__h69891 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h69915, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[232:201], - 384'd0 } : - a__h69887 ; - assign a__h69893 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h69915, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 8'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[232:201], - 352'd0 } : - a__h69889 ; - assign a__h69903 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h69915, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[199:168], - 384'd0 } : - a__h69887 ; - assign a__h69905 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? - { IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208, - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364], - 1'd0, - bth_padCnt__h69915, - 4'd0, - cntrl_pkeyReg, - 8'd0, - x__h63485, - cntrl_sqSigAllReg || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[614] || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6), - 7'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[709:686], - 8'd0, - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[199:168], - 352'd0 } : - a__h69889 ; - assign a__h9345 = { 1'd0, dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:11] } ; - assign a__h9355 = { 2'd0, dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:12] } ; - assign a__h9365 = { 3'd0, dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:13] } ; - assign a__h9375 = { 4'd0, dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:14] } ; - assign a__h9385 = { 5'd0, dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:15] } ; - assign addrChunkResp_chunkLen__h10586 = - (dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_77_BITS_ETC___d366 && - NOT_dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_77__ETC___d376 && - !dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg) ? - { 1'd0, dmaReadCntrl4SQ_addrChunkSrv_residueReg } : - dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg ; - assign b__h52254 = - { 4'd0, sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[485:478] } ; - assign b__h52264 = - { 3'd0, sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[486:478] } ; - assign b__h52274 = - { 2'd0, sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[487:478] } ; - assign b__h52284 = - { 1'd0, sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[488:478] } ; - assign b__h63244 = sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? 7'd32 : 7'd28 ; - assign b__h63246 = sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? 7'd36 : 7'd32 ; - assign b__h63254 = sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? 7'd16 : 7'd12 ; - assign b__h63258 = sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? 7'd20 : 7'd16 ; - assign b__h69892 = sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? 7'd16 : 7'd12 ; - assign b__h69894 = sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? 7'd20 : 7'd16 ; - assign b__h9346 = { 4'd0, dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[10:3] } ; - assign b__h9356 = { 3'd0, dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[11:3] } ; - assign b__h9366 = { 2'd0, dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[12:3] } ; - assign b__h9376 = { 1'd0, dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[13:3] } ; - assign bits__h49179 = - { payloadGenerator4SQ_bramQ2PipeOut_postBramQ_fi_ETC___d1852[31], - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_fi_ETC___d1852[0] } ; - assign bth_padCnt__h63283 = - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd4 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd5 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd6) ? - padCnt__h63476 : - 2'd0 ; - assign bth_padCnt__h69915 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? padCnt__h63476 : 2'd0 ; - assign cntrl_stateReg_EQ_3_AND_NOT_sq_respHandleSQ_re_ETC___d5647 = - cntrl_stateReg == 4'd3 && !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg ; - assign cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_preSta_ETC___d3624 = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd0 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg ; - assign cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_preSta_ETC___d4329 = - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg ; - assign cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_recvEr_ETC___d5683 = - (cntrl_stateReg == 4'd3 && - (sq_respHandleSQ_recvErrRespReg || - sq_respHandleSQ_errOccurredReg) || - cntrl_stateReg == 4'd6) && - sq_pendingWorkReqBuf_emptyReg ; - assign cntrl_stateReg_EQ_3_AND_sq_respHandleSQ_retryF_ETC___d5690 = - cntrl_stateReg == 4'd3 && sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg ; - assign curPSN__h61636 = - sq_reqGenSQ_isFirstOrOnlyReqPktReg ? - sq_reqGenSQ_reqCountQ_D_OUT[81:58] : - sq_reqGenSQ_curPsnReg ; - assign dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_77_BITS_ETC___d366 = - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[24:23] == 2'd0 && - !dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[22] && - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[21:20] == 2'd0 && - !dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[19] && - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[18:17] == 2'd0 && - !dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[16] && - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg[15:14] == 2'd0 ; - assign dmaReadCntrl4SQ_respQ_i_notEmpty__42_AND_NOT_d_ETC___d657 = - dmaReadCntrl4SQ_respQ_EMPTY_N && - (!dmaReadCntrl4SQ_respQ_D_OUT[0] || - payloadGenerator4SQ_pendingGenReqQ_EMPTY_N) && - (!dmaReadCntrl4SQ_respQ_D_OUT[2] && - !dmaReadCntrl4SQ_respQ_D_OUT[292] || - payloadGenerator4SQ_pendingGenReqQ_EMPTY_N && - payloadGenerator4SQ_payloadGenRespQ_FULL_N) ; - assign endPktSeqNum__h56057 = - sq_reqGenSQ_workReqPsnQ_D_OUT[5] ? - cntrl_npsnReg : - nextPktSeqNum__h56056 - 24'd1 ; - assign headerLastFragInvalidByteNum__h47982 = - 6'd32 - - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[7:2] ; - assign headerLastFragValidBitNum__h47980 = - { sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[7:2], - 3'd0 } ; - assign lastFragValidByteNumWithPadding__h13828 = - lastFragValidByteNum__h13827 + { 4'd0, padCnt__h13826 } ; - assign lastFragValidByteNum__h13827 = - (payloadGenerator4SQ_payloadGenReqQ_D_OUT[9:8] == 2'd0 && - !payloadGenerator4SQ_payloadGenReqQ_D_OUT[7] && - payloadGenerator4SQ_payloadGenReqQ_D_OUT[6:5] == 2'd0 && - (payloadGenerator4SQ_payloadGenReqQ_D_OUT[36] || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[35:34] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[33] || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[32:31] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[30] || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[29:28] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[27:26] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[25:24] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[23] || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[22:21] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[20:19] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[18:17] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[16] || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[15:14] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[13:12] != 2'd0 || - payloadGenerator4SQ_payloadGenReqQ_D_OUT[11:10] != 2'd0)) ? - 6'd32 : - lastFragValidByteNum__h13849 ; - assign lastFragValidByteNum__h13849 = - { 1'd0, payloadGenerator4SQ_payloadGenReqQ_D_OUT[9:5] } ; - assign lastFragValidByteNum__h87658 = - { 1'd0, sq_reqGenSQ_pendingReqHeaderQ_D_OUT[29:25] } ; - assign leftShiftByteEn__h49542 = - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg[33:2] << - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg ; - assign leftShiftData__h49541 = - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg[289:34] << - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg ; - assign leftShiftHeaderByteEn__h47319 = { x__h47528[31:0], 32'd0 } ; - assign leftShiftHeaderData__h47318 = { x__h47525[255:0], 256'd0 } ; - assign nextPktSeqNum__h56056 = - sq_reqGenSQ_workReqPsnQ_D_OUT[5] ? - startPlusOne__h56122 : - x__h56223[23:0] ; - assign padCnt__h13826 = - 2'd0 - payloadGenerator4SQ_payloadGenReqQ_D_OUT[6:5] ; - assign padCnt__h63476 = - 2'd0 - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[486:485] ; - assign payloadGenerator4SQ_bramQ2PipeOut_postBramQ_fi_ETC___d1852 = - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_OUT[33:2] << - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg ; - assign payloadGenerator4SQ_payloadBufQ_rRdPtr_read__7_ETC___d487 = - payloadGenerator4SQ_payloadBufQ_rRdPtr == - payloadGenerator4SQ_payloadBufQ_rWrPtr ; - assign remainingHeaderFragNum__h47317 = - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1737 - - 2'd1 ; - assign remainingHeaderLen__h47316 = - (sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg ? - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg[16:10] : - sq_reqGenSQ_reqHeaderOutQ_D_OUT[16:10]) - - 7'd32 ; - assign remainingPktNum___1__h61681 = - sq_reqGenSQ_reqCountQ_D_OUT[31:7] - 25'd2 ; - assign remainingPktNum___1__h61739 = - sq_reqGenSQ_remainingPktNumReg - 25'd1 ; - assign respPktPipe_metaDataQ_first__626_BITS_554_TO_5_ETC___d4098 = - respPktPipe_metaDataQ_D_OUT[554:531] < cntrl_npsnReg ; - assign respPktPipe_metaDataQ_first__626_BITS_554_TO_5_ETC___d4109 = - respPktPipe_metaDataQ_D_OUT[554:531] < value__h99966 ; - assign rightShiftHeaderLastFragByteEn__h48758 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[33:2] >> - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg ; - assign rightShiftHeaderLastFragData__h48757 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[289:34] >> - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg ; - assign rnrTimer__h36783 = - (sq_retryHandler_retryRnrTimerReg <= cntrl_minRnrTimerReg) ? - cntrl_minRnrTimerReg : - sq_retryHandler_retryRnrTimerReg ; - assign sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031 = - sq_pendingWorkReqBuf_deqPtrReg == - sq_pendingWorkReqBuf_scanPtrReg + 2'd1 ; - assign sq_reqGenSQ_pendingReqHeaderQ_first__424_BITS__ETC___d3563 = - { sq_reqGenSQ_pendingReqHeaderQ_D_OUT[31:25], - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[31:30] + - { 1'd0, x__h87589 }, - (sq_reqGenSQ_pendingReqHeaderQ_D_OUT[29:28] == 2'd0 && - !sq_reqGenSQ_pendingReqHeaderQ_D_OUT[27] && - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[26:25] == 2'd0 && - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[31:30] != 2'd0) ? - 6'd32 : - lastFragValidByteNum__h87658, - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[24], - 1'd0 } ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAnd_ETC___d1747 = - (sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg || - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_FULL_N && - sq_reqGenSQ_reqHeaderOutQ_EMPTY_N) && - (sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg || - sq_reqGenSQ_reqHeaderOutQ_EMPTY_N) && - IF_sq_reqGenSQ_rdmaReqPipeOut_headerDataStream_ETC___d1745 ; - assign sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAnd_ETC___d1808 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_EMPTY_N && - (sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] ? - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg || - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_FULL_N : - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_dataStreamOutQ_FULL_N) ; - assign sq_reqGenSQ_workReqCheckQ_i_notEmpty__561_AND__ETC___d2573 = - sq_reqGenSQ_workReqCheckQ_EMPTY_N && - sq_reqGenSQ_workReqOutQ_FULL_N && - (sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] || - sq_reqGenSQ_reqCountQ_FULL_N) ; - assign sq_reqGenSQ_workReqPsnQ_first__498_BIT_4_499_O_ETC___d2558 = - { sq_reqGenSQ_workReqPsnQ_D_OUT[4] || - sq_reqGenSQ_workReqPsnQ_D_OUT[82], - sq_reqGenSQ_workReqPsnQ_D_OUT[4] ? - cntrl_npsnReg : - sq_reqGenSQ_workReqPsnQ_D_OUT[81:58], - sq_reqGenSQ_workReqPsnQ_D_OUT[4] || - sq_reqGenSQ_workReqPsnQ_D_OUT[57], - sq_reqGenSQ_workReqPsnQ_D_OUT[4] ? - endPktSeqNum__h56057 : - sq_reqGenSQ_workReqPsnQ_D_OUT[56:33], - sq_reqGenSQ_workReqPsnQ_D_OUT[32:7], - sq_reqGenSQ_workReqPsnQ_D_OUT[4] || - sq_reqGenSQ_workReqPsnQ_D_OUT[6], - sq_reqGenSQ_workReqPsnQ_D_OUT[4] ? - sq_reqGenSQ_workReqPsnQ_D_OUT[5] || - sq_reqGenSQ_workReqPsnQ_D_OUT[619:616] == 4'd4 : - sq_reqGenSQ_workReqPsnQ_D_OUT[5] } ; - assign sq_respHandleSQ_pendingRetryCheckQ_first__949__ETC___d5046 = - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 || - sq_retryHandler_retryRespQ_EMPTY_N) && - IF_sq_respHandleSQ_pendingRetryCheckQ_first__9_ETC___d5037 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 || - sq_retryHandler_retryRespQ_EMPTY_N) ; - assign sq_respHandleSQ_pendingRetryCheckQ_first__949__ETC___d5187 = - { sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3], - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd0 || - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q21, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q23, - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q24, - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[0] } ; - assign sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4187 = - sq_respHandleSQ_preStagePktMetaDataReg[1] && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1000 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1010) && - sq_respHandleSQ_preStageRespTypeReg != 2'd1 && - sq_respHandleSQ_preStageRespTypeReg != 2'd2 && - sq_respHandleSQ_preStageRespTypeReg != 2'd0 ; - assign sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4200 = - sq_respHandleSQ_preStagePktMetaDataReg[1] && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg != 2'd1 && - sq_respHandleSQ_preStageRespTypeReg != 2'd2 && - sq_respHandleSQ_preStageRespTypeReg != 2'd0 ; - assign sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203 = - sq_respHandleSQ_preStagePktMetaDataReg[1] && - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q13 ; - assign sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4208 = - sq_respHandleSQ_preStagePktMetaDataReg[1] && - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q10 ; - assign sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4214 = - sq_respHandleSQ_preStagePktMetaDataReg[1] && - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q12 ; - assign sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4220 = - sq_respHandleSQ_preStagePktMetaDataReg[1] && - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q11 ; - assign sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4267 = - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b1000 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b1010 || - sq_respHandleSQ_preStageRespTypeReg != 2'd0) && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b1000 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b1010 || - sq_respHandleSQ_preStageRespTypeReg != 2'd1) && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b1000 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b1010 || - sq_respHandleSQ_preStageRespTypeReg != 2'd2) && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0001 || - sq_respHandleSQ_preStageRespTypeReg != 2'd0) && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0001 || - sq_respHandleSQ_preStageRespTypeReg != 2'd1) && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0001 || - sq_respHandleSQ_preStageRespTypeReg != 2'd2) && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0100 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0100 || - !sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1000 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0100 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) ; - assign sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4697 = - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 ; - assign sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4716 = - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - (sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd0 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd3 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd10 && - !sq_respHandleSQ_incomingRespQ_D_OUT[142]) ; - assign sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4746 = - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd6 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd2 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd5 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd0 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd3 && - (sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 || - sq_respHandleSQ_incomingRespQ_D_OUT[142]) && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd8 && - (sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 || - !sq_respHandleSQ_incomingRespQ_D_OUT[142]) && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd12 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd13 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd1 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd4 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd7 ; - assign sq_retryHandler_prepareRetryRespQ_i_notEmpty___ETC___d1411 = - sq_retryHandler_prepareRetryRespQ_EMPTY_N && - ((sq_retryHandler_prepareRetryRespQ_D_OUT[2:0] == 3'd4) ? - sq_retryHandler_timeOutNotificationQ_FULL_N : - sq_retryHandler_retryRespQ_FULL_N) ; - assign sq_retryHandler_resetReqQ_i_notEmpty__149_AND__ETC___d1155 = - sq_retryHandler_resetReqQ_EMPTY_N && - (sq_retryHandler_resetReqQ_D_OUT ? - sq_retryHandler_resetTimeOutQ_FULL_N && - sq_retryHandler_resetRetryCntQ_FULL_N : - sq_retryHandler_resetTimeOutQ_FULL_N) ; - assign sq_retryHandler_resetTimeOutQ_notEmpty__176_OR_ETC___d1209 = - sq_retryHandler_resetTimeOutQ_EMPTY_N || - sq_retryHandler_retryCntrlStateReg != 2'd0 || - !sq_retryHandler_disableTimeOutReg && - !sq_pendingWorkReqBuf_emptyReg && - sq_retryHandler_isTimeOutCntHighPartZeroReg && - sq_retryHandler_isTimeOutCntLowPartZeroReg ; - assign sq_retryHandler_updateRetryCntQ_i_notEmpty__30_ETC___d1313 = - sq_retryHandler_updateRetryCntQ_EMPTY_N && - (sq_retryHandler_updateRetryCntQ_D_OUT[3] ? - sq_retryHandler_prepareRetryRespQ_FULL_N : - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) ; - assign sq_workCompGenSQ_dmaWaitingQ_i_notFull__721_AN_ETC___d5767 = - sq_workCompGenSQ_dmaWaitingQ_FULL_N && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) && - (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[30:29] != 2'd0 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[561] || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd4 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd5 || - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] == 4'd6 || - cntrl_stateReg != 4'd0 && cntrl_stateReg != 4'd7) ; - assign startPlusOne__h56122 = cntrl_npsnReg + 24'd1 ; - assign tmpByteEn__h49088 = - { sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg[33:2], - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_OUT[33:2] } >> - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg ; - assign tmpData__h49087 = - { sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg[289:34], - payloadGenerator4SQ_bramQ2PipeOut_postBramQ_D_OUT[289:34] } >> - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg ; - assign totalPktNum__h55209 = - sq_reqGenSQ_workReqPktNumQ_D_OUT[3] ? - sq_reqGenSQ_workReqPktNumQ_D_OUT[29:5] : - sq_reqGenSQ_workReqPktNumQ_D_OUT[29:5] + 25'd1 ; - assign v__h37423 = - (sq_retryHandler_retryReasonReg == 3'd4) ? - value__h99939 : - sq_retryHandler_retryStartPsnReg ; - assign x__h12662 = payloadGenerator4SQ_payloadBufQ_rWrPtr + 10'd1 ; - assign x__h12913 = payloadGenerator4SQ_payloadBufQ_rRdPtr + 10'd1 ; - assign x__h14424 = - { _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[0], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[1], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[2], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[3], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[4], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[5], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[6], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[7], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[8], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[9], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[10], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[11], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[12], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[13], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[14], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[15], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[16], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[17], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[18], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[19], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[20], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[21], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[22], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[23], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[24], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[25], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[26], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[27], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[28], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[29], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[30], - _1_SL_IF_payloadGenerator4SQ_payloadGenReqQ_fir_ETC___d577[31] } ; - assign x__h16825 = - 8'd1 << CASE_payloadGenerator4SQ_payloadGenReqQD_OUT__ETC__q1 ; - assign x__h33715 = sq_retryHandler_timeOutCntReg - 42'd1 ; - assign x__h35617 = sq_retryHandler_retryCntReg - 3'd1 ; - assign x__h35647 = sq_retryHandler_rnrCntReg - 3'd1 ; - assign x__h37628 = { 1'b1, v__h37423 } - { 1'b0, value__h99939 } ; - assign x__h41815 = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg + 8'd1 ; - assign x__h41903 = - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg - 8'd1 ; - assign x__h47525 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg ? - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg[592:81] : - sq_reqGenSQ_reqHeaderOutQ_D_OUT[592:81] ; - assign x__h47528 = - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg ? - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg[80:17] : - sq_reqGenSQ_reqHeaderOutQ_D_OUT[80:17] ; - assign x__h56104 = endPktSeqNum__h56057 + 24'd1 ; - assign x__h56223 = - { 1'd0, cntrl_npsnReg } + sq_reqGenSQ_workReqPsnQ_D_OUT[31:7] ; - assign x__h74169 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] ? - value__h63238 : - value__h69886 ; - assign x__h81436 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] ? - value__h68654 : - value__h72405 ; - assign x__h87589 = - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[29:28] != 2'd0 || - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[27] || - sq_reqGenSQ_pendingReqHeaderQ_D_OUT[26:25] != 2'd0 ; - assign x__read_byteEn__h12579 = - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding ? - payloadGenerator4SQ_payloadBufQ_wDataIn_wget[33:2] : - 32'd0 ; - assign x__read_data__h12578 = - CAN_FIRE_RL_payloadGenerator4SQ_lastFragAddPadding ? - payloadGenerator4SQ_payloadBufQ_wDataIn_wget[289:34] : - 256'd0 ; - assign y__h42773 = cntrl_pendingWorkReqNumReg - 8'd1 ; - assign y_avValue_byteEn__h17055 = - payloadGenerator4SQ_pendingGenReqQ_D_OUT[43] ? - payloadGenerator4SQ_pendingGenReqQ_D_OUT[39:8] : - dmaReadCntrl4SQ_respQ_D_OUT[35:4] ; - always@(cntrl_reqQ_D_OUT or cntrl_pendingReadAtomicReqNumReg) - begin - case (cntrl_reqQ_D_OUT[300:299]) - 2'd0, 2'd1, 2'd2: x__h6243 = cntrl_reqQ_D_OUT[36:29]; - 2'd3: x__h6243 = cntrl_pendingReadAtomicReqNumReg; - endcase - end - always@(cntrl_reqQ_D_OUT or cntrl_npsnReg) - begin - case (cntrl_reqQ_D_OUT[300:299]) - 2'd0, 2'd1, 2'd2: x__h6205 = cntrl_reqQ_D_OUT[149:126]; - 2'd3: x__h6205 = cntrl_npsnReg; - endcase - end - always@(payloadGenerator4SQ_payloadGenReqQ_D_OUT) - begin - case (payloadGenerator4SQ_payloadGenReqQ_D_OUT[2:0]) - 3'd1: CASE_payloadGenerator4SQ_payloadGenReqQD_OUT__ETC__q1 = 32'd3; - 3'd2: CASE_payloadGenerator4SQ_payloadGenReqQD_OUT__ETC__q1 = 32'd4; - 3'd3: CASE_payloadGenerator4SQ_payloadGenReqQD_OUT__ETC__q1 = 32'd5; - 3'd4: CASE_payloadGenerator4SQ_payloadGenReqQD_OUT__ETC__q1 = 32'd6; - default: CASE_payloadGenerator4SQ_payloadGenReqQD_OUT__ETC__q1 = 32'd7; - endcase - end - always@(cntrl_sqTypeReg or - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT or cntrl_dqpnReg) - begin - case (cntrl_sqTypeReg) - 4'd2, 4'd3, 4'd9: x__h63485 = cntrl_dqpnReg; - default: x__h63485 = sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[141:118]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: value__h99740 = sq_pendingWorkReqBuf_dataVec_0[355:292]; - 2'd1: value__h99740 = sq_pendingWorkReqBuf_dataVec_1[355:292]; - 2'd2: value__h99740 = sq_pendingWorkReqBuf_dataVec_2[355:292]; - 2'd3: value__h99740 = sq_pendingWorkReqBuf_dataVec_3[355:292]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: enumBits__h93928 = sq_pendingWorkReqBuf_dataVec_0[610:606]; - 2'd1: enumBits__h93928 = sq_pendingWorkReqBuf_dataVec_1[610:606]; - 2'd2: enumBits__h93928 = sq_pendingWorkReqBuf_dataVec_2[610:606]; - 2'd3: enumBits__h93928 = sq_pendingWorkReqBuf_dataVec_3[610:606]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: value__h99767 = sq_pendingWorkReqBuf_dataVec_0[290:227]; - 2'd1: value__h99767 = sq_pendingWorkReqBuf_dataVec_1[290:227]; - 2'd2: value__h99767 = sq_pendingWorkReqBuf_dataVec_2[290:227]; - 2'd3: value__h99767 = sq_pendingWorkReqBuf_dataVec_3[290:227]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: value__h99797 = sq_pendingWorkReqBuf_dataVec_0[225:194]; - 2'd1: value__h99797 = sq_pendingWorkReqBuf_dataVec_1[225:194]; - 2'd2: value__h99797 = sq_pendingWorkReqBuf_dataVec_2[225:194]; - 2'd3: value__h99797 = sq_pendingWorkReqBuf_dataVec_3[225:194]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: value__h99854 = sq_pendingWorkReqBuf_dataVec_0[159:136]; - 2'd1: value__h99854 = sq_pendingWorkReqBuf_dataVec_1[159:136]; - 2'd2: value__h99854 = sq_pendingWorkReqBuf_dataVec_2[159:136]; - 2'd3: value__h99854 = sq_pendingWorkReqBuf_dataVec_3[159:136]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: value__h99824 = sq_pendingWorkReqBuf_dataVec_0[192:161]; - 2'd1: value__h99824 = sq_pendingWorkReqBuf_dataVec_1[192:161]; - 2'd2: value__h99824 = sq_pendingWorkReqBuf_dataVec_2[192:161]; - 2'd3: value__h99824 = sq_pendingWorkReqBuf_dataVec_3[192:161]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: value__h99881 = sq_pendingWorkReqBuf_dataVec_0[134:111]; - 2'd1: value__h99881 = sq_pendingWorkReqBuf_dataVec_1[134:111]; - 2'd2: value__h99881 = sq_pendingWorkReqBuf_dataVec_2[134:111]; - 2'd3: value__h99881 = sq_pendingWorkReqBuf_dataVec_3[134:111]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: value__h99908 = sq_pendingWorkReqBuf_dataVec_0[109:78]; - 2'd1: value__h99908 = sq_pendingWorkReqBuf_dataVec_1[109:78]; - 2'd2: value__h99908 = sq_pendingWorkReqBuf_dataVec_2[109:78]; - 2'd3: value__h99908 = sq_pendingWorkReqBuf_dataVec_3[109:78]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: value__h99939 = sq_pendingWorkReqBuf_dataVec_0[76:53]; - 2'd1: value__h99939 = sq_pendingWorkReqBuf_dataVec_1[76:53]; - 2'd2: value__h99939 = sq_pendingWorkReqBuf_dataVec_2[76:53]; - 2'd3: value__h99939 = sq_pendingWorkReqBuf_dataVec_3[76:53]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: value__h99966 = sq_pendingWorkReqBuf_dataVec_0[51:28]; - 2'd1: value__h99966 = sq_pendingWorkReqBuf_dataVec_1[51:28]; - 2'd2: value__h99966 = sq_pendingWorkReqBuf_dataVec_2[51:28]; - 2'd3: value__h99966 = sq_pendingWorkReqBuf_dataVec_3[51:28]; - endcase - end - always@(dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT or - a__h9385 or a__h9345 or a__h9355 or a__h9365 or a__h9375) - begin - case (dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[2:0]) - 3'd1: tmpPktNum__h9229 = a__h9345; - 3'd2: tmpPktNum__h9229 = a__h9355; - 3'd3: tmpPktNum__h9229 = a__h9365; - 3'd4: tmpPktNum__h9229 = a__h9375; - default: tmpPktNum__h9229 = a__h9385; - endcase - end - always@(cntrl_sqTypeReg) - begin - case (cntrl_sqTypeReg) - 4'd2, 4'd3: CASE_cntrl_sqTypeReg_2_28_3_28_32__q2 = 7'd28; - default: CASE_cntrl_sqTypeReg_2_28_3_28_32__q2 = 7'd32; - endcase - end - always@(cntrl_sqTypeReg or b__h63246 or b__h63244) - begin - case (cntrl_sqTypeReg) - 4'd2, 4'd3: CASE_cntrl_sqTypeReg_2_b3244_3_b3244_b3246__q3 = b__h63244; - default: CASE_cntrl_sqTypeReg_2_b3244_3_b3244_b3246__q3 = b__h63246; - endcase - end - always@(cntrl_sqTypeReg) - begin - case (cntrl_sqTypeReg) - 4'd2, 4'd3: CASE_cntrl_sqTypeReg_2_12_3_12_4_20_16__q4 = 7'd12; - 4'd4: CASE_cntrl_sqTypeReg_2_12_3_12_4_20_16__q4 = 7'd20; - default: CASE_cntrl_sqTypeReg_2_12_3_12_4_20_16__q4 = 7'd16; - endcase - end - always@(cntrl_sqTypeReg or b__h63258 or b__h63254) - begin - case (cntrl_sqTypeReg) - 4'd2, 4'd3: - CASE_cntrl_sqTypeReg_2_b3254_3_b3254_4_24_b3258__q5 = b__h63254; - 4'd4: CASE_cntrl_sqTypeReg_2_b3254_3_b3254_4_24_b3258__q5 = 7'd24; - default: CASE_cntrl_sqTypeReg_2_b3254_3_b3254_4_24_b3258__q5 = - b__h63258; - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT or - cntrl_sqTypeReg or - CASE_cntrl_sqTypeReg_2_28_3_28_32__q2 or - CASE_cntrl_sqTypeReg_2_b3244_3_b3244_b3246__q3 or - CASE_cntrl_sqTypeReg_2_12_3_12_4_20_16__q4 or - CASE_cntrl_sqTypeReg_2_b3254_3_b3254_4_24_b3258__q5 or - b__h63254 or b__h63258) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0: value__h68654 = CASE_cntrl_sqTypeReg_2_28_3_28_32__q2; - 4'd1: value__h68654 = CASE_cntrl_sqTypeReg_2_b3244_3_b3244_b3246__q3; - 4'd2: value__h68654 = CASE_cntrl_sqTypeReg_2_12_3_12_4_20_16__q4; - 4'd3: - value__h68654 = CASE_cntrl_sqTypeReg_2_b3254_3_b3254_4_24_b3258__q5; - 4'd4: value__h68654 = (cntrl_sqTypeReg == 4'd2) ? 7'd28 : 7'd32; - 4'd9: value__h68654 = (cntrl_sqTypeReg == 4'd2) ? b__h63254 : b__h63258; - default: value__h68654 = (cntrl_sqTypeReg == 4'd2) ? 7'd40 : 7'd44; - endcase - end - always@(cntrl_pmtuReg or - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT or - b__h52254 or b__h52264 or b__h52274 or b__h52284) - begin - case (cntrl_pmtuReg) - 3'd1: x__h52371 = b__h52254; - 3'd2: x__h52371 = b__h52264; - 3'd3: x__h52371 = b__h52274; - 3'd4: x__h52371 = b__h52284; - default: x__h52371 = - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[489:478]; - endcase - end - always@(cntrl_pmtuReg or - a__h52293 or a__h52253 or a__h52263 or a__h52273 or a__h52283) - begin - case (cntrl_pmtuReg) - 3'd1: x__h52242 = a__h52253; - 3'd2: x__h52242 = a__h52263; - 3'd3: x__h52242 = a__h52273; - 3'd4: x__h52242 = a__h52283; - default: x__h52242 = a__h52293; - endcase - end - always@(dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT or - b__h9346 or b__h9356 or b__h9366 or b__h9376) - begin - case (dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[2:0]) - 3'd1: pmtuResidue__h9230 = b__h9346; - 3'd2: pmtuResidue__h9230 = b__h9356; - 3'd3: pmtuResidue__h9230 = b__h9366; - 3'd4: pmtuResidue__h9230 = b__h9376; - default: pmtuResidue__h9230 = - dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[14:3]; - endcase - end - always@(cntrl_maxTimeOutReg) - begin - case (cntrl_maxTimeOutReg) - 5'd0: x__h32835 = 42'd0; - 5'd1: x__h32835 = 42'd1366; - 5'd2: x__h32835 = 42'd2731; - 5'd3: x__h32835 = 42'd5462; - 5'd4: x__h32835 = 42'd10923; - 5'd5: x__h32835 = 42'd21846; - 5'd6: x__h32835 = 42'd43691; - 5'd7: x__h32835 = 42'd87382; - 5'd8: x__h32835 = 42'd174763; - 5'd9: x__h32835 = 42'd349526; - 5'd10: x__h32835 = 42'd699051; - 5'd11: x__h32835 = 42'd1398102; - 5'd12: x__h32835 = 42'd2796203; - 5'd13: x__h32835 = 42'd5592406; - 5'd14: x__h32835 = 42'd11184811; - 5'd15: x__h32835 = 42'd22369622; - 5'd16: x__h32835 = 42'd44739243; - 5'd17: x__h32835 = 42'd89478486; - 5'd18: x__h32835 = 42'd178956971; - 5'd19: x__h32835 = 42'd357913942; - 5'd20: x__h32835 = 42'd715827883; - 5'd21: x__h32835 = 42'd1431655766; - 5'd22: x__h32835 = 42'h000AAAAAAAB; - 5'd23: x__h32835 = 42'h00155555556; - 5'd24: x__h32835 = 42'h002AAAAAAAB; - 5'd25: x__h32835 = 42'h00555555556; - 5'd26: x__h32835 = 42'h00AAAAAAAAB; - 5'd27: x__h32835 = 42'h01555555556; - 5'd28: x__h32835 = 42'h02AAAAAAAAB; - 5'd29: x__h32835 = 42'h05555555556; - 5'd30: x__h32835 = 42'h0AAAAAAAAAB; - 5'd31: x__h32835 = 42'h15555555556; - endcase - end - always@(cntrl_reqQ_D_OUT or cntrl_stateReg) - begin - case (cntrl_reqQ_D_OUT[300:299]) - 2'd0, 2'd1, 2'd2: - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d60 = - cntrl_reqQ_D_OUT[212:209]; - 2'd3: - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d60 = - cntrl_stateReg; - endcase - end - always@(cntrl_reqQ_D_OUT or cntrl_pkeyReg) - begin - case (cntrl_reqQ_D_OUT[300:299]) - 2'd0, 2'd1, 2'd2: - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d99 = - cntrl_reqQ_D_OUT[53:38]; - 2'd3: - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d99 = - cntrl_pkeyReg; - endcase - end - always@(cntrl_reqQ_D_OUT or cntrl_qpAccessFlagsReg) - begin - case (cntrl_reqQ_D_OUT[300:299]) - 2'd0, 2'd1, 2'd2: - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d95 = - cntrl_reqQ_D_OUT[101:94]; - 2'd3: - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d95 = - cntrl_qpAccessFlagsReg; - endcase - end - always@(cntrl_reqQ_D_OUT or - cntrl_maxTimeOutReg or cntrl_maxRetryCntReg or cntrl_maxRnrCntReg) - begin - case (cntrl_reqQ_D_OUT[300:299]) - 2'd0, 2'd1, 2'd2: - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d155 = - cntrl_reqQ_D_OUT[15:5]; - 2'd3: - IF_cntrl_reqQ_first__7_BITS_300_TO_299_8_EQ_1__ETC___d155 = - { cntrl_maxTimeOutReg, - cntrl_maxRetryCntReg, - cntrl_maxRnrCntReg }; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d861 = - sq_pendingWorkReqBuf_dataVec_0[226]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d861 = - sq_pendingWorkReqBuf_dataVec_1[226]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d861 = - sq_pendingWorkReqBuf_dataVec_2[226]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d861 = - sq_pendingWorkReqBuf_dataVec_3[226]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d951 = - sq_pendingWorkReqBuf_dataVec_0[77]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d951 = - sq_pendingWorkReqBuf_dataVec_1[77]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d951 = - sq_pendingWorkReqBuf_dataVec_2[77]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d951 = - sq_pendingWorkReqBuf_dataVec_3[77]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d894 = - sq_pendingWorkReqBuf_dataVec_0[160]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d894 = - sq_pendingWorkReqBuf_dataVec_1[160]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d894 = - sq_pendingWorkReqBuf_dataVec_2[160]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d894 = - sq_pendingWorkReqBuf_dataVec_3[160]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1001 = - sq_pendingWorkReqBuf_dataVec_0[1]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1001 = - sq_pendingWorkReqBuf_dataVec_1[1]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1001 = - sq_pendingWorkReqBuf_dataVec_2[1]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1001 = - sq_pendingWorkReqBuf_dataVec_3[1]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463 = - sq_pendingWorkReqBuf_dataVec_0[678:615]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463 = - sq_pendingWorkReqBuf_dataVec_1[678:615]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463 = - sq_pendingWorkReqBuf_dataVec_2[678:615]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463 = - sq_pendingWorkReqBuf_dataVec_3[678:615]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473 = - !sq_pendingWorkReqBuf_dataVec_0[77]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473 = - !sq_pendingWorkReqBuf_dataVec_1[77]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473 = - !sq_pendingWorkReqBuf_dataVec_2[77]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473 = - !sq_pendingWorkReqBuf_dataVec_3[77]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474 = - sq_pendingWorkReqBuf_dataVec_0[77]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474 = - sq_pendingWorkReqBuf_dataVec_1[77]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474 = - sq_pendingWorkReqBuf_dataVec_2[77]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474 = - sq_pendingWorkReqBuf_dataVec_3[77]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492 = - sq_pendingWorkReqBuf_dataVec_0[52]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492 = - sq_pendingWorkReqBuf_dataVec_1[52]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492 = - sq_pendingWorkReqBuf_dataVec_2[52]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492 = - sq_pendingWorkReqBuf_dataVec_3[52]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491 = - !sq_pendingWorkReqBuf_dataVec_0[52]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491 = - !sq_pendingWorkReqBuf_dataVec_1[52]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491 = - !sq_pendingWorkReqBuf_dataVec_2[52]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491 = - !sq_pendingWorkReqBuf_dataVec_3[52]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1620 = - sq_pendingWorkReqBuf_dataVec_0[357]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1620 = - sq_pendingWorkReqBuf_dataVec_1[357]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1620 = - sq_pendingWorkReqBuf_dataVec_2[357]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1620 = - sq_pendingWorkReqBuf_dataVec_3[357]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525 = - sq_pendingWorkReqBuf_dataVec_0[605:542]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525 = - sq_pendingWorkReqBuf_dataVec_1[605:542]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525 = - sq_pendingWorkReqBuf_dataVec_2[605:542]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525 = - sq_pendingWorkReqBuf_dataVec_3[605:542]; - endcase - end - always@(cntrl_pmtuReg or - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525 or - sq_retryHandler_psnDiffReg) - begin - case (cntrl_pmtuReg) - 3'd1: - x__h39125 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[63:8] + - { 32'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[7:0] }; - 3'd2: - x__h39125 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[63:9] + - { 31'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[8:0] }; - 3'd3: - x__h39125 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[63:10] + - { 30'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[9:0] }; - 3'd4: - x__h39125 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[63:11] + - { 29'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[10:0] }; - default: x__h39125 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[63:12] + - { 28'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525[11:0] }; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592 = - sq_pendingWorkReqBuf_dataVec_0[477:414]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592 = - sq_pendingWorkReqBuf_dataVec_1[477:414]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592 = - sq_pendingWorkReqBuf_dataVec_2[477:414]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592 = - sq_pendingWorkReqBuf_dataVec_3[477:414]; - endcase - end - always@(cntrl_pmtuReg or - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592 or - sq_retryHandler_psnDiffReg) - begin - case (cntrl_pmtuReg) - 3'd1: - x__h39664 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[63:8] + - { 32'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[7:0] }; - 3'd2: - x__h39664 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[63:9] + - { 31'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[8:0] }; - 3'd3: - x__h39664 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[63:10] + - { 30'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[9:0] }; - 3'd4: - x__h39664 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[63:11] + - { 29'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[10:0] }; - default: x__h39664 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[63:12] + - { 28'd0, sq_retryHandler_psnDiffReg }, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592[11:0] }; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1621 = - sq_pendingWorkReqBuf_dataVec_0[356]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1621 = - sq_pendingWorkReqBuf_dataVec_1[356]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1621 = - sq_pendingWorkReqBuf_dataVec_2[356]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1621 = - sq_pendingWorkReqBuf_dataVec_3[356]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d828 = - sq_pendingWorkReqBuf_dataVec_0[356]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d828 = - sq_pendingWorkReqBuf_dataVec_1[356]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d828 = - sq_pendingWorkReqBuf_dataVec_2[356]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d828 = - sq_pendingWorkReqBuf_dataVec_3[356]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1631 = - sq_pendingWorkReqBuf_dataVec_0[160]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1631 = - sq_pendingWorkReqBuf_dataVec_1[160]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1631 = - sq_pendingWorkReqBuf_dataVec_2[160]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1631 = - sq_pendingWorkReqBuf_dataVec_3[160]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1626 = - sq_pendingWorkReqBuf_dataVec_0[226]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1626 = - sq_pendingWorkReqBuf_dataVec_1[226]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1626 = - sq_pendingWorkReqBuf_dataVec_2[226]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1626 = - sq_pendingWorkReqBuf_dataVec_3[226]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1634 = - sq_pendingWorkReqBuf_dataVec_0[135]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1634 = - sq_pendingWorkReqBuf_dataVec_1[135]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1634 = - sq_pendingWorkReqBuf_dataVec_2[135]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1634 = - sq_pendingWorkReqBuf_dataVec_3[135]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d911 = - sq_pendingWorkReqBuf_dataVec_0[135]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d911 = - sq_pendingWorkReqBuf_dataVec_1[135]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d911 = - sq_pendingWorkReqBuf_dataVec_2[135]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d911 = - sq_pendingWorkReqBuf_dataVec_3[135]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1629 = - sq_pendingWorkReqBuf_dataVec_0[193]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1629 = - sq_pendingWorkReqBuf_dataVec_1[193]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1629 = - sq_pendingWorkReqBuf_dataVec_2[193]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1629 = - sq_pendingWorkReqBuf_dataVec_3[193]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d878 = - sq_pendingWorkReqBuf_dataVec_0[193]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d878 = - sq_pendingWorkReqBuf_dataVec_1[193]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d878 = - sq_pendingWorkReqBuf_dataVec_2[193]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d878 = - sq_pendingWorkReqBuf_dataVec_3[193]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1624 = - sq_pendingWorkReqBuf_dataVec_0[291]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1624 = - sq_pendingWorkReqBuf_dataVec_1[291]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1624 = - sq_pendingWorkReqBuf_dataVec_2[291]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1624 = - sq_pendingWorkReqBuf_dataVec_3[291]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d845 = - sq_pendingWorkReqBuf_dataVec_0[291]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d845 = - sq_pendingWorkReqBuf_dataVec_1[291]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d845 = - sq_pendingWorkReqBuf_dataVec_2[291]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d845 = - sq_pendingWorkReqBuf_dataVec_3[291]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d822 = - sq_pendingWorkReqBuf_dataVec_0[357]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d822 = - sq_pendingWorkReqBuf_dataVec_1[357]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d822 = - sq_pendingWorkReqBuf_dataVec_2[357]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d822 = - sq_pendingWorkReqBuf_dataVec_3[357]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618 = - sq_pendingWorkReqBuf_dataVec_0[413:382]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618 = - sq_pendingWorkReqBuf_dataVec_1[413:382]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618 = - sq_pendingWorkReqBuf_dataVec_2[413:382]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618 = - sq_pendingWorkReqBuf_dataVec_3[413:382]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d810 = - sq_pendingWorkReqBuf_dataVec_0[413:382]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d810 = - sq_pendingWorkReqBuf_dataVec_1[413:382]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d810 = - sq_pendingWorkReqBuf_dataVec_2[413:382]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d810 = - sq_pendingWorkReqBuf_dataVec_3[413:382]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d984 = - sq_pendingWorkReqBuf_dataVec_0[27]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d984 = - sq_pendingWorkReqBuf_dataVec_1[27]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d984 = - sq_pendingWorkReqBuf_dataVec_2[27]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d984 = - sq_pendingWorkReqBuf_dataVec_3[27]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649 = - sq_pendingWorkReqBuf_dataVec_0[27]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649 = - sq_pendingWorkReqBuf_dataVec_1[27]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649 = - sq_pendingWorkReqBuf_dataVec_2[27]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649 = - sq_pendingWorkReqBuf_dataVec_3[27]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652 = - sq_pendingWorkReqBuf_dataVec_0[1]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652 = - sq_pendingWorkReqBuf_dataVec_1[1]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652 = - sq_pendingWorkReqBuf_dataVec_2[1]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652 = - sq_pendingWorkReqBuf_dataVec_3[1]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d968 = - sq_pendingWorkReqBuf_dataVec_0[52]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d968 = - sq_pendingWorkReqBuf_dataVec_1[52]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d968 = - sq_pendingWorkReqBuf_dataVec_2[52]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d968 = - sq_pendingWorkReqBuf_dataVec_3[52]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562 = - sq_pendingWorkReqBuf_dataVec_0[509:478]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562 = - sq_pendingWorkReqBuf_dataVec_1[509:478]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562 = - sq_pendingWorkReqBuf_dataVec_2[509:478]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562 = - sq_pendingWorkReqBuf_dataVec_3[509:478]; - endcase - end - always@(cntrl_pmtuReg or - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562 or - sq_retryHandler_psnDiffReg) - begin - case (cntrl_pmtuReg) - 3'd1: - x__h39399 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[31:8] - - sq_retryHandler_psnDiffReg, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[7:0] }; - 3'd2: - x__h39399 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[31:9] - - sq_retryHandler_psnDiffReg[22:0], - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[8:0] }; - 3'd3: - x__h39399 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[31:10] - - sq_retryHandler_psnDiffReg[21:0], - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[9:0] }; - 3'd4: - x__h39399 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[31:11] - - sq_retryHandler_psnDiffReg[20:0], - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[10:0] }; - default: x__h39399 = - { SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[31:12] - - sq_retryHandler_psnDiffReg[19:0], - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562[11:0] }; - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT or cntrl_sqTypeReg) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0, 4'd1: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2711 = - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9; - 4'd2, 4'd3: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2711 = - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd4 && - cntrl_sqTypeReg != 4'd9; - 4'd4, 4'd9: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2711 = - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd9; - default: IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2711 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd5 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd6 || - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd9; - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT or cntrl_sqTypeReg) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0, 4'd1, 4'd2, 4'd3: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2722 = - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd9; - default: IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d2722 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd9 || - cntrl_sqTypeReg != 4'd2 && cntrl_sqTypeReg != 4'd9; - endcase - end - always@(cntrl_sqTypeReg) - begin - case (cntrl_sqTypeReg) - 4'd2: IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208 = 3'd0; - 4'd3: IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208 = 3'd1; - 4'd4: IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208 = 3'd3; - default: IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_0_ELSE_IF_ETC___d3208 = - 3'd5; - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? 5'd10 : 5'd6; - 4'd1: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? 5'd11 : 5'd6; - 4'd2: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? 5'd4 : 5'd0; - 4'd3: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? 5'd5 : 5'd0; - 4'd4: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222 = 5'd12; - 4'd5: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222 = 5'd19; - 4'd9: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7] ? 5'd23 : 5'd0; - default: IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3222 = - 5'd20; - endcase - end - always@(cntrl_sqTypeReg or a__h63241 or a__h63239) - begin - case (cntrl_sqTypeReg) - 4'd2, 4'd3: CASE_cntrl_sqTypeReg_2_a3239_3_a3239_a3241__q6 = a__h63239; - default: CASE_cntrl_sqTypeReg_2_a3239_3_a3239_a3241__q6 = a__h63241; - endcase - end - always@(cntrl_sqTypeReg or a__h63245 or a__h63243) - begin - case (cntrl_sqTypeReg) - 4'd2, 4'd3: CASE_cntrl_sqTypeReg_2_a3243_3_a3243_a3245__q7 = a__h63243; - default: CASE_cntrl_sqTypeReg_2_a3243_3_a3243_a3245__q7 = a__h63245; - endcase - end - always@(cntrl_sqTypeReg or a__h63251 or a__h63247 or a__h63249) - begin - case (cntrl_sqTypeReg) - 4'd2, 4'd3: - CASE_cntrl_sqTypeReg_2_a3247_3_a3247_4_a3249_a_ETC__q8 = a__h63247; - 4'd4: - CASE_cntrl_sqTypeReg_2_a3247_3_a3247_4_a3249_a_ETC__q8 = a__h63249; - default: CASE_cntrl_sqTypeReg_2_a3247_3_a3247_4_a3249_a_ETC__q8 = - a__h63251; - endcase - end - always@(cntrl_sqTypeReg or a__h63257 or a__h63253 or a__h63255) - begin - case (cntrl_sqTypeReg) - 4'd2, 4'd3: - CASE_cntrl_sqTypeReg_2_a3253_3_a3253_4_a3255_a_ETC__q9 = a__h63253; - 4'd4: - CASE_cntrl_sqTypeReg_2_a3253_3_a3253_4_a3255_a_ETC__q9 = a__h63255; - default: CASE_cntrl_sqTypeReg_2_a3253_3_a3253_4_a3255_a_ETC__q9 = - a__h63257; - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT or - cntrl_sqTypeReg or - a__h63269 or - a__h63272 or - CASE_cntrl_sqTypeReg_2_a3239_3_a3239_a3241__q6 or - CASE_cntrl_sqTypeReg_2_a3243_3_a3243_a3245__q7 or - CASE_cntrl_sqTypeReg_2_a3247_3_a3247_4_a3249_a_ETC__q8 or - CASE_cntrl_sqTypeReg_2_a3253_3_a3253_4_a3255_a_ETC__q9 or - a__h63239 or a__h63241 or a__h63259 or a__h63261) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0: value__h63238 = CASE_cntrl_sqTypeReg_2_a3239_3_a3239_a3241__q6; - 4'd1: value__h63238 = CASE_cntrl_sqTypeReg_2_a3243_3_a3243_a3245__q7; - 4'd2: - value__h63238 = - CASE_cntrl_sqTypeReg_2_a3247_3_a3247_4_a3249_a_ETC__q8; - 4'd3: - value__h63238 = - CASE_cntrl_sqTypeReg_2_a3253_3_a3253_4_a3255_a_ETC__q9; - 4'd4: value__h63238 = (cntrl_sqTypeReg == 4'd2) ? a__h63239 : a__h63241; - 4'd9: value__h63238 = (cntrl_sqTypeReg == 4'd2) ? a__h63259 : a__h63261; - default: value__h63238 = - (cntrl_sqTypeReg == 4'd2) ? a__h63269 : a__h63272; - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? 5'd8 : 5'd7; - 4'd1: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? 5'd9 : 5'd7; - 4'd2: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? 5'd2 : 5'd1; - 4'd3: - IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? 5'd3 : 5'd1; - default: IF_sq_reqGenSQ_reqHeaderPrepareQ_first__665_BI_ETC___d3300 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] ? 5'd22 : 5'd1; - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT or - cntrl_sqTypeReg or - a__h69903 or - a__h69905 or - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_cntrl__ETC___d3311 or - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_sq_req_ETC___d3316) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0, 4'd2: - value__h69886 = - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_cntrl__ETC___d3311; - 4'd1, 4'd3: - value__h69886 = - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_sq_req_ETC___d3316; - default: value__h69886 = - (cntrl_sqTypeReg == 4'd2) ? a__h69903 : a__h69905; - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT or - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_sq_req_ETC___d3349 or - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_12_ELSE_16___d3346) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0, 4'd2: - value__h72405 = - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_12_ELSE_16___d3346; - 4'd1: - value__h72405 = - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_sq_req_ETC___d3349; - default: value__h72405 = - IF_cntrl_sqTypeReg_887_EQ_2_888_THEN_IF_sq_req_ETC___d3349; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd0; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd0; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd0; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd0; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd1; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd1; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd1; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd1; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd2; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd2; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd2; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd2; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd3; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd3; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd3; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3780 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd3; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd4; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd4; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd4; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3791 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd4; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd5; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd5; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd5; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3803 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd5; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd6; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd6; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd6; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3816 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd6; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd7; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd7; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd7; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3830 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd7; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd8; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd8; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd8; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3845 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd8; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd9; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd9; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd9; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3861 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd9; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd10; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd10; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd10; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3878 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd10; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd11; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd11; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd11; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3896 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd11; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd12; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd12; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd12; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3915 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd12; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3935 = - sq_pendingWorkReqBuf_dataVec_0[614:611] == 4'd14; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3935 = - sq_pendingWorkReqBuf_dataVec_1[614:611] == 4'd14; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3935 = - sq_pendingWorkReqBuf_dataVec_2[614:611] == 4'd14; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3935 = - sq_pendingWorkReqBuf_dataVec_3[614:611] == 4'd14; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994 = - !sq_pendingWorkReqBuf_dataVec_0[357]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994 = - !sq_pendingWorkReqBuf_dataVec_1[357]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994 = - !sq_pendingWorkReqBuf_dataVec_2[357]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994 = - !sq_pendingWorkReqBuf_dataVec_3[357]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012 = - !sq_pendingWorkReqBuf_dataVec_0[291]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012 = - !sq_pendingWorkReqBuf_dataVec_1[291]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012 = - !sq_pendingWorkReqBuf_dataVec_2[291]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012 = - !sq_pendingWorkReqBuf_dataVec_3[291]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003 = - !sq_pendingWorkReqBuf_dataVec_0[356]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003 = - !sq_pendingWorkReqBuf_dataVec_1[356]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003 = - !sq_pendingWorkReqBuf_dataVec_2[356]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003 = - !sq_pendingWorkReqBuf_dataVec_3[356]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021 = - !sq_pendingWorkReqBuf_dataVec_0[226]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021 = - !sq_pendingWorkReqBuf_dataVec_1[226]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021 = - !sq_pendingWorkReqBuf_dataVec_2[226]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021 = - !sq_pendingWorkReqBuf_dataVec_3[226]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030 = - !sq_pendingWorkReqBuf_dataVec_0[193]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030 = - !sq_pendingWorkReqBuf_dataVec_1[193]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030 = - !sq_pendingWorkReqBuf_dataVec_2[193]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030 = - !sq_pendingWorkReqBuf_dataVec_3[193]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039 = - !sq_pendingWorkReqBuf_dataVec_0[160]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039 = - !sq_pendingWorkReqBuf_dataVec_1[160]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039 = - !sq_pendingWorkReqBuf_dataVec_2[160]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039 = - !sq_pendingWorkReqBuf_dataVec_3[160]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048 = - !sq_pendingWorkReqBuf_dataVec_0[135]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048 = - !sq_pendingWorkReqBuf_dataVec_1[135]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048 = - !sq_pendingWorkReqBuf_dataVec_2[135]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048 = - !sq_pendingWorkReqBuf_dataVec_3[135]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057 = - !sq_pendingWorkReqBuf_dataVec_0[110]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057 = - !sq_pendingWorkReqBuf_dataVec_1[110]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057 = - !sq_pendingWorkReqBuf_dataVec_2[110]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057 = - !sq_pendingWorkReqBuf_dataVec_3[110]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 = - !sq_pendingWorkReqBuf_dataVec_0[1]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 = - !sq_pendingWorkReqBuf_dataVec_1[1]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 = - !sq_pendingWorkReqBuf_dataVec_2[1]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 = - !sq_pendingWorkReqBuf_dataVec_3[1]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083 = - !sq_pendingWorkReqBuf_dataVec_0[0]; - 2'd1: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083 = - !sq_pendingWorkReqBuf_dataVec_1[0]; - 2'd2: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083 = - !sq_pendingWorkReqBuf_dataVec_2[0]; - 2'd3: - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083 = - !sq_pendingWorkReqBuf_dataVec_3[0]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521 = - sq_pendingWorkReqBuf_dataVec_0[614:611]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521 = - sq_pendingWorkReqBuf_dataVec_1[614:611]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521 = - sq_pendingWorkReqBuf_dataVec_2[614:611]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1521 = - sq_pendingWorkReqBuf_dataVec_3[614:611]; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b1000, 4'b1010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q10 = - sq_respHandleSQ_preStageRespTypeReg != 2'd0; - default: CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q10 = - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg != 2'd0; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b1000, 4'b1010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q11 = - sq_respHandleSQ_preStageRespTypeReg != 2'd2; - default: CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q11 = - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg != 2'd2; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b1000, 4'b1010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q12 = - sq_respHandleSQ_preStageRespTypeReg != 2'd1; - default: CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q12 = - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg != 2'd1; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b1000, 4'b1010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q13 = - sq_respHandleSQ_preStageRespTypeReg != 2'd1 && - sq_respHandleSQ_preStageRespTypeReg != 2'd2 && - sq_respHandleSQ_preStageRespTypeReg != 2'd0; - default: CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q13 = - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg != 2'd1 && - sq_respHandleSQ_preStageRespTypeReg != 2'd2 && - sq_respHandleSQ_preStageRespTypeReg != 2'd0; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b0100: - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4271 = - !sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]; - 4'b1000, 4'b1010: - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4271 = - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - sq_respHandleSQ_preStageRespTypeReg == 2'd0; - default: IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4271 = - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg == 2'd2; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b0100: - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4275 = - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]; - 4'b1000, 4'b1010: - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4275 = - sq_respHandleSQ_preStageRespTypeReg != 2'd2 && - sq_respHandleSQ_preStageRespTypeReg != 2'd0; - default: IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4275 = - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0001 || - sq_respHandleSQ_preStageRespTypeReg != 2'd2; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d798 = - sq_pendingWorkReqBuf_dataVec_0[509:478]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d798 = - sq_pendingWorkReqBuf_dataVec_1[509:478]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d798 = - sq_pendingWorkReqBuf_dataVec_2[509:478]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d798 = - sq_pendingWorkReqBuf_dataVec_3[509:478]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d786 = - sq_pendingWorkReqBuf_dataVec_0[605:542]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d786 = - sq_pendingWorkReqBuf_dataVec_1[605:542]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d786 = - sq_pendingWorkReqBuf_dataVec_2[605:542]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d786 = - sq_pendingWorkReqBuf_dataVec_3[605:542]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d774 = - sq_pendingWorkReqBuf_dataVec_0[614:611]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d774 = - sq_pendingWorkReqBuf_dataVec_1[614:611]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d774 = - sq_pendingWorkReqBuf_dataVec_2[614:611]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d774 = - sq_pendingWorkReqBuf_dataVec_3[614:611]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d768 = - sq_pendingWorkReqBuf_dataVec_0[678:615]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d768 = - sq_pendingWorkReqBuf_dataVec_1[678:615]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d768 = - sq_pendingWorkReqBuf_dataVec_2[678:615]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d768 = - sq_pendingWorkReqBuf_dataVec_3[678:615]; - endcase - end - always@(sq_respHandleSQ_pendingRespQ_D_OUT) - begin - case (sq_respHandleSQ_pendingRespQ_D_OUT[141:137]) - 5'd13, 5'd14, 5'd15, 5'd16: - IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4824 = - sq_respHandleSQ_pendingRespQ_D_OUT[1408:1405] != 4'd4; - 5'd18: - IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4824 = - sq_respHandleSQ_pendingRespQ_D_OUT[1408:1405] != 4'd5 && - sq_respHandleSQ_pendingRespQ_D_OUT[1408:1405] != 4'd6; - default: IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4824 = - sq_respHandleSQ_pendingRespQ_D_OUT[141:137] != 5'd17; - endcase - end - always@(sq_respHandleSQ_preRdmaOpCodeReg or - sq_respHandleSQ_pendingRespQ_D_OUT) - begin - case (sq_respHandleSQ_preRdmaOpCodeReg) - 5'd13, 5'd14: - CASE_sq_respHandleSQ_preRdmaOpCodeReg_13_NOT_s_ETC__q14 = - sq_respHandleSQ_pendingRespQ_D_OUT[141:137] != 5'd14 && - sq_respHandleSQ_pendingRespQ_D_OUT[141:137] != 5'd15; - default: CASE_sq_respHandleSQ_preRdmaOpCodeReg_13_NOT_s_ETC__q14 = - sq_respHandleSQ_preRdmaOpCodeReg != 5'd15 && - sq_respHandleSQ_preRdmaOpCodeReg != 5'd16 && - sq_respHandleSQ_preRdmaOpCodeReg != 5'd17 && - sq_respHandleSQ_preRdmaOpCodeReg != 5'd18; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N or - sq_retryHandler_retryRespQ_EMPTY_N) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd9, 4'd10: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q15 = - sq_retryHandler_retryRespQ_EMPTY_N; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q15 = - sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q15 or - sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd1, 4'd3: - IF_sq_respHandleSQ_pendingRetryCheckQ_first__9_ETC___d4989 = - sq_respHandleSQ_pendingRetryCheckQ_EMPTY_N; - default: IF_sq_respHandleSQ_pendingRetryCheckQ_first__9_ETC___d4989 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd5 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd6 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd4 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd7 || - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q15; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - sq_retryHandler_retryRespQ_D_OUT) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd9, 4'd10: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q16 = - !sq_retryHandler_retryRespQ_D_OUT; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q16 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd8; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q16) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd1: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q17 = - !sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1398] && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] != 4'd4 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] != 4'd5 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] != 4'd6; - 4'd2: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q17 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4; - 4'd3: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q17 = - !sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1398] && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] != 4'd4 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] != 4'd5 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] != 4'd6 || - !sq_respHandleSQ_pendingRetryCheckQ_D_OUT[12]; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q17 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd6 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd7 && - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q16; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561 = - sq_pendingWorkReqBuf_dataVec_0[541:510]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561 = - sq_pendingWorkReqBuf_dataVec_1[541:510]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561 = - sq_pendingWorkReqBuf_dataVec_2[541:510]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561 = - sq_pendingWorkReqBuf_dataVec_3[541:510]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1636 = - sq_pendingWorkReqBuf_dataVec_0[110]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1636 = - sq_pendingWorkReqBuf_dataVec_1[110]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1636 = - sq_pendingWorkReqBuf_dataVec_2[110]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1636 = - sq_pendingWorkReqBuf_dataVec_3[110]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619 = - sq_pendingWorkReqBuf_dataVec_0[381:358]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619 = - sq_pendingWorkReqBuf_dataVec_1[381:358]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619 = - sq_pendingWorkReqBuf_dataVec_2[381:358]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619 = - sq_pendingWorkReqBuf_dataVec_3[381:358]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650 = - sq_pendingWorkReqBuf_dataVec_0[26:2]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650 = - sq_pendingWorkReqBuf_dataVec_1[26:2]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650 = - sq_pendingWorkReqBuf_dataVec_2[26:2]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650 = - sq_pendingWorkReqBuf_dataVec_3[26:2]; - endcase - end - always@(sq_pendingWorkReqBuf_deqPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_deqPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1653 = - sq_pendingWorkReqBuf_dataVec_0[0]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1653 = - sq_pendingWorkReqBuf_dataVec_1[0]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1653 = - sq_pendingWorkReqBuf_dataVec_2[0]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1653 = - sq_pendingWorkReqBuf_dataVec_3[0]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1007 = - sq_pendingWorkReqBuf_dataVec_0[0]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1007 = - sq_pendingWorkReqBuf_dataVec_1[0]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1007 = - sq_pendingWorkReqBuf_dataVec_2[0]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1007 = - sq_pendingWorkReqBuf_dataVec_3[0]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d961 = - sq_pendingWorkReqBuf_dataVec_0[76:53]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d961 = - sq_pendingWorkReqBuf_dataVec_1[76:53]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d961 = - sq_pendingWorkReqBuf_dataVec_2[76:53]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d961 = - sq_pendingWorkReqBuf_dataVec_3[76:53]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d904 = - sq_pendingWorkReqBuf_dataVec_0[159:136]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d904 = - sq_pendingWorkReqBuf_dataVec_1[159:136]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d904 = - sq_pendingWorkReqBuf_dataVec_2[159:136]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d904 = - sq_pendingWorkReqBuf_dataVec_3[159:136]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d994 = - sq_pendingWorkReqBuf_dataVec_0[26:2]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d994 = - sq_pendingWorkReqBuf_dataVec_1[26:2]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d994 = - sq_pendingWorkReqBuf_dataVec_2[26:2]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d994 = - sq_pendingWorkReqBuf_dataVec_3[26:2]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d871 = - sq_pendingWorkReqBuf_dataVec_0[225:194]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d871 = - sq_pendingWorkReqBuf_dataVec_1[225:194]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d871 = - sq_pendingWorkReqBuf_dataVec_2[225:194]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d871 = - sq_pendingWorkReqBuf_dataVec_3[225:194]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d978 = - sq_pendingWorkReqBuf_dataVec_0[51:28]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d978 = - sq_pendingWorkReqBuf_dataVec_1[51:28]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d978 = - sq_pendingWorkReqBuf_dataVec_2[51:28]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d978 = - sq_pendingWorkReqBuf_dataVec_3[51:28]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d921 = - sq_pendingWorkReqBuf_dataVec_0[134:111]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d921 = - sq_pendingWorkReqBuf_dataVec_1[134:111]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d921 = - sq_pendingWorkReqBuf_dataVec_2[134:111]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d921 = - sq_pendingWorkReqBuf_dataVec_3[134:111]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d927 = - sq_pendingWorkReqBuf_dataVec_0[110]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d927 = - sq_pendingWorkReqBuf_dataVec_1[110]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d927 = - sq_pendingWorkReqBuf_dataVec_2[110]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d927 = - sq_pendingWorkReqBuf_dataVec_3[110]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d937 = - sq_pendingWorkReqBuf_dataVec_0[109:78]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d937 = - sq_pendingWorkReqBuf_dataVec_1[109:78]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d937 = - sq_pendingWorkReqBuf_dataVec_2[109:78]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d937 = - sq_pendingWorkReqBuf_dataVec_3[109:78]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d838 = - sq_pendingWorkReqBuf_dataVec_0[355:292]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d838 = - sq_pendingWorkReqBuf_dataVec_1[355:292]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d838 = - sq_pendingWorkReqBuf_dataVec_2[355:292]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d838 = - sq_pendingWorkReqBuf_dataVec_3[355:292]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d855 = - sq_pendingWorkReqBuf_dataVec_0[290:227]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d855 = - sq_pendingWorkReqBuf_dataVec_1[290:227]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d855 = - sq_pendingWorkReqBuf_dataVec_2[290:227]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d855 = - sq_pendingWorkReqBuf_dataVec_3[290:227]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d888 = - sq_pendingWorkReqBuf_dataVec_0[192:161]; - 2'd1: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d888 = - sq_pendingWorkReqBuf_dataVec_1[192:161]; - 2'd2: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d888 = - sq_pendingWorkReqBuf_dataVec_2[192:161]; - 2'd3: - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d888 = - sq_pendingWorkReqBuf_dataVec_3[192:161]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d816 = - sq_pendingWorkReqBuf_dataVec_0[381:358]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d816 = - sq_pendingWorkReqBuf_dataVec_1[381:358]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d816 = - sq_pendingWorkReqBuf_dataVec_2[381:358]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d816 = - sq_pendingWorkReqBuf_dataVec_3[381:358]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d804 = - sq_pendingWorkReqBuf_dataVec_0[477:414]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d804 = - sq_pendingWorkReqBuf_dataVec_1[477:414]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d804 = - sq_pendingWorkReqBuf_dataVec_2[477:414]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d804 = - sq_pendingWorkReqBuf_dataVec_3[477:414]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d792 = - sq_pendingWorkReqBuf_dataVec_0[541:510]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d792 = - sq_pendingWorkReqBuf_dataVec_1[541:510]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d792 = - sq_pendingWorkReqBuf_dataVec_2[541:510]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d792 = - sq_pendingWorkReqBuf_dataVec_3[541:510]; - endcase - end - always@(sq_pendingWorkReqBuf_scanPtrReg or - sq_pendingWorkReqBuf_dataVec_0 or - sq_pendingWorkReqBuf_dataVec_1 or - sq_pendingWorkReqBuf_dataVec_2 or sq_pendingWorkReqBuf_dataVec_3) - begin - case (sq_pendingWorkReqBuf_scanPtrReg) - 2'd0: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d780 = - sq_pendingWorkReqBuf_dataVec_0[610:606]; - 2'd1: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d780 = - sq_pendingWorkReqBuf_dataVec_1[610:606]; - 2'd2: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d780 = - sq_pendingWorkReqBuf_dataVec_2[610:606]; - 2'd3: - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d780 = - sq_pendingWorkReqBuf_dataVec_3[610:606]; - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT or cntrl_sqTypeReg) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0, 4'd1: - CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q18 = - cntrl_sqTypeReg == 4'd2 || cntrl_sqTypeReg == 4'd3 || - cntrl_sqTypeReg == 4'd9; - 4'd2, 4'd3: - CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q18 = - cntrl_sqTypeReg == 4'd2 || cntrl_sqTypeReg == 4'd3 || - cntrl_sqTypeReg == 4'd4 || - cntrl_sqTypeReg == 4'd9; - 4'd4, 4'd9: - CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q18 = - cntrl_sqTypeReg == 4'd2 || cntrl_sqTypeReg == 4'd9; - default: CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q18 = - (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5 || - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6) && - (cntrl_sqTypeReg == 4'd2 || cntrl_sqTypeReg == 4'd9); - endcase - end - always@(sq_reqGenSQ_reqHeaderPrepareQ_D_OUT or cntrl_sqTypeReg) - begin - case (sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618]) - 4'd0, 4'd1, 4'd2, 4'd3: - CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q19 = - cntrl_sqTypeReg == 4'd2 || cntrl_sqTypeReg == 4'd9; - default: CASE_sq_reqGenSQ_reqHeaderPrepareQD_OUT_BITS__ETC__q19 = - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd9 && - (cntrl_sqTypeReg == 4'd2 || cntrl_sqTypeReg == 4'd9); - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - sq_retryHandler_retryRespQ_D_OUT) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd9, 4'd10: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q20 = - sq_retryHandler_retryRespQ_D_OUT; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q20 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd8; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q20) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd1: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q21 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1398] || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd4 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd5 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd6; - 4'd2: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q21 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] == 2'd3 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] == 5'd1 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] == 5'd2 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] == 5'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] == 5'd4); - 4'd3: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q21 = - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1398] || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd4 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd5 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd6) && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[12]; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q21 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd6 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd7 || - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q20; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38]) - 5'd1: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q22 = 5'd9; - 5'd2: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q22 = 5'd10; - 5'd3: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q22 = 5'd11; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q22 = 5'd15; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q22) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd0: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q23 = 5'd7; - 4'd1, 4'd3: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q23 = 5'd0; - 4'd2: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q23 = - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q22; - 4'd6: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q23 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[142] ? 5'd1 : 5'd0; - 4'd7: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q23 = 5'd5; - 4'd9, 4'd10: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q23 = 5'd12; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q23 = 5'd20; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - IF_sq_retryHandler_retryRespQ_first__023_THEN__ETC___d5182) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q24 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[2:1]; - 4'd9, 4'd10: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q24 = - IF_sq_retryHandler_retryRespQ_first__023_THEN__ETC___d5182; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q24 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[2:1]; - endcase - end - always@(sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespTypeReg) - 2'd0, 2'd2: - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4308 = 2'd0; - 2'd1: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4308 = 2'd2; - 2'd3: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4308 = 2'd3; - endcase - end - always@(sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespTypeReg) - 2'd0: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4312 = 2'd1; - 2'd1: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4312 = 2'd2; - 2'd2: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4312 = 2'd0; - 2'd3: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4312 = 2'd3; - endcase - end - always@(sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespTypeReg) - 2'd0: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4298 = 4'd0; - 2'd1: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4298 = 4'd1; - 2'd2: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4298 = 4'd2; - 2'd3: - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4298 = 4'd14; - endcase - end - always@(sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespTypeReg) - 2'd0: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4302 = 4'd3; - 2'd1: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4302 = 4'd4; - 2'd2: IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4302 = 4'd5; - 2'd3: - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4302 = 4'd14; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd1, 4'd2, 4'd3: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q25 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[8]; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q25 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd5 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd6 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd4 || - ((sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd7) ? - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[8] : - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd9 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == - 4'd10 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[8]); - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - sq_retryHandler_retryRespQ_D_OUT) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd9, 4'd10: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q26 = - sq_retryHandler_retryRespQ_D_OUT || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[7]; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q26 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd8 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[7]; - endcase - end - always@(sq_respHandleSQ_pendingRetryCheckQ_D_OUT or - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q26) - begin - case (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3]) - 4'd1: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q27 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1398] || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd4 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd5 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd6; - 4'd3: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q27 = - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1398] || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd4 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd5 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[1405:1402] == 4'd6) && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[12] || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[7]; - 4'd5: - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q27 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[7]; - default: CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q27 = - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd6 || - ((sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd4) ? - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[7] : - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd7 || - CASE_sq_respHandleSQ_pendingRetryCheckQD_OUT__ETC__q26); - endcase - end - always@(sq_respHandleSQ_incomingRespQ_D_OUT) - begin - case (sq_respHandleSQ_incomingRespQ_D_OUT[3:0]) - 4'd0, 4'd3: - CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd3; - 4'd1, 4'd4: - CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd9; - 4'd2, 4'd5: - CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd2; - 4'd6: CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd1; - 4'd7: CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd10; - 4'd8: CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd5; - 4'd9, 4'd11: - CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd4; - 4'd10: - CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = - sq_respHandleSQ_incomingRespQ_D_OUT[142] ? 4'd6 : 4'd3; - 4'd12: CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd7; - 4'd13: CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd8; - default: CASE_sq_respHandleSQ_incomingRespQD_OUT_BITS__ETC__q28 = 4'd13; - endcase - end - always@(respPktPipe_metaDataQ_D_OUT) - begin - case (respPktPipe_metaDataQ_D_OUT[527:523]) - 5'd0: CASE_respPktPipe_metaDataQD_OUT_BITS_527_TO_5_ETC__q29 = 2'd1; - 5'd1, 5'd2, 5'd3, 5'd4: - CASE_respPktPipe_metaDataQD_OUT_BITS_527_TO_5_ETC__q29 = 2'd2; - default: CASE_respPktPipe_metaDataQD_OUT_BITS_527_TO_5_ETC__q29 = 2'd3; - endcase - end - always@(respPktPipe_metaDataQ_D_OUT or - CASE_respPktPipe_metaDataQD_OUT_BITS_527_TO_5_ETC__q29) - begin - case (respPktPipe_metaDataQ_D_OUT[529:528]) - 2'd0, 2'd1: - CASE_respPktPipe_metaDataQD_OUT_BITS_529_TO_5_ETC__q30 = - respPktPipe_metaDataQ_D_OUT[529:528]; - 2'd2: CASE_respPktPipe_metaDataQD_OUT_BITS_529_TO_5_ETC__q30 = 2'd3; - 2'd3: - CASE_respPktPipe_metaDataQD_OUT_BITS_529_TO_5_ETC__q30 = - CASE_respPktPipe_metaDataQD_OUT_BITS_527_TO_5_ETC__q29; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4312 or - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4308) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b0001, 4'b0010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q31 = - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4312; - 4'b0100: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q31 = - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4] ? - 2'd2 : - 2'd0; - 4'b1000, 4'b1010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q31 = - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4308; - default: CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q31 = 2'd2; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4302 or - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4298) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b0001, 4'b0010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q32 = - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4302; - 4'b0100: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q32 = - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4] ? - 4'd7 : - 4'd6; - 4'b1000, 4'b1010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q32 = - IF_sq_respHandleSQ_preStageRespTypeReg_177_EQ__ETC___d4298; - default: CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q32 = 4'd8; - endcase - end - always@(sq_respHandleSQ_pendingRespQ_D_OUT) - begin - case (sq_respHandleSQ_pendingRespQ_D_OUT[47:46]) - 2'd1: CASE_sq_respHandleSQ_pendingRespQD_OUT_BITS_4_ETC__q33 = 3'd1; - 2'd3: - CASE_sq_respHandleSQ_pendingRespQD_OUT_BITS_4_ETC__q33 = - (sq_respHandleSQ_pendingRespQ_D_OUT[45:41] == 5'd0) ? - 3'd2 : - 3'd0; - default: CASE_sq_respHandleSQ_pendingRespQD_OUT_BITS_4_ETC__q33 = 3'd0; - endcase - end - always@(sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT) - begin - case (sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565]) - 4'd0, 4'd1: - CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34 = 8'd1; - 4'd2, 4'd3, 4'd9: - CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34 = 8'd0; - 4'd4: CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34 = 8'd2; - 4'd5: CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34 = 8'd3; - 4'd6: CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34 = 8'd4; - 4'd7: CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34 = 8'd6; - 4'd8: CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34 = 8'd5; - default: CASE_sq_workCompGenSQ_pendingWorkCompQ4SQD_OU_ETC__q34 = 8'd7; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b0100: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q35 = - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]; - 4'b1000, 4'b1010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q35 = - sq_respHandleSQ_preStageRespTypeReg == 2'd1; - default: CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q35 = - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0001 || - sq_respHandleSQ_preStageRespTypeReg == 2'd1; - endcase - end - always@(sq_respHandleSQ_preStageRespAndWorkReqRelationReg or - sq_respHandleSQ_preStageRespTypeReg) - begin - case (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0]) - 4'b0100: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q36 = - !sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]; - 4'b1000, 4'b1010: - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q36 = - sq_respHandleSQ_preStageRespTypeReg != 2'd1; - default: CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q36 = - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg != 2'd1; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - cntrl_nextStateReg <= `BSV_ASSIGNMENT_DELAY 5'd10; - cntrl_pendingRecvReqNumReg <= `BSV_ASSIGNMENT_DELAY 8'd4; - cntrl_pendingWorkReqNumReg <= `BSV_ASSIGNMENT_DELAY 8'd4; - cntrl_preReqOpCodeReg <= `BSV_ASSIGNMENT_DELAY 5'd4; - cntrl_preStateReg <= `BSV_ASSIGNMENT_DELAY 4'd7; - cntrl_qpDestroyReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - cntrl_setStateErrReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - cntrl_stateReg <= `BSV_ASSIGNMENT_DELAY 4'd0; - dmaReadCntrl4SQ_addrChunkSrv_busyReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - dmaReadCntrl4SQ_addrChunkSrv_isFirstReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - dmaReadCntrl4SQ_cancelReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - dmaReadCntrl4SQ_gracefulStopReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - payloadGenerator4SQ_isNormalStateReg <= `BSV_ASSIGNMENT_DELAY 1'd1; - payloadGenerator4SQ_payloadBufQ_rCache <= `BSV_ASSIGNMENT_DELAY - 301'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - payloadGenerator4SQ_payloadBufQ_rRdPtr <= `BSV_ASSIGNMENT_DELAY 10'd0; - payloadGenerator4SQ_payloadBufQ_rWrPtr <= `BSV_ASSIGNMENT_DELAY 10'd0; - rqDmaReadCancelReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - rqDmaWriteCancelReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sqDmaReadCancelReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg <= `BSV_ASSIGNMENT_DELAY - 8'd0; - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg <= `BSV_ASSIGNMENT_DELAY - 1'd0; - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg <= `BSV_ASSIGNMENT_DELAY - 1'd0; - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg <= `BSV_ASSIGNMENT_DELAY - 9'd170; - sq_pendingWorkReqBuf_clearReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_pendingWorkReqBuf_deqPtrReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - sq_pendingWorkReqBuf_emptyReg <= `BSV_ASSIGNMENT_DELAY 1'd1; - sq_pendingWorkReqBuf_enqPtrReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - sq_pendingWorkReqBuf_fullReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_pendingWorkReqBuf_popReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_pendingWorkReqBuf_preScanRestartReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_pendingWorkReqBuf_preScanStartReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_pendingWorkReqBuf_pushReg <= `BSV_ASSIGNMENT_DELAY - 680'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_pendingWorkReqBuf_scanDoneReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_pendingWorkReqBuf_scanStartReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_pendingWorkReqBuf_scanStateReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - sq_pendingWorkReqBuf_scanStopReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_reqGenSQ_isFirstOrOnlyReqPktReg <= `BSV_ASSIGNMENT_DELAY 1'd1; - sq_reqGenSQ_isNormalStateReg <= `BSV_ASSIGNMENT_DELAY 1'd1; - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg <= `BSV_ASSIGNMENT_DELAY - 1'd0; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg <= `BSV_ASSIGNMENT_DELAY - 2'd0; - sq_respHandleSQ_errOccurredReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_respHandleSQ_hasInternalErrReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_respHandleSQ_hasTimeOutErrReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_respHandleSQ_preRdmaOpCodeReg <= `BSV_ASSIGNMENT_DELAY 5'd17; - sq_respHandleSQ_preStageStateReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - sq_respHandleSQ_recvErrRespReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_respHandleSQ_recvRetryRespReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_respHandleSQ_retryFlushReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_retryHandler_pauseRetryHandleReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - sq_retryHandler_retryCntrlStateReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - sq_retryHandler_retryHandleStateReg <= `BSV_ASSIGNMENT_DELAY 3'd0; - sq_workCompGenSQ_workCompGenStateReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - end - else - begin - if (cntrl_nextStateReg_EN) - cntrl_nextStateReg <= `BSV_ASSIGNMENT_DELAY cntrl_nextStateReg_D_IN; - if (cntrl_pendingRecvReqNumReg_EN) - cntrl_pendingRecvReqNumReg <= `BSV_ASSIGNMENT_DELAY - cntrl_pendingRecvReqNumReg_D_IN; - if (cntrl_pendingWorkReqNumReg_EN) - cntrl_pendingWorkReqNumReg <= `BSV_ASSIGNMENT_DELAY - cntrl_pendingWorkReqNumReg_D_IN; - if (cntrl_preReqOpCodeReg_EN) - cntrl_preReqOpCodeReg <= `BSV_ASSIGNMENT_DELAY - cntrl_preReqOpCodeReg_D_IN; - if (cntrl_preStateReg_EN) - cntrl_preStateReg <= `BSV_ASSIGNMENT_DELAY cntrl_preStateReg_D_IN; - if (cntrl_qpDestroyReg_EN) - cntrl_qpDestroyReg <= `BSV_ASSIGNMENT_DELAY cntrl_qpDestroyReg_D_IN; - if (cntrl_setStateErrReg_EN) - cntrl_setStateErrReg <= `BSV_ASSIGNMENT_DELAY - cntrl_setStateErrReg_D_IN; - if (cntrl_stateReg_EN) - cntrl_stateReg <= `BSV_ASSIGNMENT_DELAY cntrl_stateReg_D_IN; - if (dmaReadCntrl4SQ_addrChunkSrv_busyReg_EN) - dmaReadCntrl4SQ_addrChunkSrv_busyReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_addrChunkSrv_busyReg_D_IN; - if (dmaReadCntrl4SQ_addrChunkSrv_isFirstReg_EN) - dmaReadCntrl4SQ_addrChunkSrv_isFirstReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_addrChunkSrv_isFirstReg_D_IN; - if (dmaReadCntrl4SQ_cancelReg_EN) - dmaReadCntrl4SQ_cancelReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_cancelReg_D_IN; - if (dmaReadCntrl4SQ_gracefulStopReg_EN) - dmaReadCntrl4SQ_gracefulStopReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_gracefulStopReg_D_IN; - if (payloadGenerator4SQ_isNormalStateReg_EN) - payloadGenerator4SQ_isNormalStateReg <= `BSV_ASSIGNMENT_DELAY - payloadGenerator4SQ_isNormalStateReg_D_IN; - if (payloadGenerator4SQ_payloadBufQ_rCache_EN) - payloadGenerator4SQ_payloadBufQ_rCache <= `BSV_ASSIGNMENT_DELAY - payloadGenerator4SQ_payloadBufQ_rCache_D_IN; - if (payloadGenerator4SQ_payloadBufQ_rRdPtr_EN) - payloadGenerator4SQ_payloadBufQ_rRdPtr <= `BSV_ASSIGNMENT_DELAY - payloadGenerator4SQ_payloadBufQ_rRdPtr_D_IN; - if (payloadGenerator4SQ_payloadBufQ_rWrPtr_EN) - payloadGenerator4SQ_payloadBufQ_rWrPtr <= `BSV_ASSIGNMENT_DELAY - payloadGenerator4SQ_payloadBufQ_rWrPtr_D_IN; - if (rqDmaReadCancelReg_EN) - rqDmaReadCancelReg <= `BSV_ASSIGNMENT_DELAY rqDmaReadCancelReg_D_IN; - if (rqDmaWriteCancelReg_EN) - rqDmaWriteCancelReg <= `BSV_ASSIGNMENT_DELAY - rqDmaWriteCancelReg_D_IN; - if (sqDmaReadCancelReg_EN) - sqDmaReadCancelReg <= `BSV_ASSIGNMENT_DELAY sqDmaReadCancelReg_D_IN; - if (sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_EN) - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg <= `BSV_ASSIGNMENT_DELAY - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg_D_IN; - if (sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_EN) - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg <= `BSV_ASSIGNMENT_DELAY - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg_D_IN; - if (sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_EN) - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg <= `BSV_ASSIGNMENT_DELAY - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg_D_IN; - if (sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_EN) - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg <= `BSV_ASSIGNMENT_DELAY - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg_D_IN; - if (sq_pendingWorkReqBuf_clearReg_EN) - sq_pendingWorkReqBuf_clearReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_clearReg_D_IN; - if (sq_pendingWorkReqBuf_deqPtrReg_EN) - sq_pendingWorkReqBuf_deqPtrReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_deqPtrReg_D_IN; - if (sq_pendingWorkReqBuf_emptyReg_EN) - sq_pendingWorkReqBuf_emptyReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_emptyReg_D_IN; - if (sq_pendingWorkReqBuf_enqPtrReg_EN) - sq_pendingWorkReqBuf_enqPtrReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_enqPtrReg_D_IN; - if (sq_pendingWorkReqBuf_fullReg_EN) - sq_pendingWorkReqBuf_fullReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_fullReg_D_IN; - if (sq_pendingWorkReqBuf_popReg_EN) - sq_pendingWorkReqBuf_popReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_popReg_D_IN; - if (sq_pendingWorkReqBuf_preScanRestartReg_EN) - sq_pendingWorkReqBuf_preScanRestartReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_preScanRestartReg_D_IN; - if (sq_pendingWorkReqBuf_preScanStartReg_EN) - sq_pendingWorkReqBuf_preScanStartReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_preScanStartReg_D_IN; - if (sq_pendingWorkReqBuf_pushReg_EN) - sq_pendingWorkReqBuf_pushReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_pushReg_D_IN; - if (sq_pendingWorkReqBuf_scanDoneReg_EN) - sq_pendingWorkReqBuf_scanDoneReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_scanDoneReg_D_IN; - if (sq_pendingWorkReqBuf_scanStartReg_EN) - sq_pendingWorkReqBuf_scanStartReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_scanStartReg_D_IN; - if (sq_pendingWorkReqBuf_scanStateReg_EN) - sq_pendingWorkReqBuf_scanStateReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_scanStateReg_D_IN; - if (sq_pendingWorkReqBuf_scanStopReg_EN) - sq_pendingWorkReqBuf_scanStopReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_scanStopReg_D_IN; - if (sq_reqGenSQ_isFirstOrOnlyReqPktReg_EN) - sq_reqGenSQ_isFirstOrOnlyReqPktReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_isFirstOrOnlyReqPktReg_D_IN; - if (sq_reqGenSQ_isNormalStateReg_EN) - sq_reqGenSQ_isNormalStateReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_isNormalStateReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg_D_IN; - if (sq_respHandleSQ_errOccurredReg_EN) - sq_respHandleSQ_errOccurredReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_errOccurredReg_D_IN; - if (sq_respHandleSQ_hasInternalErrReg_EN) - sq_respHandleSQ_hasInternalErrReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_hasInternalErrReg_D_IN; - if (sq_respHandleSQ_hasTimeOutErrReg_EN) - sq_respHandleSQ_hasTimeOutErrReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_hasTimeOutErrReg_D_IN; - if (sq_respHandleSQ_preRdmaOpCodeReg_EN) - sq_respHandleSQ_preRdmaOpCodeReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preRdmaOpCodeReg_D_IN; - if (sq_respHandleSQ_preStageStateReg_EN) - sq_respHandleSQ_preStageStateReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preStageStateReg_D_IN; - if (sq_respHandleSQ_recvErrRespReg_EN) - sq_respHandleSQ_recvErrRespReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_recvErrRespReg_D_IN; - if (sq_respHandleSQ_recvRetryRespReg_EN) - sq_respHandleSQ_recvRetryRespReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_recvRetryRespReg_D_IN; - if (sq_respHandleSQ_retryFlushReg_EN) - sq_respHandleSQ_retryFlushReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_retryFlushReg_D_IN; - if (sq_retryHandler_pauseRetryHandleReg_EN) - sq_retryHandler_pauseRetryHandleReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_pauseRetryHandleReg_D_IN; - if (sq_retryHandler_retryCntrlStateReg_EN) - sq_retryHandler_retryCntrlStateReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_retryCntrlStateReg_D_IN; - if (sq_retryHandler_retryHandleStateReg_EN) - sq_retryHandler_retryHandleStateReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_retryHandleStateReg_D_IN; - if (sq_workCompGenSQ_workCompGenStateReg_EN) - sq_workCompGenSQ_workCompGenStateReg <= `BSV_ASSIGNMENT_DELAY - sq_workCompGenSQ_workCompGenStateReg_D_IN; - end - if (cntrl_dqpnReg_EN) - cntrl_dqpnReg <= `BSV_ASSIGNMENT_DELAY cntrl_dqpnReg_D_IN; - if (cntrl_epsnReg_EN) - cntrl_epsnReg <= `BSV_ASSIGNMENT_DELAY cntrl_epsnReg_D_IN; - if (cntrl_errFlushDoneReg_EN) - cntrl_errFlushDoneReg <= `BSV_ASSIGNMENT_DELAY - cntrl_errFlushDoneReg_D_IN; - if (cntrl_maxRetryCntReg_EN) - cntrl_maxRetryCntReg <= `BSV_ASSIGNMENT_DELAY cntrl_maxRetryCntReg_D_IN; - if (cntrl_maxRnrCntReg_EN) - cntrl_maxRnrCntReg <= `BSV_ASSIGNMENT_DELAY cntrl_maxRnrCntReg_D_IN; - if (cntrl_maxTimeOutReg_EN) - cntrl_maxTimeOutReg <= `BSV_ASSIGNMENT_DELAY cntrl_maxTimeOutReg_D_IN; - if (cntrl_minRnrTimerReg_EN) - cntrl_minRnrTimerReg <= `BSV_ASSIGNMENT_DELAY cntrl_minRnrTimerReg_D_IN; - if (cntrl_npsnReg_EN) - cntrl_npsnReg <= `BSV_ASSIGNMENT_DELAY cntrl_npsnReg_D_IN; - if (cntrl_pendingDestReadAtomicReqNumReg_EN) - cntrl_pendingDestReadAtomicReqNumReg <= `BSV_ASSIGNMENT_DELAY - cntrl_pendingDestReadAtomicReqNumReg_D_IN; - if (cntrl_pendingReadAtomicReqNumReg_EN) - cntrl_pendingReadAtomicReqNumReg <= `BSV_ASSIGNMENT_DELAY - cntrl_pendingReadAtomicReqNumReg_D_IN; - if (cntrl_pkeyReg_EN) - cntrl_pkeyReg <= `BSV_ASSIGNMENT_DELAY cntrl_pkeyReg_D_IN; - if (cntrl_pmtuReg_EN) - cntrl_pmtuReg <= `BSV_ASSIGNMENT_DELAY cntrl_pmtuReg_D_IN; - if (cntrl_qkeyReg_EN) - cntrl_qkeyReg <= `BSV_ASSIGNMENT_DELAY cntrl_qkeyReg_D_IN; - if (cntrl_qpAccessFlagsReg_EN) - cntrl_qpAccessFlagsReg <= `BSV_ASSIGNMENT_DELAY - cntrl_qpAccessFlagsReg_D_IN; - if (cntrl_sqSigAllReg_EN) - cntrl_sqSigAllReg <= `BSV_ASSIGNMENT_DELAY cntrl_sqSigAllReg_D_IN; - if (cntrl_sqTypeReg_EN) - cntrl_sqTypeReg <= `BSV_ASSIGNMENT_DELAY cntrl_sqTypeReg_D_IN; - if (cntrl_sqpnReg_EN) - cntrl_sqpnReg <= `BSV_ASSIGNMENT_DELAY cntrl_sqpnReg_D_IN; - if (dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_EN) - dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg_D_IN; - if (dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_EN) - dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg_D_IN; - if (dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg_EN) - dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg_D_IN; - if (dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_EN) - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg_D_IN; - if (dmaReadCntrl4SQ_addrChunkSrv_pmtuReg_EN) - dmaReadCntrl4SQ_addrChunkSrv_pmtuReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_addrChunkSrv_pmtuReg_D_IN; - if (dmaReadCntrl4SQ_addrChunkSrv_residueReg_EN) - dmaReadCntrl4SQ_addrChunkSrv_residueReg <= `BSV_ASSIGNMENT_DELAY - dmaReadCntrl4SQ_addrChunkSrv_residueReg_D_IN; - if (sq_pendingWorkReqBuf_dataVec_0_EN) - sq_pendingWorkReqBuf_dataVec_0 <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_dataVec_0_D_IN; - if (sq_pendingWorkReqBuf_dataVec_1_EN) - sq_pendingWorkReqBuf_dataVec_1 <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_dataVec_1_D_IN; - if (sq_pendingWorkReqBuf_dataVec_2_EN) - sq_pendingWorkReqBuf_dataVec_2 <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_dataVec_2_D_IN; - if (sq_pendingWorkReqBuf_dataVec_3_EN) - sq_pendingWorkReqBuf_dataVec_3 <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_dataVec_3_D_IN; - if (sq_pendingWorkReqBuf_headReg_EN) - sq_pendingWorkReqBuf_headReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_headReg_D_IN; - if (sq_pendingWorkReqBuf_scanAlmostDoneReg_EN) - sq_pendingWorkReqBuf_scanAlmostDoneReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_scanAlmostDoneReg_D_IN; - if (sq_pendingWorkReqBuf_scanPtrReg_EN) - sq_pendingWorkReqBuf_scanPtrReg <= `BSV_ASSIGNMENT_DELAY - sq_pendingWorkReqBuf_scanPtrReg_D_IN; - if (sq_reqGenSQ_curPsnReg_EN) - sq_reqGenSQ_curPsnReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_curPsnReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg_D_IN; - if (sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_EN) - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg_D_IN; - if (sq_reqGenSQ_remainingPktNumReg_EN) - sq_reqGenSQ_remainingPktNumReg <= `BSV_ASSIGNMENT_DELAY - sq_reqGenSQ_remainingPktNumReg_D_IN; - if (sq_respHandleSQ_nextReadRespWriteAddrReg_EN) - sq_respHandleSQ_nextReadRespWriteAddrReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_nextReadRespWriteAddrReg_D_IN; - if (sq_respHandleSQ_preStageDeqPendingWorkReqReg_EN) - sq_respHandleSQ_preStageDeqPendingWorkReqReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preStageDeqPendingWorkReqReg_D_IN; - if (sq_respHandleSQ_preStageDeqPktMetaDataReg_EN) - sq_respHandleSQ_preStageDeqPktMetaDataReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preStageDeqPktMetaDataReg_D_IN; - if (sq_respHandleSQ_preStagePktMetaDataReg_EN) - sq_respHandleSQ_preStagePktMetaDataReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preStagePktMetaDataReg_D_IN; - if (sq_respHandleSQ_preStageReqPktInfoReg_EN) - sq_respHandleSQ_preStageReqPktInfoReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preStageReqPktInfoReg_D_IN; - if (sq_respHandleSQ_preStageRespAndWorkReqRelationReg_EN) - sq_respHandleSQ_preStageRespAndWorkReqRelationReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preStageRespAndWorkReqRelationReg_D_IN; - if (sq_respHandleSQ_preStageRespTypeReg_EN) - sq_respHandleSQ_preStageRespTypeReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preStageRespTypeReg_D_IN; - if (sq_respHandleSQ_preStageWorkCompReqTypeReg_EN) - sq_respHandleSQ_preStageWorkCompReqTypeReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preStageWorkCompReqTypeReg_D_IN; - if (sq_respHandleSQ_preStageWorkReqAckTypeReg_EN) - sq_respHandleSQ_preStageWorkReqAckTypeReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_preStageWorkReqAckTypeReg_D_IN; - if (sq_respHandleSQ_remainingReadRespLenReg_EN) - sq_respHandleSQ_remainingReadRespLenReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_remainingReadRespLenReg_D_IN; - if (sq_respHandleSQ_retryResetReqReg_EN) - sq_respHandleSQ_retryResetReqReg <= `BSV_ASSIGNMENT_DELAY - sq_respHandleSQ_retryResetReqReg_D_IN; - if (sq_retryHandler_disableRetryCntReg_EN) - sq_retryHandler_disableRetryCntReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_disableRetryCntReg_D_IN; - if (sq_retryHandler_disableTimeOutReg_EN) - sq_retryHandler_disableTimeOutReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_disableTimeOutReg_D_IN; - if (sq_retryHandler_isRnrWaitCntZeroReg_EN) - sq_retryHandler_isRnrWaitCntZeroReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_isRnrWaitCntZeroReg_D_IN; - if (sq_retryHandler_isTimeOutCntHighPartZeroReg_EN) - sq_retryHandler_isTimeOutCntHighPartZeroReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_isTimeOutCntHighPartZeroReg_D_IN; - if (sq_retryHandler_isTimeOutCntLowPartZeroReg_EN) - sq_retryHandler_isTimeOutCntLowPartZeroReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_isTimeOutCntLowPartZeroReg_D_IN; - if (sq_retryHandler_psnDiffReg_EN) - sq_retryHandler_psnDiffReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_psnDiffReg_D_IN; - if (sq_retryHandler_retryCntReg_EN) - sq_retryHandler_retryCntReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_retryCntReg_D_IN; - if (sq_retryHandler_retryReasonReg_EN) - sq_retryHandler_retryReasonReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_retryReasonReg_D_IN; - if (sq_retryHandler_retryRnrTimerReg_EN) - sq_retryHandler_retryRnrTimerReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_retryRnrTimerReg_D_IN; - if (sq_retryHandler_retryStartPsnReg_EN) - sq_retryHandler_retryStartPsnReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_retryStartPsnReg_D_IN; - if (sq_retryHandler_retryWorkReqIdReg_EN) - sq_retryHandler_retryWorkReqIdReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_retryWorkReqIdReg_D_IN; - if (sq_retryHandler_rnrCntReg_EN) - sq_retryHandler_rnrCntReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_rnrCntReg_D_IN; - if (sq_retryHandler_rnrWaitCntReg_EN) - sq_retryHandler_rnrWaitCntReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_rnrWaitCntReg_D_IN; - if (sq_retryHandler_timeOutCntReg_EN) - sq_retryHandler_timeOutCntReg <= `BSV_ASSIGNMENT_DELAY - sq_retryHandler_timeOutCntReg_D_IN; - if (sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_EN) - sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg <= `BSV_ASSIGNMENT_DELAY - sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg_D_IN; - if (sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_EN) - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg <= `BSV_ASSIGNMENT_DELAY - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg_D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - cntrl_dqpnReg = 24'hAAAAAA; - cntrl_epsnReg = 24'hAAAAAA; - cntrl_errFlushDoneReg = 1'h0; - cntrl_maxRetryCntReg = 3'h2; - cntrl_maxRnrCntReg = 3'h2; - cntrl_maxTimeOutReg = 5'h0A; - cntrl_minRnrTimerReg = 5'h0A; - cntrl_nextStateReg = 5'h0A; - cntrl_npsnReg = 24'hAAAAAA; - cntrl_pendingDestReadAtomicReqNumReg = 8'hAA; - cntrl_pendingReadAtomicReqNumReg = 8'hAA; - cntrl_pendingRecvReqNumReg = 8'hAA; - cntrl_pendingWorkReqNumReg = 8'hAA; - cntrl_pkeyReg = 16'hAAAA; - cntrl_pmtuReg = 3'h2; - cntrl_preReqOpCodeReg = 5'h0A; - cntrl_preStateReg = 4'hA; - cntrl_qkeyReg = 32'hAAAAAAAA; - cntrl_qpAccessFlagsReg = 8'hAA; - cntrl_qpDestroyReg = 1'h0; - cntrl_setStateErrReg = 1'h0; - cntrl_sqSigAllReg = 1'h0; - cntrl_sqTypeReg = 4'hA; - cntrl_sqpnReg = 24'hAAAAAA; - cntrl_stateReg = 4'hA; - dmaReadCntrl4SQ_addrChunkSrv_busyReg = 1'h0; - dmaReadCntrl4SQ_addrChunkSrv_chunkAddrReg = 64'hAAAAAAAAAAAAAAAA; - dmaReadCntrl4SQ_addrChunkSrv_fullPktLenReg = 13'h0AAA; - dmaReadCntrl4SQ_addrChunkSrv_isFirstReg = 1'h0; - dmaReadCntrl4SQ_addrChunkSrv_isZeroResidueReg = 1'h0; - dmaReadCntrl4SQ_addrChunkSrv_pktNumReg = 25'h0AAAAAA; - dmaReadCntrl4SQ_addrChunkSrv_pmtuReg = 3'h2; - dmaReadCntrl4SQ_addrChunkSrv_residueReg = 12'hAAA; - dmaReadCntrl4SQ_cancelReg = 1'h0; - dmaReadCntrl4SQ_gracefulStopReg = 1'h0; - payloadGenerator4SQ_isNormalStateReg = 1'h0; - payloadGenerator4SQ_payloadBufQ_rCache = - 301'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - payloadGenerator4SQ_payloadBufQ_rRdPtr = 10'h2AA; - payloadGenerator4SQ_payloadBufQ_rWrPtr = 10'h2AA; - rqDmaReadCancelReg = 1'h0; - rqDmaWriteCancelReg = 1'h0; - sqDmaReadCancelReg = 1'h0; - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg = 8'hAA; - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_decrReg = 1'h0; - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_incrReg = 1'h0; - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_writeReg = 9'h0AA; - sq_pendingWorkReqBuf_clearReg = 1'h0; - sq_pendingWorkReqBuf_dataVec_0 = - 679'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_pendingWorkReqBuf_dataVec_1 = - 679'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_pendingWorkReqBuf_dataVec_2 = - 679'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_pendingWorkReqBuf_dataVec_3 = - 679'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_pendingWorkReqBuf_deqPtrReg = 2'h2; - sq_pendingWorkReqBuf_emptyReg = 1'h0; - sq_pendingWorkReqBuf_enqPtrReg = 2'h2; - sq_pendingWorkReqBuf_fullReg = 1'h0; - sq_pendingWorkReqBuf_headReg = - 680'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_pendingWorkReqBuf_popReg = 1'h0; - sq_pendingWorkReqBuf_preScanRestartReg = 1'h0; - sq_pendingWorkReqBuf_preScanStartReg = 1'h0; - sq_pendingWorkReqBuf_pushReg = - 680'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_pendingWorkReqBuf_scanAlmostDoneReg = 1'h0; - sq_pendingWorkReqBuf_scanDoneReg = 1'h0; - sq_pendingWorkReqBuf_scanPtrReg = 2'h2; - sq_pendingWorkReqBuf_scanStartReg = 1'h0; - sq_pendingWorkReqBuf_scanStateReg = 2'h2; - sq_pendingWorkReqBuf_scanStopReg = 1'h0; - sq_reqGenSQ_curPsnReg = 24'hAAAAAA; - sq_reqGenSQ_isFirstOrOnlyReqPktReg = 1'h0; - sq_reqGenSQ_isNormalStateReg = 1'h0; - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerValidReg = - 1'h0; - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_rdmaHeaderReg = - 593'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg = 2'h2; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerHasPayloadReg = - 1'h0; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidBitNumReg = - 9'h0AA; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragInvalidByteNumReg = - 6'h2A; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidBitNumReg = - 9'h0AA; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerLastFragValidByteNumReg = - 6'h2A; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_isFirstReg = 1'h0; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_preDataStreamReg = - 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_stageReg = 2'h2; - sq_reqGenSQ_remainingPktNumReg = 25'h0AAAAAA; - sq_respHandleSQ_errOccurredReg = 1'h0; - sq_respHandleSQ_hasInternalErrReg = 1'h0; - sq_respHandleSQ_hasTimeOutErrReg = 1'h0; - sq_respHandleSQ_nextReadRespWriteAddrReg = 64'hAAAAAAAAAAAAAAAA; - sq_respHandleSQ_preRdmaOpCodeReg = 5'h0A; - sq_respHandleSQ_preStageDeqPendingWorkReqReg = 1'h0; - sq_respHandleSQ_preStageDeqPktMetaDataReg = 1'h0; - sq_respHandleSQ_preStagePktMetaDataReg = - 649'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_respHandleSQ_preStageReqPktInfoReg = - 135'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - sq_respHandleSQ_preStageRespAndWorkReqRelationReg = 5'h0A; - sq_respHandleSQ_preStageRespTypeReg = 2'h2; - sq_respHandleSQ_preStageStateReg = 2'h2; - sq_respHandleSQ_preStageWorkCompReqTypeReg = 2'h2; - sq_respHandleSQ_preStageWorkReqAckTypeReg = 4'hA; - sq_respHandleSQ_recvErrRespReg = 1'h0; - sq_respHandleSQ_recvRetryRespReg = 1'h0; - sq_respHandleSQ_remainingReadRespLenReg = 32'hAAAAAAAA; - sq_respHandleSQ_retryFlushReg = 1'h0; - sq_respHandleSQ_retryResetReqReg = 1'h0; - sq_retryHandler_disableRetryCntReg = 1'h0; - sq_retryHandler_disableTimeOutReg = 1'h0; - sq_retryHandler_isRnrWaitCntZeroReg = 1'h0; - sq_retryHandler_isTimeOutCntHighPartZeroReg = 1'h0; - sq_retryHandler_isTimeOutCntLowPartZeroReg = 1'h0; - sq_retryHandler_pauseRetryHandleReg = 1'h0; - sq_retryHandler_psnDiffReg = 24'hAAAAAA; - sq_retryHandler_retryCntReg = 3'h2; - sq_retryHandler_retryCntrlStateReg = 2'h2; - sq_retryHandler_retryHandleStateReg = 3'h2; - sq_retryHandler_retryReasonReg = 3'h2; - sq_retryHandler_retryRnrTimerReg = 5'h0A; - sq_retryHandler_retryStartPsnReg = 24'hAAAAAA; - sq_retryHandler_retryWorkReqIdReg = 64'hAAAAAAAAAAAAAAAA; - sq_retryHandler_rnrCntReg = 3'h2; - sq_retryHandler_rnrWaitCntReg = 27'h2AAAAAA; - sq_retryHandler_timeOutCntReg = 42'h2AAAAAAAAAA; - sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg = 64'hAAAAAAAAAAAAAAAA; - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg = 1'h0; - sq_workCompGenSQ_workCompGenStateReg = 2'h2; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd1) - begin - v__h3884 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h3884, - "\"Controller.bsv\", line 512, column 21\n", - "no QP destroy on init @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("REQ_QP_DESTROY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - begin - v__h4313 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h4313, - "\"Controller.bsv\", line 540, column 21\n", - "unreachible case @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] == 2'd0) - $display("REQ_QP_CREATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onINIT && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd1) - begin - v__h4717 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h4717, - "\"Controller.bsv\", line 576, column 21\n", - "no QP destroy on RTR @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("REQ_QP_DESTROY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - begin - v__h5169 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h5169, - "\"Controller.bsv\", line 615, column 21\n", - "unreachible case @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] == 2'd0) - $display("REQ_QP_CREATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTR && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] == 2'd1) - begin - v__h5606 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h5606, - "\"Controller.bsv\", line 651, column 21\n", - "no QP destroy on RTS @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("REQ_QP_DESTROY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - begin - v__h5829 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h5829, - "\"Controller.bsv\", line 688, column 21\n", - "unreachible case @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] == 2'd0) - $display("REQ_QP_CREATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onRTS && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] == 2'd1) - begin - v__h6391 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h6391, - "\"Controller.bsv\", line 721, column 21\n", - "no QP destroy on SQD @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("REQ_QP_DESTROY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - begin - v__h6614 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h6614, - "\"Controller.bsv\", line 758, column 21\n", - "unreachible case @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] == 2'd0) - $display("REQ_QP_CREATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onSQD && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onERR && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - begin - v__h7317 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onERR && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h7317, - "\"Controller.bsv\", line 807, column 21\n", - "unreachible case @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onERR && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onERR && cntrl_reqQ_D_OUT[300:299] == 2'd0) - $display("REQ_QP_CREATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onERR && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq && - dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:3] == 32'd0) - begin - v__h9162 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq && - dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:3] == 32'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h9162, - "\"PayloadConAndGen.bsv\", line 76, column 13\n", - "totalLen assertion @ mkAddrChunkSrv"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq && - dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:3] == 32'd0) - $display("totalLen=%0d cannot be zero", - dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:3]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_dmaReadCntrl4SQ_addrChunkSrv_recvReq && - dmaReadCntrl4SQ_addrChunkSrv_reqQ_D_OUT[34:3] == 32'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq && - payloadGenerator4SQ_payloadGenReqQ_D_OUT[36:5] == 32'd0) - begin - v__h13758 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq && - payloadGenerator4SQ_payloadGenReqQ_D_OUT[36:5] == 32'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h13758, - "\"PayloadConAndGen.bsv\", line 656, column 13\n", - "payloadGenReq.dmaReadMetaData.len assertion @ mkPayloadGenerator"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq && - payloadGenerator4SQ_payloadGenReqQ_D_OUT[36:5] == 32'd0) - $display("payloadGenReq.dmaReadMetaData.len=%0d should not be zero", - payloadGenerator4SQ_payloadGenReqQ_D_OUT[36:5]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq && - payloadGenerator4SQ_payloadGenReqQ_D_OUT[36:5] == 32'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq && - lastFragValidByteNumWithPadding__h13828 == 6'd0) - begin - v__h14296 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq && - lastFragValidByteNumWithPadding__h13828 == 6'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h14296, - "\"PayloadConAndGen.bsv\", line 671, column 13\n", - "lastFragValidByteNumWithPadding assertion @ mkPayloadGenerator"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq && - lastFragValidByteNumWithPadding__h13828 == 6'd0) - $display("lastFragValidByteNumWithPadding=%0d should not be zero", - lastFragValidByteNumWithPadding__h13828, - ", totalDmaLen=%0d, lastFragValidByteNum=%0d, padCnt=%0d", - payloadGenerator4SQ_payloadGenReqQ_D_OUT[36:5], - lastFragValidByteNum__h13827, - padCnt__h13826); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_payloadGenerator4SQ_recvPayloadGenReq && - lastFragValidByteNumWithPadding__h13828 == 6'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_sq_newPendingWorkReqPiptOut_pendingNewWork_ETC___d1707) - begin - v__h43308 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (NOT_sq_newPendingWorkReqPiptOut_pendingNewWork_ETC___d1707) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h43308, - "\"QueuePair.bsv\", line 135, column 13\n", - "pendingNewWorkReqCnt assertion @ mkNewPendingWorkReqPipeOut"); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_sq_newPendingWorkReqPiptOut_pendingNewWork_ETC___d1707) - $display("pendingNewWorkReqCnt should be less than MAX_QP_WR=%0d", - $signed(32'd4)); - if (RST_N != `BSV_RESET_VALUE) - if (NOT_sq_newPendingWorkReqPiptOut_pendingNewWork_ETC___d1707) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - cntrl_sqTypeReg != 4'd4) - begin - v__h50137 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - cntrl_sqTypeReg != 4'd4) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h50137, - "\"ReqGenSQ.bsv\", line 630, column 13\n", - "qpType assertion @ mkReqGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - cntrl_sqTypeReg != 4'd4) - $display("qpType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_sqTypeReg == 4'd8) - $display("IBV_QPT_RAW_PACKET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - cntrl_sqTypeReg != 4'd4 && - cntrl_sqTypeReg != 4'd8) - $display("IBV_QPT_XRC_RECV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - cntrl_sqTypeReg != 4'd4) - $display(" unsupported"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd9 && - cntrl_sqTypeReg != 4'd4) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd9) - begin - v__h50289 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd9) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h50289, - "\"ReqGenSQ.bsv\", line 641, column 17\n", - "SQD assertion @ mkReqGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd9) - $display("cntrlStatus.comm.isSQD="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd9) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd9) - $display(" should be RC or XRC, but qpType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg == 4'd3) - $display("IBV_QPT_UC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg == 4'd4) - $display("IBV_QPT_UD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg == 4'd8) - $display("IBV_QPT_RAW_PACKET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd9 && - cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd4 && - cntrl_sqTypeReg != 4'd8) - $display("IBV_QPT_XRC_RECV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd4 && - cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd9) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd3 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606]) - begin - v__h50515 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd3 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606]) - $display("time=%0t: wait pendingWorkReqBufNotEmpty=", v__h50515); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd3 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606] && - sq_pendingWorkReqBuf_emptyReg) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd3 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606] && - !sq_pendingWorkReqBuf_emptyReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && cntrl_stateReg == 4'd3 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606]) - $display(" to be false, when IBV_QPS_SQD or IBV_SEND_FENCE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - NOT_sq_pendingWorkReqPipeOut_pipeMuxOutQ_first_ETC___d1919) - begin - v__h50628 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - NOT_sq_pendingWorkReqPipeOut_pipeMuxOutQ_first_ETC___d1919) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h50628, - "\"ReqGenSQ.bsv\", line 667, column 13\n", - "curPendingWR.wr.sqpn assertion @ mkWorkReq2RdmaReq"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - NOT_sq_pendingWorkReqPipeOut_pipeMuxOutQ_first_ETC___d1919) - $display("curPendingWR.wr.sqpn=%h should == cntrlStatus.comm.getSQPN=%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[381:358], - cntrl_sqpnReg); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - NOT_sq_pendingWorkReqPipeOut_pipeMuxOutQ_first_ETC___d1919) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - begin - v__h50773 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h50773, - "\"ReqGenSQ.bsv\", line 677, column 17\n", - "curPendingWR.wr.len assertion @ mkWorkReq2RdmaReq"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display("curPendingWR.wr.len=%0d should be %0d for atomic WR=", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478], - $signed(32'd8)); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display("PendingWorkReq { wr="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display("WorkReq { ID=%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[678:615], - ", opcode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display("IBV_WR_ATOMIC_CMP_AND_SWP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display("IBV_WR_ATOMIC_FETCH_AND_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", flags="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display("FlagsType { flags: ", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[610:606], - " = "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606]) - $display("IBV_SEND_FENCE", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[606]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[607]) - $display("IBV_SEND_SIGNALED", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[607]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[608]) - $display("IBV_SEND_SOLICITED", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[608]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[609]) - $display("IBV_SEND_INLINE", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[609]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[610]) - $display("IBV_SEND_IP_CSUM", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[610]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[610:606] == 5'd0) - $display("IBV_SEND_NO_FLAGS", " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[610:606] != 5'd0) - $display("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", raddr=%h, rkey=%h, len=%0d, laddr=%h, lkey=%h, sqpn=%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[605:542], - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[541:510], - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478], - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[477:414], - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[413:382], - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[381:358], - ", solicited="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[357]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[357]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", comp="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[356]) - $display("tagged Valid ", - "'h%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[355:292]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[356]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", swap="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[291]) - $display("tagged Valid ", - "'h%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[290:227]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[291]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", immDt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[226]) - $display("tagged Valid ", - "'h%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[225:194]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[226]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", rkey2Inv="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[193]) - $display("tagged Valid ", - "'h%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[192:161]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[193]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", srqn="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[160]) - $display("tagged Valid ", - "'h%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[159:136]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[160]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", dqpn="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[135]) - $display("tagged Valid ", - "'h%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[134:111]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[135]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", qkey="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[110]) - $display("tagged Valid ", - "'h%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[109:78]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[110]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", startPSN="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[77]) - $display("tagged Valid ", - "'h%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[76:53]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[77]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", endPSN="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[52]) - $display("tagged Valid ", - "'h%h", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[51:28]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[52]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", pktNum="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[27]) - $display("tagged Valid %0d", - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[26:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[27]) - $display("tagged Invalid PktNum"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(", isOnlyReqPkt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[1]) - $display("tagged Valid "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[1]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[1] && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[0]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[1] && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[0]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8 && - !sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[1]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $display(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_recvWorkReq && - (sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd5 || - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[614:611] == 4'd6) && - sq_pendingWorkReqPipeOut_pipeMuxOutQ_D_OUT[509:478] != 32'd8) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31])) - begin - v__h54300 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31])) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h54300, - "\"ReqGenSQ.bsv\", line 789, column 17\n", - "curPendingWR assertion @ mkReqGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31])) - $display("curPendingWR should have valid PSN and PktNum, curPendingWR="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31])) - $display("PendingWorkReq { wr="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31])) - $display("WorkReq { ID=%h", - sq_reqGenSQ_workReqPktNumQ_D_OUT[708:645], - ", opcode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd0) - $display("IBV_WR_RDMA_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd1) - $display("IBV_WR_RDMA_WRITE_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd2) - $display("IBV_WR_SEND"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd3) - $display("IBV_WR_SEND_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd4) - $display("IBV_WR_RDMA_READ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd5) - $display("IBV_WR_ATOMIC_CMP_AND_SWP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd6) - $display("IBV_WR_ATOMIC_FETCH_AND_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd7) - $display("IBV_WR_LOCAL_INV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd8) - $display("IBV_WR_BIND_MW"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd9) - $display("IBV_WR_SEND_WITH_INV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd10) - $display("IBV_WR_TSO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd11) - $display("IBV_WR_DRIVER1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd12) - $display("IBV_WR_RDMA_READ_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] == 4'd14) - $display("IBV_WR_FLUSH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd0 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd1 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd2 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd3 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd4 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd5 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd6 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd7 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd8 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd9 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd10 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd11 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd12 && - sq_reqGenSQ_workReqPktNumQ_D_OUT[644:641] != 4'd14) - $display("IBV_WR_ATOMIC_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31])) - $display(", flags="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31])) - $display("FlagsType { flags: ", - sq_reqGenSQ_workReqPktNumQ_D_OUT[640:636], - " = "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[636]) - $display("IBV_SEND_FENCE", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[636]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[637]) - $display("IBV_SEND_SIGNALED", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[637]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - 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!sq_reqGenSQ_workReqPktNumQ_D_OUT[57]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[31] && - sq_reqGenSQ_workReqPktNumQ_D_OUT[30]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57]) && - sq_reqGenSQ_workReqPktNumQ_D_OUT[31] && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[30]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31])) - $display(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktNum4NewWorkReq && - !sq_reqGenSQ_workReqPktNumQ_D_OUT[4] && - (!sq_reqGenSQ_workReqPktNumQ_D_OUT[107] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[82] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[57] || - !sq_reqGenSQ_workReqPktNumQ_D_OUT[31])) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5]) - begin - v__h58741 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h58741, - "\"ReqGenSQ.bsv\", line 874, column 17\n", - "existing UD WR assertion @ mkReqGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5]) - $display("illegal existing UD WR with length=%0d", - sq_reqGenSQ_workReqCheckQ_D_OUT[514:483], - " larger than PMTU when TypeQP="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] && - cntrl_sqTypeReg == 4'd2) - $display("IBV_QPT_RC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] && - cntrl_sqTypeReg == 4'd3) - $display("IBV_QPT_UC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] && - cntrl_sqTypeReg == 4'd4) - $display("IBV_QPT_UD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] && - cntrl_sqTypeReg == 4'd8) - $display("IBV_QPT_RAW_PACKET"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] && - cntrl_sqTypeReg == 4'd9) - $display("IBV_QPT_XRC_SEND"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] && - cntrl_sqTypeReg != 4'd2 && - cntrl_sqTypeReg != 4'd3 && - cntrl_sqTypeReg != 4'd4 && - cntrl_sqTypeReg != 4'd8 && - cntrl_sqTypeReg != 4'd9) - $display("IBV_QPT_XRC_RECV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5]) - $display(" and isOnlyReqPkt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] && - sq_reqGenSQ_workReqCheckQ_D_OUT[6]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[6]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_checkPendingWorkReq && - !sq_reqGenSQ_workReqCheckQ_D_OUT[4] && - sq_reqGenSQ_workReqCheckQ_D_OUT[1] && - !sq_reqGenSQ_workReqCheckQ_D_OUT[5]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_countReqPkt && cntrl_sqTypeReg == 4'd4 && - !sq_reqGenSQ_reqCountQ_D_OUT[5]) - begin - v__h61335 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_countReqPkt && cntrl_sqTypeReg == 4'd4 && - !sq_reqGenSQ_reqCountQ_D_OUT[5]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h61335, - "\"ReqGenSQ.bsv\", line 933, column 13\n", - "UD assertion @ mkReqGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_countReqPkt && cntrl_sqTypeReg == 4'd4 && - !sq_reqGenSQ_reqCountQ_D_OUT[5]) - $display("illegal UD WR with length=%0d", - sq_reqGenSQ_reqCountQ_D_OUT[514:483], - " larger than PMTU when TypeQP="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_countReqPkt && cntrl_sqTypeReg == 4'd4 && - !sq_reqGenSQ_reqCountQ_D_OUT[5]) - $display("IBV_QPT_UD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_countReqPkt && cntrl_sqTypeReg == 4'd4 && - !sq_reqGenSQ_reqCountQ_D_OUT[5]) - $display(" and isOnlyReqPkt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_countReqPkt && cntrl_sqTypeReg == 4'd4 && - !sq_reqGenSQ_reqCountQ_D_OUT[5] && - sq_reqGenSQ_reqCountQ_D_OUT[6]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_countReqPkt && cntrl_sqTypeReg == 4'd4 && - !sq_reqGenSQ_reqCountQ_D_OUT[5] && - !sq_reqGenSQ_reqCountQ_D_OUT[6]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_countReqPkt && cntrl_sqTypeReg == 4'd4 && - !sq_reqGenSQ_reqCountQ_D_OUT[5]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - begin - v__h63194 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h63194, - "\"ReqGenSQ.bsv\", line 1006, column 17\n", - "maybeFirstOrOnlyHeaderGenInfo assertion @ mkReqGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display("maybeFirstOrOnlyHeaderGenInfo="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(" is not valid, and current WR="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display("WorkReq { ID=%h", - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[685:622], - ", opcode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd0) - $display("IBV_WR_RDMA_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd1) - $display("IBV_WR_RDMA_WRITE_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd2) - $display("IBV_WR_SEND"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd3) - $display("IBV_WR_SEND_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4) - $display("IBV_WR_RDMA_READ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5) - $display("IBV_WR_ATOMIC_CMP_AND_SWP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd6) - $display("IBV_WR_ATOMIC_FETCH_AND_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd7) - $display("IBV_WR_LOCAL_INV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd8) - $display("IBV_WR_BIND_MW"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2742 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd9) - $display("IBV_WR_SEND_WITH_INV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd10) - $display("IBV_WR_TSO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd11) - $display("IBV_WR_DRIVER1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd12) - $display("IBV_WR_RDMA_READ_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd14) - $display("IBV_WR_FLUSH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd0 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd1 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd2 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd3 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd4 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd5 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd6 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd7 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd8 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd9 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd10 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd11 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd12 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] != 4'd14) - $display("IBV_WR_ATOMIC_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(", flags="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display("FlagsType { flags: ", - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[617:613], - " = "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[613]) - $display("IBV_SEND_FENCE", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[613]) - 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sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[516:485], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[484:421], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[420:389], - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[388:365], - ", solicited="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[364]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2712) - $display(", comp="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - 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!sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2723) - $display(" is not valid, and current WR="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2723) - $display("WorkReq { ID=%h", - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[685:622], - ", opcode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2902 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd0) - $display("IBV_WR_RDMA_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - NOT_cntrl_sqTypeReg_887_EQ_2_888_889_AND_NOT_c_ETC___d2902 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd1) - $display("IBV_WR_RDMA_WRITE_WITH_IMM"); - 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sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[685:622], - ", opcode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd0) - $display("IBV_WR_RDMA_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd1) - $display("IBV_WR_RDMA_WRITE_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd2) - $display("IBV_WR_SEND"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd3) - $display("IBV_WR_SEND_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd4) - $display("IBV_WR_RDMA_READ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[621:618] == 4'd5) - $display("IBV_WR_ATOMIC_CMP_AND_SWP"); - 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$display(", srqn="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[167]) - $display("tagged Valid ", - "'h%h", - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[166:143]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[167]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992) - $display(", dqpn="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[142]) - $display("tagged Valid ", - "'h%h", - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[141:118]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[142]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992) - $display(", qkey="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[117]) - $display("tagged Valid ", - "'h%h", - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[116:85]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[117]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992) - $display(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992) - $display(", startPSN="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[84]) - $display("tagged Valid ", - "'h%h", - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[83:60]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[84]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992) - $display(", endPSN="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[59]) - $display("tagged Valid ", - "'h%h", - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[58:35]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[59]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992) - $display(", pktNum="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[34]) - $display("tagged Valid %0d", - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[33:9]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[34]) - $display("tagged Invalid PktNum"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992) - $display(", isOnlyReqPkt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[8]) - $display("tagged Valid "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[8]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[8] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[8] && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[7]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992 && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[8]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992) - $display(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_prepareReqHeaderGen && - !sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[6] && - sq_reqGenSQ_reqHeaderPrepareQ_D_OUT[5] && - NOT_sq_reqGenSQ_reqHeaderPrepareQ_first__665_B_ETC___d2992) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_errFlushWR && - WILL_FIRE_RL_sq_reqGenSQ_outputNewPendingWorkReq && - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[2] && - sq_reqGenSQ_workReqPayloadGenQ_D_OUT[1] && - _enq_RL_sq_reqGenSQ_outputNewPendingWorkReq_EN_sq_reqGenSQ_pendingWorkReqOutQ_wget) - $display("Error: \"ReqGenSQ.bsv\", line 1142, column 10: (R0002)\n Conflict-free rules RL_sq_reqGenSQ_errFlushWR and\n RL_sq_reqGenSQ_outputNewPendingWorkReq called conflicting methods enq and\n enq of module instance sq_reqGenSQ_pendingWorkReqOutQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_errFlushWR && - WILL_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq) - $display("Error: \"ReqGenSQ.bsv\", line 1142, column 10: (R0002)\n Conflict-free rules RL_sq_reqGenSQ_errFlushWR and\n RL_sq_reqGenSQ_issuePayloadGenReq called conflicting methods first and deq\n of module instance sq_reqGenSQ_workReqPayloadGenQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_errFlushWR && - WILL_FIRE_RL_sq_reqGenSQ_issuePayloadGenReq) - $display("Error: \"ReqGenSQ.bsv\", line 1142, column 10: (R0002)\n Conflict-free rules RL_sq_reqGenSQ_errFlushWR and\n RL_sq_reqGenSQ_issuePayloadGenReq called conflicting methods deq and deq of\n module instance sq_reqGenSQ_workReqPayloadGenQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[7:2] != - 6'd0) - begin - v__h48088 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[7:2] != - 6'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h48088, - "\"ExtractAndPrependPipeOut.bsv\", line 291, column 17\n", - "empty header assertion @ mkPrependHeader2PipeOut"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[7:2] != - 6'd0) - $display("headerLastFragValidBitNum=%0d", - headerLastFragValidBitNum__h47980, - " and headerLastFragValidByteNum=%0d", - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[7:2], - " should be zero when isEmptyHeader="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[7:2] != - 6'd0) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[7:2] != - 6'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData && - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[16:10] == - 7'd0) - begin - v__h48212 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData && - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[16:10] == - 7'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h48212, - "\"ExtractAndPrependPipeOut.bsv\", line 303, column 17\n", - "headerMetaData.headerLen non-zero assertion @ mkPrependHeader2PipeOut"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData && - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[16:10] == - 7'd0) - $display("headerLen=%0d", - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[16:10], - " should not be zero when isEmptyHeader=", - "False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_popHeaderMetaData && - !sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerMetaDataOutQ_D_OUT[16:10] == - 7'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg != - 2'd0) - begin - v__h48664 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg != - 2'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h48664, - "\"ExtractAndPrependPipeOut.bsv\", line 339, column 17\n", - "headerFragCntReg zero assertion @ mkPrependHeader2PipeOut"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg != - 2'd0) - $display("headerFragCntReg=%h should be zero when curHeaderDataStreamFrag.isLast=%b", - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg, - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_outputHeader && - sq_reqGenSQ_rdmaReqPipeOut_headerDataStreamAndMetaDataPipeOut_headerDataStreamOutQ_D_OUT[0] && - sq_reqGenSQ_rdmaReqPipeOut_rdmaDataStreamPipeOut_headerFragCntReg != - 2'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18) - begin - v__h93157 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h93157, - "\"RespHandleSQ.bsv\", line 219, column 13\n", - "isRdmaRespOpCode assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18) - $display("bth.opcode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd0) - $display("SEND_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd1) - $display("SEND_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd2) - $display("SEND_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd3) - $display("SEND_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd4) - $display("SEND_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd5) - $display("SEND_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd6) - $display("RDMA_WRITE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd7) - $display("RDMA_WRITE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd8) - $display("RDMA_WRITE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd9) - $display("RDMA_WRITE_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd10) - $display("RDMA_WRITE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd11) - $display("RDMA_WRITE_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd12) - $display("RDMA_READ_REQUEST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd19) - $display("COMPARE_SWAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd20) - $display("FETCH_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd21) - $display("RESYNC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] == 5'd22) - $display("SEND_LAST_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd0 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd1 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd2 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd3 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd4 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd5 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd6 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd7 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd8 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd9 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd10 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd11 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd12 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd19 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd20 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd21 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd22) - $display("SEND_ONLY_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18) - $display(" should be RDMA response"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18 && - (respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 || - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd0 && - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd1 && - (respPktPipe_metaDataQ_D_OUT[529:528] != 2'd3 || - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd0 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd1 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd2 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd3 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd4))) - begin - v__h93514 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18 && - (respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 || - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd0 && - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd1 && - (respPktPipe_metaDataQ_D_OUT[529:528] != 2'd3 || - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd0 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd1 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd2 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd3 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd4))) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h93514, - "\"RespHandleSQ.bsv\", line 233, column 13\n", - "rdmaRespType assertion @ handleRetryResp() in mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18 && - (respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 || - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd0 && - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd1 && - (respPktPipe_metaDataQ_D_OUT[529:528] != 2'd3 || - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd0 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd1 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd2 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd3 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd4))) - $display("rdmaRespType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18 && - (respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 || - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd0 && - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd1 && - (respPktPipe_metaDataQ_D_OUT[529:528] != 2'd3 || - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd0 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd1 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd2 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd3 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd4)) && - (respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 || - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd0) && - (respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 || - respPktPipe_metaDataQ_D_OUT[529:528] == 2'd0 || - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd1 && - (respPktPipe_metaDataQ_D_OUT[529:528] != 2'd3 || - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd0)) && - (respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 || - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd3 || - respPktPipe_metaDataQ_D_OUT[527:523] == 5'd0 || - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd1 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd2 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd3 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd4)) - $display("RDMA_RESP_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18 && - (respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 || - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd0 && - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd1 && - (respPktPipe_metaDataQ_D_OUT[529:528] != 2'd3 || - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd0 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd1 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd2 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd3 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd4))) - $display(" should not be unknown"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd13 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd14 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd15 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd16 && - respPktPipe_metaDataQ_D_OUT[623:619] != 5'd18 && - (respPktPipe_metaDataQ_D_OUT[623:619] != 5'd17 || - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd0 && - respPktPipe_metaDataQ_D_OUT[529:528] != 2'd1 && - (respPktPipe_metaDataQ_D_OUT[529:528] != 2'd3 || - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd0 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd1 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd2 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd3 && - respPktPipe_metaDataQ_D_OUT[527:523] != 5'd4))) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - begin - v__h93774 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h93774, - "\"RespHandleSQ.bsv\", line 262, column 13\n", - "curPendingWR assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display("curPendingWR should have valid PSN and PktNum, curPendingWR="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display("PendingWorkReq { wr="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display("WorkReq { ID=%h", - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463, - ", opcode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753) - $display("IBV_WR_RDMA_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761) - $display("IBV_WR_RDMA_WRITE_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770) - $display("IBV_WR_SEND"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3783) - $display("IBV_WR_SEND_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3794) - $display("IBV_WR_RDMA_READ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3806) - $display("IBV_WR_ATOMIC_CMP_AND_SWP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3822) - $display("IBV_WR_ATOMIC_FETCH_AND_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3836) - $display("IBV_WR_LOCAL_INV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3851) - $display("IBV_WR_BIND_MW"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3870) - $display("IBV_WR_SEND_WITH_INV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3887) - $display("IBV_WR_TSO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3905) - $display("IBV_WR_DRIVER1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3927) - $display("IBV_WR_RDMA_READ_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3947) - $display("IBV_WR_FLUSH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3962) - $display("IBV_WR_ATOMIC_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", flags="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display("FlagsType { flags: ", enumBits__h93928, " = "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - enumBits__h93928[0]) - $display("IBV_SEND_FENCE", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !enumBits__h93928[0]) - $display(""); - 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if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !enumBits__h93928[3]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - enumBits__h93928[4]) - $display("IBV_SEND_IP_CSUM", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !enumBits__h93928[4]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - enumBits__h93928 == 5'd0) - $display("IBV_SEND_NO_FLAGS", " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - enumBits__h93928 != 5'd0) - $display("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", raddr=%h, rkey=%h, len=%0d, laddr=%h, lkey=%h, sqpn=%h", - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619, - ", solicited="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", comp="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003) - $display("tagged Valid ", "'h%h", value__h99740); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", swap="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012) - $display("tagged Valid ", "'h%h", value__h99767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", immDt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021) - $display("tagged Valid ", "'h%h", value__h99797); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", rkey2Inv="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030) - $display("tagged Valid ", "'h%h", value__h99824); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", srqn="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039) - $display("tagged Valid ", "'h%h", value__h99854); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", dqpn="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048) - $display("tagged Valid ", "'h%h", value__h99881); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", qkey="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057) - $display("tagged Valid ", "'h%h", value__h99908); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", startPSN="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473) - $display("tagged Valid ", "'h%h", value__h99939); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", endPSN="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491) - $display("tagged Valid ", "'h%h", value__h99966); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", pktNum="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - (!SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1474 || - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1492 || - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1652) && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649) - $display("tagged Valid %0d", - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649) - $display("tagged Invalid PktNum"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(", isOnlyReqPkt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074) - $display("tagged Valid "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $display(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3746) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq && - sq_reqGenSQ_workReqPsnQ_D_OUT[4] && - NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2536) - begin - v__h57516 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq && - sq_reqGenSQ_workReqPsnQ_D_OUT[4] && - NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2536) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h57516, - "\"ReqGenSQ.bsv\", line 828, column 17\n", - "startPSN, endPSN, nextPSN assertion @ mkReqGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq && - sq_reqGenSQ_workReqPsnQ_D_OUT[4] && - NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2536) - $display("endPSN=%h should >= startPSN=%h, and endPSN=%h + 1 should == nextPSN=%h", - endPktSeqNum__h56057, - cntrl_npsnReg, - endPktSeqNum__h56057, - nextPktSeqNum__h56056); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_reqGenSQ_calcPktSeqNum4NewWorkReq && - sq_reqGenSQ_workReqPsnQ_D_OUT[4] && - NOT_IF_IF_sq_reqGenSQ_workReqPsnQ_first__498_B_ETC___d2536) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4187) - begin - v__h97761 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4187) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h97761, - "\"RespHandleSQ.bsv\", line 361, column 33\n", - "unreachible case @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4187) - $display("rdmaRespType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4187) - $display("RDMA_RESP_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4187) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4200) - begin - v__h97941 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4200) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h97941, - "\"RespHandleSQ.bsv\", line 399, column 33\n", - "unreachible case @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4200) - $display("rdmaRespType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4200) - $display("RDMA_RESP_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4200) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203) - begin - v__h98281 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h98281, - "\"RespHandleSQ.bsv\", line 414, column 13\n", - "wrAckType and wcReqType assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203) - $display("wrAckType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4208 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1000 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1010) && - sq_respHandleSQ_preStageRespTypeReg == 2'd0) - $display("WR_ACK_EXPLICIT_WHOLE_NORMAL"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4214 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1000 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1010) && - sq_respHandleSQ_preStageRespTypeReg == 2'd1) - $display("WR_ACK_EXPLICIT_WHOLE_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4220 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1000 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1010) && - sq_respHandleSQ_preStageRespTypeReg == 2'd2) - $display("WR_ACK_EXPLICIT_WHOLE_ERROR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4208 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1000 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b0100 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg == 2'd0) - $display("WR_ACK_EXPLICIT_PARTIAL_NORMAL"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4214 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1000 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b0100 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg == 2'd1) - $display("WR_ACK_EXPLICIT_PARTIAL_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4220 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1000 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b0100 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg == 2'd2) - $display("WR_ACK_EXPLICIT_PARTIAL_ERROR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1000 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b0100 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b0010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b0001) - $display("WR_ACK_DUPLICATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4267) - $display("WR_ACK_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203) - $display(", and wcReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203 && - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4271) - $display("WC_REQ_TYPE_FULL_ACK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4208 && - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4275 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1000 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b1010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != 4'b0100 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0001) && - sq_respHandleSQ_preStageRespTypeReg == 2'd0) - $display("WC_REQ_TYPE_PARTIAL_ACK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203 && - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4275 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1000 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0100 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0001 || - sq_respHandleSQ_preStageRespTypeReg != 2'd0) && - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q35) - $display("WC_REQ_TYPE_NO_WC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203 && - IF_sq_respHandleSQ_preStageRespAndWorkReqRelat_ETC___d4275 && - (sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1000 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b1010 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == - 4'b0100 || - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0010 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] != - 4'b0001 || - sq_respHandleSQ_preStageRespTypeReg != 2'd0) && - CASE_sq_respHandleSQ_preStageRespAndWorkReqRel_ETC__q36) - $display("WC_REQ_TYPE_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203) - $display(" should not be unknown"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg_170_BIT_ETC___d4203) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1] && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == 4'b0100 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) - begin - v__h98457 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1] && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == 4'b0100 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h98457, - "\"RespHandleSQ.bsv\", line 423, column 13\n", - "deqPktMetaData and deqPendingWorkReq assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1] && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == 4'b0100 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) - $display("deqPktMetaData="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1] && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == 4'b0100 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1] && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == 4'b0100 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) - $display(", and deqPendingWorkReq="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1] && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == 4'b0100 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1] && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == 4'b0100 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) - $display(" should have at least one be true"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1] && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[3:0] == 4'b0100 && - sq_respHandleSQ_preStageRespAndWorkReqRelationReg[4]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1]) - $display("Error: \"RespHandleSQ.bsv\", line 310, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_preProcRespInfo and\n RL_sq_respHandleSQ_preBuildRespInfo called conflicting methods read and\n write of module instance sq_respHandleSQ_preStageRespAndWorkReqRelationReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo) - $display("Error: \"RespHandleSQ.bsv\", line 310, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_preProcRespInfo and\n RL_sq_respHandleSQ_preBuildRespInfo called conflicting methods read and\n write of module instance sq_respHandleSQ_preStagePktMetaDataReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - sq_respHandleSQ_preStagePktMetaDataReg[1]) - $display("Error: \"RespHandleSQ.bsv\", line 310, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_preProcRespInfo and\n RL_sq_respHandleSQ_preBuildRespInfo called conflicting methods read and\n write of module instance sq_respHandleSQ_preStageRespTypeReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - !sq_respHandleSQ_recvErrRespReg) - $display("Error: \"RespHandleSQ.bsv\", line 310, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_preProcRespInfo and\n RL_sq_respHandleSQ_preBuildRespInfo called conflicting methods read and\n write of module instance sq_respHandleSQ_preStageStateReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd0 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd3 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd1 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd4 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd2 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd5 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd6 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd7 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd8 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd12 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd13) - begin - v__h101559 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd0 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd3 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd1 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd4 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd2 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd5 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd6 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd7 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd8 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd12 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd13) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h101559, - "\"RespHandleSQ.bsv\", line 616, column 21\n", - "unreachible case @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd0 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd3 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd1 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd4 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd2 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd5 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd6 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd7 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd8 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd12 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd13) - $display("wrAckType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd0 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd3 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd1 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd4 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd2 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd5 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd6 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd7 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd8 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd12 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd13) - $display("WR_ACK_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd0 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd3 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd1 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd4 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd2 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd5 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd6 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd7 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd8 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd11 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd9 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd10 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd12 && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] != 4'd13) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4697) - begin - v__h101795 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4697) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h101795, - "\"RespHandleSQ.bsv\", line 625, column 17\n", - "respAction retry flush assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4697) - $display("respAction="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd6) - $display("SQ_ACT_COALESCE_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - (sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd2 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd5)) - $display("SQ_ACT_ERROR_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4716) - $display("SQ_ACT_EXPLICIT_NORMAL_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd8) - $display("SQ_ACT_DUPLICATE_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd10 && - sq_respHandleSQ_incomingRespQ_D_OUT[142]) - $display("SQ_ACT_ILLEGAL_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd12) - $display("SQ_ACT_FLUSH_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd13) - $display("SQ_ACT_TIMEOUT_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - (sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd1 || - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd4)) - $display("SQ_ACT_EXPLICIT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - sq_respHandleSQ_incomingRespQ_D_OUT[3:0] == 4'd7) - $display("SQ_ACT_IMPLICIT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4746) - $display("SQ_ACT_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4697) - $display(" should be SQ_ACT_DISCARD_RESP when inRetryState="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4697) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_retryFlushReg_616_AND_NOT_sq_r_ETC___d4697) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - NOT_sq_respHandleSQ_retryFlushReg_616_617_OR_s_ETC___d4756) - begin - v__h101959 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - NOT_sq_respHandleSQ_retryFlushReg_616_617_OR_s_ETC___d4756) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h101959, - "\"RespHandleSQ.bsv\", line 647, column 17\n", - "respAction assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - NOT_sq_respHandleSQ_retryFlushReg_616_617_OR_s_ETC___d4756) - $display("respAction="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - NOT_sq_respHandleSQ_retryFlushReg_616_617_OR_s_ETC___d4756) - $display("SQ_ACT_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - NOT_sq_respHandleSQ_retryFlushReg_616_617_OR_s_ETC___d4756) - $display(" should not be unknown"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - NOT_sq_respHandleSQ_retryFlushReg_616_617_OR_s_ETC___d4756) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd3 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd9 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd2 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd1 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd5 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd4 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd6 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd7 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd8) - begin - v__h103981 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd3 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd9 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd2 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd1 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd5 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd4 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd6 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd7 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd8) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h103981, - "\"RespHandleSQ.bsv\", line 728, column 21\n", - "unreachible case @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd3 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd9 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd2 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd1 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd5 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd4 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd6 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd7 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd8) - $display("respAction="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd0) - $display("SQ_ACT_BAD_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd11) - $display("SQ_ACT_LOCAL_ACC_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd12) - $display("SQ_ACT_LOCAL_LEN_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd3 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd9 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd2 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd1 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd5 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd4 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd6 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd7 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd8 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd0 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd11 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd12) - $display("SQ_ACT_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd3 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd9 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd10 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd2 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd1 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd5 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd4 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd6 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd7 && - sq_respHandleSQ_pendingRespQ_D_OUT[9:6] != 4'd8) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - ((sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3) ? - (IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 ? - 4'd0 : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) == - 4'd13) - begin - v__h104178 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - ((sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3) ? - (IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 ? - 4'd0 : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) == - 4'd13) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h104178, - "\"RespHandleSQ.bsv\", line 736, column 13\n", - "respAction assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - ((sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3) ? - (IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 ? - 4'd0 : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) == - 4'd13) - $display("respAction="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - ((sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3) ? - (IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 ? - 4'd0 : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) == - 4'd13) - $display("SQ_ACT_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - ((sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3) ? - (IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 ? - 4'd0 : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) == - 4'd13) - $display(" should not be unknown"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - ((sq_respHandleSQ_pendingRespQ_D_OUT[9:6] == 4'd3) ? - (IF_sq_respHandleSQ_pendingRespQ_first__787_BIT_ETC___d4844 ? - 4'd0 : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) : - sq_respHandleSQ_pendingRespQ_D_OUT[9:6]) == - 4'd13) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd13 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd15 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd16 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd17 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd18) - begin - v__h106970 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd13 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd15 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd16 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd17 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd18) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h106970, - "\"RespHandleSQ.bsv\", line 822, column 21\n", - "rdmaRespHasAETH assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd13 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd15 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd16 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd17 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd18) - $display("rdmaRespHasAETH="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd13 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd15 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd16 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd17 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd18) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd13 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd15 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd16 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd17 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd18) - $display(" should be true"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd13 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd15 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd16 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd17 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[138:134] != 5'd18) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - begin - v__h107194 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h107194, - "\"RespHandleSQ.bsv\", line 831, column 21\n", - "isValid(wcStatus) assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display("wcStatus="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display(" should be valid after call genErrWorkCompStatusFromAethSQ(aeth="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display("AETH { ", "rsvd: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display(", ", "code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] == 2'd0) - $display("AETH_CODE_ACK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] == 2'd1) - $display("AETH_CODE_RNR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] == 2'd2) - $display("AETH_CODE_RSVD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4) && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd0 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd2) - $display("AETH_CODE_NAK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display(", ", "value: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display("'h%h", sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display(", ", "msn: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display("'h%h", - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[37:14], - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $display(")"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd2 && - (sq_respHandleSQ_pendingRetryCheckQ_D_OUT[44:43] != 2'd3 || - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[42:38] != 5'd4)) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd0 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd5 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd6 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd4 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd7 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd8) - begin - v__h107798 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd0 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd5 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd6 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd4 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd7 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd8) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h107798, - "\"RespHandleSQ.bsv\", line 906, column 21\n", - "unreachible case @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd0 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd5 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd6 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd4 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd7 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd8) - $display("respAction="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd11) - $display("SQ_ACT_LOCAL_ACC_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] == 4'd12) - $display("SQ_ACT_LOCAL_LEN_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd0 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd5 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd6 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd4 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd7 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd8 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd11 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd12) - $display("SQ_ACT_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkRetryErr && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd0 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd2 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd3 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd1 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd5 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd6 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd4 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd7 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd9 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd10 && - sq_respHandleSQ_pendingRetryCheckQ_D_OUT[6:3] != 4'd8) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd0) - begin - v__h109873 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h109873, - "\"RespHandleSQ.bsv\", line 939, column 21\n", - "wcs assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd0) - $display("wcStatus="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd0) - $display("tagged Valid "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd1) - $display("IBV_WC_LOC_LEN_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd2) - $display("IBV_WC_LOC_QP_OP_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd3) - $display("IBV_WC_LOC_EEC_OP_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd4) - $display("IBV_WC_LOC_PROT_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd5) - $display("IBV_WC_WR_FLUSH_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd6) - $display("IBV_WC_MW_BIND_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd7) - $display("IBV_WC_BAD_RESP_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd8) - $display("IBV_WC_LOC_ACCESS_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd9) - $display("IBV_WC_REM_INV_REQ_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd10) - $display("IBV_WC_REM_ACCESS_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd11) - $display("IBV_WC_REM_OP_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd12) - $display("IBV_WC_RETRY_EXC_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd13) - $display("IBV_WC_RNR_RETRY_EXC_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd14) - $display("IBV_WC_LOC_RDD_VIOL_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd15) - $display("IBV_WC_REM_INV_RD_REQ_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd16) - $display("IBV_WC_REM_ABORT_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd17) - $display("IBV_WC_INV_EECN_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd18) - $display("IBV_WC_INV_EEC_STATE_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd19) - $display("IBV_WC_FATAL_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd20) - $display("IBV_WC_RESP_TIMEOUT_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd21) - $display("IBV_WC_GENERAL_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] == 5'd22) - $display("IBV_WC_TM_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd0 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd1 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd2 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd4 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd5 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd6 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd7 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd8 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd9 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd10 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd11 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd12 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd13 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd14 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd15 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd16 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd17 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd18 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd19 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd20 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd21 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd22) - $display("IBV_WC_TM_RNDV_INCOMPLETE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd0) - $display(" should be valid and IBV_WC_SUCCESS"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkPerm4NormalReadAtomicResp && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[12:9] == 4'd3 && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[8] && - sq_respHandleSQ_pendingPermCheckQ_D_OUT[7:3] != 5'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - begin - v__h117067 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h117067, - "\"RespHandleSQ.bsv\", line 1343, column 13\n", - "hasLocalErr -> genWorkComp assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display("genWorkComp="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display(" should be true when hasLocalErr="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display(", respAction="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd0) - $display("SQ_ACT_BAD_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd1) - $display("SQ_ACT_COALESCE_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd2) - $display("SQ_ACT_ERROR_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd3) - $display("SQ_ACT_EXPLICIT_NORMAL_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd4) - $display("SQ_ACT_DISCARD_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd5) - $display("SQ_ACT_DUPLICATE_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd6) - $display("SQ_ACT_ILLEGAL_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd7) - $display("SQ_ACT_FLUSH_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd8) - $display("SQ_ACT_TIMEOUT_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd9) - $display("SQ_ACT_EXPLICIT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd10) - $display("SQ_ACT_IMPLICIT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd11) - $display("SQ_ACT_LOCAL_ACC_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd12) - $display("SQ_ACT_LOCAL_LEN_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd0 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd1 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd2 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd3 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd4 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd5 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd6 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd7 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd8 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd9 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd10 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd11 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd12) - $display("SQ_ACT_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[78] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71]) - begin - v__h117291 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h117291, - "\"RespHandleSQ.bsv\", line 1352, column 13\n", - "genWorkComp -> isValid(wcStatus) assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71]) - $display("wcStatus="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71]) - $display(" should be valid when genWorkComp="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71]) - $display(", respAction="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd0) - $display("SQ_ACT_BAD_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd1) - $display("SQ_ACT_COALESCE_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd2) - $display("SQ_ACT_ERROR_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd3) - $display("SQ_ACT_EXPLICIT_NORMAL_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd4) - $display("SQ_ACT_DISCARD_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd5) - $display("SQ_ACT_DUPLICATE_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd6) - $display("SQ_ACT_ILLEGAL_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd7) - $display("SQ_ACT_FLUSH_WR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd8) - $display("SQ_ACT_TIMEOUT_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd9) - $display("SQ_ACT_EXPLICIT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd10) - $display("SQ_ACT_IMPLICIT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd11) - $display("SQ_ACT_LOCAL_ACC_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] == 4'd12) - $display("SQ_ACT_LOCAL_LEN_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd0 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd1 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd2 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd3 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd4 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd5 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd6 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd7 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd8 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd9 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd10 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd11 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[75:72] != 4'd12) - $display("SQ_ACT_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[71]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - begin - v__h117643 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h117643, - "\"RespHandleSQ.bsv\", line 1380, column 17\n", - "genWorkComp assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display("genWorkComp="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $display(" should be true when wcStatus="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd1) - $display("IBV_WC_LOC_LEN_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd2) - $display("IBV_WC_LOC_QP_OP_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd3) - $display("IBV_WC_LOC_EEC_OP_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd4) - $display("IBV_WC_LOC_PROT_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd5) - $display("IBV_WC_WR_FLUSH_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd6) - $display("IBV_WC_MW_BIND_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd7) - $display("IBV_WC_BAD_RESP_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd8) - $display("IBV_WC_LOC_ACCESS_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd9) - $display("IBV_WC_REM_INV_REQ_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd10) - $display("IBV_WC_REM_ACCESS_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd11) - $display("IBV_WC_REM_OP_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd12) - $display("IBV_WC_RETRY_EXC_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd13) - $display("IBV_WC_RNR_RETRY_EXC_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd14) - $display("IBV_WC_LOC_RDD_VIOL_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd15) - $display("IBV_WC_REM_INV_RD_REQ_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd16) - $display("IBV_WC_REM_ABORT_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd17) - $display("IBV_WC_INV_EECN_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd18) - $display("IBV_WC_INV_EEC_STATE_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd19) - $display("IBV_WC_FATAL_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd20) - $display("IBV_WC_RESP_TIMEOUT_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd21) - $display("IBV_WC_GENERAL_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] == 5'd22) - $display("IBV_WC_TM_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd1 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd2 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd3 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd4 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd5 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd6 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd7 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd8 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd9 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd10 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd11 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd12 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd13 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd14 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd15 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd16 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd17 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd18 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd19 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd20 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd21 && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd22) - $display("IBV_WC_TM_RNDV_INCOMPLETE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_issueDmaReq && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[71] && - sq_respHandleSQ_pendingDmaReqQ_D_OUT[70:66] != 5'd0 && - !sq_respHandleSQ_pendingDmaReqQ_D_OUT[76]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp && - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg && - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1452, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_discardGhostResp and\n RL_sq_respHandleSQ_handleRespByType called conflicting methods read and\n write of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1452, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_discardGhostResp and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - respPktPipe_metaDataQ_EMPTY_N && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1452, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_discardGhostResp and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_retryFlushReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkTimeOutErr && - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_retryFlushReg && - sq_retryHandler_timeOutNotificationQ_EMPTY_N && - !sq_respHandleSQ_errOccurredReg && - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1498, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_checkTimeOutErr and\n RL_sq_respHandleSQ_handleRespByType called conflicting methods read and\n write of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkTimeOutErr && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_retryFlushReg && - sq_retryHandler_timeOutNotificationQ_EMPTY_N && - !sq_respHandleSQ_errOccurredReg && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1498, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_checkTimeOutErr and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_checkTimeOutErr && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - sq_retryHandler_timeOutNotificationQ_EMPTY_N && - !sq_respHandleSQ_recvErrRespReg && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1498, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_checkTimeOutErr and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_retryFlushReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp) - $display("Error: \"RespHandleSQ.bsv\", line 1587, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushIncomingResp and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods first and deq\n of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp) - $display("Error: \"RespHandleSQ.bsv\", line 1587, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushIncomingResp and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods deq and deq\n of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp) - $display("Error: \"RespHandleSQ.bsv\", line 1587, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushIncomingResp and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods enq and enq\n of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp && - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg && - respPktPipe_metaDataQ_EMPTY_N && - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1587, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushIncomingResp and\n RL_sq_respHandleSQ_handleRespByType called conflicting methods read and\n write of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_pendingWorkReqBuf_emptyReg && - respPktPipe_metaDataQ_EMPTY_N && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1587, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushIncomingResp and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp && - respPktPipe_metaDataQ_EMPTY_N) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_errFlushIncomingResp called conflicting methods first and\n deq of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp && - respPktPipe_metaDataQ_EMPTY_N) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_errFlushIncomingResp called conflicting methods deq and\n deq of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_errFlushIncomingResp called conflicting methods notEmpty\n and deq of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp && - respPktPipe_metaDataQ_EMPTY_N) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_errFlushIncomingResp called conflicting methods enq and\n enq of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp && - respPktPipe_metaDataQ_EMPTY_N) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods first and deq\n of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp && - respPktPipe_metaDataQ_EMPTY_N) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods deq and deq\n of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods notEmpty and\n deq of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp && - respPktPipe_metaDataQ_EMPTY_N) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods enq and enq\n of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_retryFlushReg && - (!respPktPipe_metaDataQ_EMPTY_N || - sq_respHandleSQ_incomingRespQ_FULL_N) && - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_handleRespByType called conflicting methods read and\n write of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - sq_respHandleSQ_retryFlushReg && - (!respPktPipe_metaDataQ_EMPTY_N || - sq_respHandleSQ_incomingRespQ_FULL_N) && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - (!respPktPipe_metaDataQ_EMPTY_N || - sq_respHandleSQ_incomingRespQ_FULL_N) && - !sq_respHandleSQ_recvErrRespReg && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1661, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_retryFlushReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - begin - v__h122840 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h122840, - "\"RespHandleSQ.bsv\", line 1636, column 13\n", - "pendingWR notEmpty assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display("pendingWorkReqPipeIn.notEmpty="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display(" should be true, when cntrlStatus.comm.isRTS="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display(", inRetryState="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display(", retryFlushReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display(", errOccurredReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_pendingWorkReqBuf_emptyReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1633, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushDone and\n RL_sq_respHandleSQ_handleRespByType called conflicting methods read and\n write of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1633, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushDone and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_recvErrRespReg && - !sq_respHandleSQ_errOccurredReg && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1633, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_retryFlushDone and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_retryFlushReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_retryHandler_retryReasonReg == 3'd0) - begin - v__h36446 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_retryHandler_retryReasonReg == 3'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h36446, - "\"RetryHandleSQ.bsv\", line 557, column 13\n", - "retryReasonReg assertion @ mkRetryHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_retryHandler_retryReasonReg == 3'd0) - $display("retryReasonReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_retryHandler_retryReasonReg == 3'd0) - $display("RETRY_REASON_NOT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_retryHandler_retryReasonReg == 3'd0) - $display(" should not be RETRY_REASON_NOT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_retryHandler_retryReasonReg == 3'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_pendingWorkReqBuf_scanStateReg != 2'd0 && - sq_pendingWorkReqBuf_emptyReg) - begin - v__h36711 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_pendingWorkReqBuf_scanStateReg != 2'd0 && - sq_pendingWorkReqBuf_emptyReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h36711, - "\"SpecialFIFOF.bsv\", line 482, column 17\n", - "isEmpty assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_pendingWorkReqBuf_scanStateReg != 2'd0 && - sq_pendingWorkReqBuf_emptyReg) - $display("cannot restart scan when isEmpty="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_pendingWorkReqBuf_scanStateReg != 2'd0 && - sq_pendingWorkReqBuf_emptyReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_startPreRetry && - sq_pendingWorkReqBuf_scanStateReg != 2'd0 && - sq_pendingWorkReqBuf_emptyReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_checkPartialRetry && - sq_retryHandler_retryReasonReg != 3'd4 && - sq_retryHandler_retryWorkReqIdReg != - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463) - begin - v__h37491 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_checkPartialRetry && - sq_retryHandler_retryReasonReg != 3'd4 && - sq_retryHandler_retryWorkReqIdReg != - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h37491, - "\"RetryHandleSQ.bsv\", line 646, column 17\n", - "retryWorkReqIdReg assertion @ mkRetryHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_checkPartialRetry && - sq_retryHandler_retryReasonReg != 3'd4 && - sq_retryHandler_retryWorkReqIdReg != - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463) - $display("retryWorkReqIdReg=%h should == firstRetryWR.wr.id=%h", - sq_retryHandler_retryWorkReqIdReg, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_checkPartialRetry && - sq_retryHandler_retryReasonReg != 3'd4 && - sq_retryHandler_retryWorkReqIdReg != - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_checkPartialRetry && - NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1516) - begin - v__h38910 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_checkPartialRetry && - NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1516) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h38910, - "\"RetryHandleSQ.bsv\", line 659, column 13\n", - "retryStartPSN assertion @ mkRetryHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_checkPartialRetry && - NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1516) - $display("retryStartPSN=%h should between startPSN=%h and endPSN=%h inclusively", - v__h37423, - value__h99939, - value__h99966); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_checkPartialRetry && - NOT_IF_sq_retryHandler_retryReasonReg_431_EQ_4_ETC___d1516) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1) - begin - v__h35350 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h35350, - "\"RetryHandleSQ.bsv\", line 425, column 13\n", - "hasRetryErr assertion @ mkRetryHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1) - $display("hasRetryErr="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1) - $display(" should be false and retryCntrlStateReg[1]="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1) - $display("RETRY_CNTRL_ST_RETRY_LIMIT_EXC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1) - $display(" should != RETRY_CNTRL_ST_RETRY_LIMIT_EXC", - " when updateRetryCntQ.notEmpty="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1 && - sq_retryHandler_updateRetryCntQ_EMPTY_N) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1 && - !sq_retryHandler_updateRetryCntQ_EMPTY_N) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_retryCntrlStateReg_port1__read == 2'd1) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd2 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd3 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd4 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd1) - begin - v__h35692 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd2 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd3 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd4 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd1) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h35692, - "\"RetryHandleSQ.bsv\", line 168, column 25\n", - "unreachible case in decRetryCntByReason() @ mkRetryHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd2 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd3 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd4 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd1) - $display("retryReason="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd2 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd3 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd4 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd1 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd0) - $display("RETRY_REASON_NOT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd2 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd3 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd4 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd1 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd0) - $display("RETRY_REASON_TIMEOUT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd2 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd3 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd4 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd1) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg) - begin - v__h35995 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h35995, - "\"RetryHandleSQ.bsv\", line 455, column 17\n", - "pendingWorkReqNotEmpty assertion @ mkRetryHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg) - $display("pendingWorkReqNotEmpty="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg) - $display(" should be true when maybeRetryReason="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg) - $display("tagged Valid "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd0) - $display("RETRY_REASON_NOT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd1) - $display("RETRY_REASON_RNR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd2) - $display("RETRY_REASON_SEQ_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] == 3'd3) - $display("RETRY_REASON_IMPLICIT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd0 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd1 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd2 && - sq_retryHandler_updateRetryCntQ_D_OUT[2:0] != 3'd3) - $display("RETRY_REASON_TIMEOUT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryCntUpdate && - sq_retryHandler_updateRetryCntQ_D_OUT[3] && - sq_pendingWorkReqBuf_emptyReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_pendingWorkReqBuf_emptyReg) - begin - v__h34459 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_pendingWorkReqBuf_emptyReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h34459, - "\"RetryHandleSQ.bsv\", line 380, column 17\n", - "pendingWorkReqNotEmpty assertion @ mkRetryHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_pendingWorkReqBuf_emptyReg) - $display("pendingWorkReqNotEmpty="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_pendingWorkReqBuf_emptyReg) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_pendingWorkReqBuf_emptyReg) - $display(" should be true when retryReqOrResetRetryCnt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_pendingWorkReqBuf_emptyReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_pendingWorkReqBuf_emptyReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5]) - begin - v__h34954 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h34954, - "\"RetryHandleSQ.bsv\", line 396, column 25\n", - "retryRnrTimer assertion @ mkRetryHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5]) - $display("retryRnrTimer="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5]) - $display(" should be valid when retryReason="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd0) - $display("RETRY_REASON_NOT_RETRY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5]) - $display("RETRY_REASON_RNR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd2) - $display("RETRY_REASON_SEQ_ERR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd3) - $display("RETRY_REASON_IMPLICIT"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_retryHandler_handleRetryAction && - sq_retryHandler_retryActionQ_D_OUT[97] && - sq_retryHandler_retryActionQ_D_OUT[8:6] == 3'd1 && - !sq_retryHandler_retryActionQ_D_OUT[5]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - begin - v__h98868 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h98868, - "\"SpecialFIFOF.bsv\", line 434, column 17\n", - "dequeue assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - $display("cannot dequeue when scanStartReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_pendingWorkReqBuf_scanStartReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - !sq_pendingWorkReqBuf_scanStartReg_port1__read) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - $display(" or preScanRestartReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - !sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageDeqPendingWorkReqReg && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - begin - v__h99106 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h99106, - "\"RespHandleSQ.bsv\", line 521, column 17\n", - "deqPendingWorkReq assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("deqPendingWorkReq="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(" should be true when rdmaRespType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageWorkReqAckTypeReg != 4'd8 && - !sq_respHandleSQ_recvRetryRespReg && - sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("RDMA_RESP_NORMAL"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - sq_respHandleSQ_preStageWorkReqAckTypeReg != 4'd8 && - !sq_respHandleSQ_recvRetryRespReg && - sq_respHandleSQ_preStageRespTypeReg == 2'd2 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("RDMA_RESP_ERROR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", recvRetryRespReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", recvErrRespReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", and bth.psn=%h", - sq_respHandleSQ_preStageReqPktInfoReg[62:39], - ", bth.opcode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd0) - $display("SEND_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd1) - $display("SEND_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd2) - $display("SEND_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd3) - $display("SEND_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd4) - $display("SEND_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd5) - $display("SEND_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd6) - $display("RDMA_WRITE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd7) - $display("RDMA_WRITE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd8) - $display("RDMA_WRITE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd9) - $display("RDMA_WRITE_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd10) - $display("RDMA_WRITE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd11) - $display("RDMA_WRITE_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd12) - $display("RDMA_READ_REQUEST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd13) - $display("RDMA_READ_RESPONSE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd14) - $display("RDMA_READ_RESPONSE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd15) - $display("RDMA_READ_RESPONSE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd16) - $display("RDMA_READ_RESPONSE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd17) - $display("ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd18) - $display("ATOMIC_ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd19) - $display("COMPARE_SWAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd20) - $display("FETCH_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd21) - $display("RESYNC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[131:127] == 5'd22) - $display("SEND_LAST_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4479) - $display("SEND_ONLY_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(" is the last or only response, AETH="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("AETH { ", "rsvd: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("'h%h", 1'd0); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", ", "code: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[37:36] == 2'd0) - $display("AETH_CODE_ACK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[37:36] == 2'd1) - $display("AETH_CODE_RNR"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[37:36] == 2'd2) - $display("AETH_CODE_RSVD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_respHandleSQ_preStageReqPktInfoReg[37:36] != 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[37:36] != 2'd1 && - sq_respHandleSQ_preStageReqPktInfoReg[37:36] != 2'd2) - $display("AETH_CODE_NAK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", ", "value: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("'h%h", sq_respHandleSQ_preStageReqPktInfoReg[35:31]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", ", "msn: "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("'h%h", sq_respHandleSQ_preStageReqPktInfoReg[30:7], " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", pending WR="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("PendingWorkReq { wr="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("WorkReq { ID=%h", - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1463, - ", opcode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753) - $display("IBV_WR_RDMA_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761) - $display("IBV_WR_RDMA_WRITE_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3770) - $display("IBV_WR_SEND"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3783) - $display("IBV_WR_SEND_WITH_IMM"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3794) - $display("IBV_WR_RDMA_READ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3806) - $display("IBV_WR_ATOMIC_CMP_AND_SWP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3822) - $display("IBV_WR_ATOMIC_FETCH_AND_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3836) - $display("IBV_WR_LOCAL_INV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3851) - $display("IBV_WR_BIND_MW"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3870) - $display("IBV_WR_SEND_WITH_INV"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3887) - $display("IBV_WR_TSO"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3761 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3905) - $display("IBV_WR_DRIVER1"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3927) - $display("IBV_WR_RDMA_READ_RESP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3947) - $display("IBV_WR_FLUSH"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d3753 && - NOT_SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3962) - $display("IBV_WR_ATOMIC_WRITE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", flags="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display("FlagsType { flags: ", enumBits__h93928, " = "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - enumBits__h93928[0]) - $display("IBV_SEND_FENCE", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !enumBits__h93928[0]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - enumBits__h93928[1]) - $display("IBV_SEND_SIGNALED", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !enumBits__h93928[1]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - enumBits__h93928[2]) - $display("IBV_SEND_SOLICITED", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !enumBits__h93928[2]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - enumBits__h93928[3]) - $display("IBV_SEND_INLINE", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !enumBits__h93928[3]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - enumBits__h93928[4]) - $display("IBV_SEND_IP_CSUM", " | "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !enumBits__h93928[4]) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - enumBits__h93928 == 5'd0) - $display("IBV_SEND_NO_FLAGS", " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - enumBits__h93928 != 5'd0) - $display("}"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", raddr=%h, rkey=%h, len=%0d, laddr=%h, lkey=%h, sqpn=%h", - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1525, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1561, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1562, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1592, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1618, - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BITS_ETC___d1619, - ", solicited="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d3994) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", comp="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4003) - $display("tagged Valid ", "'h%h", value__h99740); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", swap="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4012) - $display("tagged Valid ", "'h%h", value__h99767); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", immDt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4021) - $display("tagged Valid ", "'h%h", value__h99797); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", rkey2Inv="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4030) - $display("tagged Valid ", "'h%h", value__h99824); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", srqn="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4039) - $display("tagged Valid ", "'h%h", value__h99854); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", dqpn="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4048) - $display("tagged Valid ", "'h%h", value__h99881); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", qkey="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4057) - $display("tagged Valid ", "'h%h", value__h99908); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", startPSN="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1473) - $display("tagged Valid ", "'h%h", value__h99939); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", endPSN="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d1491) - $display("tagged Valid ", "'h%h", value__h99966); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", pktNum="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649) - $display("tagged Valid %0d", - SEL_ARR_IF_sq_pendingWorkReqBuf_dataVec_0_59_B_ETC___d1650); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_sq_pendingWorkReqBuf_dataVec_0_59_BIT__ETC___d1649) - $display("tagged Invalid PktNum"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(", isOnlyReqPkt="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074) - $display("tagged Valid "); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 && - SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4074 && - !SEL_ARR_NOT_sq_pendingWorkReqBuf_dataVec_0_59__ETC___d4083) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $display(" }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - NOT_sq_respHandleSQ_preStageWorkReqAckTypeReg__ETC___d4352 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - sq_respHandleSQ_preStageDeqPktMetaDataReg && - respPktPipe_metaDataQ_EMPTY_N) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload called conflicting\n methods deq and deq of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - respPktPipe_metaDataQ_EMPTY_N) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload called conflicting\n methods enq and enq of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload called conflicting\n methods read and write of module instance sq_respHandleSQ_preStageStateReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - sq_respHandleSQ_preStageWorkReqAckTypeReg != 4'd8 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses999) && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - sq_retryHandler_retryHandleStateReg == 3'd7) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_retryFlushDone called conflicting methods read and write\n of module instance sq_respHandleSQ_recvRetryRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_retryFlushDone && - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N && - sq_retryHandler_retryHandleStateReg == 3'd7) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_retryFlushDone called conflicting methods read and write\n of module instance sq_respHandleSQ_retryFlushReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp && - sq_respHandleSQ_preStageDeqPktMetaDataReg) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_errFlushIncomingResp called conflicting methods deq and\n deq of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_errFlushIncomingResp called conflicting methods enq and\n enq of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp && - sq_respHandleSQ_preStageDeqPktMetaDataReg) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods deq and deq\n of module instance respPktPipe_metaDataQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods enq and enq\n of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N && - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_handleRespByType called conflicting methods read and\n write of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - sq_respHandleSQ_preStageWorkReqAckTypeReg != 4'd8 && - (sq_respHandleSQ_preStageRespTypeReg == 2'd0 && - sq_respHandleSQ_preStageReqPktInfoReg[5] || - sq_respHandleSQ_preStageRespTypeReg == 2'd2 || - __duses999) && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_recvRetryRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - sq_respHandleSQ_preStageStateReg == 2'd2 && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvRetryRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_retryFlushReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preProcRespInfo called conflicting methods read and write\n of module instance sq_respHandleSQ_preStageDeqPktMetaDataReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preProcRespInfo called conflicting methods read and write\n of module instance sq_respHandleSQ_preStageDeqPendingWorkReqReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preProcRespInfo called conflicting methods read and write\n of module instance sq_respHandleSQ_preStageWorkReqAckTypeReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preProcRespInfo called conflicting methods read and write\n of module instance sq_respHandleSQ_preStageWorkCompReqTypeReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preProcRespInfo called conflicting methods read and write\n of module instance sq_respHandleSQ_retryResetReqReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preProcRespInfo && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preProcRespInfo called conflicting methods read and write\n of module instance sq_respHandleSQ_preStageStateReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preBuildRespInfo called conflicting methods read and\n write of module instance sq_respHandleSQ_preStagePktMetaDataReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preBuildRespInfo called conflicting methods read and\n write of module instance sq_respHandleSQ_preStageReqPktInfoReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - sq_respHandleSQ_preStageWorkReqAckTypeReg != 4'd8 && - !sq_respHandleSQ_preStageDeqPendingWorkReqReg && - !sq_respHandleSQ_recvRetryRespReg) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preBuildRespInfo called conflicting methods read and\n write of module instance sq_respHandleSQ_preStageRespTypeReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_preBuildRespInfo && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_retryFlushReg && - !sq_respHandleSQ_errOccurredReg && - !sq_respHandleSQ_recvErrRespReg && - !sq_pendingWorkReqBuf_emptyReg && - (!sq_respHandleSQ_preStageDeqPendingWorkReqReg || - sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - (!sq_respHandleSQ_preStageDeqPktMetaDataReg || - respPktPipe_metaDataQ_EMPTY_N) && - sq_respHandleSQ_incomingRespQ_FULL_N) - $display("Error: \"RespHandleSQ.bsv\", line 484, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq and\n RL_sq_respHandleSQ_preBuildRespInfo called conflicting methods read and\n write of module instance sq_respHandleSQ_preStageStateReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - begin - v__h120515 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h120515, - "\"SpecialFIFOF.bsv\", line 434, column 17\n", - "dequeue assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - $display("cannot dequeue when scanStartReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - sq_pendingWorkReqBuf_scanStartReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - !sq_pendingWorkReqBuf_scanStartReg_port1__read) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - $display(" or preScanRestartReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - !sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - (sq_pendingWorkReqBuf_scanStartReg_port1__read || - sq_pendingWorkReqBuf_preScanRestartReg_port1__read)) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload && - respPktPipe_metaDataQ_EMPTY_N) - $display("Error: \"RespHandleSQ.bsv\", line 1534, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushWorkReq and\n RL_sq_respHandleSQ_retryFlushPktMetaDataAndPayload called conflicting\n methods enq and enq of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_errFlushIncomingResp) - $display("Error: \"RespHandleSQ.bsv\", line 1534, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushWorkReq and\n RL_sq_respHandleSQ_errFlushIncomingResp called conflicting methods enq and\n enq of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_checkTimeOutErr && - sq_retryHandler_timeOutNotificationQ_D_OUT) - $display("Error: \"RespHandleSQ.bsv\", line 1534, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushWorkReq and\n RL_sq_respHandleSQ_checkTimeOutErr called conflicting methods port0__read\n and port0__write of module instance sq_respHandleSQ_hasTimeOutErrReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_discardGhostResp) - $display("Error: \"RespHandleSQ.bsv\", line 1534, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushWorkReq and\n RL_sq_respHandleSQ_discardGhostResp called conflicting methods enq and enq\n of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_handleRespByType && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - (sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - sq_respHandleSQ_incomingRespQ_FULL_N && - _write_RL_sq_respHandleSQ_handleRespByType_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1534, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushWorkReq and\n RL_sq_respHandleSQ_handleRespByType called conflicting methods read and\n write of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_recvRespHeader && - cntrl_stateReg == 4'd3 && - !sq_respHandleSQ_errOccurredReg && - !sq_pendingWorkReqBuf_emptyReg && - (sq_pendingWorkReqBuf_scanStateReg == 2'd0 || - sq_pendingWorkReqBuf_scanStateReg == 2'd2) && - sq_respHandleSQ_incomingRespQ_FULL_N && - _write_RL_sq_respHandleSQ_recvRespHeader_EN_sq_respHandleSQ_recvErrRespReg_wget) - $display("Error: \"RespHandleSQ.bsv\", line 1534, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushWorkReq and\n RL_sq_respHandleSQ_recvRespHeader called conflicting methods read and write\n of module instance sq_respHandleSQ_recvErrRespReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_errFlushWorkReq && - WILL_FIRE_RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq) - $display("Error: \"RespHandleSQ.bsv\", line 1534, column 10: (R0002)\n Conflict-free rules RL_sq_respHandleSQ_errFlushWorkReq and\n RL_sq_respHandleSQ_deqPktMetaDataOrWorkReq called conflicting methods enq\n and enq of module instance sq_respHandleSQ_incomingRespQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - begin - v__h29295 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h29295, - "\"SpecialFIFOF.bsv\", line 301, column 13\n", - "scanStartReg and popReg assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("scanStartReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display(", popReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display(" cannot both be true"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - begin - v__h29442 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h29442, - "\"SpecialFIFOF.bsv\", line 310, column 13\n", - "preScanRestartReg and popReg assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("preScanRestartReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display(", popReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display(" cannot both be true"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - (sq_pendingWorkReqBuf_scanStateReg == 2'd2 || - sq_pendingWorkReqBuf_scanStateReg == 2'd1) && - sq_pendingWorkReqBuf_itemCnt_Q_OUT == 3'd0) - begin - v__h29608 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - (sq_pendingWorkReqBuf_scanStateReg == 2'd2 || - sq_pendingWorkReqBuf_scanStateReg == 2'd1) && - sq_pendingWorkReqBuf_itemCnt_Q_OUT == 3'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h29608, - "\"SpecialFIFOF.bsv\", line 321, column 17\n", - "notEmpty assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - sq_pendingWorkReqBuf_itemCnt_Q_OUT == 3'd0) - $display("itemCnt=%0d", - sq_pendingWorkReqBuf_itemCnt_Q_OUT, - " cannot be zero when scanStateReg=", - "SCAN_Q_PRE_SCAN_MODE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_itemCnt_Q_OUT == 3'd0) - $display("itemCnt=%0d", - sq_pendingWorkReqBuf_itemCnt_Q_OUT, - " cannot be zero when scanStateReg=", - "SCAN_Q_SCAN_MODE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - (sq_pendingWorkReqBuf_scanStateReg == 2'd2 || - sq_pendingWorkReqBuf_scanStateReg == 2'd1) && - sq_pendingWorkReqBuf_itemCnt_Q_OUT == 3'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_itemCnt_Q_OUT != 3'd0) - begin - v__h29763 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_itemCnt_Q_OUT != 3'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h29763, - "\"SpecialFIFOF.bsv\", line 333, column 17\n", - "isEmpty assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_itemCnt_Q_OUT != 3'd0) - $display("itemCnt=%0d should be zero when isEmpty=", - sq_pendingWorkReqBuf_itemCnt_Q_OUT, - "True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_itemCnt_Q_OUT != 3'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - !sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_fullReg && - sq_pendingWorkReqBuf_itemCnt_Q_OUT != 3'd4) - begin - v__h29891 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - !sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_fullReg && - sq_pendingWorkReqBuf_itemCnt_Q_OUT != 3'd4) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h29891, - "\"SpecialFIFOF.bsv\", line 343, column 17\n", - "isFull assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - !sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_fullReg && - sq_pendingWorkReqBuf_itemCnt_Q_OUT != 3'd4) - $display("itemCnt=%0d should == qSz=%0d when isFull=", - sq_pendingWorkReqBuf_itemCnt_Q_OUT, - $signed(32'd4), - "True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - !sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_fullReg && - sq_pendingWorkReqBuf_itemCnt_Q_OUT != 3'd4) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031) - begin - v__h30076 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h30076, - "\"SpecialFIFOF.bsv\", line 357, column 21\n", - "dequeue beyond scan assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031 && - sq_pendingWorkReqBuf_pushReg_port1__read[679] && - sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_fullReg) - $display("deqPtrReg=%0d should != scanPtrReg=%0d + 1", - sq_pendingWorkReqBuf_deqPtrReg, - sq_pendingWorkReqBuf_scanPtrReg, - " when enqPtrReg=%0d", - sq_pendingWorkReqBuf_enqPtrReg, - ", scanStateReg=", - "SCAN_Q_SCAN_MODE", - ", popReg=", - "True", - ", hasPush=", - "True", - ", scanCnt=%0d", - sq_pendingWorkReqBuf_scanCnt_Q_OUT, - ", isEmpty=", - "True", - ", isFull=", - "True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031 && - sq_pendingWorkReqBuf_pushReg_port1__read[679] && - sq_pendingWorkReqBuf_emptyReg && - !sq_pendingWorkReqBuf_fullReg) - $display("deqPtrReg=%0d should != scanPtrReg=%0d + 1", - sq_pendingWorkReqBuf_deqPtrReg, - sq_pendingWorkReqBuf_scanPtrReg, - " when enqPtrReg=%0d", - sq_pendingWorkReqBuf_enqPtrReg, - ", scanStateReg=", - "SCAN_Q_SCAN_MODE", - ", popReg=", - "True", - ", hasPush=", - "True", - ", scanCnt=%0d", - sq_pendingWorkReqBuf_scanCnt_Q_OUT, - ", isEmpty=", - "True", - ", isFull=", - "False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031 && - sq_pendingWorkReqBuf_pushReg_port1__read[679] && - !sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_fullReg) - $display("deqPtrReg=%0d should != scanPtrReg=%0d + 1", - sq_pendingWorkReqBuf_deqPtrReg, - sq_pendingWorkReqBuf_scanPtrReg, - " when enqPtrReg=%0d", - sq_pendingWorkReqBuf_enqPtrReg, - ", scanStateReg=", - "SCAN_Q_SCAN_MODE", - ", popReg=", - "True", - ", hasPush=", - "True", - ", scanCnt=%0d", - sq_pendingWorkReqBuf_scanCnt_Q_OUT, - ", isEmpty=", - "False", - ", isFull=", - "True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031 && - sq_pendingWorkReqBuf_pushReg_port1__read[679] && - !sq_pendingWorkReqBuf_emptyReg && - !sq_pendingWorkReqBuf_fullReg) - $display("deqPtrReg=%0d should != scanPtrReg=%0d + 1", - sq_pendingWorkReqBuf_deqPtrReg, - sq_pendingWorkReqBuf_scanPtrReg, - " when enqPtrReg=%0d", - sq_pendingWorkReqBuf_enqPtrReg, - ", scanStateReg=", - "SCAN_Q_SCAN_MODE", - ", popReg=", - "True", - ", hasPush=", - "True", - ", scanCnt=%0d", - sq_pendingWorkReqBuf_scanCnt_Q_OUT, - ", isEmpty=", - "False", - ", isFull=", - "False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031 && - !sq_pendingWorkReqBuf_pushReg_port1__read[679] && - sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_fullReg) - $display("deqPtrReg=%0d should != scanPtrReg=%0d + 1", - sq_pendingWorkReqBuf_deqPtrReg, - sq_pendingWorkReqBuf_scanPtrReg, - " when enqPtrReg=%0d", - sq_pendingWorkReqBuf_enqPtrReg, - ", scanStateReg=", - "SCAN_Q_SCAN_MODE", - ", popReg=", - "True", - ", hasPush=", - "False", - ", scanCnt=%0d", - sq_pendingWorkReqBuf_scanCnt_Q_OUT, - ", isEmpty=", - "True", - ", isFull=", - "True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031 && - !sq_pendingWorkReqBuf_pushReg_port1__read[679] && - sq_pendingWorkReqBuf_emptyReg && - !sq_pendingWorkReqBuf_fullReg) - $display("deqPtrReg=%0d should != scanPtrReg=%0d + 1", - sq_pendingWorkReqBuf_deqPtrReg, - sq_pendingWorkReqBuf_scanPtrReg, - " when enqPtrReg=%0d", - sq_pendingWorkReqBuf_enqPtrReg, - ", scanStateReg=", - "SCAN_Q_SCAN_MODE", - ", popReg=", - "True", - ", hasPush=", - "False", - ", scanCnt=%0d", - sq_pendingWorkReqBuf_scanCnt_Q_OUT, - ", isEmpty=", - "True", - ", isFull=", - "False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031 && - !sq_pendingWorkReqBuf_pushReg_port1__read[679] && - !sq_pendingWorkReqBuf_emptyReg && - sq_pendingWorkReqBuf_fullReg) - $display("deqPtrReg=%0d should != scanPtrReg=%0d + 1", - sq_pendingWorkReqBuf_deqPtrReg, - sq_pendingWorkReqBuf_scanPtrReg, - " when enqPtrReg=%0d", - sq_pendingWorkReqBuf_enqPtrReg, - ", scanStateReg=", - "SCAN_Q_SCAN_MODE", - ", popReg=", - "True", - ", hasPush=", - "False", - ", scanCnt=%0d", - sq_pendingWorkReqBuf_scanCnt_Q_OUT, - ", isEmpty=", - "False", - ", isFull=", - "True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031 && - !sq_pendingWorkReqBuf_pushReg_port1__read[679] && - !sq_pendingWorkReqBuf_emptyReg && - !sq_pendingWorkReqBuf_fullReg) - $display("deqPtrReg=%0d should != scanPtrReg=%0d + 1", - sq_pendingWorkReqBuf_deqPtrReg, - sq_pendingWorkReqBuf_scanPtrReg, - " when enqPtrReg=%0d", - sq_pendingWorkReqBuf_enqPtrReg, - ", scanStateReg=", - "SCAN_Q_SCAN_MODE", - ", popReg=", - "True", - ", hasPush=", - "False", - ", scanCnt=%0d", - sq_pendingWorkReqBuf_scanCnt_Q_OUT, - ", isEmpty=", - "False", - ", isFull=", - "False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_deqPtrReg_90_EQ_sq_pendin_ETC___d1031) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - begin - v__h30289 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h30289, - "\"SpecialFIFOF.bsv\", line 375, column 17\n", - "scanStopReg and preScanRestartReg assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display("scanStopReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display(", preScanRestartReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $display(" cannot both be true"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd2 && - sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - sq_pendingWorkReqBuf_popReg_port1__read) - begin - v__h30463 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h30463, - "\"SpecialFIFOF.bsv\", line 396, column 17\n", - "no pop when inPreScanMode assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("popReg[1]="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - sq_pendingWorkReqBuf_popReg_port1__read) - $display(" should be false when inPreScanMode="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - sq_pendingWorkReqBuf_scanStateReg == 2'd1 && - sq_pendingWorkReqBuf_popReg_port1__read) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - (sq_pendingWorkReqBuf_itemCnt_Q_OUT > 3'd4 || - sq_pendingWorkReqBuf_itemCnt_Q_OUT < - sq_pendingWorkReqBuf_scanCnt_Q_OUT)) - begin - v__h30613 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - (sq_pendingWorkReqBuf_itemCnt_Q_OUT > 3'd4 || - sq_pendingWorkReqBuf_itemCnt_Q_OUT < - sq_pendingWorkReqBuf_scanCnt_Q_OUT)) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h30613, - "\"SpecialFIFOF.bsv\", line 406, column 13\n", - "itemCnt >= scanCnt assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - (sq_pendingWorkReqBuf_itemCnt_Q_OUT > 3'd4 || - sq_pendingWorkReqBuf_itemCnt_Q_OUT < - sq_pendingWorkReqBuf_scanCnt_Q_OUT)) - $display("valueOf(qSz)=%0d should >= itemCnt=%0d", - $signed(32'd4), - sq_pendingWorkReqBuf_itemCnt_Q_OUT, - " and itemCnt=%0d should >= scanCnt=%0d", - sq_pendingWorkReqBuf_itemCnt_Q_OUT, - sq_pendingWorkReqBuf_scanCnt_Q_OUT); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_check && - (sq_pendingWorkReqBuf_itemCnt_Q_OUT > 3'd4 || - sq_pendingWorkReqBuf_itemCnt_Q_OUT < - sq_pendingWorkReqBuf_scanCnt_Q_OUT)) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_emptyReg) - begin - v__h24390 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_emptyReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h24390, - "\"SpecialFIFOF.bsv\", line 175, column 17\n", - "isEmpty assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_emptyReg) - $display("cannot start preScan when isEmpty="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_emptyReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_emptyReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - begin - v__h24503 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h24503, - "\"SpecialFIFOF.bsv\", line 180, column 17\n", - "no pop when startPreScan assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("popReg[1]="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display(" should be false when preScanStartReg[1]="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_fifoMode && - sq_pendingWorkReqBuf_preScanStartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_emptyReg) - begin - v__h24769 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_emptyReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h24769, - "\"SpecialFIFOF.bsv\", line 202, column 13\n", - "isEmpty assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_emptyReg) - $display("isEmpty="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_emptyReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_emptyReg) - $display(" should be false when inPreScanMode"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_emptyReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_popReg_port1__read) - begin - v__h24880 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h24880, - "\"SpecialFIFOF.bsv\", line 210, column 13\n", - "no pop when inPreScanMode assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("popReg[1]="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_popReg_port1__read) - $display(" should be false when preScanStartReg[1]="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_popReg_port1__read && - sq_pendingWorkReqBuf_preScanStartReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_popReg_port1__read && - !sq_pendingWorkReqBuf_preScanStartReg_port1__read) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_preScanMode && - sq_pendingWorkReqBuf_popReg_port1__read) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - sq_pendingWorkReqBuf_emptyReg) - begin - v__h25249 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - sq_pendingWorkReqBuf_emptyReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h25249, - "\"SpecialFIFOF.bsv\", line 234, column 13\n", - "isEmpty assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - sq_pendingWorkReqBuf_emptyReg) - $display("cannot scan next when isEmpty="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - sq_pendingWorkReqBuf_emptyReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - sq_pendingWorkReqBuf_emptyReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - !sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - begin - v__h25475 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - !sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h25475, - "\"SpecialFIFOF.bsv\", line 249, column 17\n", - "no pop when preScanRestart assertion @ mkScanFIFOF"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - !sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("popReg[1]="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - !sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - !sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display(" should be false when preScanRestartReg[1]="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - !sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_pendingWorkReqBuf_scanModeStateChange && - !sq_pendingWorkReqBuf_scanStopReg_port1__read && - sq_pendingWorkReqBuf_preScanRestartReg_port1__read && - sq_pendingWorkReqBuf_popReg_port1__read) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg == 8'd0) - begin - v__h43204 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg == 8'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h43204, - "\"QueuePair.bsv\", line 123, column 13\n", - "decrPendingNewWorkReqCnt assertion @ mkNewPendingWorkReqPipeOut"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg == 8'd0) - $display("pendingNewWorkReqCnt should larger than zero when decrOne"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_newPendingWorkReqPiptOut_decrPendingNewWorkReqCnt && - sq_newPendingWorkReqPiptOut_pendingNewWorkReqCnt_cntReg == 8'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ && - sq_respHandleSQ_pendingWorkCompQ_D_OUT[635] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[633]) - begin - v__h118758 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ && - sq_respHandleSQ_pendingWorkCompQ_D_OUT[635] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[633]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h118758, - "\"RespHandleSQ.bsv\", line 1421, column 13\n", - "hasLocalErr -> genWorkComp assertion @ mkRespHandleSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ && - sq_respHandleSQ_pendingWorkCompQ_D_OUT[635] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[633]) - $display("genWorkComp="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ && - sq_respHandleSQ_pendingWorkCompQ_D_OUT[635] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[633]) - $display("False"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ && - sq_respHandleSQ_pendingWorkCompQ_D_OUT[635] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[633]) - $display(" should be true when hasLocalErr="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ && - sq_respHandleSQ_pendingWorkCompQ_D_OUT[635] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[633]) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_respHandleSQ_genWorkCompSQ && - sq_respHandleSQ_pendingWorkCompQ_D_OUT[635] && - !sq_respHandleSQ_pendingWorkCompQ_D_OUT[633]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - begin - v__h126312 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h126312, - "\"WorkCompGen.bsv\", line 180, column 13\n", - "maybeWorkComp assertion @ mkWorkCompGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display("maybeWorkComp="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $display(" should be valid"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_genPendingWorkCompSQ && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd0 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd1 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd2 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd3 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd4 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd5 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd6 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd7 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd8 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd9 && - sq_workCompGenSQ_pendingWorkCompQ4SQ_D_OUT[568:565] != 4'd10) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] == 2'd1) - begin - v__h3196 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h3196, - "\"Controller.bsv\", line 452, column 21\n", - "no QP destroy on create @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $display("REQ_QP_DESTROY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] == 2'd1) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - begin - v__h3517 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h3517, - "\"Controller.bsv\", line 476, column 21\n", - "unreachible case @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $display("request QPN=%h", cntrl_reqQ_D_OUT[266:243], ", qpReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] == 2'd0) - $display("REQ_QP_CREATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_cntrl_onCreate && cntrl_reqQ_D_OUT[300:299] != 2'd1 && - cntrl_reqQ_D_OUT[300:299] != 2'd2 && - cntrl_reqQ_D_OUT[300:299] != 2'd3) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ && - WILL_FIRE_RL_sq_workCompGenSQ_genWorkCompSQ && - cntrl_stateReg != 4'd6 && - sq_workCompGenSQ_dmaWaitingQ_EMPTY_N && - sq_workCompGenSQ_genWorkCompQ_FULL_N && - !sq_workCompGenSQ_genWorkCompQ_D_OUT[1]) - $display("Error: \"WorkCompGen.bsv\", line 288, column 10: (R0002)\n Conflict-free rules RL_sq_workCompGenSQ_noDmaWaitSQ and\n RL_sq_workCompGenSQ_genWorkCompSQ called conflicting methods read and write\n of module instance sq_workCompGenSQ_workCompGenStateReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ && - WILL_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ) - $display("Error: \"WorkCompGen.bsv\", line 288, column 10: (R0002)\n Conflict-free rules RL_sq_workCompGenSQ_noDmaWaitSQ and\n RL_sq_workCompGenSQ_waitDmaDoneSQ called conflicting methods first and deq\n of module instance sq_workCompGenSQ_dmaWaitingQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ && - WILL_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ) - $display("Error: \"WorkCompGen.bsv\", line 288, column 10: (R0002)\n Conflict-free rules RL_sq_workCompGenSQ_noDmaWaitSQ and\n RL_sq_workCompGenSQ_waitDmaDoneSQ called conflicting methods deq and deq of\n module instance sq_workCompGenSQ_dmaWaitingQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_noDmaWaitSQ && - WILL_FIRE_RL_sq_workCompGenSQ_waitDmaDoneSQ) - $display("Error: \"WorkCompGen.bsv\", line 288, column 10: (R0002)\n Conflict-free rules RL_sq_workCompGenSQ_noDmaWaitSQ and\n RL_sq_workCompGenSQ_waitDmaDoneSQ called conflicting methods enq and enq of\n module instance sq_workCompGenSQ_genWorkCompQ.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] != 2'd0) - begin - v__h129863 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] != 2'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h129863, - "\"WorkCompGen.bsv\", line 307, column 13\n", - "wcGenReqSQ.wcReqType assertion @ mkWorkCompGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] != 2'd0) - $display("wcGenReqSQ.wcReqType="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] == 2'd1) - $display("WC_REQ_TYPE_PARTIAL_ACK"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] == 2'd2) - $display("WC_REQ_TYPE_NO_WC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] != 2'd0 && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] != 2'd1 && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] != 2'd2) - $display("WC_REQ_TYPE_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] != 2'd0) - $display(" should == WC_REQ_TYPE_FULL_ACK, when error flush"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_genWorkCompQ_D_OUT[254:253] != 2'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg && - sq_workCompGenSQ_genWorkCompQ_D_OUT[856:793] != - sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg) - begin - v__h130013 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg && - sq_workCompGenSQ_genWorkCompQ_D_OUT[856:793] != - sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h130013, - "\"WorkCompGen.bsv\", line 322, column 17\n", - "wcGenReqSQ.wr.id assertion @ mkWorkCompGenSQ"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg && - sq_workCompGenSQ_genWorkCompQ_D_OUT[856:793] != - sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg) - $display("wcGenReqSQ.wr.id=%h should == firstErrPartialAckWorkReqIdReg=%h", - sq_workCompGenSQ_genWorkCompQ_D_OUT[856:793], - sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg, - ", when error flush and isFirstErrPartialAckWorkReqReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg && - sq_workCompGenSQ_genWorkCompQ_D_OUT[856:793] != - sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_sq_workCompGenSQ_errFlushSQ && - sq_workCompGenSQ_isFirstErrPartialAckWorkReqReg && - sq_workCompGenSQ_genWorkCompQ_D_OUT[856:793] != - sq_workCompGenSQ_firstErrPartialAckWorkReqIdReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (cntrl_setStateErrReg_port1__read && - (cntrl_stateReg == 4'd7 || cntrl_stateReg == 4'd0)) - begin - v__h7672 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (cntrl_setStateErrReg_port1__read && - (cntrl_stateReg == 4'd7 || cntrl_stateReg == 4'd0)) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h7672, - "\"Controller.bsv\", line 872, column 17\n", - "set state error assertion @ mkCntrlQP"); - if (RST_N != `BSV_RESET_VALUE) - if (cntrl_setStateErrReg_port1__read && - (cntrl_stateReg == 4'd7 || cntrl_stateReg == 4'd0)) - $display("stateReg="); - if (RST_N != `BSV_RESET_VALUE) - if (cntrl_setStateErrReg_port1__read && cntrl_stateReg == 4'd0) - $display("IBV_QPS_RESET"); - if (RST_N != `BSV_RESET_VALUE) - if (cntrl_setStateErrReg_port1__read && cntrl_stateReg == 4'd7) - $display("IBV_QPS_UNKNOWN"); - if (RST_N != `BSV_RESET_VALUE) - if (cntrl_setStateErrReg_port1__read && - (cntrl_stateReg == 4'd7 || cntrl_stateReg == 4'd0)) - $display(" should not be IBV_QPS_UNKNOWN or IBV_QPS_RESET"); - if (RST_N != `BSV_RESET_VALUE) - if (cntrl_setStateErrReg_port1__read && - (cntrl_stateReg == 4'd7 || cntrl_stateReg == 4'd0)) - $finish(32'd1); - end - // synopsys translate_on -endmodule // mkQP - diff --git a/ethernet/RoCEv2/blue-rdma/mkTransportLayer.v b/ethernet/RoCEv2/blue-rdma/mkTransportLayer.v deleted file mode 100644 index 6807e7c125..0000000000 --- a/ethernet/RoCEv2/blue-rdma/mkTransportLayer.v +++ /dev/null @@ -1,15640 +0,0 @@ -/* - * ------------------------------------------------------------------- - * This Verilog file has been automatically generated from a core originally written - * in Bluespec SystemVerilog (BSV). The original source code can be found at: - * - * Repository: https://github.com/datenlord/blue-rdma - * Author: DatenLord (https://datenlord.github.io/) - * - * Modifications have been made to the original core before compiling the Verilog. - * For any questions or further information regarding the modifications, please - * feel free to contact me. - * - * Modifications by: Filippo Marini - * Email: filippo.marini@pd.infn.it - * ------------------------------------------------------------------- - */ -// -// Generated by Bluespec Compiler, version 2023.01 (build 52adafa) -// -// On Wed Sep 11 15:19:55 CEST 2024 -// -// Ports: -// Name I/O size props -// RDY_workReqInput_put O 1 reg -// RDY_rdmaDataStreamInput_put O 1 reg -// rdmaDataStreamPipeOut_first O 290 reg -// RDY_rdmaDataStreamPipeOut_first O 1 reg -// RDY_rdmaDataStreamPipeOut_deq O 1 reg -// rdmaDataStreamPipeOut_notEmpty O 1 reg -// RDY_rdmaDataStreamPipeOut_notEmpty O 1 const -// workCompPipeOutSQ_first O 222 reg -// RDY_workCompPipeOutSQ_first O 1 reg -// RDY_workCompPipeOutSQ_deq O 1 reg -// workCompPipeOutSQ_notEmpty O 1 reg -// RDY_workCompPipeOutSQ_notEmpty O 1 const -// RDY_srvPortMetaData_request_put O 1 reg -// srvPortMetaData_response_get O 276 reg -// RDY_srvPortMetaData_response_get O 1 reg -// dmaReadClt_request_get O 170 reg -// RDY_dmaReadClt_request_get O 1 reg -// RDY_dmaReadClt_response_put O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// workReqInput_put I 601 reg -// rdmaDataStreamInput_put I 290 reg -// srvPortMetaData_request_put I 303 reg -// dmaReadClt_response_put I 383 reg -// EN_workReqInput_put I 1 -// EN_rdmaDataStreamInput_put I 1 -// EN_rdmaDataStreamPipeOut_deq I 1 -// EN_workCompPipeOutSQ_deq I 1 -// EN_srvPortMetaData_request_put I 1 -// EN_dmaReadClt_response_put I 1 -// EN_srvPortMetaData_response_get I 1 -// EN_dmaReadClt_request_get I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkTransportLayer(CLK, - RST_N, - - workReqInput_put, - EN_workReqInput_put, - RDY_workReqInput_put, - - rdmaDataStreamInput_put, - EN_rdmaDataStreamInput_put, - RDY_rdmaDataStreamInput_put, - - rdmaDataStreamPipeOut_first, - RDY_rdmaDataStreamPipeOut_first, - - EN_rdmaDataStreamPipeOut_deq, - RDY_rdmaDataStreamPipeOut_deq, - - rdmaDataStreamPipeOut_notEmpty, - RDY_rdmaDataStreamPipeOut_notEmpty, - - workCompPipeOutSQ_first, - RDY_workCompPipeOutSQ_first, - - EN_workCompPipeOutSQ_deq, - RDY_workCompPipeOutSQ_deq, - - workCompPipeOutSQ_notEmpty, - RDY_workCompPipeOutSQ_notEmpty, - - srvPortMetaData_request_put, - EN_srvPortMetaData_request_put, - RDY_srvPortMetaData_request_put, - - EN_srvPortMetaData_response_get, - srvPortMetaData_response_get, - RDY_srvPortMetaData_response_get, - - EN_dmaReadClt_request_get, - dmaReadClt_request_get, - RDY_dmaReadClt_request_get, - - dmaReadClt_response_put, - EN_dmaReadClt_response_put, - RDY_dmaReadClt_response_put); - input CLK; - input RST_N; - - // action method workReqInput_put - input [600 : 0] workReqInput_put; - input EN_workReqInput_put; - output RDY_workReqInput_put; - - // action method rdmaDataStreamInput_put - input [289 : 0] rdmaDataStreamInput_put; - input EN_rdmaDataStreamInput_put; - output RDY_rdmaDataStreamInput_put; - - // value method rdmaDataStreamPipeOut_first - output [289 : 0] rdmaDataStreamPipeOut_first; - output RDY_rdmaDataStreamPipeOut_first; - - // action method rdmaDataStreamPipeOut_deq - input EN_rdmaDataStreamPipeOut_deq; - output RDY_rdmaDataStreamPipeOut_deq; - - // value method rdmaDataStreamPipeOut_notEmpty - output rdmaDataStreamPipeOut_notEmpty; - output RDY_rdmaDataStreamPipeOut_notEmpty; - - // value method workCompPipeOutSQ_first - output [221 : 0] workCompPipeOutSQ_first; - output RDY_workCompPipeOutSQ_first; - - // action method workCompPipeOutSQ_deq - input EN_workCompPipeOutSQ_deq; - output RDY_workCompPipeOutSQ_deq; - - // value method workCompPipeOutSQ_notEmpty - output workCompPipeOutSQ_notEmpty; - output RDY_workCompPipeOutSQ_notEmpty; - - // action method srvPortMetaData_request_put - input [302 : 0] srvPortMetaData_request_put; - input EN_srvPortMetaData_request_put; - output RDY_srvPortMetaData_request_put; - - // actionvalue method srvPortMetaData_response_get - input EN_srvPortMetaData_response_get; - output [275 : 0] srvPortMetaData_response_get; - output RDY_srvPortMetaData_response_get; - - // actionvalue method dmaReadClt_request_get - input EN_dmaReadClt_request_get; - output [169 : 0] dmaReadClt_request_get; - output RDY_dmaReadClt_request_get; - - // action method dmaReadClt_response_put - input [382 : 0] dmaReadClt_response_put; - input EN_dmaReadClt_response_put; - output RDY_dmaReadClt_response_put; - - // signals for module outputs - wire [289 : 0] rdmaDataStreamPipeOut_first; - wire [275 : 0] srvPortMetaData_response_get; - wire [221 : 0] workCompPipeOutSQ_first; - wire [169 : 0] dmaReadClt_request_get; - wire RDY_dmaReadClt_request_get, - RDY_dmaReadClt_response_put, - RDY_rdmaDataStreamInput_put, - RDY_rdmaDataStreamPipeOut_deq, - RDY_rdmaDataStreamPipeOut_first, - RDY_rdmaDataStreamPipeOut_notEmpty, - RDY_srvPortMetaData_request_put, - RDY_srvPortMetaData_response_get, - RDY_workCompPipeOutSQ_deq, - RDY_workCompPipeOutSQ_first, - RDY_workCompPipeOutSQ_notEmpty, - RDY_workReqInput_put, - rdmaDataStreamPipeOut_notEmpty, - workCompPipeOutSQ_notEmpty; - - // inlined wires - wire [290 : 0] pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port0__read, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port0__write_1, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port1__read, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port1__write_1, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port2__read, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port2__write_1, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port3__read, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port3__write_1, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port4__read, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port4__write_1; - wire [17 : 0] headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port0__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port0__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port1__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port1__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port2__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port2__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port3__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port3__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port4__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port4__write_1; - wire _RDY_statusSQ_comm_getPMTU_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget, - _RDY_statusSQ_comm_getPMTU_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas, - _RDY_statusSQ_comm_getQKEY_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget, - _RDY_statusSQ_comm_getQKEY_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_wget, - _deq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget, - _enq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas, - _first_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_wget, - _first_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_wget, - _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget, - _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas, - _port0__read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_wget, - _port0__read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_whas, - _port0__read_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_wget, - _port0__read_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_whas, - _port0__write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_wget, - _port0__write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_whas, - _port0__write_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_wget, - _port0__write_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_whas, - _read_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_wget, - _read_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_whas, - _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_wget, - _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_whas, - _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktLenReg_wget, - _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktLenReg_whas, - _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktValidReg_wget, - _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktValidReg_whas, - _read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_wget, - _read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_whas, - _read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_isValidPktReg_wget, - _read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_isValidPktReg_whas, - _read_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_wget, - _read_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_whas, - _read_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_qpMetaData_qpTagVec_dataVec_0_wget, - _read_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_qpMetaData_qpTagVec_dataVec_0_whas, - _read_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_qpMetaData_qpTagVec_tagVec_0_wget, - _read_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_qpMetaData_qpTagVec_tagVec_0_whas, - _statusSQ_comm_getPMTU_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget, - _statusSQ_comm_getPMTU_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas, - _statusSQ_comm_getQKEY_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget, - _statusSQ_comm_getQKEY_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas, - _statusSQ_comm_isERR_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget, - _statusSQ_comm_isERR_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas, - _statusSQ_comm_isNonErr_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget, - _statusSQ_comm_isNonErr_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas, - _statusSQ_comm_isRTS_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget, - _statusSQ_comm_isRTS_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas, - _statusSQ_getTypeQP_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget, - _statusSQ_getTypeQP_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas, - _write_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_wget, - _write_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_whas, - _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_wget, - _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_whas, - _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktLenReg_wget, - _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktLenReg_whas, - _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktValidReg_wget, - _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktValidReg_whas, - _write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_wget, - _write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_whas, - _write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_isValidPktReg_wget, - _write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_isValidPktReg_whas, - _write_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_wget, - _write_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_whas, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port0__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port1__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port2__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port3__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port4__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port0__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port0__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port1__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port1__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port2__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port2__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port3__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port3__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port4__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port4__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port0__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port1__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port2__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port3__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port4__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port0__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port0__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port1__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port1__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port2__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port2__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port3__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port3__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port4__read, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port4__write_1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port0__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port1__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port2__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port3__write, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port4__write, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port0__write, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port1__write, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port2__write, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port3__write, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port4__write, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port0__read, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port0__write_1, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port1__read, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port1__write_1, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port2__read, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port2__write_1, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port3__read, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port3__write_1, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port4__read, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_port4__write_1, - pdMetaData_pdTagVec_clearReg_EN_port0__write, - pdMetaData_pdTagVec_clearReg_EN_port1__write, - pdMetaData_pdTagVec_clearReg_EN_port2__write, - pdMetaData_pdTagVec_clearReg_EN_port3__write, - pdMetaData_pdTagVec_clearReg_EN_port4__write, - pdMetaData_pdTagVec_clearReg_port0__read, - pdMetaData_pdTagVec_clearReg_port0__write_1, - pdMetaData_pdTagVec_clearReg_port1__read, - pdMetaData_pdTagVec_clearReg_port1__write_1, - pdMetaData_pdTagVec_clearReg_port2__read, - pdMetaData_pdTagVec_clearReg_port2__write_1, - pdMetaData_pdTagVec_clearReg_port3__read, - pdMetaData_pdTagVec_clearReg_port3__write_1, - pdMetaData_pdTagVec_clearReg_port4__read, - pdMetaData_pdTagVec_clearReg_port4__write_1, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port0__write, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port1__write, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port2__write, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port3__write, - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port4__write, - qpMetaData_qpTagVec_clearReg_EN_port0__write, - qpMetaData_qpTagVec_clearReg_EN_port1__write, - qpMetaData_qpTagVec_clearReg_EN_port2__write, - qpMetaData_qpTagVec_clearReg_EN_port3__write, - qpMetaData_qpTagVec_clearReg_EN_port4__write, - qpMetaData_qpTagVec_clearReg_port0__read, - qpMetaData_qpTagVec_clearReg_port0__write_1, - qpMetaData_qpTagVec_clearReg_port1__read, - qpMetaData_qpTagVec_clearReg_port1__write_1, - qpMetaData_qpTagVec_clearReg_port2__read, - qpMetaData_qpTagVec_clearReg_port2__write_1, - qpMetaData_qpTagVec_clearReg_port3__read, - qpMetaData_qpTagVec_clearReg_port3__write_1, - qpMetaData_qpTagVec_clearReg_port4__read, - qpMetaData_qpTagVec_clearReg_port4__write_1; - - // register arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg - reg arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg; - wire arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg_D_IN, - arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg - reg [289 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg; - wire [289 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg - reg [31 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg; - wire [31 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg - reg [8 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg; - wire [8 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg - reg [5 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg; - wire [5 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg - reg [8 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg; - wire [8 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg - reg [5 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg; - wire [5 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg - reg [16 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg; - wire [16 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg - reg headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_D_IN, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg - reg headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_D_IN, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg - reg [289 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg; - wire [289 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg - reg [31 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg; - wire [31 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg - reg [1 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg; - reg [1 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv - reg headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv; - wire headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_D_IN, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv - reg headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv; - wire headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_D_IN, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN; - - // register headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv - reg [17 : 0] headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv; - wire [17 : 0] headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_D_IN; - wire headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN; - - // register metaDataSrv_mrReqReg - reg [263 : 0] metaDataSrv_mrReqReg; - wire [263 : 0] metaDataSrv_mrReqReg_D_IN; - wire metaDataSrv_mrReqReg_EN; - - // register metaDataSrv_pdReqReg - reg [64 : 0] metaDataSrv_pdReqReg; - wire [64 : 0] metaDataSrv_pdReqReg_D_IN; - wire metaDataSrv_pdReqReg_EN; - - // register metaDataSrv_qpReqReg - reg [300 : 0] metaDataSrv_qpReqReg; - wire [300 : 0] metaDataSrv_qpReqReg_D_IN; - wire metaDataSrv_qpReqReg_EN; - - // register metaDataSrv_stateReg - reg [2 : 0] metaDataSrv_stateReg; - reg [2 : 0] metaDataSrv_stateReg_D_IN; - wire metaDataSrv_stateReg_EN; - - // register pdMetaData_pdMrVec_0_mrTagVec_clearReg - reg pdMetaData_pdMrVec_0_mrTagVec_clearReg; - wire pdMetaData_pdMrVec_0_mrTagVec_clearReg_D_IN, - pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN; - - // register pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 - reg [197 : 0] pdMetaData_pdMrVec_0_mrTagVec_dataVec_0; - wire [197 : 0] pdMetaData_pdMrVec_0_mrTagVec_dataVec_0_D_IN; - wire pdMetaData_pdMrVec_0_mrTagVec_dataVec_0_EN; - - // register pdMetaData_pdMrVec_0_mrTagVec_dataVec_1 - reg [197 : 0] pdMetaData_pdMrVec_0_mrTagVec_dataVec_1; - wire [197 : 0] pdMetaData_pdMrVec_0_mrTagVec_dataVec_1_D_IN; - wire pdMetaData_pdMrVec_0_mrTagVec_dataVec_1_EN; - - // register pdMetaData_pdMrVec_0_mrTagVec_fullReg - reg pdMetaData_pdMrVec_0_mrTagVec_fullReg; - wire pdMetaData_pdMrVec_0_mrTagVec_fullReg_D_IN, - pdMetaData_pdMrVec_0_mrTagVec_fullReg_EN; - - // register pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg - reg [1 : 0] pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg; - wire [1 : 0] pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg_D_IN; - wire pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg_EN; - - // register pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg - reg pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg; - wire pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg_D_IN, - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg_EN; - - // register pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg - reg [1 : 0] pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg; - wire [1 : 0] pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg_D_IN; - wire pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg_EN; - - // register pdMetaData_pdMrVec_0_mrTagVec_tagVec_0 - reg pdMetaData_pdMrVec_0_mrTagVec_tagVec_0; - wire pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_D_IN, - pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_EN; - - // register pdMetaData_pdMrVec_0_mrTagVec_tagVec_1 - reg pdMetaData_pdMrVec_0_mrTagVec_tagVec_1; - wire pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_D_IN, - pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_EN; - - // register pdMetaData_pdTagVec_clearReg - reg pdMetaData_pdTagVec_clearReg; - wire pdMetaData_pdTagVec_clearReg_D_IN, pdMetaData_pdTagVec_clearReg_EN; - - // register pdMetaData_pdTagVec_dataVec_0 - reg [31 : 0] pdMetaData_pdTagVec_dataVec_0; - wire [31 : 0] pdMetaData_pdTagVec_dataVec_0_D_IN; - wire pdMetaData_pdTagVec_dataVec_0_EN; - - // register pdMetaData_pdTagVec_fullReg - reg pdMetaData_pdTagVec_fullReg; - wire pdMetaData_pdTagVec_fullReg_D_IN, pdMetaData_pdTagVec_fullReg_EN; - - // register pdMetaData_pdTagVec_maybeInsertIdxReg - reg pdMetaData_pdTagVec_maybeInsertIdxReg; - wire pdMetaData_pdTagVec_maybeInsertIdxReg_D_IN, - pdMetaData_pdTagVec_maybeInsertIdxReg_EN; - - // register pdMetaData_pdTagVec_respSuccessReg - reg pdMetaData_pdTagVec_respSuccessReg; - wire pdMetaData_pdTagVec_respSuccessReg_D_IN, - pdMetaData_pdTagVec_respSuccessReg_EN; - - // register pdMetaData_pdTagVec_tagVecStateReg - reg [1 : 0] pdMetaData_pdTagVec_tagVecStateReg; - wire [1 : 0] pdMetaData_pdTagVec_tagVecStateReg_D_IN; - wire pdMetaData_pdTagVec_tagVecStateReg_EN; - - // register pdMetaData_pdTagVec_tagVec_0 - reg pdMetaData_pdTagVec_tagVec_0; - wire pdMetaData_pdTagVec_tagVec_0_D_IN, pdMetaData_pdTagVec_tagVec_0_EN; - - // register pktMetaDataAndPayloadPipeOutVec_bthPadCntReg - reg [1 : 0] pktMetaDataAndPayloadPipeOutVec_bthPadCntReg; - wire [1 : 0] pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_D_IN; - wire pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_isValidPktReg - reg pktMetaDataAndPayloadPipeOutVec_isValidPktReg; - wire pktMetaDataAndPayloadPipeOutVec_isValidPktReg_D_IN, - pktMetaDataAndPayloadPipeOutVec_isValidPktReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv - reg [290 : 0] pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv; - wire [290 : 0] pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_D_IN; - wire pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN; - - // register pktMetaDataAndPayloadPipeOutVec_pktBufStateReg - reg pktMetaDataAndPayloadPipeOutVec_pktBufStateReg; - wire pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_D_IN, - pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_pktFragNumReg - reg [7 : 0] pktMetaDataAndPayloadPipeOutVec_pktFragNumReg; - wire [7 : 0] pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_D_IN; - wire pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_pktLenReg - reg [12 : 0] pktMetaDataAndPayloadPipeOutVec_pktLenReg; - wire [12 : 0] pktMetaDataAndPayloadPipeOutVec_pktLenReg_D_IN; - wire pktMetaDataAndPayloadPipeOutVec_pktLenReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_pktValidReg - reg pktMetaDataAndPayloadPipeOutVec_pktValidReg; - wire pktMetaDataAndPayloadPipeOutVec_pktValidReg_D_IN, - pktMetaDataAndPayloadPipeOutVec_pktValidReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg - reg pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg - reg [512 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg; - wire [512 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg_D_IN; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg - reg [6 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg; - wire [6 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg_D_IN; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg - reg [16 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg; - wire [16 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg_D_IN; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg_EN; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg - reg [592 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg; - wire [592 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg_D_IN; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg_EN; - - // register qpMetaData_qpTagVec_clearReg - reg qpMetaData_qpTagVec_clearReg; - wire qpMetaData_qpTagVec_clearReg_D_IN, qpMetaData_qpTagVec_clearReg_EN; - - // register qpMetaData_qpTagVec_dataVec_0 - reg [31 : 0] qpMetaData_qpTagVec_dataVec_0; - wire [31 : 0] qpMetaData_qpTagVec_dataVec_0_D_IN; - wire qpMetaData_qpTagVec_dataVec_0_EN; - - // register qpMetaData_qpTagVec_fullReg - reg qpMetaData_qpTagVec_fullReg; - wire qpMetaData_qpTagVec_fullReg_D_IN, qpMetaData_qpTagVec_fullReg_EN; - - // register qpMetaData_qpTagVec_maybeInsertIdxReg - reg qpMetaData_qpTagVec_maybeInsertIdxReg; - wire qpMetaData_qpTagVec_maybeInsertIdxReg_D_IN, - qpMetaData_qpTagVec_maybeInsertIdxReg_EN; - - // register qpMetaData_qpTagVec_respSuccessReg - reg qpMetaData_qpTagVec_respSuccessReg; - wire qpMetaData_qpTagVec_respSuccessReg_D_IN, - qpMetaData_qpTagVec_respSuccessReg_EN; - - // register qpMetaData_qpTagVec_tagVecStateReg - reg [1 : 0] qpMetaData_qpTagVec_tagVecStateReg; - wire [1 : 0] qpMetaData_qpTagVec_tagVecStateReg_D_IN; - wire qpMetaData_qpTagVec_tagVecStateReg_EN; - - // register qpMetaData_qpTagVec_tagVec_0 - reg qpMetaData_qpTagVec_tagVec_0; - wire qpMetaData_qpTagVec_tagVec_0_D_IN, qpMetaData_qpTagVec_tagVec_0_EN; - - // ports of submodule arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0 - wire [169 : 0] arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_D_IN, - arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_D_OUT; - wire arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_CLR, - arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_DEQ, - arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_EMPTY_N, - arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_ENQ, - arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_FULL_N; - - // ports of submodule arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ - wire [169 : 0] arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_IN, - arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_OUT; - wire arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_CLR, - arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_DEQ, - arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N, - arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_ENQ, - arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_FULL_N; - - // ports of submodule arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ - wire arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_CLR, - arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_DEQ, - arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_EMPTY_N, - arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_ENQ, - arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_FULL_N; - - // ports of submodule arbitratedDmaReadClt_arbitratedClient_reqQ - wire [169 : 0] arbitratedDmaReadClt_arbitratedClient_reqQ_D_IN, - arbitratedDmaReadClt_arbitratedClient_reqQ_D_OUT; - wire arbitratedDmaReadClt_arbitratedClient_reqQ_CLR, - arbitratedDmaReadClt_arbitratedClient_reqQ_DEQ, - arbitratedDmaReadClt_arbitratedClient_reqQ_EMPTY_N, - arbitratedDmaReadClt_arbitratedClient_reqQ_ENQ, - arbitratedDmaReadClt_arbitratedClient_reqQ_FULL_N; - - // ports of submodule arbitratedDmaReadClt_arbitratedClient_respQ - wire [382 : 0] arbitratedDmaReadClt_arbitratedClient_respQ_D_IN, - arbitratedDmaReadClt_arbitratedClient_respQ_D_OUT; - wire arbitratedDmaReadClt_arbitratedClient_respQ_CLR, - arbitratedDmaReadClt_arbitratedClient_respQ_DEQ, - arbitratedDmaReadClt_arbitratedClient_respQ_EMPTY_N, - arbitratedDmaReadClt_arbitratedClient_respQ_ENQ, - arbitratedDmaReadClt_arbitratedClient_respQ_FULL_N; - - // ports of submodule dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ - wire [289 : 0] dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_IN, - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_OUT; - wire dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_CLR, - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_DEQ, - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N, - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_ENQ, - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_FULL_N; - - // ports of submodule headerAndMetaDataAndPayloadPipeOut_dataInQ - wire [289 : 0] headerAndMetaDataAndPayloadPipeOut_dataInQ_D_IN, - headerAndMetaDataAndPayloadPipeOut_dataInQ_D_OUT; - wire headerAndMetaDataAndPayloadPipeOut_dataInQ_CLR, - headerAndMetaDataAndPayloadPipeOut_dataInQ_DEQ, - headerAndMetaDataAndPayloadPipeOut_dataInQ_EMPTY_N, - headerAndMetaDataAndPayloadPipeOut_dataInQ_ENQ, - headerAndMetaDataAndPayloadPipeOut_dataInQ_FULL_N; - - // ports of submodule headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ - wire [289 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_IN, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_CLR, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_DEQ, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_EMPTY_N, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_ENQ, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_FULL_N; - - // ports of submodule headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ - reg [289 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_D_IN; - wire [289 : 0] headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_D_OUT; - wire headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_CLR, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_DEQ, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_EMPTY_N, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_ENQ, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_FULL_N; - - // ports of submodule headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ - wire [16 : 0] headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_IN, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT; - wire headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_CLR, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_DEQ, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_EMPTY_N, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_ENQ, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_FULL_N; - - // ports of submodule inputDataStreamQ - wire [289 : 0] inputDataStreamQ_D_IN, inputDataStreamQ_D_OUT; - wire inputDataStreamQ_CLR, - inputDataStreamQ_DEQ, - inputDataStreamQ_EMPTY_N, - inputDataStreamQ_ENQ, - inputDataStreamQ_FULL_N; - - // ports of submodule inputWorkReqQ - wire [600 : 0] inputWorkReqQ_D_IN, inputWorkReqQ_D_OUT; - wire inputWorkReqQ_CLR, - inputWorkReqQ_DEQ, - inputWorkReqQ_EMPTY_N, - inputWorkReqQ_ENQ, - inputWorkReqQ_FULL_N; - - // ports of submodule metaDataSrv_metaDataReqQ - wire [302 : 0] metaDataSrv_metaDataReqQ_D_IN, - metaDataSrv_metaDataReqQ_D_OUT; - wire metaDataSrv_metaDataReqQ_CLR, - metaDataSrv_metaDataReqQ_DEQ, - metaDataSrv_metaDataReqQ_EMPTY_N, - metaDataSrv_metaDataReqQ_ENQ, - metaDataSrv_metaDataReqQ_FULL_N; - - // ports of submodule metaDataSrv_metaDataRespQ - reg [275 : 0] metaDataSrv_metaDataRespQ_D_IN; - wire [275 : 0] metaDataSrv_metaDataRespQ_D_OUT; - wire metaDataSrv_metaDataRespQ_CLR, - metaDataSrv_metaDataRespQ_DEQ, - metaDataSrv_metaDataRespQ_EMPTY_N, - metaDataSrv_metaDataRespQ_ENQ, - metaDataSrv_metaDataRespQ_FULL_N; - - // ports of submodule pdMetaData_pdMrVec_0_mrTagVec_itemCnt - wire [1 : 0] pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_A, - pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_B, - pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_C, - pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_F, - pdMetaData_pdMrVec_0_mrTagVec_itemCnt_Q_OUT; - wire pdMetaData_pdMrVec_0_mrTagVec_itemCnt_ADDA, - pdMetaData_pdMrVec_0_mrTagVec_itemCnt_ADDB, - pdMetaData_pdMrVec_0_mrTagVec_itemCnt_SETC, - pdMetaData_pdMrVec_0_mrTagVec_itemCnt_SETF; - - // ports of submodule pdMetaData_pdMrVec_0_mrTagVec_reqQ - wire [199 : 0] pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_IN, - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT; - wire pdMetaData_pdMrVec_0_mrTagVec_reqQ_CLR, - pdMetaData_pdMrVec_0_mrTagVec_reqQ_DEQ, - pdMetaData_pdMrVec_0_mrTagVec_reqQ_EMPTY_N, - pdMetaData_pdMrVec_0_mrTagVec_reqQ_ENQ, - pdMetaData_pdMrVec_0_mrTagVec_reqQ_FULL_N; - - // ports of submodule pdMetaData_pdMrVec_0_mrTagVec_respQ - wire [199 : 0] pdMetaData_pdMrVec_0_mrTagVec_respQ_D_IN, - pdMetaData_pdMrVec_0_mrTagVec_respQ_D_OUT; - wire pdMetaData_pdMrVec_0_mrTagVec_respQ_CLR, - pdMetaData_pdMrVec_0_mrTagVec_respQ_DEQ, - pdMetaData_pdMrVec_0_mrTagVec_respQ_EMPTY_N, - pdMetaData_pdMrVec_0_mrTagVec_respQ_ENQ, - pdMetaData_pdMrVec_0_mrTagVec_respQ_FULL_N; - - // ports of submodule pdMetaData_pdTagVec_reqQ - wire [32 : 0] pdMetaData_pdTagVec_reqQ_D_IN, pdMetaData_pdTagVec_reqQ_D_OUT; - wire pdMetaData_pdTagVec_reqQ_CLR, - pdMetaData_pdTagVec_reqQ_DEQ, - pdMetaData_pdTagVec_reqQ_EMPTY_N, - pdMetaData_pdTagVec_reqQ_ENQ, - pdMetaData_pdTagVec_reqQ_FULL_N; - - // ports of submodule pdMetaData_pdTagVec_respQ - wire [32 : 0] pdMetaData_pdTagVec_respQ_D_IN, - pdMetaData_pdTagVec_respQ_D_OUT; - wire pdMetaData_pdTagVec_respQ_CLR, - pdMetaData_pdTagVec_respQ_DEQ, - pdMetaData_pdTagVec_respQ_EMPTY_N, - pdMetaData_pdTagVec_respQ_ENQ, - pdMetaData_pdTagVec_respQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0 - wire [95 : 0] pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_D_IN; - wire pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_CLR, - pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_DEQ, - pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_ENQ, - pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_payloadFilterQ - wire [289 : 0] pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_CLR, - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ - wire [289 : 0] pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_CLR, - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_payloadOutputQ - wire [290 : 0] pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_CLR, - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ - wire [303 : 0] pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_CLR, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ - wire [290 : 0] pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_CLR, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ - wire [290 : 0] pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_CLR, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ - wire [289 : 0] pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_CLR, - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_payloadRecvQ - wire [289 : 0] pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_CLR, - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_payloadValidationQ - wire [289 : 0] pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_CLR, - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ - wire [753 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ - wire [753 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ - wire [649 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ - wire [592 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ - wire [753 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ - wire [712 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ - wire [709 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ - wire [688 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ - wire [691 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ - wire [782 : 0] pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_IN, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_CLR, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_DEQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_ENQ, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0 - wire [289 : 0] pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_D_IN, - pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_CLR, - pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_DEQ, - pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_ENQ, - pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_FULL_N; - - // ports of submodule pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0 - wire [648 : 0] pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_D_IN, - pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_D_OUT; - wire pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_CLR, - pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_DEQ, - pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_EMPTY_N, - pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_ENQ, - pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_FULL_N; - - // ports of submodule qpMetaData_qpReqQ4Cntrl - wire [300 : 0] qpMetaData_qpReqQ4Cntrl_D_IN, qpMetaData_qpReqQ4Cntrl_D_OUT; - wire qpMetaData_qpReqQ4Cntrl_CLR, - qpMetaData_qpReqQ4Cntrl_DEQ, - qpMetaData_qpReqQ4Cntrl_EMPTY_N, - qpMetaData_qpReqQ4Cntrl_ENQ, - qpMetaData_qpReqQ4Cntrl_FULL_N; - - // ports of submodule qpMetaData_qpReqQ4Resp - wire [301 : 0] qpMetaData_qpReqQ4Resp_D_IN, qpMetaData_qpReqQ4Resp_D_OUT; - wire qpMetaData_qpReqQ4Resp_CLR, - qpMetaData_qpReqQ4Resp_DEQ, - qpMetaData_qpReqQ4Resp_EMPTY_N, - qpMetaData_qpReqQ4Resp_ENQ, - qpMetaData_qpReqQ4Resp_FULL_N; - - // ports of submodule qpMetaData_qpTagVec_reqQ - wire [32 : 0] qpMetaData_qpTagVec_reqQ_D_IN, qpMetaData_qpTagVec_reqQ_D_OUT; - wire qpMetaData_qpTagVec_reqQ_CLR, - qpMetaData_qpTagVec_reqQ_DEQ, - qpMetaData_qpTagVec_reqQ_EMPTY_N, - qpMetaData_qpTagVec_reqQ_ENQ, - qpMetaData_qpTagVec_reqQ_FULL_N; - - // ports of submodule qpMetaData_qpTagVec_respQ - wire [32 : 0] qpMetaData_qpTagVec_respQ_D_IN, - qpMetaData_qpTagVec_respQ_D_OUT; - wire qpMetaData_qpTagVec_respQ_CLR, - qpMetaData_qpTagVec_respQ_DEQ, - qpMetaData_qpTagVec_respQ_EMPTY_N, - qpMetaData_qpTagVec_respQ_ENQ, - qpMetaData_qpTagVec_respQ_FULL_N; - - // ports of submodule qpMetaData_qpVec_0 - reg [300 : 0] qpMetaData_qpVec_0_srvPortQP_request_put; - wire [648 : 0] qpMetaData_qpVec_0_respPktPipeIn_pktMetaData_put; - wire [600 : 0] qpMetaData_qpVec_0_workReqIn_put; - wire [382 : 0] qpMetaData_qpVec_0_dmaReadClt4SQ_response_put; - wire [289 : 0] qpMetaData_qpVec_0_rdmaReqPipeOut_first, - qpMetaData_qpVec_0_respPktPipeIn_payload_put; - wire [273 : 0] qpMetaData_qpVec_0_srvPortQP_response_get; - wire [221 : 0] qpMetaData_qpVec_0_workCompPipeOutSQ_first; - wire [169 : 0] qpMetaData_qpVec_0_dmaReadClt4SQ_request_get; - wire [31 : 0] qpMetaData_qpVec_0_statusSQ_comm_getQKEY; - wire [3 : 0] qpMetaData_qpVec_0_statusSQ_getTypeQP; - wire [2 : 0] qpMetaData_qpVec_0_statusSQ_comm_getPMTU; - wire qpMetaData_qpVec_0_EN_dmaReadClt4SQ_request_get, - qpMetaData_qpVec_0_EN_dmaReadClt4SQ_response_put, - qpMetaData_qpVec_0_EN_rdmaReqPipeOut_deq, - qpMetaData_qpVec_0_EN_respPktPipeIn_payload_put, - qpMetaData_qpVec_0_EN_respPktPipeIn_pktMetaData_put, - qpMetaData_qpVec_0_EN_srvPortQP_request_put, - qpMetaData_qpVec_0_EN_srvPortQP_response_get, - qpMetaData_qpVec_0_EN_workCompPipeOutSQ_deq, - qpMetaData_qpVec_0_EN_workReqIn_put, - qpMetaData_qpVec_0_RDY_dmaReadClt4SQ_request_get, - qpMetaData_qpVec_0_RDY_dmaReadClt4SQ_response_put, - qpMetaData_qpVec_0_RDY_rdmaReqPipeOut_deq, - qpMetaData_qpVec_0_RDY_rdmaReqPipeOut_first, - qpMetaData_qpVec_0_RDY_respPktPipeIn_payload_put, - qpMetaData_qpVec_0_RDY_respPktPipeIn_pktMetaData_put, - qpMetaData_qpVec_0_RDY_srvPortQP_request_put, - qpMetaData_qpVec_0_RDY_srvPortQP_response_get, - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU, - qpMetaData_qpVec_0_RDY_statusSQ_comm_getQKEY, - qpMetaData_qpVec_0_RDY_workCompPipeOutSQ_deq, - qpMetaData_qpVec_0_RDY_workCompPipeOutSQ_first, - qpMetaData_qpVec_0_RDY_workReqIn_put, - qpMetaData_qpVec_0_statusSQ_comm_isERR, - qpMetaData_qpVec_0_statusSQ_comm_isNonErr, - qpMetaData_qpVec_0_statusSQ_comm_isRTS; - - // ports of submodule sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ - wire [221 : 0] sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_IN, - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_OUT; - wire sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_CLR, - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_DEQ, - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N, - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_ENQ, - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_FULL_N; - - // ports of submodule workReqPipeOutVec_workReqOutVec_0 - wire [600 : 0] workReqPipeOutVec_workReqOutVec_0_D_IN, - workReqPipeOutVec_workReqOutVec_0_D_OUT; - wire workReqPipeOutVec_workReqOutVec_0_CLR, - workReqPipeOutVec_workReqOutVec_0_DEQ, - workReqPipeOutVec_workReqOutVec_0_EMPTY_N, - workReqPipeOutVec_workReqOutVec_0_ENQ, - workReqPipeOutVec_workReqOutVec_0_FULL_N; - - // rule scheduling signals - wire CAN_FIRE_RL_addNoErrWorkCompOutRule_0_checkEmptyPipeIn, - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_dispatchResponse, - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_extractReq, - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq, - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_binaryArbitrate, - CAN_FIRE_RL_dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate, - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader, - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag, - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData, - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader, - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData, - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq, - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer, - CAN_FIRE_RL_metaDataSrv_genResp4MR, - CAN_FIRE_RL_metaDataSrv_genResp4PD, - CAN_FIRE_RL_metaDataSrv_genResp4QP, - CAN_FIRE_RL_metaDataSrv_issueReq4MR, - CAN_FIRE_RL_metaDataSrv_issueReq4PD, - CAN_FIRE_RL_metaDataSrv_issueReq4QP, - CAN_FIRE_RL_metaDataSrv_recvMetaDataReq, - CAN_FIRE_RL_mkConnectionGetPut, - CAN_FIRE_RL_mkConnectionGetPut_1, - CAN_FIRE_RL_mkConnectionGetPut_2, - CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_clearAll, - CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp, - CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp, - CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq, - CAN_FIRE_RL_pdMetaData_pdTagVec_clearAll, - CAN_FIRE_RL_pdMetaData_pdTagVec_genInsertResp, - CAN_FIRE_RL_pdMetaData_pdTagVec_genRemoveResp, - CAN_FIRE_RL_pdMetaData_pdTagVec_recvReq, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_rl_into_buffer, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData, - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag, - CAN_FIRE_RL_qpMetaData_handleReqQP, - CAN_FIRE_RL_qpMetaData_qpTagVec_clearAll, - CAN_FIRE_RL_qpMetaData_qpTagVec_genInsertResp, - CAN_FIRE_RL_qpMetaData_qpTagVec_genRemoveResp, - CAN_FIRE_RL_qpMetaData_qpTagVec_recvReq, - CAN_FIRE_RL_sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate, - CAN_FIRE_RL_workReqPipeOutVec_dispatchWorkReq, - CAN_FIRE_dmaReadClt_request_get, - CAN_FIRE_dmaReadClt_response_put, - CAN_FIRE_rdmaDataStreamInput_put, - CAN_FIRE_rdmaDataStreamPipeOut_deq, - CAN_FIRE_srvPortMetaData_request_put, - CAN_FIRE_srvPortMetaData_response_get, - CAN_FIRE_workCompPipeOutSQ_deq, - CAN_FIRE_workReqInput_put, - WILL_FIRE_RL_addNoErrWorkCompOutRule_0_checkEmptyPipeIn, - WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_dispatchResponse, - WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_extractReq, - WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq, - WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_binaryArbitrate, - WILL_FIRE_RL_dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate, - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader, - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag, - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData, - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader, - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData, - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq, - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer, - WILL_FIRE_RL_metaDataSrv_genResp4MR, - WILL_FIRE_RL_metaDataSrv_genResp4PD, - WILL_FIRE_RL_metaDataSrv_genResp4QP, - WILL_FIRE_RL_metaDataSrv_issueReq4MR, - WILL_FIRE_RL_metaDataSrv_issueReq4PD, - WILL_FIRE_RL_metaDataSrv_issueReq4QP, - WILL_FIRE_RL_metaDataSrv_recvMetaDataReq, - WILL_FIRE_RL_mkConnectionGetPut, - WILL_FIRE_RL_mkConnectionGetPut_1, - WILL_FIRE_RL_mkConnectionGetPut_2, - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_clearAll, - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp, - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp, - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq, - WILL_FIRE_RL_pdMetaData_pdTagVec_clearAll, - WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp, - WILL_FIRE_RL_pdMetaData_pdTagVec_genRemoveResp, - WILL_FIRE_RL_pdMetaData_pdTagVec_recvReq, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_rl_into_buffer, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData, - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag, - WILL_FIRE_RL_qpMetaData_handleReqQP, - WILL_FIRE_RL_qpMetaData_qpTagVec_clearAll, - WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp, - WILL_FIRE_RL_qpMetaData_qpTagVec_genRemoveResp, - WILL_FIRE_RL_qpMetaData_qpTagVec_recvReq, - WILL_FIRE_RL_sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate, - WILL_FIRE_RL_workReqPipeOutVec_dispatchWorkReq, - WILL_FIRE_dmaReadClt_request_get, - WILL_FIRE_dmaReadClt_response_put, - WILL_FIRE_rdmaDataStreamInput_put, - WILL_FIRE_rdmaDataStreamPipeOut_deq, - WILL_FIRE_srvPortMetaData_request_put, - WILL_FIRE_srvPortMetaData_response_get, - WILL_FIRE_workCompPipeOutSQ_deq, - WILL_FIRE_workReqInput_put; - - // inputs to muxes for submodule ports - reg [2 : 0] MUX_metaDataSrv_stateReg_write_1__VAL_1; - wire [289 : 0] MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__VAL_2, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__VAL_3; - wire [275 : 0] MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_1, - MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_2, - MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_3; - wire [199 : 0] MUX_pdMetaData_pdMrVec_0_mrTagVec_respQ_enq_1__VAL_1, - MUX_pdMetaData_pdMrVec_0_mrTagVec_respQ_enq_1__VAL_2; - wire [32 : 0] MUX_pdMetaData_pdTagVec_respQ_enq_1__VAL_1, - MUX_pdMetaData_pdTagVec_respQ_enq_1__VAL_2, - MUX_qpMetaData_qpTagVec_respQ_enq_1__VAL_1, - MUX_qpMetaData_qpTagVec_respQ_enq_1__VAL_2; - wire [31 : 0] MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_write_1__VAL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_write_1__VAL_2; - wire [16 : 0] MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__VAL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__VAL_2; - wire [1 : 0] MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__VAL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__VAL_2, - MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg_write_1__VAL_1, - MUX_pdMetaData_pdTagVec_tagVecStateReg_write_1__VAL_1, - MUX_qpMetaData_qpTagVec_tagVecStateReg_write_1__VAL_1; - wire MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_write_1__PSEL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__SEL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_write_1__SEL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_write_1__VAL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_write_1__VAL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_write_1__VAL_2, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__SEL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_write_1__SEL_1, - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__SEL_1, - MUX_metaDataSrv_stateReg_write_1__SEL_1, - MUX_metaDataSrv_stateReg_write_1__SEL_2, - MUX_pdMetaData_pdMrVec_0_mrTagVec_emptyReg_write_1__SEL_1, - MUX_pdMetaData_pdMrVec_0_mrTagVec_fullReg_write_1__VAL_1, - MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_write_1__SEL_1, - MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_write_1__SEL_2, - MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_write_1__SEL_1, - MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_write_1__SEL_2, - MUX_pdMetaData_pdTagVec_emptyReg_write_1__SEL_1, - MUX_pdMetaData_pdTagVec_tagVec_0_write_1__SEL_1, - MUX_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_write_1__SEL_1, - MUX_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_write_1__SEL_1, - MUX_qpMetaData_qpTagVec_emptyReg_write_1__SEL_1, - MUX_qpMetaData_qpTagVec_tagVec_0_write_1__SEL_1; - - // declarations used by system tasks - // synopsys translate_off - reg [63 : 0] v__h5492; - reg [63 : 0] v__h2324; - reg [63 : 0] v__h22546; - reg [63 : 0] v__h17340; - reg [63 : 0] v__h31186; - reg [63 : 0] v__h31150; - reg [63 : 0] v__h8367; - reg [63 : 0] v__h36179; - reg [63 : 0] v__h38749; - reg [63 : 0] v__h26277; - reg [63 : 0] v__h29124; - reg [63 : 0] v__h29221; - reg [63 : 0] v__h29617; - reg [63 : 0] v__h40540; - // synopsys translate_on - - // remaining internal signals - reg [272 : 0] CASE_qpMetaData_qpReqQ4RespD_OUT_BITS_300_TO__ETC__q4; - reg [63 : 0] CASE_pdMetaData_pdMrVec_0_mrTagVec_reqQD_OUT__ETC__q3; - reg [31 : 0] CASE_qpMetaData_qpReqQ4CntrlD_OUT_BITS_300_TO_ETC__q5, - x__h38115, - x__h6207, - x__h6223; - reg [30 : 0] x__h6228, x__h6233; - reg [23 : 0] CASE_qpMetaData_qpReqQ4CntrlD_OUT_BITS_300_TO_ETC__q6; - reg [12 : 0] pktLen__h36984; - reg [7 : 0] CASE_pdMetaData_pdMrVec_0_mrTagVec_reqQD_OUT__ETC__q2, - pktFragNum__h36981; - reg [6 : 0] headerLen__h22004; - reg [5 : 0] fragLen__h36262; - reg CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1, - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q10, - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q11, - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q7, - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q8, - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q9, - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2151, - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842, - IF_qpMetaData_qpReqQ4Cntrl_first__66_BITS_300__ETC___d184, - IF_qpMetaData_qpReqQ4Resp_first__91_BITS_300_T_ETC___d314, - SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_ETC___d56; - wire [511 : 0] _theResult___headerData__h26503, - outData__h21288, - rdmaHeader_headerData__h26487, - x1_avValue_headerData__h29692; - wire [298 : 0] IF_qpMetaData_qpReqQ4Cntrl_first__66_BITS_300__ETC___d207; - wire [272 : 0] IF_pdMetaData_pdTagVec_tagVec_0_4_THEN_IF_qpMe_ETC___d338, - IF_qpMetaData_qpReqQ4Resp_first__91_BIT_301_04_ETC___d333; - wire [261 : 0] IF_pdMetaData_pdTagVec_tagVec_0_4_THEN_pdMetaD_ETC___d279; - wire [255 : 0] leftShiftData__h21796; - wire [197 : 0] SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_dataVec__ETC___d124; - wire [101 : 0] SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_dataVec__ETC___d123; - wire [63 : 0] outByteEn__h21289, - rdmaHeader_headerByteEn__h26488, - rdmaHeader_headerByteEn__h26491, - x1_avValue_headerByteEn__h29693; - wire [31 : 0] _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428, - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379, - headerLastFragByteEn__h26468, - leftShiftByteEn__h21797, - lkey__h13067, - mrReqKey__h12289, - rightAlignedByteEn__h33653, - rkey__h13068, - x1_avValue_pdHandler__h10043, - x1_avValue_snd_byteEn__h21189, - x1_avValue_snd_byteEn__h21193, - y_avValue_byteEn__h20788; - wire [23 : 0] dqpn__h31384, x1_avValue_qpn__h10044; - wire [16 : 0] IF_headerAndMetaDataAndPayloadPipeOut_headerAn_ETC___d1422; - wire [12 : 0] bits__h38056, - fragLenExtWithOutPad__h36979, - pktLen__h37124, - pktLen__h37192, - x__h38061, - y__h38112; - wire [7 : 0] pktFragNum__h37125, pktMetaData_pktFragNum__h38817; - wire [6 : 0] _theResult___headerMetaData_headerLen__h26602; - wire [5 : 0] fragValidByteNum__h26706, - headerLastFragInvalidByteNum__h17427, - lastFragValidByteNum__h22722, - lastFragValidByteNum__h22801, - value__h36219, - x__h36323; - wire [1 : 0] _theResult___headerMetaData_headerFragNum__h26603, - bits__h21377, - bits__h30478, - bits__h36334, - headerFragNum__h22721, - headerInvalidFragNum__h26376, - headerMetaData_headerFragNum__h21034, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipe_ETC___d1419, - v__h33300, - x_headerFragNum__h20036; - wire IF_headerAndMetaDataAndPayloadPipeOut_headerAn_ETC___d451, - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2265, - IF_pktMetaDataAndPayloadPipeOutVec_payloadRecv_ETC___d1675, - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1849, - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1855, - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1884, - NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1518, - NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1549, - NOT_pdMetaData_pdTagVec_tagVec_0_4_1_OR_qpMeta_ETC___d253, - metaDataSrv_metaDataRespQ_i_notFull__60_AND_NO_ETC___d318, - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1861, - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1918, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenC_ETC___d1950, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenC_ETC___d2185, - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_i_ETC___d1565, - pktMetaDataAndPayloadPipeOutVec_payloadValidat_ETC___d1712, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilt_ETC___d1910, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecv_ETC___d1674, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderVali_ETC___d1858, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderVali_ETC___d1886, - x__h22733; - - // action method workReqInput_put - assign RDY_workReqInput_put = inputWorkReqQ_FULL_N ; - assign CAN_FIRE_workReqInput_put = inputWorkReqQ_FULL_N ; - assign WILL_FIRE_workReqInput_put = EN_workReqInput_put ; - - // action method rdmaDataStreamInput_put - assign RDY_rdmaDataStreamInput_put = inputDataStreamQ_FULL_N ; - assign CAN_FIRE_rdmaDataStreamInput_put = inputDataStreamQ_FULL_N ; - assign WILL_FIRE_rdmaDataStreamInput_put = EN_rdmaDataStreamInput_put ; - - // value method rdmaDataStreamPipeOut_first - assign rdmaDataStreamPipeOut_first = - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_OUT ; - assign RDY_rdmaDataStreamPipeOut_first = - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N ; - - // action method rdmaDataStreamPipeOut_deq - assign RDY_rdmaDataStreamPipeOut_deq = - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N ; - assign CAN_FIRE_rdmaDataStreamPipeOut_deq = - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N ; - assign WILL_FIRE_rdmaDataStreamPipeOut_deq = EN_rdmaDataStreamPipeOut_deq ; - - // value method rdmaDataStreamPipeOut_notEmpty - assign rdmaDataStreamPipeOut_notEmpty = - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N ; - assign RDY_rdmaDataStreamPipeOut_notEmpty = 1'd1 ; - - // value method workCompPipeOutSQ_first - assign workCompPipeOutSQ_first = - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_OUT ; - assign RDY_workCompPipeOutSQ_first = - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N ; - - // action method workCompPipeOutSQ_deq - assign RDY_workCompPipeOutSQ_deq = - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N ; - assign CAN_FIRE_workCompPipeOutSQ_deq = - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N ; - assign WILL_FIRE_workCompPipeOutSQ_deq = EN_workCompPipeOutSQ_deq ; - - // value method workCompPipeOutSQ_notEmpty - assign workCompPipeOutSQ_notEmpty = - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N ; - assign RDY_workCompPipeOutSQ_notEmpty = 1'd1 ; - - // action method srvPortMetaData_request_put - assign RDY_srvPortMetaData_request_put = metaDataSrv_metaDataReqQ_FULL_N ; - assign CAN_FIRE_srvPortMetaData_request_put = - metaDataSrv_metaDataReqQ_FULL_N ; - assign WILL_FIRE_srvPortMetaData_request_put = - EN_srvPortMetaData_request_put ; - - // actionvalue method srvPortMetaData_response_get - assign srvPortMetaData_response_get = metaDataSrv_metaDataRespQ_D_OUT ; - assign RDY_srvPortMetaData_response_get = - metaDataSrv_metaDataRespQ_EMPTY_N ; - assign CAN_FIRE_srvPortMetaData_response_get = - metaDataSrv_metaDataRespQ_EMPTY_N ; - assign WILL_FIRE_srvPortMetaData_response_get = - EN_srvPortMetaData_response_get ; - - // actionvalue method dmaReadClt_request_get - assign dmaReadClt_request_get = - arbitratedDmaReadClt_arbitratedClient_reqQ_D_OUT ; - assign RDY_dmaReadClt_request_get = - arbitratedDmaReadClt_arbitratedClient_reqQ_EMPTY_N ; - assign CAN_FIRE_dmaReadClt_request_get = - arbitratedDmaReadClt_arbitratedClient_reqQ_EMPTY_N ; - assign WILL_FIRE_dmaReadClt_request_get = EN_dmaReadClt_request_get ; - - // action method dmaReadClt_response_put - assign RDY_dmaReadClt_response_put = - arbitratedDmaReadClt_arbitratedClient_respQ_FULL_N ; - assign CAN_FIRE_dmaReadClt_response_put = - arbitratedDmaReadClt_arbitratedClient_respQ_FULL_N ; - assign WILL_FIRE_dmaReadClt_response_put = EN_dmaReadClt_response_put ; - - // submodule arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0 - FIFO2 #(.width(32'd170), - .guarded(1'd1)) arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0(.RST(RST_N), - .CLK(CLK), - .D_IN(arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_D_IN), - .ENQ(arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_ENQ), - .DEQ(arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_DEQ), - .CLR(arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_CLR), - .D_OUT(arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_D_OUT), - .FULL_N(arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_FULL_N), - .EMPTY_N(arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_EMPTY_N)); - - // submodule arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ - FIFO2 #(.width(32'd170), - .guarded(1'd1)) arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_IN), - .ENQ(arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_ENQ), - .DEQ(arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_DEQ), - .CLR(arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_CLR), - .D_OUT(arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_OUT), - .FULL_N(arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_FULL_N), - .EMPTY_N(arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N)); - - // submodule arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ - FIFO20 #(.guarded(1'd1)) arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ(.RST(RST_N), - .CLK(CLK), - .ENQ(arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_ENQ), - .DEQ(arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_DEQ), - .CLR(arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_CLR), - .FULL_N(arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_FULL_N), - .EMPTY_N(arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_EMPTY_N)); - - // submodule arbitratedDmaReadClt_arbitratedClient_reqQ - FIFO2 #(.width(32'd170), - .guarded(1'd1)) arbitratedDmaReadClt_arbitratedClient_reqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(arbitratedDmaReadClt_arbitratedClient_reqQ_D_IN), - .ENQ(arbitratedDmaReadClt_arbitratedClient_reqQ_ENQ), - .DEQ(arbitratedDmaReadClt_arbitratedClient_reqQ_DEQ), - .CLR(arbitratedDmaReadClt_arbitratedClient_reqQ_CLR), - .D_OUT(arbitratedDmaReadClt_arbitratedClient_reqQ_D_OUT), - .FULL_N(arbitratedDmaReadClt_arbitratedClient_reqQ_FULL_N), - .EMPTY_N(arbitratedDmaReadClt_arbitratedClient_reqQ_EMPTY_N)); - - // submodule arbitratedDmaReadClt_arbitratedClient_respQ - FIFO2 #(.width(32'd383), - .guarded(1'd1)) arbitratedDmaReadClt_arbitratedClient_respQ(.RST(RST_N), - .CLK(CLK), - .D_IN(arbitratedDmaReadClt_arbitratedClient_respQ_D_IN), - .ENQ(arbitratedDmaReadClt_arbitratedClient_respQ_ENQ), - .DEQ(arbitratedDmaReadClt_arbitratedClient_respQ_DEQ), - .CLR(arbitratedDmaReadClt_arbitratedClient_respQ_CLR), - .D_OUT(arbitratedDmaReadClt_arbitratedClient_respQ_D_OUT), - .FULL_N(arbitratedDmaReadClt_arbitratedClient_respQ_FULL_N), - .EMPTY_N(arbitratedDmaReadClt_arbitratedClient_respQ_EMPTY_N)); - - // submodule dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_IN), - .ENQ(dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_ENQ), - .DEQ(dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_DEQ), - .CLR(dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_CLR), - .D_OUT(dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_OUT), - .FULL_N(dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_FULL_N), - .EMPTY_N(dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N)); - - // submodule headerAndMetaDataAndPayloadPipeOut_dataInQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) headerAndMetaDataAndPayloadPipeOut_dataInQ(.RST(RST_N), - .CLK(CLK), - .D_IN(headerAndMetaDataAndPayloadPipeOut_dataInQ_D_IN), - .ENQ(headerAndMetaDataAndPayloadPipeOut_dataInQ_ENQ), - .DEQ(headerAndMetaDataAndPayloadPipeOut_dataInQ_DEQ), - .CLR(headerAndMetaDataAndPayloadPipeOut_dataInQ_CLR), - .D_OUT(headerAndMetaDataAndPayloadPipeOut_dataInQ_D_OUT), - .FULL_N(headerAndMetaDataAndPayloadPipeOut_dataInQ_FULL_N), - .EMPTY_N(headerAndMetaDataAndPayloadPipeOut_dataInQ_EMPTY_N)); - - // submodule headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_IN), - .ENQ(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_ENQ), - .DEQ(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_DEQ), - .CLR(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_CLR), - .D_OUT(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT), - .FULL_N(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_FULL_N), - .EMPTY_N(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_EMPTY_N)); - - // submodule headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_D_IN), - .ENQ(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_ENQ), - .DEQ(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_DEQ), - .CLR(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_CLR), - .D_OUT(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_D_OUT), - .FULL_N(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_FULL_N), - .EMPTY_N(headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_EMPTY_N)); - - // submodule headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ - FIFO2 #(.width(32'd17), - .guarded(1'd1)) headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ(.RST(RST_N), - .CLK(CLK), - .D_IN(headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_IN), - .ENQ(headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_ENQ), - .DEQ(headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_DEQ), - .CLR(headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_CLR), - .D_OUT(headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT), - .FULL_N(headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_FULL_N), - .EMPTY_N(headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_EMPTY_N)); - - // submodule inputDataStreamQ - FIFO2 #(.width(32'd290), .guarded(1'd1)) inputDataStreamQ(.RST(RST_N), - .CLK(CLK), - .D_IN(inputDataStreamQ_D_IN), - .ENQ(inputDataStreamQ_ENQ), - .DEQ(inputDataStreamQ_DEQ), - .CLR(inputDataStreamQ_CLR), - .D_OUT(inputDataStreamQ_D_OUT), - .FULL_N(inputDataStreamQ_FULL_N), - .EMPTY_N(inputDataStreamQ_EMPTY_N)); - - // submodule inputWorkReqQ - FIFO2 #(.width(32'd601), .guarded(1'd1)) inputWorkReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(inputWorkReqQ_D_IN), - .ENQ(inputWorkReqQ_ENQ), - .DEQ(inputWorkReqQ_DEQ), - .CLR(inputWorkReqQ_CLR), - .D_OUT(inputWorkReqQ_D_OUT), - .FULL_N(inputWorkReqQ_FULL_N), - .EMPTY_N(inputWorkReqQ_EMPTY_N)); - - // submodule metaDataSrv_metaDataReqQ - FIFO2 #(.width(32'd303), - .guarded(1'd1)) metaDataSrv_metaDataReqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(metaDataSrv_metaDataReqQ_D_IN), - .ENQ(metaDataSrv_metaDataReqQ_ENQ), - .DEQ(metaDataSrv_metaDataReqQ_DEQ), - .CLR(metaDataSrv_metaDataReqQ_CLR), - .D_OUT(metaDataSrv_metaDataReqQ_D_OUT), - .FULL_N(metaDataSrv_metaDataReqQ_FULL_N), - .EMPTY_N(metaDataSrv_metaDataReqQ_EMPTY_N)); - - // submodule metaDataSrv_metaDataRespQ - FIFO2 #(.width(32'd276), - .guarded(1'd1)) metaDataSrv_metaDataRespQ(.RST(RST_N), - .CLK(CLK), - .D_IN(metaDataSrv_metaDataRespQ_D_IN), - .ENQ(metaDataSrv_metaDataRespQ_ENQ), - .DEQ(metaDataSrv_metaDataRespQ_DEQ), - .CLR(metaDataSrv_metaDataRespQ_CLR), - .D_OUT(metaDataSrv_metaDataRespQ_D_OUT), - .FULL_N(metaDataSrv_metaDataRespQ_FULL_N), - .EMPTY_N(metaDataSrv_metaDataRespQ_EMPTY_N)); - - // submodule pdMetaData_pdMrVec_0_mrTagVec_itemCnt - Counter #(.width(32'd2), - .init(2'd0)) pdMetaData_pdMrVec_0_mrTagVec_itemCnt(.CLK(CLK), - .RST(RST_N), - .DATA_A(pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_A), - .DATA_B(pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_B), - .DATA_C(pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_C), - .DATA_F(pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_F), - .ADDA(pdMetaData_pdMrVec_0_mrTagVec_itemCnt_ADDA), - .ADDB(pdMetaData_pdMrVec_0_mrTagVec_itemCnt_ADDB), - .SETC(pdMetaData_pdMrVec_0_mrTagVec_itemCnt_SETC), - .SETF(pdMetaData_pdMrVec_0_mrTagVec_itemCnt_SETF), - .Q_OUT(pdMetaData_pdMrVec_0_mrTagVec_itemCnt_Q_OUT)); - - // submodule pdMetaData_pdMrVec_0_mrTagVec_reqQ - FIFO2 #(.width(32'd200), - .guarded(1'd1)) pdMetaData_pdMrVec_0_mrTagVec_reqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_IN), - .ENQ(pdMetaData_pdMrVec_0_mrTagVec_reqQ_ENQ), - .DEQ(pdMetaData_pdMrVec_0_mrTagVec_reqQ_DEQ), - .CLR(pdMetaData_pdMrVec_0_mrTagVec_reqQ_CLR), - .D_OUT(pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT), - .FULL_N(pdMetaData_pdMrVec_0_mrTagVec_reqQ_FULL_N), - .EMPTY_N(pdMetaData_pdMrVec_0_mrTagVec_reqQ_EMPTY_N)); - - // submodule pdMetaData_pdMrVec_0_mrTagVec_respQ - FIFO2 #(.width(32'd200), - .guarded(1'd1)) pdMetaData_pdMrVec_0_mrTagVec_respQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pdMetaData_pdMrVec_0_mrTagVec_respQ_D_IN), - .ENQ(pdMetaData_pdMrVec_0_mrTagVec_respQ_ENQ), - .DEQ(pdMetaData_pdMrVec_0_mrTagVec_respQ_DEQ), - .CLR(pdMetaData_pdMrVec_0_mrTagVec_respQ_CLR), - .D_OUT(pdMetaData_pdMrVec_0_mrTagVec_respQ_D_OUT), - .FULL_N(pdMetaData_pdMrVec_0_mrTagVec_respQ_FULL_N), - .EMPTY_N(pdMetaData_pdMrVec_0_mrTagVec_respQ_EMPTY_N)); - - // submodule pdMetaData_pdTagVec_reqQ - FIFO2 #(.width(32'd33), - .guarded(1'd1)) pdMetaData_pdTagVec_reqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pdMetaData_pdTagVec_reqQ_D_IN), - .ENQ(pdMetaData_pdTagVec_reqQ_ENQ), - .DEQ(pdMetaData_pdTagVec_reqQ_DEQ), - .CLR(pdMetaData_pdTagVec_reqQ_CLR), - .D_OUT(pdMetaData_pdTagVec_reqQ_D_OUT), - .FULL_N(pdMetaData_pdTagVec_reqQ_FULL_N), - .EMPTY_N(pdMetaData_pdTagVec_reqQ_EMPTY_N)); - - // submodule pdMetaData_pdTagVec_respQ - FIFO2 #(.width(32'd33), - .guarded(1'd1)) pdMetaData_pdTagVec_respQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pdMetaData_pdTagVec_respQ_D_IN), - .ENQ(pdMetaData_pdTagVec_respQ_ENQ), - .DEQ(pdMetaData_pdTagVec_respQ_DEQ), - .CLR(pdMetaData_pdTagVec_respQ_CLR), - .D_OUT(pdMetaData_pdTagVec_respQ_D_OUT), - .FULL_N(pdMetaData_pdTagVec_respQ_FULL_N), - .EMPTY_N(pdMetaData_pdTagVec_respQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0 - FIFO2 #(.width(32'd96), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_CLR), - .D_OUT(), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadFilterQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_payloadFilterQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadOutputQ - FIFO2 #(.width(32'd291), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_payloadOutputQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ - FIFO2 #(.width(32'd304), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ - FIFO2 #(.width(32'd291), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ - FIFO2 #(.width(32'd291), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadRecvQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_payloadRecvQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadValidationQ - FIFO2 #(.width(32'd290), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_payloadValidationQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ - FIFO2 #(.width(32'd754), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ - FIFO2 #(.width(32'd754), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ - FIFO2 #(.width(32'd650), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ - FIFO2 #(.width(32'd593), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ - FIFO2 #(.width(32'd754), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ - FIFO2 #(.width(32'd713), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ - FIFO2 #(.width(32'd710), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ - FIFO2 #(.width(32'd689), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ - FIFO2 #(.width(32'd692), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ - FIFO2 #(.width(32'd783), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0 - FIFO2 #(.width(32'd290), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_EMPTY_N)); - - // submodule pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0 - FIFO2 #(.width(32'd649), - .guarded(1'd1)) pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0(.RST(RST_N), - .CLK(CLK), - .D_IN(pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_D_IN), - .ENQ(pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_ENQ), - .DEQ(pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_DEQ), - .CLR(pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_CLR), - .D_OUT(pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_D_OUT), - .FULL_N(pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_FULL_N), - .EMPTY_N(pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_EMPTY_N)); - - // submodule qpMetaData_qpReqQ4Cntrl - FIFO2 #(.width(32'd301), - .guarded(1'd1)) qpMetaData_qpReqQ4Cntrl(.RST(RST_N), - .CLK(CLK), - .D_IN(qpMetaData_qpReqQ4Cntrl_D_IN), - .ENQ(qpMetaData_qpReqQ4Cntrl_ENQ), - .DEQ(qpMetaData_qpReqQ4Cntrl_DEQ), - .CLR(qpMetaData_qpReqQ4Cntrl_CLR), - .D_OUT(qpMetaData_qpReqQ4Cntrl_D_OUT), - .FULL_N(qpMetaData_qpReqQ4Cntrl_FULL_N), - .EMPTY_N(qpMetaData_qpReqQ4Cntrl_EMPTY_N)); - - // submodule qpMetaData_qpReqQ4Resp - FIFO2 #(.width(32'd302), .guarded(1'd1)) qpMetaData_qpReqQ4Resp(.RST(RST_N), - .CLK(CLK), - .D_IN(qpMetaData_qpReqQ4Resp_D_IN), - .ENQ(qpMetaData_qpReqQ4Resp_ENQ), - .DEQ(qpMetaData_qpReqQ4Resp_DEQ), - .CLR(qpMetaData_qpReqQ4Resp_CLR), - .D_OUT(qpMetaData_qpReqQ4Resp_D_OUT), - .FULL_N(qpMetaData_qpReqQ4Resp_FULL_N), - .EMPTY_N(qpMetaData_qpReqQ4Resp_EMPTY_N)); - - // submodule qpMetaData_qpTagVec_reqQ - FIFO2 #(.width(32'd33), - .guarded(1'd1)) qpMetaData_qpTagVec_reqQ(.RST(RST_N), - .CLK(CLK), - .D_IN(qpMetaData_qpTagVec_reqQ_D_IN), - .ENQ(qpMetaData_qpTagVec_reqQ_ENQ), - .DEQ(qpMetaData_qpTagVec_reqQ_DEQ), - .CLR(qpMetaData_qpTagVec_reqQ_CLR), - .D_OUT(qpMetaData_qpTagVec_reqQ_D_OUT), - .FULL_N(qpMetaData_qpTagVec_reqQ_FULL_N), - .EMPTY_N(qpMetaData_qpTagVec_reqQ_EMPTY_N)); - - // submodule qpMetaData_qpTagVec_respQ - FIFO2 #(.width(32'd33), - .guarded(1'd1)) qpMetaData_qpTagVec_respQ(.RST(RST_N), - .CLK(CLK), - .D_IN(qpMetaData_qpTagVec_respQ_D_IN), - .ENQ(qpMetaData_qpTagVec_respQ_ENQ), - .DEQ(qpMetaData_qpTagVec_respQ_DEQ), - .CLR(qpMetaData_qpTagVec_respQ_CLR), - .D_OUT(qpMetaData_qpTagVec_respQ_D_OUT), - .FULL_N(qpMetaData_qpTagVec_respQ_FULL_N), - .EMPTY_N(qpMetaData_qpTagVec_respQ_EMPTY_N)); - - // submodule qpMetaData_qpVec_0 - mkQP qpMetaData_qpVec_0(.CLK(CLK), - .RST_N(RST_N), - .dmaReadClt4SQ_response_put(qpMetaData_qpVec_0_dmaReadClt4SQ_response_put), - .respPktPipeIn_payload_put(qpMetaData_qpVec_0_respPktPipeIn_payload_put), - .respPktPipeIn_pktMetaData_put(qpMetaData_qpVec_0_respPktPipeIn_pktMetaData_put), - .srvPortQP_request_put(qpMetaData_qpVec_0_srvPortQP_request_put), - .workReqIn_put(qpMetaData_qpVec_0_workReqIn_put), - .EN_srvPortQP_request_put(qpMetaData_qpVec_0_EN_srvPortQP_request_put), - .EN_srvPortQP_response_get(qpMetaData_qpVec_0_EN_srvPortQP_response_get), - .EN_workReqIn_put(qpMetaData_qpVec_0_EN_workReqIn_put), - .EN_dmaReadClt4SQ_request_get(qpMetaData_qpVec_0_EN_dmaReadClt4SQ_request_get), - .EN_dmaReadClt4SQ_response_put(qpMetaData_qpVec_0_EN_dmaReadClt4SQ_response_put), - .EN_respPktPipeIn_pktMetaData_put(qpMetaData_qpVec_0_EN_respPktPipeIn_pktMetaData_put), - .EN_respPktPipeIn_payload_put(qpMetaData_qpVec_0_EN_respPktPipeIn_payload_put), - .EN_rdmaReqPipeOut_deq(qpMetaData_qpVec_0_EN_rdmaReqPipeOut_deq), - .EN_workCompPipeOutSQ_deq(qpMetaData_qpVec_0_EN_workCompPipeOutSQ_deq), - .RDY_srvPortQP_request_put(qpMetaData_qpVec_0_RDY_srvPortQP_request_put), - .srvPortQP_response_get(qpMetaData_qpVec_0_srvPortQP_response_get), - .RDY_srvPortQP_response_get(qpMetaData_qpVec_0_RDY_srvPortQP_response_get), - .RDY_workReqIn_put(qpMetaData_qpVec_0_RDY_workReqIn_put), - .dmaReadClt4SQ_request_get(qpMetaData_qpVec_0_dmaReadClt4SQ_request_get), - .RDY_dmaReadClt4SQ_request_get(qpMetaData_qpVec_0_RDY_dmaReadClt4SQ_request_get), - .RDY_dmaReadClt4SQ_response_put(qpMetaData_qpVec_0_RDY_dmaReadClt4SQ_response_put), - .RDY_respPktPipeIn_pktMetaData_put(qpMetaData_qpVec_0_RDY_respPktPipeIn_pktMetaData_put), - .RDY_respPktPipeIn_payload_put(qpMetaData_qpVec_0_RDY_respPktPipeIn_payload_put), - .statusSQ_comm_isCreate(), - .RDY_statusSQ_comm_isCreate(), - .statusSQ_comm_isERR(qpMetaData_qpVec_0_statusSQ_comm_isERR), - .RDY_statusSQ_comm_isERR(), - .statusSQ_comm_isInit(), - .RDY_statusSQ_comm_isInit(), - .statusSQ_comm_isReset(), - .RDY_statusSQ_comm_isReset(), - .statusSQ_comm_isRTR(), - .RDY_statusSQ_comm_isRTR(), - .statusSQ_comm_isRTS(qpMetaData_qpVec_0_statusSQ_comm_isRTS), - .RDY_statusSQ_comm_isRTS(), - .statusSQ_comm_isSQD(), - .RDY_statusSQ_comm_isSQD(), - .statusSQ_comm_isNonErr(qpMetaData_qpVec_0_statusSQ_comm_isNonErr), - .RDY_statusSQ_comm_isNonErr(), - .statusSQ_comm_isUnknown(), - .RDY_statusSQ_comm_isUnknown(), - .statusSQ_comm_isRTR2RTS(), - .RDY_statusSQ_comm_isRTR2RTS(), - .statusSQ_comm_isStableRTS(), - .RDY_statusSQ_comm_isStableRTS(), - .statusSQ_comm_getAccessFlags(), - .RDY_statusSQ_comm_getAccessFlags(), - .statusSQ_comm_getMaxRnrCnt(), - .RDY_statusSQ_comm_getMaxRnrCnt(), - .statusSQ_comm_getMaxRetryCnt(), - .RDY_statusSQ_comm_getMaxRetryCnt(), - .statusSQ_comm_getMinRnrTimer(), - .RDY_statusSQ_comm_getMinRnrTimer(), - .statusSQ_comm_getMaxTimeOut(), - .RDY_statusSQ_comm_getMaxTimeOut(), - .statusSQ_comm_getPendingWorkReqNum(), - .RDY_statusSQ_comm_getPendingWorkReqNum(), - .statusSQ_comm_getPendingRecvReqNum(), - .RDY_statusSQ_comm_getPendingRecvReqNum(), - .statusSQ_comm_getPendingReadAtomicReqNum(), - .RDY_statusSQ_comm_getPendingReadAtomicReqNum(), - .statusSQ_comm_getPendingDestReadAtomicReqNum(), - .RDY_statusSQ_comm_getPendingDestReadAtomicReqNum(), - .statusSQ_comm_getSigAll(), - .RDY_statusSQ_comm_getSigAll(), - .statusSQ_comm_getSQPN(), - .RDY_statusSQ_comm_getSQPN(), - .statusSQ_comm_getDQPN(), - .RDY_statusSQ_comm_getDQPN(), - .statusSQ_comm_getPKEY(), - .RDY_statusSQ_comm_getPKEY(), - .statusSQ_comm_getQKEY(qpMetaData_qpVec_0_statusSQ_comm_getQKEY), - .RDY_statusSQ_comm_getQKEY(qpMetaData_qpVec_0_RDY_statusSQ_comm_getQKEY), - .statusSQ_comm_getPMTU(qpMetaData_qpVec_0_statusSQ_comm_getPMTU), - .RDY_statusSQ_comm_getPMTU(qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU), - .statusSQ_getTypeQP(qpMetaData_qpVec_0_statusSQ_getTypeQP), - .RDY_statusSQ_getTypeQP(), - .statusSQ_isSQ(), - .RDY_statusSQ_isSQ(), - .rdmaReqPipeOut_first(qpMetaData_qpVec_0_rdmaReqPipeOut_first), - .RDY_rdmaReqPipeOut_first(qpMetaData_qpVec_0_RDY_rdmaReqPipeOut_first), - .RDY_rdmaReqPipeOut_deq(qpMetaData_qpVec_0_RDY_rdmaReqPipeOut_deq), - .rdmaReqPipeOut_notEmpty(), - .RDY_rdmaReqPipeOut_notEmpty(), - .workCompPipeOutSQ_first(qpMetaData_qpVec_0_workCompPipeOutSQ_first), - .RDY_workCompPipeOutSQ_first(qpMetaData_qpVec_0_RDY_workCompPipeOutSQ_first), - .RDY_workCompPipeOutSQ_deq(qpMetaData_qpVec_0_RDY_workCompPipeOutSQ_deq), - .workCompPipeOutSQ_notEmpty(), - .RDY_workCompPipeOutSQ_notEmpty()); - - // submodule sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ - FIFO2 #(.width(32'd222), - .guarded(1'd1)) sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ(.RST(RST_N), - .CLK(CLK), - .D_IN(sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_IN), - .ENQ(sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_ENQ), - .DEQ(sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_DEQ), - .CLR(sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_CLR), - .D_OUT(sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_OUT), - .FULL_N(sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_FULL_N), - .EMPTY_N(sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N)); - - // submodule workReqPipeOutVec_workReqOutVec_0 - FIFO2 #(.width(32'd601), - .guarded(1'd1)) workReqPipeOutVec_workReqOutVec_0(.RST(RST_N), - .CLK(CLK), - .D_IN(workReqPipeOutVec_workReqOutVec_0_D_IN), - .ENQ(workReqPipeOutVec_workReqOutVec_0_ENQ), - .DEQ(workReqPipeOutVec_workReqOutVec_0_DEQ), - .CLR(workReqPipeOutVec_workReqOutVec_0_CLR), - .D_OUT(workReqPipeOutVec_workReqOutVec_0_D_OUT), - .FULL_N(workReqPipeOutVec_workReqOutVec_0_FULL_N), - .EMPTY_N(workReqPipeOutVec_workReqOutVec_0_EMPTY_N)); - - // rule RL_mkConnectionGetPut - assign CAN_FIRE_RL_mkConnectionGetPut = - qpMetaData_qpVec_0_RDY_workReqIn_put && - workReqPipeOutVec_workReqOutVec_0_EMPTY_N ; - assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ; - - // rule RL_mkConnectionGetPut_1 - assign CAN_FIRE_RL_mkConnectionGetPut_1 = - qpMetaData_qpVec_0_RDY_respPktPipeIn_pktMetaData_put && - pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_EMPTY_N ; - assign WILL_FIRE_RL_mkConnectionGetPut_1 = - CAN_FIRE_RL_mkConnectionGetPut_1 ; - - // rule RL_mkConnectionGetPut_2 - assign CAN_FIRE_RL_mkConnectionGetPut_2 = - qpMetaData_qpVec_0_RDY_respPktPipeIn_payload_put && - pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_EMPTY_N ; - assign WILL_FIRE_RL_mkConnectionGetPut_2 = - CAN_FIRE_RL_mkConnectionGetPut_2 ; - - // rule RL_pdMetaData_pdTagVec_recvReq - assign CAN_FIRE_RL_pdMetaData_pdTagVec_recvReq = - pdMetaData_pdTagVec_reqQ_EMPTY_N && - !pdMetaData_pdTagVec_clearReg && - pdMetaData_pdTagVec_tagVecStateReg == 2'd0 ; - assign WILL_FIRE_RL_pdMetaData_pdTagVec_recvReq = - CAN_FIRE_RL_pdMetaData_pdTagVec_recvReq ; - - // rule RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq - assign CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq = - pdMetaData_pdMrVec_0_mrTagVec_reqQ_EMPTY_N && - !pdMetaData_pdMrVec_0_mrTagVec_clearReg && - pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg == 2'd0 ; - assign WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq = - CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq ; - - // rule RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp - assign CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp = - pdMetaData_pdMrVec_0_mrTagVec_reqQ_EMPTY_N && - pdMetaData_pdMrVec_0_mrTagVec_respQ_FULL_N && - !pdMetaData_pdMrVec_0_mrTagVec_clearReg && - pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg == 2'd1 ; - assign WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp = - CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp ; - - // rule RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp - assign CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp = - pdMetaData_pdMrVec_0_mrTagVec_reqQ_EMPTY_N && - pdMetaData_pdMrVec_0_mrTagVec_respQ_FULL_N && - !pdMetaData_pdMrVec_0_mrTagVec_clearReg && - pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg == 2'd2 ; - assign WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp = - CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp ; - - // rule RL_qpMetaData_handleReqQP - assign CAN_FIRE_RL_qpMetaData_handleReqQP = - qpMetaData_qpReqQ4Cntrl_EMPTY_N && - qpMetaData_qpReqQ4Resp_FULL_N && - IF_qpMetaData_qpReqQ4Cntrl_first__66_BITS_300__ETC___d184 ; - assign WILL_FIRE_RL_qpMetaData_handleReqQP = - CAN_FIRE_RL_qpMetaData_handleReqQP ; - - // rule RL_qpMetaData_qpTagVec_recvReq - assign CAN_FIRE_RL_qpMetaData_qpTagVec_recvReq = - qpMetaData_qpTagVec_reqQ_EMPTY_N && - !qpMetaData_qpTagVec_clearReg && - qpMetaData_qpTagVec_tagVecStateReg == 2'd0 ; - assign WILL_FIRE_RL_qpMetaData_qpTagVec_recvReq = - CAN_FIRE_RL_qpMetaData_qpTagVec_recvReq ; - - // rule RL_metaDataSrv_recvMetaDataReq - assign CAN_FIRE_RL_metaDataSrv_recvMetaDataReq = - metaDataSrv_metaDataReqQ_EMPTY_N && - metaDataSrv_stateReg == 3'd0 ; - assign WILL_FIRE_RL_metaDataSrv_recvMetaDataReq = - CAN_FIRE_RL_metaDataSrv_recvMetaDataReq ; - - // rule RL_metaDataSrv_issueReq4MR - assign CAN_FIRE_RL_metaDataSrv_issueReq4MR = - (!pdMetaData_pdTagVec_tagVec_0 || - pdMetaData_pdMrVec_0_mrTagVec_reqQ_FULL_N) && - metaDataSrv_stateReg == 3'd1 ; - assign WILL_FIRE_RL_metaDataSrv_issueReq4MR = - CAN_FIRE_RL_metaDataSrv_issueReq4MR ; - - // rule RL_metaDataSrv_issueReq4PD - assign CAN_FIRE_RL_metaDataSrv_issueReq4PD = - pdMetaData_pdTagVec_reqQ_FULL_N && metaDataSrv_stateReg == 3'd2 ; - assign WILL_FIRE_RL_metaDataSrv_issueReq4PD = - CAN_FIRE_RL_metaDataSrv_issueReq4PD ; - - // rule RL_metaDataSrv_issueReq4QP - assign CAN_FIRE_RL_metaDataSrv_issueReq4QP = - NOT_pdMetaData_pdTagVec_tagVec_0_4_1_OR_qpMeta_ETC___d253 && - metaDataSrv_stateReg == 3'd3 ; - assign WILL_FIRE_RL_metaDataSrv_issueReq4QP = - CAN_FIRE_RL_metaDataSrv_issueReq4QP ; - - // rule RL_metaDataSrv_genResp4MR - assign CAN_FIRE_RL_metaDataSrv_genResp4MR = - metaDataSrv_metaDataRespQ_FULL_N && - (!pdMetaData_pdTagVec_tagVec_0 || - pdMetaData_pdMrVec_0_mrTagVec_respQ_EMPTY_N) && - metaDataSrv_stateReg == 3'd4 ; - assign WILL_FIRE_RL_metaDataSrv_genResp4MR = - CAN_FIRE_RL_metaDataSrv_genResp4MR ; - - // rule RL_pdMetaData_pdMrVec_0_mrTagVec_clearAll - assign CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_clearAll = - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - assign WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_clearAll = - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - - // rule RL_metaDataSrv_genResp4PD - assign CAN_FIRE_RL_metaDataSrv_genResp4PD = - metaDataSrv_metaDataRespQ_FULL_N && - pdMetaData_pdTagVec_respQ_EMPTY_N && - metaDataSrv_stateReg == 3'd5 ; - assign WILL_FIRE_RL_metaDataSrv_genResp4PD = - CAN_FIRE_RL_metaDataSrv_genResp4PD ; - - // rule RL_metaDataSrv_genResp4QP - assign CAN_FIRE_RL_metaDataSrv_genResp4QP = - metaDataSrv_metaDataRespQ_i_notFull__60_AND_NO_ETC___d318 && - metaDataSrv_stateReg == 3'd6 ; - assign WILL_FIRE_RL_metaDataSrv_genResp4QP = - CAN_FIRE_RL_metaDataSrv_genResp4QP ; - - // rule RL_pdMetaData_pdTagVec_clearAll - assign CAN_FIRE_RL_pdMetaData_pdTagVec_clearAll = - pdMetaData_pdTagVec_clearReg ; - assign WILL_FIRE_RL_pdMetaData_pdTagVec_clearAll = - pdMetaData_pdTagVec_clearReg ; - - // rule RL_pdMetaData_pdTagVec_genInsertResp - assign CAN_FIRE_RL_pdMetaData_pdTagVec_genInsertResp = - pdMetaData_pdTagVec_reqQ_EMPTY_N && - pdMetaData_pdTagVec_respQ_FULL_N && - !pdMetaData_pdTagVec_clearReg && - pdMetaData_pdTagVec_tagVecStateReg == 2'd1 ; - assign WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp = - CAN_FIRE_RL_pdMetaData_pdTagVec_genInsertResp ; - - // rule RL_pdMetaData_pdTagVec_genRemoveResp - assign CAN_FIRE_RL_pdMetaData_pdTagVec_genRemoveResp = - pdMetaData_pdTagVec_reqQ_EMPTY_N && - pdMetaData_pdTagVec_respQ_FULL_N && - !pdMetaData_pdTagVec_clearReg && - pdMetaData_pdTagVec_tagVecStateReg == 2'd2 ; - assign WILL_FIRE_RL_pdMetaData_pdTagVec_genRemoveResp = - CAN_FIRE_RL_pdMetaData_pdTagVec_genRemoveResp ; - - // rule RL_workReqPipeOutVec_dispatchWorkReq - assign CAN_FIRE_RL_workReqPipeOutVec_dispatchWorkReq = - inputWorkReqQ_EMPTY_N && - workReqPipeOutVec_workReqOutVec_0_FULL_N ; - assign WILL_FIRE_RL_workReqPipeOutVec_dispatchWorkReq = - CAN_FIRE_RL_workReqPipeOutVec_dispatchWorkReq ; - - // rule RL_headerAndMetaDataAndPayloadPipeOut_extractHeader - assign CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader = - inputDataStreamQ_EMPTY_N && - headerAndMetaDataAndPayloadPipeOut_dataInQ_FULL_N && - (!inputDataStreamQ_D_OUT[1] || - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_FULL_N) ; - assign WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader ; - - // rule RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData - assign CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_EMPTY_N && - !headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv && - headerAndMetaDataAndPayloadPipeOut_dataInQ_EMPTY_N && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg == - 2'd0 ; - assign WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // rule RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader - assign CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_FULL_N && - IF_headerAndMetaDataAndPayloadPipeOut_headerAn_ETC___d451 && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg == - 2'd1 ; - assign WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader ; - - // rule RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData - assign CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_FULL_N && - (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - headerAndMetaDataAndPayloadPipeOut_dataInQ_EMPTY_N) && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg == - 2'd2 ; - assign WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData ; - - // rule RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag - assign CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_FULL_N && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg == - 2'd3 ; - assign WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[290] && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_i_ETC___d1565 ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader = - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_EMPTY_N && - IF_pktMetaDataAndPayloadPipeOutVec_payloadRecv_ETC___d1675 && - !pktMetaDataAndPayloadPipeOutVec_pktBufStateReg ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[290] && - pktMetaDataAndPayloadPipeOutVec_pktBufStateReg ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadValidat_ETC___d1712 ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - - // rule RL_qpMetaData_qpTagVec_clearAll - assign CAN_FIRE_RL_qpMetaData_qpTagVec_clearAll = - qpMetaData_qpTagVec_clearReg ; - assign WILL_FIRE_RL_qpMetaData_qpTagVec_clearAll = - qpMetaData_qpTagVec_clearReg ; - - // rule RL_qpMetaData_qpTagVec_genInsertResp - assign CAN_FIRE_RL_qpMetaData_qpTagVec_genInsertResp = - qpMetaData_qpTagVec_reqQ_EMPTY_N && - qpMetaData_qpTagVec_respQ_FULL_N && - !qpMetaData_qpTagVec_clearReg && - qpMetaData_qpTagVec_tagVecStateReg == 2'd1 ; - assign WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp = - CAN_FIRE_RL_qpMetaData_qpTagVec_genInsertResp ; - - // rule RL_qpMetaData_qpTagVec_genRemoveResp - assign CAN_FIRE_RL_qpMetaData_qpTagVec_genRemoveResp = - qpMetaData_qpTagVec_reqQ_EMPTY_N && - qpMetaData_qpTagVec_respQ_FULL_N && - !qpMetaData_qpTagVec_clearReg && - qpMetaData_qpTagVec_tagVecStateReg == 2'd2 ; - assign WILL_FIRE_RL_qpMetaData_qpTagVec_genRemoveResp = - CAN_FIRE_RL_qpMetaData_qpTagVec_genRemoveResp ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1861 ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen = - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenC_ETC___d1950 ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_FULL_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[14] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_FULL_N) ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenC_ETC___d2185 ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_EMPTY_N && - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2265 ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_outputPayload - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload = - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_EMPTY_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_OUT[0] || - pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_FULL_N) ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_EMPTY_N && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_OUT[0] || - pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_FULL_N) ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_rl_into_buffer - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_rl_into_buffer = - !pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port1__read[290] && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_EMPTY_N ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_rl_into_buffer = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_rl_into_buffer ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv[17] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData ; - - // rule RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer - assign CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_EMPTY_N && - !headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port1__read[17] && - !headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv ; - assign WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer ; - - // rule RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq - assign CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_EMPTY_N && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port1__read && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port1__read ; - assign WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_EMPTY_N && - (!headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_FULL_N) && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate ; - - // rule RL_addNoErrWorkCompOutRule_0_checkEmptyPipeIn - assign CAN_FIRE_RL_addNoErrWorkCompOutRule_0_checkEmptyPipeIn = 1'd1 ; - assign WILL_FIRE_RL_addNoErrWorkCompOutRule_0_checkEmptyPipeIn = 1'd1 ; - - // rule RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt - assign CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_EMPTY_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilt_ETC___d1910) && - (pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1918 || - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_FULL_N) ; - assign WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - - // rule RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq - assign CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq = - arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_EMPTY_N && - arbitratedDmaReadClt_arbitratedClient_reqQ_FULL_N && - (!arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg || - arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_FULL_N) ; - assign WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq ; - - // rule RL_arbitratedDmaReadClt_arbitratedClient_dispatchResponse - assign CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_dispatchResponse = - qpMetaData_qpVec_0_RDY_dmaReadClt4SQ_response_put && - arbitratedDmaReadClt_arbitratedClient_respQ_EMPTY_N && - (!arbitratedDmaReadClt_arbitratedClient_respQ_D_OUT[0] || - arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_EMPTY_N) ; - assign WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_dispatchResponse = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_dispatchResponse ; - - // rule RL_arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_binaryArbitrate - assign CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_binaryArbitrate = - arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_EMPTY_N && - arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_FULL_N ; - assign WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_binaryArbitrate = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_binaryArbitrate ; - - // rule RL_arbitratedDmaReadClt_arbitratedClient_extractReq - assign CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_extractReq = - qpMetaData_qpVec_0_RDY_dmaReadClt4SQ_request_get && - arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_FULL_N ; - assign WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_extractReq = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_extractReq ; - - // rule RL_dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate - assign CAN_FIRE_RL_dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate = - qpMetaData_qpVec_0_RDY_rdmaReqPipeOut_deq && - qpMetaData_qpVec_0_RDY_rdmaReqPipeOut_first && - dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_FULL_N ; - assign WILL_FIRE_RL_dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate = - CAN_FIRE_RL_dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate ; - - // rule RL_sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate - assign CAN_FIRE_RL_sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate = - qpMetaData_qpVec_0_RDY_workCompPipeOutSQ_deq && - qpMetaData_qpVec_0_RDY_workCompPipeOutSQ_first && - sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_FULL_N ; - assign WILL_FIRE_RL_sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate = - CAN_FIRE_RL_sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate ; - - // inputs to muxes for submodule ports - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_write_1__PSEL_1 = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__SEL_1 = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_write_1__SEL_1 = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader && - (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg) ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__SEL_1 = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] && - (bits__h21377 == 2'd0 || - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg) ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_write_1__SEL_1 = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_write_1__PSEL_1 && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__SEL_1 = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] ; - assign MUX_metaDataSrv_stateReg_write_1__SEL_1 = - WILL_FIRE_RL_metaDataSrv_recvMetaDataReq && - (metaDataSrv_metaDataReqQ_D_OUT[302:301] == 2'd1 || - metaDataSrv_metaDataReqQ_D_OUT[302:301] == 2'd0 || - metaDataSrv_metaDataReqQ_D_OUT[302:301] == 2'd2) ; - assign MUX_metaDataSrv_stateReg_write_1__SEL_2 = - WILL_FIRE_RL_metaDataSrv_genResp4QP || - WILL_FIRE_RL_metaDataSrv_genResp4PD || - WILL_FIRE_RL_metaDataSrv_genResp4MR ; - assign MUX_pdMetaData_pdMrVec_0_mrTagVec_emptyReg_write_1__SEL_1 = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq && - (pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[199] && - !pdMetaData_pdMrVec_0_mrTagVec_fullReg || - !pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[199] && - SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_ETC___d56) ; - assign MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_write_1__SEL_1 = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[0] == 1'd0 && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg ; - assign MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_write_1__SEL_2 = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp && - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0] == 1'd0 ; - assign MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_write_1__SEL_1 = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[0] == 1'd1 && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg ; - assign MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_write_1__SEL_2 = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp && - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0] == 1'd1 ; - assign MUX_pdMetaData_pdTagVec_emptyReg_write_1__SEL_1 = - WILL_FIRE_RL_pdMetaData_pdTagVec_recvReq && - (pdMetaData_pdTagVec_reqQ_D_OUT[32] && - !pdMetaData_pdTagVec_fullReg || - !pdMetaData_pdTagVec_reqQ_D_OUT[32] && - pdMetaData_pdTagVec_tagVec_0) ; - assign MUX_pdMetaData_pdTagVec_tagVec_0_write_1__SEL_1 = - WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp && - pdMetaData_pdTagVec_respSuccessReg ; - assign MUX_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_write_1__SEL_1 = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag && - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[0] ; - assign MUX_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_write_1__SEL_1 = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] ; - assign MUX_qpMetaData_qpTagVec_emptyReg_write_1__SEL_1 = - WILL_FIRE_RL_qpMetaData_qpTagVec_recvReq && - (qpMetaData_qpTagVec_reqQ_D_OUT[32] && - !qpMetaData_qpTagVec_fullReg || - !qpMetaData_qpTagVec_reqQ_D_OUT[32] && - qpMetaData_qpTagVec_tagVec_0) ; - assign MUX_qpMetaData_qpTagVec_tagVec_0_write_1__SEL_1 = - WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp && - qpMetaData_qpTagVec_respSuccessReg ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__VAL_1 = - { headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg[16:10], - headerMetaData_headerFragNum__h21034, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg[7:0] } ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__VAL_2 = - { headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10], - x_headerFragNum__h20036, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[7:0] } ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_write_1__VAL_1 = - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - bits__h21377 != 2'd0 && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_write_1__VAL_1 = - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg[9] && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg[8] ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_write_1__VAL_2 = - !headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[9] && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[8] ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__VAL_2 = - { outData__h21288[255:0], - outByteEn__h21289[31:0], - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] && - bits__h21377 == 2'd0 } ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__VAL_3 = - { leftShiftData__h21796, - leftShiftByteEn__h21797, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg, - 1'd1 } ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_write_1__VAL_1 = - headerAndMetaDataAndPayloadPipeOut_dataInQ_D_OUT[33:2] << - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_write_1__VAL_2 = - headerAndMetaDataAndPayloadPipeOut_dataInQ_D_OUT[33:2] << - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[7:2] ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__VAL_1 = - (bits__h21377 == 2'd0) ? bits__h21377 : 2'd3 ; - assign MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__VAL_2 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] ? - ((bits__h21377 != 2'd0 && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg) ? - 2'd3 : - 2'd0) : - 2'd2 ; - assign MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_1 = - { 13'd2730, - pdMetaData_pdTagVec_tagVec_0 && - pdMetaData_pdMrVec_0_mrTagVec_respQ_D_OUT[199], - IF_pdMetaData_pdTagVec_tagVec_0_4_THEN_pdMetaD_ETC___d279 } ; - assign MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_2 = - { 211'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA, - pdMetaData_pdTagVec_respQ_D_OUT, - pdMetaData_pdTagVec_respQ_D_OUT[31:0] } ; - assign MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_3 = - { 2'd2, - pdMetaData_pdTagVec_tagVec_0 && - qpMetaData_qpReqQ4Resp_D_OUT[301] && - qpMetaData_qpVec_0_srvPortQP_response_get[273], - IF_pdMetaData_pdTagVec_tagVec_0_4_THEN_IF_qpMe_ETC___d338 } ; - always@(metaDataSrv_metaDataReqQ_D_OUT) - begin - case (metaDataSrv_metaDataReqQ_D_OUT[302:301]) - 2'd0: MUX_metaDataSrv_stateReg_write_1__VAL_1 = 3'd2; - 2'd1: MUX_metaDataSrv_stateReg_write_1__VAL_1 = 3'd1; - default: MUX_metaDataSrv_stateReg_write_1__VAL_1 = 3'd3; - endcase - end - assign MUX_pdMetaData_pdMrVec_0_mrTagVec_fullReg_write_1__VAL_1 = - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[199] && - pdMetaData_pdMrVec_0_mrTagVec_itemCnt_Q_OUT[0] ; - assign MUX_pdMetaData_pdMrVec_0_mrTagVec_respQ_enq_1__VAL_1 = - { pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg, - pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[0], - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[198:1] } ; - assign MUX_pdMetaData_pdMrVec_0_mrTagVec_respQ_enq_1__VAL_2 = - { pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg, - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0], - SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_dataVec__ETC___d124 } ; - assign MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg_write_1__VAL_1 = - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[199] ? 2'd1 : 2'd2 ; - assign MUX_pdMetaData_pdTagVec_respQ_enq_1__VAL_1 = - { pdMetaData_pdTagVec_respSuccessReg, - pdMetaData_pdTagVec_reqQ_D_OUT[31:0] } ; - assign MUX_pdMetaData_pdTagVec_respQ_enq_1__VAL_2 = - { pdMetaData_pdTagVec_respSuccessReg, - pdMetaData_pdTagVec_dataVec_0 } ; - assign MUX_pdMetaData_pdTagVec_tagVecStateReg_write_1__VAL_1 = - pdMetaData_pdTagVec_reqQ_D_OUT[32] ? 2'd1 : 2'd2 ; - assign MUX_qpMetaData_qpTagVec_respQ_enq_1__VAL_1 = - { qpMetaData_qpTagVec_respSuccessReg, - qpMetaData_qpTagVec_reqQ_D_OUT[31:0] } ; - assign MUX_qpMetaData_qpTagVec_respQ_enq_1__VAL_2 = - { qpMetaData_qpTagVec_respSuccessReg, - qpMetaData_qpTagVec_dataVec_0 } ; - assign MUX_qpMetaData_qpTagVec_tagVecStateReg_write_1__VAL_1 = - qpMetaData_qpTagVec_reqQ_D_OUT[32] ? 2'd1 : 2'd2 ; - - // inlined wires - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[1] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[1] && - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[290] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_FULL_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget = - 1'd1 ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[290] && - (!pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_FULL_N) ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign _port0__write_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_wget = - 1'd1 ; - assign _port0__write_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign _port0__read_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_wget = - 1'b1 ; - assign _port0__read_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[1] ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[1] ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[290] ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_wget = - !pktMetaDataAndPayloadPipeOutVec_pktBufStateReg && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0] || - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_FULL_N) && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_EMPTY_N ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_wget = - IF_pktMetaDataAndPayloadPipeOutVec_payloadRecv_ETC___d1675 && - !pktMetaDataAndPayloadPipeOutVec_pktBufStateReg ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget = - !pktMetaDataAndPayloadPipeOutVec_pktBufStateReg && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0] && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_EMPTY_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0] || - !pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget = - !pktMetaDataAndPayloadPipeOutVec_pktBufStateReg && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_EMPTY_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_wget = - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_EMPTY_N && - IF_pktMetaDataAndPayloadPipeOutVec_payloadRecv_ETC___d1675 ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_wget = - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0]) && - !pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[0] ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[290] ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[0] ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag ; - assign _port0__write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_wget = - 1'd1 ; - assign _port0__write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag ; - assign _port0__read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_wget = - 1'b1 ; - assign _port0__read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag_EN_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_qpMetaData_qpTagVec_dataVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_qpMetaData_qpTagVec_dataVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_qpMetaData_qpTagVec_tagVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_qpMetaData_qpTagVec_tagVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_EMPTY_N ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidat_ETC___d1712 ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_FULL_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget = - 1'd1 ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_EMPTY_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_FULL_N) ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign _statusSQ_getTypeQP_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] != - 3'd4 && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] != - 3'd3 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[36:5] == - qpMetaData_qpVec_0_statusSQ_comm_getQKEY) && - (qpMetaData_qpVec_0_statusSQ_comm_isERR || - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1884) && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd3 && - !qpMetaData_qpVec_0_RDY_statusSQ_comm_getQKEY && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] && - (qpMetaData_qpVec_0_statusSQ_comm_isERR || - !IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1849) && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N && - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N ; - assign _statusSQ_getTypeQP_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _statusSQ_comm_getPMTU_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] ; - assign _statusSQ_comm_getPMTU_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _RDY_statusSQ_comm_getPMTU_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] || - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1855) && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N ; - assign _RDY_statusSQ_comm_getPMTU_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _statusSQ_comm_getQKEY_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd3 && - (qpMetaData_qpVec_0_statusSQ_comm_isERR || - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1884) && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd4 || - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1) && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] ; - assign _statusSQ_comm_getQKEY_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _RDY_statusSQ_comm_getQKEY_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] && - !IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842 && - (qpMetaData_qpVec_0_statusSQ_comm_isERR || - !IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1849) && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N && - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N ; - assign _RDY_statusSQ_comm_getQKEY_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _statusSQ_comm_isNonErr_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget = - !qpMetaData_qpVec_0_statusSQ_comm_isERR && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4] && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] != - 3'd3 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[36:5] == - qpMetaData_qpVec_0_statusSQ_comm_getQKEY) && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd4 || - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1) && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd3 && - !qpMetaData_qpVec_0_RDY_statusSQ_comm_getQKEY && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] && - !IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842 && - !qpMetaData_qpVec_0_statusSQ_comm_isERR && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4] && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N && - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N ; - assign _statusSQ_comm_isNonErr_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _statusSQ_comm_isRTS_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget = - !qpMetaData_qpVec_0_statusSQ_comm_isERR && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] != - 3'd3 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[36:5] == - qpMetaData_qpVec_0_statusSQ_comm_getQKEY) && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd4 || - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1) && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4]) && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd3 && - !qpMetaData_qpVec_0_RDY_statusSQ_comm_getQKEY && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] && - !IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842 && - !qpMetaData_qpVec_0_statusSQ_comm_isERR && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N && - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4]) && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N ; - assign _statusSQ_comm_isRTS_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _statusSQ_comm_isERR_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_wget = - !IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1884 && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] != - 3'd3 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[36:5] == - qpMetaData_qpVec_0_statusSQ_comm_getQKEY) && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd4 || - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1) && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd3 && - !qpMetaData_qpVec_0_RDY_statusSQ_comm_getQKEY && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] && - !IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842 && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N && - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N && - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1849 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N ; - assign _statusSQ_comm_isERR_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_qpMetaData_qpVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] || - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1855) && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N && - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1861 ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] || - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1855) && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N && - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget = - 1'd1 ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_EMPTY_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] || - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderVali_ETC___d1858) ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] && - (pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1918 || - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_FULL_N) && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_EMPTY_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] || - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] ? - pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_FULL_N : - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_FULL_N)) && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_EMPTY_N ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_wget = - (!pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilt_ETC___d1910) && - (pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1918 || - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_FULL_N) ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] && - (pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1918 || - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_FULL_N) && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_EMPTY_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] ? - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] : - pktMetaDataAndPayloadPipeOutVec_isValidPktReg ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget = - !pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1918 && - (!pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilt_ETC___d1910) && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_EMPTY_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_isValidPktReg_wget = - !pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_isValidPktReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_isValidPktReg_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt_EN_pktMetaDataAndPayloadPipeOutVec_isValidPktReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_EMPTY_N ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenC_ETC___d1950 ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_FULL_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget = - 1'd1 ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_EMPTY_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_FULL_N) ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_wget = - !pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_wget = - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen_EN_pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[14] ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_wget = - (!pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[14] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_FULL_N) && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_EMPTY_N ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_wget = - (!pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[14] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_FULL_N) && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_EMPTY_N ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[14] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[14] && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_EMPTY_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget = - 1'd1 ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget = - (!pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[14] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_FULL_N) && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_EMPTY_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[15:14] != - 2'b11 && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[15:14] != - 2'b10 ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_wget = - 1'd1 ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktLenReg_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[15:14] != - 2'b10 && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[15:14] != - 2'b11 ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktLenReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktLenReg_wget = - 1'd1 ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktLenReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktValidReg_wget = - _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktLenReg_wget ; - assign _read_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktValidReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktValidReg_wget = - 1'd1 ; - assign _write_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen_EN_pktMetaDataAndPayloadPipeOutVec_pktValidReg_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT[1] ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT[1] ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_EMPTY_N ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenC_ETC___d2185 ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT[1] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_FULL_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget = - 1'd1 ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_EMPTY_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_FULL_N) ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_wget = - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2] || - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_FULL_N) && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_wget = - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2265 ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget = - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2] || - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_FULL_N) && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget = - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget = - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2] && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_EMPTY_N ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_OUT[0] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_OUT[0] ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_wget = - !pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_OUT[0] || - pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_FULL_N ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload_EN_pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_OUT[0] ; - assign _enq_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_wget = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_OUT[0] ; - assign _i_notFull_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget = - 1'b1 ; - assign _first_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget = - 1'd1 ; - assign _deq_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_wget = - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_OUT[0] || - pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_FULL_N ; - assign _i_notEmpty_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData_EN_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_whas = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData ; - assign pdMetaData_pdTagVec_clearReg_port0__read = - pdMetaData_pdTagVec_clearReg ; - assign pdMetaData_pdTagVec_clearReg_EN_port0__write = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_port0__write_1 = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_port1__read = - pdMetaData_pdTagVec_clearReg ; - assign pdMetaData_pdTagVec_clearReg_EN_port1__write = - pdMetaData_pdTagVec_clearReg ; - assign pdMetaData_pdTagVec_clearReg_port1__write_1 = 1'd0 ; - assign pdMetaData_pdTagVec_clearReg_port2__read = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_EN_port2__write = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_port2__write_1 = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_port3__read = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_EN_port3__write = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_port3__write_1 = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_port4__read = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_EN_port4__write = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_port4__write_1 = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port0__read = - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port0__write = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port0__write_1 = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port1__read = - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port1__write = - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port1__write_1 = 1'd0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port2__read = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port2__write = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port2__write_1 = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port3__read = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port3__write = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port3__write_1 = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port4__read = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN_port4__write = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_port4__write_1 = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_port0__read = - qpMetaData_qpTagVec_clearReg ; - assign qpMetaData_qpTagVec_clearReg_EN_port0__write = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_port0__write_1 = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_port1__read = - qpMetaData_qpTagVec_clearReg ; - assign qpMetaData_qpTagVec_clearReg_EN_port1__write = - qpMetaData_qpTagVec_clearReg ; - assign qpMetaData_qpTagVec_clearReg_port1__write_1 = 1'd0 ; - assign qpMetaData_qpTagVec_clearReg_port2__read = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_EN_port2__write = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_port2__write_1 = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_port3__read = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_EN_port3__write = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_port3__write_1 = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_port4__read = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_EN_port4__write = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_port4__write_1 = 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port0__read = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port0__write = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port0__write_1 = - 1'd1 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port1__read = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData || - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port1__write = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port1__write_1 = - 1'd0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port2__read = - !CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port1__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port2__write = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port2__write_1 = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port3__read = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port2__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port3__write = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port3__write_1 = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port4__read = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port2__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN_port4__write = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port4__write_1 = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port0__read = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port0__write = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port0__write_1 = - 1'd1 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port1__read = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer || - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port1__write = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port1__write_1 = - 1'd0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port2__read = - !CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port1__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port2__write = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port2__write_1 = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port3__read = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port2__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port3__write = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port3__write_1 = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port4__read = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port2__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN_port4__write = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port4__write_1 = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port0__read = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port0__write = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port0__write_1 = - 18'd43690 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port1__read = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData ? - 18'd43690 : - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port1__write = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port1__write_1 = - { 1'd1, - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT } ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port2__read = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_rl_into_buffer ? - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port1__write_1 : - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port1__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port2__write = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port2__write_1 = - 18'h0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port3__read = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port2__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port3__write = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port3__write_1 = - 18'h0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port4__read = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port2__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN_port4__write = - 1'b0 ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port4__write_1 = - 18'h0 ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port0__read = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port0__write = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag || - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port0__write_1 = - 291'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port1__read = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port0__write ? - 291'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA : - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port1__write = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_rl_into_buffer ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port1__write_1 = - { 1'd1, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_D_OUT } ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port2__read = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_rl_into_buffer ? - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port1__write_1 : - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port1__read ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port2__write = - 1'b0 ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port2__write_1 = - 291'h0 ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port3__read = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port2__read ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port3__write = - 1'b0 ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port3__write_1 = - 291'h0 ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port4__read = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port2__read ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN_port4__write = - 1'b0 ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port4__write_1 = - 291'h0 ; - - // register arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg - assign arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg_D_IN = - 1'd1 ; - assign arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg_EN = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_D_IN = - headerAndMetaDataAndPayloadPipeOut_dataInQ_D_OUT ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_EN = - (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader) && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg_D_IN = - { _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[0], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[1], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[2], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[3], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[4], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[5], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[6], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[7], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[8], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[9], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[10], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[11], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[12], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[13], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[14], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[15], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[16], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[17], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[18], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[19], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[20], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[21], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[22], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[23], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[24], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[25], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[26], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[27], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[28], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[29], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[30], - _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379[31] } ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg_EN = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg_D_IN = - { headerLastFragInvalidByteNum__h17427, 3'd0 } ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg_EN = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg_D_IN = - headerLastFragInvalidByteNum__h17427 ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg_EN = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg_D_IN = - { headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[7:2], - 3'd0 } ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg_EN = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg_D_IN = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[7:2] ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg_EN = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_D_IN = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__SEL_1 ? - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__VAL_1 : - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__VAL_2 ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_EN = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_D_IN = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_write_1__SEL_1 && - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_write_1__VAL_1 ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_EN = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader && - (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg) || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_D_IN = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_write_1__SEL_1 ? - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_write_1__VAL_1 : - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_write_1__VAL_2 ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_EN = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg_D_IN = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg_EN = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_write_1__PSEL_1 ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_D_IN = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_write_1__SEL_1 ? - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_write_1__VAL_1 : - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_write_1__VAL_2 ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_EN = - (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader) && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg - always@(MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__SEL_1 or - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__VAL_1 or - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_write_1__SEL_1 or - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__VAL_2 or - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag or - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData) - begin - case (1'b1) // synopsys parallel_case - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__SEL_1: - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_D_IN = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__VAL_1; - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_write_1__SEL_1: - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_D_IN = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_write_1__VAL_2; - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag: - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_D_IN = - 2'd0; - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData: - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_D_IN = - 2'd1; - default: headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_D_IN = - 2'b10 /* unspecified value */ ; - endcase - end - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_EN = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader && - (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg) || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - - // register headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_D_IN = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_port2__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN = - 1'b1 ; - - // register headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_D_IN = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_port2__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN = - 1'b1 ; - - // register headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_D_IN = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_port2__read ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN = - 1'b1 ; - - // register metaDataSrv_mrReqReg - assign metaDataSrv_mrReqReg_D_IN = metaDataSrv_metaDataReqQ_D_OUT[263:0] ; - assign metaDataSrv_mrReqReg_EN = - WILL_FIRE_RL_metaDataSrv_recvMetaDataReq && - metaDataSrv_metaDataReqQ_D_OUT[302:301] == 2'd1 ; - - // register metaDataSrv_pdReqReg - assign metaDataSrv_pdReqReg_D_IN = metaDataSrv_metaDataReqQ_D_OUT[64:0] ; - assign metaDataSrv_pdReqReg_EN = - WILL_FIRE_RL_metaDataSrv_recvMetaDataReq && - metaDataSrv_metaDataReqQ_D_OUT[302:301] == 2'd0 ; - - // register metaDataSrv_qpReqReg - assign metaDataSrv_qpReqReg_D_IN = metaDataSrv_metaDataReqQ_D_OUT[300:0] ; - assign metaDataSrv_qpReqReg_EN = - WILL_FIRE_RL_metaDataSrv_recvMetaDataReq && - metaDataSrv_metaDataReqQ_D_OUT[302:301] == 2'd2 ; - - // register metaDataSrv_stateReg - always@(MUX_metaDataSrv_stateReg_write_1__SEL_1 or - MUX_metaDataSrv_stateReg_write_1__VAL_1 or - MUX_metaDataSrv_stateReg_write_1__SEL_2 or - WILL_FIRE_RL_metaDataSrv_issueReq4MR or - WILL_FIRE_RL_metaDataSrv_issueReq4PD or - WILL_FIRE_RL_metaDataSrv_issueReq4QP) - begin - case (1'b1) // synopsys parallel_case - MUX_metaDataSrv_stateReg_write_1__SEL_1: - metaDataSrv_stateReg_D_IN = MUX_metaDataSrv_stateReg_write_1__VAL_1; - MUX_metaDataSrv_stateReg_write_1__SEL_2: - metaDataSrv_stateReg_D_IN = 3'd0; - WILL_FIRE_RL_metaDataSrv_issueReq4MR: metaDataSrv_stateReg_D_IN = 3'd4; - WILL_FIRE_RL_metaDataSrv_issueReq4PD: metaDataSrv_stateReg_D_IN = 3'd5; - WILL_FIRE_RL_metaDataSrv_issueReq4QP: metaDataSrv_stateReg_D_IN = 3'd6; - default: metaDataSrv_stateReg_D_IN = 3'b010 /* unspecified value */ ; - endcase - end - assign metaDataSrv_stateReg_EN = - WILL_FIRE_RL_metaDataSrv_recvMetaDataReq && - (metaDataSrv_metaDataReqQ_D_OUT[302:301] == 2'd1 || - metaDataSrv_metaDataReqQ_D_OUT[302:301] == 2'd0 || - metaDataSrv_metaDataReqQ_D_OUT[302:301] == 2'd2) || - WILL_FIRE_RL_metaDataSrv_genResp4QP || - WILL_FIRE_RL_metaDataSrv_genResp4PD || - WILL_FIRE_RL_metaDataSrv_genResp4MR || - WILL_FIRE_RL_metaDataSrv_issueReq4MR || - WILL_FIRE_RL_metaDataSrv_issueReq4PD || - WILL_FIRE_RL_metaDataSrv_issueReq4QP ; - - // register pdMetaData_pdMrVec_0_mrTagVec_clearReg - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_D_IN = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN = 1'b1 ; - - // register pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 - assign pdMetaData_pdMrVec_0_mrTagVec_dataVec_0_D_IN = - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[198:1] ; - assign pdMetaData_pdMrVec_0_mrTagVec_dataVec_0_EN = - MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_write_1__SEL_1 ; - - // register pdMetaData_pdMrVec_0_mrTagVec_dataVec_1 - assign pdMetaData_pdMrVec_0_mrTagVec_dataVec_1_D_IN = - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[198:1] ; - assign pdMetaData_pdMrVec_0_mrTagVec_dataVec_1_EN = - MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_write_1__SEL_1 ; - - // register pdMetaData_pdMrVec_0_mrTagVec_fullReg - assign pdMetaData_pdMrVec_0_mrTagVec_fullReg_D_IN = - MUX_pdMetaData_pdMrVec_0_mrTagVec_emptyReg_write_1__SEL_1 && - MUX_pdMetaData_pdMrVec_0_mrTagVec_fullReg_write_1__VAL_1 ; - assign pdMetaData_pdMrVec_0_mrTagVec_fullReg_EN = - MUX_pdMetaData_pdMrVec_0_mrTagVec_emptyReg_write_1__SEL_1 || - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - - // register pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg - assign pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg_D_IN = - { !pdMetaData_pdMrVec_0_mrTagVec_tagVec_0 || - !pdMetaData_pdMrVec_0_mrTagVec_tagVec_1, - pdMetaData_pdMrVec_0_mrTagVec_tagVec_0 } ; - assign pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg_EN = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq && - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[199] ; - - // register pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg - assign pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg_D_IN = - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[199] ? - !pdMetaData_pdMrVec_0_mrTagVec_fullReg : - SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_ETC___d56 ; - assign pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg_EN = - CAN_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq ; - - // register pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg - assign pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg_D_IN = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq ? - MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg_write_1__VAL_1 : - 2'd0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg_EN = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq || - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp || - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp || - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - - // register pdMetaData_pdMrVec_0_mrTagVec_tagVec_0 - assign pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_D_IN = - !MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_write_1__SEL_2 && - !pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - assign pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_EN = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[0] == 1'd0 && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg || - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp && - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0] == 1'd0 || - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - - // register pdMetaData_pdMrVec_0_mrTagVec_tagVec_1 - assign pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_D_IN = - !MUX_pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_write_1__SEL_2 && - !pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - assign pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_EN = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[0] == 1'd1 && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg || - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp && - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0] == 1'd1 || - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - - // register pdMetaData_pdTagVec_clearReg - assign pdMetaData_pdTagVec_clearReg_D_IN = 1'b0 ; - assign pdMetaData_pdTagVec_clearReg_EN = 1'b1 ; - - // register pdMetaData_pdTagVec_dataVec_0 - assign pdMetaData_pdTagVec_dataVec_0_D_IN = - pdMetaData_pdTagVec_reqQ_D_OUT[31:0] ; - assign pdMetaData_pdTagVec_dataVec_0_EN = - MUX_pdMetaData_pdTagVec_tagVec_0_write_1__SEL_1 ; - - // register pdMetaData_pdTagVec_fullReg - assign pdMetaData_pdTagVec_fullReg_D_IN = - MUX_pdMetaData_pdTagVec_emptyReg_write_1__SEL_1 && - pdMetaData_pdTagVec_reqQ_D_OUT[32] ; - assign pdMetaData_pdTagVec_fullReg_EN = - MUX_pdMetaData_pdTagVec_emptyReg_write_1__SEL_1 || - pdMetaData_pdTagVec_clearReg ; - - // register pdMetaData_pdTagVec_maybeInsertIdxReg - assign pdMetaData_pdTagVec_maybeInsertIdxReg_D_IN = - !pdMetaData_pdTagVec_tagVec_0 ; - assign pdMetaData_pdTagVec_maybeInsertIdxReg_EN = - WILL_FIRE_RL_pdMetaData_pdTagVec_recvReq && - pdMetaData_pdTagVec_reqQ_D_OUT[32] ; - - // register pdMetaData_pdTagVec_respSuccessReg - assign pdMetaData_pdTagVec_respSuccessReg_D_IN = - pdMetaData_pdTagVec_reqQ_D_OUT[32] ? - !pdMetaData_pdTagVec_fullReg : - pdMetaData_pdTagVec_tagVec_0 ; - assign pdMetaData_pdTagVec_respSuccessReg_EN = - CAN_FIRE_RL_pdMetaData_pdTagVec_recvReq ; - - // register pdMetaData_pdTagVec_tagVecStateReg - assign pdMetaData_pdTagVec_tagVecStateReg_D_IN = - WILL_FIRE_RL_pdMetaData_pdTagVec_recvReq ? - MUX_pdMetaData_pdTagVec_tagVecStateReg_write_1__VAL_1 : - 2'd0 ; - assign pdMetaData_pdTagVec_tagVecStateReg_EN = - WILL_FIRE_RL_pdMetaData_pdTagVec_recvReq || - WILL_FIRE_RL_pdMetaData_pdTagVec_genRemoveResp || - WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp || - pdMetaData_pdTagVec_clearReg ; - - // register pdMetaData_pdTagVec_tagVec_0 - assign pdMetaData_pdTagVec_tagVec_0_D_IN = - MUX_pdMetaData_pdTagVec_tagVec_0_write_1__SEL_1 ; - assign pdMetaData_pdTagVec_tagVec_0_EN = - WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp && - pdMetaData_pdTagVec_respSuccessReg || - WILL_FIRE_RL_pdMetaData_pdTagVec_genRemoveResp || - pdMetaData_pdTagVec_clearReg ; - - // register pktMetaDataAndPayloadPipeOutVec_bthPadCntReg - assign pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_D_IN = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_OUT[150:149] ; - assign pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_EN = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] ; - - // register pktMetaDataAndPayloadPipeOutVec_isValidPktReg - assign pktMetaDataAndPayloadPipeOutVec_isValidPktReg_D_IN = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] ; - assign pktMetaDataAndPayloadPipeOutVec_isValidPktReg_EN = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] ; - - // register pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_D_IN = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_port2__read ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN = 1'b1 ; - - // register pktMetaDataAndPayloadPipeOutVec_pktBufStateReg - assign pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_D_IN = - !MUX_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_write_1__SEL_1 ; - assign pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_EN = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag && - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[0] || - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0]) && - !pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[0] ; - - // register pktMetaDataAndPayloadPipeOutVec_pktFragNumReg - assign pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_D_IN = - pktFragNum__h36981 ; - assign pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_EN = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - - // register pktMetaDataAndPayloadPipeOutVec_pktLenReg - assign pktMetaDataAndPayloadPipeOutVec_pktLenReg_D_IN = pktLen__h36984 ; - assign pktMetaDataAndPayloadPipeOutVec_pktLenReg_EN = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - - // register pktMetaDataAndPayloadPipeOutVec_pktValidReg - assign pktMetaDataAndPayloadPipeOutVec_pktValidReg_D_IN = - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2151 ; - assign pktMetaDataAndPayloadPipeOutVec_pktValidReg_EN = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_D_IN = - !MUX_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_write_1__SEL_1 ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_EN = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] || - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData ; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg_D_IN = - { 503'd0, headerInvalidFragNum__h26376, 8'd0 } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg_EN = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData ; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg_D_IN = - { headerInvalidFragNum__h26376, 5'd0 } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg_EN = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData ; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg_D_IN = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv[16:0] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg_EN = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData ; - - // register pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg_D_IN = - { x1_avValue_headerData__h29692, - x1_avValue_headerByteEn__h29693, - IF_headerAndMetaDataAndPayloadPipeOut_headerAn_ETC___d1422 } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg_EN = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate ; - - // register qpMetaData_qpTagVec_clearReg - assign qpMetaData_qpTagVec_clearReg_D_IN = 1'b0 ; - assign qpMetaData_qpTagVec_clearReg_EN = 1'b1 ; - - // register qpMetaData_qpTagVec_dataVec_0 - assign qpMetaData_qpTagVec_dataVec_0_D_IN = - qpMetaData_qpTagVec_reqQ_D_OUT[31:0] ; - assign qpMetaData_qpTagVec_dataVec_0_EN = - MUX_qpMetaData_qpTagVec_tagVec_0_write_1__SEL_1 ; - - // register qpMetaData_qpTagVec_fullReg - assign qpMetaData_qpTagVec_fullReg_D_IN = - MUX_qpMetaData_qpTagVec_emptyReg_write_1__SEL_1 && - qpMetaData_qpTagVec_reqQ_D_OUT[32] ; - assign qpMetaData_qpTagVec_fullReg_EN = - MUX_qpMetaData_qpTagVec_emptyReg_write_1__SEL_1 || - qpMetaData_qpTagVec_clearReg ; - - // register qpMetaData_qpTagVec_maybeInsertIdxReg - assign qpMetaData_qpTagVec_maybeInsertIdxReg_D_IN = - !qpMetaData_qpTagVec_tagVec_0 ; - assign qpMetaData_qpTagVec_maybeInsertIdxReg_EN = - WILL_FIRE_RL_qpMetaData_qpTagVec_recvReq && - qpMetaData_qpTagVec_reqQ_D_OUT[32] ; - - // register qpMetaData_qpTagVec_respSuccessReg - assign qpMetaData_qpTagVec_respSuccessReg_D_IN = - qpMetaData_qpTagVec_reqQ_D_OUT[32] ? - !qpMetaData_qpTagVec_fullReg : - qpMetaData_qpTagVec_tagVec_0 ; - assign qpMetaData_qpTagVec_respSuccessReg_EN = - CAN_FIRE_RL_qpMetaData_qpTagVec_recvReq ; - - // register qpMetaData_qpTagVec_tagVecStateReg - assign qpMetaData_qpTagVec_tagVecStateReg_D_IN = - WILL_FIRE_RL_qpMetaData_qpTagVec_recvReq ? - MUX_qpMetaData_qpTagVec_tagVecStateReg_write_1__VAL_1 : - 2'd0 ; - assign qpMetaData_qpTagVec_tagVecStateReg_EN = - WILL_FIRE_RL_qpMetaData_qpTagVec_recvReq || - WILL_FIRE_RL_qpMetaData_qpTagVec_genRemoveResp || - WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp || - qpMetaData_qpTagVec_clearReg ; - - // register qpMetaData_qpTagVec_tagVec_0 - assign qpMetaData_qpTagVec_tagVec_0_D_IN = - MUX_qpMetaData_qpTagVec_tagVec_0_write_1__SEL_1 ; - assign qpMetaData_qpTagVec_tagVec_0_EN = - WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp && - qpMetaData_qpTagVec_respSuccessReg || - WILL_FIRE_RL_qpMetaData_qpTagVec_genRemoveResp || - qpMetaData_qpTagVec_clearReg ; - - // submodule arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0 - assign arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_D_IN = - qpMetaData_qpVec_0_dmaReadClt4SQ_request_get ; - assign arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_ENQ = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_extractReq ; - assign arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_DEQ = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_binaryArbitrate ; - assign arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_CLR = - 1'b0 ; - - // submodule arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ - assign arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_IN = - arbitratedDmaReadClt_arbitratedClient_inputReqWithIdxVec_0_D_OUT ; - assign arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_ENQ = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_binaryArbitrate ; - assign arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_DEQ = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq ; - assign arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_CLR = - 1'b0 ; - - // submodule arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ - assign arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_ENQ = - WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq && - arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg ; - assign arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_DEQ = - WILL_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_dispatchResponse && - arbitratedDmaReadClt_arbitratedClient_respQ_D_OUT[0] ; - assign arbitratedDmaReadClt_arbitratedClient_preGrantIdxQ_CLR = 1'b0 ; - - // submodule arbitratedDmaReadClt_arbitratedClient_reqQ - assign arbitratedDmaReadClt_arbitratedClient_reqQ_D_IN = - arbitratedDmaReadClt_arbitratedClient_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_OUT ; - assign arbitratedDmaReadClt_arbitratedClient_reqQ_ENQ = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_issueArbitratedReq ; - assign arbitratedDmaReadClt_arbitratedClient_reqQ_DEQ = - EN_dmaReadClt_request_get ; - assign arbitratedDmaReadClt_arbitratedClient_reqQ_CLR = 1'b0 ; - - // submodule arbitratedDmaReadClt_arbitratedClient_respQ - assign arbitratedDmaReadClt_arbitratedClient_respQ_D_IN = - dmaReadClt_response_put ; - assign arbitratedDmaReadClt_arbitratedClient_respQ_ENQ = - EN_dmaReadClt_response_put ; - assign arbitratedDmaReadClt_arbitratedClient_respQ_DEQ = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_dispatchResponse ; - assign arbitratedDmaReadClt_arbitratedClient_respQ_CLR = 1'b0 ; - - // submodule dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ - assign dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_IN = - qpMetaData_qpVec_0_rdmaReqPipeOut_first ; - assign dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_ENQ = - CAN_FIRE_RL_dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate ; - assign dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_DEQ = - EN_rdmaDataStreamPipeOut_deq ; - assign dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_CLR = - 1'b0 ; - - // submodule headerAndMetaDataAndPayloadPipeOut_dataInQ - assign headerAndMetaDataAndPayloadPipeOut_dataInQ_D_IN = - inputDataStreamQ_D_OUT ; - assign headerAndMetaDataAndPayloadPipeOut_dataInQ_ENQ = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader ; - assign headerAndMetaDataAndPayloadPipeOut_dataInQ_DEQ = - (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader) && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData ; - assign headerAndMetaDataAndPayloadPipeOut_dataInQ_CLR = 1'b0 ; - - // submodule headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_IN = - { headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[289:34], - x1_avValue_snd_byteEn__h21193, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[1], - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg } ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_ENQ = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_CLR = - 1'b0 ; - - // submodule headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ - always@(MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__SEL_1 or - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData or - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__VAL_2 or - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag or - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__SEL_1: - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_D_IN = - 290'd3; - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData: - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_D_IN = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__VAL_2; - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag: - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_D_IN = - MUX_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_enq_1__VAL_3; - default: headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_D_IN = - 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_ENQ = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputHeader && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] && - (bits__h21377 == 2'd0 || - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg) || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_outputData || - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_extraLastFrag ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_rl_into_buffer ; - assign headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_CLR = - 1'b0 ; - - // submodule headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_IN = - { headerLen__h22004, - headerFragNum__h22721, - lastFragValidByteNum__h22722, - inputDataStreamQ_D_OUT[286:282] == 5'd0 || - inputDataStreamQ_D_OUT[286:282] == 5'd1 || - inputDataStreamQ_D_OUT[286:282] == 5'd2 || - inputDataStreamQ_D_OUT[286:282] == 5'd4 || - inputDataStreamQ_D_OUT[286:282] == 5'd3 || - inputDataStreamQ_D_OUT[286:282] == 5'd5 || - inputDataStreamQ_D_OUT[286:282] == 5'd22 || - inputDataStreamQ_D_OUT[286:282] == 5'd23 || - inputDataStreamQ_D_OUT[286:282] == 5'd6 || - inputDataStreamQ_D_OUT[286:282] == 5'd7 || - inputDataStreamQ_D_OUT[286:282] == 5'd8 || - inputDataStreamQ_D_OUT[286:282] == 5'd10 || - inputDataStreamQ_D_OUT[286:282] == 5'd9 || - inputDataStreamQ_D_OUT[286:282] == 5'd11 || - inputDataStreamQ_D_OUT[286:282] == 5'd13 || - inputDataStreamQ_D_OUT[286:282] == 5'd14 || - inputDataStreamQ_D_OUT[286:282] == 5'd15 || - inputDataStreamQ_D_OUT[286:282] == 5'd16, - 1'd0 } ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_ENQ = - WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_DEQ = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_rl_deq ; - assign headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_CLR = 1'b0 ; - - // submodule inputDataStreamQ - assign inputDataStreamQ_D_IN = rdmaDataStreamInput_put ; - assign inputDataStreamQ_ENQ = EN_rdmaDataStreamInput_put ; - assign inputDataStreamQ_DEQ = - CAN_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader ; - assign inputDataStreamQ_CLR = 1'b0 ; - - // submodule inputWorkReqQ - assign inputWorkReqQ_D_IN = workReqInput_put ; - assign inputWorkReqQ_ENQ = EN_workReqInput_put ; - assign inputWorkReqQ_DEQ = CAN_FIRE_RL_workReqPipeOutVec_dispatchWorkReq ; - assign inputWorkReqQ_CLR = 1'b0 ; - - // submodule metaDataSrv_metaDataReqQ - assign metaDataSrv_metaDataReqQ_D_IN = srvPortMetaData_request_put ; - assign metaDataSrv_metaDataReqQ_ENQ = EN_srvPortMetaData_request_put ; - assign metaDataSrv_metaDataReqQ_DEQ = - CAN_FIRE_RL_metaDataSrv_recvMetaDataReq ; - assign metaDataSrv_metaDataReqQ_CLR = 1'b0 ; - - // submodule metaDataSrv_metaDataRespQ - always@(WILL_FIRE_RL_metaDataSrv_genResp4MR or - MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_1 or - WILL_FIRE_RL_metaDataSrv_genResp4PD or - MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_2 or - WILL_FIRE_RL_metaDataSrv_genResp4QP or - MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_3) - begin - case (1'b1) // synopsys parallel_case - WILL_FIRE_RL_metaDataSrv_genResp4MR: - metaDataSrv_metaDataRespQ_D_IN = - MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_1; - WILL_FIRE_RL_metaDataSrv_genResp4PD: - metaDataSrv_metaDataRespQ_D_IN = - MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_2; - WILL_FIRE_RL_metaDataSrv_genResp4QP: - metaDataSrv_metaDataRespQ_D_IN = - MUX_metaDataSrv_metaDataRespQ_enq_1__VAL_3; - default: metaDataSrv_metaDataRespQ_D_IN = - 276'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ; - endcase - end - assign metaDataSrv_metaDataRespQ_ENQ = - WILL_FIRE_RL_metaDataSrv_genResp4MR || - WILL_FIRE_RL_metaDataSrv_genResp4PD || - WILL_FIRE_RL_metaDataSrv_genResp4QP ; - assign metaDataSrv_metaDataRespQ_DEQ = EN_srvPortMetaData_response_get ; - assign metaDataSrv_metaDataRespQ_CLR = 1'b0 ; - - // submodule pdMetaData_pdMrVec_0_mrTagVec_itemCnt - assign pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_A = 2'd1 ; - assign pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_B = 2'd3 ; - assign pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_C = 2'h0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_itemCnt_DATA_F = 2'd0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_itemCnt_ADDA = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq && - pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[199] && - !pdMetaData_pdMrVec_0_mrTagVec_fullReg ; - assign pdMetaData_pdMrVec_0_mrTagVec_itemCnt_ADDB = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_recvReq && - !pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[199] && - SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_ETC___d56 ; - assign pdMetaData_pdMrVec_0_mrTagVec_itemCnt_SETC = 1'b0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_itemCnt_SETF = - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - - // submodule pdMetaData_pdMrVec_0_mrTagVec_reqQ - assign pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_IN = - { metaDataSrv_mrReqReg[263:65], mrReqKey__h12289[31] } ; - assign pdMetaData_pdMrVec_0_mrTagVec_reqQ_ENQ = - WILL_FIRE_RL_metaDataSrv_issueReq4MR && - pdMetaData_pdTagVec_tagVec_0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_reqQ_DEQ = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp || - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp ; - assign pdMetaData_pdMrVec_0_mrTagVec_reqQ_CLR = - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - - // submodule pdMetaData_pdMrVec_0_mrTagVec_respQ - assign pdMetaData_pdMrVec_0_mrTagVec_respQ_D_IN = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp ? - MUX_pdMetaData_pdMrVec_0_mrTagVec_respQ_enq_1__VAL_1 : - MUX_pdMetaData_pdMrVec_0_mrTagVec_respQ_enq_1__VAL_2 ; - assign pdMetaData_pdMrVec_0_mrTagVec_respQ_ENQ = - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp || - WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genRemoveResp ; - assign pdMetaData_pdMrVec_0_mrTagVec_respQ_DEQ = - WILL_FIRE_RL_metaDataSrv_genResp4MR && - pdMetaData_pdTagVec_tagVec_0 ; - assign pdMetaData_pdMrVec_0_mrTagVec_respQ_CLR = - pdMetaData_pdMrVec_0_mrTagVec_clearReg ; - - // submodule pdMetaData_pdTagVec_reqQ - assign pdMetaData_pdTagVec_reqQ_D_IN = metaDataSrv_pdReqReg[64:32] ; - assign pdMetaData_pdTagVec_reqQ_ENQ = CAN_FIRE_RL_metaDataSrv_issueReq4PD ; - assign pdMetaData_pdTagVec_reqQ_DEQ = - WILL_FIRE_RL_pdMetaData_pdTagVec_genRemoveResp || - WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp ; - assign pdMetaData_pdTagVec_reqQ_CLR = pdMetaData_pdTagVec_clearReg ; - - // submodule pdMetaData_pdTagVec_respQ - assign pdMetaData_pdTagVec_respQ_D_IN = - WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp ? - MUX_pdMetaData_pdTagVec_respQ_enq_1__VAL_1 : - MUX_pdMetaData_pdTagVec_respQ_enq_1__VAL_2 ; - assign pdMetaData_pdTagVec_respQ_ENQ = - WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp || - WILL_FIRE_RL_pdMetaData_pdTagVec_genRemoveResp ; - assign pdMetaData_pdTagVec_respQ_DEQ = CAN_FIRE_RL_metaDataSrv_genResp4PD ; - assign pdMetaData_pdTagVec_respQ_CLR = pdMetaData_pdTagVec_clearReg ; - - // submodule pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0 - assign pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[160:152], - 1'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[150:149], - 4'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[144:129], - 8'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[120:96], - 7'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[88:65] } ; - assign pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] ; - assign pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_DEQ = 1'b0 ; - assign pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadFilterQ - assign pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_IN = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT ; - assign pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ENQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt ; - assign pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ - assign pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_IN = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT ; - assign pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt && - (pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] ? - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] : - pktMetaDataAndPayloadPipeOutVec_isValidPktReg) ; - assign pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadOutputQ - assign pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_IN = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT ; - assign pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1]) ; - assign pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload ; - assign pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT, - value__h36219, - x__h36323, - bits__h36334 != 2'd0, - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[33:32] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[31:30] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[29:28] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[27:26] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[25:24] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[23:22] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[21:20] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[19:18] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[17:16] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[15:14] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[13:12] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[11:10] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[9:8] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[7:6] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[5:4] == - 2'd3 && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[3:2] == - 2'd3 } ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_ENQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_IN = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_ENQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[303:14], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[3] } ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_ENQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ - assign pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_IN = - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0] || - !pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1]) ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadRecvQ - assign pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_IN = - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[289:0] ; - assign pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_ENQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag ; - assign pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader ; - assign pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_payloadValidationQ - assign pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_IN = - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT ; - assign pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_ENQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation ; - assign pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP ; - assign pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[782:181], - 1'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[179:178], - 4'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[173:158], - 8'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[149:125], - 7'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[117:94], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[92:37], - qpMetaData_qpVec_0_statusSQ_comm_getPMTU, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderVali_ETC___d1886 && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] != - 3'd3 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[36:5] == - qpMetaData_qpVec_0_statusSQ_comm_getQKEY), - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4:0] } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_DEQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[753:152], - 1'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[150:149], - 4'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[144:129], - 8'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[120:96], - 7'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[88:0] } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidHeaderPkt && - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_DEQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[21:9], - pktMetaData_pktFragNum__h38817, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[654:30], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[5] && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[4] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[3] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[0]), - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[5] || - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[4] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[1]) && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[3] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[0]), - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[0] } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_DEQ = - CAN_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_IN = - { rdmaHeader_headerData__h26487, - rdmaHeader_headerByteEn__h26488, - IF_headerAndMetaDataAndPayloadPipeOut_headerAn_ETC___d1422 } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_ENQ = - MUX_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_write_1__SEL_1 ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_DEQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag && - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_CLR = - 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_OUT[753:152], - 1'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_OUT[150:149], - 4'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_OUT[144:129], - 8'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_OUT[120:96], - 7'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_OUT[88:0] } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen && - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_DEQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[14] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT, - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[18] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[17:16] == - 2'd0 && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[15] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[14:13] == - 2'd0 && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[12] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[11:10] == - 2'd0 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[9:8] == - 2'd0 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[7:6] == - 2'd0, - bits__h38056 == 13'd0, - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q7 } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_DEQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[160:153], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[150:149], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[88:65], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[32:9], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[753:161], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[64:33], - pktFragNum__h36981, - pktLen__h36984, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[8:6], - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2151, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[1:0] } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcPktLen && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[14] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_DEQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckPktLen && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_CLR = - 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[691:90], - 1'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[88:87], - 4'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[82:67], - 8'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[58:34], - 7'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[26:3] } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_DEQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation && - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[592:584], - 1'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[582:581], - 4'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[576:561], - 8'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[552:528], - 7'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[520:497], - 1'd1, - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q9 || - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q11, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[0] && - bits__h30478 == 2'd0 } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag && - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_DEQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_IN = - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[688:87], - 1'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[85:84], - 4'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[79:64], - 8'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[55:31], - 7'd0, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[23:0], - qpMetaData_qpTagVec_tagVec_0, - qpMetaData_qpTagVec_dataVec_0, - dqpn__h31384, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[592:561], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[95:88] == - 8'd129, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd13 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd14 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd15 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd16 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd17 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd18, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd2 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd3 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd22 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd8 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd9 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd15, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd0 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd6 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd13 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd1 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd7 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd14, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd2 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd3 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd22 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd8 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd9 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd15 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd4 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd5 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd23 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd10 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd11 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd12 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd19 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd20 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd16 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd17 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] == - 5'd18 } ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_prepareValidation && - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_DEQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkMetaDataQP && - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0 - assign pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_D_IN = - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_OUT[290:1] ; - assign pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputPayload && - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_D_OUT[0] ; - assign pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_DEQ = - CAN_FIRE_RL_mkConnectionGetPut_2 ; - assign pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_CLR = 1'b0 ; - - // submodule pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0 - assign pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_D_IN = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_OUT[649:1] ; - assign pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_ENQ = - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_outputHeaderMetaData && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_D_OUT[0] ; - assign pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_DEQ = - CAN_FIRE_RL_mkConnectionGetPut_1 ; - assign pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_CLR = 1'b0 ; - - // submodule qpMetaData_qpReqQ4Cntrl - assign qpMetaData_qpReqQ4Cntrl_D_IN = metaDataSrv_qpReqReg ; - assign qpMetaData_qpReqQ4Cntrl_ENQ = - WILL_FIRE_RL_metaDataSrv_issueReq4QP && - pdMetaData_pdTagVec_tagVec_0 ; - assign qpMetaData_qpReqQ4Cntrl_DEQ = CAN_FIRE_RL_qpMetaData_handleReqQP ; - assign qpMetaData_qpReqQ4Cntrl_CLR = 1'b0 ; - - // submodule qpMetaData_qpReqQ4Resp - assign qpMetaData_qpReqQ4Resp_D_IN = - { qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] != 2'd0 && - qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] != 2'd1 || - qpMetaData_qpTagVec_respQ_D_OUT[32], - qpMetaData_qpReqQ4Cntrl_D_OUT[300:299], - IF_qpMetaData_qpReqQ4Cntrl_first__66_BITS_300__ETC___d207 } ; - assign qpMetaData_qpReqQ4Resp_ENQ = CAN_FIRE_RL_qpMetaData_handleReqQP ; - assign qpMetaData_qpReqQ4Resp_DEQ = - WILL_FIRE_RL_metaDataSrv_genResp4QP && - pdMetaData_pdTagVec_tagVec_0 ; - assign qpMetaData_qpReqQ4Resp_CLR = 1'b0 ; - - // submodule qpMetaData_qpTagVec_reqQ - assign qpMetaData_qpTagVec_reqQ_D_IN = - { metaDataSrv_qpReqReg[300:299] == 2'd0, - metaDataSrv_qpReqReg[298:267] } ; - assign qpMetaData_qpTagVec_reqQ_ENQ = - WILL_FIRE_RL_metaDataSrv_issueReq4QP && - pdMetaData_pdTagVec_tagVec_0 && - (metaDataSrv_qpReqReg[300:299] == 2'd0 || - metaDataSrv_qpReqReg[300:299] == 2'd1) ; - assign qpMetaData_qpTagVec_reqQ_DEQ = - WILL_FIRE_RL_qpMetaData_qpTagVec_genRemoveResp || - WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp ; - assign qpMetaData_qpTagVec_reqQ_CLR = qpMetaData_qpTagVec_clearReg ; - - // submodule qpMetaData_qpTagVec_respQ - assign qpMetaData_qpTagVec_respQ_D_IN = - WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp ? - MUX_qpMetaData_qpTagVec_respQ_enq_1__VAL_1 : - MUX_qpMetaData_qpTagVec_respQ_enq_1__VAL_2 ; - assign qpMetaData_qpTagVec_respQ_ENQ = - WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp || - WILL_FIRE_RL_qpMetaData_qpTagVec_genRemoveResp ; - assign qpMetaData_qpTagVec_respQ_DEQ = - WILL_FIRE_RL_qpMetaData_handleReqQP && - (qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] == 2'd0 || - qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] == 2'd1) ; - assign qpMetaData_qpTagVec_respQ_CLR = qpMetaData_qpTagVec_clearReg ; - - // submodule qpMetaData_qpVec_0 - assign qpMetaData_qpVec_0_dmaReadClt4SQ_response_put = - arbitratedDmaReadClt_arbitratedClient_respQ_D_OUT ; - assign qpMetaData_qpVec_0_respPktPipeIn_payload_put = - pktMetaDataAndPayloadPipeOutVec_respPayloadOutVec_0_D_OUT ; - assign qpMetaData_qpVec_0_respPktPipeIn_pktMetaData_put = - pktMetaDataAndPayloadPipeOutVec_respPktMetaDataOutVec_0_D_OUT ; - always@(qpMetaData_qpReqQ4Cntrl_D_OUT or qpMetaData_qpTagVec_respQ_D_OUT) - begin - case (qpMetaData_qpReqQ4Cntrl_D_OUT[300:299]) - 2'd0, 2'd1: - qpMetaData_qpVec_0_srvPortQP_request_put = - { qpMetaData_qpReqQ4Cntrl_D_OUT[300:299], - qpMetaData_qpTagVec_respQ_D_OUT[31:0], - qpMetaData_qpTagVec_respQ_D_OUT[23:0], - qpMetaData_qpReqQ4Cntrl_D_OUT[242:0] }; - default: qpMetaData_qpVec_0_srvPortQP_request_put = - qpMetaData_qpReqQ4Cntrl_D_OUT; - endcase - end - assign qpMetaData_qpVec_0_workReqIn_put = - workReqPipeOutVec_workReqOutVec_0_D_OUT ; - assign qpMetaData_qpVec_0_EN_srvPortQP_request_put = - WILL_FIRE_RL_qpMetaData_handleReqQP && - ((qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] == 2'd0 || - qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] == 2'd1) && - qpMetaData_qpTagVec_respQ_D_OUT[32] || - qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] == 2'd2 || - qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] == 2'd3) ; - assign qpMetaData_qpVec_0_EN_srvPortQP_response_get = - WILL_FIRE_RL_metaDataSrv_genResp4QP && - pdMetaData_pdTagVec_tagVec_0 && - qpMetaData_qpReqQ4Resp_D_OUT[301] ; - assign qpMetaData_qpVec_0_EN_workReqIn_put = - CAN_FIRE_RL_mkConnectionGetPut ; - assign qpMetaData_qpVec_0_EN_dmaReadClt4SQ_request_get = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_extractReq ; - assign qpMetaData_qpVec_0_EN_dmaReadClt4SQ_response_put = - CAN_FIRE_RL_arbitratedDmaReadClt_arbitratedClient_dispatchResponse ; - assign qpMetaData_qpVec_0_EN_respPktPipeIn_pktMetaData_put = - CAN_FIRE_RL_mkConnectionGetPut_1 ; - assign qpMetaData_qpVec_0_EN_respPktPipeIn_payload_put = - CAN_FIRE_RL_mkConnectionGetPut_2 ; - assign qpMetaData_qpVec_0_EN_rdmaReqPipeOut_deq = - CAN_FIRE_RL_dataStreamPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate ; - assign qpMetaData_qpVec_0_EN_workCompPipeOutSQ_deq = - CAN_FIRE_RL_sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate ; - - // submodule sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ - assign sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_D_IN = - qpMetaData_qpVec_0_workCompPipeOutSQ_first ; - assign sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_ENQ = - CAN_FIRE_RL_sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_binaryArbitrate ; - assign sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_DEQ = - EN_workCompPipeOutSQ_deq ; - assign sendWorkCompPipeOut_leafArbiterVec_binaryArbiter_0_pipeOutQ_CLR = - 1'b0 ; - - // submodule workReqPipeOutVec_workReqOutVec_0 - assign workReqPipeOutVec_workReqOutVec_0_D_IN = inputWorkReqQ_D_OUT ; - assign workReqPipeOutVec_workReqOutVec_0_ENQ = - CAN_FIRE_RL_workReqPipeOutVec_dispatchWorkReq ; - assign workReqPipeOutVec_workReqOutVec_0_DEQ = - CAN_FIRE_RL_mkConnectionGetPut ; - assign workReqPipeOutVec_workReqOutVec_0_CLR = 1'b0 ; - - // remaining internal signals - assign IF_headerAndMetaDataAndPayloadPipeOut_headerAn_ETC___d1422 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[1] ? - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg[16:10], - 2'd1, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg[7:0] } : - { pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg[16:10], - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipe_ETC___d1419, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg[7:0] } ; - assign IF_headerAndMetaDataAndPayloadPipeOut_headerAn_ETC___d451 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] ? - bits__h21377 != 2'd0 && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_payloadDataStreamOutQ_FULL_N : - headerAndMetaDataAndPayloadPipeOut_dataInQ_EMPTY_N ; - assign IF_pdMetaData_pdTagVec_tagVec_0_4_THEN_IF_qpMe_ETC___d338 = - pdMetaData_pdTagVec_tagVec_0 ? - CASE_qpMetaData_qpReqQ4RespD_OUT_BITS_300_TO__ETC__q4 : - { metaDataSrv_qpReqReg[266:243], - metaDataSrv_qpReqReg[298:267], - metaDataSrv_qpReqReg[216:0] } ; - assign IF_pdMetaData_pdTagVec_tagVec_0_4_THEN_pdMetaD_ETC___d279 = - pdMetaData_pdTagVec_tagVec_0 ? - { pdMetaData_pdMrVec_0_mrTagVec_respQ_D_OUT[197:0], - lkey__h13067, - rkey__h13068 } : - { metaDataSrv_mrReqReg[262:65], metaDataSrv_mrReqReg[63:0] } ; - assign IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2265 = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] ? - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderOutputQ_FULL_N && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2] || - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_FULL_N) : - pktMetaDataAndPayloadPipeOutVec_payloadOutputQ_FULL_N ; - assign IF_pktMetaDataAndPayloadPipeOutVec_payloadRecv_ETC___d1675 = - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] ? - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecv_ETC___d1674 : - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_FULL_N ; - assign IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1849 = - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4]) ? - !qpMetaData_qpVec_0_statusSQ_comm_isRTS : - !qpMetaData_qpVec_0_statusSQ_comm_isNonErr ; - assign IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1855 = - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842 || - !qpMetaData_qpVec_0_statusSQ_comm_isERR && - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1849 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] != - 3'd3 || - qpMetaData_qpVec_0_RDY_statusSQ_comm_getQKEY ; - assign IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1884 = - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4]) ? - qpMetaData_qpVec_0_statusSQ_comm_isRTS : - qpMetaData_qpVec_0_statusSQ_comm_isNonErr ; - assign IF_qpMetaData_qpReqQ4Cntrl_first__66_BITS_300__ETC___d207 = - { CASE_qpMetaData_qpReqQ4CntrlD_OUT_BITS_300_TO_ETC__q5, - CASE_qpMetaData_qpReqQ4CntrlD_OUT_BITS_300_TO_ETC__q6, - qpMetaData_qpReqQ4Cntrl_D_OUT[242:0] } ; - assign IF_qpMetaData_qpReqQ4Resp_first__91_BIT_301_04_ETC___d333 = - qpMetaData_qpReqQ4Resp_D_OUT[301] ? - qpMetaData_qpVec_0_srvPortQP_response_get[272:0] : - { qpMetaData_qpReqQ4Resp_D_OUT[266:243], - qpMetaData_qpReqQ4Resp_D_OUT[298:267], - qpMetaData_qpReqQ4Resp_D_OUT[216:0] } ; - assign NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1518 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[33:32] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[31:30] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[29:28] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[27:26] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[25:24] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[23:22] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[21:20] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[19:18] != - 2'd3 ; - assign NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1549 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[17:16] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[15:14] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[13:12] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[11:10] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[9:8] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[7:6] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[5:4] != - 2'd3 || - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[3:2] != - 2'd3 ; - assign NOT_pdMetaData_pdTagVec_tagVec_0_4_1_OR_qpMeta_ETC___d253 = - !pdMetaData_pdTagVec_tagVec_0 || - qpMetaData_qpReqQ4Cntrl_FULL_N && - (metaDataSrv_qpReqReg[300:299] != 2'd0 && - metaDataSrv_qpReqReg[300:299] != 2'd1 || - qpMetaData_qpTagVec_reqQ_FULL_N) ; - assign SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_dataVec__ETC___d123 = - { CASE_pdMetaData_pdMrVec_0_mrTagVec_reqQD_OUT__ETC__q2, - x__h6223, - x__h6228, - x__h6233 } ; - assign SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_dataVec__ETC___d124 = - { CASE_pdMetaData_pdMrVec_0_mrTagVec_reqQD_OUT__ETC__q3, - x__h6207, - SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_dataVec__ETC___d123 } ; - assign _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428 = - (32'd1 << fragValidByteNum__h26706) - 32'd1 ; - assign _1_SL_headerAndMetaDataAndPayloadPipeOut_header_ETC___d379 = - (32'd1 << - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[7:2]) - - 32'd1 ; - assign _theResult___headerData__h26503 = - { headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[1] ? - 256'd0 : - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg[336:81], - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[289:34] } ; - assign _theResult___headerMetaData_headerFragNum__h26603 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[1] ? - 2'd1 : - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipe_ETC___d1419 ; - assign _theResult___headerMetaData_headerLen__h26602 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[1] ? - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg[16:10] : - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg[16:10] ; - assign bits__h21377 = - { headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg[31], - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg[0] } ; - assign bits__h30478 = - { pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[33], - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[2] } ; - assign bits__h36334 = - { pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[33], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[2] } ; - assign bits__h38056 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[18:6] & - y__h38112 ; - assign dqpn__h31384 = - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[95:93] == - 3'd5 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] != - 5'd13 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] != - 5'd14 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] != - 5'd15 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] != - 5'd16 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] != - 5'd17 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[92:88] != - 5'd18 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[95:88] != - 8'd129) ? - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[584:561] : - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_D_OUT[55:32] ; - assign fragLenExtWithOutPad__h36979 = - { 7'd0, - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[7:2] } ; - assign fragValidByteNum__h26706 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[1] ? - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg[7:2] : - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg[7:2] ; - assign headerFragNum__h22721 = - headerLen__h22004[6:5] + { 1'd0, x__h22733 } ; - assign headerInvalidFragNum__h26376 = - 2'd2 - - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv[9:8] ; - assign headerLastFragByteEn__h26468 = - { _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[0], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[1], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[2], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[3], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[4], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[5], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[6], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[7], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[8], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[9], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[10], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[11], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[12], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[13], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[14], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[15], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[16], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[17], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[18], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[19], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[20], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[21], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[22], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[23], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[24], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[25], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[26], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[27], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[28], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[29], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[30], - _1_SL_IF_headerAndMetaDataAndPayloadPipeOut_hea_ETC___d1428[31] } ; - assign headerLastFragInvalidByteNum__h17427 = - 6'd32 - - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[7:2] ; - assign headerMetaData_headerFragNum__h21034 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg[9:8] - - 2'd1 ; - assign lastFragValidByteNum__h22722 = - (headerLen__h22004[4:3] == 2'd0 && !headerLen__h22004[2] && - headerLen__h22004[1:0] == 2'd0 && - headerLen__h22004[6:5] != 2'd0) ? - 6'd32 : - lastFragValidByteNum__h22801 ; - assign lastFragValidByteNum__h22801 = { 1'd0, headerLen__h22004[4:0] } ; - assign leftShiftByteEn__h21797 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg[33:2] << - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg ; - assign leftShiftData__h21796 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg[289:34] << - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg ; - assign lkey__h13067 = - { pdMetaData_pdMrVec_0_mrTagVec_respQ_D_OUT[198], - pdMetaData_pdMrVec_0_mrTagVec_respQ_D_OUT[61:31] } ; - assign metaDataSrv_metaDataRespQ_i_notFull__60_AND_NO_ETC___d318 = - metaDataSrv_metaDataRespQ_FULL_N && - (!pdMetaData_pdTagVec_tagVec_0 || - qpMetaData_qpReqQ4Resp_EMPTY_N && - (!qpMetaData_qpReqQ4Resp_D_OUT[301] || - qpMetaData_qpVec_0_RDY_srvPortQP_response_get) && - IF_qpMetaData_qpReqQ4Resp_first__91_BITS_300_T_ETC___d314) ; - assign mrReqKey__h12289 = - metaDataSrv_mrReqReg[64] ? - metaDataSrv_mrReqReg[63:32] : - metaDataSrv_mrReqReg[31:0] ; - assign outByteEn__h21289 = - { headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg[33:2], - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[33:2] } >> - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg ; - assign outData__h21288 = - { headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg[289:34], - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[289:34] } >> - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg ; - assign pktFragNum__h37125 = - pktMetaDataAndPayloadPipeOutVec_pktFragNumReg + 8'd1 ; - assign pktLen__h37124 = - (pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[6:2] == - 5'd0) ? - pktLen__h37192 : - { pktMetaDataAndPayloadPipeOutVec_pktLenReg[12:5], - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[6:2] } ; - assign pktLen__h37192 = - { pktMetaDataAndPayloadPipeOutVec_pktLenReg[12:5] + 8'd1, - pktMetaDataAndPayloadPipeOutVec_pktLenReg[4:0] } ; - assign pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1861 = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_FULL_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_D_OUT[1] || - qpMetaData_qpVec_0_RDY_statusSQ_comm_getPMTU && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderVali_ETC___d1858) ; - assign pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_ETC___d1918 = - pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_EMPTY_N || - (pktMetaDataAndPayloadPipeOutVec_payloadFilterQ_D_OUT[1] ? - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] : - !pktMetaDataAndPayloadPipeOutVec_isValidPktReg) ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenC_ETC___d1950 = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_FULL_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_FULL_N) ; - assign pktMetaDataAndPayloadPipeOutVec_payloadPktLenC_ETC___d2185 = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_FULL_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadPktLenPreCheckQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_FULL_N) ; - assign pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_i_ETC___d1565 = - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_FULL_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_FULL_N) ; - assign pktMetaDataAndPayloadPipeOutVec_payloadValidat_ETC___d1712 = - pktMetaDataAndPayloadPipeOutVec_payloadValidationQ_FULL_N && - (!pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_D_OUT[1] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_FULL_N) ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilt_ETC___d1910 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_EMPTY_N && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[5] || - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_D_OUT[4] ? - pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_FULL_N : - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_FULL_N)) ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipe_ETC___d1419 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg[9:8] + - 2'd1 ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecv_ETC___d1674 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_EMPTY_N && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0] || - pktMetaDataAndPayloadPipeOutVec_payloadPreCheckQ_FULL_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPreCheckQ_FULL_N) ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderVali_ETC___d1858 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_EMPTY_N && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFilterQ_FULL_N && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[93] || - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1855) ; - assign pktMetaDataAndPayloadPipeOutVec_rdmaHeaderVali_ETC___d1886 = - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd4 || - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1) && - (qpMetaData_qpVec_0_statusSQ_comm_isERR || - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1884) ; - assign pktMetaData_pktFragNum__h38817 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2] ? - 8'd0 : - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[29:22] ; - assign rdmaHeader_headerByteEn__h26488 = - rdmaHeader_headerByteEn__h26491 << - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg ; - assign rdmaHeader_headerByteEn__h26491 = - { headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[1] ? - 32'd0 : - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg[48:17], - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[33:2] } ; - assign rdmaHeader_headerData__h26487 = - _theResult___headerData__h26503 << - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg ; - assign rightAlignedByteEn__h33653 = - { pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[2], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[3], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[4], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[5], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[6], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[7], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[8], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[9], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[10], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[11], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[12], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[13], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[14], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[15], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[16], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[17], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[18], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[19], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[20], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[21], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[22], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[23], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[24], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[25], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[26], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[27], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[28], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[29], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[30], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[31], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[32], - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[33] } ; - assign rkey__h13068 = - { pdMetaData_pdMrVec_0_mrTagVec_respQ_D_OUT[198], - pdMetaData_pdMrVec_0_mrTagVec_respQ_D_OUT[30:0] } ; - assign v__h33300 = - pktMetaDataAndPayloadPipeOutVec_payloadFragLenCalcQ_D_OUT[1] ? - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderFragLenCalcQ_D_OUT[150:149] : - pktMetaDataAndPayloadPipeOutVec_bthPadCntReg ; - assign value__h36219 = fragLen__h36262 ; - assign x1_avValue_headerByteEn__h29693 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] ? - rdmaHeader_headerByteEn__h26488 : - rdmaHeader_headerByteEn__h26491 ; - assign x1_avValue_headerData__h29692 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] ? - rdmaHeader_headerData__h26487 : - _theResult___headerData__h26503 ; - assign x1_avValue_pdHandler__h10043 = - qpMetaData_qpTagVec_respQ_D_OUT[32] ? - qpMetaData_qpTagVec_respQ_D_OUT[31:0] : - qpMetaData_qpReqQ4Cntrl_D_OUT[298:267] ; - assign x1_avValue_qpn__h10044 = - qpMetaData_qpTagVec_respQ_D_OUT[32] ? - qpMetaData_qpTagVec_respQ_D_OUT[23:0] : - qpMetaData_qpReqQ4Cntrl_D_OUT[266:243] ; - assign x1_avValue_snd_byteEn__h21189 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg ? - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg : - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[33:2] ; - assign x1_avValue_snd_byteEn__h21193 = - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[0] ? - y_avValue_byteEn__h20788 : - x1_avValue_snd_byteEn__h21189 ; - assign x__h22733 = - headerLen__h22004[4:3] != 2'd0 || headerLen__h22004[2] || - headerLen__h22004[1:0] != 2'd0 ; - assign x__h36323 = fragLen__h36262 - { 4'd0, v__h33300 } ; - assign x__h38061 = 13'd1 << x__h38115 ; - assign x_headerFragNum__h20036 = - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[9:8] - - 2'd1 ; - assign y__h38112 = ~x__h38061 ; - assign y_avValue_byteEn__h20788 = - (bits__h21377 != 2'd0 && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg) ? - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg : - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg[33:2] ; - always@(pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1) - begin - case (pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0]) - 1'd0: x__h6207 = pdMetaData_pdMrVec_0_mrTagVec_dataVec_0[133:102]; - 1'd1: x__h6207 = pdMetaData_pdMrVec_0_mrTagVec_dataVec_1[133:102]; - endcase - end - always@(pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1) - begin - case (pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0]) - 1'd0: x__h6223 = pdMetaData_pdMrVec_0_mrTagVec_dataVec_0[93:62]; - 1'd1: x__h6223 = pdMetaData_pdMrVec_0_mrTagVec_dataVec_1[93:62]; - endcase - end - always@(pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1) - begin - case (pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0]) - 1'd0: x__h6228 = pdMetaData_pdMrVec_0_mrTagVec_dataVec_0[61:31]; - 1'd1: x__h6228 = pdMetaData_pdMrVec_0_mrTagVec_dataVec_1[61:31]; - endcase - end - always@(pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1) - begin - case (pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0]) - 1'd0: x__h6233 = pdMetaData_pdMrVec_0_mrTagVec_dataVec_0[30:0]; - 1'd1: x__h6233 = pdMetaData_pdMrVec_0_mrTagVec_dataVec_1[30:0]; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT or - pktMetaDataAndPayloadPipeOutVec_pktLenReg or - pktLen__h37192 or pktLen__h37124 or fragLenExtWithOutPad__h36979) - begin - case (pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[15:14]) - 2'b0: pktLen__h36984 = pktLen__h37192; - 2'b01: pktLen__h36984 = pktLen__h37124; - 2'b10: pktLen__h36984 = 13'd32; - 2'b11: pktLen__h36984 = fragLenExtWithOutPad__h36979; - endcase - end - always@(inputDataStreamQ_D_OUT) - begin - case (inputDataStreamQ_D_OUT[289:282]) - 8'd0, 8'd1, 8'd2, 8'd4, 8'd7, 8'd8, 8'd14, 8'd174: - headerLen__h22004 = 7'd12; - 8'd3, - 8'd5, - 8'd9, - 8'd13, - 8'd15, - 8'd16, - 8'd17, - 8'd22, - 8'd23, - 8'd160, - 8'd161, - 8'd162, - 8'd164, - 8'd167, - 8'd168, - 8'd173, - 8'd175, - 8'd176, - 8'd177: - headerLen__h22004 = 7'd16; - 8'd6, 8'd10, 8'd12, 8'd129: headerLen__h22004 = 7'd28; - 8'd11, 8'd166, 8'd170, 8'd172: headerLen__h22004 = 7'd32; - 8'd18, 8'd101, 8'd178: headerLen__h22004 = 7'd24; - 8'd19, 8'd20: headerLen__h22004 = 7'd40; - 8'd100, 8'd163, 8'd165, 8'd169, 8'd182, 8'd183: - headerLen__h22004 = 7'd20; - 8'd171: headerLen__h22004 = 7'd36; - 8'd179, 8'd180: headerLen__h22004 = 7'd44; - default: headerLen__h22004 = 7'd0; - endcase - end - always@(rightAlignedByteEn__h33653) - begin - case (rightAlignedByteEn__h33653) - 32'd15: fragLen__h36262 = 6'd4; - 32'd255: fragLen__h36262 = 6'd8; - 32'd4095: fragLen__h36262 = 6'd12; - 32'd65535: fragLen__h36262 = 6'd16; - 32'd1048575: fragLen__h36262 = 6'd20; - 32'd16777215: fragLen__h36262 = 6'd24; - 32'd268435455: fragLen__h36262 = 6'd28; - 32'hFFFFFFFF: fragLen__h36262 = 6'd32; - default: fragLen__h36262 = 6'd0; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT or - pktMetaDataAndPayloadPipeOutVec_pktFragNumReg or pktFragNum__h37125) - begin - case (pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[15:14]) - 2'b0, 2'b01: pktFragNum__h36981 = pktFragNum__h37125; - 2'b10, 2'b11: pktFragNum__h36981 = 8'd1; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT) - begin - case (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[5:3]) - 3'd1: x__h38115 = 32'd8; - 3'd2: x__h38115 = 32'd9; - 3'd3: x__h38115 = 32'd10; - 3'd4: x__h38115 = 32'd11; - default: x__h38115 = 32'd12; - endcase - end - always@(pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT or - pdMetaData_pdMrVec_0_mrTagVec_tagVec_0 or - pdMetaData_pdMrVec_0_mrTagVec_tagVec_1) - begin - case (pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0]) - 1'd0: - SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_ETC___d56 = - pdMetaData_pdMrVec_0_mrTagVec_tagVec_0; - 1'd1: - SEL_ARR_pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_ETC___d56 = - pdMetaData_pdMrVec_0_mrTagVec_tagVec_1; - endcase - end - always@(qpMetaData_qpReqQ4Resp_D_OUT or - qpMetaData_qpReqQ4Resp_EMPTY_N or - qpMetaData_qpVec_0_RDY_srvPortQP_response_get) - begin - case (qpMetaData_qpReqQ4Resp_D_OUT[300:299]) - 2'd0, 2'd1, 2'd2, 2'd3: - IF_qpMetaData_qpReqQ4Resp_first__91_BITS_300_T_ETC___d314 = - !qpMetaData_qpReqQ4Resp_D_OUT[301] || - qpMetaData_qpVec_0_RDY_srvPortQP_response_get; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT or - qpMetaData_qpVec_0_statusSQ_getTypeQP) - begin - case (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187]) - 3'd0: - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842 = - qpMetaData_qpVec_0_statusSQ_getTypeQP != 4'd2; - 3'd1: - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842 = - qpMetaData_qpVec_0_statusSQ_getTypeQP != 4'd3; - 3'd3: - IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842 = - qpMetaData_qpVec_0_statusSQ_getTypeQP != 4'd4; - default: IF_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderV_ETC___d1842 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] != - 3'd5 || - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4] || - qpMetaData_qpVec_0_statusSQ_getTypeQP != 4'd10) && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4] || - qpMetaData_qpVec_0_statusSQ_getTypeQP != 4'd9); - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT or - qpMetaData_qpVec_0_statusSQ_getTypeQP) - begin - case (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187]) - 3'd0: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1 = - qpMetaData_qpVec_0_statusSQ_getTypeQP == 4'd2; - 3'd1: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1 = - qpMetaData_qpVec_0_statusSQ_getTypeQP == 4'd3; - 3'd3: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1 = - qpMetaData_qpVec_0_statusSQ_getTypeQP == 4'd4; - default: CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q1 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[189:187] == - 3'd5 && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] && - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4] && - qpMetaData_qpVec_0_statusSQ_getTypeQP == 4'd10 || - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[3] || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderValidationQ_D_OUT[4]) && - qpMetaData_qpVec_0_statusSQ_getTypeQP == 4'd9); - endcase - end - always@(pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1) - begin - case (pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0]) - 1'd0: - CASE_pdMetaData_pdMrVec_0_mrTagVec_reqQD_OUT__ETC__q2 = - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0[101:94]; - 1'd1: - CASE_pdMetaData_pdMrVec_0_mrTagVec_reqQD_OUT__ETC__q2 = - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1[101:94]; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT or - pktMetaDataAndPayloadPipeOutVec_pktValidReg or - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT) - begin - case (pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[15:14]) - 2'd0: - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2151 = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[15:14] == - 2'b0 && - pktMetaDataAndPayloadPipeOutVec_pktValidReg && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[0]; - 2'b01: - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2151 = - pktMetaDataAndPayloadPipeOutVec_pktValidReg; - 2'b10: - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2151 = - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[0]; - 2'b11: - IF_pktMetaDataAndPayloadPipeOutVec_payloadPktL_ETC___d2151 = - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCalcQ_D_OUT[2] || - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCalcQ_D_OUT[1]); - endcase - end - always@(pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 or - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1) - begin - case (pdMetaData_pdMrVec_0_mrTagVec_reqQ_D_OUT[0]) - 1'd0: - CASE_pdMetaData_pdMrVec_0_mrTagVec_reqQD_OUT__ETC__q3 = - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0[197:134]; - 1'd1: - CASE_pdMetaData_pdMrVec_0_mrTagVec_reqQD_OUT__ETC__q3 = - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1[197:134]; - endcase - end - always@(qpMetaData_qpReqQ4Resp_D_OUT or - IF_qpMetaData_qpReqQ4Resp_first__91_BIT_301_04_ETC___d333) - begin - case (qpMetaData_qpReqQ4Resp_D_OUT[300:299]) - 2'd0, 2'd1, 2'd2, 2'd3: - CASE_qpMetaData_qpReqQ4RespD_OUT_BITS_300_TO__ETC__q4 = - IF_qpMetaData_qpReqQ4Resp_first__91_BIT_301_04_ETC___d333; - endcase - end - always@(qpMetaData_qpReqQ4Cntrl_D_OUT or x1_avValue_pdHandler__h10043) - begin - case (qpMetaData_qpReqQ4Cntrl_D_OUT[300:299]) - 2'd0, 2'd1: - CASE_qpMetaData_qpReqQ4CntrlD_OUT_BITS_300_TO_ETC__q5 = - x1_avValue_pdHandler__h10043; - default: CASE_qpMetaData_qpReqQ4CntrlD_OUT_BITS_300_TO_ETC__q5 = - qpMetaData_qpReqQ4Cntrl_D_OUT[298:267]; - endcase - end - always@(qpMetaData_qpReqQ4Cntrl_D_OUT or x1_avValue_qpn__h10044) - begin - case (qpMetaData_qpReqQ4Cntrl_D_OUT[300:299]) - 2'd0, 2'd1: - CASE_qpMetaData_qpReqQ4CntrlD_OUT_BITS_300_TO_ETC__q6 = - x1_avValue_qpn__h10044; - default: CASE_qpMetaData_qpReqQ4CntrlD_OUT_BITS_300_TO_ETC__q6 = - qpMetaData_qpReqQ4Cntrl_D_OUT[266:243]; - endcase - end - always@(qpMetaData_qpReqQ4Cntrl_D_OUT or - qpMetaData_qpVec_0_RDY_srvPortQP_request_put or - qpMetaData_qpTagVec_respQ_EMPTY_N or - qpMetaData_qpTagVec_respQ_D_OUT) - begin - case (qpMetaData_qpReqQ4Cntrl_D_OUT[300:299]) - 2'd0, 2'd1: - IF_qpMetaData_qpReqQ4Cntrl_first__66_BITS_300__ETC___d184 = - qpMetaData_qpTagVec_respQ_EMPTY_N && - (!qpMetaData_qpTagVec_respQ_D_OUT[32] || - qpMetaData_qpVec_0_RDY_srvPortQP_request_put); - default: IF_qpMetaData_qpReqQ4Cntrl_first__66_BITS_300__ETC___d184 = - qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] != 2'd2 && - qpMetaData_qpReqQ4Cntrl_D_OUT[300:299] != 2'd3 || - qpMetaData_qpVec_0_RDY_srvPortQP_request_put; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT) - begin - case (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[5:3]) - 3'd1: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q7 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[14] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[13:6] != - 8'd0; - 3'd2: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q7 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[15] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[14:6] != - 9'd0; - 3'd3: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q7 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[16] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[15:6] != - 10'd0; - 3'd4: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q7 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[17] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[16:6] != - 11'd0; - default: CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q7 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[18] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenPreCheckQ_D_OUT[17:6] != - 12'd0; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT) - begin - case (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585]) - 5'd6, 5'd7: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q8 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[582:581] == - 2'd0; - default: CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q8 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd8 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd10 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd9 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd11 || - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd12 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd19 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd20) && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[582:581] == - 2'd0; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT or - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q8) - begin - case (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585]) - 5'd0, 5'd1: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q9 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[582:581] == - 2'd0; - default: CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q9 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd2 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd4 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd3 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd5 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd22 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd23 || - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q8; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT) - begin - case (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[495:494]) - 2'd0, 2'd1: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q10 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[582:581] == - 2'd0; - default: CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q10 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[495:494] == - 2'd3 && - (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[493:489] == - 5'd0 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[493:489] == - 5'd1 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[493:489] == - 5'd2 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[493:489] == - 5'd3 || - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[493:489] == - 5'd4) && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[582:581] == - 2'd0; - endcase - end - always@(pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT or - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q10) - begin - case (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585]) - 5'd13, 5'd18: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q11 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[495:494] == - 2'd0 && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[582:581] == - 2'd0; - 5'd14: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q11 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[582:581] == - 2'd0; - 5'd15, 5'd16: - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q11 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[495:494] == - 2'd0; - default: CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q11 = - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerOutQ_D_OUT[589:585] == - 5'd17 && - CASE_pktMetaDataAndPayloadPipeOutVec_rdmaHeade_ETC__q10; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg <= `BSV_ASSIGNMENT_DELAY - 1'd1; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg <= `BSV_ASSIGNMENT_DELAY - 2'd0; - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv <= `BSV_ASSIGNMENT_DELAY - 1'd0; - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv <= `BSV_ASSIGNMENT_DELAY - 1'd0; - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv <= `BSV_ASSIGNMENT_DELAY - 18'd43690; - metaDataSrv_stateReg <= `BSV_ASSIGNMENT_DELAY 3'd0; - pdMetaData_pdMrVec_0_mrTagVec_clearReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - pdMetaData_pdMrVec_0_mrTagVec_fullReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg <= `BSV_ASSIGNMENT_DELAY - 2'd0; - pdMetaData_pdMrVec_0_mrTagVec_tagVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - pdMetaData_pdMrVec_0_mrTagVec_tagVec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0; - pdMetaData_pdTagVec_clearReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - pdMetaData_pdTagVec_fullReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - pdMetaData_pdTagVec_tagVecStateReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - pdMetaData_pdTagVec_tagVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv <= `BSV_ASSIGNMENT_DELAY - 291'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - pktMetaDataAndPayloadPipeOutVec_pktBufStateReg <= `BSV_ASSIGNMENT_DELAY - 1'd0; - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg <= `BSV_ASSIGNMENT_DELAY - 1'd0; - qpMetaData_qpTagVec_clearReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - qpMetaData_qpTagVec_fullReg <= `BSV_ASSIGNMENT_DELAY 1'd0; - qpMetaData_qpTagVec_tagVecStateReg <= `BSV_ASSIGNMENT_DELAY 2'd0; - qpMetaData_qpTagVec_tagVec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0; - end - else - begin - if (arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg_EN) - arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg <= `BSV_ASSIGNMENT_DELAY - arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_EN) - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_EN) - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_EN) - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv_D_IN; - if (metaDataSrv_stateReg_EN) - metaDataSrv_stateReg <= `BSV_ASSIGNMENT_DELAY - metaDataSrv_stateReg_D_IN; - if (pdMetaData_pdMrVec_0_mrTagVec_clearReg_EN) - pdMetaData_pdMrVec_0_mrTagVec_clearReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdMrVec_0_mrTagVec_clearReg_D_IN; - if (pdMetaData_pdMrVec_0_mrTagVec_fullReg_EN) - pdMetaData_pdMrVec_0_mrTagVec_fullReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdMrVec_0_mrTagVec_fullReg_D_IN; - if (pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg_EN) - pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg_D_IN; - if (pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_EN) - pdMetaData_pdMrVec_0_mrTagVec_tagVec_0 <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdMrVec_0_mrTagVec_tagVec_0_D_IN; - if (pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_EN) - pdMetaData_pdMrVec_0_mrTagVec_tagVec_1 <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdMrVec_0_mrTagVec_tagVec_1_D_IN; - if (pdMetaData_pdTagVec_clearReg_EN) - pdMetaData_pdTagVec_clearReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdTagVec_clearReg_D_IN; - if (pdMetaData_pdTagVec_fullReg_EN) - pdMetaData_pdTagVec_fullReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdTagVec_fullReg_D_IN; - if (pdMetaData_pdTagVec_tagVecStateReg_EN) - pdMetaData_pdTagVec_tagVecStateReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdTagVec_tagVecStateReg_D_IN; - if (pdMetaData_pdTagVec_tagVec_0_EN) - pdMetaData_pdTagVec_tagVec_0 <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdTagVec_tagVec_0_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_EN) - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_EN) - pktMetaDataAndPayloadPipeOutVec_pktBufStateReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_EN) - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg_D_IN; - if (qpMetaData_qpTagVec_clearReg_EN) - qpMetaData_qpTagVec_clearReg <= `BSV_ASSIGNMENT_DELAY - qpMetaData_qpTagVec_clearReg_D_IN; - if (qpMetaData_qpTagVec_fullReg_EN) - qpMetaData_qpTagVec_fullReg <= `BSV_ASSIGNMENT_DELAY - qpMetaData_qpTagVec_fullReg_D_IN; - if (qpMetaData_qpTagVec_tagVecStateReg_EN) - qpMetaData_qpTagVec_tagVecStateReg <= `BSV_ASSIGNMENT_DELAY - qpMetaData_qpTagVec_tagVecStateReg_D_IN; - if (qpMetaData_qpTagVec_tagVec_0_EN) - qpMetaData_qpTagVec_tagVec_0 <= `BSV_ASSIGNMENT_DELAY - qpMetaData_qpTagVec_tagVec_0_D_IN; - end - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg_D_IN; - if (headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_EN) - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg <= `BSV_ASSIGNMENT_DELAY - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg_D_IN; - if (metaDataSrv_mrReqReg_EN) - metaDataSrv_mrReqReg <= `BSV_ASSIGNMENT_DELAY metaDataSrv_mrReqReg_D_IN; - if (metaDataSrv_pdReqReg_EN) - metaDataSrv_pdReqReg <= `BSV_ASSIGNMENT_DELAY metaDataSrv_pdReqReg_D_IN; - if (metaDataSrv_qpReqReg_EN) - metaDataSrv_qpReqReg <= `BSV_ASSIGNMENT_DELAY metaDataSrv_qpReqReg_D_IN; - if (pdMetaData_pdMrVec_0_mrTagVec_dataVec_0_EN) - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0_D_IN; - if (pdMetaData_pdMrVec_0_mrTagVec_dataVec_1_EN) - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1 <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1_D_IN; - if (pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg_EN) - pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg_D_IN; - if (pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg_EN) - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg_D_IN; - if (pdMetaData_pdTagVec_dataVec_0_EN) - pdMetaData_pdTagVec_dataVec_0 <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdTagVec_dataVec_0_D_IN; - if (pdMetaData_pdTagVec_maybeInsertIdxReg_EN) - pdMetaData_pdTagVec_maybeInsertIdxReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdTagVec_maybeInsertIdxReg_D_IN; - if (pdMetaData_pdTagVec_respSuccessReg_EN) - pdMetaData_pdTagVec_respSuccessReg <= `BSV_ASSIGNMENT_DELAY - pdMetaData_pdTagVec_respSuccessReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_EN) - pktMetaDataAndPayloadPipeOutVec_bthPadCntReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_bthPadCntReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_isValidPktReg_EN) - pktMetaDataAndPayloadPipeOutVec_isValidPktReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_isValidPktReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_EN) - pktMetaDataAndPayloadPipeOutVec_pktFragNumReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_pktFragNumReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_pktLenReg_EN) - pktMetaDataAndPayloadPipeOutVec_pktLenReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_pktLenReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_pktValidReg_EN) - pktMetaDataAndPayloadPipeOutVec_pktValidReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_pktValidReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg_EN) - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg_EN) - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg_EN) - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg_D_IN; - if (pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg_EN) - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg <= `BSV_ASSIGNMENT_DELAY - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg_D_IN; - if (qpMetaData_qpTagVec_dataVec_0_EN) - qpMetaData_qpTagVec_dataVec_0 <= `BSV_ASSIGNMENT_DELAY - qpMetaData_qpTagVec_dataVec_0_D_IN; - if (qpMetaData_qpTagVec_maybeInsertIdxReg_EN) - qpMetaData_qpTagVec_maybeInsertIdxReg <= `BSV_ASSIGNMENT_DELAY - qpMetaData_qpTagVec_maybeInsertIdxReg_D_IN; - if (qpMetaData_qpTagVec_respSuccessReg_EN) - qpMetaData_qpTagVec_respSuccessReg <= `BSV_ASSIGNMENT_DELAY - qpMetaData_qpTagVec_respSuccessReg_D_IN; - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - arbitratedDmaReadClt_arbitratedClient_shouldSaveGrantIdxReg = 1'h0; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_curDataStreamReg = - 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragByteEnReg = - 32'hAAAAAAAA; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidBitNumReg = - 9'h0AA; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragInvalidByteNumReg = - 6'h2A; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidBitNumReg = - 9'h0AA; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerLastFragValidByteNumReg = - 6'h2A; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerMetaDataReg = - 17'h0AAAA; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isFirstDataFragReg = - 1'h0; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_isHeaderLastFragReg = - 1'h0; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_preDataStreamReg = - 290'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_shiftedCurDataFragByteEnReg = - 32'hAAAAAAAA; - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_stageReg = - 2'h2; - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_0_rv = - 1'h0; - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOutVec_v_taken_signal_1_rv = - 1'h0; - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv = - 18'h2AAAA; - metaDataSrv_mrReqReg = - 264'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - metaDataSrv_pdReqReg = 65'h0AAAAAAAAAAAAAAAA; - metaDataSrv_qpReqReg = - 301'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - metaDataSrv_stateReg = 3'h2; - pdMetaData_pdMrVec_0_mrTagVec_clearReg = 1'h0; - pdMetaData_pdMrVec_0_mrTagVec_dataVec_0 = - 198'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - pdMetaData_pdMrVec_0_mrTagVec_dataVec_1 = - 198'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - pdMetaData_pdMrVec_0_mrTagVec_fullReg = 1'h0; - pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg = 2'h2; - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg = 1'h0; - pdMetaData_pdMrVec_0_mrTagVec_tagVecStateReg = 2'h2; - pdMetaData_pdMrVec_0_mrTagVec_tagVec_0 = 1'h0; - pdMetaData_pdMrVec_0_mrTagVec_tagVec_1 = 1'h0; - pdMetaData_pdTagVec_clearReg = 1'h0; - pdMetaData_pdTagVec_dataVec_0 = 32'hAAAAAAAA; - pdMetaData_pdTagVec_fullReg = 1'h0; - pdMetaData_pdTagVec_maybeInsertIdxReg = 1'h0; - pdMetaData_pdTagVec_respSuccessReg = 1'h0; - pdMetaData_pdTagVec_tagVecStateReg = 2'h2; - pdMetaData_pdTagVec_tagVec_0 = 1'h0; - pktMetaDataAndPayloadPipeOutVec_bthPadCntReg = 2'h2; - pktMetaDataAndPayloadPipeOutVec_isValidPktReg = 1'h0; - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv = - 291'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - pktMetaDataAndPayloadPipeOutVec_pktBufStateReg = 1'h0; - pktMetaDataAndPayloadPipeOutVec_pktFragNumReg = 8'hAA; - pktMetaDataAndPayloadPipeOutVec_pktLenReg = 13'h0AAA; - pktMetaDataAndPayloadPipeOutVec_pktValidReg = 1'h0; - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_busyReg = 1'h0; - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragBitNumReg = - 513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerInvalidFragByteNumReg = - 7'h2A; - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg = - 17'h0AAAA; - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_rdmaHeaderReg = - 593'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA; - qpMetaData_qpTagVec_clearReg = 1'h0; - qpMetaData_qpTagVec_dataVec_0 = 32'hAAAAAAAA; - qpMetaData_qpTagVec_fullReg = 1'h0; - qpMetaData_qpTagVec_maybeInsertIdxReg = 1'h0; - qpMetaData_qpTagVec_respSuccessReg = 1'h0; - qpMetaData_qpTagVec_tagVecStateReg = 2'h2; - qpMetaData_qpTagVec_tagVec_0 = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on - - // handling of system tasks - - // synopsys translate_off - always@(negedge CLK) - begin - #0; - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg && - !pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[1]) - begin - v__h5492 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg && - !pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[1]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h5492, - "\"MetaData.bsv\", line 113, column 17\n", - "maybeInsertIdxReg assertion @ mkTagVecSrv"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg && - !pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[1]) - $display("maybeInsertIdxReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg && - !pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[1]) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg && - !pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[1]) - $display(" should be valid"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdMrVec_0_mrTagVec_genInsertResp && - pdMetaData_pdMrVec_0_mrTagVec_respSuccessReg && - !pdMetaData_pdMrVec_0_mrTagVec_maybeInsertIdxReg[1]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp && - pdMetaData_pdTagVec_respSuccessReg && - !pdMetaData_pdTagVec_maybeInsertIdxReg) - begin - v__h2324 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp && - pdMetaData_pdTagVec_respSuccessReg && - !pdMetaData_pdTagVec_maybeInsertIdxReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h2324, - "\"MetaData.bsv\", line 113, column 17\n", - "maybeInsertIdxReg assertion @ mkTagVecSrv"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp && - pdMetaData_pdTagVec_respSuccessReg && - !pdMetaData_pdTagVec_maybeInsertIdxReg) - $display("maybeInsertIdxReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp && - pdMetaData_pdTagVec_respSuccessReg && - !pdMetaData_pdTagVec_maybeInsertIdxReg) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp && - pdMetaData_pdTagVec_respSuccessReg && - !pdMetaData_pdTagVec_maybeInsertIdxReg) - $display(" should be valid"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pdMetaData_pdTagVec_genInsertResp && - pdMetaData_pdTagVec_respSuccessReg && - !pdMetaData_pdTagVec_maybeInsertIdxReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129) - begin - v__h22546 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h22546, - "\"InputPktHandle.bsv\", line 142, column 17\n", - "!isZero(headerLen) assertion @ mkExtractHeaderFromRdmaPktPipeOut"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd0) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "SEND_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd1) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "SEND_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd2) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "SEND_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd3) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "SEND_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd4) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "SEND_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd5) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "SEND_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd6) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_WRITE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd7) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_WRITE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd8) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_WRITE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd9) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_WRITE_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd10) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd11) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd12) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_READ_REQUEST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd13) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd14) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd15) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd16) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd17) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd18) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "ATOMIC_ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd19) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "COMPARE_SWAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd20) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "FETCH_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd21) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "RESYNC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] == 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "SEND_LAST_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd0 && - inputDataStreamQ_D_OUT[286:282] != 5'd0 && - inputDataStreamQ_D_OUT[286:282] != 5'd1 && - inputDataStreamQ_D_OUT[286:282] != 5'd2 && - inputDataStreamQ_D_OUT[286:282] != 5'd3 && - inputDataStreamQ_D_OUT[286:282] != 5'd4 && - inputDataStreamQ_D_OUT[286:282] != 5'd5 && - inputDataStreamQ_D_OUT[286:282] != 5'd6 && - inputDataStreamQ_D_OUT[286:282] != 5'd7 && - inputDataStreamQ_D_OUT[286:282] != 5'd8 && - inputDataStreamQ_D_OUT[286:282] != 5'd9 && - inputDataStreamQ_D_OUT[286:282] != 5'd10 && - inputDataStreamQ_D_OUT[286:282] != 5'd11 && - inputDataStreamQ_D_OUT[286:282] != 5'd12 && - inputDataStreamQ_D_OUT[286:282] != 5'd13 && - inputDataStreamQ_D_OUT[286:282] != 5'd14 && - inputDataStreamQ_D_OUT[286:282] != 5'd15 && - inputDataStreamQ_D_OUT[286:282] != 5'd16 && - inputDataStreamQ_D_OUT[286:282] != 5'd17 && - inputDataStreamQ_D_OUT[286:282] != 5'd18 && - inputDataStreamQ_D_OUT[286:282] != 5'd19 && - inputDataStreamQ_D_OUT[286:282] != 5'd20 && - inputDataStreamQ_D_OUT[286:282] != 5'd21 && - inputDataStreamQ_D_OUT[286:282] != 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RC", - ", rdmaOpCode=", - "SEND_ONLY_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd0) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "SEND_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd1) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "SEND_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd2) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "SEND_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd3) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "SEND_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd4) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "SEND_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd5) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "SEND_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd6) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_WRITE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd7) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_WRITE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd8) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_WRITE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd9) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_WRITE_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd10) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd11) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd12) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_READ_REQUEST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd13) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd14) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd15) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd16) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd17) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd18) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "ATOMIC_ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd19) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "COMPARE_SWAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd20) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "FETCH_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd21) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "RESYNC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] == 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "SEND_LAST_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd1 && - inputDataStreamQ_D_OUT[286:282] != 5'd0 && - inputDataStreamQ_D_OUT[286:282] != 5'd1 && - inputDataStreamQ_D_OUT[286:282] != 5'd2 && - inputDataStreamQ_D_OUT[286:282] != 5'd3 && - inputDataStreamQ_D_OUT[286:282] != 5'd4 && - inputDataStreamQ_D_OUT[286:282] != 5'd5 && - inputDataStreamQ_D_OUT[286:282] != 5'd6 && - inputDataStreamQ_D_OUT[286:282] != 5'd7 && - inputDataStreamQ_D_OUT[286:282] != 5'd8 && - inputDataStreamQ_D_OUT[286:282] != 5'd9 && - inputDataStreamQ_D_OUT[286:282] != 5'd10 && - inputDataStreamQ_D_OUT[286:282] != 5'd11 && - inputDataStreamQ_D_OUT[286:282] != 5'd12 && - inputDataStreamQ_D_OUT[286:282] != 5'd13 && - inputDataStreamQ_D_OUT[286:282] != 5'd14 && - inputDataStreamQ_D_OUT[286:282] != 5'd15 && - inputDataStreamQ_D_OUT[286:282] != 5'd16 && - inputDataStreamQ_D_OUT[286:282] != 5'd17 && - inputDataStreamQ_D_OUT[286:282] != 5'd18 && - inputDataStreamQ_D_OUT[286:282] != 5'd19 && - inputDataStreamQ_D_OUT[286:282] != 5'd20 && - inputDataStreamQ_D_OUT[286:282] != 5'd21 && - inputDataStreamQ_D_OUT[286:282] != 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UC", - ", rdmaOpCode=", - "SEND_ONLY_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd0) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "SEND_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd1) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "SEND_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd2) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "SEND_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd3) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "SEND_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd4) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "SEND_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd5) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "SEND_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd6) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_WRITE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd7) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_WRITE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd8) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_WRITE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd9) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_WRITE_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd10) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd11) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd12) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_READ_REQUEST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd13) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd14) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd15) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd16) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd17) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd18) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "ATOMIC_ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd19) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "COMPARE_SWAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd20) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "FETCH_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd21) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "RESYNC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] == 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "SEND_LAST_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd2 && - inputDataStreamQ_D_OUT[286:282] != 5'd0 && - inputDataStreamQ_D_OUT[286:282] != 5'd1 && - inputDataStreamQ_D_OUT[286:282] != 5'd2 && - inputDataStreamQ_D_OUT[286:282] != 5'd3 && - inputDataStreamQ_D_OUT[286:282] != 5'd4 && - inputDataStreamQ_D_OUT[286:282] != 5'd5 && - inputDataStreamQ_D_OUT[286:282] != 5'd6 && - inputDataStreamQ_D_OUT[286:282] != 5'd7 && - inputDataStreamQ_D_OUT[286:282] != 5'd8 && - inputDataStreamQ_D_OUT[286:282] != 5'd9 && - inputDataStreamQ_D_OUT[286:282] != 5'd10 && - inputDataStreamQ_D_OUT[286:282] != 5'd11 && - inputDataStreamQ_D_OUT[286:282] != 5'd12 && - inputDataStreamQ_D_OUT[286:282] != 5'd13 && - inputDataStreamQ_D_OUT[286:282] != 5'd14 && - inputDataStreamQ_D_OUT[286:282] != 5'd15 && - inputDataStreamQ_D_OUT[286:282] != 5'd16 && - inputDataStreamQ_D_OUT[286:282] != 5'd17 && - inputDataStreamQ_D_OUT[286:282] != 5'd18 && - inputDataStreamQ_D_OUT[286:282] != 5'd19 && - inputDataStreamQ_D_OUT[286:282] != 5'd20 && - inputDataStreamQ_D_OUT[286:282] != 5'd21 && - inputDataStreamQ_D_OUT[286:282] != 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_RD", - ", rdmaOpCode=", - "SEND_ONLY_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd0) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "SEND_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd1) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "SEND_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd2) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "SEND_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd3) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "SEND_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd4) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "SEND_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd5) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "SEND_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd6) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_WRITE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd7) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_WRITE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd8) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_WRITE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd9) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_WRITE_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd10) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd11) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd12) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_READ_REQUEST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd13) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd14) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd15) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd16) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd17) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd18) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "ATOMIC_ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd19) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "COMPARE_SWAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd20) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "FETCH_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd21) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "RESYNC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] == 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "SEND_LAST_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd3 && - inputDataStreamQ_D_OUT[286:282] != 5'd0 && - inputDataStreamQ_D_OUT[286:282] != 5'd1 && - inputDataStreamQ_D_OUT[286:282] != 5'd2 && - inputDataStreamQ_D_OUT[286:282] != 5'd3 && - inputDataStreamQ_D_OUT[286:282] != 5'd4 && - inputDataStreamQ_D_OUT[286:282] != 5'd5 && - inputDataStreamQ_D_OUT[286:282] != 5'd6 && - inputDataStreamQ_D_OUT[286:282] != 5'd7 && - inputDataStreamQ_D_OUT[286:282] != 5'd8 && - inputDataStreamQ_D_OUT[286:282] != 5'd9 && - inputDataStreamQ_D_OUT[286:282] != 5'd10 && - inputDataStreamQ_D_OUT[286:282] != 5'd11 && - inputDataStreamQ_D_OUT[286:282] != 5'd12 && - inputDataStreamQ_D_OUT[286:282] != 5'd13 && - inputDataStreamQ_D_OUT[286:282] != 5'd14 && - inputDataStreamQ_D_OUT[286:282] != 5'd15 && - inputDataStreamQ_D_OUT[286:282] != 5'd16 && - inputDataStreamQ_D_OUT[286:282] != 5'd17 && - inputDataStreamQ_D_OUT[286:282] != 5'd18 && - inputDataStreamQ_D_OUT[286:282] != 5'd19 && - inputDataStreamQ_D_OUT[286:282] != 5'd20 && - inputDataStreamQ_D_OUT[286:282] != 5'd21 && - inputDataStreamQ_D_OUT[286:282] != 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_UD", - ", rdmaOpCode=", - "SEND_ONLY_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd0) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "SEND_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd1) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "SEND_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd2) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "SEND_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd3) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "SEND_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd4) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "SEND_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd5) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "SEND_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd6) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_WRITE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd7) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_WRITE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd8) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_WRITE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd9) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_WRITE_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd10) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd11) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd12) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_READ_REQUEST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd13) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd14) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd15) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd16) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd17) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd18) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "ATOMIC_ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd19) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "COMPARE_SWAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd20) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "FETCH_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd21) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "RESYNC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "SEND_LAST_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] == 3'd4 && - inputDataStreamQ_D_OUT[286:282] != 5'd0 && - inputDataStreamQ_D_OUT[286:282] != 5'd1 && - inputDataStreamQ_D_OUT[286:282] != 5'd2 && - inputDataStreamQ_D_OUT[286:282] != 5'd3 && - inputDataStreamQ_D_OUT[286:282] != 5'd4 && - inputDataStreamQ_D_OUT[286:282] != 5'd5 && - inputDataStreamQ_D_OUT[286:282] != 5'd6 && - inputDataStreamQ_D_OUT[286:282] != 5'd7 && - inputDataStreamQ_D_OUT[286:282] != 5'd8 && - inputDataStreamQ_D_OUT[286:282] != 5'd9 && - inputDataStreamQ_D_OUT[286:282] != 5'd10 && - inputDataStreamQ_D_OUT[286:282] != 5'd11 && - inputDataStreamQ_D_OUT[286:282] != 5'd12 && - inputDataStreamQ_D_OUT[286:282] != 5'd13 && - inputDataStreamQ_D_OUT[286:282] != 5'd14 && - inputDataStreamQ_D_OUT[286:282] != 5'd15 && - inputDataStreamQ_D_OUT[286:282] != 5'd16 && - inputDataStreamQ_D_OUT[286:282] != 5'd17 && - inputDataStreamQ_D_OUT[286:282] != 5'd18 && - inputDataStreamQ_D_OUT[286:282] != 5'd19 && - inputDataStreamQ_D_OUT[286:282] != 5'd20 && - inputDataStreamQ_D_OUT[286:282] != 5'd21 && - inputDataStreamQ_D_OUT[286:282] != 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_CNP", - ", rdmaOpCode=", - "SEND_ONLY_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd0) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "SEND_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd1) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "SEND_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd2) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "SEND_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd3) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "SEND_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd4) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "SEND_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd5) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "SEND_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd6) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_WRITE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd7) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_WRITE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd8) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_WRITE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd9) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_WRITE_LAST_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd10) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd11) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_WRITE_ONLY_WITH_IMMEDIATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd12) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_READ_REQUEST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd13) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_FIRST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd14) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_MIDDLE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd15) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_LAST"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd16) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RDMA_READ_RESPONSE_ONLY"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd17) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd18) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "ATOMIC_ACKNOWLEDGE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd19) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "COMPARE_SWAP"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd20) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "FETCH_ADD"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd21) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "RESYNC"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] == 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "SEND_LAST_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129 && - inputDataStreamQ_D_OUT[289:287] != 3'd0 && - inputDataStreamQ_D_OUT[289:287] != 3'd1 && - inputDataStreamQ_D_OUT[289:287] != 3'd2 && - inputDataStreamQ_D_OUT[289:287] != 3'd3 && - inputDataStreamQ_D_OUT[289:287] != 3'd4 && - inputDataStreamQ_D_OUT[286:282] != 5'd0 && - inputDataStreamQ_D_OUT[286:282] != 5'd1 && - inputDataStreamQ_D_OUT[286:282] != 5'd2 && - inputDataStreamQ_D_OUT[286:282] != 5'd3 && - inputDataStreamQ_D_OUT[286:282] != 5'd4 && - inputDataStreamQ_D_OUT[286:282] != 5'd5 && - inputDataStreamQ_D_OUT[286:282] != 5'd6 && - inputDataStreamQ_D_OUT[286:282] != 5'd7 && - inputDataStreamQ_D_OUT[286:282] != 5'd8 && - inputDataStreamQ_D_OUT[286:282] != 5'd9 && - inputDataStreamQ_D_OUT[286:282] != 5'd10 && - inputDataStreamQ_D_OUT[286:282] != 5'd11 && - inputDataStreamQ_D_OUT[286:282] != 5'd12 && - inputDataStreamQ_D_OUT[286:282] != 5'd13 && - inputDataStreamQ_D_OUT[286:282] != 5'd14 && - inputDataStreamQ_D_OUT[286:282] != 5'd15 && - inputDataStreamQ_D_OUT[286:282] != 5'd16 && - inputDataStreamQ_D_OUT[286:282] != 5'd17 && - inputDataStreamQ_D_OUT[286:282] != 5'd18 && - inputDataStreamQ_D_OUT[286:282] != 5'd19 && - inputDataStreamQ_D_OUT[286:282] != 5'd20 && - inputDataStreamQ_D_OUT[286:282] != 5'd21 && - inputDataStreamQ_D_OUT[286:282] != 5'd22) - $display("headerLen=%0d should not be zero, transType=", - headerLen__h22004, - "TRANS_TYPE_XRC", - ", rdmaOpCode=", - "SEND_ONLY_WITH_INVALIDATE"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_extractHeader && - inputDataStreamQ_D_OUT[1] && - inputDataStreamQ_D_OUT[289:282] != 8'd0 && - inputDataStreamQ_D_OUT[289:282] != 8'd1 && - inputDataStreamQ_D_OUT[289:282] != 8'd2 && - inputDataStreamQ_D_OUT[289:282] != 8'd3 && - inputDataStreamQ_D_OUT[289:282] != 8'd4 && - inputDataStreamQ_D_OUT[289:282] != 8'd5 && - inputDataStreamQ_D_OUT[289:282] != 8'd6 && - inputDataStreamQ_D_OUT[289:282] != 8'd7 && - inputDataStreamQ_D_OUT[289:282] != 8'd8 && - inputDataStreamQ_D_OUT[289:282] != 8'd9 && - inputDataStreamQ_D_OUT[289:282] != 8'd10 && - inputDataStreamQ_D_OUT[289:282] != 8'd11 && - inputDataStreamQ_D_OUT[289:282] != 8'd12 && - inputDataStreamQ_D_OUT[289:282] != 8'd19 && - inputDataStreamQ_D_OUT[289:282] != 8'd20 && - inputDataStreamQ_D_OUT[289:282] != 8'd22 && - inputDataStreamQ_D_OUT[289:282] != 8'd23 && - inputDataStreamQ_D_OUT[289:282] != 8'd13 && - inputDataStreamQ_D_OUT[289:282] != 8'd173 && - inputDataStreamQ_D_OUT[289:282] != 8'd14 && - inputDataStreamQ_D_OUT[289:282] != 8'd174 && - inputDataStreamQ_D_OUT[289:282] != 8'd15 && - inputDataStreamQ_D_OUT[289:282] != 8'd175 && - inputDataStreamQ_D_OUT[289:282] != 8'd16 && - inputDataStreamQ_D_OUT[289:282] != 8'd176 && - inputDataStreamQ_D_OUT[289:282] != 8'd17 && - inputDataStreamQ_D_OUT[289:282] != 8'd177 && - inputDataStreamQ_D_OUT[289:282] != 8'd18 && - inputDataStreamQ_D_OUT[289:282] != 8'd178 && - inputDataStreamQ_D_OUT[289:282] != 8'd160 && - inputDataStreamQ_D_OUT[289:282] != 8'd161 && - inputDataStreamQ_D_OUT[289:282] != 8'd162 && - inputDataStreamQ_D_OUT[289:282] != 8'd163 && - inputDataStreamQ_D_OUT[289:282] != 8'd164 && - inputDataStreamQ_D_OUT[289:282] != 8'd165 && - inputDataStreamQ_D_OUT[289:282] != 8'd166 && - inputDataStreamQ_D_OUT[289:282] != 8'd167 && - inputDataStreamQ_D_OUT[289:282] != 8'd168 && - inputDataStreamQ_D_OUT[289:282] != 8'd169 && - inputDataStreamQ_D_OUT[289:282] != 8'd170 && - inputDataStreamQ_D_OUT[289:282] != 8'd171 && - inputDataStreamQ_D_OUT[289:282] != 8'd172 && - inputDataStreamQ_D_OUT[289:282] != 8'd179 && - inputDataStreamQ_D_OUT[289:282] != 8'd180 && - inputDataStreamQ_D_OUT[289:282] != 8'd182 && - inputDataStreamQ_D_OUT[289:282] != 8'd183 && - inputDataStreamQ_D_OUT[289:282] != 8'd100 && - inputDataStreamQ_D_OUT[289:282] != 8'd101 && - inputDataStreamQ_D_OUT[289:282] != 8'd129) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10] == - 7'd0) - begin - v__h17340 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10] == - 7'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h17340, - "\"ExtractAndPrependPipeOut.bsv\", line 480, column 13\n", - "headerMetaData.headerLen non-zero assertion @ mkExtractHeaderFromDataStreamPipeOut"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10] == - 7'd0 && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[1]) - $display("headerMetaData.headerLen=%h should not be zero, headerMetaData=", - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10], - "HeaderMetaData { headerLen=%0d, headerFragNum=%0d, lastFragValidByteNum=%0d, hasPayload=", - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10], - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[9:8], - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[7:2], - "True", - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10] == - 7'd0 && - !headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[1]) - $display("headerMetaData.headerLen=%h should not be zero, headerMetaData=", - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10], - "HeaderMetaData { headerLen=%0d, headerFragNum=%0d, lastFragValidByteNum=%0d, hasPayload=", - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10], - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[9:8], - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[7:2], - "False", - " }"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_popHeaderMetaData && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataInQ_D_OUT[16:10] == - 7'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0]) && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[0]) - begin - v__h31186 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0]) && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[0]) - $display("time=%0t: InputRdmaPktBuf preCheckHeader", - v__h31186, - ", discard invalid RDMA packet of single-fragment payload"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0]) && - !pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[0]) - begin - v__h31150 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader && - pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[1] && - (!pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[2] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[1] || - !pktMetaDataAndPayloadPipeOutVec_rdmaHeaderRecvQ_D_OUT[0]) && - !pktMetaDataAndPayloadPipeOutVec_payloadRecvQ_D_OUT[0]) - $display("time=%0t: InputRdmaPktBuf preCheckHeader", - v__h31150, - ", discard invalid RDMA packet of multi-fragment payload"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag && - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader && - pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv[290] && - _write_RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader_EN_pktMetaDataAndPayloadPipeOutVec_pktBufStateReg_wget) - $display("Error: \"InputPktHandle.bsv\", line 461, column 10: (R0002)\n Conflict-free rules RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag\n and RL_pktMetaDataAndPayloadPipeOutVec_preCheckHeader called conflicting\n methods read and write of module instance\n pktMetaDataAndPayloadPipeOutVec_pktBufStateReg.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag && - WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag) - $display("Error: \"InputPktHandle.bsv\", line 461, column 10: (R0002)\n Conflict-free rules RL_pktMetaDataAndPayloadPipeOutVec_discardInvalidFrag\n and RL_pktMetaDataAndPayloadPipeOutVec_recvPktFrag called conflicting\n methods port0__read and port0__write of module instance\n pktMetaDataAndPayloadPipeOutVec_payloadPipeIn_fifof_rv.\n"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp && - qpMetaData_qpTagVec_respSuccessReg && - !qpMetaData_qpTagVec_maybeInsertIdxReg) - begin - v__h8367 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp && - qpMetaData_qpTagVec_respSuccessReg && - !qpMetaData_qpTagVec_maybeInsertIdxReg) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h8367, - "\"MetaData.bsv\", line 113, column 17\n", - "maybeInsertIdxReg assertion @ mkTagVecSrv"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp && - qpMetaData_qpTagVec_respSuccessReg && - !qpMetaData_qpTagVec_maybeInsertIdxReg) - $display("maybeInsertIdxReg="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp && - qpMetaData_qpTagVec_respSuccessReg && - !qpMetaData_qpTagVec_maybeInsertIdxReg) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp && - qpMetaData_qpTagVec_respSuccessReg && - !qpMetaData_qpTagVec_maybeInsertIdxReg) - $display(" should be valid"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_qpMetaData_qpTagVec_genInsertResp && - qpMetaData_qpTagVec_respSuccessReg && - !qpMetaData_qpTagVec_maybeInsertIdxReg) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen && - rightAlignedByteEn__h33653 != 32'hFFFFFFFF && - rightAlignedByteEn__h33653 != 32'd268435455 && - rightAlignedByteEn__h33653 != 32'd16777215 && - rightAlignedByteEn__h33653 != 32'd1048575 && - rightAlignedByteEn__h33653 != 32'd65535 && - rightAlignedByteEn__h33653 != 32'd4095 && - rightAlignedByteEn__h33653 != 32'd255 && - rightAlignedByteEn__h33653 != 32'd15 && - rightAlignedByteEn__h33653 != 32'd0) - begin - v__h36179 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen && - rightAlignedByteEn__h33653 != 32'hFFFFFFFF && - rightAlignedByteEn__h33653 != 32'd268435455 && - rightAlignedByteEn__h33653 != 32'd16777215 && - rightAlignedByteEn__h33653 != 32'd1048575 && - rightAlignedByteEn__h33653 != 32'd65535 && - rightAlignedByteEn__h33653 != 32'd4095 && - rightAlignedByteEn__h33653 != 32'd255 && - rightAlignedByteEn__h33653 != 32'd15 && - rightAlignedByteEn__h33653 != 32'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h36179, - "\"InputPktHandle.bsv\", line 661, column 13\n", - "isValid(payloadFragLen) assertion @ mkInputRdmaPktBufAndHeaderValidation"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen && - rightAlignedByteEn__h33653 != 32'hFFFFFFFF && - rightAlignedByteEn__h33653 != 32'd268435455 && - rightAlignedByteEn__h33653 != 32'd16777215 && - rightAlignedByteEn__h33653 != 32'd1048575 && - rightAlignedByteEn__h33653 != 32'd65535 && - rightAlignedByteEn__h33653 != 32'd4095 && - rightAlignedByteEn__h33653 != 32'd255 && - rightAlignedByteEn__h33653 != 32'd15 && - rightAlignedByteEn__h33653 != 32'd0) - $display("payloadFragLen="); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen && - rightAlignedByteEn__h33653 != 32'hFFFFFFFF && - rightAlignedByteEn__h33653 != 32'd268435455 && - rightAlignedByteEn__h33653 != 32'd16777215 && - rightAlignedByteEn__h33653 != 32'd1048575 && - rightAlignedByteEn__h33653 != 32'd65535 && - rightAlignedByteEn__h33653 != 32'd4095 && - rightAlignedByteEn__h33653 != 32'd255 && - rightAlignedByteEn__h33653 != 32'd15 && - rightAlignedByteEn__h33653 != 32'd0) - $display("tagged Invalid ", ""); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen && - rightAlignedByteEn__h33653 != 32'hFFFFFFFF && - rightAlignedByteEn__h33653 != 32'd268435455 && - rightAlignedByteEn__h33653 != 32'd16777215 && - rightAlignedByteEn__h33653 != 32'd1048575 && - rightAlignedByteEn__h33653 != 32'd65535 && - rightAlignedByteEn__h33653 != 32'd4095 && - rightAlignedByteEn__h33653 != 32'd255 && - rightAlignedByteEn__h33653 != 32'd15 && - rightAlignedByteEn__h33653 != 32'd0) - $display(" should be valid"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_calcFraglen && - rightAlignedByteEn__h33653 != 32'hFFFFFFFF && - rightAlignedByteEn__h33653 != 32'd268435455 && - rightAlignedByteEn__h33653 != 32'd16777215 && - rightAlignedByteEn__h33653 != 32'd1048575 && - rightAlignedByteEn__h33653 != 32'd65535 && - rightAlignedByteEn__h33653 != 32'd4095 && - rightAlignedByteEn__h33653 != 32'd255 && - rightAlignedByteEn__h33653 != 32'd15 && - rightAlignedByteEn__h33653 != 32'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2]) - begin - v__h38749 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_checkPktLen && - pktMetaDataAndPayloadPipeOutVec_payloadPktLenCheckQ_D_OUT[1] && - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPktLenCheckQ_D_OUT[2]) - $display("time=%0t: InputRdmaPktBuf checkPktLen", - v__h38749, - ", discard zero-length payload for RDMA packet"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv[16:10] == - 7'd0) - begin - v__h26277 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv[16:10] == - 7'd0) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h26277, - "\"ExtractAndPrependPipeOut.bsv\", line 145, column 13\n", - "headerMetaData.headerLen non-zero assertion @ mkDataStream2Header"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv[16:10] == - 7'd0) - $display("headerMetaData.headerLen=%h should not be zero", - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv[16:10]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_popHeaderMetaData && - headerAndMetaDataAndPayloadPipeOut_headerMetaDataPipeOut_fifof_rv[16:10] == - 7'd0) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - headerLastFragByteEn__h26468 != - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[33:2]) - begin - v__h29124 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - headerLastFragByteEn__h26468 != - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[33:2]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h29124, - "\"ExtractAndPrependPipeOut.bsv\", line 198, column 17\n", - "headerLastFragByteEn assertion @ mkDataStream2Header"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - headerLastFragByteEn__h26468 != - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[33:2]) - $display("headerLastFragByteEn=%h should == curDataStreamFrag.byteEn=%h, headerLen=%0d", - headerLastFragByteEn__h26468, - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[33:2], - _theResult___headerMetaData_headerLen__h26602); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - headerLastFragByteEn__h26468 != - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[33:2]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - _theResult___headerMetaData_headerFragNum__h26603 != - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg[9:8]) - begin - v__h29221 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - _theResult___headerMetaData_headerFragNum__h26603 != - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg[9:8]) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h29221, - "\"ExtractAndPrependPipeOut.bsv\", line 206, column 17\n", - "headerMetaData.headerFragNum assertion @ mkDataStream2Header"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - _theResult___headerMetaData_headerFragNum__h26603 != - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg[9:8]) - $display("rdmaHeader.headerMetaData.headerFragNum=%h should == headerMetaDataReg.headerFragNum=%h when curDataStreamFrag.isLast=%b", - _theResult___headerMetaData_headerFragNum__h26603, - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg[9:8], - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - _theResult___headerMetaData_headerFragNum__h26603 != - pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_headerMetaDataReg[9:8]) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - (NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1518 || - NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1549)) - begin - v__h29617 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - (NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1518 || - NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1549)) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h29617, - "\"ExtractAndPrependPipeOut.bsv\", line 216, column 17\n", - "curDataStreamFrag.byteEn assertion @ mkDataStream2Header"); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - (NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1518 || - NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1549)) - $display("curDataStreamFrag.byteEn=%h should be all ones", - headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[33:2]); - if (RST_N != `BSV_RESET_VALUE) - if (WILL_FIRE_RL_pktMetaDataAndPayloadPipeOutVec_rdmaHeaderPipeOut_accumulate && - !headerAndMetaDataAndPayloadPipeOut_headerAndPayloadPipeOut_headerDataStreamOutQ_D_OUT[0] && - (NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1518 || - NOT_headerAndMetaDataAndPayloadPipeOut_headerA_ETC___d1549)) - $finish(32'd1); - if (RST_N != `BSV_RESET_VALUE) - if (pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_EMPTY_N) - begin - v__h40540 = $time; - #0; - end - if (RST_N != `BSV_RESET_VALUE) - if (pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_EMPTY_N) - $display("ImmAssert failed in %m @time=%0t: %s-- %s: ", - v__h40540, - "\"TransportLayer.bsv\", line 182, column 13\n", - "pktMetaDataAndPayloadPipeOutVec[0].cnpPipeOut empty assertion @ mkTransportLayerRDMA"); - if (RST_N != `BSV_RESET_VALUE) - if (pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_EMPTY_N) - $display("inputPipeOut.notEmpty="); - if (RST_N != `BSV_RESET_VALUE) - if (pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_EMPTY_N) - $display("True"); - if (RST_N != `BSV_RESET_VALUE) - if (pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_EMPTY_N) - $display(" should be empty"); - if (RST_N != `BSV_RESET_VALUE) - if (pktMetaDataAndPayloadPipeOutVec_cnpOutVec_0_EMPTY_N) $finish(32'd1); - end - // synopsys translate_on -endmodule // mkTransportLayer - From 88b1c4768f7d0aede051d13a3d84050187b9e087 Mon Sep 17 00:00:00 2001 From: Filippo Marini <58254029+FilMarini@users.noreply.github.com> Date: Thu, 9 Jul 2026 10:56:21 +0200 Subject: [PATCH 3/8] Remove blue-rdma library loading from ruckus.tcl Removed loading of blue-rdma library from the script. --- ethernet/RoCEv2/ruckus.tcl | 1 - 1 file changed, 1 deletion(-) diff --git a/ethernet/RoCEv2/ruckus.tcl b/ethernet/RoCEv2/ruckus.tcl index 174b123244..0cfbc0c112 100644 --- a/ethernet/RoCEv2/ruckus.tcl +++ b/ethernet/RoCEv2/ruckus.tcl @@ -4,7 +4,6 @@ source $::env(RUCKUS_PROC_TCL) # Load Source Code loadSource -lib surf -dir "$::DIR_PATH/rtl" loadSource -lib surf -dir "$::DIR_PATH/blue-crc" -loadSource -lib surf -dir "$::DIR_PATH/blue-rdma" loadSource -lib surf -dir "$::DIR_PATH/blue-lib" # Load mem files From 3796058eb3a97b1847bbf1817cb6c77273b5af5a Mon Sep 17 00:00:00 2001 From: FilMarini Date: Thu, 9 Jul 2026 11:12:13 +0200 Subject: [PATCH 4/8] fix re-transmission bug --- ethernet/RoCEv2/rtl/CountCF.vhd | 211 ++++++++------------------- ethernet/RoCEv2/rtl/RespHandleSq.vhd | 32 +++- ethernet/RoCEv2/rtl/ScanFifoF.vhd | 101 +++++++++---- ethernet/RoCEv2/rtl/SqQueuePair.vhd | 159 +++++++++++++++++++- 4 files changed, 317 insertions(+), 186 deletions(-) diff --git a/ethernet/RoCEv2/rtl/CountCF.vhd b/ethernet/RoCEv2/rtl/CountCF.vhd index 5f5753361f..71b7252823 100644 --- a/ethernet/RoCEv2/rtl/CountCF.vhd +++ b/ethernet/RoCEv2/rtl/CountCF.vhd @@ -2,37 +2,37 @@ -- Company : SLAC National Accelerator Laboratory ------------------------------------------------------------------------------- -- Description: --- Conflict-free up/down counter. incrOne()/decrOne() each enqueue a "tick" --- into a small FIFO; every cycle the counter applies the net delta --- (+1 / -1 / 0) of whichever ticks are pending, and _write() overrides the --- count and atomically clears both FIFOs. +-- Conflict-free up/down counter. incrOne()/decrOne() each set a one-cycle +-- registered "tick"; every cycle the counter applies the net delta +-- (+1 / -1 / 0) of the ticks captured on the previous cycle, and _write() +-- overrides the count and discards any pending ticks. -- --- There is no enumerated control FSM (single implied state OPER_S). The only --- true registered state is cntReg. The BSV CReg(2) scratch registers --- (writeReg/incrReg/decrReg) are pure intra-cycle forwarding signals and --- collapse to combinational logic here — see OQ-FSM-02. +-- Cycle accuracy vs BSV mkCountCF (PrimUtils.bsv:276-332): an incrOne() +-- issued in cycle n is visible on _read() in cycle n+2, exactly as in BSV +-- (enq cycle n -> increment rule deqs and CReg-forwards cycle n+1 -> cntReg +-- updated edge n+1 -> readable n+2). _write() lands on the same edge it is +-- issued (BSV writeReg CReg port-0 -> write rule same cycle) and discards +-- both in-flight and same-cycle ticks (BSV: increment/decrement rules are +-- guarded off and both queues cleared). -- --- SURF components instantiated: --- * U_IncrQ : surf.Fifo <- BSV incrQ (mkFIFOF FIFOF#(Bool), 1-bit) --- * U_DecrQ : surf.Fifo <- BSV decrQ (mkFIFOF FIFOF#(Bool), 1-bit) --- source: surf/base/fifo/rtl/Fifo.vhd +-- BUGFIX 2026-07-08 (OQ-FSM-03 class): the previous implementation queued +-- ticks through surf.Fifo instances, whose FWFT read path adds several +-- cycles of latency before a tick reaches cntReg. Guards written against +-- the BSV one-tick-in-flight margin (e.g. NewPendingWorkReqPipeOut's +-- "pendingCnt < getPendingWorkReqNum - 1", QueuePair.bsv:105) then act on a +-- stale count: a back-to-back 50-WR burst overshot MAX_QP_WR by ~5 and +-- flooded the "pendingCnt > MAX_QP_WR" assertion. BSV mkFIFOF ticks never +-- buffer more than one entry (the apply rules drain every cycle), so the +-- FIFOs are pure scheduling artifacts and collapse to single registered +-- tick flags — restoring the exact BSV visibility latency. -- --- BSV FIFOF.clear has NO equivalent SURF Fifo flush port (OQ-FSM-01, --- RESOLVED). It is modelled by pulsing the synchronous Fifo rst for one cycle --- on BOTH FIFOs in parallel (fifoRst = global rst OR clrStrobe), with --- GEN_SYNC_FIFO_G => true, RST_ASYNC_G => false, RST_POLARITY_G => '1'. On the --- clock edge the FifoSync FSM restores REG_INIT_C, zeroing the pointers in one --- cycle — the BSV single-cycle, two-queue atomic clear. +-- The BSV CReg(2) scratch registers (writeReg/incrReg/decrReg) are pure +-- intra-cycle forwarding signals and collapse to combinational logic here — +-- see OQ-FSM-02. -- --- Clear-vs-enq ordering (OQ-FSM-01 open follow-up): BSV mkFIFOF schedules --- clear AFTER enq, so when _write fires in the same cycle as incrOne/decrOne --- the queue ends EMPTY (the enq is discarded). Here wr_en is left ungated: --- when fifoRst asserts, FifoSync's synchronous reset dominates the concurrent --- wr_en, dropping the write and emptying the FIFO — matching BSV. (Confirm in --- cocotb.) --- --- NOTE: emitting does not prove equivalence — simulate this entity (cocotb) --- before trusting it. +-- No SURF components instantiated (tick FIFOs removed, see BUGFIX above). +-- FIFO_ADDR_WIDTH_G is retained for port/generic compatibility with +-- existing instantiations but is no longer used. ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -57,17 +57,17 @@ entity CountCF is RST_ASYNC_G : boolean := false; WIDTH_G : positive := 8; -- count width = tSz of BSV anytype RESET_VAL_G : slv := "00000000"; -- BSV mkCountCF 'resetVal' parameter (length must = WIDTH_G) - FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- tick FIFO depth = 2**ADDR (BSV mkFIFOF depth 2; SURF min 4) + FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4); -- UNUSED (legacy, kept for instantiation compatibility) port ( clk : in sl; rst : in sl := not RST_POLARITY_G; - -- incrOne() method : enq a +1 tick (ready = incrQ not full) + -- incrOne() method : register a +1 tick (always ready, see header) incrOneEn : in sl; incrOneRdy : out sl; - -- decrOne() method : enq a -1 tick (ready = decrQ not full) + -- decrOne() method : register a -1 tick (always ready, see header) decrOneEn : in sl; decrOneRdy : out sl; - -- _write() method : override count and clear both tick FIFOs + -- _write() method : override count and discard pending ticks writeEn : in sl; writeVal : in slv(WIDTH_G-1 downto 0); -- _read() method : current count (Moore, registered) @@ -76,148 +76,61 @@ end CountCF; architecture rtl of CountCF is - -- Only true registered state is the count (BSV cntReg <- mkReg(resetVal)). + -- Registered state: the count (BSV cntReg <- mkReg(resetVal)) plus one + -- pending-tick flag per direction (BSV incrQ/decrQ head, never deeper + -- than one entry — see header). type RegType is record - cntReg : slv(WIDTH_G-1 downto 0); + cntReg : slv(WIDTH_G-1 downto 0); + incrPend : sl; + decrPend : sl; end record RegType; constant REG_INIT_C : RegType := ( - cntReg => RESET_VAL_G); + cntReg => RESET_VAL_G, + incrPend => '0', + decrPend => '0'); signal r : RegType := REG_INIT_C; signal rin : RegType; - -- Tick FIFO payload is a constant 'True' (BSV enq(True)); only presence matters. - constant TICK_DIN_C : slv(0 downto 0) := "1"; - - -- SURF Fifo handshake/status (FWFT: valid = head present = BSV notEmpty) - signal incrValid : sl; - signal decrValid : sl; - signal incrNotFull : sl; - signal decrNotFull : sl; - signal incrDout : slv(0 downto 0); - signal decrDout : slv(0 downto 0); - - -- Mealy combinational outputs (BSV rule firing this cycle) - signal incrRdEn : sl; -- U_IncrQ.rd_en (increment rule deq) - signal decrRdEn : sl; -- U_DecrQ.rd_en (decrement rule deq) - - -- Atomic clear of both FIFOs (BSV write rule: incrQ.clear; decrQ.clear) - signal clrStrobe : sl; -- 1-cycle pulse when _write fires - signal rstActiveHigh : sl; -- global rst normalised to active high - signal fifoRst : sl; -- driven into both Fifo rst ports - begin -- Elaboration sanity check: the reset value must be WIDTH_G bits wide. assert (RESET_VAL_G'length = WIDTH_G) report "CountCF: RESET_VAL_G length must equal WIDTH_G" severity failure; - -- Method-readiness (implicit conditions) exposed as explicit ready outputs. - incrOneRdy <= incrNotFull; -- incrOne implicit cond: incrQ not full - decrOneRdy <= decrNotFull; -- decrOne implicit cond: decrQ not full - - -------------------------------------------------------------------------- - -- Atomic clear strobe (OQ-FSM-01): _write fires same-cycle as the BSV CReg - -- writeReg forwards _write -> write rule. fifoRst pulses both FIFOs' rst. - -------------------------------------------------------------------------- - clrStrobe <= writeEn; - rstActiveHigh <= rst when (RST_POLARITY_G = '1') else not rst; - fifoRst <= rstActiveHigh or clrStrobe; - - -------------------------------------------------------------------------- - -- BSV incrQ (mkFIFOF FIFOF#(Bool)) -> surf.Fifo - -- wr_en <- incrOneEn (incrOne method enq True); ungated so a same-cycle - -- clear (fifoRst) dominates the write, matching BSV clear-after-enq. - -------------------------------------------------------------------------- - U_IncrQ : entity surf.Fifo - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => '1', -- clear strobe is active high (OQ-FSM-01) - RST_ASYNC_G => false, -- synchronous one-cycle clear (OQ-FSM-01) - GEN_SYNC_FIFO_G => true, -- must stay sync for one-cycle clear (OQ-FSM-01) - FWFT_EN_G => true, -- valid = head present = BSV notEmpty - MEMORY_TYPE_G => "distributed", -- LUTRAM read path (FifoRdFsm 1-cycle - -- branch). BRAM ("block") adds a DOB_REG - -- stage -> 2-cycle RAM read, inflating - -- enq->valid by one extra cycle. Distributed - -- is the correct primitive for a depth-2, - -- 1-bit tick FIFO and removes that stage. - -- NOTE: even distributed leaves a ~1-cycle - -- read-latency gap vs BSV mkFIFOF, inherent - -- to surf.Fifo's sync write-ptr -> read-FSM - -- handshake. Functionally equivalent; NOT - -- cycle-accurate to BSV. (OQ-FSM-03) - DATA_WIDTH_G => 1, - ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) - port map ( - rst => fifoRst, - wr_clk => clk, - wr_en => incrOneEn, - din => TICK_DIN_C, - not_full => incrNotFull, - rd_clk => clk, - rd_en => incrRdEn, - dout => incrDout, - valid => incrValid); - - -------------------------------------------------------------------------- - -- BSV decrQ (mkFIFOF FIFOF#(Bool)) -> surf.Fifo - -------------------------------------------------------------------------- - U_DecrQ : entity surf.Fifo - generic map ( - TPD_G => TPD_G, - RST_POLARITY_G => '1', - RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, - FWFT_EN_G => true, - MEMORY_TYPE_G => "distributed", -- LUTRAM: 1-cycle read latency (see U_IncrQ) - DATA_WIDTH_G => 1, - ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) - port map ( - rst => fifoRst, - wr_clk => clk, - wr_en => decrOneEn, - din => TICK_DIN_C, - not_full => decrNotFull, - rd_clk => clk, - rd_en => decrRdEn, - dout => decrDout, - valid => decrValid); + -- Method-readiness: the tick flags are consumed every cycle, so the BSV + -- implicit conditions (incrQ/decrQ notFull) can never block. + incrOneRdy <= '1'; + decrOneRdy <= '1'; -------------------------------------------------------------------------- -- Combinatorial : per-cycle priority action table (single state OPER_S). - -- priority: write > (net incr/decr delta). See CountCF.fsm.md. + -- priority: write > (net delta of previous-cycle ticks). -------------------------------------------------------------------------- - comb : process (decrValid, incrValid, r, rst, writeEn, writeVal) is - variable v : RegType; - variable incrDeqV : sl; - variable decrDeqV : sl; + comb : process (r, rst, incrOneEn, decrOneEn, writeEn, writeVal) is + variable v : RegType; begin -- Latch the current value v := r; - -- Default Mealy strobes - incrDeqV := '0'; - decrDeqV := '0'; + -- Capture this cycle's method ticks (applied to cntReg next cycle, + -- matching the BSV enq -> deq-and-apply pipeline). + v.incrPend := incrOneEn; + v.decrPend := decrOneEn; - -- increment/decrement rules: gated off while _write fires (writeReg valid). - -- Each deqs its own FIFO independently when that FIFO is non-empty. - if (writeEn = '0') then - incrDeqV := incrValid; - decrDeqV := decrValid; - end if; - - -- cntReg update: write wins; otherwise apply the net +1/-1/0 delta. + -- cntReg update: write wins and discards ticks (BSV write rule clears + -- both queues and gates off the apply rules); otherwise apply the net + -- +1/-1/0 delta of the ticks captured on the previous cycle. if (writeEn = '1') then - v.cntReg := writeVal; - elsif (incrValid = '1') and (decrValid = '0') then + v.cntReg := writeVal; + v.incrPend := '0'; -- same-cycle enq discarded (clear after enq) + v.decrPend := '0'; + elsif (r.incrPend = '1') and (r.decrPend = '0') then v.cntReg := slv(unsigned(r.cntReg) + 1); - elsif (incrValid = '0') and (decrValid = '1') then + elsif (r.incrPend = '0') and (r.decrPend = '1') then v.cntReg := slv(unsigned(r.cntReg) - 1); - else - v.cntReg := r.cntReg; -- both ticks (net 0) or neither - end if; + end if; -- both ticks (net 0) or neither: hold -- Synchronous Reset if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then @@ -227,10 +140,6 @@ begin -- Register the variable for next clock cycle rin <= v; - -- Mealy outputs (combinational FIFO deq strobes) - incrRdEn <= incrDeqV; - decrRdEn <= decrDeqV; - -- Moore output cntOut <= r.cntReg; end process comb; diff --git a/ethernet/RoCEv2/rtl/RespHandleSq.vhd b/ethernet/RoCEv2/rtl/RespHandleSq.vhd index de884f63e2..7110193553 100644 --- a/ethernet/RoCEv2/rtl/RespHandleSq.vhd +++ b/ethernet/RoCEv2/rtl/RespHandleSq.vhd @@ -62,6 +62,13 @@ -- simulation-only and are NOT reproduced here; mkRegU latches zero-initialised; -- permCheckReq.accFlags local-write encoding confirmed against PermCheckSrv; -- the two server in-order/bounded-latency assumptions (OQ-S3-RESP-01). +-- +-- DEVIATION-SQQP-01 (2026-07-08, SQ retry partial-replay fix; see +-- SqQueuePair.vhd header): new input pendingWrDeqAllowed (default '1') +-- restores mkScanFIFOF.deq's implicit condition — no pending-WR pop while +-- the scan buffer is in PRE_SCAN mode. Enforced at the two pop sites +-- (pre-stage DONE commit, errFlushWorkReq); the whole stage stalls, exactly +-- like the guarded BSV rule. ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -101,6 +108,14 @@ entity RespHandleSq is pendingWrValid : in sl; -- notEmpty pendingWrData : in slv(678 downto 0); -- first pendingWrDeq : out sl; -- deq + -- DEVIATION-SQQP-01: deq implicit condition. mkScanFIFOF.deq is guarded + -- (!isEmpty && (inFifoMode || inScanMode)) (SpecialFIFOF.bsv:430): a pop + -- must never land while the buffer is in PRE_SCAN, or it shifts the head + -- under RetryHandleSq's getHead/modifyHead and shrinks the retry + -- snapshot. Drive with (not ScanFifoF.inPreScan); default '1' keeps + -- standalone TBs unchanged. A stage that wants to pop stalls whole + -- (pktMetaDeq + incomingRespQ enq held together) until allowed. + pendingWrDeqAllowed : in sl := '1'; -- pktMetaDataPipeIn : PipeOut#(RdmaPktMetaData) (649b) pktMetaValid : in sl; -- notEmpty pktMetaData : in slv(648 downto 0); -- first @@ -901,6 +916,7 @@ begin --------------------------------------------------------------------------- comb : process (r, rst, isReset, isRTS, isERR, isStableRTS, getPMTU, getSQPN, getNPSN, pendingWrValid, pendingWrData, + pendingWrDeqAllowed, pktMetaValid, pktMetaData, payloadConReqReady, retryResetReady, retryReqReady, retryRespValid, retryRespData, timeOutValid, timeOutData, isRetrying, permReqReady, @@ -1083,8 +1099,13 @@ begin v.preStageState := SQ_PRE_STAGE_DONE_S; ---------------------------------------------------------------- when SQ_PRE_STAGE_DONE_S => - -- deqPktMetaDataOrWorkReq: gated on incomingRespQ room - if (incNotFull = '1') then + -- deqPktMetaDataOrWorkReq: gated on incomingRespQ room. + -- DEVIATION-SQQP-01: a stage that pops the pending WR also + -- requires pendingWrDeqAllowed (BSV deq implicit condition — + -- no pop while the scan buffer is in PRE_SCAN). Non-popping + -- stages (partials, duplicates, retries) proceed unchanged. + if (incNotFull = '1' and + (r.preStageDeqPendingWorkReq = '0' or pendingWrDeqAllowed = '1')) then if r.preStageDeqPktMetaData = '1' then pktMetaDeq <= '1'; end if; if r.preStageDeqPendingWorkReq = '1' then pendingWrDeq <= '1'; end if; incWrEn <= '1'; @@ -1128,7 +1149,12 @@ begin RESET_TIMEOUT_C & WC_NO_C & WRA_DISC_C; end if; -- errFlushWorkReq: err mode, pending WR present - elsif (inErrStateAlt and pendingWrValid = '1' and incNotFull = '1') then + -- (DEVIATION-SQQP-01: same deq implicit condition as the DONE stage; + -- while blocked the errFlushIncomingResp branch below cannot fire + -- either — pendingWrValid='1' — so the flush just stalls, as the + -- blocked BSV rule would.) + elsif (inErrStateAlt and pendingWrValid = '1' and incNotFull = '1' and + pendingWrDeqAllowed = '1') then pendingWrDeq <= '1'; rpi := (others => '0'); rpi(6) := '1'; rpi(5) := '1'; -- isFirstOrOnly/isLastOrOnly diff --git a/ethernet/RoCEv2/rtl/ScanFifoF.vhd b/ethernet/RoCEv2/rtl/ScanFifoF.vhd index 2fee4d3591..8c71a254f5 100644 --- a/ethernet/RoCEv2/rtl/ScanFifoF.vhd +++ b/ethernet/RoCEv2/rtl/ScanFifoF.vhd @@ -65,6 +65,24 @@ -- Initialised to all-'0' in REG_INIT_C; each is always written before it is -- read. Don't-care at reset (mirrors OQ-FSM-04). BSV's scanAlmostDoneReg / -- scanDoneReg pair is superseded by the drain-gated scanDone above. +-- +-- DEVIATION-SQQP-01 (2026-07-08, SQ retry partial-replay fix; see +-- SqQueuePair.vhd header): enqueue is additionally legal during PRE_SCAN_S. +-- BSV forbids it (enq guard = inFifoMode) and instead relies on the NAK +-- round-trip being long enough that no sent WR is still in flight toward +-- this buffer when a retry snapshot is taken — a latent upstream hole (a +-- sent-but-not-yet-enqueued WR misses the scanCnt snapshot and is silently +-- excluded from the go-back-N replay). Here the parent holds the buffer in +-- PRE_SCAN until all in-flight new WRs have landed, so: +-- * the PRE_SCAN snapshot takes the POST-enq item count (v.itemCnt), so +-- an enqueue landing on any pre-scan cycle (including the scanStart +-- release cycle) is inside the replay window; +-- * the enq-mode simulation assert flags SCAN_S only; +-- * a new inPreScan status output lets the parent implement the enq gate +-- (FIFO_S or PRE_SCAN_S) and the deq gate (BSV deq guard forbids +-- PRE_SCAN) without duplicating this FSM's state. +-- deq during PRE_SCAN_S remains illegal (BSV guard: inFifoMode||inScanMode); +-- the parent now enforces it via RespHandleSq.pendingWrDeqAllowed. ------------------------------------------------------------------------------- -- This file is part of the BSV->VHDL transpilation output. It targets the SURF -- VHDL library and follows the SURF coding standard (style/vhdl-style-rules.md). @@ -118,6 +136,7 @@ entity ScanFifoF is preScanRestartEn : in sl; -- preScanRestart() hasScanOut : out sl; -- hasScanOut() isScanDone : out sl; -- isScanDone() + inPreScan : out sl; -- PRE_SCAN_S status (DEVIATION-SQQP-01) -- scan output PipeOut (read side of U_ScanOutQ) scanOutValid : out sl; -- scanOutQ valid scanOutData : out slv(T_SZ_G-1 downto 0); -- scanOutQ dout @@ -345,14 +364,19 @@ begin when PRE_SCAN_S => -- rule preScanMode : snapshot deqPtr->scanPtr, itemCnt->scanCnt; - -- optional transition into SCAN. (enq/deq blocked here by guards.) + -- optional transition into SCAN. (deq blocked here by guards.) -- DEVIATION: scanStop is honoured here too (BSV guards scanStop -- to inScanMode and relies on the caller's implicit conditions -- to defer the whole ERR flush; the port-level VHDL cannot, so -- an abort while pre-scanning must not strand the FSM here — -- otherwise RespHandleSq's ERR flush deqs against PRE_SCAN). + -- DEVIATION-SQQP-01: enq IS legal during PRE_SCAN (see header), + -- so the snapshot takes the post-enq count v.itemCnt — an + -- enqueue landing on the same cycle as scanStart is still + -- inside the replay window. deq stays gated off by the parent, + -- so v.deqPtrReg = r.deqPtrReg here. v.scanPtrReg := r.deqPtrReg; - v.scanCnt := r.itemCnt; + v.scanCnt := v.itemCnt; if (scanStopEn = '1') then v.scanStateReg := FIFO_S; elsif (scanStartEn = '1') then @@ -397,16 +421,6 @@ begin end if; end if; - -- pragma translate_off - -- check rule: dequeue must not overtake the scan pointer, and - -- occupancy must never drop below the remaining scan count. - assert (deqEn = '0') or - (unsigned(r.deqPtrReg) /= unsigned(r.scanPtrReg) + 1) - report "deq overtakes scanPtr @ ScanFifoF" severity error; - assert (unsigned(r.itemCnt) >= unsigned(r.scanCnt)) - report "itemCnt < scanCnt @ ScanFifoF" severity error; - -- pragma translate_on - end case; end if; @@ -434,21 +448,6 @@ begin v.outQOcc := slv(unsigned(r.outQOcc) - 1); end if; - -- pragma translate_off - -- BSV mkScanFIFOF immAsserts guarding the deq/scan interplay: a deq - -- strobe must never coincide with a scan(-re)start or land in PRE_SCAN. - -- Any violation here means the PARENT is producing the spurious pop - -- that unbalances the SQ pending-request counter. - assert not (deqEn = '1' and preScanStartEn = '1') - report "deq coincides with preScanStart @ ScanFifoF" severity error; - assert not (deqEn = '1' and scanStartEn = '1') - report "deq coincides with scanStart @ ScanFifoF" severity error; - assert not (deqEn = '1' and preScanRestartEn = '1') - report "deq coincides with preScanRestart @ ScanFifoF" severity error; - assert not (deqEn = '1' and r.scanStateReg = PRE_SCAN_S) - report "deq while in PRE_SCAN mode @ ScanFifoF" severity error; - -- pragma translate_on - -- Synchronous reset if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then v := REG_INIT_C; @@ -477,6 +476,53 @@ begin end if; end process seq; + ----------------------------------------------------------------------------- + -- Simulation-only protocol checks (BSV mkScanFIFOF immAsserts). + -- CLOCKED on purpose: enqEn/deqEn and the scan strobes are Mealy inputs + -- combinationally derived (in the parent) from this entity's own outputs + -- (isScanDone/inPreScan), so for a few delta cycles after a state edge + -- they hold stale values against the freshly updated r.scanStateReg. An + -- immediate assert in the comb process false-fires on those transients + -- (seen in Questa at the PRE_SCAN->SCAN release edge with a same-cycle + -- legal PRE_SCAN enq). Sampling at rising_edge(clk) checks exactly the + -- settled values the DUT commits. + ----------------------------------------------------------------------------- + -- pragma translate_off + chk : process (clk) is + begin + if rising_edge(clk) and (rst /= RST_POLARITY_G) then + -- a deq strobe must never coincide with a scan(-re)start or land in + -- PRE_SCAN. Any violation here means the PARENT is producing the + -- spurious pop that unbalances the SQ pending-request counter. + assert not (deqEn = '1' and preScanStartEn = '1') + report "deq coincides with preScanStart @ ScanFifoF" severity error; + assert not (deqEn = '1' and scanStartEn = '1') + report "deq coincides with scanStart @ ScanFifoF" severity error; + assert not (deqEn = '1' and preScanRestartEn = '1') + report "deq coincides with preScanRestart @ ScanFifoF" severity error; + assert not (deqEn = '1' and r.scanStateReg = PRE_SCAN_S) + report "deq while in PRE_SCAN mode @ ScanFifoF" severity error; + -- BSV enq implicit condition is (!isFull && inFifoMode) + -- (SpecialFIFOF.bsv:424). DEVIATION-SQQP-01 additionally admits enq + -- during PRE_SCAN (included in the continuous snapshot); an enq + -- landing mid-SCAN still escapes the scan snapshot and is silently + -- excluded from the retry replay (partial go-back-N retransmit) — + -- the caller must gate enq on (isScanDone or inPreScan). + assert not (enqEn = '1' and r.scanStateReg = SCAN_S) + report "enq while in SCAN mode @ ScanFifoF" severity error; + -- while scanning: dequeue must not overtake the scan pointer, and + -- occupancy must never drop below the remaining scan count. + if (r.scanStateReg = SCAN_S) then + assert (deqEn = '0') or + (unsigned(r.deqPtrReg) /= unsigned(r.scanPtrReg) + 1) + report "deq overtakes scanPtr @ ScanFifoF" severity error; + assert (unsigned(r.itemCnt) >= unsigned(r.scanCnt)) + report "itemCnt < scanCnt @ ScanFifoF" severity error; + end if; + end if; + end process chk; + -- pragma translate_on + ----------------------------------------------------------------------------- -- Outputs ----------------------------------------------------------------------------- @@ -488,6 +534,7 @@ begin deqPulse <= deqEn; fifoSize <= r.itemCnt; isScanDone <= '1' when (r.scanStateReg = FIFO_S) else '0'; + inPreScan <= '1' when (r.scanStateReg = PRE_SCAN_S) else '0'; -- Mealy (combinational array reads; BSV first()/getHead() peek semantics) fifoFirst <= r.dataVec(to_integer(unsigned(r.deqPtrReg))); diff --git a/ethernet/RoCEv2/rtl/SqQueuePair.vhd b/ethernet/RoCEv2/rtl/SqQueuePair.vhd index d47f9a38da..591aa0142c 100644 --- a/ethernet/RoCEv2/rtl/SqQueuePair.vhd +++ b/ethernet/RoCEv2/rtl/SqQueuePair.vhd @@ -51,6 +51,40 @@ -- no two-process template), OQ-EMIT-SQQP-02 (contextSQ flattened to a status -- port bundle), OQ-EMIT-SQQP-03 (PipeOutMux dependency now emitted+verified), -- OQ-EMIT-SQQP-04 (level vs pulse clear, inherited from ScanFifoF OQ-FSM-06). +-- +-- DEVIATION-SQQP-01 (2026-07-08): SQ retry partial-replay fix (intentional +-- deviation from upstream blue-rdma; touches ScanFifoF.vhd, RespHandleSq.vhd +-- and this file — grep the tag). +-- Failure (claudeSurf tb, WRITE/CASES_NUM=50/DROP_REQ_PSN=3/MAX_QP_WR=32): +-- a NAK arrived while new WRs were still in flight between the PipeOutMux +-- and the pendingWorkReqBuf enqueue (inside PipeOutMux's output Fifo and +-- ReqGenSq's stage FIFOs — all 16-deep surf.Fifo vs BSV's 2-deep mkFIFOF, +-- which amplifies the upstream hole 8x). Those WRs are PSN-stamped and +-- their packets ARE emitted, but they miss the retry scan's itemCnt +-- snapshot, so the go-back-N replay covered only WR1-24 of 32; the mux then +-- served WR33+ ahead of the never-retried WR25-32 -> second NAK + response +-- timeout (naks=2, retransmits=350, ~105us stall). Root cause: go-back-N +-- correctness requires the replay window to cover every PSN-stamped WR, but +-- the snapshot only covers buffer occupancy. Upstream BSV has the same +-- latent hole; it is NOT closed by gating the enqueue alone (a deferred +-- enqueue misses the snapshot exactly like a mid-scan one). +-- Fix (three parts): +-- 1. an in-flight counter (incr when the mux consumes a NEW WR from +-- NewPendingWorkReqPipeOut, decr on every buffer enqueue) plus a latch +-- that withholds RetryHandleSq's scanStart strobe from ScanFifoF until +-- the counter reaches zero — the buffer waits in PRE_SCAN, whose +-- snapshot re-samples every cycle, so the late WRs are replayed; +-- 2. buffer enqueue admitted during PRE_SCAN as well as FIFO mode +-- (ScanFifoF DEVIATION note; snapshot takes the post-enq count), and +-- still blocked during SCAN (BUGFIX 2026-07-08 below, now relaxed); +-- 3. RespHandleSq.pendingWrDeqAllowed = not inPreScan restores the BSV +-- deq implicit condition, keeping the head stable under +-- getHead/modifyHead across the (now longer) PRE_SCAN window. +-- No deadlock: the drain path (ReqGenSq pipeline -> packet emission -> +-- buffer enqueue) is independent of the stalled response path, and while +-- in-flight WRs exist the NewPending window arithmetic guarantees the +-- buffer is not full (in-flight + occupancy < MAX_QP_WR), so the drain +-- always completes and releases the scan. ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -63,6 +97,7 @@ library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; library surf; use surf.StdRtlPkg.all; @@ -210,6 +245,7 @@ architecture rtl of SqQueuePair is signal scanPreScanRestartEn : sl; signal scanHasScanOut : sl; signal scanIsScanDone : sl; + signal scanInPreScan : sl; signal scanOutValid : sl; signal scanOutData : slv(PENDING_WR_C-1 downto 0); signal scanOutReady : sl; @@ -266,6 +302,28 @@ architecture rtl of SqQueuePair is -- pendingWorkReq2Q connection strobe ----------------------------------------- signal pendingWr2QFire : sl; + ----------------------------------------------------------------------------- + -- DEVIATION-SQQP-01: retry scan-start gate (see header). + -- inFlightNewWr counts NEW WRs consumed from NewPendingWorkReqPipeOut by the + -- mux but not yet enqueued into pendingWorkReqBuf (they sit in PipeOutMux's + -- output Fifo and ReqGenSq's stage FIFOs). Bounded by the NewPending window + -- (< MAX_QP_WR), hence log2(MAX_QP_WR_C)+1 bits. + ----------------------------------------------------------------------------- + type RegType is record + inFlightNewWr : slv(log2(MAX_QP_WR_C) downto 0); + scanStartPend : sl; -- scanStart received, drain not done + end record RegType; + + constant REG_INIT_C : RegType := ( + inFlightNewWr => (others => '0'), + scanStartPend => '0'); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal retryScanStartReq : sl; -- RetryHandleSq's raw scanStart strobe + signal pendingWrDeqAllowed : sl; -- deq implicit condition to RespHandleSq + begin ----------------------------------------------------------------------------- @@ -280,12 +338,99 @@ begin -- pendingWorkReq2Q (mkConnection): reqGenSQ.pendingWorkReqPipeOut (Get) -> -- pendingWorkReqBuf.fifof (Put). One-cycle handshake: enqueue when producer -- valid AND fifof has room; same strobe deqs the producer. + -- BUGFIX 2026-07-08: enq is also gated on the buffer mode. mkScanFIFOF.enq's + -- implicit condition is (!isFull && inFifoMode) (SpecialFIFOF.bsv:424): no + -- enqueue may land while a retry scan is in progress (it would escape the + -- scan snapshot and be excluded from the go-back-N replay). Gating on + -- isScanDone alone did NOT cure the observed partial replay (the deferred + -- enqueue missed the snapshot all the same); DEVIATION-SQQP-01 (see header) + -- additionally admits enqueues during PRE_SCAN — the pre-scan snapshot + -- re-samples every cycle, so those WRs are inside the replay window — and + -- the scan-start gate below holds the buffer in PRE_SCAN until every + -- in-flight new WR has landed. ----------------------------------------------------------------------------- - pendingWr2QFire <= reqGenPendingOutValid and scanFifoNotFull; + pendingWr2QFire <= reqGenPendingOutValid and scanFifoNotFull and + (scanIsScanDone or scanInPreScan); scanEnqEn <= pendingWr2QFire; scanEnqData <= reqGenPendingOutData; reqGenPendingOutRdEn <= pendingWr2QFire; + ----------------------------------------------------------------------------- + -- DEVIATION-SQQP-01: retry scan-start gate (see header). + -- comb/seq pair for {inFlightNewWr, scanStartPend}. RetryHandleSq's + -- scanStart strobe (retryScanStartReq) is forwarded to ScanFifoF only once + -- inFlightNewWr (counted through this cycle's enqueue) is zero; otherwise + -- it is latched in scanStartPend and released when the drain completes. + -- RetryHandleSq meanwhile sits in WAIT_RETRY_DONE polling isScanDone — the + -- deferral is invisible to it. With no WRs in flight (the common case) the + -- strobe passes through combinationally, i.e. zero added latency. + ----------------------------------------------------------------------------- + comb : process (r, rst, isReset, newPendOutValid, newPendOutRdEn, scanEnqEn, + retryScanStartReq, scanStopEn, scanClearEn) is + variable v : RegType; + variable incr : sl; -- mux consumed a NEW WR this cycle + variable decr : sl; -- a new WR landed in the buffer + variable releaseV : sl; -- forward scanStart to ScanFifoF + begin + v := r; + + incr := newPendOutValid and newPendOutRdEn; + decr := scanEnqEn; + + -- Saturating decrement: PipeOutMux's internal output Fifo survives a QP + -- soft reset (faithful to BSV — mkSQ.resetAndClear clears only the scan + -- buffer, not pipeMuxOutQ), so a WR consumed before an isReset (counter + -- cleared) can drain into the buffer after it: a legitimate uncounted + -- enqueue, absorbed here rather than wrapping the counter. + if (incr = '1') and (decr = '0') then + v.inFlightNewWr := slv(unsigned(r.inFlightNewWr) + 1); + elsif (incr = '0') and (decr = '1') and (unsigned(r.inFlightNewWr) /= 0) then + v.inFlightNewWr := slv(unsigned(r.inFlightNewWr) - 1); + end if; + + -- latch the request; release when the drain (incl. this cycle's enq, + -- which the PRE_SCAN snapshot also includes) is complete + if (retryScanStartReq = '1') then + v.scanStartPend := '1'; + end if; + releaseV := '0'; + if ((retryScanStartReq = '1') or (r.scanStartPend = '1')) and + (unsigned(v.inFlightNewWr) = 0) then + releaseV := '1'; + v.scanStartPend := '0'; + end if; + + -- a scan abort / soft clear cancels any pending start; the counter only + -- clears with the QP soft reset (which also clears ReqGenSq's pipeline) + if (isReset = '1') or (scanClearEn = '1') or (scanStopEn = '1') then + v.scanStartPend := '0'; + end if; + if (isReset = '1') then + v.inFlightNewWr := (others => '0'); + end if; + + -- synchronous reset + if (RST_ASYNC_G = false) and (rst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + rin <= v; + + scanStartEn <= releaseV; + end process comb; + + seq : process (clk, rst) is + begin + if (RST_ASYNC_G) and (rst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(clk) then + r <= rin after TPD_G; + end if; + end process seq; + + -- DEVIATION-SQQP-01: BSV deq implicit condition (no pop while PRE_SCAN) + pendingWrDeqAllowed <= not scanInPreScan; + ----------------------------------------------------------------------------- -- U_ScanFifoF : pendingWorkReqBuf (mkScanFIFOF; register-array scan FIFO). -- fifof side : enq from reqGenSQ (above), deq by respHandleSQ (toPipeOut). @@ -325,6 +470,7 @@ begin preScanRestartEn => scanPreScanRestartEn, hasScanOut => scanHasScanOut, isScanDone => scanIsScanDone, + inPreScan => scanInPreScan, -- scanPipeOut scanOutValid => scanOutValid, scanOutData => scanOutData, @@ -358,7 +504,9 @@ begin -- scanCntrl drives scanClear => retryScanClearInt, scanStop => scanStopEn, - scanStart => scanStartEn, + -- DEVIATION-SQQP-01: raw strobe into the scan-start gate, which + -- forwards it to ScanFifoF (scanStartEn) once in-flight WRs drained + scanStart => retryScanStartReq, scanPreScanStart => scanPreScanStartEn, scanPreScanRestart => scanPreScanRestartEn, scanModifyHeadValid => scanModifyHeadEn, @@ -567,9 +715,10 @@ begin getSQPN => sqpn, getNPSN => npsnIn, -- pendingWorkReqPipeIn = toPipeOut(pendingWorkReqBuf.fifof) - pendingWrValid => scanFifoNotEmpty, - pendingWrData => scanFifoFirst, - pendingWrDeq => scanDeqEn, + pendingWrValid => scanFifoNotEmpty, + pendingWrData => scanFifoFirst, + pendingWrDeq => scanDeqEn, + pendingWrDeqAllowed => pendingWrDeqAllowed, -- DEVIATION-SQQP-01 -- pktMetaDataPipeIn = respPktPipeOut.pktMetaData pktMetaValid => respPktMetaValid, pktMetaData => respPktMetaData, From 223620590b4e20a2d39b8d6f521e42f17be58961 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Mon, 13 Jul 2026 14:16:33 +0200 Subject: [PATCH 5/8] fixed some issues --- ethernet/RoCEv2/rtl/RespHandleSq.vhd | 13 +++++++++---- ethernet/RoCEv2/rtl/RetryHandleSq.vhd | 18 ++++++++++-------- ethernet/RoCEv2/rtl/SqQueuePair.vhd | 2 +- 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/ethernet/RoCEv2/rtl/RespHandleSq.vhd b/ethernet/RoCEv2/rtl/RespHandleSq.vhd index 7110193553..3029ae9988 100644 --- a/ethernet/RoCEv2/rtl/RespHandleSq.vhd +++ b/ethernet/RoCEv2/rtl/RespHandleSq.vhd @@ -132,9 +132,9 @@ entity RespHandleSq is retryReqValid : out sl; retryReqData : out slv(96 downto 0); retryReqReady : in sl; - -- retryHandler.srvPort.response : Get#(RetryResp) (1b) + -- retryHandler.srvPort.response : Get#(RetryResp) (2b) retryRespValid : in sl; - retryRespData : in sl; -- RETRY_LIMIT_EXC='1' + retryRespData : in slv(1 downto 0); -- bit0: RETRY_LIMIT_EXC='1'; bit1: reason was RNR retryRespGetEn : out sl; -- retryHandler.notifyTimeOut2SQ : Get#(TimeOutNotification) (1b) timeOutValid : in sl; @@ -277,6 +277,7 @@ architecture rtl of RespHandleSq is constant WCS_REM_ACC_C : slv(4 downto 0) := "01010"; -- 10 constant WCS_REM_OP_C : slv(4 downto 0) := "01011"; -- 11 constant WCS_RETRY_EXC_C : slv(4 downto 0) := "01100"; -- 12 + constant WCS_RNR_RETRY_EXC_C : slv(4 downto 0) := "01101"; -- 13 constant WCS_REM_INV_RD_C : slv(4 downto 0) := "01111"; -- 15 constant WCS_RESP_TMOUT_C : slv(4 downto 0) := "10100"; -- 20 -- RdmaOpCode (5b) — relevant codes @@ -1360,8 +1361,12 @@ begin mWcStat := '1' & WCS_WR_FLUSH_C; when ACT_EXP_RETRY_C | ACT_IMP_RETRY_C => retryRespGetEn <= '1'; - if retryRespData = '1' then -- RETRY_LIMIT_EXC - mWcStat := '1' & WCS_RETRY_EXC_C; + if retryRespData(0) = '1' then -- RETRY_LIMIT_EXC + if retryRespData(1) = '1' then -- RNR exhaustion + mWcStat := '1' & WCS_RNR_RETRY_EXC_C; + else + mWcStat := '1' & WCS_RETRY_EXC_C; + end if; wcReq := WC_PART_C; rpi(0) := '1'; end if; diff --git a/ethernet/RoCEv2/rtl/RetryHandleSq.vhd b/ethernet/RoCEv2/rtl/RetryHandleSq.vhd index 0cf87f1fb8..b0bdf36e9b 100644 --- a/ethernet/RoCEv2/rtl/RetryHandleSq.vhd +++ b/ethernet/RoCEv2/rtl/RetryHandleSq.vhd @@ -135,9 +135,9 @@ entity RetryHandleSq is srvReqValid : in sl; srvReqData : in slv(96 downto 0); srvReqReady : out sl; -- retryReqQ.notFull - -- srvPort.response : Get#(RetryResp) (1b) + -- srvPort.response : Get#(RetryResp) (2b) srvRespValid : out sl; -- notEmpty - srvRespData : out sl; -- 0=RECV_RETRY_REQ, 1=RETRY_LIMIT_EXC + srvRespData : out slv(1 downto 0); -- bit0: 0=RECV_RETRY_REQ, 1=RETRY_LIMIT_EXC; bit1: reason was RNR srvRespGetEn : in sl); -- external deq end entity RetryHandleSq; @@ -165,7 +165,8 @@ architecture rtl of RetryHandleSq is -- TimeOutNotification (1b): TIMEOUT_RETRY=0, TIMEOUT_ERR=1 constant TIMEOUT_RETRY_C : sl := '0'; constant TIMEOUT_ERR_C : sl := '1'; - -- RetryResp (1b): RECV_RETRY_REQ=0, RETRY_LIMIT_EXC=1 + -- RetryResp (2b): bit0 RECV_RETRY_REQ=0 / RETRY_LIMIT_EXC=1; + -- bit1 = reason was RNR (qualifier, meaningful when bit0='1') constant RECV_RETRY_REQ_C : sl := '0'; constant RETRY_LIMIT_EXC_C : sl := '1'; @@ -250,7 +251,7 @@ architecture rtl of RetryHandleSq is signal xrqDin, xrqDout : slv(96 downto 0); -- retryRespQ (1b) signal rsqWrEn, rsqRdEn, rsqValid, rsqNotFull : sl; - signal rsqDin, rsqDout : slv(0 downto 0); + signal rsqDin, rsqDout : slv(1 downto 0); -- resetTimeOutQ (1b) signal rtqWrEn, rtqRdEn, rtqValid, rtqNotFull : sl; signal rtqDin, rtqDout : slv(0 downto 0); @@ -394,7 +395,7 @@ begin tnqRdEn <= timeOutNotifGetEn; -- srvPort.response : Get#(RetryResp) srvRespValid <= rsqValid; - srvRespData <= rsqDout(0); + srvRespData <= rsqDout; rsqRdEn <= srvRespGetEn; --------------------------------------------------------------------------- @@ -462,7 +463,7 @@ begin GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", - DATA_WIDTH_G => 1, + DATA_WIDTH_G => 2, ADDR_WIDTH_G => 4) port map ( rst => fifoClr, wr_clk => clk, wr_en => rsqWrEn, din => rsqDin, @@ -757,8 +758,9 @@ begin if (rsqNotFull = '1') then prqRdEn <= '1'; rsqWrEn <= '1'; - if (prqDout(3) = '1') then rsqDin <= (0 => RETRY_LIMIT_EXC_C); - else rsqDin <= (0 => RECV_RETRY_REQ_C); end if; + if (prqDout(3) = '1') then rsqDin(0) <= RETRY_LIMIT_EXC_C; + else rsqDin(0) <= RECV_RETRY_REQ_C; end if; + if (reason = RR_RNR_C) then rsqDin(1) <= '1'; end if; -- RNR qualifier end if; end if; end if; diff --git a/ethernet/RoCEv2/rtl/SqQueuePair.vhd b/ethernet/RoCEv2/rtl/SqQueuePair.vhd index 591aa0142c..c35a0a469b 100644 --- a/ethernet/RoCEv2/rtl/SqQueuePair.vhd +++ b/ethernet/RoCEv2/rtl/SqQueuePair.vhd @@ -265,7 +265,7 @@ architecture rtl of SqQueuePair is signal retrySrvReqData : slv(96 downto 0); signal retrySrvReqReady : sl; signal retrySrvRespValid : sl; - signal retrySrvRespData : sl; + signal retrySrvRespData : slv(1 downto 0); signal retrySrvRespGetEn : sl; -- U_NewPending (newPendingWorkReqPiptOut) ------------------------------------ From c84e787f17e0c241ff471a5ae98aa656a6bab2e1 Mon Sep 17 00:00:00 2001 From: FilMarini Date: Tue, 14 Jul 2026 15:17:02 +0200 Subject: [PATCH 6/8] optimizing resource usage --- ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd | 10 +- ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd | 16 +- ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd | 8 +- ethernet/RoCEv2/rtl/CacheFifo.vhd | 4 +- ethernet/RoCEv2/rtl/CntrlQp.vhd | 10 +- .../RoCEv2/rtl/CombineHeaderAndPayload.vhd | 2 +- .../rtl/ConnectBramQ2PipeOutConAndGen.vhd | 4 +- .../RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd | 4 +- .../rtl/ConnectPipeOut2BramQConAndGen.vhd | 4 +- .../RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd | 4 +- ethernet/RoCEv2/rtl/DataStream2Header.vhd | 6 +- ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd | 50 ++- ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd | 6 +- ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd | 10 +- ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd | 2 +- .../ExtractHeaderFromDataStreamPipeOut.vhd | 4 +- .../rtl/ExtractHeaderFromRdmaPktPipeOut.vhd | 2 +- ethernet/RoCEv2/rtl/Header2DataStream.vhd | 6 +- .../InputRdmaPktBufAndHeaderValidation.vhd | 44 +-- ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd | 8 +- ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd | 8 +- ethernet/RoCEv2/rtl/MetaDataSrv.vhd | 4 +- .../RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd | 4 +- .../RoCEv2/rtl/PayloadConsumerConAndGen.vhd | 2 +- .../RoCEv2/rtl/PayloadGeneratorConAndGen.vhd | 10 +- ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd | 30 +- ethernet/RoCEv2/rtl/PermCheckSrv.vhd | 6 +- ethernet/RoCEv2/rtl/PipeOutMux.vhd | 4 +- ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd | 4 +- ethernet/RoCEv2/rtl/Qp.vhd | 24 +- .../rtl/RdmaPktMetaDataAndPayloadPipe.vhd | 4 +- ethernet/RoCEv2/rtl/ReqGenSq.vhd | 24 +- ethernet/RoCEv2/rtl/ReqHandleRq.vhd | 129 ++++--- ethernet/RoCEv2/rtl/RespHandleSq.vhd | 26 +- ethernet/RoCEv2/rtl/RetryHandleSq.vhd | 22 +- ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd | 15 +- ethernet/RoCEv2/rtl/Rq.vhd | 9 +- ethernet/RoCEv2/rtl/SendQ.vhd | 14 +- ethernet/RoCEv2/rtl/ServerProxy.vhd | 2 +- ethernet/RoCEv2/rtl/SqQueuePair.vhd | 11 +- ethernet/RoCEv2/rtl/SqSendQ.vhd | 4 +- ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd | 359 ------------------ ethernet/RoCEv2/rtl/TransportLayer.vhd | 21 +- ethernet/RoCEv2/rtl/WorkCompGenRq.vhd | 10 +- ethernet/RoCEv2/rtl/WorkCompGenSq.vhd | 8 +- .../rtl/WorkReqAndRecvReqDispatcher.vhd | 4 +- 46 files changed, 350 insertions(+), 612 deletions(-) delete mode 100644 ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd diff --git a/ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd b/ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd index a86cc11511..7aaaa757e8 100644 --- a/ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd +++ b/ethernet/RoCEv2/rtl/AddrChunkSrvConAndGen.vhd @@ -42,11 +42,11 @@ -- RST_POLARITY_G='1'. -- -- SURF components instantiated: --- U_ReqQ : surf.Fifo DATA_WIDTH_G=99, FWFT, sync, block RAM +-- U_ReqQ : surf.Fifo DATA_WIDTH_G=99, FWFT, sync, distributed RAM -- (AddrChunkReq; source: surf/base/fifo/rtl/Fifo.vhd) --- U_RespQ : surf.Fifo DATA_WIDTH_G=79, FWFT, sync, block RAM +-- U_RespQ : surf.Fifo DATA_WIDTH_G=79, FWFT, sync, distributed RAM -- (AddrChunkResp; source: surf/base/fifo/rtl/Fifo.vhd) --- Block RAM FWFT cold latency is 2 cycles (DOB reg) — see tb-spec §8. +-- Distributed-RAM FWFT cold latency is 1 cycle (block RAM was 2) — see tb-spec §8. -- -- AddrChunkReq bit layout (BSV deriving(Bits), first-field-at-MSB): -- [98:35] startAddr[63:0] (64 bits) @@ -170,7 +170,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 99, ADDR_WIDTH_G => 4) port map ( @@ -207,7 +207,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 79, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd b/ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd index 91e50ed63e..125fd96ebf 100644 --- a/ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd +++ b/ethernet/RoCEv2/rtl/AddrChunkSrvGen.vhd @@ -44,7 +44,7 @@ -- (level-safe); no pulse generator. Requires GEN_SYNC_FIFO_G=true, -- RST_ASYNC_G=false, RST_POLARITY_G='1'. -- --- SURF components instantiated (all surf.Fifo, FWFT, sync, block RAM; +-- SURF components instantiated (all surf.Fifo, FWFT, sync, distributed RAM; -- source: surf/base/fifo/rtl/Fifo.vhd): -- U_ReqQ DATA_WIDTH_G=101 depth 16 (AddrChunkReq; MAX_SGE buf) -- U_RespQ DATA_WIDTH_G=81 (AddrChunkResp) @@ -52,7 +52,7 @@ -- U_CalcChunkMetaDataQ DATA_WIDTH_G=255 (internal pipeline handoff, Stage A->B) -- U_CalcPktMetaDataQ4SGE DATA_WIDTH_G=215 (internal pipeline handoff, Stage B->C) -- U_CalcAddrChunkRespQ DATA_WIDTH_G=197 (internal pipeline handoff, Stage C->D) --- Block RAM FWFT cold latency is 2 cycles (DOB reg) — see tb-spec §8. +-- Distributed-RAM FWFT cold latency is 1 cycle (block RAM was 2) — see tb-spec §8. -- -- Struct bit layouts (BSV deriving(Bits), first-field-at-MSB, OQ-FSM-H2DS-04): -- @@ -224,7 +224,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 101, ADDR_WIDTH_G => 4) port map ( @@ -259,7 +259,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 255, ADDR_WIDTH_G => 4) port map ( @@ -294,7 +294,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 215, ADDR_WIDTH_G => 4) port map ( @@ -330,7 +330,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 197, ADDR_WIDTH_G => 4) port map ( @@ -366,7 +366,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 54, ADDR_WIDTH_G => 4) port map ( @@ -402,7 +402,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 81, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd b/ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd index 7f3b4f7aa0..3ef0af4c84 100644 --- a/ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd +++ b/ethernet/RoCEv2/rtl/AdjustPayloadSegment.vhd @@ -310,7 +310,7 @@ begin -- U_PayloadFragShiftQ : surf.Fifo -- Internal pipeline FIFO; produced by adjustFirstOrMidPkt / -- adjustLastOrOnlyPkt, consumed by shiftPayloadFrag. - -- DATA_WIDTH_G=628, FWFT, sync, block RAM (wide word). + -- DATA_WIDTH_G=628, FWFT, sync, distributed RAM (wide word). --------------------------------------------------------------------------- U_PayloadFragShiftQ : entity surf.Fifo generic map ( @@ -319,7 +319,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 628, ADDR_WIDTH_G => 4) port map ( @@ -347,7 +347,7 @@ begin --------------------------------------------------------------------------- -- U_PktPayloadOutQ : surf.Fifo -- Output queue; its read side IS the returned PipeOut#(DataStream). - -- Produced by shiftPayloadFrag. DATA_WIDTH_G=290, FWFT, sync, block RAM. + -- Produced by shiftPayloadFrag. DATA_WIDTH_G=290, FWFT, sync, distributed RAM. --------------------------------------------------------------------------- U_PktPayloadOutQ : entity surf.Fifo generic map ( @@ -356,7 +356,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 290, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/CacheFifo.vhd b/ethernet/RoCEv2/rtl/CacheFifo.vhd index 575c914fef..96feffb4c7 100644 --- a/ethernet/RoCEv2/rtl/CacheFifo.vhd +++ b/ethernet/RoCEv2/rtl/CacheFifo.vhd @@ -63,7 +63,7 @@ entity CacheFifoRead is generic ( TPD_G : time := 1 ns; FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; - MEM_TYPE_G : string := "block"); + MEM_TYPE_G : string := "distributed"); port ( clk : in sl; rst : in sl; -- active-high synchronous @@ -532,7 +532,7 @@ entity CacheFifoAtomic is generic ( TPD_G : time := 1 ns; FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; - MEM_TYPE_G : string := "block"); + MEM_TYPE_G : string := "distributed"); port ( clk : in sl; rst : in sl; -- active-high synchronous diff --git a/ethernet/RoCEv2/rtl/CntrlQp.vhd b/ethernet/RoCEv2/rtl/CntrlQp.vhd index eede1aab14..a688ddd724 100644 --- a/ethernet/RoCEv2/rtl/CntrlQp.vhd +++ b/ethernet/RoCEv2/rtl/CntrlQp.vhd @@ -55,7 +55,8 @@ use surf.StdRtlPkg.all; entity CntrlQp is generic ( - TPD_G : time := 1 ns); + TPD_G : time := 1 ns; + MAX_QP_WR_G : positive := 4); -- Settings.bsv MAX_QP_WR (BSV default 32) port ( -- Clock and synchronous active-high reset clk : in sl; @@ -199,8 +200,8 @@ architecture rtl of CntrlQp is -- RdmaOpCode SEND_ONLY = 5'h04 (preReqOpCode reset) constant SEND_ONLY_C : slv(4 downto 0) := "00100"; - -- MAX_QP_WR = 32 (pendingWorkReqNum/pendingRecvReqNum reset) - constant MAX_QP_WR_C : slv(7 downto 0) := toSlv(32, 8); + -- MAX_QP_WR (pendingWorkReqNum/pendingRecvReqNum reset) + constant MAX_QP_WR_C : slv(7 downto 0) := toSlv(MAX_QP_WR_G, 8); --------------------------------------------------------------------------- -- containFlags(mask, required) == (mask and required) = required @@ -465,6 +466,9 @@ begin respQWrEn <= '0'; restoreQRdEn <= '0'; + -- No rule fires in states without an active on* rule (SQE/UNKNOWN) + fireV := '0'; + -- Request field views (ReqQP packed) reqType := reqQDout(300 downto 299); reqQpState := reqQDout(216 downto 213); -- qpAttr.qpState (target state) diff --git a/ethernet/RoCEv2/rtl/CombineHeaderAndPayload.vhd b/ethernet/RoCEv2/rtl/CombineHeaderAndPayload.vhd index 357189c742..57213ed9ef 100644 --- a/ethernet/RoCEv2/rtl/CombineHeaderAndPayload.vhd +++ b/ethernet/RoCEv2/rtl/CombineHeaderAndPayload.vhd @@ -199,7 +199,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_WIDTH_C, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutConAndGen.vhd b/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutConAndGen.vhd index f78945ff23..aaafe59b57 100644 --- a/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutConAndGen.vhd +++ b/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutConAndGen.vhd @@ -46,7 +46,7 @@ -- ("backfill the ConAndGen siblings"), this entity uses DATA_WIDTH_G=290. -- -- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): --- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, block RAM +-- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, distributed RAM -- (BSV postBramQ <- mkFIFOF). ADDR_WIDTH_G=4 (surf.Fifo min; -- the BSV 2-deep skid maps to depth-16 — extra buffering only, -- functionally equivalent for a skid stage). @@ -138,7 +138,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DATA_W_G, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd b/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd index b77286963f..dfd8d7a330 100644 --- a/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd +++ b/ethernet/RoCEv2/rtl/ConnectBramQ2PipeOutGen.vhd @@ -52,7 +52,7 @@ -- ("backfill the siblings"), this entity uses DATA_W_G=290. -- -- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): --- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, block RAM +-- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, distributed RAM -- (BSV postBramQ <- mkFIFOF). ADDR_WIDTH_G=4 (surf.Fifo min; -- the BSV 2-deep skid maps to depth-16 — extra buffering only, -- functionally equivalent for a skid stage). @@ -144,7 +144,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DATA_W_G, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQConAndGen.vhd b/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQConAndGen.vhd index fb02e0858f..d577b5f36e 100644 --- a/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQConAndGen.vhd +++ b/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQConAndGen.vhd @@ -62,7 +62,7 @@ -- -- SURF components instantiated (source: -- surf-catalogue-prj/surf/base/fifo/rtl/Fifo.vhd): --- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, block RAM +-- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, distributed RAM -- (BSV postBramQ <- mkFIFOF). ADDR_WIDTH_G=4 (surf.Fifo min; -- the BSV 2-deep skid maps to depth-16 — extra buffering only, -- functionally equivalent for a skid stage). @@ -170,7 +170,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DATA_W_G, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd b/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd index 5751746b82..98afde1812 100644 --- a/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd +++ b/ethernet/RoCEv2/rtl/ConnectPipeOut2BramQGen.vhd @@ -65,7 +65,7 @@ -- -- SURF components instantiated (source: -- surf-catalogue-prj/surf/base/fifo/rtl/Fifo.vhd): --- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, block RAM +-- U_PostBramQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, distributed RAM -- (BSV postBramQ <- mkFIFOF). ADDR_WIDTH_G=4 (surf.Fifo min; -- the BSV 2-deep skid maps to depth-16 — extra buffering only, -- functionally equivalent for a skid stage). @@ -173,7 +173,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DATA_W_G, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/DataStream2Header.vhd b/ethernet/RoCEv2/rtl/DataStream2Header.vhd index 0463c9073b..6b6adbfebd 100644 --- a/ethernet/RoCEv2/rtl/DataStream2Header.vhd +++ b/ethernet/RoCEv2/rtl/DataStream2Header.vhd @@ -51,7 +51,7 @@ -- -- SURF components instantiated: -- U_HeaderOutQ : surf.Fifo --- DATA_WIDTH_G=593, FWFT, sync, block RAM (wide word; 2-cycle cold +-- DATA_WIDTH_G=593, FWFT, sync, distributed RAM (wide word; 1-cycle cold -- latency, DOB reg) — source: surf/base/fifo/rtl/Fifo.vhd -- -- Scheduling / atomicity (fsm.md §scheduling): @@ -152,7 +152,7 @@ begin --------------------------------------------------------------------------- -- U_HeaderOutQ : surf.Fifo -- Holds completed HeaderRDMA words; its read side IS the returned - -- PipeOut#(HeaderRDMA) interface. DATA_WIDTH_G=593, FWFT, sync, block RAM. + -- PipeOut#(HeaderRDMA) interface. DATA_WIDTH_G=593, FWFT, sync, distributed RAM. -- rst wired directly (no software clear in this module). --------------------------------------------------------------------------- U_HeaderOutQ : entity surf.Fifo @@ -162,7 +162,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 593, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd b/ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd index 4297f4a3cb..85e1ea3616 100644 --- a/ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd +++ b/ethernet/RoCEv2/rtl/DmaReadCntrlConAndGen.vhd @@ -14,7 +14,9 @@ -- {cancel, gracefulStop} (fsm.md §State register): -- RUN_S = {cancel=0} — recvReq/issueDmaReq/recvDmaResp active -- CANCELLING_S = {cancel=1,grStop=0} — recvReq/issueDmaReq blocked; recvDmaResp --- keeps draining; await respQ + pendingRead empty +-- keeps draining; respQ autonomously +-- discarded (R5, DEVIATION-DRC-01); +-- await respQ + pendingRead empty -- STOPPED_S = {cancel=1,grStop=1} — quiesced; isIdle() true -- {cancel=0,gracefulStop=1} is unreachable. Emitted as two boolean RegType -- fields, not an enum. @@ -45,6 +47,14 @@ -- setGracefulStop(R4)— CANCELLING_S (cancel && !gracefulStop); latches -- gracefulStop:='1' once BOTH U_RespQ and -- U_PendingDmaReadReqQ are empty (no in-flight responses). +-- drainRespQ (R5) — CANCELLING_S/STOPPED_S; DEVIATION-DRC-01 (no BSV +-- counterpart): discard one U_RespQ entry per cycle and +-- suppress respOutValid so the stalled caller cannot +-- race the pop. Without it, an error landing +-- mid-retransmission strands respQ (the caller's +-- payload-gen path stops consuming outside stable RTS) +-- and R4 never latches — QP DESTROY liveness hang +-- (see qp-destroy-hang-issue.md). -- dmaCntrl.cancel()(M0)— Action pulse cancelEn -> cancel:='1' (CReg port0, -- same-cycle forwarded into the R1/R2/R4 guards) and -- re-arms gracefulStop:='0' (port0). @@ -123,11 +133,11 @@ -- [78:15] chunkAddr(64) [14:2] chunkLen(13) [1] isFirst [0] isLast -- -- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): --- U_ReqQ : surf.Fifo DATA_WIDTH_G=198, FWFT, sync, block RAM +-- U_ReqQ : surf.Fifo DATA_WIDTH_G=198, FWFT, sync, distributed RAM -- (DmaReadCntrlReq; BSV mkFIFOF reqQ) --- U_RespQ : surf.Fifo DATA_WIDTH_G=385, FWFT, sync, block RAM +-- U_RespQ : surf.Fifo DATA_WIDTH_G=385, FWFT, sync, distributed RAM -- (DmaReadCntrlResp; BSV mkFIFOF respQ) --- U_PendingDmaCntrlReqQ : surf.Fifo DATA_WIDTH_G=198, FWFT, sync, block RAM +-- U_PendingDmaCntrlReqQ : surf.Fifo DATA_WIDTH_G=198, FWFT, sync, distributed RAM -- (DmaReadCntrlReq; BSV mkFIFOF pendingDmaCntrlReqQ) -- U_PendingDmaReadReqQ : surf.Fifo DATA_WIDTH_G=178, FWFT, sync, distributed RAM -- (Tuple3; BSV mkFIFOF pendingDmaReadReqQ). Distributed @@ -215,6 +225,7 @@ architecture rtl of DmaReadCntrlConAndGen is signal respQValid : sl; -- = respQ.notEmpty signal respQWrEn : sl; signal respQDin : slv(384 downto 0); + signal respQRdEn : sl; -- caller pop OR cancel drain (DEVIATION-DRC-01) -- U_PendingDmaCntrlReqQ interface signals (DmaReadCntrlReq, 198b) signal pendCntrlNotFull : sl; @@ -250,7 +261,11 @@ begin -- srvPort boundary wiring (pass-through; not FSM-gated) reqInReady <= reqQNotFull; -- reqQ.notFull readiness to caller - respOutValid <= respQValid; -- respQ.notEmpty to caller + -- DEVIATION-DRC-01: responses are withheld from the caller while cancelling + -- (registered cancel, Moore) — the R5 drain owns the respQ read side from + -- the cycle after cancelEn; the caller only asserts respOutReady when it + -- sees respOutValid, so there is no double-pop window. + respOutValid <= respQValid and not r.cancel; -- isIdle() method (Moore): registered gracefulStop (CReg port0 read of the -- REGISTERED value). Drive from r, NOT v. @@ -268,7 +283,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 198, ADDR_WIDTH_G => 4) port map ( @@ -305,7 +320,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 385, ADDR_WIDTH_G => 4) port map ( @@ -321,7 +336,7 @@ begin almost_full => open, wr_data_count => open, rd_clk => clk, - rd_en => respOutReady, -- pass-through (caller drives) + rd_en => respQRdEn, -- FSM: caller pop / cancel drain (DEVIATION-DRC-01) dout => respOutData, valid => respQValid, underflow => open, @@ -343,7 +358,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 198, ADDR_WIDTH_G => 4) port map ( @@ -440,7 +455,7 @@ begin --------------------------------------------------------------------------- comb : process (r, rst, clearAll, cancelEn, reqQValid, reqQDout, - respQNotFull, respQValid, + respQNotFull, respQValid, respOutReady, pendCntrlNotFull, pendCntrlValid, pendCntrlDout, pendReadNotFull, pendReadValid, pendReadDout, childReqPutReady, childRespQValid, childRespQDout, @@ -503,6 +518,7 @@ begin reqQRdEn <= '0'; respQWrEn <= '0'; respQDin <= dmaRespIn & isOrigFirst & isOrigLast; -- 383+1+1=385 + respQRdEn <= respOutReady; -- srvPort.response.get pass-through (RUN_S) pendCntrlWrEn <= '0'; pendCntrlDin <= reqQDout; -- enq whole 198-bit request (R1) pendCntrlRdEn <= '0'; @@ -575,6 +591,20 @@ begin else -- cancel = '1' (CANCELLING_S / STOPPED_S). R1/R2 blocked. + -- R5 drainRespQ (DEVIATION-DRC-01, 2026-07-13): autonomously discard + -- stranded DmaReadCntrlResps while cancelling. Upstream blue-rdma + -- waits for the caller to drain respQ, but the caller (payload + -- generator -> header generation) stops consuming once the QP + -- leaves stable RTS; an error landing mid-retransmission (e.g. + -- RNR-retry exhaustion) strands respQ and R4 never latches — QP + -- DESTROY liveness hang (see qp-destroy-hang-issue.md). Gated on + -- the REGISTERED cancel so the cancelEn transition cycle keeps a + -- single respQ reader (respOutValid is suppressed off r.cancel + -- the same cycle this rule arms). R3 keeps running so remaining + -- external DMA responses still retire pendingRead tokens. + if (r.cancel = '1' and respQValid = '1') then + respQRdEn <= '1'; + end if; -- R4 setGracefulStop: latch once both the response queue and the -- pending-read queue have drained (no in-flight responses). Reads -- v.gracefulStop (post-port0; cancel() may have re-armed it to '0'). diff --git a/ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd b/ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd index ebb03eea64..2c32d09308 100644 --- a/ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd +++ b/ethernet/RoCEv2/rtl/DmaReadCntrlGen.vhd @@ -316,7 +316,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1163, ADDR_WIDTH_G => 4) port map ( @@ -342,7 +342,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 385, ADDR_WIDTH_G => 4) port map ( @@ -396,7 +396,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 133, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd b/ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd index 7a1a84195d..56c948165f 100644 --- a/ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd +++ b/ethernet/RoCEv2/rtl/DmaWriteCntrl.vhd @@ -69,13 +69,13 @@ -- (mapping.new_ports=[] is incomplete); enumerated below. -- -- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): --- U_ReqQ : surf.Fifo DATA_WIDTH_G=419, FWFT, sync, block RAM +-- U_ReqQ : surf.Fifo DATA_WIDTH_G=419, FWFT, sync, distributed RAM -- (DmaWriteReq; BSV mkFIFOF reqQ) --- U_RespQ : surf.Fifo DATA_WIDTH_G=53, FWFT, sync, block RAM +-- U_RespQ : surf.Fifo DATA_WIDTH_G=53, FWFT, sync, distributed RAM -- (DmaWriteResp; BSV mkFIFOF respQ) -- U_HasPendQ : surf.Fifo DATA_WIDTH_G=1, FWFT, sync, distributed RAM -- (Bool token; BSV mkFIFOF hasPendingReqQ) --- Block-RAM FWFT cold latency is 2 cycles (DOB reg); the 1-bit token queue +-- Distributed-RAM FWFT cold latency is 1 cycle (block RAM was 2); the 1-bit token queue -- uses distributed RAM (1-cycle FWFT) so its notEmpty tracks the BSV -- enq->notEmpty timing the R4 guard relies on — see tb-spec §8. -- @@ -205,7 +205,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 419, ADDR_WIDTH_G => 4) port map ( @@ -242,7 +242,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 53, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd b/ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd index 7045374151..a7bdb0b758 100644 --- a/ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd +++ b/ethernet/RoCEv2/rtl/DupReadAtomicCache.vhd @@ -68,7 +68,7 @@ entity DupReadAtomicCache is generic ( TPD_G : time := 1 ns; FIFO_ADDR_WIDTH_G : positive range 4 to 48 := 4; -- children + own FIFO depth = 2**N - MEM_TYPE_G : string := "block"); + MEM_TYPE_G : string := "distributed"); port ( clk : in sl; rst : in sl; -- active-high synchronous diff --git a/ethernet/RoCEv2/rtl/ExtractHeaderFromDataStreamPipeOut.vhd b/ethernet/RoCEv2/rtl/ExtractHeaderFromDataStreamPipeOut.vhd index 85adf8730c..aa76d52d3e 100644 --- a/ethernet/RoCEv2/rtl/ExtractHeaderFromDataStreamPipeOut.vhd +++ b/ethernet/RoCEv2/rtl/ExtractHeaderFromDataStreamPipeOut.vhd @@ -233,7 +233,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_WIDTH_C, ADDR_WIDTH_G => 4) port map ( @@ -270,7 +270,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_WIDTH_C, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/ExtractHeaderFromRdmaPktPipeOut.vhd b/ethernet/RoCEv2/rtl/ExtractHeaderFromRdmaPktPipeOut.vhd index 8b89d17636..ef06ee8576 100644 --- a/ethernet/RoCEv2/rtl/ExtractHeaderFromRdmaPktPipeOut.vhd +++ b/ethernet/RoCEv2/rtl/ExtractHeaderFromRdmaPktPipeOut.vhd @@ -304,7 +304,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_WIDTH_C, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/Header2DataStream.vhd b/ethernet/RoCEv2/rtl/Header2DataStream.vhd index a6ac4c2073..ac3a247727 100644 --- a/ethernet/RoCEv2/rtl/Header2DataStream.vhd +++ b/ethernet/RoCEv2/rtl/Header2DataStream.vhd @@ -26,7 +26,7 @@ -- -- SURF components instantiated: -- U_HdrDataStreamQ : surf.Fifo --- DATA_WIDTH_G=290, FWFT, sync, block RAM (2-cycle cold latency, DOB reg) +-- DATA_WIDTH_G=290, FWFT, sync, distributed RAM (1-cycle cold latency) -- source: surf/base/fifo/rtl/Fifo.vhd -- U_HdrMetaDataQ : surf.Fifo -- DATA_WIDTH_G=17, FWFT, sync, distributed RAM (1-cycle cold latency) @@ -147,7 +147,7 @@ begin --------------------------------------------------------------------------- -- U_HdrDataStreamQ : surf.Fifo -- Carries DataStream flits to the headerDataStream output interface. - -- DATA_WIDTH_G=290 (256+32+1+1), FWFT, sync, block RAM. + -- DATA_WIDTH_G=290 (256+32+1+1), FWFT, sync, distributed RAM. --------------------------------------------------------------------------- U_HdrDataStreamQ : entity surf.Fifo generic map ( @@ -156,7 +156,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 290, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/InputRdmaPktBufAndHeaderValidation.vhd b/ethernet/RoCEv2/rtl/InputRdmaPktBufAndHeaderValidation.vhd index 8c7103f734..281940b02c 100644 --- a/ethernet/RoCEv2/rtl/InputRdmaPktBufAndHeaderValidation.vhd +++ b/ethernet/RoCEv2/rtl/InputRdmaPktBufAndHeaderValidation.vhd @@ -709,7 +709,7 @@ begin --------------------------------------------------------------------------- U_RdmaHeaderRecvQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => RECV_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderRecvQWrEn, din => rdmaHeaderRecvQDin, not_full => rdmaHeaderRecvQNotFull, full => open, wr_ack => open, overflow => open, @@ -720,7 +720,7 @@ begin U_PayloadRecvQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => payloadRecvQWrEn, din => payloadRecvQDin, not_full => payloadRecvQNotFull, full => open, wr_ack => open, overflow => open, @@ -731,7 +731,7 @@ begin U_RdmaHeaderPreCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PRECHK_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderPreCheckQWrEn, din => rdmaHeaderPreCheckQDin, not_full => rdmaHeaderPreCheckQNotFull, full => open, wr_ack => open, overflow => open, @@ -742,7 +742,7 @@ begin U_PayloadPreCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => payloadPreCheckQWrEn, din => payloadPreCheckQDin, not_full => payloadPreCheckQNotFull, full => open, wr_ack => open, overflow => open, @@ -753,7 +753,7 @@ begin U_RdmaHeaderValidationQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => VALID_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderValidationQWrEn, din => rdmaHeaderValidationQDin, not_full => rdmaHeaderValidationQNotFull, full => open, wr_ack => open, overflow => open, @@ -764,7 +764,7 @@ begin U_PayloadValidationQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => payloadValidationQWrEn, din => payloadValidationQDin, not_full => payloadValidationQNotFull, full => open, wr_ack => open, overflow => open, @@ -775,7 +775,7 @@ begin U_RdmaHeaderFilterQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => FILT_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderFilterQWrEn, din => rdmaHeaderFilterQDin, not_full => rdmaHeaderFilterQNotFull, full => open, wr_ack => open, overflow => open, @@ -786,7 +786,7 @@ begin U_PayloadFilterQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => payloadFilterQWrEn, din => payloadFilterQDin, not_full => payloadFilterQNotFull, full => open, wr_ack => open, overflow => open, @@ -797,7 +797,7 @@ begin U_RdmaHeaderFragLenCalcQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => FILT_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderFragLenCalcQWrEn, din => rdmaHeaderFragLenCalcQDin, not_full => rdmaHeaderFragLenCalcQNotFull, full => open, wr_ack => open, overflow => open, @@ -808,7 +808,7 @@ begin U_PayloadFragLenCalcQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => payloadFragLenCalcQWrEn, din => payloadFragLenCalcQDin, not_full => payloadFragLenCalcQNotFull, full => open, wr_ack => open, overflow => open, @@ -819,7 +819,7 @@ begin U_RdmaHeaderPktLenCalcQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => FILT_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderPktLenCalcQWrEn, din => rdmaHeaderPktLenCalcQDin, not_full => rdmaHeaderPktLenCalcQNotFull, full => open, wr_ack => open, overflow => open, @@ -830,7 +830,7 @@ begin U_PayloadPktLenCalcQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PLC_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => payloadPktLenCalcQWrEn, din => payloadPktLenCalcQDin, not_full => payloadPktLenCalcQNotFull, full => open, wr_ack => open, overflow => open, @@ -841,7 +841,7 @@ begin U_RdmaHeaderPktLenPreCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PLCI_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderPktLenPreCheckQWrEn, din => rdmaHeaderPktLenPreCheckQDin, not_full => rdmaHeaderPktLenPreCheckQNotFull, full => open, wr_ack => open, overflow => open, @@ -852,7 +852,7 @@ begin U_PayloadPktLenPreCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PL3_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => payloadPktLenPreCheckQWrEn, din => payloadPktLenPreCheckQDin, not_full => payloadPktLenPreCheckQNotFull, full => open, wr_ack => open, overflow => open, @@ -863,7 +863,7 @@ begin U_RdmaHeaderPktLenCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PCHK4_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderPktLenCheckQWrEn, din => rdmaHeaderPktLenCheckQDin, not_full => rdmaHeaderPktLenCheckQNotFull, full => open, wr_ack => open, overflow => open, @@ -874,7 +874,7 @@ begin U_PayloadPktLenCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PL3_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => payloadPktLenCheckQWrEn, din => payloadPktLenCheckQDin, not_full => payloadPktLenCheckQNotFull, full => open, wr_ack => open, overflow => open, @@ -885,7 +885,7 @@ begin U_RdmaHeaderOutputQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => HDROUT_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => rdmaHeaderOutputQWrEn, din => rdmaHeaderOutputQDin, not_full => rdmaHeaderOutputQNotFull, full => open, wr_ack => open, overflow => open, @@ -896,7 +896,7 @@ begin U_PayloadOutputQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PL3_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => payloadOutputQWrEn, din => payloadOutputQDin, not_full => payloadOutputQNotFull, full => open, wr_ack => open, overflow => open, @@ -949,7 +949,7 @@ begin GEN_REQ_FIFOS : if EN_RX_G generate U_ReqPayloadOutVec : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => reqPayloadWrEnA(i), din => reqPayloadDinA(i), not_full => reqPayloadNotFullA(i), full => open, wr_ack => open, overflow => open, @@ -960,7 +960,7 @@ begin U_ReqPktMetaDataOutVec : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => META_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => reqMetaWrEnA(i), din => reqMetaDinA(i), not_full => reqMetaNotFullA(i), full => open, wr_ack => open, overflow => open, @@ -985,7 +985,7 @@ begin GEN_RESP_FIFOS : if EN_TX_G generate U_RespPayloadOutVec : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => respPayloadWrEnA(i), din => respPayloadDinA(i), not_full => respPayloadNotFullA(i), full => open, wr_ack => open, overflow => open, @@ -996,7 +996,7 @@ begin U_RespPktMetaDataOutVec : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => META_W_C, ADDR_WIDTH_G => ADDR_W_C) port map (rst => rst, wr_clk => clk, wr_en => respMetaWrEnA(i), din => respMetaDinA(i), not_full => respMetaNotFullA(i), full => open, wr_ack => open, overflow => open, diff --git a/ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd b/ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd index 7a919b1783..0bc7266b04 100644 --- a/ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd +++ b/ethernet/RoCEv2/rtl/MergePayloadAllSge.vhd @@ -349,7 +349,7 @@ begin -- U_PayloadFragShiftQ : surf.Fifo -- Internal pipeline FIFO; produced by mergeFirstOrMidSGE / -- mergeLastOrOnlySGE (Stage B), consumed by shiftPayloadFrag (Stage C). - -- DATA_WIDTH_G=595, FWFT, sync, block RAM (wide word). + -- DATA_WIDTH_G=595, FWFT, sync, distributed RAM (wide word). --------------------------------------------------------------------------- U_PayloadFragShiftQ : entity surf.Fifo generic map ( @@ -358,7 +358,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 595, ADDR_WIDTH_G => 4) port map ( @@ -387,7 +387,7 @@ begin -- U_PktPayloadOutQ : surf.Fifo -- Output queue; its read side IS the returned PipeOut#(DataStream). -- Produced by shiftPayloadFrag (Stage C). DATA_WIDTH_G=290, FWFT, sync, - -- block RAM. + -- distributed RAM. --------------------------------------------------------------------------- U_PktPayloadOutQ : entity surf.Fifo generic map ( @@ -396,7 +396,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 290, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd b/ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd index baa0a54fe9..ab5992b438 100644 --- a/ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd +++ b/ethernet/RoCEv2/rtl/MergePayloadEachSge.vhd @@ -294,7 +294,7 @@ begin -- U_PayloadFragShiftQ : surf.Fifo -- Internal pipeline FIFO; produced by mergeFirstOrMidPktSGE / -- mergeLastOrOnlyPktSGE, consumed by shiftPayloadFrag. - -- DATA_WIDTH_G=595, FWFT, sync, block RAM (wide word). + -- DATA_WIDTH_G=595, FWFT, sync, distributed RAM (wide word). --------------------------------------------------------------------------- U_PayloadFragShiftQ : entity surf.Fifo generic map ( @@ -303,7 +303,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 595, ADDR_WIDTH_G => 4) port map ( @@ -331,7 +331,7 @@ begin --------------------------------------------------------------------------- -- U_PktPayloadOutQ : surf.Fifo -- Output queue; its read side IS the returned PipeOut#(DataStream). - -- Produced by shiftPayloadFrag. DATA_WIDTH_G=290, FWFT, sync, block RAM. + -- Produced by shiftPayloadFrag. DATA_WIDTH_G=290, FWFT, sync, distributed RAM. --------------------------------------------------------------------------- U_PktPayloadOutQ : entity surf.Fifo generic map ( @@ -340,7 +340,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 290, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/MetaDataSrv.vhd b/ethernet/RoCEv2/rtl/MetaDataSrv.vhd index 434a457dd8..9a2026faea 100644 --- a/ethernet/RoCEv2/rtl/MetaDataSrv.vhd +++ b/ethernet/RoCEv2/rtl/MetaDataSrv.vhd @@ -207,7 +207,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => MD_REQ_W_C, ADDR_WIDTH_G => 4) port map ( @@ -243,7 +243,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => MD_RESP_W_C, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd b/ethernet/RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd index f4cb5d2a10..b4b89fc121 100644 --- a/ethernet/RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd +++ b/ethernet/RoCEv2/rtl/NewPendingWorkReqPipeOut.vhd @@ -21,7 +21,7 @@ -- The comb process drives sub-instance control ports only. -- -- SURF components instantiated: --- U_OutQ : surf.Fifo (DATA_WIDTH_G=679, FWFT, sync, block RAM) +-- U_OutQ : surf.Fifo (DATA_WIDTH_G=679, FWFT, sync, distributed RAM) -- source: surf/base/fifo/rtl/Fifo.vhd -- -- Project entities instantiated: @@ -144,7 +144,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 679, ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) port map ( diff --git a/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd b/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd index 7ca08eb4f8..e7485ec21c 100644 --- a/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd +++ b/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd @@ -421,7 +421,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 493, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/PayloadGeneratorConAndGen.vhd b/ethernet/RoCEv2/rtl/PayloadGeneratorConAndGen.vhd index 82ab850052..524e949387 100644 --- a/ethernet/RoCEv2/rtl/PayloadGeneratorConAndGen.vhd +++ b/ethernet/RoCEv2/rtl/PayloadGeneratorConAndGen.vhd @@ -84,11 +84,11 @@ -- (data=[291:36], byteEn=[35:4], isFirst=[3], isLast=[2]), isOrigLast=[0] -- -- SURF components instantiated (source: surf/base/fifo/rtl/Fifo.vhd): --- U_PayloadGenReqQ : surf.Fifo DATA_WIDTH_G=199, FWFT, sync, block RAM +-- U_PayloadGenReqQ : surf.Fifo DATA_WIDTH_G=199, FWFT, sync, distributed RAM -- (BSV payloadGenReqQ <- mkFIFOF) -- U_PayloadGenRespQ : surf.Fifo DATA_WIDTH_G=2, FWFT, sync, distributed RAM -- (BSV payloadGenRespQ <- mkFIFOF) --- U_PendingGenReqQ : surf.Fifo DATA_WIDTH_G=239, FWFT, sync, block RAM +-- U_PendingGenReqQ : surf.Fifo DATA_WIDTH_G=239, FWFT, sync, distributed RAM -- (BSV pendingGenReqQ <- mkFIFOF — pipeline FIFO) -- U_PayloadBufQ : surf.Fifo DATA_WIDTH_G=290, FWFT, sync, block RAM, -- ADDR_WIDTH_G=8 (depth 256 = DATA_STREAM_FRAG_BUF_SIZE = @@ -200,7 +200,7 @@ architecture rtl of PayloadGeneratorConAndGen is end function genByteEn; -- calcFragNumByPMTU: PktFragNum (8b) = 1 << (getPmtuLogValue(pmtu) - log2(32)) - function calcFragNumByPMTU (pmtu : slv) return slv is + function calcFragNumByPMTU (pmtu : slv(2 downto 0)) return slv is variable res : slv(7 downto 0); begin case pmtu is @@ -424,7 +424,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PAYLOAD_GEN_REQ_W_C, ADDR_WIDTH_G => 4) port map ( @@ -497,7 +497,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PENDING_REQ_W_C, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd b/ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd index 9342de1df1..a261bed602 100644 --- a/ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd +++ b/ethernet/RoCEv2/rtl/PayloadGeneratorGen.vhd @@ -181,7 +181,7 @@ architecture rtl of PayloadGeneratorGen is -- Helper functions (Utils.bsv / PrimUtils.bsv) — verified against source ----------------------------------------------------------------------------- -- calcPmtuLen: PktLen (13b) size in bytes of one PMTU packet - function calcPmtuLen (pmtu : slv) return slv is + function calcPmtuLen (pmtu : slv(2 downto 0)) return slv is begin case pmtu is when IBV_MTU_256_C => return std_logic_vector(to_unsigned(256, PKTLEN_W_C)); @@ -194,7 +194,7 @@ architecture rtl of PayloadGeneratorGen is end function calcPmtuLen; -- alignAddrByPMTU: clear the low log2(pmtu) address bits - function alignAddrByPMTU (addr : slv; pmtu : slv) return slv is + function alignAddrByPMTU (addr : slv; pmtu : slv(2 downto 0)) return slv is variable res : slv(ADDR_W_C-1 downto 0); begin res := addr(ADDR_W_C-1 downto 0); @@ -210,7 +210,7 @@ architecture rtl of PayloadGeneratorGen is end function alignAddrByPMTU; -- addrAddPsnMultiplyPMTU with psn=1: { addr[63:k]+1, addr[k-1:0] } (adds one PMTU) - function addrAddOnePMTU (addr : slv; pmtu : slv) return slv is + function addrAddOnePMTU (addr : slv; pmtu : slv(2 downto 0)) return slv is variable a : slv(ADDR_W_C-1 downto 0); variable res : slv(ADDR_W_C-1 downto 0); begin @@ -228,7 +228,7 @@ architecture rtl of PayloadGeneratorGen is end function addrAddOnePMTU; -- truncateByPMTU: ResiduePMTU (12b) = zeroExtend(bits[k-1:0]) - function truncateByPMTU (bits : slv; pmtu : slv) return slv is + function truncateByPMTU (bits : slv; pmtu : slv(2 downto 0)) return slv is variable res : slv(11 downto 0) := (others => '0'); begin res := (others => '0'); @@ -245,7 +245,7 @@ architecture rtl of PayloadGeneratorGen is -- stepOne pieces (per-PMTU slices of raddr/totalLen) ----------------------- -- pmtuMask: PktLen (13b) with low k bits set - function pmtuMaskF (pmtu : slv) return slv is + function pmtuMaskF (pmtu : slv(2 downto 0)) return slv is variable res : slv(PKTLEN_W_C-1 downto 0) := (others => '0'); begin res := (others => '0'); @@ -261,7 +261,7 @@ architecture rtl of PayloadGeneratorGen is end function pmtuMaskF; -- addrLowPart: PktLen (13b) zeroExtend of addr[k-1:0] - function addrLowPartF (addr : slv; pmtu : slv) return slv is + function addrLowPartF (addr : slv; pmtu : slv(2 downto 0)) return slv is variable res : slv(PKTLEN_W_C-1 downto 0) := (others => '0'); begin res := (others => '0'); @@ -277,7 +277,7 @@ architecture rtl of PayloadGeneratorGen is end function addrLowPartF; -- lenLowPart: PktLen (13b) zeroExtend of len[k-1:0] - function lenLowPartF (len : slv; pmtu : slv) return slv is + function lenLowPartF (len : slv; pmtu : slv(2 downto 0)) return slv is variable res : slv(PKTLEN_W_C-1 downto 0) := (others => '0'); begin res := (others => '0'); @@ -293,7 +293,7 @@ architecture rtl of PayloadGeneratorGen is end function lenLowPartF; -- truncatedPktNum: PktNum (25b) zeroExtend of len[31:k] (truncateLSB) - function truncatedPktNumF (len : slv; pmtu : slv) return slv is + function truncatedPktNumF (len : slv; pmtu : slv(2 downto 0)) return slv is variable res : slv(PKTNUM_W_C-1 downto 0) := (others => '0'); begin res := (others => '0'); @@ -1002,7 +1002,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PAYLOAD_GEN_REQ_W_C, ADDR_WIDTH_G => 4) port map ( @@ -1020,7 +1020,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => ADJ_REQ_Q_W_C, ADDR_WIDTH_G => 4) port map ( @@ -1038,7 +1038,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => TMP_FL_W_C, ADDR_WIDTH_G => 4) port map ( @@ -1056,7 +1056,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => TMP_TOTAL_W_C, ADDR_WIDTH_G => 4) port map ( @@ -1092,7 +1092,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => TMP_RESP_W_C, ADDR_WIDTH_G => 4) port map ( @@ -1128,7 +1128,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => ADD_PAD_Q_W_C, ADDR_WIDTH_G => 4) port map ( @@ -1164,7 +1164,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DS_W_C, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/PermCheckSrv.vhd b/ethernet/RoCEv2/rtl/PermCheckSrv.vhd index 2b90dd4b50..c738b7fa27 100644 --- a/ethernet/RoCEv2/rtl/PermCheckSrv.vhd +++ b/ethernet/RoCEv2/rtl/PermCheckSrv.vhd @@ -198,7 +198,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => REQ_WIDTH_C, ADDR_WIDTH_G => 4) port map ( @@ -233,7 +233,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => STEP_WIDTH_C, ADDR_WIDTH_G => 4) port map ( @@ -268,7 +268,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => STEP_WIDTH_C, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/PipeOutMux.vhd b/ethernet/RoCEv2/rtl/PipeOutMux.vhd index 3acf06de38..b83b566080 100644 --- a/ethernet/RoCEv2/rtl/PipeOutMux.vhd +++ b/ethernet/RoCEv2/rtl/PipeOutMux.vhd @@ -21,7 +21,7 @@ -- (combinatorial from `sel` and the *Valid/*Dout/notFull inputs). -- -- SURF components instantiated: --- U_PipeMuxOutQ : surf.Fifo (DATA_WIDTH_G=679, FWFT, sync, block RAM) +-- U_PipeMuxOutQ : surf.Fifo (DATA_WIDTH_G=679, FWFT, sync, distributed RAM) -- source: surf/base/fifo/rtl/Fifo.vhd -- -- DATA_WIDTH_G (OQ resolved at emit): @@ -113,7 +113,7 @@ begin RST_ASYNC_G => RST_ASYNC_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DATA_WIDTH_G, ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) port map ( diff --git a/ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd b/ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd index 3e556b549c..ddfc13e7fd 100644 --- a/ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd +++ b/ethernet/RoCEv2/rtl/PrependHeader2PipeOut.vhd @@ -163,7 +163,7 @@ begin -- U_DataStreamOutQ : surf.Fifo -- Output queue; its read side IS the returned PipeOut#(DataStream). -- Written by outputHeader / outputData / extraLastFrag. - -- DATA_WIDTH_G=290, FWFT, sync, block RAM. + -- DATA_WIDTH_G=290, FWFT, sync, distributed RAM. --------------------------------------------------------------------------- U_DataStreamOutQ : entity surf.Fifo generic map ( @@ -172,7 +172,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 290, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/Qp.vhd b/ethernet/RoCEv2/rtl/Qp.vhd index d440f05c0a..47b97b5a23 100644 --- a/ethernet/RoCEv2/rtl/Qp.vhd +++ b/ethernet/RoCEv2/rtl/Qp.vhd @@ -96,7 +96,11 @@ entity Qp is -- (ready='1'), outputs quiesce (valid='0'). EN_TX_G : boolean := true; EN_RX_G : boolean := true; - EN_READ_G : boolean := true); + EN_READ_G : boolean := true; + -- Settings.bsv MAX_QP_WR (BSV default 32): max pending work requests per + -- QP (effective in-flight window is MAX_QP_WR_G-1, one slot reserved). + -- Must be a power of 2 (sizes SqQueuePair's ScanFifoF). + MAX_QP_WR_G : positive := 4); port ( clk : in sl; rst : in sl := not RST_POLARITY_G; -- FPGA async/sync reset @@ -254,8 +258,9 @@ architecture rtl of Qp is constant DMA_WRITE_REQ_C : positive := 419; constant DMA_WRITE_RESP_C : positive := 53; constant PERM_CHECK_REQ_C : positive := 267; - -- recvReqQ = mkSizedFIFOF(MAX_QP_WR=32) -> 2**5; workReqQ = mkFIFOF -> min depth - constant RECV_REQ_AW_C : positive := 5; -- 2**5 = 32 = MAX_QP_WR + -- recvReqQ = mkSizedFIFOF(MAX_QP_WR); workReqQ = mkFIFOF -> min depth + -- surf.Fifo needs ADDR_WIDTH_G >= 4, so depth is at least 16 (>= MAX_QP_WR ok) + constant RECV_REQ_AW_C : positive := maximum(log2(MAX_QP_WR_G), 4); constant WORK_REQ_AW_C : positive := 4; -- min surf.Fifo depth (BSV mkFIFOF) ----------------------------------------------------------------------------- @@ -761,7 +766,8 @@ begin ----------------------------------------------------------------------------- U_CntrlQp : entity surf.CntrlQp generic map ( - TPD_G => TPD_G) + TPD_G => TPD_G, + MAX_QP_WR_G => MAX_QP_WR_G) port map ( clk => clk, rst => rst, @@ -900,7 +906,7 @@ begin RST_ASYNC_G => RST_ASYNC_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => WORK_REQ_C, ADDR_WIDTH_G => WORK_REQ_AW_C) port map ( @@ -1334,8 +1340,9 @@ begin GEN_RQ : if EN_RX_G generate U_Rq : entity surf.Rq generic map ( - TPD_G => TPD_G, - EN_READ_G => EN_READ_G) + TPD_G => TPD_G, + EN_READ_G => EN_READ_G, + MAX_QP_WR_G => MAX_QP_WR_G) port map ( clk => clk, rst => rst, @@ -1446,7 +1453,8 @@ begin TPD_G => TPD_G, RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, - EN_READ_G => EN_READ_G) + EN_READ_G => EN_READ_G, + MAX_QP_WR_G => MAX_QP_WR_G) port map ( clk => clk, rst => rst, diff --git a/ethernet/RoCEv2/rtl/RdmaPktMetaDataAndPayloadPipe.vhd b/ethernet/RoCEv2/rtl/RdmaPktMetaDataAndPayloadPipe.vhd index a82ad7a64f..e7c0f159cd 100644 --- a/ethernet/RoCEv2/rtl/RdmaPktMetaDataAndPayloadPipe.vhd +++ b/ethernet/RoCEv2/rtl/RdmaPktMetaDataAndPayloadPipe.vhd @@ -98,7 +98,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 649, ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) port map ( @@ -125,7 +125,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 290, ADDR_WIDTH_G => FIFO_ADDR_WIDTH_G) port map ( diff --git a/ethernet/RoCEv2/rtl/ReqGenSq.vhd b/ethernet/RoCEv2/rtl/ReqGenSq.vhd index 011e95a454..9b92427622 100644 --- a/ethernet/RoCEv2/rtl/ReqGenSq.vhd +++ b/ethernet/RoCEv2/rtl/ReqGenSq.vhd @@ -322,7 +322,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PWR_W_C, ADDR_WIDTH_G => 4) port map ( @@ -342,7 +342,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => WCREQ_W_C, ADDR_WIDTH_G => 4) port map ( @@ -362,7 +362,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => WRPG_W_C, ADDR_WIDTH_G => 4) port map ( @@ -382,7 +382,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => WRPKTNUM_W_C, ADDR_WIDTH_G => 4) port map ( @@ -402,7 +402,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => TUP2_W_C, ADDR_WIDTH_G => 4) port map ( @@ -422,7 +422,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => TUP2_W_C, ADDR_WIDTH_G => 4) port map ( @@ -442,7 +442,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => TUP2_W_C, ADDR_WIDTH_G => 4) port map ( @@ -462,7 +462,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => TUP2_W_C, ADDR_WIDTH_G => 4) port map ( @@ -482,7 +482,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => REQHDRPREP_W_C, ADDR_WIDTH_G => 4) port map ( @@ -502,7 +502,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PENDREQHDR_W_C, ADDR_WIDTH_G => 4) port map ( @@ -522,7 +522,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => REQHDRGEN_W_C, ADDR_WIDTH_G => 4) port map ( @@ -542,7 +542,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => HRDMA_W_C, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/ReqHandleRq.vhd b/ethernet/RoCEv2/rtl/ReqHandleRq.vhd index a3f65fe995..4bf067122d 100644 --- a/ethernet/RoCEv2/rtl/ReqHandleRq.vhd +++ b/ethernet/RoCEv2/rtl/ReqHandleRq.vhd @@ -98,7 +98,9 @@ entity ReqHandleRq is -- are forced false, so incoming READ/CMP_SWP/FETCH_ADD requests take the -- existing unsupported-opcode NAK-INV_REQ path and the read/atomic -- serving datapath (dup cache, payload gen, atomic srv) constant-folds. - EN_READ_G : boolean := true); + EN_READ_G : boolean := true; + -- Settings.bsv MAX_QP_WR (BSV default 32); must match CntrlQp MAX_QP_WR_G + MAX_QP_WR_G : positive := 4); port ( clk : in sl; rst : in sl; -- active-high synchronous reset @@ -282,11 +284,11 @@ architecture rtl of ReqHandleRq is -- (D) response-packet loop isFirstOrOnlyRespPkt : sl; -- mkReg True -- (E) coalesce counter - coalesceWorkReqCnt : slv(7 downto 0); -- mkCount(MAX_QP_WR-1=31) + coalesceWorkReqCnt : slv(7 downto 0); -- mkCount(MAX_QP_WR-1) isCoalesceWorkReqCntZero : sl; end record RegType; - constant COALESCE_INIT_C : slv(7 downto 0) := std_logic_vector(to_unsigned(31, 8)); -- MAX_QP_WR-1 + constant COALESCE_INIT_C : slv(7 downto 0) := std_logic_vector(to_unsigned(MAX_QP_WR_G-1, 8)); -- MAX_QP_WR-1 constant REG_INIT_C : RegType := ( preStageState => RQ_PRE_BUILD_STAGE_S, @@ -1048,224 +1050,224 @@ begin --------------------------------------------------------------------------- U_SupportedReqOpCodeCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W01_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f01WrEn, din => f01Din, not_full => f01NotFull, rd_clk => clk, rd_en => f01RdEn, dout => f01Dout, valid => f01Valid); U_ReqOpCodeSeqCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W02_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f02WrEn, din => f02Din, not_full => f02NotFull, rd_clk => clk, rd_en => f02RdEn, dout => f02Dout, valid => f02Valid); U_RnrCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W03_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f03WrEn, din => f03Din, not_full => f03NotFull, rd_clk => clk, rd_en => f03RdEn, dout => f03Dout, valid => f03Valid); U_RnrTriggerQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W04_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f04WrEn, din => f04Din, not_full => f04NotFull, rd_clk => clk, rd_en => f04RdEn, dout => f04Dout, valid => f04Valid); U_QpAccPermCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W05_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f05WrEn, din => f05Din, not_full => f05NotFull, rd_clk => clk, rd_en => f05RdEn, dout => f05Dout, valid => f05Valid); U_ReqPermInfoBuildQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W06_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f06WrEn, din => f06Din, not_full => f06NotFull, rd_clk => clk, rd_en => f06RdEn, dout => f06Dout, valid => f06Valid); U_ReqPermQueryTmpQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W07_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f07WrEn, din => f07Din, not_full => f07NotFull, rd_clk => clk, rd_en => f07RdEn, dout => f07Dout, valid => f07Valid); U_ReqPermQueryQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W08_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f08WrEn, din => f08Din, not_full => f08NotFull, rd_clk => clk, rd_en => f08RdEn, dout => f08Dout, valid => f08Valid); U_ReqPermCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W09_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f09WrEn, din => f09Din, not_full => f09NotFull, rd_clk => clk, rd_en => f09RdEn, dout => f09Dout, valid => f09Valid); U_ReadCacheInsertQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W10_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f10WrEn, din => f10Din, not_full => f10NotFull, rd_clk => clk, rd_en => f10RdEn, dout => f10Dout, valid => f10Valid); U_DupReadReqPermQueryQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W11_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f11WrEn, din => f11Din, not_full => f11NotFull, rd_clk => clk, rd_en => f11RdEn, dout => f11Dout, valid => f11Valid); U_DupReadReqPermCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W12_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f12WrEn, din => f12Din, not_full => f12NotFull, rd_clk => clk, rd_en => f12RdEn, dout => f12Dout, valid => f12Valid); U_ReqAddrCalcQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W13_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f13WrEn, din => f13Din, not_full => f13NotFull, rd_clk => clk, rd_en => f13RdEn, dout => f13Dout, valid => f13Valid); U_ReqRemainingLenCalcQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W14_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f14WrEn, din => f14Din, not_full => f14NotFull, rd_clk => clk, rd_en => f14RdEn, dout => f14Dout, valid => f14Valid); U_ReqEnoughDmaSpaceQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W15_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f15WrEn, din => f15Din, not_full => f15NotFull, rd_clk => clk, rd_en => f15RdEn, dout => f15Dout, valid => f15Valid); U_ReqTotalLenCalcQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W16_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f16WrEn, din => f16Din, not_full => f16NotFull, rd_clk => clk, rd_en => f16RdEn, dout => f16Dout, valid => f16Valid); U_ReqLenCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W17_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f17WrEn, din => f17Din, not_full => f17NotFull, rd_clk => clk, rd_en => f17RdEn, dout => f17Dout, valid => f17Valid); U_IssuePayloadConReqQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W18_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f18WrEn, din => f18Din, not_full => f18NotFull, rd_clk => clk, rd_en => f18RdEn, dout => f18Dout, valid => f18Valid); U_IssuePayloadGenReqQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W19_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f19WrEn, din => f19Din, not_full => f19NotFull, rd_clk => clk, rd_en => f19RdEn, dout => f19Dout, valid => f19Valid); U_IssueAtomicReqQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W20_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f20WrEn, din => f20Din, not_full => f20NotFull, rd_clk => clk, rd_en => f20RdEn, dout => f20Dout, valid => f20Valid); U_RespGenCheck4NormalCaseQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W21_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f21WrEn, din => f21Din, not_full => f21NotFull, rd_clk => clk, rd_en => f21RdEn, dout => f21Dout, valid => f21Valid); U_RespGenCheck4OtherCasesQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W22_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f22WrEn, din => f22Din, not_full => f22NotFull, rd_clk => clk, rd_en => f22RdEn, dout => f22Dout, valid => f22Valid); U_RespCountQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W23_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f23WrEn, din => f23Din, not_full => f23NotFull, rd_clk => clk, rd_en => f23RdEn, dout => f23Dout, valid => f23Valid); U_RespPsnAndMsnQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W24_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f24WrEn, din => f24Din, not_full => f24NotFull, rd_clk => clk, rd_en => f24RdEn, dout => f24Dout, valid => f24Valid); U_WaitAtomicRespQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W25_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f25WrEn, din => f25Din, not_full => f25NotFull, rd_clk => clk, rd_en => f25RdEn, dout => f25Dout, valid => f25Valid); U_AtomicCacheInsertQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W26_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f26WrEn, din => f26Din, not_full => f26NotFull, rd_clk => clk, rd_en => f26RdEn, dout => f26Dout, valid => f26Valid); U_RespCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W27_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f27WrEn, din => f27Din, not_full => f27NotFull, rd_clk => clk, rd_en => f27RdEn, dout => f27Dout, valid => f27Valid); U_DupAtomicReqPermQueryQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W28_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f28WrEn, din => f28Din, not_full => f28NotFull, rd_clk => clk, rd_en => f28RdEn, dout => f28Dout, valid => f28Valid); U_DupAtomicReqPermCheckQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W29_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f29WrEn, din => f29Din, not_full => f29NotFull, rd_clk => clk, rd_en => f29RdEn, dout => f29Dout, valid => f29Valid); U_RespHeaderGenQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W30_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f30WrEn, din => f30Din, not_full => f30NotFull, rd_clk => clk, rd_en => f30RdEn, dout => f30Dout, valid => f30Valid); U_PendingRespQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W31_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f31WrEn, din => f31Din, not_full => f31NotFull, rd_clk => clk, rd_en => f31RdEn, dout => f31Dout, valid => f31Valid); U_WorkCompReqQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => W32_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => f32WrEn, din => f32Din, not_full => f32NotFull, rd_clk => clk, rd_en => f32RdEn, @@ -1273,21 +1275,21 @@ begin -- output FIFOs U_WorkCompGenReqOutQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => WCW_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => wcOutWrEn, din => wcOutDin, not_full => wcOutNotFull, rd_clk => clk, rd_en => wcOutRdEn, dout => wcOutDout, valid => wcOutValid); U_RespHeaderOutQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => RHW_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => rhOutWrEn, din => rhOutDin, not_full => rhOutNotFull, rd_clk => clk, rd_en => rhOutRdEn, dout => rhOutDout, valid => rhOutValid); U_PsnRespOutQ : entity surf.Fifo generic map (TPD_G => TPD_G, RST_POLARITY_G => '1', RST_ASYNC_G => false, - GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "block", + GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PSW_C, ADDR_WIDTH_G => 4) port map (rst => fifoClr, wr_clk => clk, wr_en => psnOutWrEn, din => psnOutDin, not_full => psnOutNotFull, rd_clk => clk, rd_en => psnOutRdEn, @@ -1472,6 +1474,9 @@ begin variable rkeyM31V : slv(32 downto 0); -- Maybe#RKEY variable doDecr31V : boolean; -- pendingDestReadAtomicReqCnt.decrOne variable doWcEnq31V : boolean; -- workCompGenReqOutQ.enq + -- Phase err (SUB-FSM C errFlushRecvReq): synthetic flush-RR token fields + variable flushPmdV : slv(648 downto 0); -- synthetic RdmaPktMetaData + variable flushPktInfoV : slv(160 downto 0); -- synthetic RdmaReqPktInfo begin v := r; @@ -2723,17 +2728,51 @@ begin -- SUB-FSM C : error-flush rules (inErrorState). Exactly one of the -- normal pre-stage / errFlush consumers touches pktMetaDataPipeIn per -- cycle — inErrorState is mutually exclusive with the normal guard. + -- + -- Synthetic flush-RR token (errFlushRecvReq), values forced by the + -- stage-1..31 trace: + -- pmd: zeros except isZeroPayloadLen='1' (pmd[627]) — keeps stage 17 + -- from issuing a PayloadConReq for the synthetic token. + -- reqPktInfo: bth=0 (opcode "00000"=SEND_FIRST -> WorkCompGenRq maps + -- it to a Valid IBV_WC_RECV with isSendReq & isFirstOrOnly, the + -- errFlushRQ emit condition); epoch := getEpoch (stages 1-4 + -- demote epoch-mismatched tokens to DISCARD); all classifier + -- flags '0' (every reader is NORMAL/DUP-gated, so an + -- ERR_FLUSH_RR token skips them). -------------------------------------------------------------------- + flushPmdV := (others => '0'); + flushPmdV(PMD_ISZEROPAYLOAD_C) := '1'; + flushPktInfoV := (others => '0'); + flushPktInfoV(64) := getEpoch; + if (inErrorState = '1' and f01NotFull = '1') then - if (pktMetaValid = '0') then - -- errFlushRecvReq (synthesised flush RR, no deq) - f01WrEn <= '1'; - -- TODO(phase-err): f01Din <= flush-RR tuple (reqStatus=ERR_FLUSH_RR) - else - -- errFlushIncomingReq (deq + discard) + if (pktMetaValid = '1') then + -- errFlushIncomingReq (ReqHandleRQ.bsv errFlushIncomingReq): + -- deq + discard-enq the incoming packet. reqPktInfo keeps the + -- real BTH so stage 17 issues the Discard PayloadConReq with the + -- packet's fragNum/psn (the payload must be sunk; the + -- PayloadConsumer rules stay active under isErr). pktMetaDeq <= '1'; f01WrEn <= '1'; - -- TODO(phase-err): f01Din <= tuple4(pktMetaData, DISCARD, ...) + f01Din <= pktMetaData & ST_DISCARD_C + & pktMetaData(626 downto 531) -- reqPktInfo.bth + & flushPktInfoV(64 downto 0) -- epoch & zeros + & getEPSN; + elsif (recvReqValid = '1') then + -- errFlushRecvReq (ReqHandleRQ.bsv errFlushRecvReq): synthesize + -- one flush-RR token; stage 3's ERR_FLUSH_RR branch deqs one recv + -- WR per token and stage 31 + WorkCompGenRq.errFlushRQ complete + -- it as IBV_WC_WR_FLUSH_ERR, letting recvReqValid fall so QP + -- DESTROY can complete (qp-destroy-hang-issue.md). + -- DEVIATION-RHR-01 (2026-07-13): gated on recvReqValid — upstream + -- blue-rdma fires unconditionally, pushing a token down the + -- 32-stage pipe every cycle for as long as the QP sits in ERR. + -- Stages advance on workerEnable without needing head input, so + -- gating loses no flush coverage; surplus in-flight tokens that + -- miss the recvReq still terminate safely (Invalid rrID -> + -- genMaybeTag=0 in WorkCompGenRq.errFlushRQ -> dropped). + f01WrEn <= '1'; + f01Din <= flushPmdV & ST_ERR_FLUSH_RR_C & flushPktInfoV & getEPSN; end if; end if; diff --git a/ethernet/RoCEv2/rtl/RespHandleSq.vhd b/ethernet/RoCEv2/rtl/RespHandleSq.vhd index 3029ae9988..d76f3aaace 100644 --- a/ethernet/RoCEv2/rtl/RespHandleSq.vhd +++ b/ethernet/RoCEv2/rtl/RespHandleSq.vhd @@ -490,7 +490,7 @@ architecture rtl of RespHandleSq is end if; end function; -- genErrWorkCompStatusFromAethSQ -> Maybe#(WorkCompStatus) (tag|5b) - function genErrWcStatusFromAeth(aCode, aVal : slv) return slv is + function genErrWcStatusFromAeth(aCode : slv(1 downto 0); aVal : slv(4 downto 0)) return slv is begin if aCode = "11" then -- AETH_CODE_NAK case aVal is @@ -535,7 +535,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1470, ADDR_WIDTH_G => 4) port map ( @@ -567,7 +567,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1473, ADDR_WIDTH_G => 4) port map ( @@ -599,7 +599,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1469, ADDR_WIDTH_G => 4) port map ( @@ -631,7 +631,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1470, ADDR_WIDTH_G => 4) port map ( @@ -663,7 +663,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1476, ADDR_WIDTH_G => 4) port map ( @@ -695,7 +695,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1475, ADDR_WIDTH_G => 4) port map ( @@ -727,7 +727,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1539, ADDR_WIDTH_G => 4) port map ( @@ -759,7 +759,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1605, ADDR_WIDTH_G => 4) port map ( @@ -791,7 +791,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1573, ADDR_WIDTH_G => 4) port map ( @@ -823,7 +823,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1539, ADDR_WIDTH_G => 4) port map ( @@ -855,7 +855,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 768, ADDR_WIDTH_G => 4) port map ( @@ -887,7 +887,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 633, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/RetryHandleSq.vhd b/ethernet/RoCEv2/rtl/RetryHandleSq.vhd index b0bdf36e9b..b845398c58 100644 --- a/ethernet/RoCEv2/rtl/RetryHandleSq.vhd +++ b/ethernet/RoCEv2/rtl/RetryHandleSq.vhd @@ -408,7 +408,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1, ADDR_WIDTH_G => 4) port map ( @@ -426,7 +426,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1, ADDR_WIDTH_G => 4) port map ( @@ -444,7 +444,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 97, ADDR_WIDTH_G => 4) port map ( @@ -462,7 +462,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 2, ADDR_WIDTH_G => 4) port map ( @@ -480,7 +480,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1, ADDR_WIDTH_G => 4) port map ( @@ -498,7 +498,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1, ADDR_WIDTH_G => 4) port map ( @@ -516,7 +516,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 1, ADDR_WIDTH_G => 4) port map ( @@ -534,7 +534,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 98, ADDR_WIDTH_G => 4) port map ( @@ -552,7 +552,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 98, ADDR_WIDTH_G => 4) port map ( @@ -570,7 +570,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 4, ADDR_WIDTH_G => 4) port map ( @@ -588,7 +588,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 4, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd b/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd index f2fc4566f5..5df22e1e67 100644 --- a/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd +++ b/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd @@ -61,6 +61,10 @@ entity RoceEngineWrapper is RST_POLARITY_G : sl := '1'; -- '1' active HIGH reset, '0' active LOW RST_ASYNC_G : boolean := false; MAX_QP_G : positive := 4; -- power of 2, >= 1 (TransportLayer proviso) + MAX_QP_WR_G : positive := 4; -- max pending work requests per QP + -- (Settings.bsv MAX_QP_WR, BSV default + -- 32; effective in-flight window is + -- MAX_QP_WR_G-1). Power of 2. -- Resource-pruning generics (pass-through to TransportLayer; all true = -- full engine, identical to the verified netlist; at least one of -- EN_TX_G/EN_RX_G must be true): @@ -243,11 +247,12 @@ begin --------------------------------------------------------------------------- U_TransportLayer : entity surf.TransportLayer generic map ( - TPD_G => TPD_G, - MAX_QP_G => MAX_QP_G, - EN_TX_G => EN_TX_G, - EN_RX_G => EN_RX_G, - EN_READ_G => EN_READ_G) + TPD_G => TPD_G, + MAX_QP_G => MAX_QP_G, + MAX_QP_WR_G => MAX_QP_WR_G, + EN_TX_G => EN_TX_G, + EN_RX_G => EN_RX_G, + EN_READ_G => EN_READ_G) port map ( clk => clk, rst => rst, diff --git a/ethernet/RoCEv2/rtl/Rq.vhd b/ethernet/RoCEv2/rtl/Rq.vhd index ca01332ecb..33792f7ffd 100644 --- a/ethernet/RoCEv2/rtl/Rq.vhd +++ b/ethernet/RoCEv2/rtl/Rq.vhd @@ -46,7 +46,9 @@ entity Rq is -- false = no RDMA READ/atomic serving: U_DupReadAtomicCache is not -- generated (its client faces are tied inert) and ReqHandleRq NAKs -- incoming READ/atomic requests as unsupported (INV_REQ). - EN_READ_G : boolean := true); + EN_READ_G : boolean := true; + -- Settings.bsv MAX_QP_WR (BSV default 32); pass-through to ReqHandleRq + MAX_QP_WR_G : positive := 4); port ( clk : in sl; rst : in sl; -- active-high synchronous reset @@ -316,8 +318,9 @@ begin ------------------------------------------------------------------------------ U_ReqHandleRq : entity surf.ReqHandleRq generic map ( - TPD_G => TPD_G, - EN_READ_G => EN_READ_G) + TPD_G => TPD_G, + EN_READ_G => EN_READ_G, + MAX_QP_WR_G => MAX_QP_WR_G) port map ( clk => clk, rst => rst, diff --git a/ethernet/RoCEv2/rtl/SendQ.vhd b/ethernet/RoCEv2/rtl/SendQ.vhd index b204e4b5d3..4cbdd8e10b 100644 --- a/ethernet/RoCEv2/rtl/SendQ.vhd +++ b/ethernet/RoCEv2/rtl/SendQ.vhd @@ -243,7 +243,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => WQE_W_C, ADDR_WIDTH_G => 4) port map ( @@ -263,7 +263,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => TMD_W_C, ADDR_WIDTH_G => 4) port map ( @@ -283,7 +283,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PSNU_W_C, ADDR_WIDTH_G => 4) port map ( @@ -303,7 +303,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => HPREP_W_C, ADDR_WIDTH_G => 4) port map ( @@ -323,7 +323,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => PEND_W_C, ADDR_WIDTH_G => 4) port map ( @@ -343,7 +343,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => HRDMA_W_C, ADDR_WIDTH_G => 4) port map ( @@ -363,7 +363,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => UDP_W_C, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/ServerProxy.vhd b/ethernet/RoCEv2/rtl/ServerProxy.vhd index b5a998159d..3254d4dca1 100644 --- a/ethernet/RoCEv2/rtl/ServerProxy.vhd +++ b/ethernet/RoCEv2/rtl/ServerProxy.vhd @@ -138,7 +138,7 @@ begin -- All outputs are purely combinatorial (Mealy-degenerate); no r fields -- contribute to any output. --------------------------------------------------------------------------- - comb : process (r, srvReqValid, srvRespReady, cltReqReady, cltRespValid, + comb : process (r, rst, srvReqValid, srvRespReady, cltReqReady, cltRespValid, reqQNotFull, reqQValid, reqQDout, respQNotFull, respQValid, respQDout) is variable v : RegType; diff --git a/ethernet/RoCEv2/rtl/SqQueuePair.vhd b/ethernet/RoCEv2/rtl/SqQueuePair.vhd index c35a0a469b..dbdba000b5 100644 --- a/ethernet/RoCEv2/rtl/SqQueuePair.vhd +++ b/ethernet/RoCEv2/rtl/SqQueuePair.vhd @@ -111,7 +111,10 @@ entity SqQueuePair is -- (read-response landing -> DMA write) is not generated and RespHandleSq -- treats read/atomic responses as unknown (contract: software never -- posts READ/atomic work requests). - EN_READ_G : boolean := true); + EN_READ_G : boolean := true; + -- Settings.bsv MAX_QP_WR (BSV default 32): pendingWorkReqBuf scan depth. + -- Must match CntrlQp MAX_QP_WR_G and be a power of 2 (ScanFifoF Q_SZ_G). + MAX_QP_WR_G : positive := 4); port ( clk : in sl; rst : in sl := not RST_POLARITY_G; -- FPGA async/sync reset (active-high) @@ -222,7 +225,7 @@ architecture rtl of SqQueuePair is -- Word widths (traced from child ports / DataTypes.bsv) ----------------------------------------------------------------------------- constant PENDING_WR_C : positive := 679; -- PendingWorkReq - constant MAX_QP_WR_C : positive := 32; -- Settings.bsv MAX_QP_WR (scan depth) + constant MAX_QP_WR_C : positive := MAX_QP_WR_G; -- Settings.bsv MAX_QP_WR (scan depth) ----------------------------------------------------------------------------- -- Inter-child signals @@ -442,8 +445,8 @@ begin TPD_G => TPD_G, RST_POLARITY_G => RST_POLARITY_G, RST_ASYNC_G => RST_ASYNC_G, - MEMORY_TYPE_G => "block", -- 679b scan-output queue -> block RAM - Q_SZ_G => MAX_QP_WR_C, -- MAX_QP_WR = 32 + MEMORY_TYPE_G => "distributed", -- 679b scan-output queue -> distributed RAM + Q_SZ_G => MAX_QP_WR_C, -- MAX_QP_WR T_SZ_G => PENDING_WR_C) -- PendingWorkReq = 679b port map ( clk => clk, diff --git a/ethernet/RoCEv2/rtl/SqSendQ.vhd b/ethernet/RoCEv2/rtl/SqSendQ.vhd index 8bee9eadb9..887e92658c 100644 --- a/ethernet/RoCEv2/rtl/SqSendQ.vhd +++ b/ethernet/RoCEv2/rtl/SqSendQ.vhd @@ -186,7 +186,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 176, ADDR_WIDTH_G => 4) port map ( @@ -216,7 +216,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 383, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd b/ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd deleted file mode 100644 index 12916c9191..0000000000 --- a/ethernet/RoCEv2/rtl/TagVecSrv_tb.vhd +++ /dev/null @@ -1,359 +0,0 @@ -------------------------------------------------------------------------------- --- Company : SLAC National Accelerator Laboratory -------------------------------------------------------------------------------- --- Description: Self-checking testbench for TagVecSrv (out/04-vhdl/TagVecSrv.vhd). --- --- Configuration under test: V_SZ_G = 4, T_SZ_G = 32 (the mkMetaDataQPs / --- HandlerPD instantiation). Directed scenarios: --- 1. Reset state : empty, not full. --- 2. Inserts 0..3 : sequential free-slot allocation (LSB priority). --- 3. Fill to full : notFull deasserts after the 4th insert. --- 4. Insert while full : response success = 0, count unchanged. --- 5. Remove : success = 1, slot freed, notFull re-asserts. --- 6. Remove empty slot : success = 0. --- 7. Free-slot reuse : next insert reuses the lowest freed index. --- 8. getItem lookup : valid + data for tagged / untagged slots. --- 9. clear() + recovery : both FIFOs flushed, tags reset, then re-usable. --- --- Drives the request/response valid-ready handshakes (srvPort) and the --- getItem / notEmpty / notFull / clear method ports. Inputs are driven and --- outputs sampled on the FALLING edge so combinational FWFT outputs are fully --- settled; the DUT and SURF FIFOs latch on the rising edge. --- --- NOTE: TagVecSrv instantiates surf.Fifo, so the SURF library must be --- compiled to elaborate/run this testbench (see the run notes at end of file). -------------------------------------------------------------------------------- --- This file is part of 'SLAC Firmware Standard Library'. --- It is subject to the license terms in the LICENSE.txt file found in the --- top-level directory of this distribution and at: --- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. --- No part of 'SLAC Firmware Standard Library', including this file, --- may be copied, modified, propagated, or distributed except according to --- the terms contained in the LICENSE.txt file. -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library surf; -use surf.StdRtlPkg.all; - -entity TagVecSrv_tb is -end entity TagVecSrv_tb; - -architecture sim of TagVecSrv_tb is - - -- DUT configuration - constant T_SZ_C : positive := 32; - constant V_SZ_C : positive := 4; - constant V_LOG_SZ_C : integer := log2(V_SZ_C); -- 2 - constant FIFO_WIDTH_C : integer := 1 + T_SZ_C + V_LOG_SZ_C; -- 35 - - constant CLK_PERIOD_C : time := 10 ns; - constant SETTLE_C : time := 1 ns; -- delta-settle delay for comb reads - - -- Clock / reset - signal clk : sl := '0'; - signal rst : sl := '1'; - signal simDone : boolean := false; - - -- Request side (TB -> DUT) - signal reqValid : sl := '0'; - signal reqData : slv(FIFO_WIDTH_C-1 downto 0) := (others => '0'); - signal reqReady : sl; - - -- Response side (DUT -> TB) - signal respValid : sl; - signal respData : slv(FIFO_WIDTH_C-1 downto 0); - signal respReady : sl := '0'; - - -- Method ports - signal getItemIdx : slv(V_LOG_SZ_C-1 downto 0) := (others => '0'); - signal getItemOut : slv(T_SZ_C downto 0); - signal notEmpty : sl; - signal notFull : sl; - signal clearEn : sl := '0'; - - -- Convenience constants - constant INSERT_C : sl := '1'; - constant REMOVE_C : sl := '0'; - -begin - - ----------------------------------------------------------------------------- - -- Clock / reset generation - ----------------------------------------------------------------------------- - clk <= not clk after CLK_PERIOD_C/2 when not simDone else '0'; - - rst_proc : process is - begin - rst <= '1'; - wait for 4*CLK_PERIOD_C; - wait until falling_edge(clk); - rst <= '0'; - wait; - end process rst_proc; - - ----------------------------------------------------------------------------- - -- Device under test - ----------------------------------------------------------------------------- - U_DUT : entity surf.TagVecSrv - generic map ( - RST_POLARITY_G => '1', - RST_ASYNC_G => false, - MEMORY_TYPE_G => "distributed", - V_SZ_G => V_SZ_C, - T_SZ_G => T_SZ_C) - port map ( - clk => clk, - rst => rst, - reqValid => reqValid, - reqData => reqData, - reqReady => reqReady, - respValid => respValid, - respData => respData, - respReady => respReady, - getItemIdx => getItemIdx, - getItemOut => getItemOut, - notEmpty => notEmpty, - notFull => notFull, - clearEn => clearEn); - - ----------------------------------------------------------------------------- - -- Stimulus + checking - ----------------------------------------------------------------------------- - stim : process is - variable errCnt : natural := 0; - - -- advance one clock (sample/drive on falling edge -> settled values) - procedure step is - begin - wait until falling_edge(clk); - end procedure step; - - procedure check(cond : boolean; msg : string) is - begin - if not cond then - report "FAIL: " & msg severity error; - errCnt := errCnt + 1; - else - report "pass: " & msg severity note; - end if; - end procedure check; - - -- Enqueue one request word into reqQ (held for exactly one rising edge) - procedure enqReq(insOrRem : sl; - iVal : slv(T_SZ_C-1 downto 0); - rIdx : slv(V_LOG_SZ_C-1 downto 0)) is - begin - -- wait for space (reqReady = reqQ.not_full) - while reqReady /= '1' loop - step; - end loop; - reqValid <= '1'; - reqData <= insOrRem & iVal & rIdx; - step; - reqValid <= '0'; - reqData <= (others => '0'); - end procedure enqReq; - - -- Pop one response from respQ - procedure popResp(success : out sl; - idx : out slv(V_LOG_SZ_C-1 downto 0); - val : out slv(T_SZ_C-1 downto 0)) is - begin - respReady <= '1'; - -- wait until the response is available (FWFT valid) - while respValid /= '1' loop - step; - end loop; - -- capture head (registered/FWFT data, valid this cycle) - success := respData(FIFO_WIDTH_C-1); - idx := respData(FIFO_WIDTH_C-2 downto T_SZ_C); - val := respData(T_SZ_C-1 downto 0); - step; -- rising edge pops the entry - respReady <= '0'; - end procedure popResp; - - -- Issue an insert and check the response - procedure doInsert(iVal : slv(T_SZ_C-1 downto 0); - expSucc : sl; - expIdx : slv(V_LOG_SZ_C-1 downto 0); - chkIdx : boolean; - tag : string) is - variable s : sl; - variable i : slv(V_LOG_SZ_C-1 downto 0); - variable v : slv(T_SZ_C-1 downto 0); - begin - enqReq(INSERT_C, iVal, (others => '0')); - popResp(s, i, v); - check(s = expSucc, tag & " success"); - if expSucc = '1' then - check(v = iVal, tag & " value echoed"); - if chkIdx then - check(i = expIdx, tag & " index"); - end if; - end if; - end procedure doInsert; - - -- Issue a remove and check the response - procedure doRemove(rIdx : slv(V_LOG_SZ_C-1 downto 0); - expSucc : sl; - expVal : slv(T_SZ_C-1 downto 0); - chkVal : boolean; - tag : string) is - variable s : sl; - variable i : slv(V_LOG_SZ_C-1 downto 0); - variable v : slv(T_SZ_C-1 downto 0); - begin - enqReq(REMOVE_C, (others => '0'), rIdx); - popResp(s, i, v); - check(s = expSucc, tag & " success"); - if expSucc = '1' then - check(i = rIdx, tag & " index echoed"); - if chkVal then - check(v = expVal, tag & " value"); - end if; - end if; - end procedure doRemove; - - procedure checkItem(idx : slv(V_LOG_SZ_C-1 downto 0); - expV : sl; - expData : slv(T_SZ_C-1 downto 0); - chkData : boolean; - tag : string) is - begin - getItemIdx <= idx; - wait for SETTLE_C; - check(getItemOut(T_SZ_C) = expV, tag & " valid"); - if expV = '1' and chkData then - check(getItemOut(T_SZ_C-1 downto 0) = expData, tag & " data"); - end if; - end procedure checkItem; - - -- Slot data used through the test - constant A_C : slv(T_SZ_C-1 downto 0) := x"AAAA0001"; - constant B_C : slv(T_SZ_C-1 downto 0) := x"BBBB0002"; - constant C_C : slv(T_SZ_C-1 downto 0) := x"CCCC0003"; - constant D_C : slv(T_SZ_C-1 downto 0) := x"DDDD0004"; - constant E_C : slv(T_SZ_C-1 downto 0) := x"EEEE0005"; - constant F_C : slv(T_SZ_C-1 downto 0) := x"12345678"; - constant G_C : slv(T_SZ_C-1 downto 0) := x"0BADF00D"; - - constant IDX0_C : slv(V_LOG_SZ_C-1 downto 0) := "00"; - constant IDX1_C : slv(V_LOG_SZ_C-1 downto 0) := "01"; - constant IDX2_C : slv(V_LOG_SZ_C-1 downto 0) := "10"; - constant IDX3_C : slv(V_LOG_SZ_C-1 downto 0) := "11"; - - variable s : sl; - variable i : slv(V_LOG_SZ_C-1 downto 0); - variable v : slv(T_SZ_C-1 downto 0); - begin - ------------------------------------------------------------------------- - -- 1. Reset state - ------------------------------------------------------------------------- - wait until rst = '0'; - step; - wait for SETTLE_C; - check(notEmpty = '0', "T1 reset: notEmpty = 0 (empty)"); - check(notFull = '1', "T1 reset: notFull = 1"); - checkItem(IDX0_C, '0', (others => '0'), false, "T1 getItem(0)"); - - ------------------------------------------------------------------------- - -- 2/3. Sequential inserts -> indices 0,1,2,3 (LSB-priority free slot) - ------------------------------------------------------------------------- - doInsert(A_C, '1', IDX0_C, true, "T2 insert A"); - wait for SETTLE_C; - check(notEmpty = '1', "T2 after A: notEmpty = 1"); - check(notFull = '1', "T2 after A: notFull = 1"); - checkItem(IDX0_C, '1', A_C, true, "T2 getItem(0)=A"); - checkItem(IDX1_C, '0', (others => '0'), false, "T2 getItem(1) invalid"); - - doInsert(B_C, '1', IDX1_C, true, "T3 insert B"); - doInsert(C_C, '1', IDX2_C, true, "T3 insert C"); - doInsert(D_C, '1', IDX3_C, true, "T3 insert D"); - wait for SETTLE_C; - check(notFull = '0', "T3 after 4 inserts: notFull = 0 (full)"); - check(notEmpty = '1', "T3 after 4 inserts: notEmpty = 1"); - checkItem(IDX3_C, '1', D_C, true, "T3 getItem(3)=D"); - - ------------------------------------------------------------------------- - -- 4. Insert while full -> success = 0, count unchanged - ------------------------------------------------------------------------- - doInsert(E_C, '0', IDX0_C, false, "T4 insert while full"); - wait for SETTLE_C; - check(notFull = '0', "T4 still full after rejected insert"); - - ------------------------------------------------------------------------- - -- 5. Remove idx 1 -> success, slot freed - ------------------------------------------------------------------------- - doRemove(IDX1_C, '1', B_C, true, "T5 remove idx1"); - wait for SETTLE_C; - check(notFull = '1', "T5 after remove: notFull = 1"); - checkItem(IDX1_C, '0', (others => '0'), false, "T5 getItem(1) invalid"); - checkItem(IDX0_C, '1', A_C, true, "T5 getItem(0) still A"); - - ------------------------------------------------------------------------- - -- 6. Remove an already-empty slot -> success = 0 - ------------------------------------------------------------------------- - doRemove(IDX1_C, '0', (others => '0'), false, "T6 remove empty idx1"); - - ------------------------------------------------------------------------- - -- 7. Free-slot reuse -> next insert takes the lowest free index (1) - ------------------------------------------------------------------------- - doInsert(F_C, '1', IDX1_C, true, "T7 insert F reuses idx1"); - wait for SETTLE_C; - checkItem(IDX1_C, '1', F_C, true, "T7 getItem(1)=F"); - check(notFull = '0', "T7 full again after reuse"); - - ------------------------------------------------------------------------- - -- 8. clear() -> flush both FIFOs, reset all tags, then recover - ------------------------------------------------------------------------- - clearEn <= '1'; - step; - clearEn <= '0'; - -- allow clearAll + FIFO synchronous flush to settle - for k in 0 to 4 loop - step; - end loop; - wait for SETTLE_C; - check(notEmpty = '0', "T8 after clear: notEmpty = 0"); - check(notFull = '1', "T8 after clear: notFull = 1"); - checkItem(IDX0_C, '0', (others => '0'), false, "T8 getItem(0) invalid"); - checkItem(IDX3_C, '0', (others => '0'), false, "T8 getItem(3) invalid"); - - -- 9. Recovery: insert after clear -> idx 0, success - doInsert(G_C, '1', IDX0_C, true, "T9 insert after clear"); - wait for SETTLE_C; - check(notEmpty = '1', "T9 after recovery insert: notEmpty = 1"); - checkItem(IDX0_C, '1', G_C, true, "T9 getItem(0)=G"); - - ------------------------------------------------------------------------- - -- Final report - ------------------------------------------------------------------------- - step; - if errCnt = 0 then - report "==== TagVecSrv_tb: ALL CHECKS PASSED ====" severity note; - else - report "==== TagVecSrv_tb: " & integer'image(errCnt) & - " CHECK(S) FAILED ====" severity failure; - end if; - - simDone <= true; - wait; - end process stim; - -end architecture sim; - -------------------------------------------------------------------------------- --- Run notes (GHDL example; requires the SURF library compiled into lib 'surf'): --- # analyze surf sources (StdRtlPkg, Fifo + its FifoSync/FifoAsync deps, ...) --- ghdl -a --std=08 --work=surf --- # analyze the DUT and this testbench --- ghdl -a --std=08 --work=surf out/04-vhdl/TagVecSrv.vhd --- ghdl -a --std=08 out/04-vhdl/TagVecSrv_tb.vhd --- ghdl --elab-run --std=08 TagVecSrv_tb --assert-level=error --- A failing check stops the run with severity failure; otherwise the final --- "ALL CHECKS PASSED" note is printed. -------------------------------------------------------------------------------- diff --git a/ethernet/RoCEv2/rtl/TransportLayer.vhd b/ethernet/RoCEv2/rtl/TransportLayer.vhd index c51853332c..f424dd8ffe 100644 --- a/ethernet/RoCEv2/rtl/TransportLayer.vhd +++ b/ethernet/RoCEv2/rtl/TransportLayer.vhd @@ -84,7 +84,11 @@ entity TransportLayer is -- Software contract: never post READ/atomic WRs. EN_TX_G : boolean := true; EN_RX_G : boolean := true; - EN_READ_G : boolean := true); + EN_READ_G : boolean := true; + -- MAX_QP_WR (Settings.bsv:15; BSV default 32): max pending work requests + -- per QP (effective in-flight window is MAX_QP_WR_G-1, one slot + -- reserved). Must be a power of 2. + MAX_QP_WR_G : positive := 4); port ( clk : in sl; rst : in sl; -- active-high synchronous reset @@ -365,7 +369,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => DATA_STREAM_W_C, ADDR_WIDTH_G => 4) port map ( @@ -406,7 +410,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => WORK_REQ_W_C, ADDR_WIDTH_G => 4) port map ( @@ -448,7 +452,7 @@ begin TPD_G => TPD_G, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => RECV_REQ_W_C, ADDR_WIDTH_G => 4) port map ( @@ -612,10 +616,11 @@ begin GEN_QP : for i in 0 to MAX_QP_G-1 generate U_Qp : entity surf.Qp generic map ( - TPD_G => TPD_G, - EN_TX_G => EN_TX_G, - EN_RX_G => EN_RX_G, - EN_READ_G => EN_READ_G) + TPD_G => TPD_G, + EN_TX_G => EN_TX_G, + EN_RX_G => EN_RX_G, + EN_READ_G => EN_READ_G, + MAX_QP_WR_G => MAX_QP_WR_G) port map ( clk => clk, rst => rst, diff --git a/ethernet/RoCEv2/rtl/WorkCompGenRq.vhd b/ethernet/RoCEv2/rtl/WorkCompGenRq.vhd index 61fd7885fa..1cd87d5148 100644 --- a/ethernet/RoCEv2/rtl/WorkCompGenRq.vhd +++ b/ethernet/RoCEv2/rtl/WorkCompGenRq.vhd @@ -81,7 +81,7 @@ -- workCompPipeOut (downstream drives rd_en). -- U_WcStatusQ4SQ : surf.Fifo DATA_WIDTH_G=5 ADDR_WIDTH_G=4 -- WorkCompStatus ; mkFIFOF. DEAD (no reader) — see above. --- Block-RAM FWFT cold latency is 2 cycles (DOB reg) — see tb-spec §8. +-- Distributed-RAM FWFT cold latency is 1 cycle (block RAM was 2) — see tb-spec §8. -- -- Type widths (BSV deriving(Bits), first-field-at-MSB; traced from -- DataTypes.bsv/Headers.bsv/Settings.bsv — see OQ-FSM-H2DS-04 packing rule): @@ -233,7 +233,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 428, ADDR_WIDTH_G => 4) port map ( @@ -271,7 +271,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 428, ADDR_WIDTH_G => 4) port map ( @@ -309,7 +309,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 222, ADDR_WIDTH_G => 5) port map ( @@ -351,7 +351,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 5, ADDR_WIDTH_G => 4) port map ( diff --git a/ethernet/RoCEv2/rtl/WorkCompGenSq.vhd b/ethernet/RoCEv2/rtl/WorkCompGenSq.vhd index 62c84d74d3..d32febaa5e 100644 --- a/ethernet/RoCEv2/rtl/WorkCompGenSq.vhd +++ b/ethernet/RoCEv2/rtl/WorkCompGenSq.vhd @@ -69,7 +69,7 @@ -- U_WorkCompOutQ4SQ : surf.Fifo DATA_WIDTH_G=222 ADDR_WIDTH_G=5 (depth 32) -- WorkComp ; mkSizedFIFOF MAX_CQE. rd side exported -- as workCompPipeOut (downstream drives rd_en). --- Block-RAM FWFT cold latency is 2 cycles (DOB reg) — see tb-spec §8. +-- Distributed-RAM FWFT cold latency is 1 cycle (block RAM was 2) — see tb-spec §8. -- -- Type widths (BSV deriving(Bits), first-field-at-MSB; traced from -- DataTypes.bsv/Headers.bsv/Settings.bsv): @@ -267,7 +267,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 857, ADDR_WIDTH_G => 4) port map ( @@ -305,7 +305,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 857, ADDR_WIDTH_G => 4) port map ( @@ -343,7 +343,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => 222, ADDR_WIDTH_G => 5) port map ( diff --git a/ethernet/RoCEv2/rtl/WorkReqAndRecvReqDispatcher.vhd b/ethernet/RoCEv2/rtl/WorkReqAndRecvReqDispatcher.vhd index 5a4ce02c90..0ad99cbebc 100644 --- a/ethernet/RoCEv2/rtl/WorkReqAndRecvReqDispatcher.vhd +++ b/ethernet/RoCEv2/rtl/WorkReqAndRecvReqDispatcher.vhd @@ -173,7 +173,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => WORK_REQ_WIDTH_C, ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C) port map ( @@ -221,7 +221,7 @@ begin RST_ASYNC_G => false, GEN_SYNC_FIFO_G => true, FWFT_EN_G => true, - MEMORY_TYPE_G => "block", + MEMORY_TYPE_G => "distributed", DATA_WIDTH_G => RECV_REQ_WIDTH_C, ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C) port map ( From a0c00522ab928597cf16495ecba956a7c58dc2cc Mon Sep 17 00:00:00 2001 From: FilMarini Date: Thu, 16 Jul 2026 10:50:26 +0200 Subject: [PATCH 7/8] replaced blue-crc with SURF's own CRC module --- .../EthMacCore/rtl/EthMacCrcAxiStream.vhd | 308 + ethernet/RoCEv2/README.md | 19 - .../blue-crc/mkCrcRawAxiStreamCustomRecv.v | 7330 ----------------- .../blue-crc/mkCrcRawAxiStreamCustomSend.v | 7304 ---------------- ethernet/RoCEv2/blue-crc/tab/crc_tab_0.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_1.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_10.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_11.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_12.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_13.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_14.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_15.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_16.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_17.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_18.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_19.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_2.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_20.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_21.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_22.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_23.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_24.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_25.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_26.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_27.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_28.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_29.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_3.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_30.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_31.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_32.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_33.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_34.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_35.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_4.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_5.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_6.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_7.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_8.mem | 256 - ethernet/RoCEv2/blue-crc/tab/crc_tab_9.mem | 256 - ethernet/RoCEv2/blue-lib/BRAM2.v | 94 - ethernet/RoCEv2/blue-lib/BypassWire.v | 13 - ethernet/RoCEv2/blue-lib/CRegN5.v | 103 - ethernet/RoCEv2/blue-lib/CRegUN5.v | 92 - ethernet/RoCEv2/blue-lib/ConfigRegN.v | 50 - ethernet/RoCEv2/blue-lib/Counter.v | 75 - ethernet/RoCEv2/blue-lib/FIFO2.v | 153 - ethernet/RoCEv2/blue-lib/FIFO20.v | 110 - ethernet/RoCEv2/blue-lib/README.md | 3 - ethernet/RoCEv2/blue-lib/RWire.v | 22 - ethernet/RoCEv2/blue-lib/RWire0.v | 14 - ethernet/RoCEv2/blue-lib/RegN.v | 50 - ethernet/RoCEv2/blue-lib/RegUN.v | 35 - ethernet/RoCEv2/blue-lib/SizedFIFO.v | 258 - ethernet/RoCEv2/ruckus.tcl | 9 +- 55 files changed, 309 insertions(+), 24949 deletions(-) create mode 100644 ethernet/EthMacCore/rtl/EthMacCrcAxiStream.vhd delete mode 100644 ethernet/RoCEv2/README.md delete mode 100644 ethernet/RoCEv2/blue-crc/mkCrcRawAxiStreamCustomRecv.v delete mode 100644 ethernet/RoCEv2/blue-crc/mkCrcRawAxiStreamCustomSend.v delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_0.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_1.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_10.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_11.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_12.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_13.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_14.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_15.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_16.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_17.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_18.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_19.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_2.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_20.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_21.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_22.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_23.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_24.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_25.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_26.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_27.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_28.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_29.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_3.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_30.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_31.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_32.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_33.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_34.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_35.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_4.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_5.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_6.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_7.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_8.mem delete mode 100644 ethernet/RoCEv2/blue-crc/tab/crc_tab_9.mem delete mode 100644 ethernet/RoCEv2/blue-lib/BRAM2.v delete mode 100644 ethernet/RoCEv2/blue-lib/BypassWire.v delete mode 100644 ethernet/RoCEv2/blue-lib/CRegN5.v delete mode 100644 ethernet/RoCEv2/blue-lib/CRegUN5.v delete mode 100644 ethernet/RoCEv2/blue-lib/ConfigRegN.v delete mode 100644 ethernet/RoCEv2/blue-lib/Counter.v delete mode 100644 ethernet/RoCEv2/blue-lib/FIFO2.v delete mode 100644 ethernet/RoCEv2/blue-lib/FIFO20.v delete mode 100644 ethernet/RoCEv2/blue-lib/README.md delete mode 100644 ethernet/RoCEv2/blue-lib/RWire.v delete mode 100644 ethernet/RoCEv2/blue-lib/RWire0.v delete mode 100644 ethernet/RoCEv2/blue-lib/RegN.v delete mode 100644 ethernet/RoCEv2/blue-lib/RegUN.v delete mode 100644 ethernet/RoCEv2/blue-lib/SizedFIFO.v diff --git a/ethernet/EthMacCore/rtl/EthMacCrcAxiStream.vhd b/ethernet/EthMacCore/rtl/EthMacCrcAxiStream.vhd new file mode 100644 index 0000000000..a0a149cf66 --- /dev/null +++ b/ethernet/EthMacCore/rtl/EthMacCrcAxiStream.vhd @@ -0,0 +1,308 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: AXI-Stream CRC-32 (IEEE 802.3) calculator around +-- surf.EthCrc32Parallel. Sinks a 16-byte EMAC-style stream and +-- emits ONE 4-byte beat per packet carrying the CRC result. +-- CRC_MODE_G = "SEND": tData(31:0) = CRC-32 of the payload, +-- first-on-wire CRC byte in tData(7:0) (zlib.crc32 order). +-- CRC_MODE_G = "RECV": input is payload||receivedCRC; +-- tData(31:0) = x"00000000" iff the trailer is correct +-- (residue method: engine output xor RECV_RESIDUE_C). +------------------------------------------------------------------------------- +-- Generated by: bsv-icrc-to-vhdl Stage 4 (vhdl-emit) +-- BSV source : src-bsv/blue-crc/src/CrcAxiStream.bsv +-- (mkCrcAxiStreamFifoOut, mkCrcAxiStream, mkCrcRawAxiStream) +-- src-bsv/blue-crc/src/CrcAxiStreamCustom.bsv (tops) +-- Substitution: per SURF-CRC-REPLACEMENT-PLAN.md the blue-crc 8-stage +-- table-driven engine (36 file-initialized ROMs) is REPLACED by +-- surf.EthCrc32Parallel (poly 0x04C11DB7, reflect-in/out and +-- final inversion hard-coded in the engine); this wrapper only +-- reproduces blue-crc's external AXI-Stream contract. +------------------------------------------------------------------------------- +-- 2026-07-15 rework (udploop-crc-stall-frame-loss-issue.md): the original +-- 4-state FSM held sAxisSlave.tReady LOW from tLast until its single result +-- beat was consumed. On the MAC RX path the consumer (EthMacRxCheckICrc) +-- consumes a result only when it STARTS draining that frame, so the stall +-- stretched to a full frame-drain; the RoCE RX branch has no upstream flow +-- control (EthMacRxRoCEv2 DeMux slave open) and beats presented meanwhile +-- were silently destroyed. blue-crc never back-pressured (pipelined engine + +-- result FIFO: mkCrcAxiStreamFifoOut). This rework restores that contract: +-- * input is ALWAYS ready (guarded only by result-FIFO prog_full, which is +-- unreachable in practice: results outstanding <= frames resident in the +-- downstream delay FIFO); +-- * every accepted beat is folded immediately; a packet's final CRC is +-- captured 2 cycles after its tLast beat (beat presented at N folds +-- during N+1; r.crc final and stable during N+2 even if the next packet +-- folds back-to-back, since that overwrite lands on the N+2 -> N+3 edge) +-- into a 256-deep result FIFO; +-- * the engine is re-seeded per packet by a registered crcReset pulse +-- aligned to the FOLD cycle of each packet's first beat (crcReset is a +-- combinational prevCrc mux in the fold cycle; in idle cycles it +-- synchronously loads CRC_INIT, which also covers null first beats). +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; + +entity EthMacCrcAxiStream is + generic ( + TPD_G : time := 1 ns; + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_ASYNC_G : boolean := false; + CRC_MODE_G : string := "SEND"); -- "SEND" or "RECV" + port ( + -- Clock and Reset + ethClk : in sl; + ethRst : in sl; + -- Inbound data to be CRC'd (16-byte EMAC-style stream, TKEEP_COMP_C) + sAxisMaster : in AxiStreamMasterType; + sAxisSlave : out AxiStreamSlaveType; + -- Outbound CRC result (one 4-byte beat per packet) + mAxisMaster : out AxiStreamMasterType; + mAxisSlave : in AxiStreamSlaveType); +end EthMacCrcAxiStream; + +architecture rtl of EthMacCrcAxiStream is + + -- Input stream geometry (only TDATA_BYTES_C/TKEEP_MODE_C are consumed, + -- via getTKeep); upstream guarantees LSB-contiguous tKeep (TKEEP_COMP_C) + constant CRC_IN_AXIS_CONFIG_C : AxiStreamConfigType := ( + TSTRB_EN_C => false, + TDATA_BYTES_C => 16, + TDEST_BITS_C => 0, + TID_BITS_C => 0, + TKEEP_MODE_C => TKEEP_COMP_C, + TUSER_BITS_C => 1, + TUSER_MODE_C => TUSER_NONE_C); + + -- Output stream geometry: single 4-byte beat (tKeep = x"F") + constant CRC_OUT_AXIS_CONFIG_C : AxiStreamConfigType := ( + TSTRB_EN_C => false, + TDATA_BYTES_C => 4, + TDEST_BITS_C => 0, + TID_BITS_C => 0, + TKEEP_MODE_C => TKEEP_COMP_C, + TUSER_BITS_C => 1, + TUSER_MODE_C => TUSER_NONE_C); + + -- Reflected CRC-32 residue of message||correctCRC: for any correct RECV + -- packet the engine output equals this constant, so XOR-ing it yields the + -- zero-on-pass contract of EthMacRxCheckICrc. Verified numerically by the + -- Stage 5 golden-vector generator (zlib.crc32(msg + crc_le) = 0x2144DF1C). + constant RECV_RESIDUE_C : slv(31 downto 0) := x"2144DF1C"; + + -- Result FIFO sizing: results outstanding are bounded by whole frames + -- resident in the RX delay FIFO (1024 beats / >=4-beat min frame = 256). + -- prog_full backs tReady off with margin for the 2 in-flight captures. + constant RESULT_FIFO_ADDR_WIDTH_C : positive := 8; + constant RESULT_FIFO_FULL_THRES_C : positive := 2**RESULT_FIFO_ADDR_WIDTH_C - 8; + + type RegType is record + sofPending : sl; -- next accepted beat starts a packet + seedPulse : sl; -- high during that beat's FOLD cycle + lastD1 : sl; -- tLast accepted 1 cycle ago + lastD2 : sl; -- tLast accepted 2 cycles ago: capture + txMaster : AxiStreamMasterType; + end record RegType; + + constant REG_INIT_C : RegType := ( + sofPending => '1', + seedPulse => '0', + lastD1 => '0', + lastD2 => '0', + txMaster => AXI_STREAM_MASTER_INIT_C); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal crcRst : sl; + signal crcDataValid : sl; + signal crcDataWidth : slv(3 downto 0); + signal crcIn : slv(127 downto 0); + signal crcOut : slv(31 downto 0); + + signal fifoWrEn : sl; + signal fifoDin : slv(31 downto 0); + signal fifoProgFull : sl; + signal fifoRdEn : sl; + signal fifoDout : slv(31 downto 0); + signal fifoValid : sl; + +begin + + assert (CRC_MODE_G = "SEND") or (CRC_MODE_G = "RECV") + report "CRC_MODE_G must be ""SEND"" or ""RECV""" severity failure; + + -- First-on-wire byte tData(7:0) lands in the engine's MSByte lane + -- (analogue of blue-crc's swapEndian in rule preProcess); inactive byte + -- lanes are zeroed inside the engine via crcDataWidth (no bitMask needed) + crcIn <= endianSwap(sAxisMaster.tData(127 downto 0)); + + U_Crc : entity surf.EthCrc32Parallel + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '1', -- crcRst generated active-high below + USE_DSP_G => false, -- true is untested upstream + CRC_INIT_G => x"FFFFFFFF", + BYTE_WIDTH_G => 16) + port map ( + crcClk => ethClk, -- [in] + crcReset => crcRst, -- [in] + crcDataValid => crcDataValid, -- [in] + crcDataWidth => crcDataWidth, -- [in] + crcIn => crcIn, -- [in] + crcOut => crcOut); -- [out] + + -- Per-packet result queue (blue-crc's finalCrcResBuf analogue). rd side is + -- the registered mAxis output stage below; wr side is the lastD2 capture. + U_ResultFifo : entity surf.Fifo + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => RST_POLARITY_G, + RST_ASYNC_G => RST_ASYNC_G, + GEN_SYNC_FIFO_G => true, + FWFT_EN_G => true, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 32, + ADDR_WIDTH_G => RESULT_FIFO_ADDR_WIDTH_C, + FULL_THRES_G => RESULT_FIFO_FULL_THRES_C) + port map ( + rst => ethRst, + wr_clk => ethClk, + wr_en => fifoWrEn, + din => fifoDin, + wr_data_count => open, + wr_ack => open, + overflow => open, + prog_full => fifoProgFull, + almost_full => open, + full => open, + not_full => open, + rd_clk => ethClk, + rd_en => fifoRdEn, + dout => fifoDout, + rd_data_count => open, + valid => fifoValid, + underflow => open, + prog_empty => open, + almost_empty => open, + empty => open); + + comb : process (crcOut, ethRst, fifoDout, fifoProgFull, fifoValid, + mAxisSlave, r, sAxisMaster) is + variable v : RegType; + variable keepVar : natural range 0 to 16; + variable tReadyVar : sl; + variable acceptVar : sl; + variable resultVar : slv(31 downto 0); + begin + -- Latch the current value + v := r; + + -- Input always ready; prog_full is unreachable in normal operation and + -- only guards the capture pipeline against a pathological result burst + if (fifoProgFull = '0') and (ethRst /= RST_POLARITY_G) then + tReadyVar := '1'; + else + tReadyVar := '0'; + end if; + acceptVar := sAxisMaster.tValid and tReadyVar; + + -- Valid byte count of the current input beat (TKEEP_COMP_C) + keepVar := getTKeep(sAxisMaster.tKeep(15 downto 0), CRC_IN_AXIS_CONFIG_C); + + -- Engine drives: fold every accepted non-null beat (the engine + -- registers its inputs; the fold happens the NEXT cycle) + crcDataValid <= '0'; + if (keepVar /= 0) then + crcDataWidth <= toSlv(keepVar-1, 4); + else + -- don't care: crcDataValid is gated off for null beats + crcDataWidth <= (others => '0'); + end if; + if (acceptVar = '1') and (keepVar /= 0) then + crcDataValid <= '1'; + end if; + + -- Packet tracking: + -- seedPulse -> crcReset during the fold cycle of a first beat (for a + -- null first beat there is no fold and the engine's idle path loads + -- CRC_INIT instead — same outcome); + -- lastD1/lastD2 -> capture r.crc two cycles after the tLast beat. + v.seedPulse := acceptVar and r.sofPending; + v.lastD1 := acceptVar and sAxisMaster.tLast; + v.lastD2 := r.lastD1; + if (acceptVar = '1') then + v.sofPending := sAxisMaster.tLast; + end if; + + -- Result capture into the FIFO (crcOut = final CRC of the packet whose + -- tLast was accepted 2 cycles ago; a back-to-back next fold overwrites + -- r.crc only on this cycle's closing edge, after din is sampled) + if (CRC_MODE_G = "RECV") then + resultVar := endianSwap(crcOut) xor RECV_RESIDUE_C; + else + resultVar := endianSwap(crcOut); + end if; + fifoWrEn <= r.lastD2; + fifoDin <= resultVar; + + -- Registered output stage: one 4-byte beat per queued result + fifoRdEn <= '0'; + if (mAxisSlave.tReady = '1') then + v.txMaster.tValid := '0'; + end if; + if (v.txMaster.tValid = '0') and (fifoValid = '1') then + fifoRdEn <= '1'; + v.txMaster := axiStreamMasterInit(CRC_OUT_AXIS_CONFIG_C); + v.txMaster.tValid := '1'; + v.txMaster.tLast := '1'; + v.txMaster.tData(31 downto 0) := fifoDout; + end if; + + -- Combinational engine re-seed: fold-cycle pulse per packet, plus the + -- whole duration of ethRst (recovers mid-packet aborts; the engine has + -- no reset port of its own — while idle it synchronously loads INIT) + if (r.seedPulse = '1') or (ethRst = RST_POLARITY_G) then + crcRst <= '1'; + else + crcRst <= '0'; + end if; + + -- Synchronous reset + if (RST_ASYNC_G = false) and (ethRst = RST_POLARITY_G) then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + -- Outputs + sAxisSlave.tReady <= tReadyVar; + mAxisMaster <= r.txMaster; + + end process comb; + + seq : process (ethClk, ethRst) is + begin + if (RST_ASYNC_G) and (ethRst = RST_POLARITY_G) then + r <= REG_INIT_C after TPD_G; + elsif rising_edge(ethClk) then + r <= rin after TPD_G; + end if; + end process seq; + +end rtl; diff --git a/ethernet/RoCEv2/README.md b/ethernet/RoCEv2/README.md deleted file mode 100644 index a6d40bdd3b..0000000000 --- a/ethernet/RoCEv2/README.md +++ /dev/null @@ -1,19 +0,0 @@ -# Hardware Implementation of RoCEv2 Engine -This folder contains files generated from Bluespec SystemVerilog (BSV) source code located in different repositories: [blue-rdma](https://github.com/datenlord/blue-rdma), [blue-crc](https://github.com/datenlord/blue-crc) - -## Description -The verilog files in the `blue-rdma` and `blue-crc` folders represent a hardware implementation of the RoCEv2 engine and a iCRC calculation engine, respectively. -These files have been generated from a modified version of the BSV sources. The forked repo with the modifed version can be found [here](https://github.com/FilMarini/blue-rdma) - -The modifications consists in: - -* **Receiving Path Removed**: The RoCEv2 engine's receiving path as well as support for RDMA-Read operations has been entirely removed. - -* **Resource Optimization**: By removing the receiving path, the core now consumes fewer hardware resources, allowing it to fit on smaller FPGAs. - -* **Fixed settings**: the generated verilog has support for 1 PD, 1 QP, 2 CQ and 2 MR, in order to be as light as possible. To change these settings, the core needs to be re-generated from its original or modified repo - -## License information -The BSV-generated files follow the licensing terms from the original repositories. A copy of the original license can be found in the folders. - -Please ensure compliance with both licenses when using or modifying these files. diff --git a/ethernet/RoCEv2/blue-crc/mkCrcRawAxiStreamCustomRecv.v b/ethernet/RoCEv2/blue-crc/mkCrcRawAxiStreamCustomRecv.v deleted file mode 100644 index 8eea77c6f1..0000000000 --- a/ethernet/RoCEv2/blue-crc/mkCrcRawAxiStreamCustomRecv.v +++ /dev/null @@ -1,7330 +0,0 @@ -/* - * ------------------------------------------------------------------- - * This Verilog file has been automatically generated from a core originally written - * in Bluespec SystemVerilog (BSV). The original source code can be found at: - * - * Repository: https://github.com/datenlord/blue-crc - * Author: DatenLord (https://datenlord.github.io/) - * ------------------------------------------------------------------- - */ -// -// Generated by Bluespec Compiler, version 2023.01 (build 52adafa) -// -// On Wed Sep 11 15:19:22 CEST 2024 -// -// -// Ports: -// Name I/O size props -// s_axis_tready O 1 reg -// m_crc_stream_data O 32 reg -// m_crc_stream_valid O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// s_axis_tvalid I 1 -// s_axis_tdata I 256 reg -// s_axis_tkeep I 32 reg -// s_axis_tlast I 1 reg -// s_axis_tuser I 1 reg -// m_crc_stream_ready I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCrcRawAxiStreamCustomRecv(CLK, - RST_N, - - s_axis_tvalid, - s_axis_tdata, - s_axis_tkeep, - s_axis_tlast, - s_axis_tuser, - - s_axis_tready, - - m_crc_stream_data, - - m_crc_stream_valid, - - m_crc_stream_ready); - input CLK; - input RST_N; - - // action method rawCrcReq_tValid - input s_axis_tvalid; - input [255 : 0] s_axis_tdata; - input [31 : 0] s_axis_tkeep; - input s_axis_tlast; - input s_axis_tuser; - - // value method rawCrcReq_tReady - output s_axis_tready; - - // value method rawCrcResp_data - output [31 : 0] m_crc_stream_data; - - // value method rawCrcResp_valid - output m_crc_stream_valid; - - // action method rawCrcResp_ready - input m_crc_stream_ready; - - // signals for module outputs - wire [31 : 0] m_crc_stream_data; - wire m_crc_stream_valid, s_axis_tready; - - // inlined wires - wire [289 : 0] crc_rawAxiStreamSlave_rawBus_rawBus_dataW_wget; - - // register crc_crcAxiStream_crcRespFifoOut_interCrcRes - reg [31 : 0] crc_crcAxiStream_crcRespFifoOut_interCrcRes; - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_interCrcRes_D_IN; - wire crc_crcAxiStream_crcRespFifoOut_interCrcRes_EN; - - // register crc_crcAxiStream_crcRespFifoOut_isFirstFlag - reg crc_crcAxiStream_crcRespFifoOut_isFirstFlag; - wire crc_crcAxiStream_crcRespFifoOut_isFirstFlag_D_IN, - crc_crcAxiStream_crcRespFifoOut_isFirstFlag_EN; - - // ports of submodule crc_crcAxiStream_crcReqBuf - wire [289 : 0] crc_crcAxiStream_crcReqBuf_D_IN, - crc_crcAxiStream_crcReqBuf_D_OUT; - wire crc_crcAxiStream_crcReqBuf_CLR, - crc_crcAxiStream_crcReqBuf_DEQ, - crc_crcAxiStream_crcReqBuf_EMPTY_N, - crc_crcAxiStream_crcReqBuf_ENQ, - crc_crcAxiStream_crcReqBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf - wire [71 : 0] crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_preProcessResBuf - wire [263 : 0] crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf - wire [1031 : 0] crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf - wire [1183 : 0] crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf - wire [39 : 0] crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf - wire [263 : 0] crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf - wire [319 : 0] crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_FULL_N; - - // ports of submodule crc_rawAxiStreamSlave_rawBus_fifo - wire [289 : 0] crc_rawAxiStreamSlave_rawBus_fifo_D_IN, - crc_rawAxiStreamSlave_rawBus_fifo_D_OUT; - wire crc_rawAxiStreamSlave_rawBus_fifo_CLR, - crc_rawAxiStreamSlave_rawBus_fifo_DEQ, - crc_rawAxiStreamSlave_rawBus_fifo_EMPTY_N, - crc_rawAxiStreamSlave_rawBus_fifo_ENQ, - crc_rawAxiStreamSlave_rawBus_fifo_FULL_N; - - // ports of submodule crc_rawBusMaster_fifo - wire [31 : 0] crc_rawBusMaster_fifo_D_IN, crc_rawBusMaster_fifo_D_OUT; - wire crc_rawBusMaster_fifo_CLR, - crc_rawBusMaster_fifo_DEQ, - crc_rawBusMaster_fifo_EMPTY_N, - crc_rawBusMaster_fifo_ENQ, - crc_rawBusMaster_fifo_FULL_N; - - // remaining internal signals - reg [7 : 0] CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40, - CASE_shiftAmt70081_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39, - CASE_shiftAmt70081_0_0_1_0_2_crc_crcAxiStream__ETC__q38, - CASE_shiftAmt70081_0_0_1_crc_crcAxiStream_crcR_ETC__q37, - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q33, - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q34, - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q35, - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q36; - wire [287 : 0] interCrc__h170060; - wire [255 : 0] IF_crc_crcAxiStream_crcReqBufD_OUT_BIT_2_THEN_ETC__q69, - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139, - preProcessRes_data__h13182, - x_data__h64227; - wire [31 : 0] crc1__h169284, - crc1__h169800, - crc2__h169285, - crc2__h169801, - crcRes__h159777, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146, - firstHalfRes__h159800, - firstHalfRes__h159809, - firstHalfRes__h159818, - firstHalfRes__h159827, - firstHalfRes__h162162, - firstHalfRes__h162946, - firstHalfRes__h162955, - firstHalfRes__h164036, - firstHalfRes__h164820, - firstHalfRes__h164829, - firstHalfRes__h164838, - firstHalfRes__h166480, - firstHalfRes__h167264, - firstHalfRes__h167273, - firstHalfRes__h168354, - firstHalfRes__h169280, - firstHalfRes__h287945, - firstHalfRes__h287954, - firstHalfRes__h287963, - firstHalfRes__h287972, - firstHalfRes__h287981, - firstHalfRes__h290879, - firstHalfRes__h291663, - firstHalfRes__h291672, - firstHalfRes__h291681, - firstHalfRes__h293175, - firstHalfRes__h293959, - firstHalfRes__h293968, - firstHalfRes__h293977, - firstHalfRes__h293986, - firstHalfRes__h296107, - firstHalfRes__h296891, - firstHalfRes__h296900, - firstHalfRes__h296909, - firstHalfRes__h298403, - interCrc__h287602, - nextInterCrc__h169186, - nextInterCrc__h169187, - secondHalfRes__h159801, - secondHalfRes__h159810, - secondHalfRes__h159819, - secondHalfRes__h159828, - secondHalfRes__h162163, - secondHalfRes__h162947, - secondHalfRes__h162956, - secondHalfRes__h164037, - secondHalfRes__h164821, - secondHalfRes__h164830, - secondHalfRes__h164839, - secondHalfRes__h166481, - secondHalfRes__h167265, - secondHalfRes__h167274, - secondHalfRes__h168355, - secondHalfRes__h169281, - secondHalfRes__h287946, - secondHalfRes__h287955, - secondHalfRes__h287964, - secondHalfRes__h287973, - secondHalfRes__h290880, - secondHalfRes__h291664, - secondHalfRes__h291673, - secondHalfRes__h293176, - secondHalfRes__h293960, - secondHalfRes__h293969, - secondHalfRes__h293978, - secondHalfRes__h296108, - secondHalfRes__h296892, - secondHalfRes__h296901, - secondHalfRes__h298404; - wire [6 : 0] shiftAmt___1__h171513, shiftAmt__h170059, shiftAmt__h170081; - wire [5 : 0] ctrlSig_shiftAmt__h59003; - - // value method rawCrcReq_tReady - assign s_axis_tready = crc_rawAxiStreamSlave_rawBus_fifo_FULL_N ; - - // value method rawCrcResp_data - assign m_crc_stream_data = crc_rawBusMaster_fifo_D_OUT ; - - // value method rawCrcResp_valid - assign m_crc_stream_valid = crc_rawBusMaster_fifo_EMPTY_N ; - - // submodule crc_crcAxiStream_crcReqBuf - FIFO2 #(.width(32'd290), - .guarded(1'd1)) crc_crcAxiStream_crcReqBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcReqBuf_D_IN), - .ENQ(crc_crcAxiStream_crcReqBuf_ENQ), - .DEQ(crc_crcAxiStream_crcReqBuf_DEQ), - .CLR(crc_crcAxiStream_crcReqBuf_CLR), - .D_OUT(crc_crcAxiStream_crcReqBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcReqBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcReqBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf - FIFO2 #(.width(32'd72), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_0.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_10.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_11.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_12.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_13.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_14.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_15.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_16.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_17.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_18.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_19.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_1.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_20.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_21.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_22.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_23.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_24.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_25.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_26.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_27.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_28.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_29.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_2.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_30.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_31.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_32.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_33.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_34.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_35.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_3.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_4.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_5.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_6.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_7.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_8.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable - LookupTableLoadRecv #(.file("crc_tab_9.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf - FIFO2 #(.width(32'd32), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_preProcessResBuf - FIFO2 #(.width(32'd264), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_preProcessResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf - FIFO2 #(.width(32'd1032), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf - FIFO2 #(.width(32'd1184), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf - FIFO2 #(.width(32'd40), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf - FIFO2 #(.width(32'd264), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf - FIFO2 #(.width(32'd320), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_EMPTY_N)); - - // submodule crc_rawAxiStreamSlave_rawBus_fifo - FIFO2 #(.width(32'd290), - .guarded(1'd1)) crc_rawAxiStreamSlave_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_rawAxiStreamSlave_rawBus_fifo_D_IN), - .ENQ(crc_rawAxiStreamSlave_rawBus_fifo_ENQ), - .DEQ(crc_rawAxiStreamSlave_rawBus_fifo_DEQ), - .CLR(crc_rawAxiStreamSlave_rawBus_fifo_CLR), - .D_OUT(crc_rawAxiStreamSlave_rawBus_fifo_D_OUT), - .FULL_N(crc_rawAxiStreamSlave_rawBus_fifo_FULL_N), - .EMPTY_N(crc_rawAxiStreamSlave_rawBus_fifo_EMPTY_N)); - - // submodule crc_rawBusMaster_fifo - FIFO2 #(.width(32'd32), .guarded(1'd1)) crc_rawBusMaster_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_rawBusMaster_fifo_D_IN), - .ENQ(crc_rawBusMaster_fifo_ENQ), - .DEQ(crc_rawBusMaster_fifo_DEQ), - .CLR(crc_rawBusMaster_fifo_CLR), - .D_OUT(crc_rawBusMaster_fifo_D_OUT), - .FULL_N(crc_rawBusMaster_fifo_FULL_N), - .EMPTY_N(crc_rawBusMaster_fifo_EMPTY_N)); - - // inlined wires - assign crc_rawAxiStreamSlave_rawBus_rawBus_dataW_wget = - { s_axis_tdata, s_axis_tkeep, s_axis_tlast, s_axis_tuser } ; - - // register crc_crcAxiStream_crcRespFifoOut_interCrcRes - assign crc_crcAxiStream_crcRespFifoOut_interCrcRes_D_IN = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] ? - 32'hFFFFFFFF : - nextInterCrc__h169187 ; - assign crc_crcAxiStream_crcRespFifoOut_interCrcRes_EN = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N && - (!crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] || - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N) ; - - // register crc_crcAxiStream_crcRespFifoOut_isFirstFlag - assign crc_crcAxiStream_crcRespFifoOut_isFirstFlag_D_IN = - crc_crcAxiStream_crcReqBuf_D_OUT[1] ; - assign crc_crcAxiStream_crcRespFifoOut_isFirstFlag_EN = - crc_crcAxiStream_crcReqBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N ; - - // submodule crc_crcAxiStream_crcReqBuf - assign crc_crcAxiStream_crcReqBuf_D_IN = - crc_rawAxiStreamSlave_rawBus_fifo_D_OUT ; - assign crc_crcAxiStream_crcReqBuf_ENQ = - crc_rawAxiStreamSlave_rawBus_fifo_EMPTY_N && - crc_crcAxiStream_crcReqBuf_FULL_N ; - assign crc_crcAxiStream_crcReqBuf_DEQ = - crc_crcAxiStream_crcReqBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N ; - assign crc_crcAxiStream_crcReqBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf - assign crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_IN = - { crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[39:8], - crc_crcAxiStream_crcRespFifoOut_interCrcRes, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7:0] } ; - assign crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N && - (!crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] || - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N) && - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] ; - assign crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[15:8] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[7:0] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[95:88] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[87:80] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[103:96] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[95:88] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[111:104] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[103:96] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[119:112] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[111:104] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[127:120] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[119:112] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[135:128] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[127:120] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[143:136] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[135:128] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[151:144] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[143:136] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[159:152] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[151:144] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[167:160] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[159:152] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[23:16] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[15:8] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[175:168] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[167:160] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[183:176] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[175:168] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[191:184] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[183:176] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[199:192] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[191:184] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[207:200] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[199:192] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[215:208] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[207:200] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[223:216] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[215:208] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[231:224] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[223:216] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[239:232] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[7:0] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[231:224] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[247:240] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[15:8] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[239:232] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[31:24] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[23:16] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[255:248] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[23:16] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[247:240] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[263:256] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[31:24] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[255:248] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_1 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[7:0] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[263:256] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_1 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[15:8] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[271:264] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_1 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[23:16] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[279:272] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_1 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[31:24] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[287:280] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[39:32] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[31:24] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[47:40] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[39:32] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[55:48] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[47:40] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[63:56] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[55:48] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[71:64] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[63:56] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[79:72] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[71:64] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[87:80] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[79:72] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf - assign crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_IN = - { ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[0], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[1], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[2], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[3], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[4], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[5], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[6], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[7], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[8], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[9], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[10], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[11], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[12], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[13], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[14], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[15], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[16], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[17], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[18], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[19], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[20], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[21], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[22], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[23], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[24], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[25], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[26], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[27], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[28], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[29], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[30], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146[31] } ; - assign crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_EMPTY_N && - crc_rawBusMaster_fifo_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_preProcessResBuf - assign crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_IN = - { preProcessRes_data__h13182, - crc_crcAxiStream_crcReqBuf_D_OUT[1], - crc_crcAxiStream_crcRespFifoOut_isFirstFlag, - ctrlSig_shiftAmt__h59003 } ; - assign crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_ENQ = - crc_crcAxiStream_crcReqBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf - assign crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_IN = - { crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[7:0] } ; - assign crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_IN = - { crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[319:288] } ; - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf - assign crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_IN = - { crcRes__h159777, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[7:0] } ; - assign crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N && - (!crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] || - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N) ; - assign crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf - assign crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_IN = - { x_data__h64227, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[7:0] } ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf - assign crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_IN = - { crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[71:40], - interCrc__h170060 } ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_CLR = 1'b0 ; - - // submodule crc_rawAxiStreamSlave_rawBus_fifo - assign crc_rawAxiStreamSlave_rawBus_fifo_D_IN = - crc_rawAxiStreamSlave_rawBus_rawBus_dataW_wget ; - assign crc_rawAxiStreamSlave_rawBus_fifo_ENQ = - crc_rawAxiStreamSlave_rawBus_fifo_FULL_N && s_axis_tvalid ; - assign crc_rawAxiStreamSlave_rawBus_fifo_DEQ = - crc_rawAxiStreamSlave_rawBus_fifo_EMPTY_N && - crc_crcAxiStream_crcReqBuf_FULL_N ; - assign crc_rawAxiStreamSlave_rawBus_fifo_CLR = 1'b0 ; - - // submodule crc_rawBusMaster_fifo - assign crc_rawBusMaster_fifo_D_IN = - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_OUT ; - assign crc_rawBusMaster_fifo_ENQ = - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_EMPTY_N && - crc_rawBusMaster_fifo_FULL_N ; - assign crc_rawBusMaster_fifo_DEQ = - crc_rawBusMaster_fifo_EMPTY_N && m_crc_stream_ready ; - assign crc_rawBusMaster_fifo_CLR = 1'b0 ; - - // remaining internal signals - assign IF_crc_crcAxiStream_crcReqBufD_OUT_BIT_2_THEN_ETC__q69 = - crc_crcAxiStream_crcReqBuf_D_OUT[2] ? 256'd1 : 256'd0 ; - assign crc1__h169284 = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[6] ? - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_2 : - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_2 ; - assign crc1__h169800 = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[6] ? - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_2 : - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_2 ; - assign crc2__h169285 = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[6] ? - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_2 : - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_2 ; - assign crc2__h169801 = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[6] ? - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_2 : - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_2 ; - assign crcRes__h159777 = firstHalfRes__h159800 ^ secondHalfRes__h159801 ; - assign crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139 = - { crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33:32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32:31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31:30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30:29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29:28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28:27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27:26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26:25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25:24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24:23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23:22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22:21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21:20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20:19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19:18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18:17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17:16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16:15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15:14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14:13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13:12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12:11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11:10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10:9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9:8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8:7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7:6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6:5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5:4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4:3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3:2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - IF_crc_crcAxiStream_crcReqBufD_OUT_BIT_2_THEN_ETC__q69[0] } & - crc_crcAxiStream_crcReqBuf_D_OUT[289:34] ; - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1146 = - interCrc__h287602 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[31:0] ; - assign ctrlSig_shiftAmt__h59003 = - crc_crcAxiStream_crcReqBuf_D_OUT[33] ? - 6'd0 : - (crc_crcAxiStream_crcReqBuf_D_OUT[32] ? - 6'd1 : - (crc_crcAxiStream_crcReqBuf_D_OUT[31] ? - 6'd2 : - (crc_crcAxiStream_crcReqBuf_D_OUT[30] ? - 6'd3 : - (crc_crcAxiStream_crcReqBuf_D_OUT[29] ? - 6'd4 : - (crc_crcAxiStream_crcReqBuf_D_OUT[28] ? - 6'd5 : - (crc_crcAxiStream_crcReqBuf_D_OUT[27] ? - 6'd6 : - (crc_crcAxiStream_crcReqBuf_D_OUT[26] ? - 6'd7 : - (crc_crcAxiStream_crcReqBuf_D_OUT[25] ? - 6'd8 : - (crc_crcAxiStream_crcReqBuf_D_OUT[24] ? - 6'd9 : - (crc_crcAxiStream_crcReqBuf_D_OUT[23] ? - 6'd10 : - (crc_crcAxiStream_crcReqBuf_D_OUT[22] ? - 6'd11 : - (crc_crcAxiStream_crcReqBuf_D_OUT[21] ? - 6'd12 : - (crc_crcAxiStream_crcReqBuf_D_OUT[20] ? - 6'd13 : - (crc_crcAxiStream_crcReqBuf_D_OUT[19] ? - 6'd14 : - (crc_crcAxiStream_crcReqBuf_D_OUT[18] ? - 6'd15 : - (crc_crcAxiStream_crcReqBuf_D_OUT[17] ? - 6'd16 : - (crc_crcAxiStream_crcReqBuf_D_OUT[16] ? - 6'd17 : - (crc_crcAxiStream_crcReqBuf_D_OUT[15] ? - 6'd18 : - (crc_crcAxiStream_crcReqBuf_D_OUT[14] ? - 6'd19 : - (crc_crcAxiStream_crcReqBuf_D_OUT[13] ? - 6'd20 : - (crc_crcAxiStream_crcReqBuf_D_OUT[12] ? - 6'd21 : - (crc_crcAxiStream_crcReqBuf_D_OUT[11] ? - 6'd22 : - (crc_crcAxiStream_crcReqBuf_D_OUT[10] ? - 6'd23 : - (crc_crcAxiStream_crcReqBuf_D_OUT[9] ? - 6'd24 : - (crc_crcAxiStream_crcReqBuf_D_OUT[8] ? - 6'd25 : - (crc_crcAxiStream_crcReqBuf_D_OUT[7] ? - 6'd26 : - (crc_crcAxiStream_crcReqBuf_D_OUT[6] ? - 6'd27 : - (crc_crcAxiStream_crcReqBuf_D_OUT[5] ? - 6'd28 : - (crc_crcAxiStream_crcReqBuf_D_OUT[4] ? - 6'd29 : - (crc_crcAxiStream_crcReqBuf_D_OUT[3] ? - 6'd30 : - (crc_crcAxiStream_crcReqBuf_D_OUT[2] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign firstHalfRes__h159800 = - firstHalfRes__h159809 ^ secondHalfRes__h159810 ; - assign firstHalfRes__h159809 = - firstHalfRes__h159818 ^ secondHalfRes__h159819 ; - assign firstHalfRes__h159818 = - firstHalfRes__h159827 ^ secondHalfRes__h159828 ; - assign firstHalfRes__h159827 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[39:8] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[71:40] ; - assign firstHalfRes__h162162 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[167:136] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[199:168] ; - assign firstHalfRes__h162946 = - firstHalfRes__h162955 ^ secondHalfRes__h162956 ; - assign firstHalfRes__h162955 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[295:264] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[327:296] ; - assign firstHalfRes__h164036 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[423:392] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[455:424] ; - assign firstHalfRes__h164820 = - firstHalfRes__h164829 ^ secondHalfRes__h164830 ; - assign firstHalfRes__h164829 = - firstHalfRes__h164838 ^ secondHalfRes__h164839 ; - assign firstHalfRes__h164838 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[551:520] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[583:552] ; - assign firstHalfRes__h166480 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[679:648] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[711:680] ; - assign firstHalfRes__h167264 = - firstHalfRes__h167273 ^ secondHalfRes__h167274 ; - assign firstHalfRes__h167273 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[807:776] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[839:808] ; - assign firstHalfRes__h168354 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[935:904] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[967:936] ; - assign firstHalfRes__h169280 = crc1__h169284 ^ crc2__h169285 ; - assign firstHalfRes__h287945 = - firstHalfRes__h287954 ^ secondHalfRes__h287955 ; - assign firstHalfRes__h287954 = - firstHalfRes__h287963 ^ secondHalfRes__h287964 ; - assign firstHalfRes__h287963 = - firstHalfRes__h287972 ^ secondHalfRes__h287973 ; - assign firstHalfRes__h287972 = - firstHalfRes__h287981 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[127:96] ; - assign firstHalfRes__h287981 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[63:32] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[95:64] ; - assign firstHalfRes__h290879 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[223:192] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[255:224] ; - assign firstHalfRes__h291663 = - firstHalfRes__h291672 ^ secondHalfRes__h291673 ; - assign firstHalfRes__h291672 = - firstHalfRes__h291681 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[415:384] ; - assign firstHalfRes__h291681 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[351:320] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[383:352] ; - assign firstHalfRes__h293175 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[511:480] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[543:512] ; - assign firstHalfRes__h293959 = - firstHalfRes__h293968 ^ secondHalfRes__h293969 ; - assign firstHalfRes__h293968 = - firstHalfRes__h293977 ^ secondHalfRes__h293978 ; - assign firstHalfRes__h293977 = - firstHalfRes__h293986 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[703:672] ; - assign firstHalfRes__h293986 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[639:608] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[671:640] ; - assign firstHalfRes__h296107 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[799:768] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[831:800] ; - assign firstHalfRes__h296891 = - firstHalfRes__h296900 ^ secondHalfRes__h296901 ; - assign firstHalfRes__h296900 = - firstHalfRes__h296909 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[991:960] ; - assign firstHalfRes__h296909 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[927:896] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[959:928] ; - assign firstHalfRes__h298403 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1087:1056] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1119:1088] ; - assign interCrc__h170060 = - (shiftAmt__h170081 <= 7'd36) ? - { CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q33, - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q34, - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q35, - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q36, - CASE_shiftAmt70081_0_0_1_crc_crcAxiStream_crcR_ETC__q37, - CASE_shiftAmt70081_0_0_1_0_2_crc_crcAxiStream__ETC__q38, - CASE_shiftAmt70081_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67, - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 } : - 288'd0 ; - assign interCrc__h287602 = firstHalfRes__h287945 ^ secondHalfRes__h287946 ; - assign nextInterCrc__h169186 = - firstHalfRes__h169280 ^ secondHalfRes__h169281 ; - assign nextInterCrc__h169187 = - nextInterCrc__h169186 ^ - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[39:8] ; - assign preProcessRes_data__h13182 = - { crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[0], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[1], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[2], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[3], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[4], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[5], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[6], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[7], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[8], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[9], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[10], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[11], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[12], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[13], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[14], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[15], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[16], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[17], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[18], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[19], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[20], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[21], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[22], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[23], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[24], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[25], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[26], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[27], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[28], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[29], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[30], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[31], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[32], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[33], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[34], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[35], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[36], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[37], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[38], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[39], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[40], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[41], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[42], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[43], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[44], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[45], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[46], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[47], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[48], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[49], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[50], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[51], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[52], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[53], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[54], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[55], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[56], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[57], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[58], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[59], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[60], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[61], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[62], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[63], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[64], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[65], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[66], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[67], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[68], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[69], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[70], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[71], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[72], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[73], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[74], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[75], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[76], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[77], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[78], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[79], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[80], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[81], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[82], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[83], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[84], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[85], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[86], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[87], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[88], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[89], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[90], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[91], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[92], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[93], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[94], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[95], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[96], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[97], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[98], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[99], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[100], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[101], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[102], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[103], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[104], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[105], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[106], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[107], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[108], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[109], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[110], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[111], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[112], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[113], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[114], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[115], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[116], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[117], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[118], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[119], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[120], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[121], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[122], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[123], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[124], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[125], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[126], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[127], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[128], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[129], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[130], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[131], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[132], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[133], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[134], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[135], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[136], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[137], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[138], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[139], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[140], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[141], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[142], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[143], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[144], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[145], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[146], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[147], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[148], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[149], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[150], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[151], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[152], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[153], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[154], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[155], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[156], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[157], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[158], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[159], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[160], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[161], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[162], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[163], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[164], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[165], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[166], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[167], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[168], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[169], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[170], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[171], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[172], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[173], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[174], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[175], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[176], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[177], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[178], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[179], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[180], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[181], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[182], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[183], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[184], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[185], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[186], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[187], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[188], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[189], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[190], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[191], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[192], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[193], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[194], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[195], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[196], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[197], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[198], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[199], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[200], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[201], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[202], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[203], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[204], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[205], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[206], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[207], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[208], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[209], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[210], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[211], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[212], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[213], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[214], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[215], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[216], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[217], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[218], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[219], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[220], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[221], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[222], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[223], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[224], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[225], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[226], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[227], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[228], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[229], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[230], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[231], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[232], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[233], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[234], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[235], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[236], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[237], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[238], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[239], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[240], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[241], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[242], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[243], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[244], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[245], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[246], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[247], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[248], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[249], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[250], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[251], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[252], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[253], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[254], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[255] } ; - assign secondHalfRes__h159801 = - firstHalfRes__h164820 ^ secondHalfRes__h164821 ; - assign secondHalfRes__h159810 = - firstHalfRes__h162946 ^ secondHalfRes__h162947 ; - assign secondHalfRes__h159819 = - firstHalfRes__h162162 ^ secondHalfRes__h162163 ; - assign secondHalfRes__h159828 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[103:72] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[135:104] ; - assign secondHalfRes__h162163 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[231:200] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[263:232] ; - assign secondHalfRes__h162947 = - firstHalfRes__h164036 ^ secondHalfRes__h164037 ; - assign secondHalfRes__h162956 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[359:328] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[391:360] ; - assign secondHalfRes__h164037 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[487:456] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[519:488] ; - assign secondHalfRes__h164821 = - firstHalfRes__h167264 ^ secondHalfRes__h167265 ; - assign secondHalfRes__h164830 = - firstHalfRes__h166480 ^ secondHalfRes__h166481 ; - assign secondHalfRes__h164839 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[615:584] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[647:616] ; - assign secondHalfRes__h166481 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[743:712] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[775:744] ; - assign secondHalfRes__h167265 = - firstHalfRes__h168354 ^ secondHalfRes__h168355 ; - assign secondHalfRes__h167274 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[871:840] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[903:872] ; - assign secondHalfRes__h168355 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[999:968] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[1031:1000] ; - assign secondHalfRes__h169281 = crc1__h169800 ^ crc2__h169801 ; - assign secondHalfRes__h287946 = - firstHalfRes__h293959 ^ secondHalfRes__h293960 ; - assign secondHalfRes__h287955 = - firstHalfRes__h291663 ^ secondHalfRes__h291664 ; - assign secondHalfRes__h287964 = - firstHalfRes__h290879 ^ secondHalfRes__h290880 ; - assign secondHalfRes__h287973 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[159:128] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[191:160] ; - assign secondHalfRes__h290880 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[287:256] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[319:288] ; - assign secondHalfRes__h291664 = - firstHalfRes__h293175 ^ secondHalfRes__h293176 ; - assign secondHalfRes__h291673 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[447:416] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[479:448] ; - assign secondHalfRes__h293176 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[575:544] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[607:576] ; - assign secondHalfRes__h293960 = - firstHalfRes__h296891 ^ secondHalfRes__h296892 ; - assign secondHalfRes__h293969 = - firstHalfRes__h296107 ^ secondHalfRes__h296108 ; - assign secondHalfRes__h293978 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[735:704] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[767:736] ; - assign secondHalfRes__h296108 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[863:832] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[895:864] ; - assign secondHalfRes__h296892 = - firstHalfRes__h298403 ^ secondHalfRes__h298404 ; - assign secondHalfRes__h296901 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1023:992] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1055:1024] ; - assign secondHalfRes__h298404 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1151:1120] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1183:1152] ; - assign shiftAmt___1__h171513 = shiftAmt__h170059 + 7'd4 ; - assign shiftAmt__h170059 = - { 1'd0, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[5:0] } ; - assign shiftAmt__h170081 = - (crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[6] && - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[7]) ? - shiftAmt___1__h171513 : - shiftAmt__h170059 ; - assign x_data__h64227 = - (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0] <= - 6'd32) ? - { CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 } : - 256'd0 ; - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd1, - 6'd2, - 6'd3, - 6'd4, - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd2, - 6'd3, - 6'd4, - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd3, - 6'd4, - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd4, - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd23, 6'd24, 6'd25, 6'd26, 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd24, 6'd25, 6'd26, 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd25, 6'd26, 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd26, 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[39:32]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd28: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[31:24]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[39:32]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd28: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd29: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[23:16]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[31:24]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[39:32]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd28: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd29: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd30: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[15:8]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[23:16]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[31:24]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[39:32]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd28: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd29: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd30: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd31: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd32: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q33 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q33 = 8'd0; - default: CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q33 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q34 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd1: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q34 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q34 = 8'd0; - default: CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q34 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q35 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd1: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q35 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd2: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q35 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q35 = 8'd0; - default: CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q35 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q36 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd1: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q36 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd2: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q36 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd3: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q36 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q36 = 8'd0; - default: CASE_shiftAmt70081_0_crc_crcAxiStream_crcRespF_ETC__q36 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = 8'd0; - 7'd1: - CASE_shiftAmt70081_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd2: - CASE_shiftAmt70081_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd3: - CASE_shiftAmt70081_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd4: - CASE_shiftAmt70081_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = 8'd0; - 7'd2: - CASE_shiftAmt70081_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd3: - CASE_shiftAmt70081_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd4: - CASE_shiftAmt70081_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd5: - CASE_shiftAmt70081_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = 8'd0; - 7'd3: - CASE_shiftAmt70081_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd4: - CASE_shiftAmt70081_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd5: - CASE_shiftAmt70081_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd6: - CASE_shiftAmt70081_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = 8'd0; - 7'd4: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd5: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd6: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd7: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = 8'd0; - 7'd5: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd6: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd7: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd8: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = 8'd0; - 7'd6: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd7: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd8: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd9: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = 8'd0; - 7'd7: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd8: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd9: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd10: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = 8'd0; - 7'd8: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd9: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd10: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd11: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = 8'd0; - 7'd9: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd10: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd11: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd12: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = 8'd0; - 7'd10: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd11: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd12: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd13: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = 8'd0; - 7'd11: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd12: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd13: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd14: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = 8'd0; - 7'd12: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd13: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd14: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd15: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = 8'd0; - 7'd13: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd14: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd15: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd16: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = 8'd0; - 7'd14: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd15: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd16: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd17: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = 8'd0; - 7'd15: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd16: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd17: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd18: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = 8'd0; - 7'd16: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd17: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd18: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd19: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = 8'd0; - 7'd17: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd18: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd19: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd20: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = 8'd0; - 7'd18: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd19: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd20: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd21: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = 8'd0; - 7'd19: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd20: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd21: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd22: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = 8'd0; - 7'd20: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd21: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd22: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd23: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = 8'd0; - 7'd21: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd22: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd23: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd24: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = 8'd0; - 7'd22: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd23: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd24: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd25: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = 8'd0; - 7'd23: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd24: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd25: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd26: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = 8'd0; - 7'd24: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd25: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd26: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd27: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = 8'd0; - 7'd25: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd26: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd27: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd28: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = 8'd0; - 7'd26: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd27: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd28: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd29: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = 8'd0; - 7'd27: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd28: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd29: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd30: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = 8'd0; - 7'd28: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd29: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd30: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd31: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = 8'd0; - 7'd29: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd30: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd31: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd32: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = 8'd0; - 7'd30: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd31: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd32: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd33: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd35, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = 8'd0; - 7'd31: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd32: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd33: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd34: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h170081 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h170081) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd36: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = 8'd0; - 7'd32: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd33: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd34: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd35: - CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt70081_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - 8'b10101010 /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - crc_crcAxiStream_crcRespFifoOut_interCrcRes <= `BSV_ASSIGNMENT_DELAY - 32'hFFFFFFFF; - crc_crcAxiStream_crcRespFifoOut_isFirstFlag <= `BSV_ASSIGNMENT_DELAY - 1'd1; - end - else - begin - if (crc_crcAxiStream_crcRespFifoOut_interCrcRes_EN) - crc_crcAxiStream_crcRespFifoOut_interCrcRes <= `BSV_ASSIGNMENT_DELAY - crc_crcAxiStream_crcRespFifoOut_interCrcRes_D_IN; - if (crc_crcAxiStream_crcRespFifoOut_isFirstFlag_EN) - crc_crcAxiStream_crcRespFifoOut_isFirstFlag <= `BSV_ASSIGNMENT_DELAY - crc_crcAxiStream_crcRespFifoOut_isFirstFlag_D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - crc_crcAxiStream_crcRespFifoOut_interCrcRes = 32'hAAAAAAAA; - crc_crcAxiStream_crcRespFifoOut_isFirstFlag = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCrcRawAxiStreamCustomRecv - - -`ifdef BSV_WARN_REGFILE_ADDR_RANGE -`else -`define BSV_WARN_REGFILE_ADDR_RANGE 0 -`endif - -`ifdef BSV_ASSIGNMENT_DELAY -`else -`define BSV_ASSIGNMENT_DELAY -`endif - - -// Multi-ported Lookup Table(ROM) -- initializable from a file. -module LookupTableLoadRecv( - CLK, - ADDR_1, D_OUT_1, - ADDR_2, D_OUT_2, - ADDR_3, D_OUT_3, - ADDR_4, D_OUT_4, - ADDR_5, D_OUT_5 -); - parameter file = ""; - parameter addr_width = 1; - parameter data_width = 1; - parameter lo = 0; - parameter hi = 1; - parameter binary = 0; - - input CLK; - - input [addr_width - 1 : 0] ADDR_1; - output [data_width - 1 : 0] D_OUT_1; - - input [addr_width - 1 : 0] ADDR_2; - output [data_width - 1 : 0] D_OUT_2; - - input [addr_width - 1 : 0] ADDR_3; - output [data_width - 1 : 0] D_OUT_3; - - input [addr_width - 1 : 0] ADDR_4; - output [data_width - 1 : 0] D_OUT_4; - - input [addr_width - 1 : 0] ADDR_5; - output [data_width - 1 : 0] D_OUT_5; - - reg [data_width - 1 : 0] arr[lo:hi]; - - - initial - begin : init_rom_block - if (binary) - $readmemb(file, arr, lo, hi); - else - $readmemh(file, arr, lo, hi); - end // initial begin - - assign D_OUT_1 = arr[ADDR_1]; - assign D_OUT_2 = arr[ADDR_2]; - assign D_OUT_3 = arr[ADDR_3]; - assign D_OUT_4 = arr[ADDR_4]; - assign D_OUT_5 = arr[ADDR_5]; - -endmodule diff --git a/ethernet/RoCEv2/blue-crc/mkCrcRawAxiStreamCustomSend.v b/ethernet/RoCEv2/blue-crc/mkCrcRawAxiStreamCustomSend.v deleted file mode 100644 index adff363430..0000000000 --- a/ethernet/RoCEv2/blue-crc/mkCrcRawAxiStreamCustomSend.v +++ /dev/null @@ -1,7304 +0,0 @@ -/* - * ------------------------------------------------------------------- - * This Verilog file has been automatically generated from a core originally written - * in Bluespec SystemVerilog (BSV). The original source code can be found at: - * - * Repository: https://github.com/datenlord/blue-crc - * Author: DatenLord (https://datenlord.github.io/) - * ------------------------------------------------------------------- - */ -// -// Generated by Bluespec Compiler, version 2023.01 (build 52adafa) -// -// On Wed Sep 11 15:19:11 CEST 2024 -// -// -// Ports: -// Name I/O size props -// s_axis_tready O 1 reg -// m_crc_stream_data O 32 reg -// m_crc_stream_valid O 1 reg -// CLK I 1 clock -// RST_N I 1 reset -// s_axis_tvalid I 1 -// s_axis_tdata I 256 reg -// s_axis_tkeep I 32 reg -// s_axis_tlast I 1 reg -// s_axis_tuser I 1 reg -// m_crc_stream_ready I 1 -// -// No combinational paths from inputs to outputs -// -// - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -module mkCrcRawAxiStreamCustomSend(CLK, - RST_N, - - s_axis_tvalid, - s_axis_tdata, - s_axis_tkeep, - s_axis_tlast, - s_axis_tuser, - - s_axis_tready, - - m_crc_stream_data, - - m_crc_stream_valid, - - m_crc_stream_ready); - input CLK; - input RST_N; - - // action method rawCrcReq_tValid - input s_axis_tvalid; - input [255 : 0] s_axis_tdata; - input [31 : 0] s_axis_tkeep; - input s_axis_tlast; - input s_axis_tuser; - - // value method rawCrcReq_tReady - output s_axis_tready; - - // value method rawCrcResp_data - output [31 : 0] m_crc_stream_data; - - // value method rawCrcResp_valid - output m_crc_stream_valid; - - // action method rawCrcResp_ready - input m_crc_stream_ready; - - // signals for module outputs - wire [31 : 0] m_crc_stream_data; - wire m_crc_stream_valid, s_axis_tready; - - // inlined wires - wire [289 : 0] crc_rawAxiStreamSlave_rawBus_rawBus_dataW_wget; - - // register crc_crcAxiStream_crcRespFifoOut_interCrcRes - reg [31 : 0] crc_crcAxiStream_crcRespFifoOut_interCrcRes; - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_interCrcRes_D_IN; - wire crc_crcAxiStream_crcRespFifoOut_interCrcRes_EN; - - // register crc_crcAxiStream_crcRespFifoOut_isFirstFlag - reg crc_crcAxiStream_crcRespFifoOut_isFirstFlag; - wire crc_crcAxiStream_crcRespFifoOut_isFirstFlag_D_IN, - crc_crcAxiStream_crcRespFifoOut_isFirstFlag_EN; - - // ports of submodule crc_crcAxiStream_crcReqBuf - wire [289 : 0] crc_crcAxiStream_crcReqBuf_D_IN, - crc_crcAxiStream_crcReqBuf_D_OUT; - wire crc_crcAxiStream_crcReqBuf_CLR, - crc_crcAxiStream_crcReqBuf_DEQ, - crc_crcAxiStream_crcReqBuf_EMPTY_N, - crc_crcAxiStream_crcReqBuf_ENQ, - crc_crcAxiStream_crcReqBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf - wire [71 : 0] crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_3; - wire [7 : 0] crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_2, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_4, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_5; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf - wire [31 : 0] crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_preProcessResBuf - wire [263 : 0] crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf - wire [1031 : 0] crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf - wire [1183 : 0] crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf - wire [39 : 0] crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf - wire [263 : 0] crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_FULL_N; - - // ports of submodule crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf - wire [319 : 0] crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_IN, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT; - wire crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_CLR, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_DEQ, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_EMPTY_N, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_ENQ, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_FULL_N; - - // ports of submodule crc_rawAxiStreamSlave_rawBus_fifo - wire [289 : 0] crc_rawAxiStreamSlave_rawBus_fifo_D_IN, - crc_rawAxiStreamSlave_rawBus_fifo_D_OUT; - wire crc_rawAxiStreamSlave_rawBus_fifo_CLR, - crc_rawAxiStreamSlave_rawBus_fifo_DEQ, - crc_rawAxiStreamSlave_rawBus_fifo_EMPTY_N, - crc_rawAxiStreamSlave_rawBus_fifo_ENQ, - crc_rawAxiStreamSlave_rawBus_fifo_FULL_N; - - // ports of submodule crc_rawBusMaster_fifo - wire [31 : 0] crc_rawBusMaster_fifo_D_IN, crc_rawBusMaster_fifo_D_OUT; - wire crc_rawBusMaster_fifo_CLR, - crc_rawBusMaster_fifo_DEQ, - crc_rawBusMaster_fifo_EMPTY_N, - crc_rawBusMaster_fifo_ENQ, - crc_rawBusMaster_fifo_FULL_N; - - // remaining internal signals - reg [7 : 0] CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40, - CASE_shiftAmt69932_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39, - CASE_shiftAmt69932_0_0_1_0_2_crc_crcAxiStream__ETC__q38, - CASE_shiftAmt69932_0_0_1_crc_crcAxiStream_crcR_ETC__q37, - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q33, - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q34, - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q35, - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q36; - wire [287 : 0] interCrc__h169911; - wire [255 : 0] IF_crc_crcAxiStream_crcReqBufD_OUT_BIT_2_THEN_ETC__q69, - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139, - preProcessRes_data__h13182, - x_data__h64227; - wire [31 : 0] crcRes__h159813, - crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132, - firstHalfRes__h159836, - firstHalfRes__h159845, - firstHalfRes__h159854, - firstHalfRes__h159863, - firstHalfRes__h162198, - firstHalfRes__h162982, - firstHalfRes__h162991, - firstHalfRes__h164072, - firstHalfRes__h164856, - firstHalfRes__h164865, - firstHalfRes__h164874, - firstHalfRes__h166516, - firstHalfRes__h167300, - firstHalfRes__h167309, - firstHalfRes__h168390, - firstHalfRes__h169316, - firstHalfRes__h287806, - firstHalfRes__h287815, - firstHalfRes__h287824, - firstHalfRes__h287833, - firstHalfRes__h287842, - firstHalfRes__h290740, - firstHalfRes__h291524, - firstHalfRes__h291533, - firstHalfRes__h291542, - firstHalfRes__h293036, - firstHalfRes__h293820, - firstHalfRes__h293829, - firstHalfRes__h293838, - firstHalfRes__h293847, - firstHalfRes__h295968, - firstHalfRes__h296752, - firstHalfRes__h296761, - firstHalfRes__h296770, - firstHalfRes__h298264, - interCrc__h287463, - nextInterCrc__h169222, - nextInterCrc__h169223, - secondHalfRes__h159837, - secondHalfRes__h159846, - secondHalfRes__h159855, - secondHalfRes__h159864, - secondHalfRes__h162199, - secondHalfRes__h162983, - secondHalfRes__h162992, - secondHalfRes__h164073, - secondHalfRes__h164857, - secondHalfRes__h164866, - secondHalfRes__h164875, - secondHalfRes__h166517, - secondHalfRes__h167301, - secondHalfRes__h167310, - secondHalfRes__h168391, - secondHalfRes__h169317, - secondHalfRes__h287807, - secondHalfRes__h287816, - secondHalfRes__h287825, - secondHalfRes__h287834, - secondHalfRes__h290741, - secondHalfRes__h291525, - secondHalfRes__h291534, - secondHalfRes__h293037, - secondHalfRes__h293821, - secondHalfRes__h293830, - secondHalfRes__h293839, - secondHalfRes__h295969, - secondHalfRes__h296753, - secondHalfRes__h296762, - secondHalfRes__h298265; - wire [6 : 0] shiftAmt__h169932; - wire [5 : 0] ctrlSig_shiftAmt__h59003; - - // value method rawCrcReq_tReady - assign s_axis_tready = crc_rawAxiStreamSlave_rawBus_fifo_FULL_N ; - - // value method rawCrcResp_data - assign m_crc_stream_data = crc_rawBusMaster_fifo_D_OUT ; - - // value method rawCrcResp_valid - assign m_crc_stream_valid = crc_rawBusMaster_fifo_EMPTY_N ; - - // submodule crc_crcAxiStream_crcReqBuf - FIFO2 #(.width(32'd290), - .guarded(1'd1)) crc_crcAxiStream_crcReqBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcReqBuf_D_IN), - .ENQ(crc_crcAxiStream_crcReqBuf_ENQ), - .DEQ(crc_crcAxiStream_crcReqBuf_DEQ), - .CLR(crc_crcAxiStream_crcReqBuf_CLR), - .D_OUT(crc_crcAxiStream_crcReqBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcReqBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcReqBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf - FIFO2 #(.width(32'd72), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_0.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_10.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_11.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_12.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_13.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_14.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_15.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_16.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_17.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_18.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_19.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_1.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_20.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_21.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_22.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_23.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_24.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_25.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_26.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_27.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_28.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_29.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_2.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_30.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_31.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_32.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_33.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_34.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_35.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_2), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_3.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_4.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_5.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_6.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_7.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_8.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable - LookupTableLoadSend #(.file("crc_tab_9.mem"), - .addr_width(32'd8), - .data_width(32'd32), - .lo(32'd0), - .hi(32'd255), - .binary(32'd0)) crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable(.CLK(CLK), - .ADDR_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_1), - .ADDR_2(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_2), - .ADDR_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_3), - .ADDR_4(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_4), - .ADDR_5(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_5), - .D_OUT_1(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_1), - .D_OUT_2(), - .D_OUT_3(crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_3), - .D_OUT_4(), - .D_OUT_5()); - - // submodule crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf - FIFO2 #(.width(32'd32), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_preProcessResBuf - FIFO2 #(.width(32'd264), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_preProcessResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf - FIFO2 #(.width(32'd1032), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf - FIFO2 #(.width(32'd1184), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf - FIFO2 #(.width(32'd40), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf - FIFO2 #(.width(32'd264), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_EMPTY_N)); - - // submodule crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf - FIFO2 #(.width(32'd320), - .guarded(1'd1)) crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_IN), - .ENQ(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_ENQ), - .DEQ(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_DEQ), - .CLR(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_CLR), - .D_OUT(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT), - .FULL_N(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_FULL_N), - .EMPTY_N(crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_EMPTY_N)); - - // submodule crc_rawAxiStreamSlave_rawBus_fifo - FIFO2 #(.width(32'd290), - .guarded(1'd1)) crc_rawAxiStreamSlave_rawBus_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_rawAxiStreamSlave_rawBus_fifo_D_IN), - .ENQ(crc_rawAxiStreamSlave_rawBus_fifo_ENQ), - .DEQ(crc_rawAxiStreamSlave_rawBus_fifo_DEQ), - .CLR(crc_rawAxiStreamSlave_rawBus_fifo_CLR), - .D_OUT(crc_rawAxiStreamSlave_rawBus_fifo_D_OUT), - .FULL_N(crc_rawAxiStreamSlave_rawBus_fifo_FULL_N), - .EMPTY_N(crc_rawAxiStreamSlave_rawBus_fifo_EMPTY_N)); - - // submodule crc_rawBusMaster_fifo - FIFO2 #(.width(32'd32), .guarded(1'd1)) crc_rawBusMaster_fifo(.RST(RST_N), - .CLK(CLK), - .D_IN(crc_rawBusMaster_fifo_D_IN), - .ENQ(crc_rawBusMaster_fifo_ENQ), - .DEQ(crc_rawBusMaster_fifo_DEQ), - .CLR(crc_rawBusMaster_fifo_CLR), - .D_OUT(crc_rawBusMaster_fifo_D_OUT), - .FULL_N(crc_rawBusMaster_fifo_FULL_N), - .EMPTY_N(crc_rawBusMaster_fifo_EMPTY_N)); - - // inlined wires - assign crc_rawAxiStreamSlave_rawBus_rawBus_dataW_wget = - { s_axis_tdata, s_axis_tkeep, s_axis_tlast, s_axis_tuser } ; - - // register crc_crcAxiStream_crcRespFifoOut_interCrcRes - assign crc_crcAxiStream_crcRespFifoOut_interCrcRes_D_IN = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] ? - 32'hFFFFFFFF : - nextInterCrc__h169223 ; - assign crc_crcAxiStream_crcRespFifoOut_interCrcRes_EN = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N && - (!crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] || - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N) ; - - // register crc_crcAxiStream_crcRespFifoOut_isFirstFlag - assign crc_crcAxiStream_crcRespFifoOut_isFirstFlag_D_IN = - crc_crcAxiStream_crcReqBuf_D_OUT[1] ; - assign crc_crcAxiStream_crcRespFifoOut_isFirstFlag_EN = - crc_crcAxiStream_crcReqBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N ; - - // submodule crc_crcAxiStream_crcReqBuf - assign crc_crcAxiStream_crcReqBuf_D_IN = - crc_rawAxiStreamSlave_rawBus_fifo_D_OUT ; - assign crc_crcAxiStream_crcReqBuf_ENQ = - crc_rawAxiStreamSlave_rawBus_fifo_EMPTY_N && - crc_crcAxiStream_crcReqBuf_FULL_N ; - assign crc_crcAxiStream_crcReqBuf_DEQ = - crc_crcAxiStream_crcReqBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N ; - assign crc_crcAxiStream_crcReqBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf - assign crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_IN = - { crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[39:8], - crc_crcAxiStream_crcRespFifoOut_interCrcRes, - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7:0] } ; - assign crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N && - (!crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] || - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N) && - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] ; - assign crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_1 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[7:0] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[63:56] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[87:80] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[71:64] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[95:88] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[79:72] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[103:96] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[87:80] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[111:104] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[95:88] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[119:112] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[103:96] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[127:120] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[111:104] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[135:128] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[119:112] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[143:136] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[127:120] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[151:144] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[135:128] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[159:152] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_1 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[15:8] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[143:136] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[167:160] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[151:144] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[175:168] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[159:152] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[183:176] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[167:160] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[191:184] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[175:168] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[199:192] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[183:176] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[207:200] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[191:184] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[215:208] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[199:192] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[223:216] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[207:200] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[231:224] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[215:208] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[239:232] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_1 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[23:16] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[223:216] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[247:240] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[231:224] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[255:248] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[239:232] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[7:0] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[263:256] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[247:240] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[15:8] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[271:264] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[255:248] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[23:16] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[279:272] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[263:256] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_2 = - crc_crcAxiStream_crcRespFifoOut_interCrcRes[31:24] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[287:280] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_1 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[31:24] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[15:8] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[39:32] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[23:16] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[47:40] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[31:24] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[55:48] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[39:32] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[63:56] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[47:40] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[71:64] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_1 = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[55:48] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_2 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_3 = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[79:72] ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_4 = - 8'h0 ; - assign crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_ADDR_5 = - 8'h0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf - assign crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_IN = - { ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[0], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[1], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[2], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[3], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[4], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[5], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[6], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[7], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[8], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[9], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[10], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[11], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[12], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[13], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[14], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[15], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[16], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[17], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[18], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[19], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[20], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[21], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[22], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[23], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[24], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[25], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[26], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[27], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[28], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[29], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[30], - ~crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132[31] } ; - assign crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_EMPTY_N && - crc_rawBusMaster_fifo_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_preProcessResBuf - assign crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_IN = - { preProcessRes_data__h13182, - crc_crcAxiStream_crcReqBuf_D_OUT[1], - crc_crcAxiStream_crcRespFifoOut_isFirstFlag, - ctrlSig_shiftAmt__h59003 } ; - assign crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_ENQ = - crc_crcAxiStream_crcReqBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf - assign crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_IN = - { crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_1, - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_OUT[7:0] } ; - assign crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_IN = - { crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_31_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_30_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_29_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_28_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_27_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_26_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_25_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_24_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_23_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_22_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_21_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_20_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_19_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_18_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_17_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_16_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_15_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_14_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_13_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_12_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_11_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_10_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_9_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_8_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_7_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_6_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_5_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_4_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_3_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_2_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_1_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_crcTabVec_0_lookupTable_lookupTable_D_OUT_3, - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_OUT[319:288] } ; - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf - assign crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_IN = - { crcRes__h159813, - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[7:0] } ; - assign crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_EMPTY_N && - (!crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[7] || - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_FULL_N) ; - assign crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf - assign crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_D_IN = - { x_data__h64227, - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[7:0] } ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInputResBuf_CLR = 1'b0 ; - - // submodule crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf - assign crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_D_IN = - { crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[71:40], - interCrc__h169911 } ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_ENQ = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_DEQ = - crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_EMPTY_N && - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_FULL_N ; - assign crc_crcAxiStream_crcRespFifoOut_shiftInterCrcResBuf_CLR = 1'b0 ; - - // submodule crc_rawAxiStreamSlave_rawBus_fifo - assign crc_rawAxiStreamSlave_rawBus_fifo_D_IN = - crc_rawAxiStreamSlave_rawBus_rawBus_dataW_wget ; - assign crc_rawAxiStreamSlave_rawBus_fifo_ENQ = - crc_rawAxiStreamSlave_rawBus_fifo_FULL_N && s_axis_tvalid ; - assign crc_rawAxiStreamSlave_rawBus_fifo_DEQ = - crc_rawAxiStreamSlave_rawBus_fifo_EMPTY_N && - crc_crcAxiStream_crcReqBuf_FULL_N ; - assign crc_rawAxiStreamSlave_rawBus_fifo_CLR = 1'b0 ; - - // submodule crc_rawBusMaster_fifo - assign crc_rawBusMaster_fifo_D_IN = - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_D_OUT ; - assign crc_rawBusMaster_fifo_ENQ = - crc_crcAxiStream_crcRespFifoOut_finalCrcResBuf_EMPTY_N && - crc_rawBusMaster_fifo_FULL_N ; - assign crc_rawBusMaster_fifo_DEQ = - crc_rawBusMaster_fifo_EMPTY_N && m_crc_stream_ready ; - assign crc_rawBusMaster_fifo_CLR = 1'b0 ; - - // remaining internal signals - assign IF_crc_crcAxiStream_crcReqBufD_OUT_BIT_2_THEN_ETC__q69 = - crc_crcAxiStream_crcReqBuf_D_OUT[2] ? 256'd1 : 256'd0 ; - assign crcRes__h159813 = firstHalfRes__h159836 ^ secondHalfRes__h159837 ; - assign crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139 = - { crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33], - crc_crcAxiStream_crcReqBuf_D_OUT[33:32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32], - crc_crcAxiStream_crcReqBuf_D_OUT[32:31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31], - crc_crcAxiStream_crcReqBuf_D_OUT[31:30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30], - crc_crcAxiStream_crcReqBuf_D_OUT[30:29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29], - crc_crcAxiStream_crcReqBuf_D_OUT[29:28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28], - crc_crcAxiStream_crcReqBuf_D_OUT[28:27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27], - crc_crcAxiStream_crcReqBuf_D_OUT[27:26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26], - crc_crcAxiStream_crcReqBuf_D_OUT[26:25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25], - crc_crcAxiStream_crcReqBuf_D_OUT[25:24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24], - crc_crcAxiStream_crcReqBuf_D_OUT[24:23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23], - crc_crcAxiStream_crcReqBuf_D_OUT[23:22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22], - crc_crcAxiStream_crcReqBuf_D_OUT[22:21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21], - crc_crcAxiStream_crcReqBuf_D_OUT[21:20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20], - crc_crcAxiStream_crcReqBuf_D_OUT[20:19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19], - crc_crcAxiStream_crcReqBuf_D_OUT[19:18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18], - crc_crcAxiStream_crcReqBuf_D_OUT[18:17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17], - crc_crcAxiStream_crcReqBuf_D_OUT[17:16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16], - crc_crcAxiStream_crcReqBuf_D_OUT[16:15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15], - crc_crcAxiStream_crcReqBuf_D_OUT[15:14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14], - crc_crcAxiStream_crcReqBuf_D_OUT[14:13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13], - crc_crcAxiStream_crcReqBuf_D_OUT[13:12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12], - crc_crcAxiStream_crcReqBuf_D_OUT[12:11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11], - crc_crcAxiStream_crcReqBuf_D_OUT[11:10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10], - crc_crcAxiStream_crcReqBuf_D_OUT[10:9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9], - crc_crcAxiStream_crcReqBuf_D_OUT[9:8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8], - crc_crcAxiStream_crcReqBuf_D_OUT[8:7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7], - crc_crcAxiStream_crcReqBuf_D_OUT[7:6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6], - crc_crcAxiStream_crcReqBuf_D_OUT[6:5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5], - crc_crcAxiStream_crcReqBuf_D_OUT[5:4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4], - crc_crcAxiStream_crcReqBuf_D_OUT[4:3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3], - crc_crcAxiStream_crcReqBuf_D_OUT[3:2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - crc_crcAxiStream_crcReqBuf_D_OUT[2], - IF_crc_crcAxiStream_crcReqBufD_OUT_BIT_2_THEN_ETC__q69[0] } & - crc_crcAxiStream_crcReqBuf_D_OUT[289:34] ; - assign crc_crcAxiStream_crcRespFifoOut_readInterCrcTa_ETC___d1132 = - interCrc__h287463 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[31:0] ; - assign ctrlSig_shiftAmt__h59003 = - crc_crcAxiStream_crcReqBuf_D_OUT[33] ? - 6'd0 : - (crc_crcAxiStream_crcReqBuf_D_OUT[32] ? - 6'd1 : - (crc_crcAxiStream_crcReqBuf_D_OUT[31] ? - 6'd2 : - (crc_crcAxiStream_crcReqBuf_D_OUT[30] ? - 6'd3 : - (crc_crcAxiStream_crcReqBuf_D_OUT[29] ? - 6'd4 : - (crc_crcAxiStream_crcReqBuf_D_OUT[28] ? - 6'd5 : - (crc_crcAxiStream_crcReqBuf_D_OUT[27] ? - 6'd6 : - (crc_crcAxiStream_crcReqBuf_D_OUT[26] ? - 6'd7 : - (crc_crcAxiStream_crcReqBuf_D_OUT[25] ? - 6'd8 : - (crc_crcAxiStream_crcReqBuf_D_OUT[24] ? - 6'd9 : - (crc_crcAxiStream_crcReqBuf_D_OUT[23] ? - 6'd10 : - (crc_crcAxiStream_crcReqBuf_D_OUT[22] ? - 6'd11 : - (crc_crcAxiStream_crcReqBuf_D_OUT[21] ? - 6'd12 : - (crc_crcAxiStream_crcReqBuf_D_OUT[20] ? - 6'd13 : - (crc_crcAxiStream_crcReqBuf_D_OUT[19] ? - 6'd14 : - (crc_crcAxiStream_crcReqBuf_D_OUT[18] ? - 6'd15 : - (crc_crcAxiStream_crcReqBuf_D_OUT[17] ? - 6'd16 : - (crc_crcAxiStream_crcReqBuf_D_OUT[16] ? - 6'd17 : - (crc_crcAxiStream_crcReqBuf_D_OUT[15] ? - 6'd18 : - (crc_crcAxiStream_crcReqBuf_D_OUT[14] ? - 6'd19 : - (crc_crcAxiStream_crcReqBuf_D_OUT[13] ? - 6'd20 : - (crc_crcAxiStream_crcReqBuf_D_OUT[12] ? - 6'd21 : - (crc_crcAxiStream_crcReqBuf_D_OUT[11] ? - 6'd22 : - (crc_crcAxiStream_crcReqBuf_D_OUT[10] ? - 6'd23 : - (crc_crcAxiStream_crcReqBuf_D_OUT[9] ? - 6'd24 : - (crc_crcAxiStream_crcReqBuf_D_OUT[8] ? - 6'd25 : - (crc_crcAxiStream_crcReqBuf_D_OUT[7] ? - 6'd26 : - (crc_crcAxiStream_crcReqBuf_D_OUT[6] ? - 6'd27 : - (crc_crcAxiStream_crcReqBuf_D_OUT[5] ? - 6'd28 : - (crc_crcAxiStream_crcReqBuf_D_OUT[4] ? - 6'd29 : - (crc_crcAxiStream_crcReqBuf_D_OUT[3] ? - 6'd30 : - (crc_crcAxiStream_crcReqBuf_D_OUT[2] ? - 6'd31 : - 6'd32))))))))))))))))))))))))))))))) ; - assign firstHalfRes__h159836 = - firstHalfRes__h159845 ^ secondHalfRes__h159846 ; - assign firstHalfRes__h159845 = - firstHalfRes__h159854 ^ secondHalfRes__h159855 ; - assign firstHalfRes__h159854 = - firstHalfRes__h159863 ^ secondHalfRes__h159864 ; - assign firstHalfRes__h159863 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[39:8] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[71:40] ; - assign firstHalfRes__h162198 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[167:136] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[199:168] ; - assign firstHalfRes__h162982 = - firstHalfRes__h162991 ^ secondHalfRes__h162992 ; - assign firstHalfRes__h162991 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[295:264] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[327:296] ; - assign firstHalfRes__h164072 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[423:392] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[455:424] ; - assign firstHalfRes__h164856 = - firstHalfRes__h164865 ^ secondHalfRes__h164866 ; - assign firstHalfRes__h164865 = - firstHalfRes__h164874 ^ secondHalfRes__h164875 ; - assign firstHalfRes__h164874 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[551:520] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[583:552] ; - assign firstHalfRes__h166516 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[679:648] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[711:680] ; - assign firstHalfRes__h167300 = - firstHalfRes__h167309 ^ secondHalfRes__h167310 ; - assign firstHalfRes__h167309 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[807:776] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[839:808] ; - assign firstHalfRes__h168390 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[935:904] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[967:936] ; - assign firstHalfRes__h169316 = - crc_crcAxiStream_crcRespFifoOut_crcTabVec_32_lookupTable_lookupTable_D_OUT_2 ^ - crc_crcAxiStream_crcRespFifoOut_crcTabVec_33_lookupTable_lookupTable_D_OUT_2 ; - assign firstHalfRes__h287806 = - firstHalfRes__h287815 ^ secondHalfRes__h287816 ; - assign firstHalfRes__h287815 = - firstHalfRes__h287824 ^ secondHalfRes__h287825 ; - assign firstHalfRes__h287824 = - firstHalfRes__h287833 ^ secondHalfRes__h287834 ; - assign firstHalfRes__h287833 = - firstHalfRes__h287842 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[127:96] ; - assign firstHalfRes__h287842 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[63:32] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[95:64] ; - assign firstHalfRes__h290740 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[223:192] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[255:224] ; - assign firstHalfRes__h291524 = - firstHalfRes__h291533 ^ secondHalfRes__h291534 ; - assign firstHalfRes__h291533 = - firstHalfRes__h291542 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[415:384] ; - assign firstHalfRes__h291542 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[351:320] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[383:352] ; - assign firstHalfRes__h293036 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[511:480] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[543:512] ; - assign firstHalfRes__h293820 = - firstHalfRes__h293829 ^ secondHalfRes__h293830 ; - assign firstHalfRes__h293829 = - firstHalfRes__h293838 ^ secondHalfRes__h293839 ; - assign firstHalfRes__h293838 = - firstHalfRes__h293847 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[703:672] ; - assign firstHalfRes__h293847 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[639:608] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[671:640] ; - assign firstHalfRes__h295968 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[799:768] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[831:800] ; - assign firstHalfRes__h296752 = - firstHalfRes__h296761 ^ secondHalfRes__h296762 ; - assign firstHalfRes__h296761 = - firstHalfRes__h296770 ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[991:960] ; - assign firstHalfRes__h296770 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[927:896] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[959:928] ; - assign firstHalfRes__h298264 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1087:1056] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1119:1088] ; - assign interCrc__h169911 = - (shiftAmt__h169932 <= 7'd36) ? - { CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q33, - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q34, - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q35, - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q36, - CASE_shiftAmt69932_0_0_1_crc_crcAxiStream_crcR_ETC__q37, - CASE_shiftAmt69932_0_0_1_0_2_crc_crcAxiStream__ETC__q38, - CASE_shiftAmt69932_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67, - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 } : - 288'd0 ; - assign interCrc__h287463 = firstHalfRes__h287806 ^ secondHalfRes__h287807 ; - assign nextInterCrc__h169222 = - firstHalfRes__h169316 ^ secondHalfRes__h169317 ; - assign nextInterCrc__h169223 = - nextInterCrc__h169222 ^ - crc_crcAxiStream_crcRespFifoOut_reduceCrcResBuf_D_OUT[39:8] ; - assign preProcessRes_data__h13182 = - { crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[0], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[1], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[2], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[3], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[4], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[5], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[6], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[7], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[8], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[9], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[10], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[11], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[12], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[13], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[14], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[15], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[16], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[17], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[18], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[19], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[20], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[21], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[22], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[23], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[24], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[25], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[26], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[27], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[28], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[29], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[30], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[31], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[32], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[33], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[34], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[35], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[36], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[37], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[38], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[39], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[40], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[41], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[42], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[43], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[44], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[45], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[46], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[47], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[48], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[49], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[50], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[51], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[52], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[53], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[54], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[55], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[56], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[57], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[58], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[59], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[60], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[61], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[62], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[63], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[64], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[65], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[66], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[67], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[68], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[69], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[70], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[71], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[72], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[73], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[74], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[75], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[76], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[77], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[78], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[79], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[80], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[81], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[82], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[83], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[84], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[85], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[86], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[87], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[88], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[89], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[90], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[91], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[92], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[93], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[94], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[95], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[96], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[97], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[98], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[99], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[100], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[101], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[102], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[103], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[104], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[105], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[106], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[107], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[108], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[109], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[110], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[111], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[112], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[113], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[114], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[115], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[116], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[117], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[118], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[119], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[120], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[121], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[122], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[123], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[124], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[125], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[126], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[127], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[128], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[129], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[130], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[131], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[132], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[133], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[134], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[135], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[136], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[137], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[138], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[139], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[140], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[141], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[142], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[143], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[144], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[145], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[146], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[147], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[148], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[149], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[150], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[151], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[152], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[153], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[154], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[155], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[156], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[157], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[158], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[159], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[160], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[161], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[162], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[163], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[164], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[165], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[166], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[167], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[168], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[169], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[170], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[171], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[172], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[173], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[174], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[175], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[176], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[177], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[178], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[179], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[180], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[181], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[182], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[183], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[184], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[185], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[186], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[187], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[188], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[189], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[190], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[191], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[192], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[193], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[194], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[195], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[196], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[197], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[198], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[199], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[200], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[201], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[202], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[203], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[204], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[205], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[206], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[207], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[208], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[209], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[210], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[211], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[212], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[213], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[214], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[215], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[216], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[217], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[218], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[219], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[220], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[221], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[222], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[223], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[224], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[225], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[226], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[227], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[228], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[229], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[230], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[231], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[232], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[233], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[234], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[235], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[236], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[237], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[238], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[239], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[240], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[241], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[242], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[243], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[244], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[245], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[246], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[247], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[248], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[249], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[250], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[251], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[252], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[253], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[254], - crc_crcAxiStream_crcReqBuf_first_BIT_33_CONCAT_ETC___d139[255] } ; - assign secondHalfRes__h159837 = - firstHalfRes__h164856 ^ secondHalfRes__h164857 ; - assign secondHalfRes__h159846 = - firstHalfRes__h162982 ^ secondHalfRes__h162983 ; - assign secondHalfRes__h159855 = - firstHalfRes__h162198 ^ secondHalfRes__h162199 ; - assign secondHalfRes__h159864 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[103:72] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[135:104] ; - assign secondHalfRes__h162199 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[231:200] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[263:232] ; - assign secondHalfRes__h162983 = - firstHalfRes__h164072 ^ secondHalfRes__h164073 ; - assign secondHalfRes__h162992 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[359:328] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[391:360] ; - assign secondHalfRes__h164073 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[487:456] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[519:488] ; - assign secondHalfRes__h164857 = - firstHalfRes__h167300 ^ secondHalfRes__h167301 ; - assign secondHalfRes__h164866 = - firstHalfRes__h166516 ^ secondHalfRes__h166517 ; - assign secondHalfRes__h164875 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[615:584] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[647:616] ; - assign secondHalfRes__h166517 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[743:712] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[775:744] ; - assign secondHalfRes__h167301 = - firstHalfRes__h168390 ^ secondHalfRes__h168391 ; - assign secondHalfRes__h167310 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[871:840] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[903:872] ; - assign secondHalfRes__h168391 = - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[999:968] ^ - crc_crcAxiStream_crcRespFifoOut_readCrcTabResBuf_D_OUT[1031:1000] ; - assign secondHalfRes__h169317 = - crc_crcAxiStream_crcRespFifoOut_crcTabVec_34_lookupTable_lookupTable_D_OUT_2 ^ - crc_crcAxiStream_crcRespFifoOut_crcTabVec_35_lookupTable_lookupTable_D_OUT_2 ; - assign secondHalfRes__h287807 = - firstHalfRes__h293820 ^ secondHalfRes__h293821 ; - assign secondHalfRes__h287816 = - firstHalfRes__h291524 ^ secondHalfRes__h291525 ; - assign secondHalfRes__h287825 = - firstHalfRes__h290740 ^ secondHalfRes__h290741 ; - assign secondHalfRes__h287834 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[159:128] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[191:160] ; - assign secondHalfRes__h290741 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[287:256] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[319:288] ; - assign secondHalfRes__h291525 = - firstHalfRes__h293036 ^ secondHalfRes__h293037 ; - assign secondHalfRes__h291534 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[447:416] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[479:448] ; - assign secondHalfRes__h293037 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[575:544] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[607:576] ; - assign secondHalfRes__h293821 = - firstHalfRes__h296752 ^ secondHalfRes__h296753 ; - assign secondHalfRes__h293830 = - firstHalfRes__h295968 ^ secondHalfRes__h295969 ; - assign secondHalfRes__h293839 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[735:704] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[767:736] ; - assign secondHalfRes__h295969 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[863:832] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[895:864] ; - assign secondHalfRes__h296753 = - firstHalfRes__h298264 ^ secondHalfRes__h298265 ; - assign secondHalfRes__h296762 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1023:992] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1055:1024] ; - assign secondHalfRes__h298265 = - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1151:1120] ^ - crc_crcAxiStream_crcRespFifoOut_readInterCrcTabResBuf_D_OUT[1183:1152] ; - assign shiftAmt__h169932 = - { 1'd0, - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[5:0] } ; - assign x_data__h64227 = - (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0] <= - 6'd32) ? - { CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31, - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 } : - 256'd0 ; - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd1, - 6'd2, - 6'd3, - 6'd4, - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q1 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd2, - 6'd3, - 6'd4, - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q2 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd3, - 6'd4, - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q3 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd4, - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q4 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd5, - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q5 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd6, - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q6 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd7, - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q7 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd8, - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q8 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd9, - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q9 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd10, - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q10 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd11, - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q11 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd12, - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q12 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd13, - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q13 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd14, - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q14 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd15, - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q15 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd16, - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q16 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd17, - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q17 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd18, - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q18 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd19, - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q19 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd20, - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q20 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd21, - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q21 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd22, - 6'd23, - 6'd24, - 6'd25, - 6'd26, - 6'd27, - 6'd28, - 6'd29, - 6'd30, - 6'd31, - 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q22 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd23, 6'd24, 6'd25, 6'd26, 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q23 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd24, 6'd25, 6'd26, 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q24 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd25, 6'd26, 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q25 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd26, 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q26 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd27, 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q27 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd28, 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q28 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[39:32]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd28: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd29, 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q29 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[31:24]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[39:32]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd28: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd29: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd30, 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q30 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[23:16]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[31:24]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[39:32]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd28: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd29: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd30: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd31, 6'd32: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q31 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT) - begin - case (crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[5:0]) - 6'd0: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[15:8]; - 6'd1: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[23:16]; - 6'd2: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[31:24]; - 6'd3: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[39:32]; - 6'd4: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[47:40]; - 6'd5: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[55:48]; - 6'd6: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[63:56]; - 6'd7: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[71:64]; - 6'd8: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[79:72]; - 6'd9: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[87:80]; - 6'd10: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[95:88]; - 6'd11: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[103:96]; - 6'd12: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[111:104]; - 6'd13: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[119:112]; - 6'd14: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[127:120]; - 6'd15: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[135:128]; - 6'd16: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[143:136]; - 6'd17: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[151:144]; - 6'd18: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[159:152]; - 6'd19: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[167:160]; - 6'd20: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[175:168]; - 6'd21: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[183:176]; - 6'd22: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[191:184]; - 6'd23: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[199:192]; - 6'd24: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[207:200]; - 6'd25: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[215:208]; - 6'd26: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[223:216]; - 6'd27: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[231:224]; - 6'd28: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[239:232]; - 6'd29: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[247:240]; - 6'd30: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[255:248]; - 6'd31: - CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - crc_crcAxiStream_crcRespFifoOut_preProcessResBuf_D_OUT[263:256]; - 6'd32: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = 8'd0; - default: CASE_crc_crcAxiStream_crcRespFifoOut_preProces_ETC__q32 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q33 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q33 = 8'd0; - default: CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q33 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q34 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd1: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q34 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q34 = 8'd0; - default: CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q34 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q35 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd1: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q35 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd2: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q35 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q35 = 8'd0; - default: CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q35 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q36 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd1: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q36 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd2: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q36 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd3: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q36 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q36 = 8'd0; - default: CASE_shiftAmt69932_0_crc_crcAxiStream_crcRespF_ETC__q36 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = 8'd0; - 7'd1: - CASE_shiftAmt69932_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd2: - CASE_shiftAmt69932_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd3: - CASE_shiftAmt69932_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd4: - CASE_shiftAmt69932_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_crc_crcAxiStream_crcR_ETC__q37 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = 8'd0; - 7'd2: - CASE_shiftAmt69932_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd3: - CASE_shiftAmt69932_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd4: - CASE_shiftAmt69932_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd5: - CASE_shiftAmt69932_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_crc_crcAxiStream__ETC__q38 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = 8'd0; - 7'd3: - CASE_shiftAmt69932_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd4: - CASE_shiftAmt69932_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd5: - CASE_shiftAmt69932_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd6: - CASE_shiftAmt69932_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_crc_crcAxiStr_ETC__q39 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = 8'd0; - 7'd4: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd5: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd6: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd7: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_crc_crcAx_ETC__q40 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = 8'd0; - 7'd5: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd6: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd7: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd8: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_crc_c_ETC__q41 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = 8'd0; - 7'd6: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd7: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd8: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd9: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_c_ETC__q42 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = 8'd0; - 7'd7: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd8: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd9: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd10: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q43 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = 8'd0; - 7'd8: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd9: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd10: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd11: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q44 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = 8'd0; - 7'd9: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd10: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd11: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd12: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q45 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = 8'd0; - 7'd10: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd11: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd12: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd13: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q46 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = 8'd0; - 7'd11: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd12: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd13: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd14: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q47 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = 8'd0; - 7'd12: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd13: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd14: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd15: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q48 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = 8'd0; - 7'd13: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd14: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd15: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd16: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q49 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = 8'd0; - 7'd14: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd15: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd16: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd17: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q50 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = 8'd0; - 7'd15: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd16: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd17: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd18: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q51 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = 8'd0; - 7'd16: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd17: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd18: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd19: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q52 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = 8'd0; - 7'd17: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd18: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd19: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd20: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q53 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = 8'd0; - 7'd18: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd19: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd20: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd21: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q54 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = 8'd0; - 7'd19: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd20: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd21: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd22: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q55 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = 8'd0; - 7'd20: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd21: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd22: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd23: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q56 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = 8'd0; - 7'd21: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd22: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd23: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd24: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q57 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = 8'd0; - 7'd22: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd23: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd24: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd25: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q58 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = 8'd0; - 7'd23: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd24: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd25: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd26: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q59 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = 8'd0; - 7'd24: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd25: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd26: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd27: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q60 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd29, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = 8'd0; - 7'd25: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd26: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd27: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd28: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q61 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd30, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = 8'd0; - 7'd26: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd27: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd28: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd29: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q62 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd31, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = 8'd0; - 7'd27: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd28: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd29: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd30: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q63 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd32, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = 8'd0; - 7'd28: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd29: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd30: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd31: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q64 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd33, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = 8'd0; - 7'd29: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd30: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd31: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd32: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q65 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd34, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = 8'd0; - 7'd30: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd31: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd32: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd33: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q66 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd35, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = 8'd0; - 7'd31: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd32: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd33: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd34: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q67 = - 8'b10101010 /* unspecified value */ ; - endcase - end - always@(shiftAmt__h169932 or - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT) - begin - case (shiftAmt__h169932) - 7'd0, - 7'd1, - 7'd2, - 7'd3, - 7'd4, - 7'd5, - 7'd6, - 7'd7, - 7'd8, - 7'd9, - 7'd10, - 7'd11, - 7'd12, - 7'd13, - 7'd14, - 7'd15, - 7'd16, - 7'd17, - 7'd18, - 7'd19, - 7'd20, - 7'd21, - 7'd22, - 7'd23, - 7'd24, - 7'd25, - 7'd26, - 7'd27, - 7'd28, - 7'd29, - 7'd30, - 7'd31, - 7'd36: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = 8'd0; - 7'd32: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[15:8]; - 7'd33: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[23:16]; - 7'd34: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[31:24]; - 7'd35: - CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - crc_crcAxiStream_crcRespFifoOut_accuCrcResBuf_D_OUT[39:32]; - default: CASE_shiftAmt69932_0_0_1_0_2_0_3_0_4_0_5_0_6_0_ETC__q68 = - 8'b10101010 /* unspecified value */ ; - endcase - end - - // handling of inlined registers - - always@(posedge CLK) - begin - if (RST_N == `BSV_RESET_VALUE) - begin - crc_crcAxiStream_crcRespFifoOut_interCrcRes <= `BSV_ASSIGNMENT_DELAY - 32'hFFFFFFFF; - crc_crcAxiStream_crcRespFifoOut_isFirstFlag <= `BSV_ASSIGNMENT_DELAY - 1'd1; - end - else - begin - if (crc_crcAxiStream_crcRespFifoOut_interCrcRes_EN) - crc_crcAxiStream_crcRespFifoOut_interCrcRes <= `BSV_ASSIGNMENT_DELAY - crc_crcAxiStream_crcRespFifoOut_interCrcRes_D_IN; - if (crc_crcAxiStream_crcRespFifoOut_isFirstFlag_EN) - crc_crcAxiStream_crcRespFifoOut_isFirstFlag <= `BSV_ASSIGNMENT_DELAY - crc_crcAxiStream_crcRespFifoOut_isFirstFlag_D_IN; - end - end - - // synopsys translate_off - `ifdef BSV_NO_INITIAL_BLOCKS - `else // not BSV_NO_INITIAL_BLOCKS - initial - begin - crc_crcAxiStream_crcRespFifoOut_interCrcRes = 32'hAAAAAAAA; - crc_crcAxiStream_crcRespFifoOut_isFirstFlag = 1'h0; - end - `endif // BSV_NO_INITIAL_BLOCKS - // synopsys translate_on -endmodule // mkCrcRawAxiStreamCustomSend - - -`ifdef BSV_WARN_REGFILE_ADDR_RANGE -`else -`define BSV_WARN_REGFILE_ADDR_RANGE 0 -`endif - -`ifdef BSV_ASSIGNMENT_DELAY -`else -`define BSV_ASSIGNMENT_DELAY -`endif - - -// Multi-ported Lookup Table(ROM) -- initializable from a file. -module LookupTableLoadSend( - CLK, - ADDR_1, D_OUT_1, - ADDR_2, D_OUT_2, - ADDR_3, D_OUT_3, - ADDR_4, D_OUT_4, - ADDR_5, D_OUT_5 -); - parameter file = ""; - parameter addr_width = 1; - parameter data_width = 1; - parameter lo = 0; - parameter hi = 1; - parameter binary = 0; - - input CLK; - - input [addr_width - 1 : 0] ADDR_1; - output [data_width - 1 : 0] D_OUT_1; - - input [addr_width - 1 : 0] ADDR_2; - output [data_width - 1 : 0] D_OUT_2; - - input [addr_width - 1 : 0] ADDR_3; - output [data_width - 1 : 0] D_OUT_3; - - input [addr_width - 1 : 0] ADDR_4; - output [data_width - 1 : 0] D_OUT_4; - - input [addr_width - 1 : 0] ADDR_5; - output [data_width - 1 : 0] D_OUT_5; - - reg [data_width - 1 : 0] arr[lo:hi]; - - - initial - begin : init_rom_block - if (binary) - $readmemb(file, arr, lo, hi); - else - $readmemh(file, arr, lo, hi); - end // initial begin - - assign D_OUT_1 = arr[ADDR_1]; - assign D_OUT_2 = arr[ADDR_2]; - assign D_OUT_3 = arr[ADDR_3]; - assign D_OUT_4 = arr[ADDR_4]; - assign D_OUT_5 = arr[ADDR_5]; - -endmodule diff --git a/ethernet/RoCEv2/blue-crc/tab/crc_tab_0.mem b/ethernet/RoCEv2/blue-crc/tab/crc_tab_0.mem deleted file mode 100644 index 3d40d4d253..0000000000 --- a/ethernet/RoCEv2/blue-crc/tab/crc_tab_0.mem +++ /dev/null @@ -1,256 +0,0 @@ -00000000 -00000001 -00000002 -00000003 -00000004 -00000005 -00000006 -00000007 -00000008 -00000009 -0000000a -0000000b -0000000c -0000000d -0000000e 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-afafd6b6 -b487dbce -99ffcc46 -82d7c13e -1a4f8896 -016785ee -2c1f9266 -37379f1e -76efbd76 -6dc7b00e -40bfa786 -5b97aafe -1d0ca0b8 -0624adc0 -2b5cba48 -3074b730 -71ac9558 -6a849820 -47fc8fa8 -5cd482d0 -c44ccb78 -df64c600 -f21cd188 -e934dcf0 -a8ecfe98 -b3c4f3e0 -9ebce468 -8594e910 -ab4d6a8f -b06567f7 -9d1d707f -86357d07 -c7ed5f6f -dcc55217 -f1bd459f -ea9548e7 -720d014f -69250c37 -445d1bbf -5f7516c7 -1ead34af -058539d7 -28fd2e5f -33d52327 diff --git a/ethernet/RoCEv2/blue-lib/BRAM2.v b/ethernet/RoCEv2/blue-lib/BRAM2.v deleted file mode 100644 index 417ee3148c..0000000000 --- a/ethernet/RoCEv2/blue-lib/BRAM2.v +++ /dev/null @@ -1,94 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -// Dual-Ported BRAM (WRITE FIRST) -module BRAM2(CLKA, - ENA, - WEA, - ADDRA, - DIA, - DOA, - CLKB, - ENB, - WEB, - ADDRB, - DIB, - DOB - ); - - parameter PIPELINED = 0; - parameter ADDR_WIDTH = 1; - parameter DATA_WIDTH = 1; - parameter MEMSIZE = 1; - - input CLKA; - input ENA; - input WEA; - input [ADDR_WIDTH-1:0] ADDRA; - input [DATA_WIDTH-1:0] DIA; - output [DATA_WIDTH-1:0] DOA; - - input CLKB; - input ENB; - input WEB; - input [ADDR_WIDTH-1:0] ADDRB; - input [DATA_WIDTH-1:0] DIB; - output [DATA_WIDTH-1:0] DOB; - - reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ; - reg [DATA_WIDTH-1:0] DOA_R; - reg [DATA_WIDTH-1:0] DOB_R; - reg [DATA_WIDTH-1:0] DOA_R2; - reg [DATA_WIDTH-1:0] DOB_R2; - -`ifdef BSV_NO_INITIAL_BLOCKS -`else - // synopsys translate_off - integer i; - initial - begin : init_block - for (i = 0; i < MEMSIZE; i = i + 1) begin - RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } }; - end - DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; - DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } }; - DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; - DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } }; - end - // synopsys translate_on -`endif // !`ifdef BSV_NO_INITIAL_BLOCKS - - always @(posedge CLKA) begin - if (ENA) begin - if (WEA) begin - RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA; - DOA_R <= `BSV_ASSIGNMENT_DELAY DIA; - end - else begin - DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA]; - end - end - DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R; - end - - always @(posedge CLKB) begin - if (ENB) begin - if (WEB) begin - RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB; - DOB_R <= `BSV_ASSIGNMENT_DELAY DIB; - end - else begin - DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB]; - end - end - DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R; - end - - // Output drivers - assign DOA = (PIPELINED) ? DOA_R2 : DOA_R; - assign DOB = (PIPELINED) ? DOB_R2 : DOB_R; - -endmodule // BRAM2 diff --git a/ethernet/RoCEv2/blue-lib/BypassWire.v b/ethernet/RoCEv2/blue-lib/BypassWire.v deleted file mode 100644 index c6fbf8804a..0000000000 --- a/ethernet/RoCEv2/blue-lib/BypassWire.v +++ /dev/null @@ -1,13 +0,0 @@ - -module BypassWire(WGET, WVAL); - - - parameter width = 1; - - input [width - 1 : 0] WVAL; - - output [width - 1 : 0] WGET; - - assign WGET = WVAL; - -endmodule diff --git a/ethernet/RoCEv2/blue-lib/CRegN5.v b/ethernet/RoCEv2/blue-lib/CRegN5.v deleted file mode 100644 index fd22e366be..0000000000 --- a/ethernet/RoCEv2/blue-lib/CRegN5.v +++ /dev/null @@ -1,103 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - - -module CRegN5 - (CLK, - RST, - - // port 0 read - Q_OUT_0, - // port 0 write - EN_0, D_IN_0, - - // port 1 read - Q_OUT_1, - // port 1 write - EN_1, D_IN_1, - - // port 2 read - Q_OUT_2, - // port 2 write - EN_2, D_IN_2, - - // port 3 read - Q_OUT_3, - // port 3 write - EN_3, D_IN_3, - - // port 4 read - Q_OUT_4, - // port 4 write - EN_4, D_IN_4 - ); - - parameter width = 1 ; - parameter init = { width {1'b0} } ; - - input CLK ; - input RST ; - - output [width - 1 : 0] Q_OUT_0 ; - input EN_0 ; - input [width - 1 : 0] D_IN_0 ; - - output [width - 1 : 0] Q_OUT_1 ; - input EN_1 ; - input [width - 1 : 0] D_IN_1 ; - - output [width - 1 : 0] Q_OUT_2 ; - input EN_2 ; - input [width - 1 : 0] D_IN_2 ; - - output [width - 1 : 0] Q_OUT_3 ; - input EN_3 ; - input [width - 1 : 0] D_IN_3 ; - - output [width - 1 : 0] Q_OUT_4 ; - input EN_4 ; - input [width - 1 : 0] D_IN_4 ; - - reg [width - 1 : 0] Q_OUT_0 ; - wire [width - 1 : 0] Q_OUT_1 ; - wire [width - 1 : 0] Q_OUT_2 ; - wire [width - 1 : 0] Q_OUT_3 ; - wire [width - 1 : 0] Q_OUT_4 ; - wire [width - 1 : 0] Q_OUT_5 ; - - assign Q_OUT_1 = EN_0 ? D_IN_0 : Q_OUT_0 ; - assign Q_OUT_2 = EN_1 ? D_IN_1 : Q_OUT_1 ; - assign Q_OUT_3 = EN_2 ? D_IN_2 : Q_OUT_2 ; - assign Q_OUT_4 = EN_3 ? D_IN_3 : Q_OUT_3 ; - assign Q_OUT_5 = EN_4 ? D_IN_4 : Q_OUT_4 ; - - always@(posedge CLK) - begin - if (RST == `BSV_RESET_VALUE) - Q_OUT_0 <= `BSV_ASSIGNMENT_DELAY init ; - else - Q_OUT_0 <= `BSV_ASSIGNMENT_DELAY Q_OUT_5 ; - end - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial begin - Q_OUT_0 = {((width + 1)/2){2'b10}} ; - end - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - -endmodule - diff --git a/ethernet/RoCEv2/blue-lib/CRegUN5.v b/ethernet/RoCEv2/blue-lib/CRegUN5.v deleted file mode 100644 index 25682c15b6..0000000000 --- a/ethernet/RoCEv2/blue-lib/CRegUN5.v +++ /dev/null @@ -1,92 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - - -module CRegUN5 - (CLK, - RST, - - // port 0 read - Q_OUT_0, - // port 0 write - EN_0, D_IN_0, - - // port 1 read - Q_OUT_1, - // port 1 write - EN_1, D_IN_1, - - // port 2 read - Q_OUT_2, - // port 2 write - EN_2, D_IN_2, - - // port 3 read - Q_OUT_3, - // port 3 write - EN_3, D_IN_3, - - // port 4 read - Q_OUT_4, - // port 4 write - EN_4, D_IN_4 - ); - - parameter width = 1 ; - parameter init = { width {1'b0} } ; - - input CLK ; - input RST ; - - output [width - 1 : 0] Q_OUT_0 ; - input EN_0 ; - input [width - 1 : 0] D_IN_0 ; - - output [width - 1 : 0] Q_OUT_1 ; - input EN_1 ; - input [width - 1 : 0] D_IN_1 ; - - output [width - 1 : 0] Q_OUT_2 ; - input EN_2 ; - input [width - 1 : 0] D_IN_2 ; - - output [width - 1 : 0] Q_OUT_3 ; - input EN_3 ; - input [width - 1 : 0] D_IN_3 ; - - output [width - 1 : 0] Q_OUT_4 ; - input EN_4 ; - input [width - 1 : 0] D_IN_4 ; - - reg [width - 1 : 0] Q_OUT_0 ; - wire [width - 1 : 0] Q_OUT_1 ; - wire [width - 1 : 0] Q_OUT_2 ; - wire [width - 1 : 0] Q_OUT_3 ; - wire [width - 1 : 0] Q_OUT_4 ; - wire [width - 1 : 0] Q_OUT_5 ; - - assign Q_OUT_1 = EN_0 ? D_IN_0 : Q_OUT_0 ; - assign Q_OUT_2 = EN_1 ? D_IN_1 : Q_OUT_1 ; - assign Q_OUT_3 = EN_2 ? D_IN_2 : Q_OUT_2 ; - assign Q_OUT_4 = EN_3 ? D_IN_3 : Q_OUT_3 ; - assign Q_OUT_5 = EN_4 ? D_IN_4 : Q_OUT_4 ; - - always@(posedge CLK) - begin - Q_OUT_0 <= `BSV_ASSIGNMENT_DELAY Q_OUT_5 ; - end - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial begin - Q_OUT_0 = {((width + 1)/2){2'b10}} ; - end - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - -endmodule - diff --git a/ethernet/RoCEv2/blue-lib/ConfigRegN.v b/ethernet/RoCEv2/blue-lib/ConfigRegN.v deleted file mode 100644 index 05c5aed665..0000000000 --- a/ethernet/RoCEv2/blue-lib/ConfigRegN.v +++ /dev/null @@ -1,50 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - - -module ConfigRegN(CLK, RST, Q_OUT, D_IN, EN); - - parameter width = 1; - parameter init = { width {1'b0} } ; - - input CLK; - input RST; - input EN; - input [width - 1 : 0] D_IN; - output [width - 1 : 0] Q_OUT; - - reg [width - 1 : 0] Q_OUT; - - always@(posedge CLK) - begin - if (RST == `BSV_RESET_VALUE) - Q_OUT <= `BSV_ASSIGNMENT_DELAY init; - else - begin - if (EN) - Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; - end // else: !if(RST == `BSV_RESET_VALUE) - end - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial begin - Q_OUT = {((width + 1)/2){2'b10}} ; - end - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - -endmodule - diff --git a/ethernet/RoCEv2/blue-lib/Counter.v b/ethernet/RoCEv2/blue-lib/Counter.v deleted file mode 100644 index fc51e0cfa4..0000000000 --- a/ethernet/RoCEv2/blue-lib/Counter.v +++ /dev/null @@ -1,75 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - - -`ifdef BSV_ASYNC_RESET - `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST -`else - `define BSV_ARESET_EDGE_META -`endif - - -// N -bit counter with load, set and 2 increment -module Counter(CLK, - RST, - Q_OUT, - DATA_A, ADDA, - DATA_B, ADDB, - DATA_C, SETC, - DATA_F, SETF); - - parameter width = 1; - parameter init = 0; - - input CLK; - input RST; - input [width - 1 : 0] DATA_A; - input ADDA; - input [width - 1 : 0] DATA_B; - input ADDB; - input [width - 1 : 0] DATA_C; - input SETC; - input [width - 1 : 0] DATA_F; - input SETF; - - output [width - 1 : 0] Q_OUT; - - - - reg [width - 1 : 0] q_state ; - - assign Q_OUT = q_state ; - - always@(posedge CLK `BSV_ARESET_EDGE_META) begin - if (RST == `BSV_RESET_VALUE) - q_state <= `BSV_ASSIGNMENT_DELAY init; - else - begin - if ( SETF ) - q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ; - else - q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ; - end // else: !if(RST == `BSV_RESET_VALUE) - end // always@ (posedge CLK) - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial begin - q_state = {((width + 1)/2){2'b10}} ; - end - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - -endmodule diff --git a/ethernet/RoCEv2/blue-lib/FIFO2.v b/ethernet/RoCEv2/blue-lib/FIFO2.v deleted file mode 100644 index 070b518865..0000000000 --- a/ethernet/RoCEv2/blue-lib/FIFO2.v +++ /dev/null @@ -1,153 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -`ifdef BSV_ASYNC_RESET - `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST -`else - `define BSV_ARESET_EDGE_META -`endif - -`ifdef BSV_RESET_FIFO_HEAD - `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META -`else - `define BSV_ARESET_EDGE_HEAD -`endif - -// Depth 2 FIFO -module FIFO2(CLK, - RST, - D_IN, - ENQ, - FULL_N, - D_OUT, - DEQ, - EMPTY_N, - CLR); - - parameter width = 1; - parameter guarded = 1'b1; - - input CLK ; - input RST ; - input [width - 1 : 0] D_IN; - input ENQ; - input DEQ; - input CLR ; - - output FULL_N; - output EMPTY_N; - output [width - 1 : 0] D_OUT; - - reg full_reg; - reg empty_reg; - reg [width - 1 : 0] data0_reg; - reg [width - 1 : 0] data1_reg; - - assign FULL_N = full_reg ; - assign EMPTY_N = empty_reg ; - assign D_OUT = data0_reg ; - - - // Optimize the loading logic since state encoding is not power of 2! - wire d0di = (ENQ && ! empty_reg ) || ( ENQ && DEQ && full_reg ) ; - wire d0d1 = DEQ && ! full_reg ; - wire d0h = ((! DEQ) && (! ENQ )) || (!DEQ && empty_reg ) || ( ! ENQ &&full_reg) ; - wire d1di = ENQ & empty_reg ; - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial - begin - data0_reg = {((width + 1)/2) {2'b10}} ; - data1_reg = {((width + 1)/2) {2'b10}} ; - empty_reg = 1'b0; - full_reg = 1'b1; - end // initial begin - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - - always@(posedge CLK `BSV_ARESET_EDGE_META) - begin - if (RST == `BSV_RESET_VALUE) - begin - empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; - full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - end // if (RST == `BSV_RESET_VALUE) - else - begin - if (CLR) - begin - empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; - full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - end // if (CLR) - else if ( ENQ && ! DEQ ) // just enq - begin - empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg ; - end - else if ( DEQ && ! ENQ ) - begin - full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg; - end // if ( DEQ && ! ENQ ) - end // else: !if(RST == `BSV_RESET_VALUE) - - end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - - - always@(posedge CLK `BSV_ARESET_EDGE_HEAD) - begin -`ifdef BSV_RESET_FIFO_HEAD - if (RST == `BSV_RESET_VALUE) - begin - data0_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ; - data1_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ; - end - else -`endif - begin - data0_reg <= `BSV_ASSIGNMENT_DELAY - {width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ; - data1_reg <= `BSV_ASSIGNMENT_DELAY - d1di ? D_IN : data1_reg ; - end // else: !if(RST == `BSV_RESET_VALUE) - end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - - - - // synopsys translate_off - always@(posedge CLK) - begin: error_checks - reg deqerror, enqerror ; - - deqerror = 0; - enqerror = 0; - if (RST == ! `BSV_RESET_VALUE) - begin - if ( ! empty_reg && DEQ ) - begin - deqerror = 1; - $display( "Warning: FIFO2: %m -- Dequeuing from empty fifo" ) ; - end - if ( ! full_reg && ENQ && (!DEQ || guarded) ) - begin - enqerror = 1; - $display( "Warning: FIFO2: %m -- Enqueuing to a full fifo" ) ; - end - end - end // always@ (posedge CLK) - // synopsys translate_on - -endmodule diff --git a/ethernet/RoCEv2/blue-lib/FIFO20.v b/ethernet/RoCEv2/blue-lib/FIFO20.v deleted file mode 100644 index e06e428545..0000000000 --- a/ethernet/RoCEv2/blue-lib/FIFO20.v +++ /dev/null @@ -1,110 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - - -`ifdef BSV_ASYNC_RESET - `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST -`else - `define BSV_ARESET_EDGE_META -`endif - - -// Depth 2 FIFO Data width 0 -module FIFO20(CLK, - RST, - ENQ, - FULL_N, - DEQ, - EMPTY_N, - CLR - ); - parameter guarded = 1'b1; - - input RST; - input CLK; - input ENQ; - input CLR; - input DEQ; - - output FULL_N; - output EMPTY_N; - - reg empty_reg; - reg full_reg; - - assign FULL_N = full_reg ; - assign EMPTY_N = empty_reg ; - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial - begin - empty_reg = 1'b0 ; - full_reg = 1'b1 ; - end // initial begin - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - - always@(posedge CLK `BSV_ARESET_EDGE_META) - begin - if (RST == `BSV_RESET_VALUE) - begin - empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; - full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - end // if (RST == `BSV_RESET_VALUE) - else - begin - if (CLR) - begin - empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0; - full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - end - else if (ENQ && !DEQ) - begin - empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg; - end // if (ENQ && !DEQ) - else if (!ENQ && DEQ) - begin - full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1; - empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg; - end // if (!ENQ && DEQ) - end // else: !if(RST == `BSV_RESET_VALUE) - end // always@ (posedge CLK or `BSV_RESET_EDGE RST) - - // synopsys translate_off - always@(posedge CLK) - begin: error_checks - reg deqerror, enqerror ; - - deqerror = 0; - enqerror = 0; - if (RST == ! `BSV_RESET_VALUE) - begin - if ( ! empty_reg && DEQ ) - begin - deqerror = 1 ; - $display( "Warning: FIFO20: %m -- Dequeuing from empty fifo" ) ; - end - if ( ! full_reg && ENQ && (!DEQ || guarded) ) - begin - enqerror = 1 ; - $display( "Warning: FIFO20: %m -- Enqueuing to a full fifo" ) ; - end - end // if (RST == ! `BSV_RESET_VALUE) - end - // synopsys translate_on - -endmodule diff --git a/ethernet/RoCEv2/blue-lib/README.md b/ethernet/RoCEv2/blue-lib/README.md deleted file mode 100644 index e762d7e3aa..0000000000 --- a/ethernet/RoCEv2/blue-lib/README.md +++ /dev/null @@ -1,3 +0,0 @@ -These files are taken from the [B-Lang-org/bsc](https://github.com/B-Lang-org/bsc) repo. - -The license file from the original repo applies to the files in this folder diff --git a/ethernet/RoCEv2/blue-lib/RWire.v b/ethernet/RoCEv2/blue-lib/RWire.v deleted file mode 100644 index c4b366d0a7..0000000000 --- a/ethernet/RoCEv2/blue-lib/RWire.v +++ /dev/null @@ -1,22 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else -`define BSV_ASSIGNMENT_DELAY -`endif - - -module RWire(WGET, WHAS, WVAL, WSET); - - - parameter width = 1; - - input [width - 1 : 0] WVAL; - input WSET; - - output [width - 1 : 0] WGET; - output WHAS; - - assign WGET = WVAL; - assign WHAS = WSET; - -endmodule diff --git a/ethernet/RoCEv2/blue-lib/RWire0.v b/ethernet/RoCEv2/blue-lib/RWire0.v deleted file mode 100644 index 02eb7ce0f1..0000000000 --- a/ethernet/RoCEv2/blue-lib/RWire0.v +++ /dev/null @@ -1,14 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else -`define BSV_ASSIGNMENT_DELAY -`endif - - -module RWire0(WHAS, WSET); - input WSET; - output WHAS; - - assign WHAS = WSET; - -endmodule diff --git a/ethernet/RoCEv2/blue-lib/RegN.v b/ethernet/RoCEv2/blue-lib/RegN.v deleted file mode 100644 index 9798617824..0000000000 --- a/ethernet/RoCEv2/blue-lib/RegN.v +++ /dev/null @@ -1,50 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - - -module RegN(CLK, RST, Q_OUT, D_IN, EN); - - parameter width = 1; - parameter init = { width {1'b0} } ; - - input CLK; - input RST; - input EN; - input [width - 1 : 0] D_IN; - output [width - 1 : 0] Q_OUT; - - reg [width - 1 : 0] Q_OUT; - - always@(posedge CLK) - begin - if (RST == `BSV_RESET_VALUE) - Q_OUT <= `BSV_ASSIGNMENT_DELAY init; - else - begin - if (EN) - Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; - end // else: !if(RST == `BSV_RESET_VALUE) - end - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial begin - Q_OUT = {((width + 1)/2){2'b10}} ; - end - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - -endmodule - diff --git a/ethernet/RoCEv2/blue-lib/RegUN.v b/ethernet/RoCEv2/blue-lib/RegUN.v deleted file mode 100644 index 5630f824bd..0000000000 --- a/ethernet/RoCEv2/blue-lib/RegUN.v +++ /dev/null @@ -1,35 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else -`define BSV_ASSIGNMENT_DELAY -`endif - - -// Basic register without reset. -module RegUN(CLK, EN, D_IN, Q_OUT); - parameter width = 1; - - input CLK; - input EN; - input [width - 1 : 0] D_IN; - - output [width - 1 : 0] Q_OUT; - reg [width - 1 : 0] Q_OUT; - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial begin - Q_OUT = {((width + 1)/2){2'b10}} ; - end - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - - - always@(posedge CLK) - begin - if (EN) - Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; - end -endmodule - diff --git a/ethernet/RoCEv2/blue-lib/SizedFIFO.v b/ethernet/RoCEv2/blue-lib/SizedFIFO.v deleted file mode 100644 index 18714ac6ab..0000000000 --- a/ethernet/RoCEv2/blue-lib/SizedFIFO.v +++ /dev/null @@ -1,258 +0,0 @@ - -`ifdef BSV_ASSIGNMENT_DELAY -`else - `define BSV_ASSIGNMENT_DELAY -`endif - -`ifdef BSV_POSITIVE_RESET - `define BSV_RESET_VALUE 1'b1 - `define BSV_RESET_EDGE posedge -`else - `define BSV_RESET_VALUE 1'b0 - `define BSV_RESET_EDGE negedge -`endif - -`ifdef BSV_ASYNC_RESET - `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST -`else - `define BSV_ARESET_EDGE_META -`endif - -`ifdef BSV_RESET_FIFO_HEAD - `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META -`else - `define BSV_ARESET_EDGE_HEAD -`endif - -`ifdef BSV_RESET_FIFO_ARRAY - `define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META -`else - `define BSV_ARESET_EDGE_ARRAY -`endif - - -// Sized fifo. Model has output register which improves timing -module SizedFIFO(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR); - parameter p1width = 1; // data width - parameter p2depth = 3; - parameter p3cntr_width = 1; // log(p2depth-1) - // The -1 is allowed since this model has a fast output register - parameter guarded = 1'b1; - localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ; - - input CLK; - input RST; - input CLR; - input [p1width - 1 : 0] D_IN; - input ENQ; - input DEQ; - - output FULL_N; - output EMPTY_N; - output [p1width - 1 : 0] D_OUT; - - reg not_ring_full; - reg ring_empty; - - reg [p3cntr_width-1 : 0] head; - wire [p3cntr_width-1 : 0] next_head; - - reg [p3cntr_width-1 : 0] tail; - wire [p3cntr_width-1 : 0] next_tail; - - // if the depth is too small, don't create an ill-sized array; - // instead, make a 1-sized array and let the initial block report an error - reg [p1width - 1 : 0] arr[0: p2depth2]; - - reg [p1width - 1 : 0] D_OUT; - reg hasodata; - - wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ; - - wire [p3cntr_width-1 : 0] incr_tail; - wire [p3cntr_width-1 : 0] incr_head; - - assign incr_tail = tail + 1'b1 ; - assign incr_head = head + 1'b1 ; - - assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ; - assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ; - - assign EMPTY_N = hasodata; - assign FULL_N = not_ring_full; - -`ifdef BSV_NO_INITIAL_BLOCKS -`else // not BSV_NO_INITIAL_BLOCKS - // synopsys translate_off - initial - begin : initial_block - integer i; - D_OUT = {((p1width + 1)/2){2'b10}} ; - - ring_empty = 1'b1; - not_ring_full = 1'b1; - hasodata = 1'b0; - head = {p3cntr_width {1'b0}} ; - tail = {p3cntr_width {1'b0}} ; - - for (i = 0; i <= p2depth2; i = i + 1) - begin - arr[i] = D_OUT ; - end - end - // synopsys translate_on -`endif // BSV_NO_INITIAL_BLOCKS - - - always @(posedge CLK `BSV_ARESET_EDGE_META) - begin - if (RST == `BSV_RESET_VALUE) - begin - head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; - tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; - ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1; - not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1; - hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0; - end // if (RST == `BSV_RESET_VALUE) - else - begin - - casez ({CLR, DEQ, ENQ, hasodata, ring_empty}) - // Clear operation - 5'b1????: begin - head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; - tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ; - ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1; - not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1; - hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0; - end - // ----------------------- - // DEQ && ENQ case -- change head and tail if added to ring - 5'b011?0: begin - tail <= `BSV_ASSIGNMENT_DELAY next_tail; - head <= `BSV_ASSIGNMENT_DELAY next_head; - end - // ----------------------- - // DEQ only and NO data is in ring - 5'b010?1: begin - hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0; - end - // DEQ only and data is in ring (move the head pointer) - 5'b010?0: begin - head <= `BSV_ASSIGNMENT_DELAY next_head; - not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1; - ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ; - end - // ----------------------- - // ENQ only when empty - 5'b0010?: begin - hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1; - end - // ENQ only when not empty - 5'b0011?: begin - if ( not_ring_full ) // Drop this test to save redundant test - // but be warnned that with test fifo overflow causes loss of new data - // while without test fifo drops all but head entry! (pointer overflow) - begin - tail <= `BSV_ASSIGNMENT_DELAY next_tail; - ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0; - not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ; - end - end - endcase - end // else: !if(RST == `BSV_RESET_VALUE) - end // always @ (posedge CLK) - - // Update the fast data out register - always @(posedge CLK `BSV_ARESET_EDGE_HEAD) - begin -`ifdef BSV_RESET_FIFO_HEAD - if (RST == `BSV_RESET_VALUE) - begin - D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ; - end // if (RST == `BSV_RESET_VALUE) - else -`endif - begin - casez ({CLR, DEQ, ENQ, hasodata, ring_empty}) - // DEQ && ENQ cases - 5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end - 5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end - // DEQ only and data is in ring - 5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end - // ENQ only when empty - 5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end - endcase - end // else: !if(RST == `BSV_RESET_VALUE) - end // always @ (posedge CLK) - - // Update the memory array reset is OFF - always @(posedge CLK `BSV_ARESET_EDGE_ARRAY) - begin: array -`ifdef BSV_RESET_FIFO_ARRAY - if (RST == `BSV_RESET_VALUE) - begin: rst_array - integer i; - for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1) - begin - arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ; - end - end // if (RST == `BSV_RESET_VALUE) - else -`endif - begin - if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full))) - begin - arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN; - end - end // else: !if(RST == `BSV_RESET_VALUE) - end // always @ (posedge CLK) - - // synopsys translate_off - always@(posedge CLK) - begin: error_checks - reg deqerror, enqerror ; - - deqerror = 0; - enqerror = 0; - if (RST == ! `BSV_RESET_VALUE) - begin - if ( ! EMPTY_N && DEQ ) - begin - deqerror = 1 ; - $display( "Warning: SizedFIFO: %m -- Dequeuing from empty fifo" ) ; - end - if ( ! FULL_N && ENQ && (!DEQ || guarded) ) - begin - enqerror = 1 ; - $display( "Warning: SizedFIFO: %m -- Enqueuing to a full fifo" ) ; - end - end - end // block: error_checks - // synopsys translate_on - - // synopsys translate_off - // Some assertions about parameter values - initial - begin : parameter_assertions - integer ok ; - ok = 1 ; - - if ( p2depth <= 1) - begin - ok = 0; - $display ( "Warning SizedFIFO: %m -- depth parameter increased from %0d to 2", p2depth); - end - - if ( p3cntr_width <= 0 ) - begin - ok = 0; - $display ( "ERROR SizedFIFO: %m -- width parameter must be greater than 0" ) ; - end - - if ( ok == 0 ) $finish ; - - end // initial begin - // synopsys translate_on - -endmodule diff --git a/ethernet/RoCEv2/ruckus.tcl b/ethernet/RoCEv2/ruckus.tcl index 0cfbc0c112..f46f7f52bf 100644 --- a/ethernet/RoCEv2/ruckus.tcl +++ b/ethernet/RoCEv2/ruckus.tcl @@ -2,11 +2,4 @@ source $::env(RUCKUS_PROC_TCL) # Load Source Code -loadSource -lib surf -dir "$::DIR_PATH/rtl" -loadSource -lib surf -dir "$::DIR_PATH/blue-crc" -loadSource -lib surf -dir "$::DIR_PATH/blue-lib" - -# Load mem files -for {set i 0} {$i <= 35} {incr i} { - add_files -norecurse "$::DIR_PATH/blue-crc/tab/crc_tab_$i.mem" -} +loadSource -lib surf -fileType "VHDL 2008" -dir "$::DIR_PATH/rtl" From a6bbe0a6da24c478de49e091c4a3ec7dce9cea3e Mon Sep 17 00:00:00 2001 From: FilMarini Date: Fri, 17 Jul 2026 09:19:33 +0200 Subject: [PATCH 8/8] bug fixes when used in multi-QP conf --- .../RoCEv2/rtl/PayloadConsumerConAndGen.vhd | 41 +++++++- ethernet/RoCEv2/rtl/ReqGenSq.vhd | 96 ++++++++++++++++--- ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd | 2 +- 3 files changed, 124 insertions(+), 15 deletions(-) diff --git a/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd b/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd index e7485ec21c..fb80b68523 100644 --- a/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd +++ b/ethernet/RoCEv2/rtl/PayloadConsumerConAndGen.vhd @@ -24,6 +24,13 @@ -- R5 genConResp — get the DmaWriteResp, build the PayloadConResp, enq it. -- R6 flushDmaWriteResp / R7 flushPipelineQ / R8 flushPayloadConResp — error-mode -- drains (see Clear / error-flush below). +-- R9 errDrainPayload — error-mode payload sink (BUGFIX 2026-07-16, no BSV +-- counterpart): while isErr, deq payloadPipeIn every +-- cycle it offers a fragment and drop it (the child is +-- masked off). Without it an erred QP stops sinking +-- payload (bufRst holds U_PayloadBufQ in reset, so the +-- child never deqs) and the SHARED InputRdmaPktBuf +-- jams head-of-line, freezing ingress for every QP. -- -- Mode inputs (cntrlStatus.comm; one-hot, NOT state): -- isReset guards R0 (clear all); isNonErr guards R1-R5; isErr guards R1-R3,R6-R8. @@ -262,6 +269,12 @@ architecture rtl of PayloadConsumerConAndGen is signal bufPipeFirst : slv(289 downto 0); signal bufPipeDeq : sl; + -- R9 errDrainPayload (see error-flush note below): child-facing view of the + -- payloadPipeIn face; in isErr the child is masked off and the fragments + -- are sunk directly. + signal childPipeInNotEmpty : sl; + signal childPipeInDeq : sl; + begin --------------------------------------------------------------------------- @@ -275,6 +288,27 @@ begin pendDmaRst <= rst or isReset or isErr; -- + R7 bufRst <= rst or isReset or isErr; -- + R7 + --------------------------------------------------------------------------- + -- R9 errDrainPayload (BUGFIX 2026-07-16, no BSV counterpart): while isErr, + -- sink payloadPipeIn unconditionally and mask it off the child. + -- + -- Packets addressed to an ERR QP pass header validation BY DESIGN + -- (InputRdmaPktBufAndHeaderValidation validateHeader: statusIsERR -> + -- qpStateMatch true) so the erred QP's flush rules can consume them. But + -- with U_PayloadBufQ held in reset by R7 (bufRst above), the child's + -- bramQNotFull is low for as long as the QP sits in ERR, so the child + -- never deqs payloadPipeIn: an erred QP stopped sinking payload, its + -- RdmaPktMetaDataAndPayloadPipe backed up mid-packet (so no further meta + -- -> no further Discard tokens either), and the SHARED input packet buffer + -- jammed head-of-line — freezing ingress for EVERY QP of the + -- TransportLayer. Token/fragment pairing is irrelevant during ERR (R7 + -- discards the tokens); everything is cleared by R0 on the ERR->RESET + -- transition before the QP can be reused. + --------------------------------------------------------------------------- + childPipeInNotEmpty <= payloadPipeInValid and (not isErr); + payloadPipeInReady <= (payloadPipeInValid and isErr) or + (childPipeInDeq and (not isErr)); + -- srvPort response valid/data are driven directly by U_PayloadConRespQ -- (valid => respOutValid, dout => respOutData below); request ready by -- U_PayloadConReqQ (not_full => reqInReady). @@ -475,10 +509,11 @@ begin clk => clk, rst => rst, clearEnI => isReset, -- R0 child clear - -- pipeIn (entity input pipe) - pipeInNotEmpty => payloadPipeInValid, + -- pipeIn (entity input pipe; masked off + free-drained during isErr, + -- see R9 errDrainPayload above) + pipeInNotEmpty => childPipeInNotEmpty, pipeInFirst => payloadPipeInData, - pipeInDeq => payloadPipeInReady, + pipeInDeq => childPipeInDeq, -- bramQ (parent-owned U_PayloadBufQ) bramQNotFull => bufNotFull, bramQWrEn => bufWrEn, diff --git a/ethernet/RoCEv2/rtl/ReqGenSq.vhd b/ethernet/RoCEv2/rtl/ReqGenSq.vhd index 9b92427622..0a61f06ac7 100644 --- a/ethernet/RoCEv2/rtl/ReqGenSq.vhd +++ b/ethernet/RoCEv2/rtl/ReqGenSq.vhd @@ -759,6 +759,13 @@ begin variable r11Guard : sl; variable r11Fire : sl; variable r11DoEnq : sl; + -- R11a-d errFlushStrandedWR (BUGFIX 2026-07-16): error-drain of the + -- stage-2..6 intermediate FIFOs (see Stage 11 comment) + variable errFlushMode : sl; + variable r11aPwr, r11bPwr, r11cPwr, r11dPwr : slv(678 downto 0); + variable r11aEnq, r11bEnq, r11cEnq, r11dEnq : sl; + variable r11aFire, r11bFire, r11cFire, r11dFire : sl; + variable r11aDoEnq, r11bDoEnq, r11cDoEnq, r11dDoEnq : sl; begin v := r; @@ -869,7 +876,7 @@ begin r3Fire := notReset and isStableRTS and r.isNormalStateReg and wrPktNumValid and wrPsnNotFull; - wrPktNumRdEn <= r3Fire; + -- wrPktNumRdEn driven after Stage 11 (r3Fire or errFlush R11a) wrPsnWrEn <= r3Fire; wrPsnDin <= r3Pwr & r3Wi; -- Tuple2(pendingWR, workReqInfo) @@ -910,7 +917,7 @@ begin npsnWrEn <= r4Fire and r4IsNew; -- contextSQ.setNPSN npsnOut <= r4NextPsn; - wrPsnRdEn <= r4Fire; + -- wrPsnRdEn driven after Stage 11 (r4Fire or errFlush R11b) wrChkWrEn <= r4Fire; wrChkDin <= r4Pwr & r4Wi; -- Tuple2(pendingWR, workReqInfo) @@ -926,7 +933,7 @@ begin r5Fire := notReset and isStableRTS and r.isNormalStateReg and wrChkValid and wrOutNotFull and (not r5Valid or reqCntNotFull); - wrChkRdEn <= r5Fire; + -- wrChkRdEn driven after Stage 11 (r5Fire or errFlush R11c) reqCntWrEn <= r5Fire and r5Valid; reqCntDin <= r5Pwr & r5Wi; wrOutWrEn <= r5Fire; @@ -941,7 +948,7 @@ begin r6Fire := notReset and isStableRTS and r.isNormalStateReg and wrOutValid and (not r6Enq or pwrOutNotFull); - wrOutRdEn <= r6Fire; + -- wrOutRdEn driven after Stage 11 (r6Fire or errFlush R11d) r6DoEnq := r6Fire and r6Enq; ---------------------------------------------------------------------- @@ -1085,22 +1092,89 @@ begin ---------------------------------------------------------------------- -- Stage 11 : errFlushWR (guard isERR || (isRTS && !isNormalStateReg)) + -- + -- BUGFIX 2026-07-16 (R11a-d errFlushStrandedWR): the original flush + -- drained ONLY workReqPayloadGenQ (wrPg). WRs admitted into the normal + -- pipeline in the few cycles between the fatal WC (whose pendingWR pop + -- reopens the NewPendingWorkReqPipeOut window) and the QP's isERR + -- assertion get consumed by R2 and are then STRANDED in the frozen + -- stage-2..6 FIFOs (wrPktNumQ / wrPsnQ / wrChkQ / wrOutQ) — their flush + -- WCs are never generated (observed: suite tests 7/8 in the two-QP + -- topology lose the last 3-4 WCs). R11a-d drain those FIFOs in ERR, + -- OLDEST FIRST (wrOut > wrChk > wrPsn > wrPktNum > wrPg, one per cycle) + -- to keep flush-WC submission order. Enq condition per entry is the + -- same isNewWorkReq && isReliableConnection as R11/R6 (a stranded retry + -- REPLAY is deq'd without enq — its pending entry lives in ScanFifoF + -- and is flushed by RespHandleSq). The stage-5 fork duplicate in + -- reqCntQ stays inert (stage 7 is frozen in ERR; cleared on isReset). + -- The stage rules R3-R6 are frozen in both err-flush guard arms + -- (isStableRTS=0 resp. isNormalStateReg=0), so the rdEn ORs below never + -- double-fire. ---------------------------------------------------------------------- + errFlushMode := notReset and (isERR or (isRTS and not r.isNormalStateReg)); + + -- R11d : wrOutQ (stage-6 input; oldest) + r11dPwr := wrOutDout(683 downto 5); + r11dEnq := wrOutDout(4) and wrOutDout(2); -- wi: isNewWorkReq && isRC + r11dFire := errFlushMode and wrOutValid and (not r11dEnq or pwrOutNotFull); + r11dDoEnq := r11dFire and r11dEnq; + + -- R11c : wrChkQ (stage-5 input) + r11cPwr := wrChkDout(683 downto 5); + r11cEnq := wrChkDout(4) and wrChkDout(2); + r11cFire := errFlushMode and (not wrOutValid) and wrChkValid and + (not r11cEnq or pwrOutNotFull); + r11cDoEnq := r11cFire and r11cEnq; + + -- R11b : wrPsnQ (stage-4 input) + r11bPwr := wrPsnDout(683 downto 5); + r11bEnq := wrPsnDout(4) and wrPsnDout(2); + r11bFire := errFlushMode and (not wrOutValid) and (not wrChkValid) and + wrPsnValid and (not r11bEnq or pwrOutNotFull); + r11bDoEnq := r11bFire and r11bEnq; + + -- R11a : wrPktNumQ (stage-3 input) + r11aPwr := wrPktNumDout(708 downto 30); + r11aEnq := wrPktNumDout(4) and wrPktNumDout(2); + r11aFire := errFlushMode and (not wrOutValid) and (not wrChkValid) and + (not wrPsnValid) and wrPktNumValid and + (not r11aEnq or pwrOutNotFull); + r11aDoEnq := r11aFire and r11aEnq; + + -- R11 : wrPg (stage-2 input; youngest) r11Pwr := wrPgDout(719 downto 41); r11Enq := wrPgDout(2) and wrPgDout(1); -- isNewWorkReq && isReliableConnection - r11Guard := notReset and (isERR or (isRTS and not r.isNormalStateReg)) and wrPgValid; + r11Guard := errFlushMode and (not wrOutValid) and (not wrChkValid) and + (not wrPsnValid) and (not wrPktNumValid) and wrPgValid; r11Fire := r11Guard and (not r11Enq or pwrOutNotFull); r11DoEnq := r11Fire and r11Enq; - -- workReqPayloadGenQ dequeued by R2 (normal) or R11 (err-flush) — mutually - -- exclusive on the mode bit / QP status (FSM spec Conflicts/scheduling). - wrPgRdEn <= r2Fire or r11Fire; - - -- pendingWorkReqOutQ enqueued by R6 (normal) or R11 (err-flush) — mutually - -- exclusive on the mode bit. + -- Stage FIFOs dequeued by their normal stage rule (R2-R6) or the + -- err-flush rules (R11/R11a-d) — mutually exclusive on the QP status. + wrPgRdEn <= r2Fire or r11Fire; + wrPktNumRdEn <= r3Fire or r11aFire; + wrPsnRdEn <= r4Fire or r11bFire; + wrChkRdEn <= r5Fire or r11cFire; + wrOutRdEn <= r6Fire or r11dFire; + + -- pendingWorkReqOutQ enqueued by R6 (normal) or R11/R11a-d (err-flush) — + -- mutually exclusive on the mode bit; the R11* branches are one-hot by + -- the oldest-first priority chain above. if (r6DoEnq = '1') then pwrOutWrEn <= '1'; pwrOutDin <= r6Pwr; + elsif (r11dDoEnq = '1') then + pwrOutWrEn <= '1'; + pwrOutDin <= r11dPwr; + elsif (r11cDoEnq = '1') then + pwrOutWrEn <= '1'; + pwrOutDin <= r11cPwr; + elsif (r11bDoEnq = '1') then + pwrOutWrEn <= '1'; + pwrOutDin <= r11bPwr; + elsif (r11aDoEnq = '1') then + pwrOutWrEn <= '1'; + pwrOutDin <= r11aPwr; elsif (r11DoEnq = '1') then pwrOutWrEn <= '1'; pwrOutDin <= r11Pwr; diff --git a/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd b/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd index 5df22e1e67..4e9912dbbd 100644 --- a/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd +++ b/ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd @@ -53,7 +53,7 @@ use surf.AxiStreamPkg.all; use surf.AxiLitePkg.all; use surf.EthMacPkg.all; -use work.RocePkg.all; +use surf.RocePkg.all; entity RoceEngineWrapper is generic (