From 115aa0fb28b82fccbc2f9a2c85d9e9fcc722ee4c Mon Sep 17 00:00:00 2001
From: Tim Fischer <fischeti@iis.ee.ethz.ch>
Date: Mon, 17 Aug 2026 11:01:34 +0200
Subject: [PATCH] fix(templates): remove defines from VDHL file lists

---
 CHANGELOG.md                      | 1 +
 src/script_fmt/formality_tcl.tera | 4 ++--
 src/script_fmt/genus_tcl.tera     | 4 ++--
 src/script_fmt/synopsys_tcl.tera  | 4 +++-
 4 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5c48b42e..58f32ebe 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -12,6 +12,7 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) a
 - `bender clone`: primary flag for the checkout directory is now `--working-dir`, matching `bender snapshot`'s flag for the same concept; `-p`/`--path` are kept as hidden aliases for backwards compatibility.
 
 ### Fixed
+- script: stop emitting `-define` flags on VHDL compile commands in the `synopsys`, `formality` and `genus` templates (`--compilation-mode separate` only). VHDL has no preprocessor, and some tools error out on the extra option (https://github.com/pulp-platform/bender/issues/350).
 - script: apply `override_files` before validation and the slang pass, so overriding files replace their targets in file-existence checks and in `--top`/`--trim-incdirs` reduction (previously slang saw both the original and the override as duplicate modules); the overridden-file annotation is preserved.
 
 ## 0.32.1 - 2026-07-07
diff --git a/src/script_fmt/formality_tcl.tera b/src/script_fmt/formality_tcl.tera
index 08b6b8a9..bdda0c38 100644
--- a/src/script_fmt/formality_tcl.tera
+++ b/src/script_fmt/formality_tcl.tera
@@ -8,11 +8,11 @@ set search_path $search_path_initial
 {% for incdir in group.incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
 {% endfor %}
 {% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}read_sverilog{% elif group.file_type == 'vhdl' %}read_vhdl{% endif %} -r \
-    {% for define in group.defines %}{% if loop.first %}-define { \
+    {# VHDL has no preprocessor: never pass defines to read_vhdl #}{% if group.file_type == 'verilog' %}{% for define in group.defines %}{% if loop.first %}-define { \
         {% endif %}{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
     } \
     {% else %} \
-        {% endif %}{% endfor %}[list \
+        {% endif %}{% endfor %}{% endif %}[list \
     {% for file in group.files %}{% if source_annotations %}{% if file.comment %}{{ '    ' }}# {{ file.comment }}
     {% endif %}{% endif %}{{ '    ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
     {% endfor %}]
diff --git a/src/script_fmt/genus_tcl.tera b/src/script_fmt/genus_tcl.tera
index e25a455b..063215ad 100644
--- a/src/script_fmt/genus_tcl.tera
+++ b/src/script_fmt/genus_tcl.tera
@@ -14,11 +14,11 @@ set search_path $search_path_initial
 
 {% if group.file_type == 'verilog' %}read_hdl -language sv \
     {% elif group.file_type == 'vhdl' %}read_hdl -language vhdl \
-    {% endif %}{% for define in group.defines %}{% if loop.first %}-define { \
+    {% endif %}{# VHDL has no preprocessor: never pass defines to a VHDL read_hdl #}{% if group.file_type == 'verilog' %}{% for define in group.defines %}{% if loop.first %}-define { \
         {% endif %}{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
     } \
     {% else %} \
-        {% endif %}{% endfor %}[list \
+        {% endif %}{% endfor %}{% endif %}[list \
     {% for file in group.files %}{% if source_annotations %}{% if file.comment %}{{ '    ' }}# {{ file.comment }}
     {% endif %}{% endif %}{{ '    ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
     {% endfor %}]
diff --git a/src/script_fmt/synopsys_tcl.tera b/src/script_fmt/synopsys_tcl.tera
index a5847a7b..9992b064 100644
--- a/src/script_fmt/synopsys_tcl.tera
+++ b/src/script_fmt/synopsys_tcl.tera
@@ -18,12 +18,14 @@ analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type =
 {%- for tmp_arg in vhdl_args %}{{ tmp_arg }} \
 {% endfor -%}
 {%- endif -%}
+{# VHDL has no preprocessor: never pass defines to a VHDL analyze -#}
+{%- if group.file_type == 'verilog' -%}
 {%- for define in group.defines -%}
 {%- if loop.first %}-define { \
         {% endif %}{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
     } \
     {% else %} \
-        {% endif %}{% endfor %}[list \
+        {% endif %}{% endfor %}{% else %}    {% endif %}[list \
     {% for file in group.files -%}
 {%- if source_annotations %}{% if file.comment %}{{ '    ' }}# {{ file.comment }}
 {% endif %}{% endif %}{{ '    ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \