diff --git a/.github/ISSUE_TEMPLATE/1-bug.yaml b/.github/ISSUE_TEMPLATE/1-bug.yaml new file mode 100644 index 00000000000..f258ad58efe --- /dev/null +++ b/.github/ISSUE_TEMPLATE/1-bug.yaml @@ -0,0 +1,37 @@ +name: Bug +description: Report a CVA6 RTL bug +title: "[BUG] " +labels: ["Type:Bug"] +body: +- type: checkboxes + attributes: + label: Code of Conduct + options: + - label: I have searched the existing bug issues. + required: true + - label: >- + I am a human engaging in an interpersonal interaction. + During this interaction, my words are my own and are not generated. + If relevant, I provide links to my sources. + required: true +- type: input + attributes: + label: CVA6 commit affected + description: The git hash of a commit in the official CVA6 repository that was used to demonstrate the bug. + placeholder: "0123abc" + validations: + required: true +- type: textarea + attributes: + label: Bug Description + value: | + <!-- Introduction --> + + # Steps to reproduce + + ## Expected behavior + + ## Observed behavior + + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/task.yaml b/.github/ISSUE_TEMPLATE/2-task.yaml similarity index 84% rename from .github/ISSUE_TEMPLATE/task.yaml rename to .github/ISSUE_TEMPLATE/2-task.yaml index b679f04288e..07c18d215dc 100644 --- a/.github/ISSUE_TEMPLATE/task.yaml +++ b/.github/ISSUE_TEMPLATE/2-task.yaml @@ -1,14 +1,18 @@ -name: CVA6 Task -description: Create a CVA6 Project Task +name: Task +description: A CVA6 Project Task title: "[TASK] <title>" labels: ["task"] body: - type: checkboxes attributes: - label: Is there an existing CVA6 task for this? - description: Please search to see if a task issue already exists for the task you need to create + label: Code of Conduct options: - - label: I have searched the existing task issues + - label: I have searched the existing task issues. + required: true + - label: >- + I am a human engaging in an interpersonal interaction. + During this interaction, my words are my own and are not generated. + If relevant, I provide links to my sources. required: true - type: textarea attributes: diff --git a/.github/ISSUE_TEMPLATE/3-other.yaml b/.github/ISSUE_TEMPLATE/3-other.yaml new file mode 100644 index 00000000000..8e5cb6410db --- /dev/null +++ b/.github/ISSUE_TEMPLATE/3-other.yaml @@ -0,0 +1,19 @@ +name: Other +description: Other issues +title: "<title>" +labels: [] +body: +- type: checkboxes + attributes: + label: Code of Conduct + options: + - label: >- + I am a human engaging in an interpersonal interaction. + During this interaction, my words are my own and are not generated. + If relevant, I provide links to my sources. + required: true +- type: textarea + attributes: + label: Description + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/bug.yaml b/.github/ISSUE_TEMPLATE/bug.yaml deleted file mode 100644 index 6fb9c0b8655..00000000000 --- a/.github/ISSUE_TEMPLATE/bug.yaml +++ /dev/null @@ -1,18 +0,0 @@ -name: CVA6 bug -description: Create a CVA6 bug -title: "[BUG] <title>" -labels: ["Type:Bug"] -body: -- type: checkboxes - attributes: - label: Is there an existing CVA6 bug for this? - description: Please search to see if an issue already exist for the bug you need to create - options: - - label: I have searched the existing bug issues - required: true -- type: textarea - attributes: - label: Bug Description - description: A concise description of the bug - validations: - required: true diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 00000000000..3ba13e0cec6 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -0,0 +1 @@ +blank_issues_enabled: false diff --git a/.github/actions/setup-cva6-env/action.yml b/.github/actions/setup-cva6-env/action.yml new file mode 100644 index 00000000000..da4a15d3539 --- /dev/null +++ b/.github/actions/setup-cva6-env/action.yml @@ -0,0 +1,88 @@ +# Copyright 2026 OpenHW Group +# SPDX-License-Identifier: Apache-2.0 +# +# Composite Action: Setup CVA6 Simulation Environment +# Handles caching, optional tool installation, and environment setup for CVA6 CI jobs + +name: 'Setup CVA6 Environment' +description: 'Cache/restore tools and prepare the CVA6 simulation environment' + +inputs: + install-tools: + description: 'Run ci/setup.sh to install tools if cache miss' + required: false + default: 'true' + +outputs: + toolchain-cache-hit: + description: 'Whether RISC-V toolchain cache was hit' + value: ${{ steps.cache-toolchain.outputs.cache-hit }} + verilator-cache-hit: + description: 'Whether Verilator cache was hit' + value: ${{ steps.cache-verilator.outputs.cache-hit }} + spike-cache-hit: + description: 'Whether Spike cache was hit' + value: ${{ steps.cache-spike.outputs.cache-hit }} + +runs: + using: 'composite' + steps: + # Step 1: Get submodule hash for Spike cache key + - name: Get core-v-verif submodule hash + id: submodule-hash + shell: bash + run: | + cd verif/core-v-verif + echo "hash=$(git rev-parse HEAD)" >> $GITHUB_OUTPUT + + # Step 2: Cache RISC-V Toolchain + - name: Cache RISC-V Toolchain + id: cache-toolchain + uses: actions/cache@v6 + with: + path: tools/riscv-toolchain/ + key: ${{ runner.os }}-toolchain-${{ hashFiles('ci/install-toolchain.sh') }} + # restore-keys: | + # ${{ runner.os }}-toolchain- + + # Step 3: Cache Verilator + - name: Cache Verilator + id: cache-verilator + uses: actions/cache@v6 + with: + path: tools/verilator/ + key: ${{ runner.os }}-verilator-${{ hashFiles('verif/regress/install-verilator.sh') }} + # restore-keys: | + # ${{ runner.os }}-verilator- + + # Step 4: Cache Spike + - name: Cache Spike + id: cache-spike + uses: actions/cache@v6 + with: + path: tools/spike/ + key: ${{ runner.os }}-spike-${{ hashFiles('verif/regress/install-spike.sh') }}-${{ steps.submodule-hash.outputs.hash }} + # restore-keys: | + # ${{ runner.os }}-spike-${{ hashFiles('verif/regress/install-spike.sh') }}- + # ${{ runner.os }}-spike- + + # Step 5: Install tools if cache miss and requested + - name: Setup tools (if cache miss) + if: | + inputs.install-tools == 'true' && ( + steps.cache-toolchain.outputs.cache-hit != 'true' || + steps.cache-verilator.outputs.cache-hit != 'true' || + steps.cache-spike.outputs.cache-hit != 'true' + ) + shell: bash + run: | + set -x + ci/setup.sh + + # Step 6: Setup environment variables + - name: Setup environment variables + shell: bash + run: | + echo "RISCV=$(pwd)/tools/riscv-toolchain" >> $GITHUB_ENV + echo "$(pwd)/tools/verilator/bin" >> $GITHUB_PATH + echo "$(pwd)/tools/spike/bin" >> $GITHUB_PATH diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md new file mode 100644 index 00000000000..9d002ca173a --- /dev/null +++ b/.github/pull_request_template.md @@ -0,0 +1,16 @@ +<!-- Contents within these symbols are commented out and will not appear in the PR description --> + +<!-- Thanks for your contribution! Before sending us a pull request, please make sure you have read CONTRIBUTING.md --> + +- [ ] I have searched for similar pull requests +- [ ] I am a human engaging in an interpersonal interaction. During this interaction, my words are my own and are not generated. If relevant, I provide links to my sources. + + +<!-- Please indicate why this PR is needed for the project --> + +<!-- Is this PR related to existing issues? If so, link to them below --> + +<!-- Are there limitations with the current state of this contribution? --> + +<!-- If the contribution is not ready to be merged yet, please make this PR a draft: https://docs.github.com/fr/pull-requests/collaborating-with-pull-requests/proposing-changes-to-your-work-with-pull-requests/about-pull-requests#draft-pull-requests --> + diff --git a/.github/scripts/dashboard_tiers/collect_data.py b/.github/scripts/dashboard_tiers/collect_data.py new file mode 100644 index 00000000000..e629ff08850 --- /dev/null +++ b/.github/scripts/dashboard_tiers/collect_data.py @@ -0,0 +1,253 @@ +#!/usr/bin/env python3 +# Copyright 2026 OpenHW Group +# SPDX-License-Identifier: Apache-2.0 +"""Collect CI run/job data from GitHub API for the CVA6 tier dashboard. + +Uses `gh api` (pre-installed on GHA runners, auto-authenticated). +Produces per-workflow JSON files with incremental updates. +""" + +import argparse +import json +import os +import subprocess +import sys +from datetime import datetime, timezone +from pathlib import Path + +from parser import parse_job_name + +# Workflows to track +WORKFLOWS = { + "ci": "ci.yml", + "tier1": "openhw-cva6-ci-tier1.yml", + "tier2": "openhw-cva6-ci-tier2.yml", +} + +MAX_HISTORY = 50 + + +def gh_api(endpoint: str, repo: str) -> dict: + """Call GitHub API via `gh api` and return parsed JSON.""" + url = f"/repos/{repo}/actions/{endpoint}" + result = subprocess.run( + ["gh", "api", url, "--paginate"], + capture_output=True, + text=True, + ) + if result.returncode != 0: + print(f"ERROR: gh api {url} failed: {result.stderr}", file=sys.stderr) + sys.exit(1) + return json.loads(result.stdout) + + +def gh_api_list(endpoint: str, repo: str, per_page: int = 100) -> dict: + """Call GitHub API with per_page parameter.""" + url = f"/repos/{repo}/actions/{endpoint}" + sep = "&" if "?" in url else "?" + result = subprocess.run( + ["gh", "api", f"{url}{sep}per_page={per_page}"], + capture_output=True, + text=True, + ) + if result.returncode != 0: + print(f"ERROR: gh api {url} failed: {result.stderr}", file=sys.stderr) + sys.exit(1) + return json.loads(result.stdout) + + +def fetch_runs(repo: str, workflow_file: str, count: int) -> list: + """Fetch the latest `count` completed workflow runs.""" + data = gh_api_list( + f"workflows/{workflow_file}/runs?status=completed&per_page={count}", + repo, + ) + runs = data.get("workflow_runs", []) + return runs[:count] + + +def fetch_jobs(repo: str, run_id: int) -> list: + """Fetch all jobs for a given workflow run.""" + data = gh_api(f"runs/{run_id}/jobs", repo) + return data.get("jobs", []) + + +def duration_seconds(started_at: str, completed_at: str) -> int: + """Calculate duration in seconds between two ISO timestamps.""" + if not started_at or not completed_at: + return 0 + try: + start = datetime.fromisoformat(started_at.replace("Z", "+00:00")) + end = datetime.fromisoformat(completed_at.replace("Z", "+00:00")) + return max(0, int((end - start).total_seconds())) + except (ValueError, TypeError): + return 0 + + +def process_run(repo: str, run: dict, workflow_name: str) -> dict: + """Process a single workflow run into our data format.""" + run_id = run["id"] + jobs_raw = fetch_jobs(repo, run_id) + + jobs = [] + total_jobs = 0 + passed_jobs = 0 + failed_jobs = 0 + + for job in jobs_raw: + parsed = parse_job_name(job["name"], workflow_name) + if parsed is None: + continue # Skip utility jobs + + total_jobs += 1 + conclusion = job.get("conclusion", "unknown") + if conclusion == "success": + passed_jobs += 1 + elif conclusion in ("failure", "timed_out"): + failed_jobs += 1 + + job_data = { + "name": job["name"], + "conclusion": conclusion, + "started_at": job.get("started_at", ""), + "completed_at": job.get("completed_at", ""), + "duration_seconds": duration_seconds( + job.get("started_at", ""), job.get("completed_at", "") + ), + "html_url": job.get("html_url", ""), + } + job_data.update(parsed) + jobs.append(job_data) + + # Calculate run-level duration + run_duration = duration_seconds( + run.get("run_started_at", run.get("created_at", "")), + run.get("updated_at", ""), + ) + + return { + "id": run_id, + "source": "github-actions", # Extensibility: "questa-aws", "gitlab-ci", etc. + "simulator": "verilator", # Extensibility: "questa", "vcs", etc. + "run_number": run.get("run_number", 0), + "status": run.get("status", ""), + "conclusion": run.get("conclusion", "unknown"), + "html_url": run.get("html_url", ""), + "head_branch": run.get("head_branch", ""), + "head_sha": run.get("head_sha", "")[:8], + "event": run.get("event", ""), + "created_at": run.get("created_at", ""), + "updated_at": run.get("updated_at", ""), + "run_started_at": run.get("run_started_at", run.get("created_at", "")), + "duration_seconds": run_duration, + "total_jobs": total_jobs, + "passed_jobs": passed_jobs, + "failed_jobs": failed_jobs, + "skipped_jobs": total_jobs - passed_jobs - failed_jobs, + "jobs": jobs, + } + + +def load_existing(path: Path) -> list: + """Load existing run data from JSON file.""" + if path.exists(): + try: + with open(path) as f: + return json.load(f) + except (json.JSONDecodeError, IOError): + print(f"WARNING: Could not read {path}, starting fresh", file=sys.stderr) + return [] + + +def merge_runs(existing: list, new_runs: list) -> list: + """Merge new runs into existing data, deduplicating by run_id.""" + existing_ids = {r["id"] for r in existing} + merged = list(existing) + + for run in new_runs: + if run["id"] not in existing_ids: + merged.append(run) + existing_ids.add(run["id"]) + + # Sort by created_at descending (newest first) + merged.sort(key=lambda r: r.get("created_at", ""), reverse=True) + + # Trim to MAX_HISTORY + return merged[:MAX_HISTORY] + + +def main(): + parser = argparse.ArgumentParser(description="Collect CVA6 tier CI data from GitHub API") + parser.add_argument( + "--repo", + default=os.environ.get("GITHUB_REPOSITORY", "openhwgroup/cva6"), + help="GitHub repository (owner/name)", + ) + parser.add_argument( + "--data-dir", + default="data", + help="Directory to store JSON data files", + ) + parser.add_argument( + "--fetch-count", + type=int, + default=10, + help="Number of recent runs to fetch per workflow", + ) + args = parser.parse_args() + + data_dir = Path(args.data_dir) + data_dir.mkdir(parents=True, exist_ok=True) + + for wf_name, wf_file in WORKFLOWS.items(): + print(f"\n{'='*60}") + print(f"Processing workflow: {wf_name} ({wf_file})") + print(f"{'='*60}") + + json_path = data_dir / f"runs_{wf_name}.json" + existing = load_existing(json_path) + existing_ids = {r["id"] for r in existing} + + print(f" Existing records: {len(existing)}") + + # Fetch latest runs + runs = fetch_runs(args.repo, wf_file, args.fetch_count) + print(f" Fetched {len(runs)} runs from API") + + # Only process new runs (incremental update) + new_runs = [] + for run in runs: + if run["id"] in existing_ids: + print(f" Skipping run #{run['run_number']} (id={run['id']}) - already exists") + continue + + print(f" Processing run #{run['run_number']} (id={run['id']})...") + processed = process_run(args.repo, run, wf_name) + new_runs.append(processed) + print( + f" -> {processed['total_jobs']} jobs: " + f"{processed['passed_jobs']} passed, " + f"{processed['failed_jobs']} failed" + ) + + # Merge and save + merged = merge_runs(existing, new_runs) + with open(json_path, "w") as f: + json.dump(merged, f, indent=2) + + print(f" Saved {len(merged)} records to {json_path}") + + # Write metadata + meta = { + "generated_at": datetime.now(timezone.utc).isoformat(), + "repo": args.repo, + "workflows": list(WORKFLOWS.keys()), + } + with open(data_dir / "metadata.json", "w") as f: + json.dump(meta, f, indent=2) + + print(f"\nDone! Data saved to {data_dir}/") + + +if __name__ == "__main__": + main() diff --git a/.github/scripts/dashboard_tiers/generate_dashboard.py b/.github/scripts/dashboard_tiers/generate_dashboard.py new file mode 100644 index 00000000000..abd77ca8638 --- /dev/null +++ b/.github/scripts/dashboard_tiers/generate_dashboard.py @@ -0,0 +1,330 @@ +#!/usr/bin/env python3 +# Copyright 2026 OpenHW Group +# SPDX-License-Identifier: Apache-2.0 +"""Generate CVA6 tier dashboard HTML from collected JSON data. + +Reads per-workflow JSON files and renders a Jinja2 template into +a self-contained static HTML file. +""" + +import argparse +import json +import os +import shutil +from datetime import datetime, timezone +from pathlib import Path + +from jinja2 import Environment, FileSystemLoader + +# Workflow display info (order matters for UI) +WORKFLOW_INFO = [ + {"key": "ci", "display_name": "ci.yml (Reference)", "file": "runs_ci.json"}, + {"key": "tier1", "display_name": "Tier 1", "file": "runs_tier1.json"}, + {"key": "tier2", "display_name": "Tier 2", "file": "runs_tier2.json"}, +] + +# Preferred display order for configs and test suites in the matrix. +# Any configs/suites not listed here but found in the data will be +# appended at the end automatically. +MATRIX_CONFIGS_ORDER = [ + "cv32a65x", + "cv32a60x", + "cv64a6_imafdc_sv39_hpdcache_wb", + "cv64a6_imafdc_sv39_hpdcache", + "cv64a6_imafdc_sv39_wb", + "cv64a6_imafdc_sv39", +] + +MATRIX_SUITES_ORDER = [ + "smoke-tests-cv32a65x", + "cv32a6_tests", + "cv64a6_imafdc_tests", + "dv-riscv-arch-test", + "dv-riscv-tests-p", + "dv-riscv-tests-v", + "dv-riscv-compliance", + "dv-riscv-csr-access-test", + "benchmark", +] + +TREND_COUNT = 20 + + +def is_valid_matrix_job(job: dict) -> bool: + """Return True if a job has usable config/testcase for matrix rendering.""" + config = job.get("config", "") + testcase = job.get("testcase", "") + if not config or not testcase: + return False + if "${{" in config or "${{" in testcase: + return False + return True + + +def format_duration(seconds: int) -> str: + """Format seconds into human-readable duration.""" + if seconds <= 0: + return "N/A" + minutes = seconds // 60 + secs = seconds % 60 + if minutes >= 60: + hours = minutes // 60 + mins = minutes % 60 + return f"{hours}h {mins}m" + return f"{minutes}m {secs}s" + + +def format_datetime(iso_str: str) -> str: + """Format ISO datetime to readable string.""" + if not iso_str: + return "N/A" + try: + dt = datetime.fromisoformat(iso_str.replace("Z", "+00:00")) + return dt.strftime("%Y-%m-%d %H:%M UTC") + except (ValueError, TypeError): + return iso_str + + +def load_workflow_data(data_dir: Path) -> dict: + """Load all workflow JSON data files.""" + result = {} + for wf in WORKFLOW_INFO: + path = data_dir / wf["file"] + if path.exists(): + with open(path) as f: + result[wf["key"]] = json.load(f) + else: + result[wf["key"]] = [] + return result + + +def build_matrix(all_data: dict) -> tuple: + """Build unified config x testsuite matrix from ALL workflows. + + Each cell is a dict keyed by workflow name, e.g.: + matrix["cv64a6_imafdc_sv39_hpdcache_wb"]["dv-riscv-arch-test"] = { + "ci": {"conclusion": "success", "html_url": "..."}, + "tier2": {"conclusion": "success", "html_url": "..."}, + } + + Returns: (matrix_data, configs_used, suites_used) + """ + # matrix[config][testcase][workflow_key] = {conclusion, html_url} + matrix = {} + all_configs = set() + all_suites = set() + + for wf in WORKFLOW_INFO: + key = wf["key"] + runs = all_data.get(key, []) + if not runs: + continue + + # Use the latest run that actually has usable matrix jobs. + # This avoids rendering placeholder jobs from early setup failures. + latest = next( + (run for run in runs if any(is_valid_matrix_job(job) for job in run.get("jobs", []))), + None, + ) + if latest is None: + continue + + for job in latest.get("jobs", []): + if not is_valid_matrix_job(job): + continue + config = job.get("config", "") + testcase = job.get("testcase", "") + + all_configs.add(config) + all_suites.add(testcase) + + if config not in matrix: + matrix[config] = {} + if testcase not in matrix[config]: + matrix[config][testcase] = {} + + matrix[config][testcase][key] = { + "conclusion": job.get("conclusion", "unknown"), + "html_url": job.get("html_url", ""), + } + + # Order: preferred order first, then any extras alphabetically + def ordered(items, preferred): + result = [c for c in preferred if c in items] + extras = sorted(items - set(preferred)) + return result + extras + + configs_used = ordered(all_configs, MATRIX_CONFIGS_ORDER) + suites_used = ordered(all_suites, MATRIX_SUITES_ORDER) + + return matrix, configs_used, suites_used + + +def build_chart_data(all_data: dict) -> dict: + """Build Chart.js data for trend charts.""" + chart_data = {} + + for wf in WORKFLOW_INFO: + key = wf["key"] + runs = all_data.get(key, []) + + # Take last TREND_COUNT runs, reversed for chronological order + trend_runs = list(reversed(runs[:TREND_COUNT])) + + labels = [] + pass_rates = [] + durations = [] + + for run in trend_runs: + labels.append(str(run.get("run_number", ""))) + total = run.get("total_jobs", 0) + passed = run.get("passed_jobs", 0) + rate = round(passed / total * 100, 1) if total > 0 else 0 + pass_rates.append(rate) + dur_min = round(run.get("duration_seconds", 0) / 60, 1) + durations.append(dur_min) + + chart_data[key] = { + "labels": labels, + "pass_rates": pass_rates, + "durations": durations, + } + + return chart_data + + +def enrich_run(run: dict) -> dict: + """Add display-friendly fields to a run dict.""" + run["duration_display"] = format_duration(run.get("duration_seconds", 0)) + run["created_at_display"] = format_datetime(run.get("created_at", "")) + for job in run.get("jobs", []): + job["duration_display"] = format_duration(job.get("duration_seconds", 0)) + return run + + +def build_workflows_context(all_data: dict) -> list: + """Build the workflows list for the template context.""" + workflows = [] + + for wf in WORKFLOW_INFO: + key = wf["key"] + runs = all_data.get(key, []) + + # Enrich all runs + for run in runs: + enrich_run(run) + + # Build latest run summary (or placeholder) + if runs: + latest = runs[0] + else: + latest = { + "conclusion": "unknown", + "head_branch": "N/A", + "head_sha": "N/A", + "passed_jobs": 0, + "failed_jobs": 0, + "skipped_jobs": 0, + "total_jobs": 0, + "duration_display": "N/A", + "run_number": 0, + "html_url": "#", + } + + workflows.append( + { + "key": key, + "display_name": wf["display_name"], + "latest": latest, + "runs": runs, + } + ) + + return workflows + + +def main(): + parser = argparse.ArgumentParser( + description="Generate CVA6 CI Dashboard HTML" + ) + parser.add_argument( + "--data-dir", + default="data", + help="Directory containing JSON data files", + ) + parser.add_argument( + "--output-dir", + default="site", + help="Output directory for generated HTML", + ) + parser.add_argument( + "--repo", + default=os.environ.get("GITHUB_REPOSITORY", "openhwgroup/cva6"), + help="GitHub repository (owner/name)", + ) + args = parser.parse_args() + + data_dir = Path(args.data_dir) + output_dir = Path(args.output_dir) + output_dir.mkdir(parents=True, exist_ok=True) + + # Load data + all_data = load_workflow_data(data_dir) + + # Build template context + now = datetime.now(timezone.utc) + workflows = build_workflows_context(all_data) + matrix_data, matrix_configs, matrix_suites = build_matrix(all_data) + chart_data = build_chart_data(all_data) + + default_matrix_wf = "tier2" + if not all_data.get("tier2"): + for wf in WORKFLOW_INFO: + if all_data.get(wf["key"]): + default_matrix_wf = wf["key"] + break + + context = { + "generated_at": now.strftime("%Y-%m-%d %H:%M UTC"), + "year": now.year, + "repo": args.repo, + "workflows": workflows, + "matrix_data": matrix_data, + "matrix_data_json": json.dumps(matrix_data), + "matrix_configs": matrix_configs, + "matrix_configs_json": json.dumps(matrix_configs), + "matrix_suites": matrix_suites, + "matrix_suites_json": json.dumps(matrix_suites), + "default_matrix_wf": default_matrix_wf, + "chart_data_json": json.dumps(chart_data), + "trend_count": TREND_COUNT, + } + + # Render template + template_dir = Path(__file__).parent / "templates" + env = Environment(loader=FileSystemLoader(str(template_dir)), autoescape=True) + template = env.get_template("index.html") + html = template.render(**context) + + # Write output + output_file = output_dir / "index.html" + with open(output_file, "w") as f: + f.write(html) + + # Copy static dashboard assets, such as the local OpenHW logo. + static_dir = Path(__file__).parent / "static" + if static_dir.exists(): + assets_dir = output_dir / "assets" + if assets_dir.exists(): + shutil.rmtree(assets_dir) + shutil.copytree(static_dir, assets_dir) + + print(f"Dashboard generated: {output_file}") + print(f" Workflows: {len(workflows)}") + for wf in workflows: + print(f" - {wf['display_name']}: {len(wf['runs'])} runs") + print(f" Matrix: {len(matrix_configs)} configs x {len(matrix_suites)} suites") + + +if __name__ == "__main__": + main() diff --git a/.github/scripts/dashboard_tiers/parser.py b/.github/scripts/dashboard_tiers/parser.py new file mode 100644 index 00000000000..bd702f72ee2 --- /dev/null +++ b/.github/scripts/dashboard_tiers/parser.py @@ -0,0 +1,146 @@ +#!/usr/bin/env python3 +# Copyright 2026 OpenHW Group +# SPDX-License-Identifier: Apache-2.0 +"""Parse CI job names into structured data for the CVA6 tier dashboard.""" + +import re +from typing import Optional + +# Utility/infrastructure jobs to skip (not actual test executions) +SKIP_JOBS = { + "Setup Tools", + "Test Summary", + "Resolve Tier", + "Prepare Matrix", + "build-riscv-tests", + "report-summary", + "setup-tools", + "resolve-tier", + "prepare-matrix", +} + +# All known CVA6 configs (longest first for greedy match) +KNOWN_CONFIGS = [ + "cv64a6_imafdc_sv39_hpdcache_wb", + "cv32a60x", + "cv32a65x", +] + + +def parse_job_name(job_name: str, workflow_name: str) -> Optional[dict]: + """Parse a CI job name into structured fields. + + Returns: + dict with keys: arch, config, testcase, simulator (optional) + None if the job should be skipped (utility/infrastructure job) + """ + name = job_name.strip() + + # Skip utility jobs + if name in SKIP_JOBS: + return None + + # --- tier workflows --- + m = re.match(r"^(RV(?:32|64))\s+Tier[12]\s+(.+?)\s+/\s+(.+)$", name) + if m: + arch = m.group(1).lower() + config = m.group(2).strip() + testcase = m.group(3).strip() + if "${{" in testcase or "${{" in config: + return None + return { + "arch": arch, + "config": config, + "testcase": testcase, + } + + # --- tier workflows and similar matrix-style workflows --- + # Format: "RV64 {testcase} ({config})" or "RV32 {testcase} ({config})" + m = re.match(r"^(RV(?:32|64))\s+(.+?)\s+\(([^)]+)\)$", name) + if m: + arch = m.group(1).lower() + testcase = m.group(2).strip() + config = m.group(3).strip() + # Skip unresolved matrix placeholders from early-failed/skipped runs + # (e.g. "RV64 ${{ matrix.testcase }} (${{ matrix.config }})") + if "${{" in testcase or "${{" in config: + return None + return { + "arch": arch, + "config": config, + "testcase": testcase, + } + + # --- ci.yml --- + # Format: "execute-riscv64-tests (config, simulator, testcase)" + # or "execute-riscv32-tests (testcase, config, simulator)" + m = re.match( + r"^execute-riscv(32|64)-tests\s+\(([^)]+)\)$", name + ) + if m: + arch = f"rv{m.group(1)}" + params = [p.strip() for p in m.group(2).split(",")] + + if arch == "rv64" and len(params) == 3: + # ci.yml rv64 matrix: (testcase, config, simulator) + # Actually from the workflow: matrix keys are testcase, config, simulator + # GitHub renders them in the order they appear in the matrix definition + # For execute-riscv64-tests: testcase, config, simulator + testcase, config, simulator = params + return { + "arch": arch, + "config": config, + "testcase": testcase, + "simulator": simulator, + } + elif arch == "rv32" and len(params) == 3: + # ci.yml rv32 matrix: (testcase, config, simulator) + testcase, config, simulator = params + return { + "arch": arch, + "config": config, + "testcase": testcase, + "simulator": simulator, + } + elif len(params) >= 2: + # Fallback for unexpected param count + return { + "arch": arch, + "config": params[1] if len(params) > 1 else "unknown", + "testcase": params[0], + } + + # Unrecognized job name - skip it + return None + + +def arch_from_config(config: str) -> str: + """Infer architecture from config name.""" + if config.startswith("cv64"): + return "rv64" + elif config.startswith("cv32"): + return "rv32" + return "unknown" + + +if __name__ == "__main__": + # Quick self-test + test_cases = [ + ("RV64 Tier2 cv64a6_imafdc_sv39_hpdcache_wb / dv-riscv-arch-test", "tier2"), + ("RV32 Tier1 cv32a65x / smoke-tests-cv32a65x", "tier1"), + ("RV64 Tier2 cv64a6_imafdc_sv39_hpdcache_wb / benchmark", "tier2"), + ( + "execute-riscv64-tests (cv64a6_imafdc_tests, cv64a6_imafdc_sv39_hpdcache, veri-testharness)", + "ci", + ), + ( + "execute-riscv32-tests (dv-riscv-arch-test, cv32a65x, veri-testharness)", + "ci", + ), + ("Setup Tools", "tier2"), + ("Test Summary", "tier1"), + ] + + for job_name, wf in test_cases: + result = parse_job_name(job_name, wf) + print(f" {job_name!r:80s} -> {result}") diff --git a/.github/scripts/dashboard_tiers/static/openhw-landscape.svg b/.github/scripts/dashboard_tiers/static/openhw-landscape.svg new file mode 100644 index 00000000000..baf06fb702d --- /dev/null +++ b/.github/scripts/dashboard_tiers/static/openhw-landscape.svg @@ -0,0 +1,1145 @@ +<?xml version="1.0" encoding="UTF-8"?> +<svg xmlns="http://www.w3.org/2000/svg" xmlns:i="http://ns.adobe.com/AdobeIllustrator/10.0/" version="1.1" viewBox="0 0 446.6 104"> + <defs> + <style> + .cls-1 { + fill: #18a13b; + } + + .cls-2 { + fill: #747173; + } + + .cls-3 { + fill: none; + stroke: #747173; + stroke-miterlimit: 10; + } + + .cls-4 { + fill: #222e5b; + } + </style> + </defs> + <!-- Generator: Adobe Illustrator 28.7.0, SVG Export Plug-In . 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+14oAuwBvauFGnu/uikdIlChbrAD/8QLJbgFDhhWT0FoG+Mu5QNhXBsSpLtTBo2XhT0Q5/N1d33j8 +pEnTfF8FnH97aBfgcB10iwy67VQDHsNpmN1x3d3QO/kN8yfJrrBL/DLsawSfonjS9s8UGn5GVOYX +HT0BH7oKGBOOT/DcbpG2xa0k8V9zO8+u4R8cWMxJbM3mp8Z41wVDGnaElfRK3FHbagXfFgJvCAi1 +rYfbpSLo6Bpta5q3hXXfVk/4ahuuOMxqdPj9/grO3gBQ0qRtfr0Alnm95FpQ4jPQCnjjC5CHdPcl +ou3nnmxplEHDLyWIBmr7t9zGezjhSgmkfCm5nUMGQ5f5wlu7jyAV8PoJGNxUwBsulbXAP6A21Cih +efjj9+8pLdl4pvl63yTR4r2oGVkD +]]> + </i:aipgf> + </metadata> +</svg> \ No newline at end of file diff --git a/.github/scripts/dashboard_tiers/templates/index.html b/.github/scripts/dashboard_tiers/templates/index.html new file mode 100644 index 00000000000..14a2120621b --- /dev/null +++ b/.github/scripts/dashboard_tiers/templates/index.html @@ -0,0 +1,484 @@ +<!DOCTYPE html> +<html lang="en" data-bs-theme="light"> +<head> + <meta charset="utf-8"> + <meta name="viewport" content="width=device-width, initial-scale=1"> + <title>OpenHW CVA6 Tier CI Dashboard + + + + + + + + + + + +
+ + + + +
+
Latest Run Status
+
+ {% for wf in workflows %} +
+
+
+
+
{{ wf.display_name }}
+ {% if wf.latest.conclusion == 'success' %} + PASS + {% elif wf.latest.conclusion == 'failure' %} + FAIL + {% else %} + {{ wf.latest.conclusion|upper }} + {% endif %} +
+
+
+ Branch: {{ wf.latest.head_branch }} + · {{ wf.latest.head_sha }} +
+
+ Jobs: + {{ wf.latest.passed_jobs }} passed + {% if wf.latest.failed_jobs > 0 %} + / {{ wf.latest.failed_jobs }} failed + {% endif %} + {% if wf.latest.skipped_jobs > 0 %} + / {{ wf.latest.skipped_jobs }} skipped + {% endif %} + ({{ wf.latest.total_jobs }} total) +
+
+ Duration: {{ wf.latest.duration_display }} + · Run: #{{ wf.latest.run_number }} +
+
+
+ + View on GitHub → + +
+
+
+
+ {% endfor %} +
+
+ + + + +
+
+
Test Coverage Matrix
+ +
+ {% for wf in workflows %} + + + {% endfor %} +
+ +
+ + {% if matrix_data %} +
+
+
+ Legend: + ✓ Pass + ✗ Fail + – Not in matrix +
+
+ + + +
+
+
+
+ {% else %} +
No CI run data available yet.
+ {% endif %} +
+ + + + +
+
Trends (Last {{ trend_count }} Runs)
+
+ {% for wf in workflows %} +
+
+
{{ wf.display_name }}
+
+
+ +
+
+
+
+ {% endfor %} +
+
+ + + + +
+
Run History
+
+ {% for wf in workflows %} +
+

+ +

+
+
+ {% if wf.runs %} +
+ {% for run in wf.runs[:20] %} +
+

+ +

+
+
+
+ View on GitHub + · Event: {{ run.event }} + · Jobs: {{ run.passed_jobs }}/{{ run.total_jobs }} passed +
+ {% if run.jobs %} +
+ + + + + + + + + + + + {% for job in run.jobs %} + + + + + + + + {% endfor %} + +
ArchConfigTest SuiteStatusDuration
{{ job.arch|upper }}{{ job.config }}{{ job.testcase }} + {% if job.conclusion == 'success' %} + PASS + {% elif job.conclusion == 'failure' %} + FAIL + {% else %} + {{ job.conclusion|upper }} + {% endif %} + {{ job.duration_display }}
+
+ {% else %} +
No job data available.
+ {% endif %} +
+
+
+ {% endfor %} +
+ {% else %} +
No run history available.
+ {% endif %} +
+
+
+ {% endfor %} +
+
+ +
+ + + + + + + + + + diff --git a/.github/scripts/run-tier-regression.sh b/.github/scripts/run-tier-regression.sh new file mode 100755 index 00000000000..1cf17b4755e --- /dev/null +++ b/.github/scripts/run-tier-regression.sh @@ -0,0 +1,199 @@ +#!/usr/bin/env bash +# Copyright 2026 OpenHW Group +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +set -o pipefail + +RUN_LOG="$(pwd)/ci-results/run.log" +FAILURE_SUMMARY="$(pwd)/ci-results/failure_summary.log" +EXIT_CODE_FILE="$(pwd)/ci-results/exit_code" + +mkdir -p ci-results +: > "${RUN_LOG}" +: > "${FAILURE_SUMMARY}" +echo "1" > "${EXIT_CODE_FILE}" + +TIER_NAME="${TIER_NAME:-Tier}" +TIER_MODE="${TIER_MODE:-script}" +TIER_CONFIG="${TIER_CONFIG:?TIER_CONFIG is required}" +TIER_TESTCASE="${TIER_TESTCASE:?TIER_TESTCASE is required}" +TIER_SIMULATOR="${TIER_SIMULATOR:?TIER_SIMULATOR is required}" +TIER_INSTALL_SCRIPT="${TIER_INSTALL_SCRIPT:-}" +TIER_TESTLIST="${TIER_TESTLIST:-}" +TIER_TEST_NAME="${TIER_TEST_NAME:-}" +TIER_LINKER="${TIER_LINKER:-}" +TIER_HWCONFIG_OPTS="${TIER_HWCONFIG_OPTS:-}" + +log_info() { + echo "$*" | tee -a "${RUN_LOG}" +} + +run_logged() { + set +e + "$@" > >(tee -a "${RUN_LOG}") 2>&1 + local cmd_rc=$? + return "${cmd_rc}" +} + +source_logged() { + local script_path="$1" + set +e + # shellcheck source=/dev/null + source "${script_path}" > >(tee -a "${RUN_LOG}") 2>&1 + local source_rc=$? + return "${source_rc}" +} + +record_rc() { + local step_rc="$1" + if [ "${step_rc}" -ne 0 ] && [ "${rc}" -eq 0 ]; then + rc="${step_rc}" + fi +} + +append_failure() { + echo "$*" | tee -a "${FAILURE_SUMMARY}" >&2 +} + +collect_reports() { + find verif/sim -name "iss_regr.log" -exec cp {} ci-results/ \; 2>/dev/null || true +} + +scan_for_failures() { + local matches + local -a scan_files=("${RUN_LOG}") + + while IFS= read -r -d '' file_path; do + scan_files+=("${file_path}") + done < <( + find verif/sim -type f \ + \( -name "*.log" -o -name "*.txt" -o -name "iss_regr.log" \) \ + -print0 2>/dev/null || true + ) + + matches="$( + grep -HnE \ + "\\[FAILED\\]|SIMULATION FAILED|(^|[^0-9])[1-9][0-9]* FAILED|ERROR return code:|bad syscall|unrecognized opcode|extension .* required|make(\\[[0-9]+\\])?: \\*\\*\\*.*Error|terminate called|Traceback \\(most recent call last\\)" \ + "${scan_files[@]}" 2>/dev/null || true + )" + + if [ -n "${matches}" ]; then + append_failure "ERROR: ${TIER_NAME} job reported success, but failure patterns were found in logs." + echo "${matches}" | tee -a "${FAILURE_SUMMARY}" >&2 + return 1 + fi + + return 0 +} + +scan_iss_traces() { + local matches="" + local critical_patterns + critical_patterns="ERROR return code:|bad syscall|unrecognized opcode|extension .* required|terminate called|Traceback \\(most recent call last\\)" + + while IFS= read -r -d '' file_path; do + local critical_matches + local last_status + + critical_matches="$(grep -HnE "${critical_patterns}" "${file_path}" 2>/dev/null || true)" + if [ -n "${critical_matches}" ]; then + matches+="${critical_matches}"$'\n' + fi + + last_status="$( + grep -nE "\\*\\*\\*[[:space:]]+(FAILED|SUCCESS)[[:space:]]+\\*\\*\\*|SIMULATION FAILED" "${file_path}" 2>/dev/null | tail -n 1 || true + )" + if [[ -n "${last_status}" && "${last_status}" != *"SUCCESS"* ]]; then + matches+="${file_path}:${last_status}"$'\n' + fi + done < <(find verif/sim -type f -name "*.iss" -print0 2>/dev/null || true) + + if [ -n "${matches}" ]; then + append_failure "ERROR: ${TIER_NAME} job reported success, but ISS trace failure patterns were found." + printf "%s" "${matches}" | tee -a "${FAILURE_SUMMARY}" >&2 + return 1 + fi + + return 0 +} + +rc=0 + +log_info "Running ${TIER_NAME}: ${TIER_CONFIG} / ${TIER_TESTCASE} (${TIER_MODE})" + +source_logged verif/sim/setup-env.sh +record_rc "$?" + +if [ "${rc}" -eq 0 ]; then + if [ "${TIER_MODE}" = "testlist" ]; then + if [[ "${TIER_SIMULATOR}" == *"veri-testharness"* ]]; then + source_logged verif/regress/install-verilator.sh + record_rc "$?" + fi + + if [ "${rc}" -eq 0 ]; then + source_logged verif/regress/install-spike.sh + record_rc "$?" + fi + + if [ "${rc}" -eq 0 ] && [ -n "${TIER_INSTALL_SCRIPT}" ]; then + source_logged "verif/regress/${TIER_INSTALL_SCRIPT}.sh" + record_rc "$?" + fi + + if [ "${rc}" -eq 0 ]; then + cva6_cmd=( + python3 cva6.py + "--testlist=${TIER_TESTLIST}" + --target "${TIER_CONFIG}" + --iss_yaml=cva6.yaml + "--iss=${TIER_SIMULATOR}" + "--issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=UVM_NONE" + ) + + if [ -n "${TIER_LINKER}" ]; then + cva6_cmd+=("--linker=${TIER_LINKER}") + fi + + if [ -n "${TIER_TEST_NAME}" ]; then + cva6_cmd+=(--test "${TIER_TEST_NAME}") + fi + + pushd verif/sim > /dev/null || rc=$? + if [ "${rc}" -eq 0 ]; then + run_logged "${cva6_cmd[@]}" + record_rc "$?" + fi + popd > /dev/null || true + fi + else + if [ -n "${TIER_HWCONFIG_OPTS}" ]; then + export DV_HWCONFIG_OPTS="${TIER_HWCONFIG_OPTS}" + fi + + run_logged env \ + DV_SIMULATORS="${TIER_SIMULATOR}" \ + DV_TARGET="${TIER_CONFIG}" \ + bash -e "verif/regress/${TIER_TESTCASE}.sh" + record_rc "$?" + fi +fi + +collect_reports + +if [ "${rc}" -eq 0 ] && ! compgen -G "verif/sim/out*" > /dev/null; then + append_failure "ERROR: ${TIER_NAME} job reported success but produced no verif/sim/out* results." + rc=1 +fi + +if [ "${rc}" -eq 0 ] && ! scan_for_failures; then + rc=1 +fi + +if [ "${rc}" -eq 0 ] && ! scan_iss_traces; then + rc=1 +fi + +echo "${rc}" > "${EXIT_CODE_FILE}" +exit "${rc}" diff --git a/.github/workflows/bender-up-to-date.yml b/.github/workflows/bender-up-to-date.yml index bc3f38c79c6..89b2982de5f 100644 --- a/.github/workflows/bender-up-to-date.yml +++ b/.github/workflows/bender-up-to-date.yml @@ -13,4 +13,4 @@ jobs: runs-on: ubuntu-latest steps: - name: Check Bender up-to-date - uses: pulp-platform/pulp-actions/bender-up-to-date@v2 + uses: pulp-platform/pulp-actions/bender-up-to-date@v2.4.4 diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 5b18be59f85..a95ad038b8a 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -13,7 +13,7 @@ jobs: env: NUM_JOBS: 8 steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v7 with: submodules: recursive @@ -25,7 +25,7 @@ jobs: - name: Cache toolchain id: cache-toolchain - uses: actions/cache@v3 + uses: actions/cache@v6 env: cache-name: cache-toolchain with: @@ -34,7 +34,7 @@ jobs: - name: Cache verilator id: cache-verilator - uses: actions/cache@v3 + uses: actions/cache@v6 env: cache-name: cache-verilator with: @@ -43,7 +43,7 @@ jobs: - name: Cache Spike id: cache-spike - uses: actions/cache@v3 + uses: actions/cache@v6 env: cache-name: cache-spike with: @@ -72,10 +72,13 @@ jobs: - testcase: dv-riscv-arch-test config: cv64a6_imafdc_sv39_hpdcache_wb simulator: veri-testharness + - testcase: pmp_lsu_transaction + config: cv64a6_imafdc_sv39 + simulator: veri-testharness needs: build-riscv-tests steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v7 with: submodules: recursive @@ -87,7 +90,7 @@ jobs: - name: Cache toolchain id: cache-toolchain - uses: actions/cache@v3 + uses: actions/cache@v6 env: cache-name: cache-toolchain with: @@ -96,7 +99,7 @@ jobs: - name: Cache verilator id: cache-verilator - uses: actions/cache@v3 + uses: actions/cache@v6 env: cache-name: cache-verilator with: @@ -105,7 +108,7 @@ jobs: - name: Cache Spike id: cache-spike - uses: actions/cache@v3 + uses: actions/cache@v6 env: cache-name: cache-spike with: @@ -141,7 +144,7 @@ jobs: needs: build-riscv-tests steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v7 with: submodules: recursive @@ -153,7 +156,7 @@ jobs: - name: Cache toolchain id: cache-toolchain - uses: actions/cache@v3 + uses: actions/cache@v6 env: cache-name: cache-toolchain with: @@ -162,7 +165,7 @@ jobs: - name: Cache verilator id: cache-verilator - uses: actions/cache@v3 + uses: actions/cache@v6 env: cache-name: cache-verilator with: @@ -171,7 +174,7 @@ jobs: - name: Cache Spike id: cache-spike - uses: actions/cache@v3 + uses: actions/cache@v6 env: cache-name: cache-spike with: diff --git a/.github/workflows/openhw-cva6-ci-tier1.yml b/.github/workflows/openhw-cva6-ci-tier1.yml new file mode 100644 index 00000000000..c11b2796ee9 --- /dev/null +++ b/.github/workflows/openhw-cva6-ci-tier1.yml @@ -0,0 +1,197 @@ +# Copyright 2026 OpenHW Group +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# ================================================================================ +# OpenHW CVA6 CI - Tier 1: Fast Verilator Sanity +# ================================================================================ +# +# PURPOSE: +# Fast Verilator-based sanity regression for the three phase-1 "green" +# configurations selected for the first GitHub CI rollout. +# Runs one representative smoke or directed test per approved +# configuration to provide automatic sanity checks for pull-requests. +# +# TRIGGER POLICY: +# pull_request -> Automatic sanity checks for PRs targeting master +# workflow_dispatch -> On-demand rerun for manual validation +# +# COVERED CONFIGURATIONS (Phase-1 Green Config subset): +# RV32: +# - cv32a65x (dual-issue, no MMU) +# - cv32a60x (single-issue, no MMU) +# RV64: +# - cv64a6_imafdc_sv39_hpdcache_wb (HPDcache + write-back) +# +# TEST SUITES PER CONFIG: +# - cv32a65x -> smoke-tests-cv32a65x +# - cv32a60x -> cv32a6_tests +# - cv64a6_imafdc_sv39_hpdcache_wb -> cv64a6_imafdc_tests +# +# NOTES: +# - Phase 1 Tier 1 is Verilator-only. +# - Tier 1 is intentionally narrower than Tier 2: the goal is fast signal, +# not broad regression depth. +# ================================================================================ + +name: openhw-cva6-ci-tier1 + +on: + pull_request: + branches: + - master + workflow_dispatch: + +concurrency: + group: openhw-cva6-ci-tier1-${{ github.ref }} + cancel-in-progress: true + +env: + SPIKE_TANDEM: 1 + NUM_JOBS: 8 + FORCE_JAVASCRIPT_ACTIONS_TO_NODE24: "true" + +jobs: + # ============================================================ + # Stage 1: Populate tool cache + # ============================================================ + setup-tools: + name: Setup Tools + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v7 + with: + submodules: recursive + + - name: Setup CVA6 Environment + uses: ./.github/actions/setup-cva6-env + with: + install-tools: "true" + + # ============================================================ + # Stage 2: RV32 Fast Sanity (parallel matrix jobs) + # ============================================================ + execute-rv32-tier1: + name: RV32 Tier1 ${{ matrix.config }} / ${{ matrix.testcase }} + runs-on: ubuntu-latest + needs: setup-tools + strategy: + fail-fast: false + matrix: + include: + # ---------------------------------------------------------- + # cv32a65x - dual-issue RV32, no MMU + # ---------------------------------------------------------- + # Quickest RV32 sanity signal for the higher-feature RV32 core + - config: cv32a65x + testcase: smoke-tests-cv32a65x + mode: script + simulator: veri-testharness,spike + install_script: "" + testlist: "" + test_name: "" + linker: "" + + # ---------------------------------------------------------- + # cv32a60x - single-issue RV32, no MMU + # ---------------------------------------------------------- + # Directed sanity regression; no dedicated workflow-native smoke exists + - config: cv32a60x + testcase: cv32a6_tests + mode: script + simulator: veri-testharness,spike + install_script: "" + testlist: "" + test_name: "" + linker: "" + + steps: + - uses: actions/checkout@v7 + with: + submodules: recursive + + - name: Setup CVA6 Environment + uses: ./.github/actions/setup-cva6-env + + - name: Install prerequisites + run: source ci/install-prereq.sh + + - name: Run Tier 1 for ${{ matrix.config }} / ${{ matrix.testcase }} + env: + TIER_NAME: Tier 1 + TIER_MODE: ${{ matrix.mode }} + TIER_CONFIG: ${{ matrix.config }} + TIER_TESTCASE: ${{ matrix.testcase }} + TIER_SIMULATOR: ${{ matrix.simulator }} + TIER_INSTALL_SCRIPT: ${{ matrix.install_script }} + TIER_TESTLIST: ${{ matrix.testlist }} + TIER_TEST_NAME: ${{ matrix.test_name }} + TIER_LINKER: ${{ matrix.linker }} + run: bash .github/scripts/run-tier-regression.sh + + - name: Upload Results + if: always() + uses: actions/upload-artifact@v4 + with: + name: tier1-rv32-${{ matrix.config }}-${{ matrix.testcase }} + path: | + ci-results/ + verif/sim/out*/ + retention-days: 14 + + # ============================================================ + # Stage 3: RV64 Fast Sanity + # ============================================================ + execute-rv64-tier1: + name: RV64 Tier1 ${{ matrix.config }} / ${{ matrix.testcase }} + runs-on: ubuntu-latest + needs: setup-tools + strategy: + fail-fast: false + matrix: + include: + # ---------------------------------------------------------- + # cv64a6_imafdc_sv39_hpdcache_wb - RV64 HPDcache + write-back + # ---------------------------------------------------------- + # Fast RV64 sanity using the existing directed script + - config: cv64a6_imafdc_sv39_hpdcache_wb + testcase: cv64a6_imafdc_tests + mode: script + simulator: veri-testharness,spike + install_script: "" + testlist: "" + test_name: "" + linker: "" + + steps: + - uses: actions/checkout@v7 + with: + submodules: recursive + + - name: Setup CVA6 Environment + uses: ./.github/actions/setup-cva6-env + + - name: Install prerequisites + run: source ci/install-prereq.sh + + - name: Run Tier 1 for ${{ matrix.config }} / ${{ matrix.testcase }} + env: + TIER_NAME: Tier 1 + TIER_MODE: ${{ matrix.mode }} + TIER_CONFIG: ${{ matrix.config }} + TIER_TESTCASE: ${{ matrix.testcase }} + TIER_SIMULATOR: ${{ matrix.simulator }} + TIER_INSTALL_SCRIPT: ${{ matrix.install_script }} + TIER_TESTLIST: ${{ matrix.testlist }} + TIER_TEST_NAME: ${{ matrix.test_name }} + TIER_LINKER: ${{ matrix.linker }} + run: bash .github/scripts/run-tier-regression.sh + + - name: Upload Results + if: always() + uses: actions/upload-artifact@v4 + with: + name: tier1-rv64-${{ matrix.config }}-${{ matrix.testcase }} + path: | + ci-results/ + verif/sim/out*/ + retention-days: 14 diff --git a/.github/workflows/openhw-cva6-ci-tier2.yml b/.github/workflows/openhw-cva6-ci-tier2.yml new file mode 100644 index 00000000000..72c493a8801 --- /dev/null +++ b/.github/workflows/openhw-cva6-ci-tier2.yml @@ -0,0 +1,370 @@ +# Copyright 2026 OpenHW Group +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# ================================================================================ +# OpenHW CVA6 CI - Tier 2: Daily Verilator Regression +# ================================================================================ +# +# PURPOSE: +# Nightly Verilator regression for the three phase-1 "green" +# configurations selected for the first GitHub CI rollout. +# Runs a curated Tier 2 set of functional and workload-oriented tests, +# expanding coverage beyond Tier 1. +# +# SCHEDULE: Daily at 22:00 UTC +# +# TRIGGER POLICY: +# schedule -> Automatic daily regression (22:00 UTC) +# workflow_dispatch -> On-demand Tier 2 regression for manual validation +# +# COVERED CONFIGURATIONS (Green Config subset from Jerome's color-coded figure): +# RV32: +# - cv32a65x (dual-issue, no MMU) [ 8 testcases] +# - cv32a60x (single-issue, no MMU) [ 4 testcases] +# RV64: +# - cv64a6_imafdc_sv39_hpdcache_wb (HPDcache + write-back) [ 5 testcases] +# +# TEST SUITES PER CONFIG: +# cv32a65x (8 jobs): +# smoke-tests, cv32a6_tests, dv-riscv-arch-test, dv-riscv-tests-p, +# dv-riscv-compliance, dv-csr-embedded-tests, +# hwconfig_tests, coremark +# +# cv32a60x (4 jobs): +# cv32a6_tests, dv-riscv-arch-test, dv-riscv-tests-p, +# dv-riscv-compliance +# (Note: hwconfig/coremark/dv-csr-embedded-tests are cv32a65x-specific) +# +# cv64a6_imafdc_sv39_hpdcache_wb (5 jobs): +# cv64a6_imafdc_tests, dv-riscv-arch-test, +# dv-riscv-tests-v [testlist], dv-riscv-tests-p [testlist], +# dv-riscv-compliance [testlist] +# +# NOTES: +# - "dv-riscv-tests-v" / "dv-riscv-tests-p" are job label names, not script +# names. They run via python3 cva6.py --testlist= (no .sh equivalent). +# Splitting v (virtual mode) / p (physical mode) into separate jobs enables +# per-mode failure isolation. +# - dv-csr-embedded-tests uses veri-testharness only: spike does not emulate +# embedded CSR side effects. +# - hwconfig_tests and coremark require DV_HWCONFIG_OPTS, encoded via the +# matrix hwconfig_opts field and applied in the run step. +# - coremark uses veri-testharness only: spike times out on long benchmark loops. +# - benchmark and dv-riscv-csr-access-test are intentionally excluded from +# Phase 1 Tier 2 until their legacy regression scripts propagate failures +# and produce trustworthy artifacts. +# ================================================================================ + +name: openhw-cva6-ci-tier2 + +on: + schedule: + - cron: "0 22 * * *" # 22:00 UTC + workflow_dispatch: + +concurrency: + group: openhw-cva6-ci-tier2-${{ github.ref }} + cancel-in-progress: true + +env: + SPIKE_TANDEM: 1 + NUM_JOBS: 8 + FORCE_JAVASCRIPT_ACTIONS_TO_NODE24: "true" + +jobs: + # ============================================================ + # Stage 1: Populate tool cache + # ============================================================ + setup-tools: + name: Setup Tools + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v7 + with: + submodules: recursive + + - name: Setup CVA6 Environment + uses: ./.github/actions/setup-cva6-env + with: + install-tools: "true" + + # ============================================================ + # Stage 2: RV32 Regression (parallel matrix jobs) + # ============================================================ + execute-rv32-tier2: + name: RV32 Tier2 ${{ matrix.config }} / ${{ matrix.testcase }} + runs-on: ubuntu-latest + needs: setup-tools + strategy: + fail-fast: false + matrix: + include: + # ---------------------------------------------------------- + # cv32a65x - dual-issue RV32, no MMU + # ---------------------------------------------------------- + + # Quick sanity check (~1 test) + - config: cv32a65x + testcase: smoke-tests-cv32a65x + mode: script + simulator: veri-testharness,spike + install_script: "" + testlist: "" + test_name: "" + linker: "" + + # CVA6-specific directed tests + - config: cv32a65x + testcase: cv32a6_tests + mode: script + simulator: veri-testharness,spike + install_script: "" + testlist: "" + test_name: "" + linker: "" + + # RISC-V architecture test suite (~105 tests) + - config: cv32a65x + testcase: dv-riscv-arch-test + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-arch-test + testlist: "../tests/testlist_riscv-arch-test-cv32a65x.yaml" + test_name: "" + linker: "../tests/riscv-arch-test/riscv-target/spike/link.ld" + + # Standard RISC-V tests, p-mode only (no MMU on cv32a65x, ~94 tests) + - config: cv32a65x + testcase: dv-riscv-tests-p + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-tests + testlist: "../tests/testlist_riscv-tests-cv32a65x-p.yaml" + test_name: "" + linker: "" + + # RISC-V compliance suite (~183 tests) + - config: cv32a65x + testcase: dv-riscv-compliance + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-compliance + testlist: "../tests/testlist_riscv-compliance-cv32a65x.yaml" + test_name: "" + linker: "" + + # Embedded CSR behavior (~5 tests); veri-testharness only - + # spike does not emulate embedded CSR side effects + - config: cv32a65x + testcase: dv-csr-embedded-tests + mode: script + simulator: veri-testharness + install_script: "" + testlist: "" + test_name: "" + linker: "" + + # hwconfig toolchain sanity (requires DV_HWCONFIG_OPTS) + - config: cv32a65x + testcase: hwconfig_tests + mode: script + simulator: veri-testharness,spike + install_script: "" + testlist: "" + test_name: "" + linker: "" + hwconfig_opts: cv32a65x + + # CoreMark benchmark on hwconfig; veri-testharness only - + # spike times out on long-running benchmark loops + - config: cv32a65x + testcase: coremark + mode: script + simulator: veri-testharness + install_script: "" + testlist: "" + test_name: "" + linker: "" + hwconfig_opts: cv32a65x + + # ---------------------------------------------------------- + # cv32a60x - single-issue RV32, no MMU + # ---------------------------------------------------------- + + # CVA6-specific directed tests + - config: cv32a60x + testcase: cv32a6_tests + mode: script + simulator: veri-testharness,spike + install_script: "" + testlist: "" + test_name: "" + linker: "" + + # RISC-V architecture test suite + - config: cv32a60x + testcase: dv-riscv-arch-test + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-arch-test + testlist: "../tests/testlist_riscv-arch-test-cv32a60x.yaml" + test_name: "" + linker: "../tests/riscv-arch-test/riscv-target/spike/link.ld" + + # Standard RISC-V tests, p-mode only (no MMU on cv32a60x) + - config: cv32a60x + testcase: dv-riscv-tests-p + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-tests + testlist: "../tests/testlist_riscv-tests-cv32a60x-p.yaml" + test_name: "" + linker: "" + + # RISC-V compliance suite + - config: cv32a60x + testcase: dv-riscv-compliance + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-compliance + testlist: "../tests/testlist_riscv-compliance-cv32a60x.yaml" + test_name: "" + linker: "" + + steps: + - uses: actions/checkout@v7 + with: + submodules: recursive + + - name: Setup CVA6 Environment + uses: ./.github/actions/setup-cva6-env + + - name: Install prerequisites + run: source ci/install-prereq.sh + + - name: Run Tier 2 for ${{ matrix.config }} / ${{ matrix.testcase }} + env: + TIER_NAME: Tier 2 + TIER_MODE: ${{ matrix.mode }} + TIER_CONFIG: ${{ matrix.config }} + TIER_TESTCASE: ${{ matrix.testcase }} + TIER_SIMULATOR: ${{ matrix.simulator }} + TIER_INSTALL_SCRIPT: ${{ matrix.install_script }} + TIER_TESTLIST: ${{ matrix.testlist }} + TIER_TEST_NAME: ${{ matrix.test_name }} + TIER_LINKER: ${{ matrix.linker }} + TIER_HWCONFIG_OPTS: ${{ matrix.hwconfig_opts }} + run: bash .github/scripts/run-tier-regression.sh + + - name: Upload Results + if: always() + uses: actions/upload-artifact@v4 + with: + name: tier2-rv32-${{ matrix.config }}-${{ matrix.testcase }} + path: | + ci-results/ + verif/sim/out*/ + retention-days: 14 + + # ============================================================ + # Stage 3: RV64 Regression (parallel matrix jobs) + # ============================================================ + execute-rv64-tier2: + name: RV64 Tier2 ${{ matrix.config }} / ${{ matrix.testcase }} + runs-on: ubuntu-latest + needs: setup-tools + strategy: + fail-fast: false + matrix: + include: + # ---------------------------------------------------------- + # cv64a6_imafdc_sv39_hpdcache_wb - RV64 HPDcache + write-back + # ---------------------------------------------------------- + + # CVA6-specific directed tests + - config: cv64a6_imafdc_sv39_hpdcache_wb + testcase: cv64a6_imafdc_tests + mode: script + simulator: veri-testharness,spike + install_script: "" + testlist: "" + test_name: "" + linker: "" + + # RISC-V architecture test suite + - config: cv64a6_imafdc_sv39_hpdcache_wb + testcase: dv-riscv-arch-test + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-arch-test + testlist: "../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml" + test_name: "" + linker: "../tests/riscv-arch-test/riscv-target/spike/link.ld" + + # Standard RISC-V tests, virtual-mode (SV39 MMU) + # "dv-riscv-tests-v" is a job label - runs via cva6.py --testlist, + # there is no verif/regress/dv-riscv-tests-v.sh + - config: cv64a6_imafdc_sv39_hpdcache_wb + testcase: dv-riscv-tests-v + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-tests + testlist: "../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml" + test_name: "" + linker: "" + + # Standard RISC-V tests, physical-mode + # "dv-riscv-tests-p" is a job label - same note as dv-riscv-tests-v above + - config: cv64a6_imafdc_sv39_hpdcache_wb + testcase: dv-riscv-tests-p + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-tests + testlist: "../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml" + test_name: "" + linker: "" + + # RISC-V compliance suite (uses sv39 testlist - valid for hpdcache_wb) + - config: cv64a6_imafdc_sv39_hpdcache_wb + testcase: dv-riscv-compliance + mode: testlist + simulator: veri-testharness,spike + install_script: install-riscv-compliance + testlist: "../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml" + test_name: "" + linker: "" + + steps: + - uses: actions/checkout@v7 + with: + submodules: recursive + + - name: Setup CVA6 Environment + uses: ./.github/actions/setup-cva6-env + + - name: Install prerequisites + run: source ci/install-prereq.sh + + - name: Run Tier 2 for ${{ matrix.config }} / ${{ matrix.testcase }} + env: + TIER_NAME: Tier 2 + TIER_MODE: ${{ matrix.mode }} + TIER_CONFIG: ${{ matrix.config }} + TIER_TESTCASE: ${{ matrix.testcase }} + TIER_SIMULATOR: ${{ matrix.simulator }} + TIER_INSTALL_SCRIPT: ${{ matrix.install_script }} + TIER_TESTLIST: ${{ matrix.testlist }} + TIER_TEST_NAME: ${{ matrix.test_name }} + TIER_LINKER: ${{ matrix.linker }} + TIER_HWCONFIG_OPTS: ${{ matrix.hwconfig_opts }} + run: bash .github/scripts/run-tier-regression.sh + + - name: Upload Results + if: always() + uses: actions/upload-artifact@v4 + with: + name: tier2-rv64-${{ matrix.config }}-${{ matrix.testcase }} + path: | + ci-results/ + verif/sim/out*/ + retention-days: 14 diff --git a/.github/workflows/openhw-cva6-tier-dashboard.yml b/.github/workflows/openhw-cva6-tier-dashboard.yml new file mode 100644 index 00000000000..18bc892f9a4 --- /dev/null +++ b/.github/workflows/openhw-cva6-tier-dashboard.yml @@ -0,0 +1,137 @@ +name: openhw-cva6-tier-dashboard + +on: + workflow_run: + workflows: + - ci + - openhw-cva6-ci-tier1 + - openhw-cva6-ci-tier2 + types: + - completed + workflow_dispatch: + +concurrency: + group: openhw-cva6-tier-dashboard + cancel-in-progress: false + +permissions: + actions: read + contents: write + pages: write + id-token: write + +jobs: + build: + name: Build Tier Dashboard + runs-on: ubuntu-latest + steps: + - name: Checkout repository + uses: actions/checkout@v7 + + - name: Restore tier dashboard history from gh-pages-cva6-tier-dashboard-data + run: | + mkdir -p /tmp/tier-data + if git ls-remote --heads origin gh-pages-cva6-tier-dashboard-data | grep -q gh-pages-cva6-tier-dashboard-data; then + git fetch origin gh-pages-cva6-tier-dashboard-data --depth=1 + git checkout origin/gh-pages-cva6-tier-dashboard-data -- data/ 2>/dev/null && \ + cp -r data/* /tmp/tier-data/ 2>/dev/null || \ + echo "No existing data on gh-pages-cva6-tier-dashboard-data, starting fresh" + else + echo "gh-pages-cva6-tier-dashboard-data branch does not exist yet, starting fresh" + fi + + - name: Collect tier dashboard CI data + env: + GH_TOKEN: ${{ github.token }} + run: | + python3 .github/scripts/dashboard_tiers/collect_data.py \ + --repo "${{ github.repository }}" \ + --data-dir /tmp/tier-data \ + --fetch-count 20 + + - name: Install Jinja2 + run: pip install jinja2 + + - name: Generate tier dashboard HTML + run: | + python3 .github/scripts/dashboard_tiers/generate_dashboard.py \ + --data-dir /tmp/tier-data \ + --output-dir /tmp/dash-site \ + --repo "${{ github.repository }}" + + - name: Prepare Pages artifact + run: | + cp -r /tmp/tier-data /tmp/dash-site/data + + - name: Upload Pages artifact + uses: actions/upload-pages-artifact@v3 + with: + path: /tmp/dash-site + + - name: Upload preview artifact + uses: actions/upload-artifact@v4 + with: + name: cva6-tier-dashboard-site + path: /tmp/dash-site + retention-days: 14 + + - name: Upload data for persistence job + uses: actions/upload-artifact@v4 + with: + name: cva6-tier-dashboard-data + path: /tmp/tier-data/ + retention-days: 7 + + deploy: + name: Deploy to Pages + needs: build + runs-on: ubuntu-latest + environment: + name: github-pages + url: ${{ steps.deployment.outputs.page_url }} + steps: + - name: Deploy to GitHub Pages + id: deployment + uses: actions/deploy-pages@v4 + + persist-tier-data: + name: Persist Tier Dashboard Data + needs: build + runs-on: ubuntu-latest + steps: + - name: Checkout repository + uses: actions/checkout@v7 + + - name: Prepare gh-pages-cva6-tier-dashboard-data branch + run: | + git config user.name "github-actions[bot]" + git config user.email "github-actions[bot]@users.noreply.github.com" + if git ls-remote --exit-code --heads origin gh-pages-cva6-tier-dashboard-data >/dev/null 2>&1; then + git fetch origin gh-pages-cva6-tier-dashboard-data --depth=1 + git checkout -B gh-pages-cva6-tier-dashboard-data origin/gh-pages-cva6-tier-dashboard-data + else + git checkout --orphan gh-pages-cva6-tier-dashboard-data + git rm -rf . >/dev/null 2>&1 || true + find . -mindepth 1 -maxdepth 1 ! -name .git -exec rm -rf {} + + echo "# CVA6 Tier Dashboard Data" > README.md + git add README.md + git commit -m "Initialize gh-pages-cva6-tier-dashboard-data branch" + fi + + - name: Download updated tier data + uses: actions/download-artifact@v4 + with: + name: cva6-tier-dashboard-data + path: data/ + + - name: Commit and push tier data + run: | + git config user.name "github-actions[bot]" + git config user.email "github-actions[bot]@users.noreply.github.com" + git add data/ + if git diff --cached --quiet; then + echo "No data changes to commit" + else + git commit -m "Update cva6 tier dashboard data [skip ci]" + git push origin HEAD:gh-pages-cva6-tier-dashboard-data + fi diff --git a/.github/workflows/verible.yml b/.github/workflows/verible.yml index 87496bc03a3..c36eccc1784 100644 --- a/.github/workflows/verible.yml +++ b/.github/workflows/verible.yml @@ -4,20 +4,21 @@ name: Verible on: - pull_request_target: + pull_request: jobs: format: runs-on: ubuntu-latest - permissions: - checks: write - contents: read - pull-requests: write steps: - - uses: actions/checkout@v3 - with: - ref: ${{ github.event.pull_request.head.sha }} + - uses: actions/checkout@v7 - uses: chipsalliance/verible-formatter-action@main with: github_token: ${{ secrets.GITHUB_TOKEN }} - files: '$(find core -regex ".*\.\(v\|sv\)$" | grep -v "^core/include/.*_config_pkg.sv$")' + verible_version: v0.0-4084-gf3e4d98b + files: '$(find core -regex ".*\.\(v\|sv\)$" | grep -v "^core/include/.*_config_pkg\.sv$")' + fail_on_formatting_suggestions: true + - name: CVA6Cfg's XLEN attribute usage verificatory script + if: always() + run: | + chmod +x util/sanitize/systemverilog/xlen_misuse.sh + util/sanitize/systemverilog/xlen_misuse.sh diff --git a/.gitignore b/.gitignore index 962e0666325..0ae122fe666 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,5 @@ +*.swp +*.swo site/* *.ucdb covhtmlreport/* @@ -50,3 +52,8 @@ Bender.lock # Both following lines are needed to list contents of ISA manual build dir. !/vendor/riscv/riscv-isa-manual/build/ !/vendor/riscv/riscv-isa-manual/build/* +/config/gen_from_riscv_config/hwconfig/linker/link.ld +/config/gen_from_riscv_config/hwconfig/spike/spike.yaml +/verif/sim/encaps.traces +/verif/sim/iti.traces +/verif/sim/verilator.fst.hier diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index d108464c673..5c6bc2dc1c5 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -124,7 +124,7 @@ build_tools: stage: light tests rules: *on_dev before_script: - - git -C verif/core-v-verif fetch --unshallow + - git -C verif/core-v-verif fetch --unshallow || git -C verif/core-v-verif fetch --all - !reference [.copy_spike_artifacts] - rm -rf artifacts/ - mkdir -p artifacts/{reports,logs} @@ -141,7 +141,7 @@ smoke-tests: - .fe_smoke_test variables: DASHBOARD_JOB_TITLE: "Smoke test $DV_SIMULATORS $DV_TARGET" - DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenchs configurations" + DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most architectures with most testbenches configurations" DASHBOARD_SORT_INDEX: 0 DASHBOARD_JOB_CATEGORY: "Basic" SPIKE_TANDEM: 1 @@ -156,6 +156,29 @@ smoke-tests: - if [[ $DV_SIMULATORS == *"questa"* ]]; then source $QUESTA_BASHRC; fi - bash verif/regress/smoke-tests-$DV_TARGET.sh - !reference [.simu_after_script] + rules: + - allow_failure: true + +sdtrig-tests: + extends: + - .fe_smoke_test + variables: + DASHBOARD_JOB_TITLE: "Sdtrig test $DV_SIMULATORS $DV_TARGET" + DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge sdtrig features in cv32a65x configuration" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Basic" + COLLECT_SIMU_LOGS: 1 + parallel: + matrix: + - DV_SIMULATORS: "vcs-uvm" + DV_TARGET: "cv32a65x" + - DV_SIMULATORS: "vcs-uvm" + DV_TARGET: "cv32a60x" + script: + - bash verif/regress/triggers-tests-$DV_TARGET.sh + - python3 .gitlab-ci/scripts/report_pass.py + rules: + - allow_failure: true smoke-gen: extends: @@ -208,6 +231,19 @@ smoke-hwconfig: - source verif/regress/hwconfig_tests.sh - python3 .gitlab-ci/scripts/report_pass.py +hello-pk: + extends: + - .fe_smoke_test + variables: + DASHBOARD_JOB_TITLE: "Hello world with veri-testharness-pk on multiple RTL targets." + DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge target configurations" + DASHBOARD_SORT_INDEX: 1 + DASHBOARD_JOB_CATEGORY: "Basic" + COLLECT_SIMU_LOGS: 1 + script: + - bash verif/regress/veri-testharness-pk-tests.sh + - python3 .gitlab-ci/scripts/report_pass.py + .synthesis_test: stage: heavy tests timeout: 2 hours @@ -225,6 +261,21 @@ smoke-hwconfig: - when: manual allow_failure: true +it-test: + extends: + - .synthesis_test + variables: + DASHBOARD_JOB_TITLE: "Instruction Trace test" + DASHBOARD_JOB_DESCRIPTION: "Test to Challenge the Hardware flow of the Instruction Tracer" + DASHBOARD_SORT_INDEX: 0 + DASHBOARD_JOB_CATEGORY: "Basic" + DV_SIMULATORS: "vcs-testharness" + script: + - python3 .gitlab-ci/scripts/report_fail.py + - bash verif/regress/Instr_tracing_test.sh ../tests/custom/ITI/test_iti_asm.o + - python3 .gitlab-ci/scripts/report_pass.py + - cp -r verif/sim/Instr_tracing_artifact artifacts/ + spyglass: extends: - .synthesis_test @@ -243,7 +294,7 @@ spyglass: - cp spyglass/reference_summary.rpt artifacts/lint_reports - python3 .gitlab-ci/scripts/report_spyglass_lint.py spyglass/reference_summary.rpt artifacts/lint_reports/cva6_lint_lint_rtl/summary.rpt -cvxif-regression: +.cvxif-regression: extends: - .synthesis_test variables: @@ -273,7 +324,7 @@ asic-synthesis: - echo $DV_TARGET - source ./verif/sim/setup-env.sh - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH} - - git -C ${SYNTH_SCRIPT_PATH} checkout cce5ea41 + - git -C ${SYNTH_SCRIPT_PATH} checkout 3c0dd72d - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../ - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC @@ -304,6 +355,20 @@ fpga-build: - mv corev_apu/fpga/work-fpga/ariane_xilinx.bit artifacts/ariane_xilinx_$TARGET.bit - python3 .gitlab-ci/scripts/report_fpga.py corev_apu/fpga/reports/ariane.utilization.rpt +pmp_tests: + timeout : 2 hours + extends: + - .synthesis_test + variables: + DASHBOARD_JOB_TITLE: "PMP $DV_TARGET" + DASHBOARD_JOB_DESCRIPTION: "Physical Memory Protection tests" + DASHBOARD_SORT_INDEX: 2 + DASHBOARD_JOB_CATEGORY: "Test suites" + DV_SIMULATORS: "vcs-uvm" + SPIKE_TANDEM: 1 + script: source verif/regress/pmp_cv32a65x_tests.sh + after_script: *simu_after_script + .regress_test: stage: heavy tests before_script: @@ -323,20 +388,21 @@ benchmarks: DASHBOARD_SORT_INDEX: 5 DASHBOARD_JOB_CATEGORY: "Performance" SPIKE_TANDEM: 1 + RISCV: "${RISCV_GCC15}" parallel: matrix: - BENCH: "dhrystone" ISSUE: "single" - DV_HWCONFIG_OPTS: ["cv32a60x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a60x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT BPType=config_pkg::PH_BHT"] - BENCH: "dhrystone" ISSUE: "dual" - DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT BPType=config_pkg::PH_BHT"] - BENCH: "coremark" ISSUE: "single" - DV_HWCONFIG_OPTS: ["cv32a60x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a60x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT BPType=config_pkg::PH_BHT"] - BENCH: "coremark" ISSUE: "dual" - DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT BPType=config_pkg::PH_BHT"] script: - bash verif/regress/"$BENCH".sh - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_"$ISSUE" verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log @@ -543,12 +609,12 @@ simu-gate: PERIOD: "15" # 66 Mhz script: - mkdir -p artifacts/{reports,logs} - - git -C verif/core-v-verif fetch --unshallow + - git -C verif/core-v-verif fetch --unshallow || git -C verif/core-v-verif fetch --all - !reference [.copy_spike_artifacts] - echo $PERIOD - source ./verif/sim/setup-env.sh - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH} - - git -C ${SYNTH_SCRIPT_PATH} checkout cce5ea41 + - git -C ${SYNTH_SCRIPT_PATH} checkout 3c0dd72d - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../ - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch - source verif/regress/install-riscv-tests.sh diff --git a/.gitlab-ci/README.md b/.gitlab-ci/README.md index 0a1d7678246..5af80202b26 100644 --- a/.gitlab-ci/README.md +++ b/.gitlab-ci/README.md @@ -144,7 +144,7 @@ import report_builder as rb # Create metrics metric = rb.TableMetric('Metric name') -metric.add_value('colomn 1', 'colomn 2', 'etc') +metric.add_value('column 1', 'column 2', 'etc') # Gather them into a report report = rb.Report('report label') @@ -159,12 +159,12 @@ There are 3 kinds of metric: ```python # A simple table metric = rb.TableMetric('Metric name, actually not displayed yet') -metric.add_value('colomn 1', 'colomn 2', 'etc') +metric.add_value('column 1', 'column 2', 'etc') # A table with a pass/fail label on each line metric = rb.TableStatusMetric('Metric name, actually not displayed yet') -metric.add_pass('colomn 1', 'colomn 2', 'etc') -metric.add_fail('colomn 1', 'colomn 2', 'etc') +metric.add_pass('column 1', 'column 2', 'etc') +metric.add_fail('column 1', 'column 2', 'etc') # A log metric = rb.LogMetric('Metric name, actually not displayed yet') diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml index 72ae96f3981..49cb562e554 100644 --- a/.gitlab-ci/expected_synth.yml +++ b/.gitlab-ci/expected_synth.yml @@ -1,2 +1,2 @@ cv32a65x: - gates: 184679 + gates: 182900 diff --git a/.gitlab-ci/scripts/github_integration.py b/.gitlab-ci/scripts/github_integration.py index c49c5b79838..d91016ebd7c 100644 --- a/.gitlab-ci/scripts/github_integration.py +++ b/.gitlab-ci/scripts/github_integration.py @@ -3,6 +3,7 @@ """ from os import environ as env +import time import requests def api_url(owner, repo): @@ -52,6 +53,7 @@ def send(self, pr, success): 'pr_number': str(pr), 'success': success, } + time.sleep(120) return self._trigger(inputs) def send_success(self, pr): diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py index cec2c10fdc1..a29f3ec93a5 100644 --- a/.gitlab-ci/scripts/report_benchmark.py +++ b/.gitlab-ci/scripts/report_benchmark.py @@ -19,12 +19,12 @@ # Keep it up-to-date with compiler version and core performance improvements # Will fail if the number of cycles is different from this one valid_cycles = { - "dhrystone_dual": 18935, - "dhrystone_single": 24127, - "coremark_dual": 1001191, - "coremark_single": 1300030, - "dhrystone_cv32a65x": 31976, - "dhrystone_cv32a60x": 39449, + "dhrystone_dual": 16990, + "dhrystone_single": 23866, + "coremark_dual": 199928, + "coremark_single": 290690, + "dhrystone_cv32a65x": 27329, + "dhrystone_cv32a60x": 36629, } for arg in sys.argv[1:]: @@ -33,7 +33,7 @@ iterations = 50 else: if "--coremark" in arg: - iterations = 4 + iterations = 1 mode = arg.replace("-", "") else: path = arg diff --git a/.gitlab-ci/scripts/report_synth.py b/.gitlab-ci/scripts/report_synth.py index 06cf9833b04..bd33df72f4a 100644 --- a/.gitlab-ci/scripts/report_synth.py +++ b/.gitlab-ci/scripts/report_synth.py @@ -45,7 +45,7 @@ warning_log.append(line) log_metric.values = error_log + warning_log -# Area repport: +# Area report: pattern = re.compile( "^(Combinational area|Buf/Inv area|Noncombinational area|Macro/Black Box area):\ *(\d*\.\d*)$", re.MULTILINE) @@ -82,7 +82,7 @@ for i in hier: hier_metric.add_value( i[0], # hier - f"{int(float(i[1])/kgate_ratio)} kGates", # area + f"{float(i[1])/kgate_ratio:.3f} kGates", # area f"{int(float(i[2]))} %", # % #int(float(i[3]))/int(float(i[1])*100), # % combi #int(float(i[4]))/int(float(i[1])*100), # % reg diff --git a/.gitmodules b/.gitmodules index ef0f5995179..e87394db64e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -19,9 +19,6 @@ [submodule "corev_apu/fpga/src/ariane-ethernet"] path = corev_apu/fpga/src/ariane-ethernet url = https://github.com/lowRISC/ariane-ethernet.git -[submodule "corev_apu/src/axi_riscv_atomics"] - path = corev_apu/src/axi_riscv_atomics - url = https://github.com/pulp-platform/axi_riscv_atomics.git [submodule "corev_apu/riscv-dbg"] path = corev_apu/riscv-dbg url = https://github.com/pulp-platform/riscv-dbg.git diff --git a/.readthedocs.yaml b/.readthedocs.yaml index d9241c38438..394ddbbd995 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -10,7 +10,7 @@ submodules: recursive: true build: - os: "ubuntu-20.04" + os: "ubuntu-26.04" tools: python: "3.9" nodejs: "20" diff --git a/Bender.yml b/Bender.yml index 5ef388dad7b..966c56388ab 100644 --- a/Bender.yml +++ b/Bender.yml @@ -1,5 +1,5 @@ package: - name: ariane + name: cva6 authors: - "Florian Zaruba " - "Michael Schaffner " @@ -10,12 +10,14 @@ dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 } common_cells: { git: "https://github.com/pulp-platform/common_cells", version: 1.23.0 } - fpnew: { git: "https://github.com/openhwgroup/cvfpu.git", version: 0.7.0 } + fpnew: { git: "https://github.com/openhwgroup/cvfpu.git", rev: 3eb6afe } # branch: develop tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 } export_include_dirs: - core/include + - core/cache_subsystem/hpdcache/rtl/include + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc sources: - include_dirs: @@ -35,6 +37,14 @@ sources: files: - core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv + - target: cv64a6_imafdc_sv39_hpdcache + files: + - core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv + + - target: cv64a6_imafdc_sv39_hpdcache_wb + files: + - core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv + - target: cv64a6_imafdch_sv39 files: - core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -55,6 +65,18 @@ sources: files: - core/include/cv32a6_imafc_sv32_config_pkg.sv + - target: cv32a60x + files: + - core/include/cv32a60x_config_pkg.sv + + - target: cv32a65x + files: + - core/include/cv32a65x_config_pkg.sv + + - target: cv64a60ax_cvfpu_uvm + files: + - core/include/cv64a60ax_config_pkg_cvfpu-uvm.sv + # General config infrastructure - core/include/riscv_pkg.sv - core/include/ariane_pkg.sv @@ -65,19 +87,24 @@ sources: - core/cva6_accel_first_pass_decoder_stub.sv # MMU - - target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdch_sv39_wb, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32) + - target: any(cv64a6_imafdcv_sv39, cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_wb, cv64a6_imafdch_sv39, cv64a6_imafdc_sv39_hpdcache, cv64a6_imafdc_sv39_hpdcache_wb, cv64a6_imafdch_sv39_wb, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32) files: - core/cva6_mmu/cva6_tlb.sv + - core/cva6_mmu/cva6_shared_tlb.sv - core/cva6_mmu/cva6_mmu.sv - core/cva6_mmu/cva6_ptw.sv # Packages + - core/include/dummy_l15_pkg.sv - core/include/wt_cache_pkg.sv - core/include/std_cache_pkg.sv + - core/include/aes_pkg.sv # Extension Interface - core/cvxif_example/include/cvxif_instr_pkg.sv - core/cvxif_fu.sv + - core/cvxif_issue_register_commit_if_driver.sv + - core/cvxif_compressed_if_driver.sv - core/cvxif_example/cvxif_example_coprocessor.sv - core/cvxif_example/instr_decoder.sv @@ -86,7 +113,9 @@ sources: - core/cva6_fifo_v3.sv # Top-level source files (not necessarily instantiated at the top of the cva6). - core/cva6.sv + - core/aes.sv - core/alu.sv + - core/alu_wrapper.sv - core/fpu_wrap.sv # depends on fpnew_pkg, above - core/branch_unit.sv - core/compressed_decoder.sv @@ -95,6 +124,7 @@ sources: - core/csr_regfile.sv - core/decoder.sv - core/ex_stage.sv + - core/acc_dispatcher.sv - core/instr_realign.sv - core/id_stage.sv - core/issue_read_operands.sv @@ -109,6 +139,7 @@ sources: - core/ariane_regfile_ff.sv - core/ariane_regfile_fpga.sv - core/scoreboard.sv + - core/raw_checker.sv - core/store_buffer.sv - core/amo_buffer.sv - core/store_unit.sv @@ -118,6 +149,7 @@ sources: # Frontend (i.e., fetch, decode, dispatch) - core/frontend/btb.sv - core/frontend/bht.sv + - core/frontend/bht2lvl.sv - core/frontend/ras.sv - core/frontend/instr_scan.sv - core/frontend/instr_queue.sv @@ -138,10 +170,81 @@ sources: - core/cache_subsystem/cache_ctrl.sv - core/cache_subsystem/std_nbdcache.sv - core/cache_subsystem/std_cache_subsystem.sv + # HPDCache sources + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg_initialized.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_bin_encoder.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv + - core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv + - core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv + - core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv + - core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv + - core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv + - core/cache_subsystem/hpdcache/rtl/src/hpdcache_cbuf.sv + # HPDCache integration + - core/cache_subsystem/cva6_hpdcache_if_adapter.sv + - core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv + - core/cache_subsystem/cva6_hpdcache_subsystem.sv + - core/cache_subsystem/cva6_hpdcache_wrapper.sv + # HPDCache ECC + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc/prim_secded_pkg.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc/prim_secded_36_29_dec.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc/prim_secded_36_29_enc.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc/prim_secded_39_32_dec.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc/prim_secded_39_32_enc.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc/prim_secded_55_48_dec.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc/prim_secded_55_48_enc.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc/prim_secded_72_64_dec.sv + - core/cache_subsystem/hpdcache/rtl/src/utils/ecc/prim_secded_72_64_enc.sv + # HPDCache SRAM models + - core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv + - core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_ecc_1rw.sv + - core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv + - core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_ecc_1rw.sv + - core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv + - core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_ecc_1rw.sv # Physical Memory Protection - core/pmp/src/pmp.sv - core/pmp/src/pmp_entry.sv + - core/pmp/src/pmp_data_if.sv - include_dirs: - common/local/util @@ -153,12 +256,16 @@ sources: - common/local/util files: - common/local/util/tc_sram_wrapper.sv + - common/local/util/sram_cache.sv + - common/local/util/tc_sram_wrapper_cache_techno.sv - target: all(fpga, xilinx) include_dirs: - common/local/util files: + - common/local/util/sram_cache.sv - common/local/util/tc_sram_fpga_wrapper.sv + - vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv - target: not(synthesis) include_dirs: diff --git a/CHANGELOG.md b/CHANGELOG.md index 3046b001e78..e58658fd622 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -218,7 +218,7 @@ src/util/axi_slave_connect_rev.sv ### Added -- Improved instruction fetch fronten-end +- Improved instruction fetch front-end - Add RAS - Add support for Bender hardware management diff --git a/CODEOWNERS b/CODEOWNERS index 9a4976dad47..67589d40d8e 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -1,5 +1,5 @@ # Global Owners -* @JeanRochCoulon @zarubaf +* @JeanRochCoulon # Core @@ -7,9 +7,18 @@ core/mmu_sv39 @sjthales core/cvxif_example @Gchauvon core/cvxif_fu.sv @Gchauvon -# APU +# HPDCache + +core/cache_subsystem/hpdcache @cfuguet +core/cache_subsystem/cva6_hpdcache* @cfuguet +core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @cfuguet +core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv @cfuguet + +# OpenPiton corev_apu/openpiton @Jbalkind +core/cache_subsystem/wt_l15_adapter.sv @Jbalkind +core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @Jbalkind ## Documentation diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 51b182403c2..3d8d0008fa9 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -1,39 +1,55 @@ # Contributing -New Contributors are always welcome. + +New motivated Contributors are always welcome. Note that Contributors are required to be covered by an [Eclipse Contributor Agreement](https://www.eclipse.org/legal/ECA.php). -Contributors are encouraged, but not required, to be a [member](https://www.openhwgroup.org/membership/) of the OpenHW Group. +If a pull request has been open with no ECA for more than 24 hours, we consider it as either an automated pull request, which is not allowed, or an unmotivated pull request, which is rejected. +Such pull requests will be closed by maintainers. +So, if you encounter any issues, with the signing process, please tell us! +We will be glad to help. +Drop a comment in your pull request so we know about your problem and we do not close your pull request. + +Contributors are encouraged, but not required, to be a [member](https://openhwfoundation.org/membership/become-a-member/) of the OpenHW Foundation, part of the Eclipse Foundation. -## Read this before +## Read this first ### Major evolutions CVA6 has turned into an industrial project, where the core is being verified to be integrated in production ICs. -In the same time, we'd like to continue integrating some new contributions to keep CVA6 a vivid and innovative ecosystem. -But this comes with constraints to ensure that new contributions do not put the industrial project at risk. +At the same time, we'd like to continue integrating some new contributions to keep CVA6 a vivid and innovative ecosystem. +This comes with constraints to ensure that new contributions do not put the industrial project at risk. -Therefore here are guidelines to help the CVA6 team accept new contributions: +Past experience indicates that a workplan shared early with the CVA6 project team and regular synchronization improves the project's ability to integrate major contributions. +Early discussions with the CVA6 team will help us to develop a strategy to integrate your contribution onto a specific development branch, with the goal of upstreaming to the master branch. +Here are some guidelines to help the CVA6 team accept new contributions of major features: - Get in touch early with the CVA6 team, present your initiative, get feedback, synchronize with the team... * The CVA6 team wants to assess the potential of your contribution. + * The CVA6 team plans the next evolutions, and your contributions could be incompatible with them. * The CVA6 team can provide you recommendations to ease the upcoming contribution. * This can help save significant review and overhauling effort for you and us when dealing with the pull request review. * Together, we can anticipate specific cases that are not addressed here. - * If you do not know how to contact us already, get in touch through info@openhwgroup.org or open an issue in GitHub. + * If you do not know how to contact us already, get in touch through info@eclipse-foundation.org or open an issue in GitHub. - Specific recommendations: - * Always consider using the CV-X-IF interface if your contribution is an instruction-set extension. - - and talk to the team if it's not possible. + * For instruction set extensions, talk to the team to assess the relevance of including it into the core or as a coprocessor on the CV-X-IF interface. + - If the extension is custom (not a RISC-V specified extension), a coprocessor on CV-X-IF is definitely its place. * Your contribution shall be optional and fully disabled by default. - so that projects already using CVA6 are not impacted (no functionality change, no extra silicon...). - * To configure your contribution, System Verilog top-level parameters are preferred. - - Synchronize with CVA6 team if this is not possible and you need other means (`directives, ariane_pkg parameters, templating...) - - Synchronize with CVA6 team (again) because this rule is likely to change over time as we are considering templating. + * To configure your contribution, System Verilog top-level parameters are strongly advised. + - Conditional compiler directives such as `ifdef, etc. are strongly discouraged. + - Please review our wiki on the topic of [Configuring SystemVerilog RTL Models](https://github.com/openhwgroup/cva6/wiki/Configuring-SystemVerilog-RTL-Models), in particular the [CVA6 use case](https://github.com/openhwgroup/cva6/wiki/Configuring-SystemVerilog-RTL-Models#use-case-the-openhw-foundation-cva6). + - Synchronize with CVA6 team if you do not find an appropriate solution. * Commit to maintain your contribution 2 years after the pull request - We know it's not always possible, so refer to the next rule. - * Your complete contribution shall be identifiable with parameters (or `directives / templating if together we decide to go this way). + * Your complete contribution shall be identifiable with parameters. - If at some point we need to revert it, e.g. if there is no-one maintaining nor using it and it has become a burden to the project. - We call this the "parachute" rule: The CVA6 team does not want to use it but is far more comfortable getting one. + - Also, this allows not to lose code coverage in verification when your contribution is not enabled (with some tweaks in the coverage tool). + - This rule also applies to CSRs which are specific to your contribution. + * To ease maintenance, all common code lines shall exist only once. + - Counter-example: CVA6 used to have two different MMU modules (Sv32 and Sv39) for CV32A6 and CV64A6. It took time to refactor both in a joint design to ease maintenance. + - Related reading for reference: [DRY principle](https://en.wikipedia.org/wiki/Don%27t_repeat_yourself) * Your contribution shall pass the Continuous Integration (CI) flow - When the contribution is disabled: in all cases, to ensure you have not broken the design. - When the contribution is disabled: the line and condition code coverage shall not be impacted. @@ -44,12 +60,34 @@ Therefore here are guidelines to help the CVA6 team accept new contributions: - So that we can detect quickly if future updates break your contribution. - To avoid impacting those users who use your contribution in their project. - At this point, we do not request a 100%-coverage verification suite. + * Please consider adding related documentation in the user's guide and design document. + * Be kind to the people who process your pull request(s) + - Explain your contribution in the pull request. + - If your contribution solves an issue, fill in an issue and cross link it in the pull-request. + - The reviewer(s) prefer to review several small pull requests rather one large pull request. Synchronize with the team to identify the right breakdown. If you encounter difficulties with these guidelines, get in touch with the team! ### Bug fixing -Bug fixing is always welcome. You can issue a GitHub issue. Better: solve the bug and trigger a pull request. +Bug fixing is always welcome. You can open a GitHub issue. +Better: in addition to the issue, solve the bug and trigger a pull request. +Ideally, your pull request will include a testcase that illustrates the bug. + +### Use of AI + +We understand that some developers are assisted by large language models to help write code. However, AI-generated code shall always be reviewed and endorsed **by the human contributor** before submitting the pull request. +The review by the human contributor shall be as thorough as if they had written the code themselves. Notably the human contributor shall understand and explain all generated code and assess the relevance of comments. + +Contributions through code/documentation (pull requests) or feedback (issues) are highly appreciated, but keep in mind that each contribution has a cost for the project, as reviewers will spend time discussing the contributions. +For more information on this topic, see: + +This is why **automated pull requests, directly generated by large language models or AI coding assistants, are not permitted in this repository**. +Such contributions will be closed without review. + +Also, note that the review process implies discussing the contribution between the reviewers and the author. +We consider that it would be particularly rude if the author lets an AI answer instead of answering themselves. +We are not expecting long answers with a perfect English. We are expecting *the author's* thoughts on a specific topic. ## The Mechanics 1. From GitHub: [fork](https://help.github.com/articles/fork-a-repo/) the [cva6](https://github.com/openhwgroup/cva6) repository @@ -59,7 +97,7 @@ See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/Git 4. Make your edits... 5. Commit your changes: `git commit -m 'Add some feature'` 6. Push feature branch: `git push origin ` -7. From GitHub: submit a pull request +7. From GitHub: submit a pull request. The description must tell the reviewers why these changes are important for the project. More advice is provided in the pull request template. Please note that we do not accept outdated pull requests. This makes sure the CI flow has run in the to-be version of the master. @@ -67,12 +105,16 @@ This makes sure the CI flow has run in the to-be version of the master. To allow us to update the pull request before merging it, please consider checking the "Allow edits from maintainers" checkbox. Note that this can only be done with pull requests from your personal repository (it is impossible from organization repositories). +One last note: use the same email address for your GitHub and Eclipse accounts, to ensure a smooth Eclipse Contributor Agreement +check for your pull request. + ## Coding Style -For RTL coding, the OpenHW Group has adopted the [lowRISC Style Guides](https://github.com/lowRISC/style-guides/). +For RTL coding, the OpenHW Foundation has adopted the [lowRISC Style Guides](https://github.com/lowRISC/style-guides/). ## Git Considerations +- The pull request must be rebased on the master branch to be merged on GitHub. That is why we are requesting permissions on the PR branch to allow the committer to perform the rebasing. - Do not push to master, if you want to add a feature do it in your branch. - Separate subject from body with a blank line. - Limit the subject line to 50 characters. @@ -99,3 +141,5 @@ To format RTL files checked by GitHub , use the following command: ``` verible-verilog-format --inplace $(git ls-tree -r HEAD --name-only core |grep '\.sv$' |grep -v '^core/include/std_cache_pkg.sv$' |grep -v cvfpu) ``` + +The Verible version currently used in the GitHub CI worflow can be found in [`.github/workflows/verible.yml`](.github/workflows/verible.yml). diff --git a/Flist.ariane b/Flist.ariane index 0edfa8e4f59..d26530549d3 100644 --- a/Flist.ariane +++ b/Flist.ariane @@ -20,24 +20,40 @@ +incdir+common/local/util/ +incdir+corev_apu/register_interface/include/ +core/include/config_pkg.sv core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv core/include/riscv_pkg.sv corev_apu/riscv-dbg/src/dm_pkg.sv -vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv +core/cvfpu/src/fpnew_pkg.sv core/include/ariane_pkg.sv -core/include/acc_pkg.sv corev_apu/tb/ariane_soc_pkg.sv vendor/pulp-platform/axi/src/axi_pkg.sv corev_apu/tb/ariane_axi_pkg.sv core/include/wt_cache_pkg.sv corev_apu/tb/axi_intf.sv -core/include/cvxif_pkg.sv vendor/pulp-platform/common_cells/src/cf_math_pkg.sv core/include/instr_tracer_pkg.sv core/cvxif_example/include/cvxif_instr_pkg.sv core/acc_dispatcher.sv corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv +core/cache_subsystem/cva6_hpdcache_wrapper.sv +core/cache_subsystem/cva6_hpdcache_subsystem.sv +core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv +core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv +core/cache_subsystem/cva6_hpdcache_if_adapter.sv +core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv +core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv +core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv +core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_req_arbiter.sv +core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_l15_resp_demux.sv +core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_to_l15.sv +core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv +core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv +core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv +core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv +core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv common/local/util/sram.sv +common/local/util/sram_cache.sv vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv @@ -60,8 +76,11 @@ vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv core/cache_subsystem/axi_adapter.sv core/alu.sv +core/alu_wrapper.sv core/fpu_wrap.sv corev_apu/src/ariane.sv +core/include/build_config_pkg.sv +core/cva6_rvfi_probes.sv core/cva6.sv core/branch_unit.sv core/compressed_decoder.sv @@ -72,6 +91,7 @@ core/decoder.sv core/ex_stage.sv core/frontend/btb.sv core/frontend/bht.sv +core/frontend/bht2lvl.sv core/frontend/ras.sv core/frontend/instr_scan.sv core/frontend/instr_queue.sv @@ -83,22 +103,21 @@ core/issue_stage.sv core/load_unit.sv core/load_store_unit.sv core/lsu_bypass.sv -core/mmu_sv39/mmu.sv -core/mmu_sv39x4/cva6_mmu_sv39x4.sv +core/cva6_mmu/cva6_shared_tlb.sv +core/cva6_mmu/cva6_mmu.sv core/mult.sv core/multiplier.sv core/serdiv.sv core/perf_counters.sv -core/mmu_sv39/ptw.sv -core/mmu_sv39x4/ptw_sv39x4.sv +core/cva6_mmu/cva6_ptw.sv core/ariane_regfile_ff.sv -core/re_name.sv core/scoreboard.sv +core/raw_checker.sv core/store_buffer.sv +core/cva6_fifo_v3.sv core/amo_buffer.sv core/store_unit.sv -core/mmu_sv39/tlb.sv -core/mmu_sv39x4/tlb_sv39x4.sv +core/cva6_mmu/cva6_tlb.sv core/commit_stage.sv core/cache_subsystem/wt_dcache_ctrl.sv core/cache_subsystem/wt_dcache_mem.sv @@ -112,7 +131,6 @@ core/cache_subsystem/wt_cache_subsystem.sv corev_apu/clint/clint.sv corev_apu/clint/axi_lite_interface.sv corev_apu/riscv-dbg/debug_rom/debug_rom.sv -corev_apu/riscv-dbg/src/dm_pkg.sv corev_apu/riscv-dbg/src/dm_csrs.sv corev_apu/riscv-dbg/src/dm_mem.sv corev_apu/riscv-dbg/src/dm_top.sv @@ -139,25 +157,38 @@ corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv corev_apu/register_interface/src/apb_to_reg.sv corev_apu/register_interface/src/reg_intf.sv -vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv -vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv -vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv -vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv -vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv -vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv -vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv -vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv -vendor/openhwgroup/cvfpu/src/fpnew_cast_multi.sv -vendor/openhwgroup/cvfpu/src/fpnew_classifier.sv -vendor/openhwgroup/cvfpu/src/fpnew_divsqrt_multi.sv -vendor/openhwgroup/cvfpu/src/fpnew_fma_multi.sv -vendor/openhwgroup/cvfpu/src/fpnew_fma.sv -vendor/openhwgroup/cvfpu/src/fpnew_noncomp.sv -vendor/openhwgroup/cvfpu/src/fpnew_opgroup_block.sv -vendor/openhwgroup/cvfpu/src/fpnew_opgroup_fmt_slice.sv -vendor/openhwgroup/cvfpu/src/fpnew_opgroup_multifmt_slice.sv -vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv -vendor/openhwgroup/cvfpu/src/fpnew_top.sv +core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv +core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv +core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv +core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv +core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv +core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv +core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv +core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv +core/cvfpu/src/fpnew_cast_multi.sv +core/cvfpu/src/fpnew_classifier.sv +core/cvfpu/src/fpnew_divsqrt_multi.sv +core/cvfpu/src/fpnew_divsqrt_th_64_multi.sv +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ctrl.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_double.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ff1.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_pack.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_prepare.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_round.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_scalar_dp.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_bound_table.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_with_sqrt.v +core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_top.v +core/cvfpu/src/fpnew_fma_multi.sv +core/cvfpu/src/fpnew_fma.sv +core/cvfpu/src/fpnew_noncomp.sv +core/cvfpu/src/fpnew_opgroup_block.sv +core/cvfpu/src/fpnew_opgroup_fmt_slice.sv +core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv +core/cvfpu/src/fpnew_rounding.sv +core/cvfpu/src/fpnew_top.sv core/pmp/src/pmp.sv core/pmp/src/pmp_entry.sv core/pmp/src/pmp_data_if.sv @@ -167,3 +198,5 @@ core/cvxif_example/instr_decoder.sv vendor/pulp-platform/common_cells/src/counter.sv vendor/pulp-platform/common_cells/src/delta_counter.sv core/cvxif_fu.sv +core/cvxif_issue_register_commit_if_driver.sv +core/cvxif_compressed_if_driver.sv diff --git a/Makefile b/Makefile index 915b2df775b..eff5f790801 100644 --- a/Makefile +++ b/Makefile @@ -167,9 +167,9 @@ src := $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv) $(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \ $(wildcard corev_apu/fpga/src/apb_timer/*.sv) \ $(wildcard corev_apu/fpga/src/axi_slice/src/*.sv) \ - $(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv) \ + $(wildcard vendor/pulp-platform/axi_riscv_atomics/src/*.sv) \ $(wildcard corev_apu/axi_mem_if/src/*.sv) \ - $(wildcard corev_apu/riscv-dbg/src/*.sv) \ + $(wildcard corev_apu/riscv-dbg/src/*.sv) \ corev_apu/rv_plic/rtl/rv_plic_target.sv \ corev_apu/rv_plic/rtl/rv_plic_gateway.sv \ corev_apu/rv_plic/rtl/plic_regmap.sv \ @@ -201,13 +201,34 @@ src := $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv) vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv \ vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv \ vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv \ + corev_apu/instr_tracing/ITI/include/iti_pkg.sv \ + corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv \ + corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv \ corev_apu/tb/ariane_testharness.sv \ corev_apu/tb/ariane_peripherals.sv \ corev_apu/tb/rvfi_tracer.sv \ corev_apu/tb/common/uart.sv \ corev_apu/tb/common/SimDTM.sv \ - corev_apu/tb/common/SimJTAG.sv - + corev_apu/tb/common/SimJTAG.sv \ + corev_apu/instr_tracing/ITI/cva6_iti/iti.sv \ + corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv \ + corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv \ + corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv \ + vendor/pulp-platform/common_cells/src/counter.sv \ + vendor/pulp-platform/common_cells/src/sync.sv \ + vendor/pulp-platform/common_cells/src/sync_wedge.sv \ + vendor/pulp-platform/common_cells/src/edge_detect.sv \ + corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv \ + corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv \ + corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv \ + corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv \ + corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv \ + corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv \ + corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv \ + corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv \ + vendor/pulp-platform/common_cells/src/fifo_v3.sv \ + corev_apu/instr_tracing/DPTI/slicer_DPTI.sv \ + corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv src := $(addprefix $(root-dir), $(src)) copro_src := core/cvxif_example/include/cvxif_instr_pkg.sv \ @@ -217,6 +238,9 @@ copro_src := $(addprefix $(root-dir), $(copro_src)) uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/vhdl_orig/*.vhd) uart_src := $(addprefix $(root-dir), $(uart_src)) +dpti_src := $(wildcard corev_apu/instr_tracing/DPTI/*.vhd) +dpti_src := $(addprefix $(root-dir), $(dpti_src)) + uart_src_sv:= corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv \ corev_apu/fpga/src/apb_uart/src/slib_counter.sv \ corev_apu/fpga/src/apb_uart/src/slib_edge_detect.sv \ @@ -279,7 +303,8 @@ xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag_t xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag.sv) src := $(filter-out $(xil_debug_filter), $(src)) -fpga_src := $(addprefix $(root-dir), $(fpga_src)) src/bootrom/bootrom_$(XLEN).sv +fpga_src += corev_apu/fpga/src/bootrom/bootrom_$(XLEN).sv +fpga_src := $(addprefix $(root-dir), $(fpga_src)) # look for testbenches tbs := $(top_level_path) corev_apu/tb/ariane_testharness.sv core/cva6_rvfi.sv @@ -287,7 +312,7 @@ tbs := $(top_level_path) corev_apu/tb/ariane_testharness.sv core/cva6_rvfi.sv tbs := $(addprefix $(root-dir), $(tbs)) # RISCV asm tests and benchmark setup (used for CI) -# there is a definesd test-list with selected CI tests +# there is a defined test-list with selected CI tests riscv-test-dir := tmp/riscv-tests/build/isa/ riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/ riscv-asm-tests-list := ci/riscv-asm-tests.list @@ -311,6 +336,9 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/ \ $(CVA6_REPO_DIR)/verif/tb/core/ \ $(CVA6_REPO_DIR)/core/include/ \ + $(HPDCACHE_DIR)/rtl/include \ + $(HPDCACHE_DIR)/rtl/src/utils/ecc \ + $(CVA6_REPO_DIR)/corev_apu/instr_tracing/ITI/include \ $(SPIKE_INSTALL_DIR)/include/disasm/ # Compile and sim flags @@ -507,6 +535,8 @@ XRUN_RUN_LOG ?= xrun_run.log CVA6_HOME ?= $(realpath -s $(root-dir)) XRUN_INCDIR :=+incdir+$(CVA6_HOME)/core/include \ + +incdir+$(HPDCACHE_DIR)/rtl/include \ + +incdir+$(HPDCACHE_DIR)/rtl/src/utils/ecc \ +incdir+$(CVA6_HOME)/vendor/pulp-platform/axi/include/ \ +incdir+$(CVA6_HOME)/corev_apu/register_interface/include @@ -780,12 +810,13 @@ fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/co fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv) fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv) -src/bootrom/bootrom_$(XLEN).sv: +$(addprefix $(root-dir), corev_apu/fpga/src/bootrom/bootrom_$(XLEN).sv): $(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) PLATFORM=$(PLATFORM) bootrom_$(XLEN).sv -fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist) +fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(dpti_src) $(src_flist) @echo "[FPGA] Generate sources" @echo read_vhdl {$(uart_src)} > corev_apu/fpga/scripts/add_sources.tcl + @echo read_vhdl {$(dpti_src)} >> corev_apu/fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(ariane_pkg)} >> corev_apu/fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(filter-out $(fpga_filter), $(src_flist))} >> corev_apu/fpga/scripts/add_sources.tcl @echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> corev_apu/fpga/scripts/add_sources.tcl diff --git a/README.md b/README.md index 6e8c9e54bd8..cf49306f4af 100644 --- a/README.md +++ b/README.md @@ -1,9 +1,17 @@ -# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/) [![Documentation Status](https://readthedocs.com/projects/openhw-group-cva6-user-manual/badge/?version=latest)](https://docs.openhwgroup.org/projects/cva6-user-manual/?badge=latest) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=&sort=semver&color=blue)](https://github.com/openhwgroup/cva6/releases/) +# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge_master.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_cva6.html) [![Documentation Status](https://readthedocs.com/projects/openhw-group-cva6-user-manual/badge/?version=latest)](https://docs.openhwgroup.org/projects/cva6-user-manual/?badge=latest) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=&sort=semver&color=blue)](https://github.com/openhwgroup/cva6/releases/) + +> [!IMPORTANT] +> This ``master`` branch is protected and does not accept new pull requests. It is kept online for users who want to continue integrating legacy versions. Please direct new contributions to the ``main`` branch, which has become the default CVA6 branch. CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13. It has a configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length. +The CVA6 core is part of a vivid ecosystem. In [this document](RESOURCES.md), we gather pointers to this ecosystem (building blocks, designs, partners...). + +A performance model of CVA6 is available in the `perf-model/` folder of this repository. +It can be used to investigate performance-related micro-architecture changes. + @@ -56,403 +64,15 @@ export DV_SIMULATORS=veri-testharness,spike bash verif/regress/smoke-tests.sh ``` -# Running standalone simulations - -Simulating the CVA6 is done by using `verif/sim/cva6.py`. - -The environment variable `DV_SIMULATORS` allows you to specify which simulator to use. - -Four simulation types are supported: -- **veri-testharness**: verilator with corev_apu/testharness testbench -- **vcs-testharness**: vcs with corev_apu/testharness testbench -- **vcs-uvm**: vcs with UVM testbench -- **Spike** ISS - -You can set several simulators, such as : - -```sh -export DV_SIMULATORS=veri-testharness,vcs-testharness,vcs_uvm -``` - -If exactly 2 simulators are given, their trace is compared ([see the Regression tests section](#running-regression-tests-simulations)). - -Here is how you can run the hello world C program with the Verilator model: - -```sh -# Make sure to source this script from the root directory -# to correctly set the environment variables related to the tools -source verif/sim/setup-env.sh - -# Set the NUM_JOBS variable to increase the number of parallel make jobs -# export NUM_JOBS= - -export DV_SIMULATORS=veri-testharness - -cd ./verif/sim - -python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml \ ---c_tests ../tests/custom/hello_world/hello_world.c \ ---linker=../../config/gen_from_riscv_config/linker/link.ld \ ---gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib \ --nostartfiles -g ../tests/custom/common/syscalls.c \ -../tests/custom/common/crt.S -lgcc \ --I../tests/custom/env -I../tests/custom/common" -``` - -You can run either assembly programs (check `verif/test/custom/hello_world/custom_test_template.S`) or C programs. Run `python3 cva6.py --help` to have more informations on the available parameters. - -## Simulating with VCS and Verdi - -You can set the environment variable `VERDI` as such if you want to launch Verdi while simulating with VCS: - -```sh -export VERDI=1 -``` - - -# Running regression tests simulations - -The smoke-tests script installs a random instruction generator and several tests suites: -- [riscv-dv](https://github.com/chipsalliance/riscv-dv) -- [riscv-compliance](https://github.com/lowRISC/riscv-compliance) -- [riscv-tests](https://github.com/riscv-software-src/riscv-tests) -- [riscv-arch-test](https://github.com/riscv-non-isa/riscv-arch-test) - - -The regression tests are done by comparing a model simulation trace with the Spike trace. - -Several tests scripts can be found in `./verif/regress` - -For example, here is how would run the riscv-arch-test regression test suite with the Verilator model: - -```sh -export DV_SIMULATORS=veri-testharness,spike -bash verif/regress/dv-riscv-arch-test.sh -``` - - -# Logs - -The logs from cva6.py are located in `./verif/sim/out_YEAR-MONTH-DAY`. - -Assuming you ran the smoke-tests scripts in the previous step, here is the log directory hierarchy: - -- **directed_asm_tests/**: The compiled (to .o then .bin) assembly tests -- **directed_c_tests/**: The compiled (to .o then .bin) c tests -- **spike_sim/**: Spike simulation log and trace files -- **veri_testharness_sim**: Verilator simulation log and trace files -- **iss_regr.log**: The regression test log - -The regression test log summarizes the comparison between the simulator trace and the Spike trace. Beware that a if a test fails before the comparison step, it will not appear in this log, check the output of cva6.py and the logs of the simulation instead. - - -# Waveform generation - -Waveform generation is currently supported for Verilator (`veri-testharness`) -and VCS with full UVM testbench (`vcs-uvm`) simulation types. It is disabled -by default to save simulation time and storage space. - -To enable waveform generation for a supported simulation mode, set either -of the two shell variables that control tracing before running any of the -test scripts under `verif/regress`: -- `export TRACE_FAST=1` enables "fast" waveform generation (keep simulation - time low at the expense of space). This will produce VCD files when using - Verilator, and VPD files when using Synopsys VCS with UVM testbench (`vcs-uvm`). -- `export TRACE_COMPACT=1` enables "compact" waveform generation (keep waveform - files smaller at the expense of increased simulation time). This will - produce FST files when using Verilator, and FSDB files when using Synopsys - VCS with UVM testbench (`vcs-uvm`). - -To generate VCD waveforms of the `smoke-tests` regression suite using Verilator, use: -```sh -export DV_SIMULATORS=veri-testharness,spike -export TRACE_FAST=1 -bash verif/regress/smoke-tests-.sh -``` - -Where `` is one of the following, depending on the CPU variant you want to use. -- `cv32a65x`. -- `cv32a6_imac_sv32`. -- `cv64a6_imafdc_sv39`. - -After each simulation run involving Verilator or VCS, the generated waveforms -will be copied to the directory containing the log files (see above,) with -the name of the current HW configuration added to the file name right before -the file type suffix (e.g., `I-ADD-01.cv32a60x.vcd`). - - -# Physical Implementation - -## ASIC Synthesis - -How to make cva6 synthesis ? -``` -make -C pd/synth cva6_synth FOUNDRY_PATH=/your/techno/basepath/ TECH_NAME=yourTechnoName TARGET_LIBRARY_FILES="yourLib1.db\ yourLib2.db" PERIOD=10 NAND2_AREA=650 TARGET=cv64a6_imafdc_sv39 ADDITIONAL_SEARCH_PATH="others/libs/paths/one\ others/libs/paths/two" -``` -Don't forget to escape spaces in lists. -Reports are under: pd/synth/ariane/reports - - -## ASIC Gate Simulation with `core-v-verif` repository - -> :warning: **Warning**: this chapter needs to be updated. See Github issue https://github.com/openhwgroup/cva6/issues/1358. - -```sh -export DV_SIMULATORS=veri-testharness,spike -cva6/regress/smoke-tests.sh -make -C pd/synth cva6_synth FOUNDRY_PATH=/your/techno/basepath/ TECH_NAME=yourTechnoName TARGET_LIBRARY_FILES="yourLib1.db\ yourLib2.db" PERIOD=10 NAND2_AREA=650 TARGET=cv64a6_imafdc_sv39 ADDITIONAL_SEARCH_PATH="others/libs/paths/one\ others/libs/paths/two" -sed 's/module SyncSpRamBeNx64_1/module SyncSpRamBeNx64_2/' pd/synth/ariane_synth.v > pd/synth/ariane_synth_modified.v -cd cva6/sim -make vcs_clean -python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-ld --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=spike,vcs-core-gate $DV_OPTS -``` - - -# COREV-APU FPGA Emulation - -We currently provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual) and the [Agilex 7 Development Kit](https://www.intel.la/content/www/xl/es/products/details/fpga/development-kits/agilex/agf014.html). - -- **Genesys 2** - - We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/openhwgroup/cva6/releases). - - Tested on Vivado 2018.2. The FPGA currently contains the following peripherals: - - - DDR3 memory controller - - SPI controller to conncet to an SDCard - - Ethernet controller - - JTAG port (see debugging section below) - - Bootrom containing zero stage bootloader and device tree. - - UART - - GPIOs connected to LEDs - -> The ethernet controller and the corresponding network connection is still work in progress and not functional at the moment. Expect some updates soon-ish. - -- **Agilex 7** - - Tested on Quartus Prime Version 24.1.0 Pro Edition. The FPGA currently contains the following peripherals: - - - DDR4 memory controller - - JTAG port (see debugging section below) - - Bootrom containing zero stage bootloader - - UART - - GPIOs connected to LEDs - -> The ethernet controller and the corresponding network connection, as well as the SD Card connection and the capability to boot linux are still work in progress and not functional at the moment. Expect some updates soon-ish. - - -## Programming the Memory Configuration File or bitstream - -- **Genesys 2** - - - Open Vivado - - Open the hardware manager and open the target board (Genesys II - `xc7k325t`) - - Tools - Add Configuration Memory Device - - Select the following Spansion SPI flash `s25fl256xxxxxx0` - - Add `ariane_xilinx.mcs` - - Press Ok. Flashing will take a couple of minutes. - - Right click on the FPGA device - Boot from Configuration Memory Device (or press the program button on the FPGA) - -- **Agilex 7** - - - Open Quartus programmer - - Configure HW Setup by selecting the AGF FPGA Development Kit - - Click Auto-Detect to scan the JTAG chain - - In the device list, right click over device AGFB014R24B and add file (.sof) - - Click on Start button to program the FPGA - - Right now only baremetal is supported, so right after programming you can connect to the UART and see your CVA6 alive on Agilex! - - For this you need to use the JTAG UART provided with Quartus installation - -``` -.$quartus_installation_path/qprogrammer/quartus/bin/juart-terminal -juart-terminal: connected to hardware target using JTAG UART on cable -juart-terminal: "AGF FPGA Development Kit [1-3]", device 1, instance 0 -juart-terminal: (Use the IDE stop button or Ctrl-C to terminate) - -Hello World! -``` - -## Preparing the SD Card - -The first stage bootloader will boot from SD Card by default. Get yourself a suitable SD Card (we use [this](https://www.amazon.com/Kingston-Digital-Mobility-MBLY10G2-32GB/dp/B00519BEQO) one). Either grab a pre-built Linux image from [here](https://github.com/pulp-platform/ariane-sdk/releases) or generate the Linux image yourself following the README in the [ariane-sdk repository](https://github.com/pulp-platform/ariane-sdk). Prepare the SD Card by following the "Booting from SD card" section in the ariane-sdk repository. - -Connect a terminal to the USB serial device opened by the FTDI chip e.g.: -``` -screen /dev/ttyUSB0 115200 -``` - -Default baudrate set by the bootlaoder and Linux is `115200`. - -After you've inserted the SD Card and programmed the FPGA you can connect to the serial port of the FPGA and should see the bootloader and afterwards Linux booting. Default username is `root`, no password required. - -## Generating a Bitstream - -- **Genesys 2** - -To generate the FPGA bitstream (and memory configuration) yourself for the Genesys II board run: - -``` -make fpga -``` +# Tutorials -This will produce a bitstream file and memory configuration file (in `fpga/work-fpga`) which you can permanently flash by running the above commands. - -- **Agilex 7** - -To generate the FPGA bitstream yourself for the Agilex 7 board run: - -``` -make altera -``` - -We recommend to set the parameter FpgaAlteraEn (and also FpgaEn) to benefit from the FPGA optimizations. - -This will produce a bitstream file (in `altera/output_files`) which you can program following the previous instructions. **Note: Bear in mind that you need a Quartus Pro Licence to be able to generate this bitstream** - -To clean the project after generating the bitstream, use - -``` -make clean-altera -``` - -## Debugging - -- **Genesys 2** -You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD below. - -To get started, connect the micro USB port that is labeled with JTAG to your machine. This port is attached to the FTDI 2232 USB-to-serial chip on the Genesys 2 board, and is usually used to access the native JTAG interface of the Kintex-7 FPGA (e.g. to program the device using Vivado). However, the FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module. - ->If you are on an Ubuntu based system you need to add the following udev rule to `/etc/udev/rules.d/99-ftdi.rules` ->``` -> SUBSYSTEM=="usb", ACTION=="add", ATTRS{idProduct}=="6010", ATTRS{idVendor}=="0403", MODE="664", GROUP="plugdev" ->``` - -Once attached to your system, the FTDI chip should be listed when you type `lsusb`: - -``` -Bus 005 Device 019: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC -``` +* **[Running Simulations](tutorials/running_sim.md)** +* **[ASIC Implementation](tutorials/asic.md)** +* **[FPGA Implementation and running an OS](tutorials/fpga.md)** +* **[Instruction Tracing](corev_apu/instr_tracing/README.md)** -If this is the case, you can go on and start openocd with the `fpga/ariane.cfg` configuration file: - -``` -openocd -f fpga/ariane.cfg - -Open On-Chip Debugger 0.10.0+dev-00195-g933cb87 (2018-09-14-19:32) -Licensed under GNU GPL v2 -For bug reports, read - http://openocd.org/doc/doxygen/bugs.html -adapter speed: 1000 kHz -Info : auto-selecting first available session transport "jtag". To override use 'transport select '. -Info : clock speed 1000 kHz -Info : TAP riscv.cpu does not have IDCODE -Info : datacount=2 progbufsize=8 -Info : Examined RISC-V core; found 1 harts -Info : hart 0: XLEN=64, misa=0x8000000000141105 -Info : Listening on port 3333 for gdb connections -Ready for Remote Connections -Info : Listening on port 6666 for tcl connections -Info : Listening on port 4444 for telnet connections -Info : accepting 'gdb' connection on tcp/3333 -``` -- **Agilex 7** - -You can debug (and program) the FPGA using a modified version of OpenOCD included with Quartus installation ($quartus_installation_path/qprogrammer/quartus/bin/openocd). - -To get started, connect the micro USB port that is labeled with J13 to your machine. It is the same port that is used for the UART. Both use the JTAG interface and connect to the System Level Debugging (SLD) Hub instantiated inside the FPGA. Then the debugger connection goes to the virtual JTAG IP (vJTAG) which can be accessed with the modified version of OpenOCD. - -You can start openocd with the `altera/cva6.cfg` configuration file: - -``` -./$quartus_installation_path/qprogrammer/quartus/bin/openocd -f altera/cva6.cfg -Open On-Chip Debugger 0.11.0-R22.4 -Licensed under GNU GPL v2 -For bug reports, read - http://openocd.org/doc/doxygen/bugs.html -Info : only one transport option; autoselect 'jtag' -Info : Application name is OpenOCD.20241016093010 -Info : No cable specified, so will be searching for cables - -Info : At present, The first hardware cable will be used [1 cable(s) detected] -Info : Cable 1: device_name=(null), hw_name=AGF FPGA Development Kit, server=(null), port=1-3, chain_id=0x559319c8cde0, persistent_id=1, chain_type=1, features=34816, server_version_info=Version 24.1.0 Build 115 03/21/2024 SC Pro Edition -Info : TAP position 0 (C341A0DD) has 3 SLD nodes -Info : node 0 idcode=00406E00 position_n=0 -Info : node 1 idcode=30006E00 position_n=0 -Info : node 2 idcode=0C006E00 position_n=0 -Info : TAP position 1 (20D10DD) has 1 SLD nodes -Info : node 0 idcode=0C206E00 position_n=0 -Info : Discovered 2 TAP devices -Info : Detected device (tap_position=0) device_id=c341a0dd, instruction_length=10, features=12, device_name=AGFB014R24A(.|R1|R2)/.. -Info : Found an Intel device at tap_position 0.Currently assuming it is SLD Hub -Info : Detected device (tap_position=1) device_id=020d10dd, instruction_length=10, features=4, device_name=VTAP10 -Info : Found an Intel device at tap_position 1.Currently assuming it is SLD Hub -Info : This adapter doesn't support configurable speed -Info : JTAG tap: agilex7.fpga.tap tap/device found: 0xc341a0dd (mfg: 0x06e (Altera), part: 0x341a, ver: 0xc) -Info : JTAG tap: auto0.tap tap/device found: 0x020d10dd (mfg: 0x06e (Altera), part: 0x20d1, ver: 0x0) -Info : JTAG tap: agilex7.fpga.tap Parent Tap found: 0xc341a0dd (mfg: 0x06e (Altera), part: 0x341a, ver: 0xc) -Info : Virtual Tap/SLD node 0x00406E00 found at tap position 0 vtap position 0 -Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 10 -expected-id 0x020d10dd" -Info : datacount=2 progbufsize=8 -Info : Examined RISC-V core; found 1 harts -Info : hart 0: XLEN=32, misa=0x40141107 -Info : starting gdb server for agilex7.cva6.0 on 3333 -Info : Listening on port 3333 for gdb connections -Ready for Remote Connections -Info : Listening on port 6666 for tcl connections -Info : Listening on port 4444 for telnet connections -``` - -- **Common for both boards** - -Then you will be able to either connect through `telnet` or with `gdb`: - -``` -riscv64-unknown-elf-gdb /path/to/elf - -(gdb) target remote localhost:3333 -(gdb) load -Loading section .text, size 0x6508 lma 0x80000000 -Loading section .rodata, size 0x900 lma 0x80006508 -(gdb) b putchar -(gdb) c -Continuing. - -Program received signal SIGTRAP, Trace/breakpoint trap. -0x0000000080009126 in putchar (s=72) at lib/qprintf.c:69 -69 uart_sendchar(s); -(gdb) si -0x000000008000912a 69 uart_sendchar(s); -(gdb) p/x $mepc -$1 = 0xfffffffffffdb5ee -``` - -You can read or write device memory by using: -``` -(gdb) x/i 0x1000 - 0x1000: lui t0,0x4 -(gdb) set {int} 0x1000 = 22 -(gdb) set $pc = 0x1000 -``` - - -## Preliminary Support for OpenPiton Cache System - -CVA6 has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/wt_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics. - -The corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the `README` in that repository to see how to use CVA6 in the OpenPiton setting. - -To activate the different cache system, compile your code with the macro `DCACHE_TYPE`. - - -## Re-generating the Bootcode (ZSBL) - -The zero stage bootloader (ZSBL) for RTL simulation lives in `bootrom/` while the bootcode for the FPGA is in `fpga/src/bootrom`. The RTL bootcode simply jumps to the base of the DRAM where the FSBL takes over. For the FPGA the ZSBL performs additional housekeeping. Both bootloader pass the hartid as well as address to the device tree in argumen register `a0` and `a1` respectively. - -To re-generate the bootcode you can use the existing makefile within those directories. To generate the SystemVerilog files you will need the `bitstring` python package installed on your system. - - -# Directory Structure: +# Directory Structure The directory structure separates the [CVA6 RISC-V CPU](#cva6-risc-v-cpu) core from the [CORE-V-APU FPGA Emulation Platform](#corev-apu-fpga-emulation). Files, directories and submodules under `cva6` are for the core _only_ and should not have any dependencies on the APU. @@ -480,21 +100,17 @@ This BSP is used by both `core` testbench and `uvmt_cva6` UVM verification envir - **tb**: testbench module instancing the core - **tests**: source of test cases and test lists -# Planned Improvements - -Go to the CVA6 Kanban Board which also loosely tracks planned improvements. - # Contributing We highly appreciate community contributions. -

To ease the work of reviewing contributions, please review [CONTRIBUTING](CONTRIBUTING.md). - +To ease the work of reviewing contributions, please review [CONTRIBUTING](CONTRIBUTING.md). -# Issues and Troubleshooting +Contributions to the documentation (`docs/` and `tutorials/` directories) are very welcome as well. If you find any problems or issues with CVA6 or the documentation, please check out the [issue tracker](https://github.com/openhwgroup/cva6/issues) -and create a new issue if your problem is not yet tracked. +and create a new issue if your problem is not yet tracked. \ +[The CVA6 Kanban Board](https://github.com/orgs/openhwgroup/project/3/view/7) loosely tracks planned improvements. # Publication @@ -503,7 +119,7 @@ If you use CVA6 in your academic work you can cite us:
CVA6 Publication -

+ ``` @article{zaruba2019cost, author={F. {Zaruba} and L. {Benini}}, @@ -518,15 +134,11 @@ If you use CVA6 in your academic work you can cite us: month={Nov}, } ``` -

-
-
- -# Resources and Ecosystem - -The CVA6 core is part of a vivid ecosystem. In [this document](RESOURCES.md), we gather pointers to this ecosystem (building blocks, designs, partners...) + # Acknowledgements Check out the [acknowledgements](ACKNOWLEDGEMENTS.md). + + diff --git a/RESOURCES.md b/RESOURCES.md index 659c7c48c9d..3272f27f8f3 100644 --- a/RESOURCES.md +++ b/RESOURCES.md @@ -9,7 +9,7 @@ Please help improve this page, by filing an [issue](https://github.com/openhwgro > Resources that reach the TRL-5 maturity (ready to integrate into productions ICs) are clearly mentioned. > Otherwise, you can assume a TRL-4 maturity. -> [!WARNING] +> [!WARNING] > The CVA6 team is not liable for the other repositories. > Assess their content and make sure they fit your needs and are mature enough for your design. > Plese direct your issues or pull requests to these external repositories. @@ -70,6 +70,8 @@ The [technical kits](https://github.com/thalesgroup/cva6-softcore-contest) of a **[CVA6 with Xilinx Ethernet](https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet/)** is an alternative design which implements Xilinx 1G/2.5G Ethernet Subsystem on the Digilent Genesys 2 FPGA board. It has been tested with TFTP boot in u-boot and SSH in Linux. +**[CVA6-MPSoC](https://github.com/NicolasDerumigny/cva6)** is an alternative design for AMD PYNQ-Z2 and ZCU104 boards, which optionnally includes Xilinx 1G/2.5G Ethernet Subsystem and an experimental dual-core, shared-L1 configuration. It has been tested to boot to Linux 6.6 through u-boot. + ### Platforms, subsystems and systems These are large subsystems and systems that are more complex than the "APU". They can be a starting point for your design: diff --git a/SECURITY.md b/SECURITY.md new file mode 100644 index 00000000000..7c46cccd358 --- /dev/null +++ b/SECURITY.md @@ -0,0 +1,14 @@ +# CVA6 Security Policy + +## Reporting a Vulnerability + +If you think you have found a vulnerability in a specific configuration of the CVA6 you can report it using one of the following ways: + +* Contact the [Eclipse Foundation Security Team](mailto:security@eclipse-foundation.org) +* [Report a Vulnerability](https://github.com/openhwgroup/cva6/security/advisories/new) + +You can find more information about reporting and disclosure at the [Eclipse Foundation Security page](https://www.eclipse.org/security/). + +## Security Policy + +This project follows [Eclipse Foundation Vulnerability Reporting Policy](https://www.eclipse.org/security/policy/). diff --git a/ci/install-prereq.sh b/ci/install-prereq.sh index 0f99c37f57f..5b58291f9a9 100644 --- a/ci/install-prereq.sh +++ b/ci/install-prereq.sh @@ -1,8 +1,4 @@ #!/bin/bash -echo 'deb http://download.opensuse.org/repositories/home:/phiwag:/edatools/xUbuntu_20.04/ /' | sudo tee /etc/apt/sources.list.d/home:phiwag:edatools.list -curl -fsSL https://download.opensuse.org/repositories/home:phiwag:edatools/Debian_Unstable/Release.key | gpg --dearmor | sudo tee /etc/apt/trusted.gpg.d/home_phiwag_edatools.gpg > /dev/null - sudo apt update sudo apt install device-tree-compiler libfl-dev help2man - diff --git a/common/local/util/hpdcache_sram_1rw.sv b/common/local/util/hpdcache_sram_1rw.sv index 7893a4bad14..5bc12be96e1 100644 --- a/common/local/util/hpdcache_sram_1rw.sv +++ b/common/local/util/hpdcache_sram_1rw.sv @@ -12,22 +12,23 @@ module hpdcache_sram_1rw #( parameter int unsigned ADDR_SIZE = 0, parameter int unsigned DATA_SIZE = 0, - parameter int unsigned DEPTH = 2**ADDR_SIZE + parameter int unsigned DEPTH = 2**ADDR_SIZE, + parameter int unsigned NDATA = 1 ) ( - input logic clk, - input logic rst_n, - input logic cs, - input logic we, - input logic [ADDR_SIZE-1:0] addr, - input logic [DATA_SIZE-1:0] wdata, - output logic [DATA_SIZE-1:0] rdata + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [NDATA-1:0][DATA_SIZE-1:0] wdata, + output logic [NDATA-1:0][DATA_SIZE-1:0] rdata ); SyncSpRam #( .ADDR_WIDTH(ADDR_SIZE), .DATA_DEPTH(DEPTH), // usually 2**ADDR_WIDTH, but can be lower - .DATA_WIDTH(DATA_SIZE), + .DATA_WIDTH(NDATA*DATA_SIZE), .OUT_REGS (0), .SIM_INIT (1) // for simulation only, will not be synthesized // 0: no init, 1: zero init, 2: random init diff --git a/common/local/util/hpdcache_sram_wbyteenable_1rw.sv b/common/local/util/hpdcache_sram_wbyteenable_1rw.sv index d9f29961014..4c5641347fb 100644 --- a/common/local/util/hpdcache_sram_wbyteenable_1rw.sv +++ b/common/local/util/hpdcache_sram_wbyteenable_1rw.sv @@ -12,28 +12,28 @@ module hpdcache_sram_wbyteenable_1rw #( parameter int unsigned ADDR_SIZE = 0, parameter int unsigned DATA_SIZE = 0, - parameter int unsigned DEPTH = 2**ADDR_SIZE + parameter int unsigned DEPTH = 2**ADDR_SIZE, + parameter int unsigned NDATA = 1 ) ( - input logic clk, - input logic rst_n, - input logic cs, - input logic we, - input logic [ADDR_SIZE-1:0] addr, - input logic [DATA_SIZE-1:0] wdata, - input logic [DATA_SIZE/8-1:0] wbyteenable, - output logic [DATA_SIZE-1:0] rdata + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [NDATA-1:0][DATA_SIZE-1:0] wdata, + input logic [NDATA-1:0][DATA_SIZE/8-1:0] wbyteenable, + output logic [NDATA-1:0][DATA_SIZE-1:0] rdata ); -if (DATA_SIZE == 128) begin - // Découpage des données en deux moitiés de 64 bits - logic [DATA_SIZE/2-1:0] wdata_low, wdata_high; - logic [DATA_SIZE/2-1:0] rdata_low, rdata_high; - logic [7:0] be_low, be_high; - assign wdata_low = wdata[63:0]; - assign wdata_high = wdata[127:64]; - assign be_low = wbyteenable[7:0]; - assign be_high = wbyteenable[15:8]; +if (NDATA*DATA_SIZE == 128) begin + // split in two 64-bits wide SRAMs + logic [127:0] __wdata; + logic [127:0] __rdata; + logic [15:0] __be; + + assign __wdata = wdata; + assign __be = wbyteenable; SyncSpRamBeNx64 #( .ADDR_WIDTH(ADDR_SIZE), @@ -44,11 +44,11 @@ if (DATA_SIZE == 128) begin .Clk_CI (clk), .Rst_RBI (rst_n), .CSel_SI (cs), - .WrEn_SI (we), // Ecriture sur la banque basse - .BEn_SI (be_low), + .WrEn_SI (we), + .BEn_SI (__be[0 +: 8]), // write LSBs .Addr_DI (addr), - .WrData_DI(wdata_low), - .RdData_DO(rdata_low) + .WrData_DI(__wdata[0 +: 64]), + .RdData_DO(__rdata[0 +: 64]) ); SyncSpRamBeNx64 #( @@ -60,16 +60,16 @@ if (DATA_SIZE == 128) begin .Clk_CI (clk), .Rst_RBI (rst_n), .CSel_SI (cs), - .WrEn_SI (we), // Ecriture sur la banque haute - .BEn_SI (be_high), + .WrEn_SI (we), + .BEn_SI (__be[8 +: 8]), // write MSbs .Addr_DI (addr), - .WrData_DI(wdata_high), - .RdData_DO(rdata_high) + .WrData_DI(__wdata[64 +: 64]), + .RdData_DO(__rdata[64 +: 64]) ); - assign rdata = {rdata_high, rdata_low}; + assign rdata = __rdata; -end else if (DATA_SIZE == 64) begin +end else if (NDATA*DATA_SIZE == 64) begin SyncSpRamBeNx64 #( .ADDR_WIDTH(ADDR_SIZE), .DATA_DEPTH(DEPTH), // usually 2**ADDR_WIDTH, but can be lower @@ -87,7 +87,7 @@ end else if (DATA_SIZE == 64) begin .WrData_DI(wdata), .RdData_DO(rdata) ); -end else if (DATA_SIZE == 32) begin +end else if (NDATA*DATA_SIZE == 32) begin SyncSpRamBeNx32 #( .ADDR_WIDTH(ADDR_SIZE), .DATA_DEPTH(DEPTH), // usually 2**ADDR_WIDTH, but can be lower @@ -107,7 +107,7 @@ end else if (DATA_SIZE == 32) begin ); end else begin - $fatal(1, "DATASIZE=%d, in not supported " ,DATA_SIZE); + $fatal(1, "DATASIZE=%d, in not supported", NDATA*DATA_SIZE); end diff --git a/common/local/util/instr_trace_item.svh b/common/local/util/instr_trace_item.svh index c1ea36e2977..7bcbdc3dda0 100644 --- a/common/local/util/instr_trace_item.svh +++ b/common/local/util/instr_trace_item.svh @@ -41,6 +41,8 @@ class instr_trace_item #( logic result_fpr [$]; logic [63:0] imm; logic [63:0] result; + logic dest_we_valid; + logic dest_is_fp; logic [CVA6Cfg.PLEN-1:0] paddr; string priv_lvl; bp_resolve_t bp; @@ -49,7 +51,7 @@ class instr_trace_item #( // constructor creating a new instruction trace item, e.g.: a single instruction with all relevant information function new (time simtime, longint unsigned cycle, scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32], - logic [63:0] fp_reg_file [32], logic [63:0] result, logic [CVA6Cfg.PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp); + logic [63:0] fp_reg_file [32], logic [63:0] result, logic dest_we_valid, logic dest_is_fp, logic [CVA6Cfg.PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp); this.simtime = simtime; this.cycle = cycle; this.pc = sbe.pc; @@ -57,6 +59,8 @@ class instr_trace_item #( this.gp_reg_file = gp_reg_file; this.fp_reg_file = fp_reg_file; this.result = result; + this.dest_we_valid = dest_we_valid; + this.dest_is_fp = dest_is_fp; this.paddr = paddr; this.bp = bp; this.priv_lvl = (debug_mode) ? "D" : getPrivLevel(priv_lvl); @@ -195,6 +199,68 @@ class instr_trace_item #( endcase endfunction + function logic scoreboardDestIsFp(); + if (sbe.fu inside {ariane_pkg::FPU, ariane_pkg::FPU_VEC}) begin + return ariane_pkg::fd_changes_rd_state(sbe.op); + end + return ariane_pkg::is_rd_fpr(sbe.op); + endfunction + + function logic rawDestIsFp(); + if (dest_we_valid) begin + return dest_is_fp; + end + return scoreboardDestIsFp(); + endfunction + + function logic fpInstrForcesGprDest(); + logic [6:0] opcode = instr[6:0]; + logic [4:0] funct5 = instr[31:27]; + logic [2:0] rm = instr[14:12]; + + if (opcode == riscv::OpcodeOpFp) begin + if (funct5 == 5'b11000) begin + // fcvt.*.* instructions that target an integer register + return 1'b1; + end + + if (funct5 == 5'b10100) begin + // fle.*, flt.*, feq.* comparisons produce integer results. + return 1'b1; + end + + if (funct5 == 5'b11100) begin + // fmv.x.* (rm == 000) and fclass (rm == 001) always write GPRs. + if ((rm == 3'b000) || (rm == 3'b001)) begin + return 1'b1; + end + // Alternate encodings when FP16ALT is enabled mirror rm encodings. + if (CVA6Cfg.XF16ALT && ((rm == 3'b100) || (rm == 3'b101))) begin + return 1'b1; + end + end + end + + return 1'b0; + endfunction + + function logic effectiveDestIsFp(); + logic dest_is_fp_raw = rawDestIsFp(); + + if (fpInstrForcesGprDest()) begin + return 1'b0; + end + + return dest_is_fp_raw; + endfunction + + function void adjustResultRegKinds(); + logic final_dest_is_fp = effectiveDestIsFp(); + foreach (result_fpr[i]) begin + result_fpr[i] = final_dest_is_fp; + end + endfunction + function string printInstr(); string s; @@ -379,6 +445,8 @@ class instr_trace_item #( // instr, // s); + adjustResultRegKinds(); + foreach (result_regs[i]) begin if (result_fpr[i]) s = $sformatf("%s %-4s:%16x", s, fpRegAddrToStr(result_regs[i]), this.result); @@ -466,45 +534,48 @@ class instr_trace_item #( function string printRFBCInstr(input string mnemonic, input bit use_rnd); + logic dest_fp = effectiveDestIsFp(); result_regs.push_back(rd); - result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); + result_fpr.push_back(dest_fp); read_regs.push_back(rs2); read_fpr.push_back(ariane_pkg::is_rs2_fpr(sbe.op)); read_regs.push_back(sbe.result[4:0]); read_fpr.push_back(ariane_pkg::is_imm_fpr(sbe.op)); if (use_rnd && instr[14:12]!=3'b111) - return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0]), fpRmToStr(instr[14:12])); + return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0]), fpRmToStr(instr[14:12])); else - return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0])); + return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0])); endfunction // printRFInstr function string printRFInstr(input string mnemonic, input bit use_rnd); + logic dest_fp = effectiveDestIsFp(); result_regs.push_back(rd); - result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); + result_fpr.push_back(dest_fp); read_regs.push_back(rs1); read_fpr.push_back(ariane_pkg::is_rs1_fpr(sbe.op)); read_regs.push_back(rs2); read_fpr.push_back(ariane_pkg::is_rs2_fpr(sbe.op)); if (use_rnd && instr[14:12]!=3'b111) - return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), fpRmToStr(instr[14:12])); + return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), fpRmToStr(instr[14:12])); else - return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2)); + return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2)); endfunction // printRFInstr function string printRFInstr1Op(input string mnemonic, input bit use_rnd); + logic dest_fp = effectiveDestIsFp(); result_regs.push_back(rd); - result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); + result_fpr.push_back(dest_fp); read_regs.push_back(rs1); read_fpr.push_back(ariane_pkg::is_rs1_fpr(sbe.op)); if (use_rnd && instr[14:12]!=3'b111) - return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), fpRmToStr(instr[14:12])); + return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), fpRmToStr(instr[14:12])); else - return $sformatf("%-12s %4s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1)); + return $sformatf("%-12s %4s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1)); endfunction // printRFInstr1Op function string printR4Instr(input string mnemonic); @@ -523,8 +594,9 @@ class instr_trace_item #( function string printFpSpecialInstr(); + logic dest_fp = effectiveDestIsFp(); result_regs.push_back(rd); - result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); + result_fpr.push_back(dest_fp); read_regs.push_back(rs1); read_fpr.push_back(ariane_pkg::is_rs1_fpr(sbe.op)); @@ -634,8 +706,9 @@ class instr_trace_item #( endfunction // printCSRInstr function string printLoadInstr(input string mnemonic); + logic dest_fp = effectiveDestIsFp(); result_regs.push_back(rd); - result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op)); + result_fpr.push_back(dest_fp); read_regs.push_back(rs1); read_fpr.push_back(1'b0); // save the immediate for calculating the virtual address diff --git a/common/local/util/instr_tracer.sv b/common/local/util/instr_tracer.sv index 9083664069d..dad2f29ceb7 100644 --- a/common/local/util/instr_tracer.sv +++ b/common/local/util/instr_tracer.sv @@ -25,32 +25,33 @@ module instr_tracer #( parameter type exception_t = logic, parameter interrupts_t INTERRUPTS = '0 )( - input logic pck, - input logic rstn, - input logic flush_unissued, - input logic flush_all, - input logic [31:0] instruction, - input logic fetch_valid, - input logic fetch_ack, - input logic issue_ack, // issue acknowledged - input scoreboard_entry_t issue_sbe, // issue scoreboard entry - input logic [1:0][4:0] waddr, // WB stage - input logic [1:0][63:0] wdata, - input logic [1:0] we_gpr, - input logic [1:0] we_fpr, - input scoreboard_entry_t [1:0] commit_instr, // commit instruction - input logic [1:0] commit_ack, - input logic st_valid, // stores - address translation - input logic [CVA6Cfg.PLEN-1:0] st_paddr, - input logic ld_valid, // loads - input logic ld_kill, - input logic [CVA6Cfg.PLEN-1:0] ld_paddr, - input bp_resolve_t resolve_branch, // misprediction - input exception_t commit_exception, - input riscv::priv_lvl_t priv_lvl, // current privilege level - input logic debug_mode, + input logic pck, + input logic rstn, + input logic flush_unissued, + input logic flush_all, + input logic [31:0] instruction [CVA6Cfg.NrIssuePorts-1:0], + input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_valid, + input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_ack, + input logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack, // issue acknowledged + input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_sbe, // issue scoreboard entry + input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr, // WB stage + input logic [CVA6Cfg.NrCommitPorts-1:0][63:0] wdata, + input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr, + input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr, + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr, // commit instruction + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_drop, + input logic st_valid, // stores - address translation + input logic [CVA6Cfg.PLEN-1:0] st_paddr, + input logic ld_valid, // loads + input logic ld_kill, + input logic [CVA6Cfg.PLEN-1:0] ld_paddr, + input bp_resolve_t resolve_branch, // misprediction + input exception_t commit_exception, + input riscv::priv_lvl_t priv_lvl, // current privilege level + input logic debug_mode, - input logic[CVA6Cfg.XLEN-1:0] hart_id_i + input logic[CVA6Cfg.XLEN-1:0] hart_id_i ); // keep the decoded instructions in a queue @@ -59,7 +60,6 @@ module instr_tracer #( logic [31:0] issue_queue [$]; // issue scoreboard entries scoreboard_entry_t issue_sbe_queue [$]; - scoreboard_entry_t issue_sbe_item; // store resolved branches, get (mis-)predictions bp_resolve_t bp [$]; // shadow copy of the register files @@ -87,6 +87,7 @@ module instr_tracer #( task trace(); automatic logic [31:0] decode_instruction, issue_instruction, issue_commit_instruction; automatic scoreboard_entry_t commit_instruction; + automatic scoreboard_entry_t issue_sbe_item; // initialize register 0 gp_reg_file = '{default:0}; fp_reg_file = '{default:0}; @@ -94,7 +95,7 @@ module instr_tracer #( forever begin automatic bp_resolve_t bp_instruction = '0; // new cycle, we are only interested if reset is de-asserted - @(pck) if (rstn !== 1'b1) begin + @(posedge pck) if (rstn !== 1'b1) begin flush(); continue; end @@ -106,20 +107,24 @@ module instr_tracer #( // Instruction Decode // ------------------- // we are decoding an instruction - if (fetch_valid && fetch_ack) begin - decode_instruction = instruction; - decode_queue.push_back(decode_instruction); + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; ++i) begin + if (fetch_valid[i] && fetch_ack[i]) begin + decode_instruction = instruction[i]; + decode_queue.push_back(decode_instruction); + end end // ------------------- // Instruction Issue // ------------------- // we got a new issue ack, so put the element from the decode queue to // the issue queue - if (issue_ack && !flush_unissued) begin - issue_instruction = decode_queue.pop_front(); - issue_queue.push_back(issue_instruction); - // also save the scoreboard entry to a separate issue queue - issue_sbe_queue.push_back(scoreboard_entry_t'(issue_sbe)); + for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; ++i) begin + if (issue_ack[i] && !flush_unissued) begin + issue_instruction = decode_queue.pop_front(); + issue_queue.push_back(issue_instruction); + // also save the scoreboard entry to a separate issue queue + issue_sbe_queue.push_back(scoreboard_entry_t'(issue_sbe[i])); + end end // -------------------- @@ -138,11 +143,11 @@ module instr_tracer #( if (resolve_branch.valid) begin bp.push_back(resolve_branch); end - // -------------- - // Commit - // -------------- - // we are committing an instruction - for (int i = 0; i < 2; i++) begin + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + // -------------- + // Commit + // -------------- + // we are committing an instruction if (commit_ack[i]) begin commit_instruction = scoreboard_entry_t'(commit_instr[i]); issue_commit_instruction = issue_queue.pop_front(); @@ -155,30 +160,62 @@ module instr_tracer #( if (commit_instr[i].fu == ariane_pkg::CTRL_FLOW) bp_instruction = bp.pop_front(); + + // all the queues have been popped + // if the commit is to be dropped, we can do it now + if (commit_drop[i]) continue; // the scoreboards issue entry still contains the immediate value as a result // check if the write back is valid, if not we need to source the result from the register file // as the most recent version of this register will be there. if (we_gpr[i] || we_fpr[i]) begin - printInstr(issue_sbe_item, issue_commit_instruction, wdata[i], address_mapping, priv_lvl, debug_mode, bp_instruction); + printInstr( + issue_sbe_item, + issue_commit_instruction, + wdata[i], + we_gpr[i] || we_fpr[i], + we_fpr[i], + address_mapping, + priv_lvl, + debug_mode, + bp_instruction + ); end else if (ariane_pkg::is_rd_fpr(commit_instruction.op)) begin - printInstr(issue_sbe_item, issue_commit_instruction, fp_reg_file[commit_instruction.rd], address_mapping, priv_lvl, debug_mode, bp_instruction); + printInstr( + issue_sbe_item, + issue_commit_instruction, + fp_reg_file[commit_instruction.rd], + 1'b0, + 1'b1, + address_mapping, + priv_lvl, + debug_mode, + bp_instruction + ); end else begin - printInstr(issue_sbe_item, issue_commit_instruction, gp_reg_file[commit_instruction.rd], address_mapping, priv_lvl, debug_mode, bp_instruction); + printInstr( + issue_sbe_item, + issue_commit_instruction, + gp_reg_file[commit_instruction.rd], + 1'b0, + 1'b0, + address_mapping, + priv_lvl, + debug_mode, + bp_instruction + ); end end - end - // -------------- - // Exceptions - // -------------- - if (commit_exception.valid && !(debug_mode && commit_exception.cause == riscv::BREAKPOINT)) begin - // print exception - printException(commit_instr[0].pc, commit_exception.cause, commit_exception.tval); - end - // ---------------------- - // Commit Registers - // ---------------------- - // update shadow reg files here - for (int i = 0; i < 2; i++) begin + // -------------- + // Exceptions + // -------------- + if (i == 0 && commit_exception.valid && !(debug_mode && commit_exception.cause == riscv::BREAKPOINT)) begin + // print exception + printException(commit_instr[0].pc, commit_exception.cause, commit_exception.tval); + end + // ---------------------- + // Commit Registers + // ---------------------- + // update shadow reg files here if (we_gpr[i] && waddr[i] != 5'b0) begin gp_reg_file[waddr[i]] = wdata[i]; end else if (we_fpr[i]) begin @@ -217,16 +254,31 @@ module instr_tracer #( bp = {}; endfunction - function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [CVA6Cfg.PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp); + function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic dest_we_valid, logic dest_is_fp, logic [CVA6Cfg.PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp); automatic instr_trace_item #( .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), .scoreboard_entry_t(scoreboard_entry_t) - ) iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp); + ) iti = new ( + $time, + clk_ticks, + sbe, + instr, + gp_reg_file, + fp_reg_file, + result, + dest_we_valid, + dest_is_fp, + paddr, + priv_lvl, + debug_mode, + bp + ); // print instruction to console automatic string print_instr = iti.printInstr(); + automatic logic commit_is_fp = dest_we_valid ? dest_is_fp : ariane_pkg::is_rd_fpr(sbe.op); if (ariane_pkg::ENABLE_SPIKE_COMMIT_LOG && !debug_mode) begin - $fwrite(commit_log, riscv::spikeCommitLog(sbe.pc, priv_lvl, instr, sbe.rd, result, ariane_pkg::is_rd_fpr(sbe.op))); + $fwrite(commit_log, riscv::spikeCommitLog(sbe.pc, priv_lvl, instr, sbe.rd, result, commit_is_fp)); end $fwrite(f, {print_instr, "\n"}); endfunction diff --git a/config/gen_from_riscv_config/README.md b/config/gen_from_riscv_config/README.md index 2422c973e03..6eb8a8dc2de 100644 --- a/config/gen_from_riscv_config/README.md +++ b/config/gen_from_riscv_config/README.md @@ -18,7 +18,7 @@ # Gen From Risc-V Config -This software takes a `Risc -V Config Yaml` description of CSR Registers, and generates ReStructuredText documents and Mardown Documents for CSR Registers and ISA Extensions. In the example/tb directory there is an example of how to generate +This software takes a `Risc-V Config Yaml` description of CSR Registers, and generates ReStructuredText documents and Markdown Documents for CSR Registers and ISA Extensions. In the example/tb directory there is an example of how to generate the packages. For more details about RISC-V Config Yaml, see [Annexes](##Annexes) section @@ -33,13 +33,13 @@ pip3 install -r requirements.txt ## Usage ```bash -#Generate Restructred-text documentation for Control and Status Registers (CSR) +#Generate Restructured-text documentation for Control and Status Registers (CSR) python3 .py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -c <../riscv-config/Config_Name/generated/custom_gen>.yaml -d <../riscv-config/Config_Name/generated/debug_gen>.yaml -m .yaml -t < Config_Name> -#Generate Restructred-text documentation for ISA extensions +#Generate Restructured-text documentation for ISA extensions python3 .py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -i .yaml -m .yaml -t < Config_Name> -#Generate the Yaml spike configuration file +#Generate the Yaml spike configuration file python3 .py -s <../riscv-config/Config_Name/generated/isa_gen>.yaml -c <../riscv-config/Config_Name/generated/custom_gen>.yaml -i .mako -m .yaml -t < Config_Name> ``` @@ -47,13 +47,13 @@ python3 .py -s <../riscv-config/Config_Name/generated/ ## Usage with cv32a65x ```bash -#Generate the Restructred-text documentation for Control and Status Registers (CSR) +#Generate the Restructured-text documentation for Control and Status Registers (CSR) python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -c ../riscv-config/cv32a65x/generated/custom_gen.yaml -d ../riscv-config/cv32a65x/generated/debug_gen.yaml -m updaters/cv32a65x/csr_updater.yaml -t cv32a65x -#Generate the Restructred-text documentation for ISA extensions +#Generate the Restructured-text documentation for ISA extensions python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/cv32a65x/isa_updater.yaml -t cv32a65x -#Generate the Yaml spike configuration file +#Generate the Yaml spike configuration file python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -c ../riscv-config/cv32a65x/generated/custom_gen.yaml -i templates/spike.mako -m updaters/cv32a65x/spike_updater.yaml -t cv32a65x ``` @@ -167,7 +167,7 @@ Example : ISA_Updater.yaml sub_key : sub_value (if exist if not dont include it ) cond: value -- Exemple : +- Example : exclude : @@ -185,7 +185,7 @@ Example : ISA_Updater.yaml Register Name : range : number -- Exemple : +- Example : pmpaddr : @@ -217,10 +217,10 @@ CSR/ISA Updater read RISC-CONFIG.yaml and update the registers so if you want to cores: : -- Exemple : +- Example : Bootroom : true -- Exemple : +- Example : cores: isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei @@ -260,7 +260,7 @@ Risc-V Config Yaml file is generated based on Risc-Config tool which include all You can execute the tool from `../config/riscv-config` repo : -- It needs python dependancies with : +- It needs python dependencies with : 'pip3 install -r ../../vendor/riscv-config/Requirements.txt' . @@ -311,7 +311,7 @@ __Format__ : Pseudocode: Invalid_Values: Exception_Raised: -__Exemple__: +__Example__: RV32I Base Integer Instructions: Description : | diff --git a/config/gen_from_riscv_config/cv32a60x/linker/link.ld b/config/gen_from_riscv_config/cv32a60x/linker/link.ld index a134ec289a8..5722241bef6 100644 --- a/config/gen_from_riscv_config/cv32a60x/linker/link.ld +++ b/config/gen_from_riscv_config/cv32a60x/linker/link.ld @@ -9,7 +9,7 @@ /* The OUTPUT_ARCH command specifies the machine architecture where the argument is one of the names used in the BFD library. More - specifically one of the entires in bfd/cpu-mips.c */ + specifically one of the entries in bfd/cpu-*.c */ OUTPUT_ARCH( "riscv" ) ENTRY(_start) @@ -76,7 +76,7 @@ SECTIONS _tbss_end = .; } - /* End of uninitalized data segement */ + /* End of uninitialized data segment */ _end = .; } diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc index f7c8f5aeea3..816d9f93a87 100644 --- a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc +++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc @@ -12,7 +12,7 @@ |=== |Subset Name | Name | Description -|I | RV32I Base Integer Instructions | the base integer instruction set, also known as the 'RV32I' or 'RV64I' instruction set , depending on the address space size, provides the core functionality required for general-purpose computing .it includes instructions for arithmetic, logical, and control operations, as well as memory accessand manipulation +|I | RV32I Base Integer Instructions | the base integer instruction set, also known as the 'RV32I' or 'RV64I' instruction set, depending on the address space size, provides the core functionality required for general-purpose computing. It includes instructions for arithmetic, logical, and control operations, as well as memory access and manipulation. |M | RV32M Multiplication and Division Instructions | the standard integer multiplication and division instruction extension, which is named “M” and contains instructions that multiply or divide values held in two integer registers. |C | RV32C Compressed Instructions | RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when: the immediate or address offset is small; one of the registers is the zero register (x0), the ABI link register (x1), or the ABI stack pointer (x2); the destination register and the first source register are identical; the registers used are the 8 most popular ones.The C extension is compatible with all other standard instruction extensions. The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary. With the addition of the C extension, JAL and JALR instructions will no longer raise an instruction misaligned exception |Zicsr | RV32Zicsr Control and Status Register Instructions | All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field. diff --git a/config/gen_from_riscv_config/cv32a65x/linker/link.ld b/config/gen_from_riscv_config/cv32a65x/linker/link.ld index a134ec289a8..5722241bef6 100644 --- a/config/gen_from_riscv_config/cv32a65x/linker/link.ld +++ b/config/gen_from_riscv_config/cv32a65x/linker/link.ld @@ -9,7 +9,7 @@ /* The OUTPUT_ARCH command specifies the machine architecture where the argument is one of the names used in the BFD library. More - specifically one of the entires in bfd/cpu-mips.c */ + specifically one of the entries in bfd/cpu-*.c */ OUTPUT_ARCH( "riscv" ) ENTRY(_start) @@ -76,7 +76,7 @@ SECTIONS _tbss_end = .; } - /* End of uninitalized data segement */ + /* End of uninitialized data segment */ _end = .; } diff --git a/config/gen_from_riscv_config/scripts/libs/isa_updater.py b/config/gen_from_riscv_config/scripts/libs/isa_updater.py index aea4245910a..b19eeb000a4 100644 --- a/config/gen_from_riscv_config/scripts/libs/isa_updater.py +++ b/config/gen_from_riscv_config/scripts/libs/isa_updater.py @@ -71,12 +71,12 @@ def isa_recursive_update(original_dict, isa_dict): # Extracting subset names from the YAML data def isa_filter(parsed_data, updater, template): """ - create dict of filtred data from isa_template based on supported extensions + create dict of filtered data from isa_template based on supported extensions read from ISA String from RISC-V Yaml file :param parsed_data : parsed data of RISC-V Config Yaml file updater : parsed data of updater template : parsed data of isa_template - :return: dict of filtred data from isa_template + :return: dict of filtered data from isa_template """ # Define the regular expression pattern isa_regex = re.compile( diff --git a/config/gen_from_riscv_config/scripts/libs/utils.py b/config/gen_from_riscv_config/scripts/libs/utils.py index 796a6057ce3..93a57452e67 100644 --- a/config/gen_from_riscv_config/scripts/libs/utils.py +++ b/config/gen_from_riscv_config/scripts/libs/utils.py @@ -1273,7 +1273,11 @@ def returnDocument(self): if isinstance(RegElement.get("address", None), str) else hex(RegElement.get("address", None)) ) - reset = hex(RegElement.get("reset-val", "")) + + if RegElement.get("reset-val", "") != "": + reset = hex(RegElement.get("reset-val", "")) + else: + print(regName, "reset val not defined") access = RegElement.get("priv_mode", "") if Registers.get(register, {}).get("description", "") is not None: diff --git a/config/gen_from_riscv_config/scripts/riscv_config_gen.py b/config/gen_from_riscv_config/scripts/riscv_config_gen.py index ea5a58e5552..919a472eca4 100644 --- a/config/gen_from_riscv_config/scripts/riscv_config_gen.py +++ b/config/gen_from_riscv_config/scripts/riscv_config_gen.py @@ -39,8 +39,8 @@ parser.add_argument("-d", "--debugFile", help=" debug_gen yaml input file") parser.add_argument("-m", "--modif", help="ISA /CSR Formatter if exist") parser.add_argument("-i", "--temp", help="Full ISA /SPIKETemplate") - parser.add_argument("-t", "--target", help="Specifiy Config Name") - parser.add_argument("-f", "--format", help="Specifiy format output") + parser.add_argument("-t", "--target", help="Specify Config Name") + parser.add_argument("-f", "--format", help="Specify format output") args, unknown_args = parser.parse_known_args() if args.format in ['rst']: diff --git a/config/riscv-config/cv64a60ax/spec/custom_spec.yaml b/config/riscv-config/cv64a60ax/spec/custom_spec.yaml new file mode 100644 index 00000000000..ec2c1f8449c --- /dev/null +++ b/config/riscv-config/cv64a60ax/spec/custom_spec.yaml @@ -0,0 +1,55 @@ +# Copyright 2024 Thales DIS France SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Original Author: Zbigniew CHAMSKI - Thales + +hart_ids: [0] +hart0: + icache: + reset-val: 0x1 + rv32: + accessible: false + rv64: + accessible: true + icache: + implemented: true + type: + rw: true + description: bit for cache-enable of instruction cache + msb: 0 + lsb: 0 + shadow: + shadow_type: + description: the register controls the operation of the i-cache unit. + address: 0x7c0 + priv_mode: M + dcache: + reset-val: 0x1 + rv32: + accessible: false + rv64: + accessible: true + dcache: + implemented: true + type: + rw: true + description: bit for cache-enable of data cache + shadow: + shadow_type: + msb: 0 + lsb: 0 + description: the register controls the operation of the d-cache unit. + address: 0x7c1 + priv_mode: M + diff --git a/config/riscv-config/cv64a60ax/spec/debug_spec.yaml b/config/riscv-config/cv64a60ax/spec/debug_spec.yaml new file mode 100644 index 00000000000..7c1f981a689 --- /dev/null +++ b/config/riscv-config/cv64a60ax/spec/debug_spec.yaml @@ -0,0 +1,168 @@ +# Copyright 2024 Thales DIS France SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Original Author: Zbigniew CHAMSKI - Thales +# Updated from CV66 64 CEA - Tanuj Khandelwal - Thales + +hart_ids: [0] +hart0: &hart0 + Debug_Spec_Version: '1.0.0' + supported_xlen: [64] + debug_mode: true + parking_loop: 0x800 + dcsr: + reset-val: 0x40000413 + rv64: + accessible: true + debugver: + implemented: true + type: + ro_constant: 0x4 + ebreakvs: + implemented: false + ebreakvu: + implemented: false + ebreakm: + implemented: true + ebreaks: + implemented: true + ebreaku: + implemented: true + stepie: + implemented: true + stopcount: + implemented: true + stoptime: + implemented: true + cause: + implemented: true + type: + ro_variable: true + v: + implemented: true + mprven: + implemented: true + nmip: + implemented: true + type: + ro_variable: true + step: + implemented: true + prv: + implemented: true + rv32: + accessible: false + dpc: + rv64: + accessible: true + rv32: + accessible: false + tselect: + rv32: + accessible: False + rv64: + accessible: True + type: + warl: + dependency_fields: [] + legal: + - tselect[63:0] in [0x00000000:0x3] + wr_illegal: + - unchanged + tinfo: #FIXME + rv32: + accessible: False + rv64: + accessible: True + index_select_reg: tselect + index_list: + - reset-val: 0x78 + index_val: 0 + shadow: + shadow_type: + type: + ro_constant: 0x78 + - reset-val: 0x8 + index_val: 1 + shadow: + shadow_type: + type: + ro_constant: 0x8 + - reset-val: 0x10 + index_val: 2 + shadow: + shadow_type: + type: + ro_constant: 0x10 + tdata1: + rv32: + accessible: False + rv64: + accessible: True + index_select_reg: tselect + index_list: + - reset-val: 0xdeadbeef + index_val: 0 + shadow: + shadow_type: + type: + ro_constant: 0xdeadbeef + - reset-val: 0 + index_val: 1 + shadow: + shadow_type: + type: &mywarl + warl: + dependency_fields: [] + legal: + - writeval[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + - reset-val: 0 + index_val: 2 + shadow: + shadow_type: + type: + warl: + dependency_fields: [] + legal: + - writeval[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + + #FIXME NTO SUPPORTED BY RISCV CNFIG + # tdata2: + # rv64: + # accessible: true + # type: + # ro_variable: true + # rv32: + # accessible: false + # tdata3: + # rv64: + # accessible: true + # type: + # ro_variable: true + # rv32: + # accessible: false + dscratch0: + rv64: + accessible: true + rv32: + accessible: false + dscratch1: + rv64: + accessible: true + rv32: + accessible: false diff --git a/config/riscv-config/cv64a60ax/spec/isa_spec.yaml b/config/riscv-config/cv64a60ax/spec/isa_spec.yaml new file mode 100644 index 00000000000..cef6c746bc8 --- /dev/null +++ b/config/riscv-config/cv64a60ax/spec/isa_spec.yaml @@ -0,0 +1,1863 @@ +# Copyright 2024 Thales DIS France SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Original Author: Zbigniew CHAMSKI - Thales +# Updated from CV6A60AX 64 CEA - Tanuj Khandelwal - Thales + +hart_ids: [0] +hart0: &hart0 + ISA: RV64IMAFDCNSUZicsr_Zicbom_Zicbop_Zicboz_Zifencei_Zcb_Zba_Zbb_Zbc_Zbs + User_Spec_Version: '2.3' + supported_xlen: [64] + physical_addr_sz: 39 + pmp_granularity: 10 # FIXME: To verify + misa: + reset-val: 0x800000000014312D # B: bit 1, C: bit 2, I = bit 8, M = bit 12, Z = bit 25 + rv64: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mxl[1:0] in [0x2] + wr_illegal: + - unchanged + extensions: + implemented: true + type: + # ro_constant: 0x214312F + mvendorid: + reset-val: 0x00000602 + rv64: + accessible: true + type: + ro_constant: 0x00000602 + rv32: + accessible: false + fcsr: + rv32: + accessible: false + rv64: + accessible: true + fflags: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - fflags[4:0] in [0x00:0x1F] + wr_illegal: + - Unchanged + mtvec: + reset-val: 0x80010000 + rv64: + accessible: true + base: + implemented: true + type: + warl: + dependency_fields: [] + legal: + # The 62 bits of 'base' are suffixed with 2'b00 + # ==> all values are legal, alignment 4 bytes is implied + - base[61:0] in [0x00000000:0x3FFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + mode: + implemented: true + type: + warl: + dependency_fields: [] + legal: + # Only Direct mode. + - mode[1:0] in [0x0] + wr_illegal: + - Unchanged + vsstatus: + reset-val: 0x0 + rv64: + accessible: false + rv32: + accessible: false + mstatus: # FIXME verify details + reset-val: 0xA00001800 # .mpp = 0x3 + rv64: + accessible: true + uie: + implemented: true + sie: + implemented: true + mie: + implemented: true + upie: + implemented: true + spie: + implemented: true + sxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - sxl[1:0] in [0x2] + wr_illegal: + - unchanged + uxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - uxl[1:0] in [0x2] + wr_illegal: + - unchanged + mpie: + implemented: true + mpp: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mpp[1:0] in [0x3] + wr_illegal: + - Unchanged + fs: + implemented: true + xs: + implemented: true + mprv: + implemented: false + sum: + implemented: true + mxr: + implemented: true + tvm: + implemented: false + tw: + implemented: false + tsr: + implemented: false + rv32: + accessible: false + mip: # Check if readonly or not + reset-val: 0 + rv64: + accessible: true + usip: + implemented: true + ssip: + implemented: true + msip: + implemented: true + utip: + implemented: true + stip: + implemented: true + mtip: + implemented: true + type: + ro_variable: true + ueip: + implemented: true + seip: + implemented: true + meip: + implemented: true + type: + ro_variable: true + rv32: + accessible: false + hip: + reset-val: 0 + rv64: + accessible: false + vssip: + implemented: false + vstip: + implemented: false + vseip: + implemented: false + sgeip: + implemented: false + rv32: + accessible: false + mie: + reset-val: 0 + rv64: + accessible: true + usie: + implemented: true + ssie: + implemented: true + msie: + implemented: true + utie: + implemented: true + stie: + implemented: true + mtie: + implemented: true + ueie: + implemented: true + seie: + implemented: true + meie: + implemented: true + rv32: + accessible: false + hie: + reset-val: 0 + rv64: + accessible: false + vssie: + implemented: false + vstie: + implemented: false + vseie: + implemented: false + sgeie: + implemented: false + rv32: + accessible: false + mepc: + reset-val: 0x0 + rv64: + accessible: true + rv32: + accessible: false + mtval: + reset-val: 0x0 + rv64: + accessible: true + rv32: + accessible: false + mcause: + reset-val: 0 + rv64: + accessible: true + interrupt: + implemented: true + exception_code: + implemented: true + rv32: + accessible: false + medeleg: + reset-val: 0 + rv64: + accessible: true + rv32: + accessible: false + mideleg: + reset-val: 0 + rv64: + accessible: true + rv32: + accessible: false + menvcfg: #FIXME: not convinced if it is needed + reset-val: 0 + rv64: + accessible: true + rv32: + accessible: false + marchid: + rv64: + accessible: true + type: + ro_constant: 0x00000003 + rv32: + accessible: false + reset-val: 0x00000003 + # FIXME not supported yet + # mconfigptr: + # rv64: + # accessible: true + # type: + # ro_constant: 0x0 + # rv32: + # accessible: false + # reset-val: 0x0 + mhartid: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x00 + mhpmcounter3: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter4: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter5: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter6: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter7: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter8: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter9: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter10: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter11: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter12: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter13: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter14: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter15: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter16: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter17: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter18: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter19: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter20: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter21: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter22: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter23: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter24: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter25: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter26: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter27: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter28: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter29: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter30: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmcounter31: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + # FIXME NOT SUPPORTED + # instret: + # rv64: + # accessible: true + # type: + # warl: + # dependency_fields: [] + # legal: + # - instret[31:0] in [0x00000000:0xFFFFFFFF] + # wr_illegal: + # - unchanged + # rv32: + # accessible: false + # reset-val: 0 + mcountinhibit: #FIXME Details + rv64: + accessible: true + rv32: + accessible: false + reset-val: 0x0 + mhpmevent3: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent4: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent5: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent6: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent7: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent8: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent9: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent10: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent11: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent12: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent13: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent14: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent15: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent16: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent17: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent18: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent19: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent20: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent21: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent22: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent23: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent24: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent25: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent26: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent27: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent28: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent29: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent30: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mhpmevent31: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0x0 + mimpid: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + mcounteren: #FIXME Check details + rv64: + accessible: true + rv32: + accessible: false + reset-val: 0 + pmpcfg0: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp0cfg: + implemented: true + type: + warl: + dependency_fields: [pmpcfg0::pmp0cfg] + legal: + - "pmp0cfg[7] in [0] -> pmp0cfg[7] in [0x0:0x1] pmp0cfg[6:5] in [0] pmp0cfg[4:3] not in [2] pmp0cfg[2:0] not in [2,6]" + wr_illegal: + - Unchanged + pmp1cfg: + implemented: true + type: + warl: + dependency_fields: [pmpcfg0::pmp1cfg] + legal: + - "pmp1cfg[7] in [0] -> pmp1cfg[7] in [0x0,0x1] pmp1cfg[6:5] in [0] pmp1cfg[4:3] not in [2] pmp1cfg[2:0] not in [2,6]" + wr_illegal: + - Unchanged + pmp2cfg: + implemented: true + type: + warl: + dependency_fields: [pmpcfg0::pmp2cfg] + legal: + - "pmp2cfg[7] in [0] -> pmp2cfg[7] in [0x0,0x1] pmp2cfg[6:5] in [0] pmp2cfg[4:3] not in [2] pmp2cfg[2:0] not in [2,6]" + wr_illegal: + - Unchanged + pmp3cfg: + implemented: true + type: + warl: + dependency_fields: [pmpcfg0::pmp3cfg] + legal: + - "pmp3cfg[7] in [0] -> pmp3cfg[7] in [0x0,0x1] pmp3cfg[6:5] in [0] pmp3cfg[4:3] not in [2] pmp3cfg[2:0] not in [2,6]" + wr_illegal: + - Unchanged + pmp4cfg: + implemented: true + type: + ro_constant: 0 + pmp5cfg: + implemented: true + type: + ro_constant: 0 + pmp6cfg: + implemented: true + type: + ro_constant: 0 + pmp7cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg2: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp8cfg: + implemented: true + type: + ro_constant: 0 + pmp9cfg: + implemented: true + type: + ro_constant: 0 + pmp10cfg: + implemented: true + type: + ro_constant: 0 + pmp11cfg: + implemented: true + type: + ro_constant: 0 + pmp12cfg: + implemented: true + type: + ro_constant: 0 + pmp13cfg: + implemented: true + type: + ro_constant: 0 + pmp14cfg: + implemented: true + type: + ro_constant: 0 + pmp15cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg4: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp16cfg: + implemented: true + type: + ro_constant: 0 + pmp17cfg: + implemented: true + type: + ro_constant: 0 + pmp18cfg: + implemented: true + type: + ro_constant: 0 + pmp19cfg: + implemented: true + type: + ro_constant: 0 + pmp20cfg: + implemented: true + type: + ro_constant: 0 + pmp21cfg: + implemented: true + type: + ro_constant: 0 + pmp22cfg: + implemented: true + type: + ro_constant: 0 + pmp23cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg6: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp24cfg: + implemented: true + type: + ro_constant: 0 + pmp25cfg: + implemented: true + type: + ro_constant: 0 + pmp26cfg: + implemented: true + type: + ro_constant: 0 + pmp27cfg: + implemented: true + type: + ro_constant: 0 + pmp28cfg: + implemented: true + type: + ro_constant: 0 + pmp29cfg: + implemented: true + type: + ro_constant: 0 + pmp30cfg: + implemented: true + type: + ro_constant: 0 + pmp31cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg8: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp32cfg: + implemented: true + type: + ro_constant: 0 + pmp33cfg: + implemented: true + type: + ro_constant: 0 + pmp34cfg: + implemented: true + type: + ro_constant: 0 + pmp35cfg: + implemented: true + type: + ro_constant: 0 + pmp36cfg: + implemented: true + type: + ro_constant: 0 + pmp37cfg: + implemented: true + type: + ro_constant: 0 + pmp38cfg: + implemented: true + type: + ro_constant: 0 + pmp39cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg10: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp40cfg: + implemented: true + type: + ro_constant: 0 + pmp41cfg: + implemented: true + type: + ro_constant: 0 + pmp42cfg: + implemented: true + type: + ro_constant: 0 + pmp43cfg: + implemented: true + type: + ro_constant: 0 + pmp44cfg: + implemented: true + type: + ro_constant: 0 + pmp45cfg: + implemented: true + type: + ro_constant: 0 + pmp46cfg: + implemented: true + type: + ro_constant: 0 + pmp47cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg12: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp48cfg: + implemented: true + type: + ro_constant: 0 + pmp49cfg: + implemented: true + type: + ro_constant: 0 + pmp50cfg: + implemented: true + type: + ro_constant: 0 + pmp51cfg: + implemented: true + type: + ro_constant: 0 + pmp52cfg: + implemented: true + type: + ro_constant: 0 + pmp53cfg: + implemented: true + type: + ro_constant: 0 + pmp54cfg: + implemented: true + type: + ro_constant: 0 + pmp55cfg: + implemented: true + type: + ro_constant: 0 + pmpcfg14: + reset-val: 0 + rv32: + accessible: false + rv64: + accessible: true + pmp56cfg: + implemented: true + type: + ro_constant: 0 + pmp57cfg: + implemented: true + type: + ro_constant: 0 + pmp58cfg: + implemented: true + type: + ro_constant: 0 + pmp59cfg: + implemented: true + type: + ro_constant: 0 + pmp60cfg: + implemented: true + type: + ro_constant: 0 + pmp61cfg: + implemented: true + type: + ro_constant: 0 + pmp62cfg: + implemented: true + type: + ro_constant: 0 + pmp63cfg: + implemented: true + type: + ro_constant: 0 + mcycle: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mcycle[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + minstret: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - minstret[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr0: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr0[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr1: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr1[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr2: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr2[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr3: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr3[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr4: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr4[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr5: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr5[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr6: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr6[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr7: + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr7[63:0] bitmask [0xFFFFFFFFFFFFFFFE, 0x0000000000000000] + wr_illegal: + - unchanged + rv32: + accessible: false + reset-val: 0 + pmpaddr8: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr9: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr10: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr11: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr12: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr13: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr14: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr15: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr16: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr17: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr18: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr19: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr20: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr21: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr22: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr23: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr24: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr25: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr26: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr27: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr28: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr29: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr30: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr31: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr32: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr33: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr34: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr35: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr36: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr37: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr38: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr39: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr40: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr41: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr42: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr43: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr44: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr45: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr46: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr47: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr48: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr49: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr50: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr51: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr52: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr53: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr54: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr55: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr56: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr57: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr58: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr59: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr60: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr61: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr62: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + pmpaddr63: + rv64: + accessible: true + type: + ro_constant: 0x0 + rv32: + accessible: false + reset-val: 0 + satp: + rv32: + accessible: false + rv64: + accessible: true + ppn: + type: + warl: + dependency_fields: [] + legal: + - "ppn[43:0] in [0x00000000000:0xFFFFFFFFFFF]" + wr_illegal: + - Unchanged + asid: + type: + warl: + dependency_fields: [] + legal: + - "asid[15:0] in [0x0000:0x00FF]" + wr_illegal: + - Unchanged + mode: + type: + warl: + dependency_fields: [] + legal: + - "mode[3:0] in [0,8]" + wr_illegal: + - Unchanged + reset-val: 0x0000000000000000 + scause: + rv32: + accessible: false + rv64: + accessible: true + exception_code: + implemented: True + interrupt: + implemented: True + reset-val: 0 + senvcfg: + rv32: + accessible: false + rv64: + accessible: true + reset-val: 0 + sepc: + rv32: + accessible: false + rv64: + accessible: true + reset-val: 0 + sie: #FIXME Check if readonly or not + reset-val: 0 + rv64: + accessible: true + ssie: + implemented: true + stie: + implemented: true + seie: + implemented: true + rv32: + accessible: false + sip: #FIXME Check if readonly or not + reset-val: 0 + rv64: + accessible: true + ssip: + implemented: true + stip: + implemented: true + seip: + implemented: true + rv32: + accessible: false + sscratch: + rv64: + accessible: true + rv32: + accessible: false + sstatus: + reset-val: 0x0 + rv64: + accessible: true + uie: + implemented: false + sie: + implemented: true + upie: + implemented: false + spie: + implemented: true + spp: + implemented: true + fs: + implemented: false + xs: + implemented: true + sum: + implemented: true + mxr: + implemented: true + # FIXME not supported yet + #uxl: + # implemented: true + # type: + # warl: + # dependency_fields: [] + # legal: + # - uxl[1:0] in [0x2] + # wr_illegal: + # - unchanged + sd: + implemented: true + rv32: + accessible: false + stval: + rv32: + accessible: false + rv64: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - stval[63:0] in [0x0000000000000000:0xFFFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + reset-val: 0 + stvec: + reset-val: 0x80010000 + rv64: + accessible: true + base: + implemented: true + type: + warl: + dependency_fields: [] + legal: + # The 62 bits of 'base' are suffixed with 2'b00 + # ==> all values are legal, alignment 4 bytes is implied + - base[61:0] in [0x00000000:0x3FFFFFFFFFFFFFFF] + wr_illegal: + - Unchanged + mode: + implemented: true + type: + warl: + dependency_fields: [] + legal: + # Only Direct mode. + - mode[1:0] in [0x0] + wr_illegal: + - Unchanged + time: + rv64: + accessible: true + type: + ro_variable: true + rv32: + accessible: false + reset-val: 0 diff --git a/config/riscv-config/cv64a60ax/spec/platform_spec.yaml b/config/riscv-config/cv64a60ax/spec/platform_spec.yaml new file mode 100644 index 00000000000..23d847bf398 --- /dev/null +++ b/config/riscv-config/cv64a60ax/spec/platform_spec.yaml @@ -0,0 +1,53 @@ +# Copyright 2024 Thales DIS France SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Original Author: Tanuj Khandelwal CEA (copied from riscv-config examples) + +nmi: + label: nmi_vector + # address: 12288 +reset: + label: reset_vector + # address: 16384 +mtime: + implemented: false +mtimecmp: + implemented: false + #mcause_non_standard: + # implemented: true +mtval_condition_writes: + implemented: false +scause_non_standard: + implemented: false +stval_condition_writes: + implemented: false +zicbo_cache_block_sz : + implemented: true + zicbom_sz: 64 + zicboz_sz: 64 + +#memory_map: +# - memory_region: +# name: bootrom +# base_addr: 0x10000 +# size: 0x10000 +# description: System boot ROM +# attributes: +# read_only: true +# cached: false +# - memory_region: +# name: dram +# base_addr: 0x80000000 +# size: 0x40000000 +# description: System (D)RAM diff --git a/core/Flist.cva6 b/core/Flist.cva6 index e82365d12bb..8511533159c 100644 --- a/core/Flist.cva6 +++ b/core/Flist.cva6 @@ -20,7 +20,7 @@ // // Manifest for the CVA6 CORE RTL model. // - This is a CORE-ONLY manifest. -// - Relevent synthesis and simulation scripts/Makefiles must set the shell +// - Relevant synthesis and simulation scripts/Makefiles must set the shell // ENV variable CVA6_REPO_DIR. // /////////////////////////////////////////////////////////////////////////////// @@ -37,11 +37,37 @@ ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv +incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/ +incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/axi/include/ +incdir+${CVA6_REPO_DIR}/common/local/util/ ++incdir+${HPDCACHE_DIR}/rtl/src/utils/ecc // Floating point unit ${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_pkg.sv ${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_cast_multi.sv ${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_classifier.sv +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_special.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_srt_single.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_top.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_dp.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_frbus.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_src_type.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ctrl.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_double.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_ff1.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_pack.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_prepare.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_round.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_scalar_dp.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_bound_table.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt_radix16_with_sqrt.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_srt.v +${CVA6_REPO_DIR}/core/cvfpu/vendor/openc910/C910_RTL_FACTORY/gen_rtl/vfdsu/rtl/ct_vfdsu_top.v +${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_divsqrt_th_32.sv +${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_divsqrt_th_64_multi.sv ${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_divsqrt_multi.sv ${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_fma_multi.sv ${CVA6_REPO_DIR}/core/cvfpu/src/fpnew_fma.sv @@ -71,6 +97,8 @@ ${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv ${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv ${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv ${CVA6_REPO_DIR}/core/include/build_config_pkg.sv +${CVA6_REPO_DIR}/core/include/aes_pkg.sv +${CVA6_REPO_DIR}/core/include/triggers_pkg.sv //CVXIF ${CVA6_REPO_DIR}/core/cvxif_compressed_if_driver.sv @@ -106,6 +134,8 @@ ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/delta_counter.sv ${CVA6_REPO_DIR}/core/cva6.sv ${CVA6_REPO_DIR}/core/cva6_rvfi_probes.sv ${CVA6_REPO_DIR}/core/alu.sv +${CVA6_REPO_DIR}/core/alu_wrapper.sv +${CVA6_REPO_DIR}/core/aes.sv // Note: depends on fpnew_pkg, above ${CVA6_REPO_DIR}/core/fpu_wrap.sv ${CVA6_REPO_DIR}/core/branch_unit.sv @@ -115,6 +145,7 @@ ${CVA6_REPO_DIR}/core/controller.sv ${CVA6_REPO_DIR}/core/zcmt_decoder.sv ${CVA6_REPO_DIR}/core/csr_buffer.sv ${CVA6_REPO_DIR}/core/csr_regfile.sv +${CVA6_REPO_DIR}/core/trigger_module.sv ${CVA6_REPO_DIR}/core/decoder.sv ${CVA6_REPO_DIR}/core/ex_stage.sv ${CVA6_REPO_DIR}/core/instr_realign.sv @@ -132,6 +163,7 @@ ${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv ${CVA6_REPO_DIR}/core/ariane_regfile_fpga.sv // NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators) ${CVA6_REPO_DIR}/core/scoreboard.sv +${CVA6_REPO_DIR}/core/raw_checker.sv ${CVA6_REPO_DIR}/core/store_buffer.sv ${CVA6_REPO_DIR}/core/amo_buffer.sv ${CVA6_REPO_DIR}/core/store_unit.sv @@ -144,6 +176,7 @@ ${CVA6_REPO_DIR}/core/cva6_fifo_v3.sv // What is "frontend"? ${CVA6_REPO_DIR}/core/frontend/btb.sv ${CVA6_REPO_DIR}/core/frontend/bht.sv +${CVA6_REPO_DIR}/core/frontend/bht2lvl.sv ${CVA6_REPO_DIR}/core/frontend/ras.sv ${CVA6_REPO_DIR}/core/frontend/instr_scan.sv ${CVA6_REPO_DIR}/core/frontend/instr_queue.sv @@ -166,9 +199,19 @@ ${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache_axi_wrapper.sv ${CVA6_REPO_DIR}/core/cache_subsystem/std_cache_subsystem.sv ${CVA6_REPO_DIR}/core/cache_subsystem/std_nbdcache.sv -F ${HPDCACHE_DIR}/rtl/hpdcache.Flist +${HPDCACHE_DIR}/rtl/src/utils/ecc/prim_secded_36_29_dec.sv +${HPDCACHE_DIR}/rtl/src/utils/ecc/prim_secded_36_29_enc.sv +${HPDCACHE_DIR}/rtl/src/utils/ecc/prim_secded_39_32_dec.sv +${HPDCACHE_DIR}/rtl/src/utils/ecc/prim_secded_39_32_enc.sv +${HPDCACHE_DIR}/rtl/src/utils/ecc/prim_secded_55_48_dec.sv +${HPDCACHE_DIR}/rtl/src/utils/ecc/prim_secded_55_48_enc.sv +${HPDCACHE_DIR}/rtl/src/utils/ecc/prim_secded_72_64_dec.sv +${HPDCACHE_DIR}/rtl/src/utils/ecc/prim_secded_72_64_enc.sv +${HPDCACHE_DIR}/rtl/src/utils/ecc/prim_secded_pkg.sv ${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_resp_demux.sv ${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_to_axi_read.sv ${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_to_axi_write.sv +${CVA6_REPO_DIR}/core/include/dummy_l15_pkg.sv ${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_subsystem.sv ${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv ${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_if_adapter.sv @@ -176,6 +219,9 @@ ${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_wrapper.sv ${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv ${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv ${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv +${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_ecc_1rw.sv +${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_ecc_1rw.sv +${HPDCACHE_DIR}/rtl/src/common/macros/behav/hpdcache_sram_wmask_ecc_1rw.sv // Physical Memory Protection // NOTE: pmp.sv modified for DSIM (unchanged for other simulators) diff --git a/core/Flist.cva6_gate b/core/Flist.cva6_gate index a6e76e48f44..50eb099e80e 100644 --- a/core/Flist.cva6_gate +++ b/core/Flist.cva6_gate @@ -61,8 +61,8 @@ ${CVA6_REPO_DIR}/pd/synth/cva6_${TARGET_CFG}_synth.v # Dedicated to black box in caches, cv32a65x only ${CVA6_REPO_DIR}/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080.sv -${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv +${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002.sv +${CVA6_REPO_DIR}/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040_00000001.sv ${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv ${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper_cache_techno.sv diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index d00e7eb5f03..5309b2fc43d 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -23,36 +23,12 @@ module acc_dispatcher parameter type exception_t = logic, parameter type fu_data_t = logic, parameter type scoreboard_entry_t = logic, - localparam type accelerator_req_t = struct packed { - logic req_valid; - logic resp_ready; - riscv::instruction_t insn; - logic [CVA6Cfg.XLEN-1:0] rs1; - logic [CVA6Cfg.XLEN-1:0] rs2; - fpnew_pkg::roundmode_e frm; - logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; - logic store_pending; - // Invalidation interface - logic acc_cons_en; - logic inval_ready; - }, - parameter type acc_req_t = accelerator_req_t, - parameter type acc_resp_t = struct packed { - logic req_ready; - logic resp_valid; - logic [CVA6Cfg.XLEN-1:0] result; - logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; - exception_t exception; - // Metadata - logic store_pending; - logic store_complete; - logic load_complete; - logic [4:0] fflags; - logic fflags_valid; - // Invalidation interface - logic inval_valid; - logic [63:0] inval_addr; - }, + parameter type acc_req_t = logic, + parameter type acc_resp_t = logic, + parameter type accelerator_req_t = logic, + parameter type accelerator_resp_t = logic, + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic, parameter type acc_cfg_t = logic, parameter acc_cfg_t AccCfg = '0 ) ( @@ -65,10 +41,11 @@ module acc_dispatcher // Interface with the CSRs input priv_lvl_t ld_st_priv_lvl_i, input logic sum_i, - input pmpcfg_t [CVA6Cfg.NrPMPEntries-1:0] pmpcfg_i, - input logic [CVA6Cfg.NrPMPEntries-1:0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, input logic [2:0] fcsr_frm_i, output logic dirty_v_state_o, + input logic acc_mmu_en_i, // Interface with the issue stage input scoreboard_entry_t issue_instr_i, input logic issue_instr_hs_i, @@ -83,11 +60,14 @@ module acc_dispatcher output logic acc_valid_ex_o, // FU executed // Interface with the commit stage input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, - input logic commit_st_barrier_i, // A store barrier was commited + input logic commit_st_barrier_i, // A store barrier was committed // Interface with the load/store unit output logic acc_stall_st_pending_o, input logic acc_no_st_pending_i, input dcache_req_i_t [2:0] dcache_req_ports_i, + // Interface with the MMU + output acc_mmu_req_t acc_mmu_req_o, + input acc_mmu_resp_t acc_mmu_resp_i, // Interface with the controller output logic ctrl_halt_o, input logic [11:0] csr_addr_i, @@ -209,8 +189,6 @@ module acc_dispatcher // We received a new instruction if (acc_valid_q) insn_pending_d[acc_data.trans_id] = 1'b1; - // Flush all received instructions - if (flush_ex_i) insn_pending_d = '0; // An accelerator instruction is no longer speculative. if (acc_commit && insn_pending_q[acc_commit_trans_id]) begin @@ -219,7 +197,16 @@ module acc_dispatcher end // An accelerator instruction was issued. - if (acc_req_o.req_valid) insn_ready_d[acc_req_o.trans_id] = 1'b0; + if (acc_req_o.acc_req.req_valid) insn_ready_d[acc_req_o.acc_req.trans_id] = 1'b0; + + // Flush all received instructions. This branch must appear LAST so that + // it wins the lexical-priority contest against a simultaneous acc_commit + // (which reads the registered insn_pending_q and would otherwise leave a + // stale insn_ready bit set for a just-flushed trans_id). + if (flush_ex_i) begin + insn_pending_d = '0; + insn_ready_d = '0; + end end : p_non_speculative_ff /************************* @@ -231,29 +218,31 @@ module acc_dispatcher logic acc_req_ready; accelerator_req_t acc_req_int; - fall_through_register #( + spill_register #( .T(accelerator_req_t) ) i_accelerator_req_register ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .clr_i (1'b0), - .testmode_i(1'b0), - .data_i (acc_req), - .valid_i (acc_req_valid), - .ready_o (acc_req_ready), - .data_o (acc_req_int), - .valid_o (acc_req_o.req_valid), - .ready_i (acc_resp_i.req_ready) + .clk_i (clk_i), + .rst_ni (rst_ni), + .data_i (acc_req), + .valid_i(acc_req_valid), + .ready_o(acc_req_ready), + .data_o (acc_req_int), + .valid_o(acc_req_o.acc_req.req_valid), + .ready_i(acc_resp_i.acc_resp.req_ready) ); - assign acc_req_o.insn = acc_req_int.insn; - assign acc_req_o.rs1 = acc_req_int.rs1; - assign acc_req_o.rs2 = acc_req_int.rs2; - assign acc_req_o.frm = acc_req_int.frm; - assign acc_req_o.trans_id = acc_req_int.trans_id; - assign acc_req_o.store_pending = !acc_no_st_pending_i && acc_cons_en_i; - assign acc_req_o.acc_cons_en = acc_cons_en_i; - assign acc_req_o.inval_ready = inval_ready_i; + assign acc_req_o.acc_req.insn = acc_req_int.insn; + assign acc_req_o.acc_req.rs1 = acc_req_int.rs1; + assign acc_req_o.acc_req.rs2 = acc_req_int.rs2; + assign acc_req_o.acc_req.frm = acc_req_int.frm; + assign acc_req_o.acc_req.trans_id = acc_req_int.trans_id; + assign acc_req_o.acc_req.store_pending = !acc_no_st_pending_i && acc_cons_en_i; + assign acc_req_o.acc_req.acc_cons_en = acc_cons_en_i; + assign acc_req_o.acc_req.inval_ready = inval_ready_i; + + // MMU interface + assign acc_req_o.acc_mmu_resp = acc_mmu_resp_i; + assign acc_req_o.acc_mmu_en = acc_mmu_en_i; always_comb begin : accelerator_req_dispatcher // Do not fetch from the instruction queue @@ -263,7 +252,7 @@ module acc_dispatcher acc_req = '0; acc_req_valid = 1'b0; - // Unpack fu_data_t into accelerator_req_t + // Unpack fu_data_t into acc_req_t if (!acc_insn_queue_empty) begin acc_req = '{ // Instruction is forwarded from the decoder as an immediate @@ -297,23 +286,27 @@ module acc_dispatcher logic acc_ld_disp; logic acc_st_disp; - assign acc_trans_id_o = acc_resp_i.trans_id; - assign acc_result_o = acc_resp_i.result; - assign acc_valid_o = acc_resp_i.resp_valid; - assign acc_exception_o = acc_resp_i.exception; + assign acc_trans_id_o = acc_resp_i.acc_resp.trans_id; + assign acc_result_o = acc_resp_i.acc_resp.result; + assign acc_valid_o = acc_resp_i.acc_resp.resp_valid; + assign acc_exception_o = acc_resp_i.acc_resp.exception; // Unpack the accelerator response - assign acc_fflags_valid_o = acc_resp_i.fflags_valid; - assign acc_fflags_o = acc_resp_i.fflags; + assign acc_fflags_valid_o = acc_resp_i.acc_resp.fflags_valid; + assign acc_fflags_o = acc_resp_i.acc_resp.fflags; + + // MMU interface + assign acc_mmu_req_o = acc_resp_i.acc_mmu_req; + // Always ready to receive responses - assign acc_req_o.resp_ready = 1'b1; + assign acc_req_o.acc_req.resp_ready = 1'b1; // Signal dispatched load/store to issue stage - assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD); - assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE); + assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD); + assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE); // Cache invalidation - assign inval_valid_o = acc_resp_i.inval_valid; - assign inval_addr_o = acc_resp_i.inval_addr; + assign inval_valid_o = acc_resp_i.acc_resp.inval_valid; + assign inval_addr_o = acc_resp_i.acc_resp.inval_addr; /************************** * Accelerator commit * @@ -344,15 +337,15 @@ module acc_dispatcher * Accelerator barriers * **************************/ - // On a store barrier (i.e. any barrier that requires preceeding stores to complete + // On a store barrier (i.e. any barrier that requires preceding stores to complete // before continuing execution), halt execution while there are pending stores in // the accelerator pipeline. logic wait_acc_store_d, wait_acc_store_q; `FF(wait_acc_store_q, wait_acc_store_d, '0) // Set on store barrier. Clear when no store is pending. - assign wait_acc_store_d = (wait_acc_store_q | commit_st_barrier_i) & acc_resp_i.store_pending; - assign ctrl_halt_o = wait_acc_store_q; + assign wait_acc_store_d = (wait_acc_store_q | commit_st_barrier_i) & acc_resp_i.acc_resp.store_pending; + assign ctrl_halt_o = wait_acc_store_q; /************************** * Load/Store tracking * @@ -390,9 +383,9 @@ module acc_dispatcher .clk_i (clk_i), .rst_ni (rst_ni), .clear_i (1'b0), - .en_i (acc_ld_disp ^ acc_resp_i.load_complete), + .en_i (acc_ld_disp ^ acc_resp_i.acc_resp.load_complete), .load_i (1'b0), - .down_i (acc_resp_i.load_complete), + .down_i (acc_resp_i.acc_resp.load_complete), .d_i ('0), .q_o (acc_disp_loads_pending), .overflow_o(acc_disp_loads_overflow) @@ -435,9 +428,9 @@ module acc_dispatcher .clk_i (clk_i), .rst_ni (rst_ni), .clear_i (1'b0), - .en_i (acc_st_disp ^ acc_resp_i.store_complete), + .en_i (acc_st_disp ^ acc_resp_i.acc_resp.store_complete), .load_i (1'b0), - .down_i (acc_resp_i.store_complete), + .down_i (acc_resp_i.acc_resp.store_complete), .d_i ('0), .q_o (acc_disp_stores_pending), .overflow_o(acc_disp_stores_overflow) diff --git a/core/aes.sv b/core/aes.sv new file mode 100644 index 00000000000..d79a5dd9764 --- /dev/null +++ b/core/aes.sv @@ -0,0 +1,234 @@ +// Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Author: Munail Waqar, 10xEngineers +// Date: 03.05.2025 +// Description: The Zkn extension including its subsets accelerates cryptographic workloads by introducing dedicated +// scalar instructions compliant with the RISC-V Scalar Cryptography specification. The subsets include: +// Zknd (AES Decryption and related instructions), Zkne (AES Encryption support, including AES rounds and key expansion steps), +// Zknh (SHA-256 and SHA-512 hash functions for secure hashing operations). +// +module aes + import ariane_pkg::*; + import aes_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // FU data needed to execute instruction - ISSUE_STAGE + input fu_data_t fu_data_i, + // Original instruction bits for aes + input logic [ 5:0] orig_instr_aes, + // AES result - ISSUE_STAGE + output logic [CVA6Cfg.XLEN-1:0] result_o +); + + logic [63:0] sr; + logic [ 7:0] sbox_in; + logic [31:0] aes32esi_gen; + logic [31:0] aes32esmi_gen; + logic [63:0] aes64es_gen; + logic [63:0] aes64esm_gen; + logic [31:0] aes32dsi_gen; + logic [31:0] aes32dsmi_gen; + logic [63:0] sr_inv; + logic [63:0] aes64ds_gen; + logic [63:0] aes64dsm_gen; + logic [63:0] aes64im_gen; + logic [63:0] aes64ks1i_gen; + logic [63:0] aes64ks2_gen; + + logic [31:0] sha256sig0_gen; + logic [31:0] sha256sig1_gen; + logic [31:0] sha256sum0_gen; + logic [31:0] sha256sum1_gen; + + logic [31:0] sha512sig0h_gen; + logic [31:0] sha512sig0l_gen; + logic [31:0] sha512sig1h_gen; + logic [31:0] sha512sig1l_gen; + logic [31:0] sha512sum0r_gen; + logic [31:0] sha512sum1r_gen; + + logic [63:0] sha512sig0_gen; + logic [63:0] sha512sig1_gen; + logic [63:0] sha512sum0_gen; + logic [63:0] sha512sum1_gen; + + // AES gen block + if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : aes_gen_block + // SHA256 sigma0 transformation function by rotating, shifting and XORing rs1 + assign sha256sig0_gen = (fu_data_i.operand_a[31:0] >> 7 | fu_data_i.operand_a[31:0] << 25) ^ (fu_data_i.operand_a[31:0] >> 18 | fu_data_i.operand_a[31:0] << 14) ^ (fu_data_i.operand_a[31:0] >> 3); + // SHA256 sigma1 transformation function by rotating, shifting and XORing rs1 + assign sha256sig1_gen = (fu_data_i.operand_a[31:0] >> 17 | fu_data_i.operand_a[31:0] << 15) ^ (fu_data_i.operand_a[31:0] >> 19 | fu_data_i.operand_a[31:0] << 13) ^ (fu_data_i.operand_a[31:0] >> 10); + // SHA256 sum0 transformation function by rotating, shifting and XORing rs1 + assign sha256sum0_gen = (fu_data_i.operand_a[31:0] >> 2 | fu_data_i.operand_a[31:0] << 30) ^ (fu_data_i.operand_a[31:0] >> 13 | fu_data_i.operand_a[31:0] << 19) ^ (fu_data_i.operand_a[31:0] >> 22 | fu_data_i.operand_a[31:0] << 10); + // SHA256 sum1 transformation function by rotating, shifting and XORing rs1 + assign sha256sum1_gen = (fu_data_i.operand_a[31:0] >> 6 | fu_data_i.operand_a[31:0] << 26) ^ (fu_data_i.operand_a[31:0] >> 11 | fu_data_i.operand_a[31:0] << 21) ^ (fu_data_i.operand_a[31:0] >> 25 | fu_data_i.operand_a[31:0] << 7); + if (CVA6Cfg.IS_XLEN32) begin + assign sbox_in = fu_data_i.operand_b >> {orig_instr_aes[5:4], 3'b000}; + // AES 32-bit final round encryption by applying rotations and the forward sbox to a single byte of rs2 based on the MSB byte of the instruction itself + assign aes32esi_gen = (fu_data_i.operand_a ^ ({24'b0, aes_sbox_fwd( + sbox_in[7:0] + )} << {orig_instr_aes[5:4], 3'b000}) | ({24'b0, aes_sbox_fwd( + sbox_in[7:0] + )} >> (32 - {orig_instr_aes[5:4], 3'b000}))); + // AES 32-bit middle round encryption by applying rotations, forward mix-columns and the forward sbox to a single byte of rs2 based on the MSB byte of the instruction itself + assign aes32esmi_gen = fu_data_i.operand_a ^ ((aes_mixcolumn_fwd( + {24'h000000, aes_sbox_fwd(sbox_in[7:0])} + ) << {orig_instr_aes[5:4], 3'b000}) | (aes_mixcolumn_fwd( + {24'h000000, aes_sbox_fwd(sbox_in[7:0])} + ) >> (32 - {orig_instr_aes[5:4], 3'b000}))); + // AES 32-bit final round decryption by applying rotations and the inverse sbox to a single byte of rs2 based on the MSB byte of the instruction itself + assign aes32dsi_gen = (fu_data_i.operand_a ^ ({24'b0, aes_sbox_inv( + sbox_in[7:0] + )} << {orig_instr_aes[5:4], 3'b000}) | ({24'b0, aes_sbox_inv( + sbox_in[7:0] + )} >> (32 - {orig_instr_aes[5:4], 3'b000}))); + // AES 32-bit middle round decryption by applying rotations, inverse mix-columns and the inverse sbox to a single byte of rs2 based on the MSB byte of the instruction itself + assign aes32dsmi_gen = fu_data_i.operand_a ^ ((aes_mixcolumn_inv( + {24'h000000, aes_sbox_inv(sbox_in[7:0])} + ) << {orig_instr_aes[5:4], 3'b000}) | (aes_mixcolumn_inv( + {24'h000000, aes_sbox_inv(sbox_in[7:0])} + ) >> (32 - {orig_instr_aes[5:4], 3'b000}))); + // SHA512 32-bit shifting and XORing rs1 and rs2 + assign sha512sig0h_gen = (fu_data_i.operand_a >> 1) ^ (fu_data_i.operand_a >> 7) ^ (fu_data_i.operand_a >> 8) ^ (fu_data_i.operand_b << 31) ^ (fu_data_i.operand_b << 24); + assign sha512sig0l_gen = (fu_data_i.operand_a >> 1) ^ (fu_data_i.operand_a >> 7) ^ (fu_data_i.operand_a >> 8) ^ (fu_data_i.operand_b << 31) ^ (fu_data_i.operand_b << 25) ^ (fu_data_i.operand_b << 24); + assign sha512sig1h_gen = (fu_data_i.operand_a << 3) ^ (fu_data_i.operand_a >> 6) ^ (fu_data_i.operand_a >> 19) ^ (fu_data_i.operand_b >> 29) ^ (fu_data_i.operand_b << 13); + assign sha512sig1l_gen = (fu_data_i.operand_a << 3) ^ (fu_data_i.operand_a >> 6) ^ (fu_data_i.operand_a >> 19) ^ (fu_data_i.operand_b >> 29) ^ (fu_data_i.operand_b << 26) ^ (fu_data_i.operand_b << 13); + assign sha512sum0r_gen = (fu_data_i.operand_a << 25) ^ (fu_data_i.operand_a << 30) ^ (fu_data_i.operand_a >> 28) ^ (fu_data_i.operand_b >> 7) ^ (fu_data_i.operand_b >> 2) ^ (fu_data_i.operand_b << 4); + assign sha512sum1r_gen = (fu_data_i.operand_a << 23) ^ (fu_data_i.operand_a >> 14) ^ (fu_data_i.operand_a >> 18) ^ (fu_data_i.operand_b >> 9) ^ (fu_data_i.operand_b << 18) ^ (fu_data_i.operand_b << 14); + end else if (CVA6Cfg.IS_XLEN64) begin + // AES Shift rows forward and inverse step + assign sr = { + fu_data_i.operand_a[31:24], + fu_data_i.operand_b[55:48], + fu_data_i.operand_b[15:8], + fu_data_i.operand_a[39:32], + fu_data_i.operand_b[63:56], + fu_data_i.operand_b[23:16], + fu_data_i.operand_a[47:40], + fu_data_i.operand_a[7:0] + }; + assign sr_inv = { + fu_data_i.operand_b[31:24], + fu_data_i.operand_b[55:48], + fu_data_i.operand_a[15:8], + fu_data_i.operand_a[39:32], + fu_data_i.operand_a[63:56], + fu_data_i.operand_b[23:16], + fu_data_i.operand_b[47:40], + fu_data_i.operand_a[7:0] + }; + // AES 64-bit final round encryption by applying forward shift-rows and the forward sbox to each byte + assign aes64es_gen = { + aes_sbox_fwd(sr[63:56]), + aes_sbox_fwd(sr[55:48]), + aes_sbox_fwd(sr[47:40]), + aes_sbox_fwd(sr[39:32]), + aes_sbox_fwd(sr[31:24]), + aes_sbox_fwd(sr[23:16]), + aes_sbox_fwd(sr[15:8]), + aes_sbox_fwd(sr[7:0]) + }; + // AES 64-bit middle round encryption by applying forward shift-rows, forward sbox and forward mix-columns to all bytes + assign aes64esm_gen = { + aes_mixcolumn_fwd(aes64es_gen[63:32]), aes_mixcolumn_fwd(aes64es_gen[31:0]) + }; + // AES 64-bit final round decryption by applying inverse shift-rows and the inverse sbox to each byte + assign aes64ds_gen = { + aes_sbox_inv(sr_inv[63:56]), + aes_sbox_inv(sr_inv[55:48]), + aes_sbox_inv(sr_inv[47:40]), + aes_sbox_inv(sr_inv[39:32]), + aes_sbox_inv(sr_inv[31:24]), + aes_sbox_inv(sr_inv[23:16]), + aes_sbox_inv(sr_inv[15:8]), + aes_sbox_inv(sr_inv[7:0]) + }; + // AES 64-bit middle round decryption by applying inverse shift-rows, inverse sbox and inverse mix-columns to all bytes + assign aes64dsm_gen = { + aes_mixcolumn_inv(aes64ds_gen[63:32]), aes_mixcolumn_inv(aes64ds_gen[31:0]) + }; + // AES 64-bit keySchedule decryption by applying inverse mix-columns on rs1 + assign aes64im_gen = { + aes_mixcolumn_inv(fu_data_i.operand_a[63:32]), aes_mixcolumn_inv(fu_data_i.operand_a[31:0]) + }; + // AES Key Schedule part by XORing different slices of rs1 and rs2 + assign aes64ks2_gen = { + (fu_data_i.operand_a[63:32] ^ fu_data_i.operand_b[31:0] ^ fu_data_i.operand_b[63:32]), + (fu_data_i.operand_a[63:32] ^ fu_data_i.operand_b[31:0]) + }; + // AES Key Schedule part by substituting round constant based on round number(from instruction), rotations and forward subword substitutions + assign aes64ks1i_gen = (orig_instr_aes[3:0] <= 4'hA) ? {((aes_subword_fwd( + (orig_instr_aes[3:0] == 4'hA) ? fu_data_i.operand_a[63:32] : ((fu_data_i.operand_a[63:32] >> 8) | (fu_data_i.operand_a[63:32] << 24)) + )) ^ (aes_decode_rcon( + orig_instr_aes[3:0] + ))), ((aes_subword_fwd( + (orig_instr_aes[3:0] == 4'hA) ? fu_data_i.operand_a[63:32] : ((fu_data_i.operand_a[63:32] >> 8) | (fu_data_i.operand_a[63:32] << 24)) + )) ^ (aes_decode_rcon( + orig_instr_aes[3:0] + )))} : 64'h0; + // SHA512 64bit rotating, shifting and XORing rs1 + assign sha512sig0_gen = (fu_data_i.operand_a >> 1 | fu_data_i.operand_a << 63) ^ (fu_data_i.operand_a >> 8 | fu_data_i.operand_a << 56) ^ (fu_data_i.operand_a >> 7); + assign sha512sig1_gen = (fu_data_i.operand_a >> 19 | fu_data_i.operand_a << 45) ^ (fu_data_i.operand_a >> 61 | fu_data_i.operand_a << 3) ^ (fu_data_i.operand_a >> 6); + assign sha512sum0_gen = (fu_data_i.operand_a >> 28 | fu_data_i.operand_a << 36) ^ (fu_data_i.operand_a >> 34 | fu_data_i.operand_a << 30) ^ (fu_data_i.operand_a >> 39 | fu_data_i.operand_a << 25); + assign sha512sum1_gen = (fu_data_i.operand_a >> 14 | fu_data_i.operand_a << 50) ^ (fu_data_i.operand_a >> 18 | fu_data_i.operand_a << 46) ^ (fu_data_i.operand_a >> 41 | fu_data_i.operand_a << 23); + end + end + + // ----------- + // Result MUX + // ----------- + always_comb begin + result_o = '0; + // AES instructions + if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin + if (CVA6Cfg.IS_XLEN32) begin + unique case (fu_data_i.operation) + AES32ESI: result_o = aes32esi_gen; + AES32ESMI: result_o = aes32esmi_gen; + AES32DSI: result_o = aes32dsi_gen; + AES32DSMI: result_o = aes32dsmi_gen; + SHA256SIG0: result_o = sha256sig0_gen; + SHA256SIG1: result_o = sha256sig1_gen; + SHA256SUM0: result_o = sha256sum0_gen; + SHA256SUM1: result_o = sha256sum1_gen; + SHA512SIG0H: result_o = sha512sig0h_gen; + SHA512SIG0L: result_o = sha512sig0l_gen; + SHA512SIG1H: result_o = sha512sig1h_gen; + SHA512SIG1L: result_o = sha512sig1l_gen; + SHA512SUM0R: result_o = sha512sum0r_gen; + SHA512SUM1R: result_o = sha512sum1r_gen; + default: ; + endcase + end + if (CVA6Cfg.IS_XLEN64) begin + unique case (fu_data_i.operation) + AES64ES: result_o = aes64es_gen; + AES64ESM: result_o = aes64esm_gen; + AES64DS: result_o = aes64ds_gen; + AES64DSM: result_o = aes64dsm_gen; + AES64IM: result_o = aes64im_gen; + AES64KS1I: result_o = aes64ks1i_gen; + AES64KS2: result_o = aes64ks2_gen; + SHA256SIG0: result_o = {{32{sha256sig0_gen[31]}}, sha256sig0_gen}; + SHA256SIG1: result_o = {{32{sha256sig1_gen[31]}}, sha256sig1_gen}; + SHA256SUM0: result_o = {{32{sha256sum0_gen[31]}}, sha256sum0_gen}; + SHA256SUM1: result_o = {{32{sha256sum1_gen[31]}}, sha256sum1_gen}; + SHA512SIG0: result_o = sha512sig0_gen; + SHA512SIG1: result_o = sha512sig1_gen; + SHA512SUM0: result_o = sha512sum0_gen; + SHA512SUM1: result_o = sha512sum1_gen; + default: ; + endcase + end + end + end +endmodule diff --git a/core/alu.sv b/core/alu.sv index 9f69f6ef93f..2a83c8c4a03 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -31,14 +31,18 @@ module alu input logic rst_ni, // FU data needed to execute instruction - ISSUE_STAGE input fu_data_t fu_data_i, + // FU data needed to execute CPOP/CPOPW - ISSUE_STAGE + input fu_data_t fu_data_cpop_i, // ALU result - ISSUE_STAGE output logic [CVA6Cfg.XLEN-1:0] result_o, // ALU branch compare result - branch_unit output logic alu_branch_res_o ); + logic [CVA6Cfg.XLEN-1:0] operand_a; logic [CVA6Cfg.XLEN-1:0] operand_a_rev; logic [ 31:0] operand_a_rev32; + logic [CVA6Cfg.XLEN-1:0] operand_b; logic [ CVA6Cfg.XLEN:0] operand_b_neg; logic [CVA6Cfg.XLEN+1:0] adder_result_ext_o; logic less; // handles both signed and unsigned forms @@ -54,13 +58,18 @@ module alu logic [CVA6Cfg.XLEN-1:0] brev8_reversed; logic [ 31:0] unzip_gen; logic [ 31:0] zip_gen; + logic [CVA6Cfg.XLEN-1:0] xperm8_result; + logic [CVA6Cfg.XLEN-1:0] xperm4_result; + + assign operand_a = fu_data_i.operand_a; + assign operand_b = fu_data_i.operand_b; + // bit reverse operand_a for left shifts and bit counting generate genvar k; - for (k = 0; k < CVA6Cfg.XLEN; k++) - assign operand_a_rev[k] = fu_data_i.operand_a[CVA6Cfg.XLEN-1-k]; + for (k = 0; k < CVA6Cfg.XLEN; k++) assign operand_a_rev[k] = operand_a[CVA6Cfg.XLEN-1-k]; - for (k = 0; k < 32; k++) assign operand_a_rev32[k] = fu_data_i.operand_a[31-k]; + for (k = 0; k < 32; k++) assign operand_a_rev32[k] = operand_a[31-k]; endgenerate // ------ @@ -71,27 +80,30 @@ module alu logic [CVA6Cfg.XLEN:0] adder_in_a, adder_in_b; logic [CVA6Cfg.XLEN-1:0] adder_result; logic [CVA6Cfg.XLEN-1:0] operand_a_bitmanip, bit_indx; + logic [CVA6Cfg.XLEN-1:0] operand_a_cpop; assign adder_op_b_negate = fu_data_i.operation inside {EQ, NE, SUB, SUBW, ANDN, ORN, XNOR}; always_comb begin - operand_a_bitmanip = fu_data_i.operand_a; + operand_a_bitmanip = operand_a; + operand_a_cpop = fu_data_cpop_i.operand_a; if (CVA6Cfg.RVB) begin if (CVA6Cfg.IS_XLEN64) begin unique case (fu_data_i.operation) - SH1ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 1; - SH2ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 2; - SH3ADDUW: operand_a_bitmanip = fu_data_i.operand_a[31:0] << 3; - CTZW: operand_a_bitmanip = operand_a_rev32; - ADDUW, CPOPW, CLZW: operand_a_bitmanip = fu_data_i.operand_a[31:0]; - default: ; + SH1ADDUW: operand_a_bitmanip = operand_a[31:0] << 1; + SH2ADDUW: operand_a_bitmanip = operand_a[31:0] << 2; + SH3ADDUW: operand_a_bitmanip = operand_a[31:0] << 3; + CTZW: operand_a_bitmanip = operand_a_rev32; + ADDUW, CLZW: operand_a_bitmanip = operand_a[31:0]; + CPOPW: operand_a_cpop = fu_data_cpop_i.operand_a[31:0]; + default: ; endcase end unique case (fu_data_i.operation) - SH1ADD: operand_a_bitmanip = fu_data_i.operand_a << 1; - SH2ADD: operand_a_bitmanip = fu_data_i.operand_a << 2; - SH3ADD: operand_a_bitmanip = fu_data_i.operand_a << 3; + SH1ADD: operand_a_bitmanip = operand_a << 1; + SH2ADD: operand_a_bitmanip = operand_a << 2; + SH3ADD: operand_a_bitmanip = operand_a << 3; CTZ: operand_a_bitmanip = operand_a_rev; default: ; endcase @@ -102,7 +114,7 @@ module alu assign adder_in_a = {operand_a_bitmanip, 1'b1}; // prepare operand b - assign operand_b_neg = {fu_data_i.operand_b, 1'b0} ^ {CVA6Cfg.XLEN + 1{adder_op_b_negate}}; + assign operand_b_neg = {operand_b, 1'b0} ^ {CVA6Cfg.XLEN + 1{adder_op_b_negate}}; assign adder_in_b = operand_b_neg; // actual adder @@ -147,7 +159,7 @@ module alu logic [CVA6Cfg.XLEN-1:0] shift_left_result; logic [ 31:0] shift_left_result32; - assign shift_amt = fu_data_i.operand_b; + assign shift_amt = operand_b; assign shift_left = (fu_data_i.operation == SLL) | (CVA6Cfg.IS_XLEN64 && fu_data_i.operation == SLLW); @@ -158,8 +170,8 @@ module alu logic [32:0] shift_op_a_32; // choose the bit reversed or the normal input for shift operand a - assign shift_op_a = shift_left ? operand_a_rev : fu_data_i.operand_a; - assign shift_op_a32 = shift_left ? operand_a_rev32 : fu_data_i.operand_a[31:0]; + assign shift_op_a = shift_left ? operand_a_rev : operand_a; + assign shift_op_a32 = shift_left ? operand_a_rev32 : operand_a[31:0]; assign shift_op_a_64 = {shift_arithmetic & shift_op_a[CVA6Cfg.XLEN-1], shift_op_a}; assign shift_op_a_32 = {shift_arithmetic & shift_op_a[31], shift_op_a32}; @@ -195,8 +207,8 @@ module alu (fu_data_i.operation == MIN)) sgn = 1'b1; - less = ($signed({sgn & fu_data_i.operand_a[CVA6Cfg.XLEN-1], fu_data_i.operand_a}) < - $signed({sgn & fu_data_i.operand_b[CVA6Cfg.XLEN-1], fu_data_i.operand_b})); + less = ($signed({sgn & operand_a[CVA6Cfg.XLEN-1], operand_a}) < + $signed({sgn & operand_b[CVA6Cfg.XLEN-1], operand_b})); end if (CVA6Cfg.RVB) begin : gen_bitmanip @@ -205,7 +217,7 @@ module alu popcount #( .INPUT_WIDTH(CVA6Cfg.XLEN) ) i_cpop_count ( - .data_i (operand_a_bitmanip), + .data_i (operand_a_cpop), .popcount_o(cpop) ); @@ -234,31 +246,19 @@ module alu if (CVA6Cfg.RVB) begin : gen_orcbw_rev8w_results assign orcbw = { - {8{|fu_data_i.operand_a[31:24]}}, - {8{|fu_data_i.operand_a[23:16]}}, - {8{|fu_data_i.operand_a[15:8]}}, - {8{|fu_data_i.operand_a[7:0]}} - }; - assign rev8w = { - {fu_data_i.operand_a[7:0]}, - {fu_data_i.operand_a[15:8]}, - {fu_data_i.operand_a[23:16]}, - {fu_data_i.operand_a[31:24]} + {8{|operand_a[31:24]}}, {8{|operand_a[23:16]}}, {8{|operand_a[15:8]}}, {8{|operand_a[7:0]}} }; + assign rev8w = {{operand_a[7:0]}, {operand_a[15:8]}, {operand_a[23:16]}, {operand_a[31:24]}}; if (CVA6Cfg.IS_XLEN64) begin : gen_64b assign orcbw_result = { - {8{|fu_data_i.operand_a[63:56]}}, - {8{|fu_data_i.operand_a[55:48]}}, - {8{|fu_data_i.operand_a[47:40]}}, - {8{|fu_data_i.operand_a[39:32]}}, + {8{|operand_a[63:56]}}, + {8{|operand_a[55:48]}}, + {8{|operand_a[47:40]}}, + {8{|operand_a[39:32]}}, orcbw }; assign rev8w_result = { - rev8w, - {fu_data_i.operand_a[39:32]}, - {fu_data_i.operand_a[47:40]}, - {fu_data_i.operand_a[55:48]}, - {fu_data_i.operand_a[63:56]} + rev8w, {operand_a[39:32]}, {operand_a[47:40]}, {operand_a[55:48]}, {operand_a[63:56]} }; end else begin : gen_32b assign orcbw_result = orcbw; @@ -268,23 +268,29 @@ module alu // ZKN gen block if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : zkn_gen_block - genvar i, m, n; - // Generate brev8_reversed by reversing bits within each byte - for (i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_gen + genvar i, m, n, q; + for (i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_xperm8_gen + // Generating xperm8_result by extracting bytes from operand a based on indices from operand b + assign xperm8_result[i << 3 +: 8] = (operand_b[i << 3 +: 8] < (CVA6Cfg.XLEN / 8)) ? operand_a[operand_b[i << 3 +: 8] << 3 +: 8] : 8'b0; + // Generate brev8_reversed by reversing bits within each byte for (m = 0; m < 8; m++) begin : reverse_bits // Reversing the order of bits within a single byte - assign brev8_reversed[(i<<3)+m] = fu_data_i.operand_a[(i<<3)+(7-m)]; + assign brev8_reversed[(i<<3)+m] = operand_a[(i<<3)+(7-m)]; end end - // Generate zip and unzip results + for (q = 0; q < (CVA6Cfg.XLEN / 4); q++) begin : xperm4_gen + // Generating xperm4_result by extracting nibbles from operand a based on indices from operand b + assign xperm4_result[q << 2 +: 4] = (operand_b[q << 2 +: 4] < (CVA6Cfg.XLEN / 4)) ? operand_a[{2'b0, operand_b[q << 2 +: 4]} << 2 +: 4] : 4'b0; + end if (CVA6Cfg.IS_XLEN32) begin + // Generate zip and unzip results for (n = 0; n < 16; n++) begin : zip_unzip_gen // Assigning lower and upper half of operand into the even and odd positions of result - assign zip_gen[n<<1] = fu_data_i.operand_a[n]; - assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+16]; + assign zip_gen[n<<1] = operand_a[n]; + assign zip_gen[(n<<1)+1] = operand_a[n+16]; // Assigning even and odd bits of operand into lower and upper halves of result - assign unzip_gen[n] = fu_data_i.operand_a[n<<1]; - assign unzip_gen[n+16] = fu_data_i.operand_a[(n<<1)+1]; + assign unzip_gen[n] = operand_a[n<<1]; + assign unzip_gen[n+16] = operand_a[(n<<1)+1]; end end end @@ -307,13 +313,13 @@ module alu end unique case (fu_data_i.operation) // Standard Operations - ANDL, ANDN: result_o = fu_data_i.operand_a & operand_b_neg[CVA6Cfg.XLEN:1]; - ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[CVA6Cfg.XLEN:1]; - XORL, XNOR: result_o = fu_data_i.operand_a ^ operand_b_neg[CVA6Cfg.XLEN:1]; + ANDL, ANDN: result_o = operand_a & operand_b_neg[CVA6Cfg.XLEN:1]; + ORL, ORN: result_o = operand_a | operand_b_neg[CVA6Cfg.XLEN:1]; + XORL, XNOR: result_o = operand_a ^ operand_b_neg[CVA6Cfg.XLEN:1]; // Adder Operations ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD: result_o = adder_result; // Shift Operations - SLL, SRL, SRA: result_o = (CVA6Cfg.IS_XLEN64) ? shift_result : shift_result32; + SLL, SRL, SRA: result_o = CVA6Cfg.IS_XLEN64 ? shift_result : shift_result32; // Comparison Operations SLTS, SLTU: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, less}; default: ; // default case to suppress unique warning @@ -321,11 +327,11 @@ module alu if (CVA6Cfg.RVB) begin // Index for Bitwise Rotation - bit_indx = 1 << (fu_data_i.operand_b & (CVA6Cfg.XLEN - 1)); + bit_indx = 1 << (operand_b & (CVA6Cfg.XLEN - 1)); if (CVA6Cfg.IS_XLEN64) begin // rolw, roriw, rorw - rolw = ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> (CVA6Cfg.XLEN-32-fu_data_i.operand_b[4:0])); - rorw = ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (CVA6Cfg.XLEN-32-fu_data_i.operand_b[4:0])); + rolw = ({{CVA6Cfg.XLEN-32{1'b0}},operand_a[31:0]} << operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},operand_a[31:0]} >> (CVA6Cfg.XLEN-32-operand_b[4:0])); + rorw = ({{CVA6Cfg.XLEN-32{1'b0}},operand_a[31:0]} >> operand_b[4:0]) | ({{CVA6Cfg.XLEN-32{1'b0}},operand_a[31:0]} << (CVA6Cfg.XLEN-32-operand_b[4:0])); unique case (fu_data_i.operation) CLZW, CTZW: result_o = (lz_tz_wempty) ? 32 : {{CVA6Cfg.XLEN - 5{1'b0}}, lz_tz_wcount}; // change @@ -336,16 +342,16 @@ module alu end unique case (fu_data_i.operation) // Integer minimum/maximum - MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a; - MAXU: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a; - MIN: result_o = ~less ? fu_data_i.operand_b : fu_data_i.operand_a; - MINU: result_o = ~less ? fu_data_i.operand_b : fu_data_i.operand_a; + MAX: result_o = less ? operand_b : operand_a; + MAXU: result_o = less ? operand_b : operand_a; + MIN: result_o = ~less ? operand_b : operand_a; + MINU: result_o = ~less ? operand_b : operand_a; // Single bit instructions operations - BCLR, BCLRI: result_o = fu_data_i.operand_a & ~bit_indx; - BEXT, BEXTI: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, |(fu_data_i.operand_a & bit_indx)}; - BINV, BINVI: result_o = fu_data_i.operand_a ^ bit_indx; - BSET, BSETI: result_o = fu_data_i.operand_a | bit_indx; + BCLR, BCLRI: result_o = operand_a & ~bit_indx; + BEXT, BEXTI: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, |(operand_a & bit_indx)}; + BINV, BINVI: result_o = operand_a ^ bit_indx; + BSET, BSETI: result_o = operand_a | bit_indx; // Count Leading/Trailing Zeros CLZ, CTZ: @@ -356,31 +362,31 @@ module alu CPOP, CPOPW: result_o = {{(CVA6Cfg.XLEN - ($clog2(CVA6Cfg.XLEN) + 1)) {1'b0}}, cpop}; // Sign and Zero Extend - SEXTB: result_o = {{CVA6Cfg.XLEN - 8{fu_data_i.operand_a[7]}}, fu_data_i.operand_a[7:0]}; - SEXTH: result_o = {{CVA6Cfg.XLEN - 16{fu_data_i.operand_a[15]}}, fu_data_i.operand_a[15:0]}; - ZEXTH: result_o = {{CVA6Cfg.XLEN - 16{1'b0}}, fu_data_i.operand_a[15:0]}; + SEXTB: result_o = {{CVA6Cfg.XLEN - 8{operand_a[7]}}, operand_a[7:0]}; + SEXTH: result_o = {{CVA6Cfg.XLEN - 16{operand_a[15]}}, operand_a[15:0]}; + ZEXTH: result_o = {{CVA6Cfg.XLEN - 16{1'b0}}, operand_a[15:0]}; // Bitwise Rotation ROL: - result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a << fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a >> (CVA6Cfg.XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a << fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a >> (CVA6Cfg.XLEN-fu_data_i.operand_b[4:0]))); + result_o = CVA6Cfg.IS_XLEN64 ? ((operand_a << operand_b[5:0]) | (operand_a >> (CVA6Cfg.XLEN-operand_b[5:0]))) : ((operand_a << operand_b[4:0]) | (operand_a >> (CVA6Cfg.XLEN-operand_b[4:0]))); ROR, RORI: - result_o = (CVA6Cfg.IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (CVA6Cfg.XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (CVA6Cfg.XLEN-fu_data_i.operand_b[4:0]))); + result_o = CVA6Cfg.IS_XLEN64 ? ((operand_a >> operand_b[5:0]) | (operand_a << (CVA6Cfg.XLEN-operand_b[5:0]))) : ((operand_a >> operand_b[4:0]) | (operand_a << (CVA6Cfg.XLEN-operand_b[4:0]))); ORCB: result_o = orcbw_result; REV8: result_o = rev8w_result; default: if (fu_data_i.operation == SLLIUW && CVA6Cfg.IS_XLEN64) - result_o = {{CVA6Cfg.XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned + result_o = {{CVA6Cfg.XLEN-32{1'b0}}, operand_a[31:0]} << operand_b[5:0]; // Left Shift 32 bit unsigned endcase end if (CVA6Cfg.RVZiCond) begin unique case (fu_data_i.operation) CZERO_EQZ: - result_o = (|fu_data_i.operand_b) ? fu_data_i.operand_a : '0; // move zero to rd if rs2 is equal to zero else rs1 + result_o = (|operand_b) ? operand_a : '0; // move zero to rd if rs2 is equal to zero else rs1 CZERO_NEZ: - result_o = (|fu_data_i.operand_b) ? '0 : fu_data_i.operand_a; // move zero to rd if rs2 is nonzero else rs1 + result_o = (|operand_b) ? '0 : operand_a; // move zero to rd if rs2 is nonzero else rs1 default: ; // default case to suppress unique warning endcase end @@ -388,18 +394,20 @@ module alu if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin unique case (fu_data_i.operation) PACK: - result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]}); + result_o = CVA6Cfg.IS_XLEN32 ? ({operand_b[15:0], operand_a[15:0]}) : ({operand_b[31:0], operand_a[31:0]}); PACK_H: - result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}); + result_o = CVA6Cfg.IS_XLEN32 ? ({16'b0, operand_b[7:0], operand_a[7:0]}) : ({48'b0, operand_b[7:0], operand_a[7:0]}); BREV8: result_o = brev8_reversed; + XPERM8: result_o = xperm8_result; + XPERM4: result_o = xperm4_result; default: ; endcase if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) - result_o = { - {32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]} - }; - if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen; - if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen; + result_o = {{32{operand_b[15]}}, {operand_b[15:0]}, {operand_a[15:0]}}; + if (CVA6Cfg.IS_XLEN32) begin + if (fu_data_i.operation == UNZIP) result_o = unzip_gen; + if (fu_data_i.operation == ZIP) result_o = zip_gen; + end end end endmodule diff --git a/core/alu_wrapper.sv b/core/alu_wrapper.sv new file mode 100644 index 00000000000..461b7d0898e --- /dev/null +++ b/core/alu_wrapper.sv @@ -0,0 +1,71 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Original authors: Gianmarco Ottavi, University of Bologna +// Riccardo Tedeschi, University of Bologna +// Description: ALU(s) wrapper + +module alu_wrapper + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input alu_bypass_t alu_bypass_i, + input fu_data_t [CVA6Cfg.NrALUs-1:0] fu_data_i, + output logic [CVA6Cfg.NrALUs-1:0][CVA6Cfg.XLEN-1:0] result_o, + output logic alu_branch_res_o +); + + alu #( + .CVA6Cfg (CVA6Cfg), + .HasBranch(1'b1), + .fu_data_t(fu_data_t) + ) alu_i ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .fu_data_i (fu_data_i[0]), + .fu_data_cpop_i (fu_data_i[0]), + .result_o (result_o[0]), + .alu_branch_res_o(alu_branch_res_o) + ); + + if (CVA6Cfg.SuperscalarEn) begin : gen_alu2 + + fu_data_t fu_data_bypass; + + always_comb begin + fu_data_bypass = fu_data_i[1]; + + if (alu_bypass_i.rs1_from_rd) begin + fu_data_bypass.operand_a = result_o[0]; + end + if (alu_bypass_i.rs2_from_rd) begin + fu_data_bypass.operand_b = result_o[0]; + end + end + + alu #( + .CVA6Cfg (CVA6Cfg), + .HasBranch(1'b0), + .fu_data_t(fu_data_t) + ) alu2_i ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .fu_data_i (fu_data_bypass), + .fu_data_cpop_i (fu_data_i[1]), + .result_o (result_o[1]), + .alu_branch_res_o( /* Unconnected */) + ); + end + +endmodule diff --git a/core/amo_buffer.sv b/core/amo_buffer.sv index 8aca2a13eb0..d489dde5017 100644 --- a/core/amo_buffer.sv +++ b/core/amo_buffer.sv @@ -11,7 +11,7 @@ // Author: Florian Zaruba, ETH Zurich // Date: 20.09.2018 // Description: Buffers AMO requests -// This unit buffers an atomic memory operations for the cache subsyste. +// This unit buffers an atomic memory operation for the cache subsystem. // Furthermore it handles interfacing with the commit stage module amo_buffer #( @@ -28,10 +28,10 @@ module amo_buffer #( input logic [CVA6Cfg.XLEN-1:0] data_i, // data which is placed in the queue input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write) // D$ - output ariane_pkg::amo_req_t amo_req_o, // request to cache subsytem + output ariane_pkg::amo_req_t amo_req_o, // request to cache subsystem input ariane_pkg::amo_resp_t amo_resp_i, // response from cache subsystem // Auxiliary signals - input logic amo_valid_commit_i, // We have a vaild AMO in the commit stage + input logic amo_valid_commit_i, // We have a valid AMO in the commit stage input logic no_st_pending_i // there is currently no store pending anymore ); logic flush_amo_buffer; diff --git a/core/ariane_regfile.sv b/core/ariane_regfile.sv deleted file mode 100644 index 653b7ede4e7..00000000000 --- a/core/ariane_regfile.sv +++ /dev/null @@ -1,114 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Author: Antonio Pullini - pullinia@iis.ee.ethz.ch -// -// Additional contributions by: -// Sven Stucki - svstucki@student.ethz.ch -// Markus Wegmann - markus.wegmann@technokrat.ch -// -// Design Name: RISC-V register file -// Project Name: zero-riscy -// Language: SystemVerilog -// -// Description: Register file with 31 or 15x 32 bit wide registers. -// Register 0 is fixed to 0. This register file is based on -// latches and is thus smaller than the flip-flop based RF. -// - -module ariane_regfile_lol #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter int unsigned DATA_WIDTH = 32, - parameter int unsigned NR_READ_PORTS = 2, - parameter bit ZERO_REG_ZERO = 0 -) ( - // clock and reset - input logic clk_i, - input logic rst_ni, - // disable clock gates for testing - input logic test_en_i, - // read port - input logic [ NR_READ_PORTS-1:0][ 4:0] raddr_i, - output logic [ NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, - // write port - input logic [CVA6Cfg.NrCommitPorts-1:0][ 4:0] waddr_i, - input logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i, - input logic [CVA6Cfg.NrCommitPorts-1:0] we_i -); - - localparam ADDR_WIDTH = 5; - localparam NUM_WORDS = 2 ** ADDR_WIDTH; - - logic [NUM_WORDS-1:ZERO_REG_ZERO] mem_clocks; - - logic [ DATA_WIDTH-1:0] mem [NUM_WORDS]; - logic [CVA6Cfg.NrCommitPorts-1:0][NUM_WORDS-1:1] waddr_onehot, waddr_onehot_q; - logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_q; - - - // decode addresses - for (genvar i = 0; i < NR_READ_PORTS; i++) assign rdata_o[i] = mem[raddr_i[i][ADDR_WIDTH-1:0]]; - - always_ff @(posedge clk_i, negedge rst_ni) begin : sample_waddr - if (~rst_ni) begin - wdata_q <= '0; - end else begin - for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) - // enable flipflop will most probably infer clock gating - if (we_i[i]) begin - wdata_q[i] <= wdata_i[i]; - end - waddr_onehot_q <= waddr_onehot; - end - end - - // WRITE : Write Address Decoder (WAD), combinatorial process - always_comb begin : decode_write_addess - for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin - for (int unsigned j = 1; j < NUM_WORDS; j++) begin - if (we_i[i] && (waddr_i[i] == j)) waddr_onehot[i][j] = 1'b1; - else waddr_onehot[i][j] = 1'b0; - end - end - end - - // WRITE : Clock gating (if integrated clock-gating cells are available) - for (genvar x = ZERO_REG_ZERO; x < NUM_WORDS; x++) begin - - logic [CVA6Cfg.NrCommitPorts-1:0] waddr_ored; - - for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) assign waddr_ored[i] = waddr_onehot[i][x]; - - cluster_clock_gating i_cg ( - .clk_i (clk_i), - .en_i (|waddr_ored), - .test_en_i(test_en_i), - .clk_o (mem_clocks[x]) - ); - end - - // Generate M = WORDS sequential processes, each of which describes one - // word of the memory. The processes are synchronized with the clocks - // ClocksxC(i), i = 0, 1, ..., M-1 - // Use active low, i.e. transparent on low latches as storage elements - // Data is sampled on rising clock edge - - // Integer registers - always_latch begin : latch_wdata - // Note: The assignment has to be done inside this process or Modelsim complains about it - if (ZERO_REG_ZERO) mem[0] = '0; - - for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin - for (int unsigned k = ZERO_REG_ZERO; k < NUM_WORDS; k++) begin - if (mem_clocks[k] && waddr_onehot_q[i][k]) mem[k] = wdata_q[i]; - end - end - end -endmodule diff --git a/core/ariane_regfile_fpga.sv b/core/ariane_regfile_fpga.sv index 9169482e3a3..f12cc7b3d2b 100644 --- a/core/ariane_regfile_fpga.sv +++ b/core/ariane_regfile_fpga.sv @@ -1,5 +1,5 @@ // Copyright 2018 ETH Zurich and University of Bologna. -// Copyright 2024 - PlanV Technologies for additionnal contribution. +// Copyright 2024 - PlanV Technologies for additional contribution. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at @@ -23,7 +23,7 @@ // sync-write port, each with a parametrized number of async-read ports. // Read-accesses are multiplexed from the relevant block depending on which block // was last written to. For that purpose an additional array of registers is -// maintained keeping track of write acesses. +// maintained keeping track of write accesses. // module ariane_regfile_fpga #( @@ -62,7 +62,7 @@ module ariane_regfile_fpga #( logic [NR_READ_PORTS-1:0][4:0] raddr_q; logic [NR_READ_PORTS-1:0][4:0] raddr; - // write adress decoder (for block selector) + // write address decoder (for block selector) always_comb begin for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin for (int unsigned i = 0; i < NUM_WORDS; i++) begin diff --git a/core/branch_unit.sv b/core/branch_unit.sv index 097416756db..9c91c60dda6 100644 --- a/core/branch_unit.sv +++ b/core/branch_unit.sv @@ -100,7 +100,7 @@ module branch_unit #( end if (fu_data_i.operation == ariane_pkg::JALR // check if the address of the jump register is correct and that we actually predicted - && (branch_predict_i.cf == ariane_pkg::NoCF || target_address != branch_predict_i.predict_address)) begin + && (!branch_predict_i.valid || target_address != branch_predict_i.predict_address)) begin resolved_branch_o.is_mispredict = 1'b1; // update BTB only if this wasn't a return if (branch_predict_i.cf != ariane_pkg::Return) @@ -120,7 +120,9 @@ module branch_unit #( branch_exception_o.cause = riscv::INSTR_ADDR_MISALIGNED; branch_exception_o.valid = 1'b0; if (CVA6Cfg.TvalEn) - branch_exception_o.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; + branch_exception_o.tval = { + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{target_address[CVA6Cfg.VLEN-1]}}, target_address + }; else branch_exception_o.tval = '0; branch_exception_o.tval2 = {CVA6Cfg.GPLEN{1'b0}}; branch_exception_o.tinst = '0; diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv index 3ee65421b7d..bdaa2dc3cb1 100644 --- a/core/cache_subsystem/axi_adapter.sv +++ b/core/cache_subsystem/axi_adapter.sv @@ -250,6 +250,7 @@ module axi_adapter #( // ~> from single write WAIT_AW_READY: begin axi_req_o.aw_valid = 1'b1; + axi_req_o.aw.lock = amo_i == ariane_pkg::AMO_SC; if (axi_resp_i.aw_ready) begin gnt_o = 1'b1; diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv index 8091e6a8235..a76c62e06bc 100644 --- a/core/cache_subsystem/cache_ctrl.sv +++ b/core/cache_subsystem/cache_ctrl.sv @@ -128,6 +128,7 @@ module cache_ctrl req_port_o.data_rvalid = 1'b0; req_port_o.data_rdata = '0; req_port_o.data_rid = mem_req_q.id; + req_port_o.data_ruser = '0; miss_req_o = '0; mshr_addr_o = '0; // Memory array communication diff --git a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv index d9e9f233166..b111944c0b0 100644 --- a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv +++ b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv @@ -113,6 +113,7 @@ module cva6_hpdcache_if_adapter assign cva6_req_o.data_rvalid = hpdcache_rsp_valid_i; assign cva6_req_o.data_rdata = hpdcache_rsp_i.rdata; assign cva6_req_o.data_rid = hpdcache_rsp_i.tid; + assign cva6_req_o.data_error = hpdcache_rsp_i.error; assign cva6_req_o.data_gnt = hpdcache_req_ready_i; // Assertions @@ -145,6 +146,7 @@ module cva6_hpdcache_if_adapter flush_fsm_t flush_fsm_q, flush_fsm_d; logic forward_store, forward_amo, forward_flush; + hpdcache_pkg::hpdcache_req_op_t store_op; // DCACHE flush request // {{{ @@ -185,6 +187,23 @@ module cva6_hpdcache_if_adapter end // }}} + // CBO logic + // {{{ + always_comb begin : store_cmo_comb + store_op = hpdcache_pkg::HPDCACHE_REQ_STORE; + + if (CVA6Cfg.RVZiCbom) begin + case (cva6_req_i.cbo_op) + ariane_pkg::CBO_INVAL: store_op = hpdcache_pkg::HPDCACHE_REQ_CMO_INVAL_NLINE; + ariane_pkg::CBO_CLEAN: store_op = hpdcache_pkg::HPDCACHE_REQ_CMO_FLUSH_NLINE; + ariane_pkg::CBO_FLUSH: store_op = hpdcache_pkg::HPDCACHE_REQ_CMO_FLUSH_INVAL_NLINE; + default: ; // store - above + endcase + end + end + // }}} + + // AMO logic // {{{ always_comb begin : amo_op_comb @@ -221,7 +240,7 @@ module cva6_hpdcache_if_adapter assign amo_is_word = (cva6_amo_req_i.size == 2'b10); assign amo_is_word_hi = cva6_amo_req_i.operand_a[2]; - if (CVA6Cfg.XLEN == 64) begin : amo_data_64_gen + if (CVA6Cfg.IS_XLEN64) begin : amo_data_64_gen assign amo_data = amo_is_word ? {2{cva6_amo_req_i.operand_b[0+:32]}} : cva6_amo_req_i.operand_b; assign amo_data_be = amo_is_word_hi ? 8'hf0 : amo_is_word ? 8'h0f : 8'hff; end else begin : amo_data_32_gen @@ -250,12 +269,15 @@ module cva6_hpdcache_if_adapter assign hpdcache_req_store = '{ addr_offset: cva6_req_i.address_index, wdata: cva6_req_i.data_wdata, - op: hpdcache_pkg::HPDCACHE_REQ_STORE, + op: store_op, be: cva6_req_i.data_be, size: cva6_req_i.data_size, sid: hpdcache_req_sid_i, tid: '0, - need_rsp: 1'b0, + need_rsp: + store_op + != + hpdcache_pkg::HPDCACHE_REQ_STORE, // CMO requests need a response phys_indexed: 1'b1, addr_tag: cva6_req_i.address_tag, pma: '{ @@ -305,7 +327,8 @@ module cva6_hpdcache_if_adapter // Response forwarding // {{{ - if (CVA6Cfg.XLEN == 64) begin : amo_resp_64_gen + ariane_pkg::amo_resp_t cva6_amo_resp; + if (CVA6Cfg.IS_XLEN64) begin : amo_resp_64_gen assign amo_resp_word = amo_is_word_hi ? hpdcache_rsp_i.rdata[0][32 +: 32] : hpdcache_rsp_i.rdata[0][0 +: 32]; @@ -318,18 +341,25 @@ module cva6_hpdcache_if_adapter assign cva6_req_o.data_rid = hpdcache_rsp_i.tid; assign cva6_req_o.data_gnt = hpdcache_req_ready_i; - assign cva6_amo_resp_o.ack = hpdcache_rsp_valid_i && (hpdcache_rsp_i.tid == '1); - assign cva6_amo_resp_o.result = amo_is_word ? {{32{amo_resp_word[31]}}, amo_resp_word} - : hpdcache_rsp_i.rdata[0]; + assign cva6_amo_resp.ack = hpdcache_rsp_valid_i && (hpdcache_rsp_i.tid == '1); + assign cva6_amo_resp.result = amo_is_word ? {{32{amo_resp_word[31]}}, amo_resp_word} + : hpdcache_rsp_i.rdata[0]; // }}} always_ff @(posedge clk_i or negedge rst_ni) begin : amo_pending_ff if (!rst_ni) begin - amo_pending_q <= 1'b0; + amo_pending_q <= 1'b0; + cva6_amo_resp_o <= '0; end else begin amo_pending_q <= - ( cva6_amo_req_i.req & hpdcache_req_ready_i & ~amo_pending_q) | - (~cva6_amo_resp_o.ack & amo_pending_q); + (~amo_pending_q & cva6_amo_req_i.req & hpdcache_req_ready_i) | + ( amo_pending_q & ~cva6_amo_resp_o.ack); + + if (cva6_amo_resp_o.ack) begin + cva6_amo_resp_o <= '0; + end else if (cva6_amo_resp.ack) begin + cva6_amo_resp_o <= cva6_amo_resp; + end end end diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index 6d13f6517cc..c404f9dd8d3 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -34,9 +34,7 @@ module cva6_hpdcache_subsystem parameter type axi_b_chan_t = logic, parameter type axi_r_chan_t = logic, parameter type noc_req_t = logic, - parameter type noc_resp_t = logic, - parameter type cmo_req_t = logic, - parameter type cmo_rsp_t = logic + parameter type noc_resp_t = logic ) // }}} @@ -63,7 +61,7 @@ module cva6_hpdcache_subsystem input logic icache_en_i, // Flush the instruction cache - CONTROLLER input logic icache_flush_i, - // instructino cache miss - PERF_COUNTERS + // instruction cache miss - PERF_COUNTERS output logic icache_miss_o, // Input address translation request - EX_STAGE input icache_areq_t icache_areq_i, @@ -79,22 +77,32 @@ module cva6_hpdcache_subsystem // {{{ // Cache management // Data cache enable - CSR_REGFILE - input logic dcache_enable_i, + input logic dcache_enable_i, // Data cache flush - CONTROLLER - input logic dcache_flush_i, + input logic dcache_flush_i, // Flush acknowledge - CONTROLLER output logic dcache_flush_ack_o, // Load or store miss - PERF_COUNTERS output logic dcache_miss_o, + // Data cache scrubber enable - CSR_REGFILE + input logic dcache_scrub_enable_i, + // Data cache scrubber period - CSR_REGFILE + input logic [5:0] dcache_scrub_period_i, + // Data cache scrubber cycle - CSR_REGFILE + output logic dcache_scrub_cycle_o, + // Data cache data error corrected - CSR_REGFILE + output logic dcache_dat_cor_err_o, + // Data cache data error detected but not corrected - CSR_REGFILE + output logic dcache_dat_unc_err_o, + // Data cache tag error corrected - CSR_REGFILE + output logic dcache_dir_cor_err_o, + // Data cache tag error detected but not corrected - CSR_REGFILE + output logic dcache_dir_unc_err_o, // AMO request - EX_STAGE input ariane_pkg::amo_req_t dcache_amo_req_i, // AMO response - EX_STAGE output ariane_pkg::amo_resp_t dcache_amo_resp_o, - // CMO interface request - TO_BE_COMPLETED - input cmo_req_t dcache_cmo_req_i, - // CMO interface response - TO_BE_COMPLETED - output cmo_rsp_t dcache_cmo_resp_o, // Data cache input request ports - EX_STAGE input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // Data cache output request ports - EX_STAGE @@ -185,9 +193,8 @@ module cva6_hpdcache_subsystem // . // . // . - // NumPorts: CMO - // NumPorts + 1: Hardware Memory Prefetcher (hwpf) - localparam int HPDCACHE_NREQUESTERS = NumPorts + 2; + // NumPorts: Hardware Memory Prefetcher (hwpf) + localparam int HPDCACHE_NREQUESTERS = NumPorts + 1; function automatic hpdcache_pkg::hpdcache_user_cfg_t hpdcacheSetConfig(); hpdcache_pkg::hpdcache_user_cfg_t userCfg; @@ -196,7 +203,7 @@ module cva6_hpdcache_subsystem userCfg.wordWidth = CVA6Cfg.XLEN; userCfg.sets = CVA6Cfg.DCACHE_NUM_WORDS; userCfg.ways = CVA6Cfg.DCACHE_SET_ASSOC; - userCfg.clWords = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.XLEN; + userCfg.clWords = CVA6Cfg.DCACHE_LINE_WIDTH / userCfg.wordWidth; userCfg.reqWords = 1; userCfg.reqTransIdWidth = CVA6Cfg.DcacheIdWidth; userCfg.reqSrcIdWidth = 3; // Up to 8 requesters @@ -204,24 +211,28 @@ module cva6_hpdcache_subsystem userCfg.dataWaysPerRamWord = __minu(CVA6Cfg.DCACHE_SET_ASSOC, 128 / CVA6Cfg.XLEN); userCfg.dataSetsPerRam = CVA6Cfg.DCACHE_NUM_WORDS; userCfg.dataRamByteEnable = 1'b1; - userCfg.accessWords = __maxu(CVA6Cfg.AxiDataWidth / CVA6Cfg.XLEN, 1 /*reqWords*/); + userCfg.accessWords = __maxu(CVA6Cfg.AxiDataWidth / userCfg.wordWidth, userCfg.reqWords); userCfg.mshrSets = CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2; userCfg.mshrWays = CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2; userCfg.mshrWaysPerRamWord = CVA6Cfg.NrLoadBufEntries < 16 ? CVA6Cfg.NrLoadBufEntries : 2; userCfg.mshrSetsPerRam = CVA6Cfg.NrLoadBufEntries < 16 ? 1 : CVA6Cfg.NrLoadBufEntries / 2; userCfg.mshrRamByteEnable = 1'b1; userCfg.mshrUseRegbank = (CVA6Cfg.NrLoadBufEntries < 16); + userCfg.cbufEntries = CVA6Cfg.WtDcacheWbufDepth; userCfg.refillCoreRspFeedthrough = 1'b1; - userCfg.refillFifoDepth = 2; + if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_BIG_ENDIAN || CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_LITTLE_ENDIAN) begin + // OpenPiton needs a larger refill FIFO to store as many invalidations as in-flight requests (plus some extra to be safe) + userCfg.refillFifoDepth = (userCfg.mshrSets * userCfg.mshrWays) + 10; + end else begin + userCfg.refillFifoDepth = 2 * (CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth); + end userCfg.wbufDirEntries = CVA6Cfg.WtDcacheWbufDepth; userCfg.wbufDataEntries = CVA6Cfg.WtDcacheWbufDepth; userCfg.wbufWords = 1; userCfg.wbufTimecntWidth = 3; userCfg.rtabEntries = 4; - /*FIXME we should add additional CVA6 config parameters (flushEntries)*/ - userCfg.flushEntries = CVA6Cfg.WtDcacheWbufDepth; - /*FIXME we should add additional CVA6 config parameters (flushFifoDepth)*/ - userCfg.flushFifoDepth = CVA6Cfg.WtDcacheWbufDepth; + userCfg.flushEntries = CVA6Cfg.WtDcacheWbufDepth; /*FIXME add additional CVA6 parameter*/ + userCfg.flushFifoDepth = CVA6Cfg.WtDcacheWbufDepth; /*FIXME add additional CVA6 parameter*/ userCfg.memAddrWidth = CVA6Cfg.AxiAddrWidth; userCfg.memIdWidth = CVA6Cfg.MEM_TID_WIDTH; userCfg.memDataWidth = CVA6Cfg.AxiDataWidth; @@ -231,6 +242,9 @@ module cva6_hpdcache_subsystem userCfg.wbEn = (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WB) || (CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT_WB); + userCfg.lowLatency = 1'b1; + userCfg.eccEn = CVA6Cfg.DcacheEccEnable; + userCfg.eccScrubberEn = CVA6Cfg.DcacheEccScrubberEnable; return userCfg; endfunction @@ -256,6 +270,7 @@ module cva6_hpdcache_subsystem hpdcache_req_tid_t); typedef logic [HPDcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t; + typedef logic [HPDcacheCfg.nlineWidth-1:0] hpdcache_nline_t; logic dcache_read_ready; logic dcache_read_valid; @@ -277,6 +292,9 @@ module cva6_hpdcache_subsystem logic dcache_write_resp_valid; hpdcache_mem_resp_w_t dcache_write_resp; + logic dcache_resp_read_inval; + hpdcache_nline_t dcache_resp_read_inval_nline; + cva6_hpdcache_wrapper #( .CVA6Cfg(CVA6Cfg), .HPDcacheCfg(HPDcacheCfg), @@ -284,8 +302,6 @@ module cva6_hpdcache_subsystem .dcache_req_o_t(dcache_req_o_t), .NumPorts(NumPorts), .NrHwPrefetchers(NrHwPrefetchers), - .cmo_req_t(cmo_req_t), - .cmo_rsp_t(cmo_rsp_t), .hpdcache_mem_addr_t(hpdcache_mem_addr_t), .hpdcache_mem_id_t(hpdcache_mem_id_t), .hpdcache_mem_data_t(hpdcache_mem_data_t), @@ -314,10 +330,15 @@ module cva6_hpdcache_subsystem .dcache_miss_o(dcache_miss_o), .dcache_amo_req_i(dcache_amo_req_i), .dcache_amo_resp_o(dcache_amo_resp_o), - .dcache_cmo_req_i(dcache_cmo_req_i), - .dcache_cmo_resp_o(dcache_cmo_resp_o), .dcache_req_ports_i(dcache_req_ports_i), .dcache_req_ports_o(dcache_req_ports_o), + .dcache_scrub_enable_i, + .dcache_scrub_period_i, + .dcache_scrub_cycle_o, + .dcache_dat_cor_err_o, + .dcache_dat_unc_err_o, + .dcache_dir_cor_err_o, + .dcache_dir_unc_err_o, .wbuffer_empty_o(wbuffer_empty_o), .wbuffer_not_ni_o(wbuffer_not_ni_o), .hwpf_base_set_i(hwpf_base_set_i), @@ -339,6 +360,9 @@ module cva6_hpdcache_subsystem .dcache_mem_resp_read_valid_i(dcache_read_resp_valid), .dcache_mem_resp_read_i(dcache_read_resp), + .dcache_mem_resp_read_inval_i(dcache_resp_read_inval), + .dcache_mem_resp_read_inval_nline_i(dcache_resp_read_inval_nline), + .dcache_mem_req_write_ready_i(dcache_write_ready), .dcache_mem_req_write_valid_o(dcache_write_valid), .dcache_mem_req_write_o(dcache_write), @@ -352,78 +376,164 @@ module cva6_hpdcache_subsystem .dcache_mem_resp_write_i(dcache_write_resp) ); - // AXI arbiter instantiation - // {{{ - cva6_hpdcache_subsystem_axi_arbiter #( - .CVA6Cfg (CVA6Cfg), - .hpdcache_mem_id_t (hpdcache_mem_id_t), - .hpdcache_mem_req_t (hpdcache_mem_req_t), - .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), - .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), - .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t), - .icache_req_t (icache_req_t), - .icache_rtrn_t (icache_rtrn_t), - - .AxiAddrWidth (CVA6Cfg.AxiAddrWidth), - .AxiDataWidth (CVA6Cfg.AxiDataWidth), - .AxiIdWidth (CVA6Cfg.AxiIdWidth), - .AxiUserWidth (CVA6Cfg.AxiUserWidth), - .axi_ar_chan_t(axi_ar_chan_t), - .axi_aw_chan_t(axi_aw_chan_t), - .axi_w_chan_t (axi_w_chan_t), - .axi_b_chan_t (axi_b_chan_t), - .axi_r_chan_t (axi_r_chan_t), - .axi_req_t (noc_req_t), - .axi_rsp_t (noc_resp_t) - ) i_axi_arbiter ( - .clk_i, - .rst_ni, - - .icache_miss_valid_i(icache_miss_valid), - .icache_miss_ready_o(icache_miss_ready), - .icache_miss_i (icache_miss), - .icache_miss_id_i (hpdcache_mem_id_t'(ICACHE_RDTXID)), - - .icache_miss_resp_valid_o(icache_miss_resp_valid), - .icache_miss_resp_o (icache_miss_resp), - - .dcache_read_ready_o(dcache_read_ready), - .dcache_read_valid_i(dcache_read_valid), - .dcache_read_i (dcache_read), - - .dcache_read_resp_ready_i(dcache_read_resp_ready), - .dcache_read_resp_valid_o(dcache_read_resp_valid), - .dcache_read_resp_o (dcache_read_resp), - - .dcache_write_ready_o(dcache_write_ready), - .dcache_write_valid_i(dcache_write_valid), - .dcache_write_i (dcache_write), - - .dcache_write_data_ready_o(dcache_write_data_ready), - .dcache_write_data_valid_i(dcache_write_data_valid), - .dcache_write_data_i (dcache_write_data), - - .dcache_write_resp_ready_i(dcache_write_resp_ready), - .dcache_write_resp_valid_o(dcache_write_resp_valid), - .dcache_write_resp_o (dcache_write_resp), - - .axi_req_o (noc_req_o), - .axi_resp_i(noc_resp_i) - ); - // }}} + if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_BIG_ENDIAN || CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_LITTLE_ENDIAN) begin + /////////////////////////////////////////////////////// + // memory plumbing, either use 64bit AXI port or native + // L15 cache interface (derived from OpenSPARC CCX). + /////////////////////////////////////////////////////// + + localparam NUM_PORTS_ADAPTER = 4; + localparam NUM_PORTS_ADAPTER_WIDTH = $clog2(NUM_PORTS_ADAPTER); + // Adapter HPDC-L1.5 Request Ports type + // 0: Maximum priority + // NUM_PORTS_ADAPTER - 1 : Less priority + localparam [NUM_PORTS_ADAPTER_WIDTH-1:0] ICACHE_PORT = 0; + localparam [NUM_PORTS_ADAPTER_WIDTH-1:0] DCACHE_READ_PORT = 1; + localparam [NUM_PORTS_ADAPTER_WIDTH-1:0] DCACHE_WRITE_PORT = 2; + localparam [NUM_PORTS_ADAPTER_WIDTH-1:0] DCACHE_AMO_PORT = 3; + + typedef logic [NUM_PORTS_ADAPTER_WIDTH-1:0] req_portid_t; + //L15 adapter instantiation + //{{{ + cva6_hpdcache_subsystem_l15_adapter #( + .CVA6Cfg(CVA6Cfg), + + .NumPorts (NUM_PORTS_ADAPTER), + .IcachePort (ICACHE_PORT), + .DcacheReadPort (DCACHE_READ_PORT), + .DcacheWritePort(DCACHE_WRITE_PORT), + .DcacheAmoPort (DCACHE_AMO_PORT), + + .HPDcacheMemDataWidth(CVA6Cfg.DCACHE_LINE_WIDTH), + .L15BusWidth (l15_pkg::L15_DATA_BUS_WIDTH), + + .icache_req_t (icache_req_t), + .icache_rtrn_t (icache_rtrn_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), + + .l15_req_t (noc_req_t), + .l15_rtrn_t(noc_resp_t), + + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), + .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t), + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_addr_t (hpdcache_mem_addr_t), + .hpdcache_nline_t (hpdcache_nline_t), + .req_portid_t (req_portid_t) + ) i_l15_adapter ( + .clk_i, + .rst_ni, + + .icache_miss_valid_i(icache_miss_valid), + .icache_miss_ready_o(icache_miss_ready), + .icache_miss_i (icache_miss), + + .icache_miss_resp_valid_o(icache_miss_resp_valid), + .icache_miss_resp_o (icache_miss_resp), + + .dcache_read_ready_o(dcache_read_ready), + .dcache_read_valid_i(dcache_read_valid), + .dcache_read_i (dcache_read), + + .dcache_read_resp_ready_i(dcache_read_resp_ready), + .dcache_read_resp_valid_o(dcache_read_resp_valid), + .dcache_read_resp_o (dcache_read_resp), + + .dcache_inval_valid_o(dcache_resp_read_inval), + .dcache_inval_o (dcache_resp_read_inval_nline), + + .dcache_write_ready_o(dcache_write_ready), + .dcache_write_valid_i(dcache_write_valid), + .dcache_write_i (dcache_write), + + .dcache_write_data_ready_o(dcache_write_data_ready), + .dcache_write_data_valid_i(dcache_write_data_valid), + .dcache_write_data_i (dcache_write_data), + + .dcache_write_resp_ready_i(dcache_write_resp_ready), + .dcache_write_resp_valid_o(dcache_write_resp_valid), + .dcache_write_resp_o (dcache_write_resp), + + .l15_req_o (noc_req_o), + .l15_rtrn_i(noc_resp_i) + ); + //}}} + end else begin + + // AXI arbiter instantiation + // {{{ + cva6_hpdcache_subsystem_axi_arbiter #( + .CVA6Cfg (CVA6Cfg), + .hpdcache_mem_id_t (hpdcache_mem_id_t), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), + .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), + .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t), + .icache_req_t (icache_req_t), + .icache_rtrn_t (icache_rtrn_t), + + .AxiAddrWidth (CVA6Cfg.AxiAddrWidth), + .AxiDataWidth (CVA6Cfg.AxiDataWidth), + .AxiIdWidth (CVA6Cfg.AxiIdWidth), + .AxiUserWidth (CVA6Cfg.AxiUserWidth), + .axi_ar_chan_t(axi_ar_chan_t), + .axi_aw_chan_t(axi_aw_chan_t), + .axi_w_chan_t (axi_w_chan_t), + .axi_b_chan_t (axi_b_chan_t), + .axi_r_chan_t (axi_r_chan_t), + .axi_req_t (noc_req_t), + .axi_rsp_t (noc_resp_t) + ) i_axi_arbiter ( + .clk_i, + .rst_ni, + + .icache_miss_valid_i(icache_miss_valid), + .icache_miss_ready_o(icache_miss_ready), + .icache_miss_i (icache_miss), + .icache_miss_id_i (hpdcache_mem_id_t'(ICACHE_RDTXID)), + + .icache_miss_resp_valid_o(icache_miss_resp_valid), + .icache_miss_resp_o (icache_miss_resp), + + .dcache_read_ready_o(dcache_read_ready), + .dcache_read_valid_i(dcache_read_valid), + .dcache_read_i (dcache_read), + + .dcache_read_resp_ready_i(dcache_read_resp_ready), + .dcache_read_resp_valid_o(dcache_read_resp_valid), + .dcache_read_resp_o (dcache_read_resp), + + .dcache_write_ready_o(dcache_write_ready), + .dcache_write_valid_i(dcache_write_valid), + .dcache_write_i (dcache_write), + + .dcache_write_data_ready_o(dcache_write_data_ready), + .dcache_write_data_valid_i(dcache_write_data_valid), + .dcache_write_data_i (dcache_write_data), + + .dcache_write_resp_ready_i(dcache_write_resp_ready), + .dcache_write_resp_valid_o(dcache_write_resp_valid), + .dcache_write_resp_o (dcache_write_resp), + + .axi_req_o (noc_req_o), + .axi_resp_i(noc_resp_i) + ); + // }}} + + // AXI NoC doesn't support invalidations + assign dcache_resp_read_inval = 0; + assign dcache_resp_read_inval_nline = '0; + end // Assertions // {{{ // pragma translate_off initial begin : initial_assertions - assert (HPDcacheCfg.u.reqSrcIdWidth >= $clog2(HPDcacheCfg.u.nRequesters)) - else $fatal(1, "HPDCACHE_REQ_SRC_ID_WIDTH is not wide enough"); assert (CVA6Cfg.MEM_TID_WIDTH <= CVA6Cfg.AxiIdWidth) else $fatal(1, "MEM_TID_WIDTH shall be less or equal to the AxiIdWidth"); - assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(HPDcacheCfg.u.mshrSets * HPDcacheCfg.u.mshrWays) + 1)) - else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ and I$ miss requests "); - assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(HPDcacheCfg.u.wbufDirEntries) + 1)) - else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ write requests "); end a_invalid_instruction_fetch : diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv index 901175f79c2..06a8a7c5668 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv @@ -99,8 +99,9 @@ module cva6_hpdcache_subsystem_axi_arbiter // Adapt the I$ interface to the HPDcache memory interface // {{{ - localparam int ICACHE_CL_WORDS = CVA6Cfg.ICACHE_LINE_WIDTH / 64; - localparam int ICACHE_CL_WORD_INDEX = $clog2(ICACHE_CL_WORDS); + localparam int ICACHE_UC_WORD_INDEX = CVA6Cfg.AxiDataWidth > 64 ? $clog2( + CVA6Cfg.AxiDataWidth / 64 + ) : 1; localparam int ICACHE_CL_SIZE = $clog2(CVA6Cfg.ICACHE_LINE_WIDTH / 8); localparam int ICACHE_WORD_SIZE = 3; localparam int ICACHE_MEM_REQ_CL_LEN = @@ -120,7 +121,7 @@ module cva6_hpdcache_subsystem_axi_arbiter logic icache_miss_pending_q; - // This FIFO has two functionnalities: + // This FIFO has two functionalities: // - Stabilize the ready-valid protocol. The ICACHE can abort a valid // transaction without receiving the corresponding ready signal. This // behavior is not supported by AXI. @@ -211,29 +212,31 @@ module cva6_hpdcache_subsystem_axi_arbiter assign icache_miss_resp_wok = icache_miss_resp_data_wok & ( icache_miss_resp_meta_wok | ~icache_miss_resp_wdata.mem_resp_r_last); - assign icache_miss_rdata = icache_miss_resp_data_rdata; - end else begin assign icache_miss_resp_data_rok = icache_miss_resp_w; assign icache_miss_resp_meta_rok = icache_miss_resp_w; assign icache_miss_resp_wok = 1'b1; assign icache_miss_resp_meta_id = icache_miss_resp_wdata.mem_resp_r_id; assign icache_miss_resp_data_rdata = icache_miss_resp_wdata.mem_resp_r_data; + end + endgenerate - // In the case of uncacheable accesses, the Icache expects the data to be right-aligned - always_comb begin : icache_miss_resp_data_comb - if (!icache_miss_req_rdata.mem_req_cacheable) begin - automatic logic [ICACHE_CL_WORD_INDEX - 1:0] icache_miss_word_index; - automatic logic [63:0] icache_miss_word; - icache_miss_word_index = icache_miss_req_rdata.mem_req_addr[3+:ICACHE_CL_WORD_INDEX]; - icache_miss_word = icache_miss_resp_data_rdata[icache_miss_word_index*64+:64]; - icache_miss_rdata = {{CVA6Cfg.ICACHE_LINE_WIDTH - 64{1'b0}}, icache_miss_word}; - end else begin - icache_miss_rdata = icache_miss_resp_data_rdata; - end + // In the case of uncacheable accesses, the Icache expects the data to be right-aligned + always_comb begin : icache_miss_resp_data_comb + if (!icache_miss_req_rdata.mem_req_cacheable) begin + automatic logic [ICACHE_UC_WORD_INDEX - 1:0] icache_miss_word_index; + automatic logic [63:0] icache_miss_word; + if (CVA6Cfg.AxiDataWidth > 64) begin + icache_miss_word_index = icache_miss_req_rdata.mem_req_addr[3+:ICACHE_UC_WORD_INDEX]; + end else begin + icache_miss_word_index = 0; end + icache_miss_word = icache_miss_resp_data_rdata[icache_miss_word_index*64+:64]; + icache_miss_rdata = {{CVA6Cfg.ICACHE_LINE_WIDTH - 64{1'b0}}, icache_miss_word}; + end else begin + icache_miss_rdata = icache_miss_resp_data_rdata; end - endgenerate + end assign icache_miss_resp_valid_o = icache_miss_resp_meta_rok; assign icache_miss_resp_o.rtype = wt_cache_pkg::ICACHE_IFILL_ACK; @@ -278,7 +281,9 @@ module cva6_hpdcache_subsystem_axi_arbiter .mem_req_read_ready_i(mem_req_read_ready_arb), .mem_req_read_valid_o(mem_req_read_valid_arb), - .mem_req_read_o (mem_req_read_arb) + .mem_req_read_o (mem_req_read_arb), + + .gnt_index_o( /*open*/) ); // }}} diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv b/core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv new file mode 100644 index 00000000000..91b31216bc1 --- /dev/null +++ b/core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv @@ -0,0 +1,448 @@ +/* + * Copyright 2023 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ +/* + * Authors : Noelia Oliete, Cesar Fuguet + * Creation Date: June, 2023 + * Description : Adapter module to connect the HPDC and L1I$ to the native interface of the OpenPiton L1.5 cache. + * L1 Dcache (CV-HPDcache). + * History : + */ +module cva6_hpdcache_subsystem_l15_adapter + import ariane_pkg::*; + import wt_cache_pkg::*; + import hpdcache_pkg::*; +// Parameters +// {{{ +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, // contains cacheable regions + + parameter int NumPorts = 4, + parameter [$clog2(NumPorts)-1:0] IcachePort = 0, + parameter [$clog2(NumPorts)-1:0] DcacheReadPort = 1, + parameter [$clog2(NumPorts)-1:0] DcacheWritePort = 2, + parameter [$clog2(NumPorts)-1:0] DcacheAmoPort = 3, + + // Cache parameters + parameter int HPDcacheMemDataWidth = 128, //L1D cacheline + parameter int L15BusWidth = 128, + + // L1 cache types + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + + //L1.5 cache types + parameter type l15_req_t = logic, + parameter type l15_rtrn_t = logic, + + parameter type hpdcache_mem_req_t = logic, + parameter type hpdcache_mem_req_w_t = logic, + parameter type hpdcache_mem_resp_r_t = logic, + parameter type hpdcache_mem_resp_w_t = logic, + parameter type hpdcache_mem_id_t = logic, + parameter type hpdcache_mem_addr_t = logic, + parameter type req_portid_t = logic, + parameter type hpdcache_nline_t = logic +) +// }}} + +// Ports +// {{{ +( + input logic clk_i, + input logic rst_ni, + + // Interfaces from/to I$ + // {{{ + input logic icache_miss_valid_i, + output logic icache_miss_ready_o, + input icache_req_t icache_miss_i, + + output logic icache_miss_resp_valid_o, + output icache_rtrn_t icache_miss_resp_o, + // }}} + + // Interfaces from/to D$ + // {{{ + output logic dcache_read_ready_o, + input logic dcache_read_valid_i, + input hpdcache_mem_req_t dcache_read_i, + + input logic dcache_read_resp_ready_i, + output logic dcache_read_resp_valid_o, + output hpdcache_mem_resp_r_t dcache_read_resp_o, + + output logic dcache_inval_valid_o, + output hpdcache_nline_t dcache_inval_o, + + output logic dcache_write_ready_o, + input logic dcache_write_valid_i, + input hpdcache_mem_req_t dcache_write_i, + + output logic dcache_write_data_ready_o, + input logic dcache_write_data_valid_i, + input hpdcache_mem_req_w_t dcache_write_data_i, + + input logic dcache_write_resp_ready_i, + output logic dcache_write_resp_valid_o, + output hpdcache_mem_resp_w_t dcache_write_resp_o, + // }}} + + // Ports to/from L1.5 + // {{{ + output l15_req_t l15_req_o, + input l15_rtrn_t l15_rtrn_i + // }}} +); + // }}} + + // Internal types of the adapter + // {{{ + typedef logic [CVA6Cfg.ICACHE_LINE_WIDTH-1:0] icache_resp_data_t; + typedef logic [L15BusWidth-1:0] l15_resp_data_t; + + //Unified structure for r and w responses + typedef struct packed { + + hpdcache_mem_error_e mem_resp_error; //mem_resp_r_error/mem_resp_w_error + hpdcache_mem_id_t mem_resp_id; //mem_resp_r_id/mem_resp_w_id + l15_resp_data_t mem_resp_r_data; + logic mem_resp_r_last; + logic mem_resp_w_is_atomic; + logic mem_inval_icache_valid; + logic mem_inval_dcache_valid; + logic [CVA6Cfg.PLEN-1:0] mem_inval; + } hpdcache_mem_resp_t; + // }}} + + // Adapt the I$ interface to the HPDcache memory interface + // {{{ + localparam int ICACHE_CL_WORDS = CVA6Cfg.ICACHE_LINE_WIDTH / 64; + localparam int ICACHE_CL_WORD_INDEX = $clog2(ICACHE_CL_WORDS); + localparam int ICACHE_CL_SIZE = $clog2(CVA6Cfg.ICACHE_LINE_WIDTH / 8); + localparam int ICACHE_WORD_SIZE = $clog2(CVA6Cfg.XLEN / 8); + localparam int ICACHE_MEM_REQ_CL_LEN = (CVA6Cfg.ICACHE_LINE_WIDTH + HPDcacheMemDataWidth - 1)/HPDcacheMemDataWidth; + localparam int ICACHE_MEM_REQ_CL_SIZE = (HPDcacheMemDataWidth <= CVA6Cfg.ICACHE_LINE_WIDTH) ? $clog2( + HPDcacheMemDataWidth / 8 + ) : ICACHE_CL_SIZE; + + // I$ request + // {{{ + hpdcache_mem_req_t icache_miss_req_wdata; + logic icache_miss_req_w, icache_miss_req_wok; + + hpdcache_mem_req_t icache_miss_req_rdata; + logic icache_miss_req_r, icache_miss_req_rok; + + // This FIFO has two functionnalities: + // - Stabilize the ready-valid protocol. The ICACHE can abort a valid + // transaction without receiving the corresponding ready signal. This + // behavior is not supported by AXI. + // - Cut a possible long timing path. + hpdcache_fifo_reg #( + .FIFO_DEPTH (1), + .fifo_data_t(hpdcache_mem_req_t) + ) i_icache_miss_req_fifo ( + .clk_i, + .rst_ni, + + .w_i (icache_miss_req_w), + .wok_o (icache_miss_req_wok), + .wdata_i(icache_miss_req_wdata), + + .r_i (icache_miss_req_r), + .rok_o (icache_miss_req_rok), + .rdata_o(icache_miss_req_rdata) + ); + + assign icache_miss_req_w = icache_miss_valid_i, icache_miss_ready_o = icache_miss_req_wok; + + assign icache_miss_req_wdata.mem_req_addr = icache_miss_i.paddr, + icache_miss_req_wdata.mem_req_len = '0, + icache_miss_req_wdata.mem_req_size = icache_miss_i.nc ? ICACHE_WORD_SIZE : ICACHE_MEM_REQ_CL_SIZE, + icache_miss_req_wdata.mem_req_id = icache_miss_i.tid, + icache_miss_req_wdata.mem_req_command = hpdcache_pkg::HPDCACHE_MEM_READ, + icache_miss_req_wdata.mem_req_atomic = hpdcache_pkg::hpdcache_mem_atomic_e'(0), + icache_miss_req_wdata.mem_req_cacheable = ~icache_miss_i.nc; + // }}} + + + // I$ response + // {{{ + logic icache_miss_resp_w, icache_miss_resp_wok; + hpdcache_mem_resp_t icache_miss_resp_wdata; + + logic icache_miss_resp_data_w, icache_miss_resp_data_wok; + logic icache_miss_resp_data_r; + icache_resp_data_t icache_miss_resp_data_rdata; + + logic icache_miss_resp_meta_w, icache_miss_resp_meta_wok; + logic icache_miss_resp_meta_r, icache_miss_resp_meta_rok; + hpdcache_mem_id_t icache_miss_resp_meta_id; + logic [CVA6Cfg.PLEN-1:0] icache_miss_resp_inval_address; + + //Translate the request from HPDC format to ariane's format + assign icache_miss_resp_valid_o = icache_miss_resp_meta_rok, + icache_miss_resp_o.rtype = (icache_miss_resp_wdata.mem_inval_icache_valid) ? wt_cache_pkg::ICACHE_INV_REQ : wt_cache_pkg::ICACHE_IFILL_ACK, + icache_miss_resp_o.data = icache_miss_resp_data_rdata, + icache_miss_resp_o.user = '0, + icache_miss_resp_o.inv.idx = { + icache_miss_resp_inval_address[CVA6Cfg.ICACHE_INDEX_WIDTH-1:4], 4'b0000 + }, + icache_miss_resp_o.inv.all = icache_miss_resp_wdata.mem_inval_icache_valid, + icache_miss_resp_o.inv.way = '0, + icache_miss_resp_o.inv.vld = '0, + icache_miss_resp_o.tid = icache_miss_resp_meta_id; + + assign icache_miss_resp_meta_rok = icache_miss_resp_w, + icache_miss_resp_wok = 1'b1, + icache_miss_resp_meta_id = icache_miss_resp_wdata.mem_resp_id, + icache_miss_resp_data_rdata = icache_miss_resp_wdata.mem_resp_r_data[CVA6Cfg.ICACHE_LINE_WIDTH-1:0], + icache_miss_resp_inval_address = icache_miss_resp_wdata.mem_inval; + // }}} + // }}} + + // L1.5 Request arbiter + // {{{ + + // Requests + logic mem_req_ready [NumPorts-2:0]; + logic mem_req_valid [NumPorts-2:0]; + hpdcache_mem_req_t mem_req [NumPorts-2:0]; + + + logic mem_req_ready_arb; + logic mem_req_valid_arb; + hpdcache_mem_req_t mem_req_arb; + + // Data + logic mem_req_data_ready[NumPorts-2:0]; + logic mem_req_data_valid[NumPorts-2:0]; + hpdcache_mem_req_w_t mem_req_data [NumPorts-2:0]; + hpdcache_mem_req_w_t mem_req_data_arb; + + // Port of the Request, NumPorts-1 available request ports + req_portid_t mem_req_pid [NumPorts-2:0]; + req_portid_t mem_req_pid_arb; + + // Request type selected + logic mem_req_index_arb [NumPorts-2:0]; + // LR/SC back-off + logic sc_backoff_over; + + + //Request types + //IFILL + assign icache_miss_req_r = mem_req_ready[IcachePort], + mem_req_valid[IcachePort] = icache_miss_req_rok, + mem_req_pid[IcachePort] = IcachePort, + mem_req[IcachePort] = icache_miss_req_rdata, + mem_req_data_valid[IcachePort] = 1'b1, //There is no data for this request -> always valid + mem_req_data[IcachePort] = '0; + + //Read + assign dcache_read_ready_o = mem_req_ready[DcacheReadPort], + mem_req_valid[DcacheReadPort] = dcache_read_valid_i, + mem_req_pid[DcacheReadPort] = DcacheReadPort, + mem_req[DcacheReadPort] = dcache_read_i, + mem_req_data_valid[DcacheReadPort] = 1'b1, //There is no data for this request -> always valid + mem_req_data[DcacheReadPort] = '0; + + //Write + assign dcache_write_ready_o = mem_req_ready[DcacheWritePort], + mem_req_valid[DcacheWritePort] = dcache_write_valid_i, + mem_req_pid[DcacheWritePort] = DcacheWritePort, + mem_req[DcacheWritePort] = dcache_write_i; + + assign dcache_write_data_ready_o = mem_req_ready[DcacheWritePort], //Ready at the same time as the request + mem_req_data_valid[DcacheWritePort] = dcache_write_data_valid_i, + mem_req_data[DcacheWritePort] = dcache_write_data_i; + + hpdcache_l15_req_arbiter #( + .N (NumPorts - 1), + .hpdcache_mem_req_t (hpdcache_mem_req_t), + .hpdcache_mem_req_w_t(hpdcache_mem_req_w_t), + .req_portid_t (req_portid_t) + ) i_l15_req_arbiter ( + .clk_i, + .rst_ni, + //Request + .mem_req_ready_o(mem_req_ready), + .mem_req_valid_i(mem_req_valid), + .mem_req_pid_i (mem_req_pid), + .mem_req_i (mem_req), + + //Data + .mem_req_data_valid_i(mem_req_data_valid), + .mem_req_data_i (mem_req_data), + //Arbiter + .mem_req_ready_i (mem_req_ready_arb), + .mem_req_valid_o (mem_req_valid_arb), //Valid when both request and data are valid. + + //Req & Data selected + .mem_req_pid_o (mem_req_pid_arb), + .mem_req_o (mem_req_arb), + //Data output + //Arbiter ready is the same for the request and the valid==1 if + //the request and the optional date are also valid + .mem_req_data_o (mem_req_data_arb), + .mem_req_index_o(mem_req_index_arb) + + ); + // }}} + + // L1.5 Response demultiplexor + // {{{ + logic mem_resp_ready; + logic mem_resp_valid; + hpdcache_mem_resp_t mem_resp; + + logic mem_resp_ready_arb[NumPorts-1:0]; + logic mem_resp_valid_arb[NumPorts-1:0]; + hpdcache_mem_resp_t mem_resp_arb [NumPorts-1:0]; + + //Port IcachePort -> ICACHE, Port DcacheReadPort -> Read, Port DcacheWritePort -> Write, Port DcacheUncReadPort -> UC Read, Port DcacheUncWritePort -> UC Write DcacheAmoPort -> Atomic operations + req_portid_t mem_resp_pid; + + // L1.5 Invalidation request to dcache + logic inval_ready; + logic inval_valid; + hpdcache_nline_t inval; + + hpdcache_l15_resp_demux #( + .N (NumPorts), + .resp_t (hpdcache_mem_resp_t), + .resp_id_t (hpdcache_mem_id_t), + .req_portid_t(req_portid_t) + ) i_l15_resp_demux ( + .clk_i, + .rst_ni, + //From arbiter + .mem_resp_ready_o(mem_resp_ready), + .mem_resp_valid_i(mem_resp_valid), + .mem_resp_i (mem_resp), + //To HPDC + .mem_resp_ready_i(mem_resp_ready_arb), + .mem_resp_valid_o(mem_resp_valid_arb), + .mem_resp_o (mem_resp_arb), + //Port selecter + .mem_sel_i (mem_resp_pid) + ); + + // Responses + // IFILL + assign icache_miss_resp_w = mem_resp_valid_arb[IcachePort], + icache_miss_resp_wdata = mem_resp_arb[IcachePort], + mem_resp_ready_arb[IcachePort] = icache_miss_resp_wok; + // Read & AMO responses + assign dcache_read_resp_valid_o = mem_resp_valid_arb[DcacheAmoPort] || mem_resp_valid_arb[DcacheReadPort] || inval_valid, + dcache_read_resp_o.mem_resp_r_data = mem_resp_valid_arb[DcacheAmoPort] ? mem_resp_arb[DcacheAmoPort].mem_resp_r_data[HPDcacheMemDataWidth-1:0] : + mem_resp_arb[DcacheReadPort].mem_resp_r_data[HPDcacheMemDataWidth-1:0], + dcache_read_resp_o.mem_resp_r_error = mem_resp_valid_arb[DcacheAmoPort] ? mem_resp_arb[DcacheAmoPort].mem_resp_error : + mem_resp_arb[DcacheReadPort].mem_resp_error, + dcache_read_resp_o.mem_resp_r_id = mem_resp_valid_arb[DcacheAmoPort] ? mem_resp_arb[DcacheAmoPort].mem_resp_id : + mem_resp_arb[DcacheReadPort].mem_resp_id, + dcache_read_resp_o.mem_resp_r_last = mem_resp_valid_arb[DcacheAmoPort] ? mem_resp_arb[DcacheAmoPort].mem_resp_r_last : + mem_resp_arb[DcacheReadPort].mem_resp_r_last, + dcache_inval_valid_o = inval_valid, + dcache_inval_o = inval, + mem_resp_ready_arb[DcacheReadPort] = dcache_read_resp_ready_i; + + // Write + assign dcache_write_resp_valid_o = mem_resp_valid_arb[DcacheAmoPort] || mem_resp_valid_arb[DcacheWritePort], + dcache_write_resp_o.mem_resp_w_is_atomic = mem_resp_valid_arb[DcacheAmoPort] ? mem_resp_arb[DcacheAmoPort].mem_resp_w_is_atomic : + mem_resp_arb[DcacheWritePort].mem_resp_w_is_atomic, + dcache_write_resp_o.mem_resp_w_error = mem_resp_valid_arb[DcacheAmoPort] ? mem_resp_arb[DcacheAmoPort].mem_resp_error : + mem_resp_arb[DcacheWritePort].mem_resp_error, + dcache_write_resp_o.mem_resp_w_id = mem_resp_valid_arb[DcacheAmoPort] ? mem_resp_arb[DcacheAmoPort].mem_resp_id : + mem_resp_arb[DcacheWritePort].mem_resp_id, + mem_resp_ready_arb[DcacheWritePort] = dcache_write_resp_ready_i; + + // Atomic operations send the response to both Read and Write ports + assign mem_resp_ready_arb[DcacheAmoPort] = dcache_read_resp_ready_i & dcache_write_resp_ready_i; + + // L1.5 Invalidation request to dcache + assign inval_ready = dcache_read_resp_ready_i, // Refill ready declares if hpdc is ready to receive an invalidation + inval_valid = mem_resp.mem_inval_dcache_valid, + inval = mem_resp.mem_inval[$bits( + hpdcache_mem_addr_t + )-1:$clog2( + HPDcacheMemDataWidth/8 + )]; // Convert address to cacheline number + + // }}} + + // L15 Adapter + // {{{ + + l15_req_t l15_req; + l15_rtrn_t l15_rtrn; + logic dcache_inval_ready; + + hpdcache_to_l15 #( + .NumPorts(NumPorts), // Number of request types + .IcachePort(IcachePort), + .DcacheReadPort(DcacheReadPort), + .DcacheWritePort(DcacheWritePort), + .DcacheAmoPort(DcacheAmoPort), + .WriteByteMaskEnabled(1'b0), //TODO!!!!! + .SwapEndianness(CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_BIG_ENDIAN), + .HPDcacheMemDataWidth(HPDcacheMemDataWidth), + .hpdcache_mem_req_t(hpdcache_mem_req_t), + .hpdcache_mem_req_w_t(hpdcache_mem_req_w_t), + .hpdcache_mem_id_t(hpdcache_mem_id_t), + .hpdcache_mem_addr_t(hpdcache_mem_addr_t), + .hpdcache_mem_resp_t(hpdcache_mem_resp_t), + .req_portid_t(req_portid_t), + .l15_req_t(l15_req_t), + .l15_rtrn_t(l15_rtrn_t) + ) i_hpdcache_to_l15 ( + + .clk_i, + .rst_ni, + + //HPDC to Adapter + .req_ready_o (mem_req_ready_arb), // L1.5 is ready to receive + .req_valid_i (mem_req_valid_arb), // Request and optional data are valid + .req_pid_i (mem_req_pid_arb), + .req_i (mem_req_arb), + .req_data_i (mem_req_data_arb), + .req_index_i (mem_req_index_arb), // Identify the type of request + //Adapter to HPDC + .resp_ready_i (mem_resp_ready), + .resp_valid_o (mem_resp_valid), + .resp_pid_o (mem_resp_pid), + .resp_o (mem_resp), + //HPDC Inval ready + .hpdc_inval_ready_i(inval_ready), + //Back-off parameter to guarantee the LR/SC completion + .sc_backoff_over_o (sc_backoff_over), + + //Adapter to L1.5, sending request + .l15_req_o (l15_req), // L1.5 Request + //L1.5 to Adapter + .l15_rtrn_i(l15_rtrn) // L1.5 Response + ); + + assign l15_req_o = l15_req; + assign l15_rtrn = l15_rtrn_i; + // }}} +endmodule : cva6_hpdcache_subsystem_l15_adapter diff --git a/core/cache_subsystem/cva6_hpdcache_wrapper.sv b/core/cache_subsystem/cva6_hpdcache_wrapper.sv index 7727dc703d0..081f177c479 100644 --- a/core/cache_subsystem/cva6_hpdcache_wrapper.sv +++ b/core/cache_subsystem/cva6_hpdcache_wrapper.sv @@ -23,8 +23,6 @@ module cva6_hpdcache_wrapper parameter int NumPorts = 4, parameter int NrHwPrefetchers = 4, - parameter type cmo_req_t = logic, - parameter type cmo_rsp_t = logic, parameter type hpdcache_mem_addr_t = logic, parameter type hpdcache_mem_id_t = logic, parameter type hpdcache_mem_data_t = logic, @@ -43,7 +41,9 @@ module cva6_hpdcache_wrapper parameter type hpdcache_req_t = logic, parameter type hpdcache_rsp_t = logic, parameter type hpdcache_wbuf_timecnt_t = logic, - parameter type hpdcache_data_be_t = logic + parameter type hpdcache_data_be_t = logic, + + localparam type hpdcache_nline_t = logic [HPDcacheCfg.nlineWidth-1:0] ) // }}} @@ -71,15 +71,27 @@ module cva6_hpdcache_wrapper // AMO request/response - EX_STAGE input ariane_pkg::amo_req_t dcache_amo_req_i, output ariane_pkg::amo_resp_t dcache_amo_resp_o, - // CMO interface request/response - input cmo_req_t dcache_cmo_req_i, - output cmo_rsp_t dcache_cmo_resp_o, // Data cache input request/response ports - EX_STAGE input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, + // Data cache scrubber enable - CSR_REGFILE + input logic dcache_scrub_enable_i, + // Data cache scrubber period - CSR_REGFILE + input logic [ 5:0] dcache_scrub_period_i, + // Data cache scrub cycle - CSR_REGFILE + output logic dcache_scrub_cycle_o, + // Data cache data error corrected - CSR_REGFILE + output logic dcache_dat_cor_err_o, + // Data cache data error detected but not corrected - CSR_REGFILE + output logic dcache_dat_unc_err_o, + // Data cache tag error corrected - CSR_REGFILE + output logic dcache_dir_cor_err_o, + // Data cache tag error detected but not corrected - CSR_REGFILE + output logic dcache_dir_unc_err_o, + // Write buffer status - EX_STAGE - output logic wbuffer_empty_o, - output logic wbuffer_not_ni_o, + output logic wbuffer_empty_o, + output logic wbuffer_not_ni_o, // Hardware memory prefetcher configuration input logic [NrHwPrefetchers-1:0] hwpf_base_set_i, @@ -101,6 +113,9 @@ module cva6_hpdcache_wrapper input logic dcache_mem_resp_read_valid_i, input hpdcache_mem_resp_r_t dcache_mem_resp_read_i, + input logic dcache_mem_resp_read_inval_i, + input hpdcache_nline_t dcache_mem_resp_read_inval_nline_i, + input logic dcache_mem_req_write_ready_i, output logic dcache_mem_req_write_valid_o, output hpdcache_mem_req_t dcache_mem_req_write_o, @@ -114,7 +129,7 @@ module cva6_hpdcache_wrapper input hpdcache_mem_resp_w_t dcache_mem_resp_write_i ); - localparam int HPDCACHE_NREQUESTERS = NumPorts + 2; + localparam int HPDCACHE_NREQUESTERS = NumPorts + 1; typedef logic [63:0] hwpf_stride_param_t; @@ -128,13 +143,11 @@ module cva6_hpdcache_wrapper hpdcache_rsp_t dcache_rsp [HPDCACHE_NREQUESTERS]; logic dcache_read_miss, dcache_write_miss; - logic [ 2:0] snoop_valid; - logic [ 2:0] snoop_abort; - hpdcache_req_offset_t [ 2:0] snoop_addr_offset; - hpdcache_tag_t [ 2:0] snoop_addr_tag; - logic [ 2:0] snoop_phys_indexed; - - logic dcache_cmo_req_is_prefetch; + logic [ 1:0] snoop_valid; + logic [ 1:0] snoop_abort; + hpdcache_req_offset_t [ 1:0] snoop_addr_offset; + hpdcache_tag_t [ 1:0] snoop_addr_tag; + logic [ 1:0] snoop_phys_indexed; hwpf_stride_pkg::hwpf_stride_throttle_t [NrHwPrefetchers-1:0] hwpf_throttle_in; hwpf_stride_pkg::hwpf_stride_throttle_t [NrHwPrefetchers-1:0] hwpf_throttle_out; @@ -219,37 +232,6 @@ module cva6_hpdcache_wrapper .hpdcache_rsp_valid_i(dcache_rsp_valid[NumPorts-1]), .hpdcache_rsp_i (dcache_rsp[NumPorts-1]) ); - -`ifdef HPDCACHE_ENABLE_CMO - cva6_hpdcache_cmo_if_adapter #( - .cmo_req_t(cmo_req_t), - .cmo_rsp_t(cmo_rsp_t) - ) i_cva6_hpdcache_cmo_if_adapter ( - .clk_i, - .rst_ni, - - .dcache_req_sid_i(hpdcache_req_sid_t'(NumPorts)), - - .cva6_cmo_req_i (dcache_cmo_req_i), - .cva6_cmo_resp_o(dcache_cmo_resp_o), - - .dcache_req_valid_o(dcache_req_valid[NumPorts]), - .dcache_req_ready_i(dcache_req_ready[NumPorts]), - .dcache_req_o (dcache_req[NumPorts]), - .dcache_req_abort_o(dcache_req_abort[NumPorts]), - .dcache_req_tag_o (dcache_req_tag[NumPorts]), - .dcache_req_pma_o (dcache_req_pma[NumPorts]), - - .dcache_rsp_valid_i(dcache_rsp_valid[NumPorts]), - .dcache_rsp_i (dcache_rsp[NumPorts]) - ); -`else - assign dcache_req_valid[NumPorts] = 1'b0, - dcache_req[NumPorts] = '0, - dcache_req_abort[NumPorts] = 1'b0, - dcache_req_tag[NumPorts] = '0, - dcache_req_pma[NumPorts] = '0; -`endif endgenerate // Snoop load port @@ -266,26 +248,6 @@ module cva6_hpdcache_wrapper snoop_addr_tag[1] = dcache_req_tag[NumPorts-1], snoop_phys_indexed[1] = dcache_req[NumPorts-1].phys_indexed; -`ifdef HPDCACHE_ENABLE_CMO - // Snoop CMO port (in case of read prefetch accesses) - assign dcache_cmo_req_is_prefetch = hpdcache_pkg::is_cmo_prefetch( - dcache_req[NumPorts].op, dcache_req[NumPorts].size - ); - assign snoop_valid[2] = dcache_req_valid[NumPorts] - & dcache_req_ready[NumPorts] - & dcache_cmo_req_is_prefetch, - snoop_abort[2] = dcache_req_abort[NumPorts], - snoop_addr_offset[2] = dcache_req[NumPorts].addr_offset, - snoop_addr_tag[2] = dcache_req_tag[NumPorts], - snoop_phys_indexed[2] = dcache_req[NumPorts].phys_indexed; -`else - assign snoop_valid[2] = 1'b0, - snoop_abort[2] = 1'b0, - snoop_addr_offset[2] = '0, - snoop_addr_tag[2] = '0, - snoop_phys_indexed[2] = 1'b0; -`endif - generate for (genvar h = 0; h < NrHwPrefetchers; h++) begin : gen_hwpf_throttle assign hwpf_throttle_in[h] = hwpf_stride_pkg::hwpf_stride_throttle_t'(hwpf_throttle_i[h]); @@ -296,7 +258,7 @@ module cva6_hpdcache_wrapper hwpf_stride_wrapper #( .HPDcacheCfg (HPDcacheCfg), .NUM_HW_PREFETCH (NrHwPrefetchers), - .NUM_SNOOP_PORTS (3), + .NUM_SNOOP_PORTS (2), .hpdcache_tag_t (hpdcache_tag_t), .hpdcache_req_offset_t(hpdcache_req_offset_t), .hpdcache_req_data_t (hpdcache_req_data_t), @@ -326,16 +288,16 @@ module cva6_hpdcache_wrapper .snoop_addr_tag_i (snoop_addr_tag), .snoop_phys_indexed_i(snoop_phys_indexed), - .hpdcache_req_sid_i(hpdcache_req_sid_t'(NumPorts + 1)), + .hpdcache_req_sid_i(hpdcache_req_sid_t'(NumPorts)), - .hpdcache_req_valid_o(dcache_req_valid[NumPorts+1]), - .hpdcache_req_ready_i(dcache_req_ready[NumPorts+1]), - .hpdcache_req_o (dcache_req[NumPorts+1]), - .hpdcache_req_abort_o(dcache_req_abort[NumPorts+1]), - .hpdcache_req_tag_o (dcache_req_tag[NumPorts+1]), - .hpdcache_req_pma_o (dcache_req_pma[NumPorts+1]), - .hpdcache_rsp_valid_i(dcache_rsp_valid[NumPorts+1]), - .hpdcache_rsp_i (dcache_rsp[NumPorts+1]) + .hpdcache_req_valid_o(dcache_req_valid[NumPorts]), + .hpdcache_req_ready_i(dcache_req_ready[NumPorts]), + .hpdcache_req_o (dcache_req[NumPorts]), + .hpdcache_req_abort_o(dcache_req_abort[NumPorts]), + .hpdcache_req_tag_o (dcache_req_tag[NumPorts]), + .hpdcache_req_pma_o (dcache_req_pma[NumPorts]), + .hpdcache_rsp_valid_i(dcache_rsp_valid[NumPorts]), + .hpdcache_rsp_i (dcache_rsp[NumPorts]) ); hpdcache #( @@ -383,6 +345,9 @@ module cva6_hpdcache_wrapper .mem_resp_read_valid_i(dcache_mem_resp_read_valid_i), .mem_resp_read_i (dcache_mem_resp_read_i), + .mem_resp_read_inval_i (dcache_mem_resp_read_inval_i), + .mem_resp_read_inval_nline_i(dcache_mem_resp_read_inval_nline_i), + .mem_req_write_ready_i(dcache_mem_req_write_ready_i), .mem_req_write_valid_o(dcache_mem_req_write_valid_o), .mem_req_write_o (dcache_mem_req_write_o), @@ -395,17 +360,22 @@ module cva6_hpdcache_wrapper .mem_resp_write_valid_i(dcache_mem_resp_write_valid_i), .mem_resp_write_i (dcache_mem_resp_write_i), - .evt_cache_write_miss_o(dcache_write_miss), - .evt_cache_read_miss_o (dcache_read_miss), - .evt_uncached_req_o ( /* unused */), - .evt_cmo_req_o ( /* unused */), - .evt_write_req_o ( /* unused */), - .evt_read_req_o ( /* unused */), - .evt_prefetch_req_o ( /* unused */), - .evt_req_on_hold_o ( /* unused */), - .evt_rtab_rollback_o ( /* unused */), - .evt_stall_refill_o ( /* unused */), - .evt_stall_o ( /* unused */), + .evt_cache_write_miss_o (dcache_write_miss), + .evt_cache_read_miss_o (dcache_read_miss), + .evt_cache_dir_unc_err_o(dcache_dir_unc_err_o), + .evt_cache_dir_cor_err_o(dcache_dir_cor_err_o), + .evt_cache_dat_unc_err_o(dcache_dat_unc_err_o), + .evt_cache_dat_cor_err_o(dcache_dat_cor_err_o), + .evt_scrub_complete_o (dcache_scrub_cycle_o), + .evt_uncached_req_o ( /* unused */), + .evt_cmo_req_o ( /* unused */), + .evt_write_req_o ( /* unused */), + .evt_read_req_o ( /* unused */), + .evt_prefetch_req_o ( /* unused */), + .evt_req_on_hold_o ( /* unused */), + .evt_rtab_rollback_o ( /* unused */), + .evt_stall_refill_o ( /* unused */), + .evt_stall_o ( /* unused */), .wbuf_empty_o(wbuffer_empty_o), @@ -417,7 +387,10 @@ module cva6_hpdcache_wrapper .cfg_prefetch_updt_plru_i (1'b1), .cfg_error_on_cacheable_amo_i (1'b0), .cfg_rtab_single_entry_i (1'b0), - .cfg_default_wb_i (1'b0) + .cfg_default_wb_i (1'b0), + .cfg_scrub_enable_i (dcache_scrub_enable_i), + .cfg_scrub_period_i (dcache_scrub_period_i), + .cfg_scrub_restart_i (1'b0) ); assign dcache_miss_o = dcache_read_miss, wbuffer_not_ni_o = wbuffer_empty_o; diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index d97fed369a0..d84ee26d26f 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -209,7 +209,7 @@ module cva6_icache miss_o = 1'b0; // handle invalidations unconditionally - // note: invald are mutually exclusive with + // note: invals are mutually exclusive with // ifills, since both arrive over the same IF // however, we need to make sure below that we // do not trigger a cache readout at the same time... @@ -424,9 +424,9 @@ module cva6_icache logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] hit_idx; for (genvar i = 0; i < CVA6Cfg.ICACHE_SET_ASSOC; i++) begin : gen_tag_cmpsel - assign cl_hit[i] = (cl_tag_rdata[i] == cl_tag_d) & vld_rdata[i]; - assign cl_sel[i] = cl_rdata[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH]; - assign cl_user[i] = cl_ruser[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_USER_WIDTH]; + assign cl_hit[i] = (cl_tag_rdata[i] == cl_tag_d) & vld_rdata[i]; + assign cl_sel[i] = cl_rdata[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH]; + assign cl_user[i] = CVA6Cfg.FETCH_USER_EN ? cl_ruser[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_USER_WIDTH] : '0; end @@ -441,10 +441,10 @@ module cva6_icache always_comb begin if (cmp_en_q) begin dreq_o.data = cl_sel[hit_idx]; - dreq_o.user = cl_user[hit_idx]; + dreq_o.user = CVA6Cfg.FETCH_USER_EN ? cl_user[hit_idx] : '0; end else begin dreq_o.data = mem_rtrn_i.data[{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH]; - dreq_o.user = mem_rtrn_i.user[{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_USER_WIDTH]; + dreq_o.user = CVA6Cfg.FETCH_USER_EN ? mem_rtrn_i.user[{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_USER_WIDTH] : '0; end end diff --git a/core/cache_subsystem/hpdcache b/core/cache_subsystem/hpdcache index 04de8089698..e8f072e117e 160000 --- a/core/cache_subsystem/hpdcache +++ b/core/cache_subsystem/hpdcache @@ -1 +1 @@ -Subproject commit 04de80896981527c34fbbd35d7b1ef787a082d7c +Subproject commit e8f072e117ed3282950d4d1e975f462b173f0de0 diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index 7adb935c27a..a38e2e7a7a9 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -183,7 +183,7 @@ module std_cache_subsystem // W Channel cva6_fifo_v3 #( .DATA_WIDTH (2), - // we can have a maximum of 4 oustanding transactions as each port is blocking + // we can have a maximum of 4 outstanding transactions as each port is blocking .DEPTH (4), .FALL_THROUGH(1'b1), .FPGA_EN (CVA6Cfg.FpgaEn) diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 22cc5c075c2..784c193b22d 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -52,6 +52,9 @@ module wt_axi_adapter output axi_req_t axi_req_o, input axi_rsp_t axi_resp_i, + // Endianness Control Signal from CSR + input logic mbe_i, + // Invalidations input logic [63:0] inval_addr_i, input logic inval_valid_i, @@ -264,43 +267,98 @@ module wt_axi_adapter end // RISC-V atops have a load semantic AMO_SWAP: axi_wr_atop = axi_pkg::ATOP_ATOMICSWAP; - AMO_ADD: - axi_wr_atop = { - axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD - }; + AMO_ADD: begin + if (mbe_i) begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_BIG_END, axi_pkg::ATOP_ADD + }; + end else begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD + }; + end + end AMO_AND: begin // in this case we need to invert the data to get a "CLR" axi_wr_data[0] = ~{(CVA6Cfg.AxiDataWidth / CVA6Cfg.XLEN) {dcache_data.data}}; axi_wr_user = ~{(CVA6Cfg.AxiDataWidth / CVA6Cfg.XLEN) {dcache_data.user}}; - axi_wr_atop = { - axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR - }; + if (mbe_i) begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_BIG_END, axi_pkg::ATOP_CLR + }; + end else begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR + }; + end + end + AMO_OR: begin + if (mbe_i) begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_BIG_END, axi_pkg::ATOP_SET + }; + end else begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET + }; + end + end + AMO_XOR: begin + if (mbe_i) begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_BIG_END, axi_pkg::ATOP_EOR + }; + end else begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR + }; + end + end + AMO_MAX: begin + if (mbe_i) begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_BIG_END, axi_pkg::ATOP_SMAX + }; + end else begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX + }; + end + end + AMO_MAXU: begin + if (mbe_i) begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_BIG_END, axi_pkg::ATOP_UMAX + }; + end else begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX + }; + end + end + AMO_MIN: begin + if (mbe_i) begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_BIG_END, axi_pkg::ATOP_SMIN + }; + end else begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN + }; + end + end + AMO_MINU: begin + if (mbe_i) begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_BIG_END, axi_pkg::ATOP_UMIN + }; + end else begin + axi_wr_atop = { + axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN + }; + end end - AMO_OR: - axi_wr_atop = { - axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET - }; - AMO_XOR: - axi_wr_atop = { - axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR - }; - AMO_MAX: - axi_wr_atop = { - axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX - }; - AMO_MAXU: - axi_wr_atop = { - axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX - }; - AMO_MIN: - axi_wr_atop = { - axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN - }; - AMO_MINU: - axi_wr_atop = { - axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN - }; - default: ; // Do nothing + default: ; // Do nothing endcase end end diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index 0a2ac0c79c4..4f40002f482 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -59,6 +59,7 @@ module wt_cache_subsystem // AMO interface input amo_req_t dcache_amo_req_i, output amo_resp_t dcache_amo_resp_o, + input logic mbe_i, // Request ports input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU @@ -91,7 +92,7 @@ module wt_cache_subsystem logic [CVA6Cfg.XLEN-1:0] data; // word width of processor (no block stores at the moment) logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] user; // user width of processor (no block stores at the moment) logic nc; // noncacheable - logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // thread id (used as transaction id in Ariane) ariane_pkg::amo_t amo_op; // amo opcode }; @@ -100,7 +101,7 @@ module wt_cache_subsystem logic [CVA6Cfg.DCACHE_LINE_WIDTH-1:0] data; // full cache line width logic [CVA6Cfg.DCACHE_USER_LINE_WIDTH-1:0] user; // user bits dcache_inval_t inv; // invalidation vector - logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // thread id (used as transaction id in Ariane) }; logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld; @@ -164,6 +165,7 @@ module wt_cache_subsystem .wbuffer_not_ni_o(wbuffer_not_ni_o), .amo_req_i (dcache_amo_req_i), .amo_resp_o (dcache_amo_resp_o), + .mbe_i (mbe_i), .req_ports_i (dcache_req_ports_i), .req_ports_o (dcache_req_ports_o), .miss_vld_bits_o (miss_vld_bits_o), @@ -228,6 +230,7 @@ module wt_cache_subsystem .dcache_rtrn_o (adapter_dcache), .axi_req_o (noc_req_o), .axi_resp_i (noc_resp_i), + .mbe_i (mbe_i), .inval_addr_i (inval_addr_i), .inval_valid_i (inval_valid_i), .inval_ready_o (inval_ready_o) diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index 5b49d957fbe..76248861597 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -41,6 +41,7 @@ module wt_dcache // AMO interface input amo_req_t amo_req_i, output amo_resp_t amo_resp_o, + input logic mbe_i, // Request ports input dcache_req_i_t [NumPorts-1:0] req_ports_i, @@ -148,6 +149,7 @@ module wt_dcache // amo interface .amo_req_i (amo_req_i), .amo_resp_o (amo_resp_o), + .mbe_i (mbe_i), // miss handling interface .miss_req_i (miss_req), .miss_ack_o (miss_ack), diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv index 5eb202e08e6..c40491ab45d 100644 --- a/core/cache_subsystem/wt_dcache_missunit.sv +++ b/core/cache_subsystem/wt_dcache_missunit.sv @@ -38,6 +38,7 @@ module wt_dcache_missunit // AMO interface input amo_req_t amo_req_i, output amo_resp_t amo_resp_o, + input logic mbe_i, // miss handling interface (ld, ptw, wbuffer) input logic [NumPorts-1:0] miss_req_i, output logic [NumPorts-1:0] miss_ack_o, @@ -53,7 +54,7 @@ module wt_dcache_missunit output logic [NumPorts-1:0] miss_replay_o, // signals response from memory output logic [NumPorts-1:0] miss_rtrn_vld_o, - output logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_rtrn_id_o, // only used for writes, set to zero fro reads + output logic [CVA6Cfg.MEM_TID_WIDTH-1:0] miss_rtrn_id_o, // only used for writes, set to zero for reads // from writebuffer input logic [CVA6Cfg.DCACHE_MAX_TX-1:0][CVA6Cfg.PLEN-1:0] tx_paddr_i, // used to check for address collisions with read operations input logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_i, // used to check for address collisions with read operations @@ -288,9 +289,32 @@ module wt_dcache_missunit assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:3]*64+:64]; end - // always sign extend 32bit values - assign amo_resp_o.result = (amo_req_i.size==2'b10) ? {{32{amo_rtrn_mux[amo_req_i.operand_a[2]*32 + 31]}},amo_rtrn_mux[amo_req_i.operand_a[2]*32 +: 32]} : - amo_rtrn_mux ; + // BIG ENDIAN CAPABLE logic for amo return value from memory + logic [63:0] amoResult_LE; + logic [63:0] amoResult_BE; + + // Little Endian Calculation of return value from memory (when 32bit, we need to sign extend) + logic [63:0] amoResult_32bitLE; + assign amoResult_32bitLE = { + {32{amo_rtrn_mux[amo_req_i.operand_a[2]*32+31]}}, amo_rtrn_mux[amo_req_i.operand_a[2]*32+:32] + }; + + // Big Endian Calculations of return value from memory with AMO operations (Bytes need swapping and sign extension is different) + logic [63:0] amoResult_64bitBE; + logic [31:0] amoResult_32bitBE_NoSign; + logic [63:0] amoResult_32bitBE; + assign amoResult_64bitBE = {<<8{amo_rtrn_mux}}; + assign amoResult_32bitBE_NoSign = {<<8{amo_rtrn_mux[amo_req_i.operand_a[2]*32+:32]}}; + assign amoResult_32bitBE = { + {32{amo_rtrn_mux[amo_req_i.operand_a[2]*32+7]}}, amoResult_32bitBE_NoSign + }; // +7 to the base address to find the sign bit, as in BE the Most Significant Byte is always at the lowest addressed byte. + + assign amoResult_BE = (amo_req_i.size == 2'b10) ? amoResult_32bitBE : amoResult_64bitBE; + assign amoResult_LE = (amo_req_i.size == 2'b10) ? amoResult_32bitLE : amo_rtrn_mux; + + assign amo_resp_o.result = mbe_i ? amoResult_BE : amoResult_LE; + // end BIG ENDIAN CAPABLE logic for amo return value from memory + assign amo_req_d = amo_req_i.req; end diff --git a/core/cache_subsystem/wt_l15_adapter.sv b/core/cache_subsystem/wt_l15_adapter.sv index cd1ca229678..bba4886893e 100644 --- a/core/cache_subsystem/wt_l15_adapter.sv +++ b/core/cache_subsystem/wt_l15_adapter.sv @@ -48,10 +48,10 @@ // https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf // - module wt_l15_adapter import ariane_pkg::*; import wt_cache_pkg::*; + import l15_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type icache_req_t = logic, @@ -83,51 +83,6 @@ module wt_l15_adapter input l15_rtrn_t l15_rtrn_i ); - localparam type l15_req_t = struct packed { - logic l15_val; // valid signal, asserted with request - logic l15_req_ack; // ack for response - wt_cache_pkg::l15_reqtypes_t l15_rqtype; // see below for encoding - logic l15_nc; // non-cacheable bit - logic [2:0] l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) - logic [CVA6Cfg.MEM_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1 - logic l15_prefetch; // unused in openpiton - logic l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment - logic l15_blockstore; // unused in openpiton - logic l15_blockinitstore; // unused in openpiton - logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] l15_l1rplway; // way to replace - logic [39:0] l15_address; // physical address - logic [63:0] l15_data; // word to write - logic [63:0] l15_data_next_entry; // unused in Ariane (only used for CAS atomic requests) - logic [wt_cache_pkg::L15_TLB_CSM_WIDTH-1:0] l15_csm_data; // unused in Ariane - logic [3:0] l15_amo_op; // atomic operation type - }; - localparam type l15_rtrn_t = struct packed { - logic l15_ack; // ack for request struct - logic l15_header_ack; // ack for request struct - logic l15_val; // valid signal for return struct - wt_l15_adapter::l15_rtrntypes_t l15_returntype; // see below for encoding - logic l15_l2miss; // unused in Ariane - logic [1:0] l15_error; // unused in openpiton - logic l15_noncacheable; // non-cacheable bit - logic l15_atomic; // asserted in load return and store ack packets of atomic tx - logic [CVA6Cfg.MEM_TID_WIDTH-1:0] l15_threadid; // used as transaction ID - logic l15_prefetch; // unused in openpiton - logic l15_f4b; // 4byte instruction fill from I/O space (nc). - logic [63:0] l15_data_0; // used for both caches - logic [63:0] l15_data_1; // used for both caches - logic [63:0] l15_data_2; // currently only used for I$ - logic [63:0] l15_data_3; // currently only used for I$ - logic l15_inval_icache_all_way; // invalidate all ways - logic l15_inval_dcache_all_way; // unused in openpiton - logic [15:4] l15_inval_address_15_4; // invalidate selected cacheline - logic l15_cross_invalidate; // unused in openpiton - logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] l15_cross_invalidate_way; // unused in openpiton - logic l15_inval_dcache_inval; // invalidate selected cacheline and way - logic l15_inval_icache_inval; // unused in openpiton - logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] l15_inval_way; // way to invalidate - logic l15_blockinitstore; // unused in openpiton - }; - // request path icache_req_t icache_data; logic icache_data_full, icache_data_empty; @@ -166,7 +121,10 @@ module wt_l15_adapter // data mux assign l15_req_o.l15_nc = (arb_idx) ? dcache_data.nc : icache_data.nc; // icache fills are either cachelines or 4byte fills, depending on whether they go to the Piton I/O space or not. - assign l15_req_o.l15_size = (arb_idx) ? dcache_data.size : (icache_data.nc) ? 3'b010 : 3'b111; + assign l15_req_o.l15_size = (arb_idx) ? (dcache_data.size == 3'b111) ? ((CVA6Cfg.DCACHE_OFFSET_WIDTH == 3'b100) ? 3'b101 : + (CVA6Cfg.DCACHE_OFFSET_WIDTH == 3'b101) ? 3'b110 : 3'b111) : + dcache_data.size + 1 : + (icache_data.nc) ? 3'b011 : 3'b110; assign l15_req_o.l15_threadid = (arb_idx) ? dcache_data.tid : icache_data.tid; assign l15_req_o.l15_prefetch = '0; // unused in openpiton assign l15_req_o.l15_invalidate_cacheline = '0; // unused by Ariane as L1 has no ECC at the moment @@ -178,7 +136,8 @@ module wt_l15_adapter assign l15_req_o.l15_data_next_entry = '0; // unused in Ariane (only used for CAS atomic requests) assign l15_req_o.l15_csm_data = '0; // unused in Ariane (only used for coherence domain restriction features) - assign l15_req_o.l15_amo_op = dcache_data.amo_op; + assign l15_req_o.l15_amo_op = l15_pkg::l15_amo_e'(logic'(dcache_data.amo_op)); + assign l15_req_o.l15_be = '0; // Not supported by WT cache // openpiton is big endian @@ -303,8 +262,12 @@ module wt_l15_adapter always_comb begin : p_rtrn_logic icache_rtrn_o.rtype = ICACHE_IFILL_ACK; dcache_rtrn_o.rtype = DCACHE_LOAD_ACK; - icache_rtrn_vld_o = 1'b0; - dcache_rtrn_vld_o = 1'b0; + icache_rtrn_vld_o = 1'b0; + dcache_rtrn_vld_o = 1'b0; + icache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_icache_inval; + icache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_icache_all_way; + dcache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_dcache_inval; + dcache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_dcache_all_way; if (!rtrn_fifo_empty) begin unique case (rtrn_fifo_data.l15_returntype) L15_LOAD_RET: begin @@ -341,7 +304,7 @@ module wt_l15_adapter end // openpiton is big endian - if (SwapEndianess) begin : gen_swap + if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_BIG_ENDIAN) begin : gen_swap assign dcache_rtrn_o.data = { swendian64(rtrn_fifo_data.l15_data_1), swendian64(rtrn_fifo_data.l15_data_0) }; @@ -368,15 +331,11 @@ module wt_l15_adapter assign dcache_rtrn_o.tid = rtrn_fifo_data.l15_threadid; // invalidation signal mapping - assign icache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address_15_4, 4'b0000}; + assign icache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address[15:4], 4'b0000}; assign icache_rtrn_o.inv.way = rtrn_fifo_data.l15_inval_way; - assign icache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_icache_inval; - assign icache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_icache_all_way; - assign dcache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address_15_4, 4'b0000}; + assign dcache_rtrn_o.inv.idx = {rtrn_fifo_data.l15_inval_address[15:4], 4'b0000}; assign dcache_rtrn_o.inv.way = rtrn_fifo_data.l15_inval_way; - assign dcache_rtrn_o.inv.vld = rtrn_fifo_data.l15_inval_dcache_inval; - assign dcache_rtrn_o.inv.all = rtrn_fifo_data.l15_inval_dcache_all_way; fifo_v2 #( .dtype(l15_rtrn_t), diff --git a/core/commit_stage.sv b/core/commit_stage.sv index d41c6b5a309..4577de449d5 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -72,7 +72,7 @@ module commit_stage output logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_tran_id_o, // Valid AMO in commit stage - EX_STAGE output logic amo_valid_commit_o, - // no store is pending - EX_STAGE + // No store is pending - EX_STAGE input logic no_st_pending_i, // Commit the pending CSR instruction - EX_STAGE output logic commit_csr_o, @@ -87,7 +87,14 @@ module commit_stage // TO_BE_COMPLETED - CONTROLLER output logic hfence_vvma_o, // TO_BE_COMPLETED - CONTROLLER - output logic hfence_gvma_o + output logic hfence_gvma_o, + // Shared TLB is still processing a multi-cycle flush + input logic shared_tlb_flush_busy_i, + // Trigger module + input logic sdtrig_commit_icount_valid_i, + input logic [$clog2(CVA6Cfg.NrCommitPorts)-1:0] sdtrig_commit_icount_nr_instr_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_commit_action_i, + input logic sdtrig_commit_std_exception_valid_i ); // ila_0 i_ila_commit ( @@ -113,21 +120,27 @@ module commit_stage always_comb begin : dirty_fp_state dirty_fp_state_o = 1'b0; for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin - dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + dirty_fp_state_o |= commit_ack_o[i] & ((commit_instr_i[i].fu inside {FPU, FPU_VEC} & CVA6Cfg.FpPresent & ariane_pkg::fd_changes_rd_state( commit_instr_i[i].op - // Check if we issued a vector floating-point instruction to the accellerator - ))) | commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp; + )) || (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( + commit_instr_i[i].op + // Check if we issued a vector floating-point instruction to the accelerator + ))) | (commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp); end end assign commit_tran_id_o = commit_instr_i[0].trans_id; + exception_t ex_next_instr_d, ex_next_instr_q; + logic instr_0_is_amo; logic [CVA6Cfg.NrCommitPorts-1:0] commit_macro_ack; assign instr_0_is_amo = is_amo(commit_instr_i[0].op); // ------------------- // Commit Instruction // ------------------- + logic tlb_flush_can_commit; + assign tlb_flush_can_commit = no_st_pending_i && !shared_tlb_flush_busy_i; // write register file or commit instruction in LSU or CSR Buffer always_comb begin : commit // default assignments @@ -155,7 +168,8 @@ module commit_stage // we do not commit the instruction yet if we requested a halt if (commit_instr_i[0].valid && !halt_i) begin // we will not commit the instruction if we took an exception - if (commit_instr_i[0].ex.valid) begin + if (commit_instr_i[0].ex.valid + || ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_commit_std_exception_valid_i || (CVA6Cfg.SdtrigIcount && sdtrig_commit_icount_valid_i && sdtrig_commit_icount_nr_instr_i == 0))) begin // However we can drop it (with its exception) if (commit_drop_i[0]) begin commit_ack_o[0] = 1'b1; @@ -227,9 +241,9 @@ module commit_stage if (CVA6Cfg.RVS && commit_instr_i[0].op == SFENCE_VMA) begin if (!commit_drop_i[0]) begin // no store pending so we can flush the TLBs and pipeline - sfence_vma_o = no_st_pending_i; + sfence_vma_o = tlb_flush_can_commit; //Only retire the fence when stores are drained and the shared TLB // wait for the store buffer to drain until flushing the pipeline - commit_ack_o[0] = no_st_pending_i; + commit_ack_o[0] = tlb_flush_can_commit; end end // ------------------ @@ -241,9 +255,9 @@ module commit_stage if (CVA6Cfg.RVH && commit_instr_i[0].op == HFENCE_VVMA) begin if (!commit_drop_i[0]) begin // no store pending so we can flush the TLBs and pipeline - hfence_vvma_o = no_st_pending_i; + hfence_vvma_o = tlb_flush_can_commit; // wait for the store buffer to drain until flushing the pipeline - commit_ack_o[0] = no_st_pending_i; + commit_ack_o[0] = tlb_flush_can_commit; end end // ------------------ @@ -255,9 +269,9 @@ module commit_stage if (CVA6Cfg.RVH && commit_instr_i[0].op == HFENCE_GVMA) begin if (!commit_drop_i[0]) begin // no store pending so we can flush the TLBs and pipeline - hfence_gvma_o = no_st_pending_i; + hfence_gvma_o = tlb_flush_can_commit; // wait for the store buffer to drain until flushing the pipeline - commit_ack_o[0] = no_st_pending_i; + commit_ack_o[0] = tlb_flush_can_commit; end end // ------------------ @@ -316,7 +330,9 @@ module commit_stage && !(commit_instr_i[0].fu inside {CSR}) && !flush_dcache_i && !(CVA6Cfg.RVA && instr_0_is_amo) - && !single_step_i) begin + && !single_step_i + && !(CVA6Cfg.Sdtrig && sdtrig_commit_icount_valid_i && sdtrig_commit_icount_nr_instr_i < CVA6Cfg.NrCommitPorts) + && (CVA6Cfg.SdtrigMcontrol6LoadData ? !commit_instr_i[0].ex.timing : !CVA6Cfg.SdtrigMcontrol6LoadData)) begin // only if the first instruction didn't throw an exception and this instruction won't throw an exception // and the functional unit is of type ALU, LOAD, CTRL_FLOW, MULT, FPU or FPU_VEC if (!commit_instr_i[1].ex.valid && (commit_instr_i[1].fu inside {ALU, LOAD, CTRL_FLOW, MULT, FPU, FPU_VEC})) begin @@ -366,10 +382,25 @@ module commit_stage // interrupts are correctly prioritized in the CSR reg file, exceptions are prioritized here exception_o.valid = 1'b0; exception_o.cause = '0; - exception_o.tval = '0; + exception_o.tval = '0; exception_o.tval2 = '0; exception_o.tinst = '0; - exception_o.gva = 1'b0; + exception_o.gva = 1'b0; + exception_o.timing = 1'b0; + + if (CVA6Cfg.SdtrigMcontrol6LoadData) begin + if (commit_ack_o[0]) begin + if(commit_instr_i[0].ex.timing && commit_ack_o[0]) begin //save exception if timing is set, with priority to port 0 + ex_next_instr_d = commit_instr_i[0].ex; + end else if (CVA6Cfg.NrCommitPorts > 1 && commit_instr_i[1].ex.timing && commit_ack_o[1]) begin + ex_next_instr_d = commit_instr_i[1].ex; + end else begin + ex_next_instr_d = ex_next_instr_q; + end + end + end else begin + ex_next_instr_d = '0; + end // we need a valid instruction in the commit stage if (commit_instr_i[0].valid && !commit_drop_i[0]) begin @@ -381,7 +412,7 @@ module commit_stage // if no earlier exception happened the commit instruction will still contain // the instruction bits from the ID stage. If a earlier exception happened we don't care // as we will overwrite it anyway in the next IF bl - exception_o.tval = commit_instr_i[0].ex.tval; + exception_o.tval = (CVA6Cfg.TvalEn) ? commit_instr_i[0].ex.tval : '0; if (CVA6Cfg.RVH) begin exception_o.tinst = commit_instr_i[0].ex.tinst; exception_o.tval2 = commit_instr_i[0].ex.tval2; @@ -402,5 +433,41 @@ module commit_stage if (halt_i) begin exception_o.valid = 1'b0; end + + // The trigger action is taken on a valid instruction, when the commit stage is not halted + if (commit_instr_i[0].valid && !halt_i + && ((CVA6Cfg.SdtrigIcount && sdtrig_commit_icount_valid_i && sdtrig_commit_icount_nr_instr_i == 'd0) + || ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_commit_std_exception_valid_i))) begin + exception_o.valid = 1'b1; + exception_o.cause = sdtrig_commit_action_i; + // icount, itrigger and etrigger write 0 to tval + exception_o.tval = '0; + end + + if(CVA6Cfg.SdtrigMcontrol6LoadData && ex_next_instr_q.timing && !commit_instr_i[0].ex.timing) begin + //there should never be 2 timing bits set one after the other (port 1 and 2) because LSU can only make one mem access at a time + exception_o = ex_next_instr_q; + exception_o.timing = 1'b0; + exception_o.valid = 1'b1; + ex_next_instr_d = '0; + end + end + + if (CVA6Cfg.SdtrigMcontrol6LoadData) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + ex_next_instr_q.valid <= 1'b0; + ex_next_instr_q.cause <= '0; + ex_next_instr_q.tval <= '0; + ex_next_instr_q.tval2 <= '0; + ex_next_instr_q.tinst <= '0; + ex_next_instr_q.gva <= 1'b0; + ex_next_instr_q.timing <= 1'b0; + end else begin + ex_next_instr_q <= ex_next_instr_d; + end + end + end else begin + assign ex_next_instr_q = '0; end endmodule diff --git a/core/compressed_decoder.sv b/core/compressed_decoder.sv index 26c0289a185..76385e5ea0b 100644 --- a/core/compressed_decoder.sv +++ b/core/compressed_decoder.sv @@ -227,6 +227,7 @@ module compressed_decoder #( 1'b0, riscv::OpcodeStore }; + if (instr_i[6] == 1'b1) illegal_instr_o = 1'b1; end default: begin diff --git a/core/controller.sv b/core/controller.sv index 8016869ec32..eae7f8f55b7 100644 --- a/core/controller.sv +++ b/core/controller.sv @@ -53,6 +53,8 @@ module controller input logic halt_csr_i, // Halt request from accelerator dispatcher - ACC_DISPATCHER input logic halt_acc_i, + // Halt frontend during fence.i to prevent fetching stale instructions + output logic halt_frontend_o, // Halt signal to commit stage - COMMIT_STAGE output logic halt_o, // Return from exception - CSR_REGFILE @@ -84,12 +86,15 @@ module controller // active fence - high if we are currently flushing the dcache logic fence_active_d, fence_active_q; logic flush_dcache; + // Added fence_i_active state to track fence.i progress + logic fence_i_active_d, fence_i_active_q; // ------------ // Flush CTRL // ------------ always_comb begin : flush_ctrl fence_active_d = fence_active_q; + fence_i_active_d = fence_i_active_q; set_pc_commit_o = 1'b0; flush_if_o = 1'b0; flush_unissued_instr_o = 1'b0; @@ -124,6 +129,7 @@ module controller flush_ex_o = 1'b1; // this is not needed in the case since we // have a write-through cache in this case + // or we are expecting explicit flush/inval via RVZiCbom if (CVA6Cfg.DcacheFlushOnFence) begin flush_dcache = 1'b1; fence_active_d = 1'b1; @@ -142,16 +148,22 @@ module controller flush_icache_o = 1'b1; // this is not needed in the case since we // have a write-through cache in this case - if (CVA6Cfg.DcacheFlushOnFence) begin - flush_dcache = 1'b1; + // When handling fence.i, flush both caches and activate fence_i state + if (CVA6Cfg.DcacheFlushOnFenceI) begin + flush_dcache = 1'b1; fence_active_d = 1'b1; + fence_i_active_d = 1'b1; end end // this is not needed in the case since we // have a write-through cache in this case - if (CVA6Cfg.DcacheFlushOnFence) begin - // wait for the acknowledge here + if (CVA6Cfg.DcacheFlushOnFence || CVA6Cfg.DcacheFlushOnFenceI) begin + // Wait for the acknowledge here + // Deassert fence_i state only after DCache flush completes + if (flush_dcache_ack_i && fence_i_active_q) begin + fence_i_active_d = 1'b0; + end if (flush_dcache_ack_i && fence_active_q) begin fence_active_d = 1'b0; // keep the flush dcache signal high as long as we didn't get the acknowledge from the cache @@ -242,7 +254,9 @@ module controller // ---------------------- always_comb begin // halt the core if the fence is active - halt_o = halt_csr_i || halt_acc_i || (CVA6Cfg.DcacheFlushOnFence && fence_active_q); + halt_o = halt_csr_i || halt_acc_i || ((CVA6Cfg.DcacheFlushOnFence || CVA6Cfg.DcacheFlushOnFenceI) && fence_active_q); + // Halt frontend during fence.i to synchronize ICache/DCache flushes + halt_frontend_o = fence_i_active_q; end // ---------------------- @@ -250,12 +264,14 @@ module controller // ---------------------- always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin - fence_active_q <= 1'b0; - flush_dcache_o <= 1'b0; + fence_active_q <= 1'b0; + fence_i_active_q <= 1'b0; + flush_dcache_o <= 1'b0; end else begin - fence_active_q <= fence_active_d; + fence_active_q <= fence_active_d; + fence_i_active_q <= fence_i_active_d; // register on the flush signal, this signal might be critical - flush_dcache_o <= flush_dcache; + flush_dcache_o <= flush_dcache; end end endmodule diff --git a/core/csr_buffer.sv b/core/csr_buffer.sv index 3ea7eab05ba..104325e5b0a 100644 --- a/core/csr_buffer.sv +++ b/core/csr_buffer.sv @@ -56,7 +56,7 @@ module csr_buffer csr_reg_n = csr_reg_q; // by default we are ready csr_ready_o = 1'b1; - // if we have a valid uncomiited csr req or are just getting one WITHOUT a commit in, we are not ready + // if we have a valid uncommitted csr req or are just getting one WITHOUT a commit in, we are not ready if ((csr_reg_q.valid || csr_valid_i) && ~csr_commit_i) csr_ready_o = 1'b0; // if we got a valid from the scoreboard // store the CSR address diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index bc9e82720f5..96c6cdba2ae 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -23,13 +23,14 @@ module csr_regfile parameter type scoreboard_entry_t = logic, parameter type rvfi_probes_csr_t = logic, parameter int VmidWidth = 1, - parameter int unsigned MHPMCounterNum = 6 + parameter int unsigned MHPMCounterNum = 6, + parameter int unsigned N_Triggers = 4 ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, - // Timer threw a interrupt - SUBSYSTEM + // Timer threw an interrupt - SUBSYSTEM input logic time_irq_i, // send a flush request out when a CSR with a side effect changes - CONTROLLER output logic flush_o, @@ -37,7 +38,7 @@ module csr_regfile output logic halt_csr_o, // Instruction to be committed - ID_STAGE input scoreboard_entry_t commit_instr_i, - // Commit acknowledged a instruction -> increase instret CSR - COMMIT_STAGE + // Commit acknowledged an instruction -> increase instret CSR - COMMIT_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // Address from which to start booting, mtvec is set to the same address - SUBSYSTEM input logic [CVA6Cfg.VLEN-1:0] boot_addr_i, @@ -53,7 +54,7 @@ module csr_regfile input logic [CVA6Cfg.XLEN-1:0] csr_wdata_i, // Read data out - COMMIT_STAGE output logic [CVA6Cfg.XLEN-1:0] csr_rdata_o, - // Mark the FP sate as dirty - COMMIT_STAGE + // Mark the FP state as dirty - COMMIT_STAGE input logic dirty_fp_state_i, // Write fflags register e.g.: we are retiring a floating point instruction - COMMIT_STAGE input logic csr_write_fflags_i, @@ -71,6 +72,8 @@ module csr_regfile output logic [CVA6Cfg.VLEN-1:0] trap_vector_base_o, // Current privilege level the CPU is in - EX_STAGE output riscv::priv_lvl_t priv_lvl_o, + // Data Endian mode + output logic mbe_o, // Current virtualization mode state the CPU is in - EX_STAGE output logic v_o, // Imprecise FP exception from the accelerator (fcsr.fflags format) - ACC_DISPATCHER @@ -81,7 +84,7 @@ module csr_regfile output riscv::xs_t fs_o, // Floating point extension virtual status - ID_STAGE output riscv::xs_t vfs_o, - // Floating-Point Accured Exceptions - COMMIT_STAGE + // Floating-Point Occurred Exceptions - COMMIT_STAGE output logic [4:0] fflags_o, // Floating-Point Dynamic Rounding Mode - EX_STAGE output logic [2:0] frm_o, @@ -125,6 +128,18 @@ module csr_regfile output logic [CVA6Cfg.PPNW-1:0] hgatp_ppn_o, // TO_BE_COMPLETED - EX_STAGE output logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_o, + // machine-mode cache block invalidate enable - ID_STAGE + output riscv::cbie_t mcbie_o, + // supervisor-mode cache block invalidate enable - ID_STAGE + output riscv::cbie_t scbie_o, + // hypervisor-mode cache block invalidate enable - ID_STAGE + output riscv::cbie_t hcbie_o, + // machine-mode clean/flush cache block invalidate enable - ID_STAGE + output logic mcbcfe_o, + // supervisor-mode clean/flush cache block invalidate enable - ID_STAGE + output logic scbcfe_o, + // hypervisor-mode clean/flush cache block invalidate enable - ID_STAGE + output logic hcbcfe_o, // external interrupt in - SUBSYSTEM input logic [1:0] irq_i, // inter processor interrupt -> connected to machine mode sw - SUBSYSTEM @@ -151,6 +166,13 @@ module csr_regfile output logic icache_en_o, // L1 DCache Enable - CACHE output logic dcache_en_o, + output logic dcache_scrub_en_o, + output logic [5:0] dcache_scrub_period_o, + input logic dcache_scrub_cycle_i, + input logic dcache_dat_cor_err_i, + input logic dcache_dat_unc_err_i, + input logic dcache_dir_cor_err_i, + input logic dcache_dir_unc_err_i, // Accelerator memory consistent mode - ACC_DISPATCHER output logic acc_cons_en_o, // read/write address to performance counter module - PERF_COUNTERS @@ -162,17 +184,42 @@ module csr_regfile // TO_BE_COMPLETED - PERF_COUNTERS output logic perf_we_o, // PMP configuration containing pmpcfg for max 64 PMPs - ACC_DISPATCHER - output riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_o, + output riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_o, // PMP addresses - ACC_DISPATCHER - output logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_o, + output logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_o, // TO_BE_COMPLETED - PERF_COUNTERS output logic [31:0] mcountinhibit_o, // RVFI output rvfi_probes_csr_t rvfi_csr_o, //jvt output - output jvt_t jvt_o + output jvt_t jvt_o, + // trigger module signals + input logic [CVA6Cfg.VLEN-1:0] sdtrig_lsu_inputs_vaddr_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_lsu_inputs_data_i, + input logic sdtrig_lsu_inputs_fu_i, + input ariane_pkg::fu_op sdtrig_lsu_inputs_op_i, + input logic sdtrig_lsu_inputs_valid_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_load_data_i, + input logic sdtrig_load_valid_i, + + //LSU <-> trigger module commmunication + output logic sdtrig_load_stall_o, + output logic sdtrig_load_cancel_o, + output logic [CVA6Cfg.XLEN-1:0] sdtrig_load_action_o, + output logic sdtrig_store_stall_o, + output logic [CVA6Cfg.XLEN-1:0] sdtrig_store_action_o, + + //Decoder/fetch <-> trigger module communication + input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] fetch_sdtrig_pc_i, + input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] fetch_sdtrig_instr_i, + output logic [CVA6Cfg.XLEN-1:0] sdtrig_decoder_action_o[CVA6Cfg.NrIssuePorts], + + //Commit <- trigger module + output logic sdtrig_commit_icount_valid_o, + output logic [$clog2(CVA6Cfg.NrCommitPorts)-1:0] sdtrig_commit_icount_nr_instr_o, + output logic [CVA6Cfg.XLEN-1:0] sdtrig_commit_action_o, + output logic sdtrig_commit_std_exception_valid_o ); - localparam logic [63:0] SMODE_STATUS_READ_MASK = ariane_pkg::smode_status_read_mask(CVA6Cfg); localparam logic [63:0] HS_DELEG_INTERRUPTS = { {32{1'b0}}, ariane_pkg::hs_deleg_interrupts(CVA6Cfg) @@ -195,6 +242,20 @@ module csr_regfile logic [CVA6Cfg.PPNW-1:0] ppn; } hgatp_t; + typedef struct packed { + logic eccPresent; + logic eccScrubberPresent; + logic [CVA6Cfg.XLEN-1:30] rsvd; + logic [3:0] dirCorErr; + logic [3:0] dirUncErr; + logic [3:0] datCorErr; + logic [3:0] datUncErr; + logic [3:0] scrubCycles; + logic [5:0] scrubPeriod; + logic scrubEn; + logic cacheEn; + } dcache_cfg_t; + // internal signal to keep track of access exceptions logic read_access_exception, update_access_exception, privilege_violation; logic virtual_read_access_exception, virtual_update_access_exception, virtual_privilege_violation; @@ -215,6 +276,7 @@ module csr_regfile riscv::hstatus_rv_t hstatus_q, hstatus_d; riscv::mstatus_rv_t vsstatus_q, vsstatus_d; logic [CVA6Cfg.XLEN-1:0] mstatus_extended; + logic [31:0] mstatush; logic [CVA6Cfg.XLEN-1:0] vsstatus_extended; satp_t satp_q, satp_d; satp_t vsatp_q, vsatp_d; @@ -266,7 +328,7 @@ module csr_regfile logic [CVA6Cfg.XLEN-1:0] vscause_q, vscause_d; logic [CVA6Cfg.XLEN-1:0] vstval_q, vstval_d; - logic [CVA6Cfg.XLEN-1:0] dcache_q, dcache_d; + dcache_cfg_t dcache_q, dcache_d; logic [CVA6Cfg.XLEN-1:0] icache_q, icache_d; logic [CVA6Cfg.XLEN-1:0] acc_cons_q, acc_cons_d; @@ -279,6 +341,29 @@ module csr_regfile logic [63:0][CVA6Cfg.PLEN-3:0] pmpaddr_q, pmpaddr_d, pmpaddr_next; logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q; + // CBO enable flags from menvcfg/senvcfg/henvcfg + riscv::cbie_t mcbie_q, mcbie_d, scbie_q, scbie_d, hcbie_q, hcbie_d; + logic mcbcfe_q, mcbcfe_d, scbcfe_q, scbcfe_d, hcbcfe_q, hcbcfe_d; + + // Trigger Module Registers + logic [CVA6Cfg.XLEN-1:0] scontext_d, scontext_q; + logic [CVA6Cfg.XLEN-1:0] tdata1_from_tm; + logic [CVA6Cfg.XLEN-1:0] tdata1_to_tm; + logic [CVA6Cfg.XLEN-1:0] tdata2_from_tm; + logic [CVA6Cfg.XLEN-1:0] tdata2_to_tm; + logic [CVA6Cfg.XLEN-1:0] tdata3_from_tm; + logic [CVA6Cfg.XLEN-1:0] tdata3_to_tm; + logic [CVA6Cfg.XLEN-1:0] tselect_to_tm; + logic [CVA6Cfg.XLEN-1:0] tselect_from_tm; + logic tselect_we, tdata1_we, tdata2_we, tdata3_we; + logic flush_from_tm; + logic sdtrig_commit_std_exception_valid; + //Trigger module helpers + logic sdtrig_etrigger_context_saved_valid; + logic [CVA6Cfg.XLEN-1:0] sdtrig_etrigger_context_mepc; + logic [CVA6Cfg.XLEN-1:0] sdtrig_etrigger_context_mcause; + logic [CVA6Cfg.XLEN-1:0] sdtrig_etrigger_context_mtval; + localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = (CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension | (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // B - Bitmanip extension | (CVA6Cfg.XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension @@ -292,7 +377,7 @@ module csr_regfile | (CVA6Cfg.XLEN'(CVA6Cfg.RVU) << 20) // U - User mode implemented | (CVA6Cfg.XLEN'(CVA6Cfg.RVV) << 21) // V - Vector extension | (CVA6Cfg.XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present - | ((CVA6Cfg.XLEN == 64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL + | ((CVA6Cfg.IS_XLEN64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL assign pmpcfg_o = pmpcfg_q[(CVA6Cfg.NrPMPEntries>0?CVA6Cfg.NrPMPEntries-1 : 0):0]; assign pmpaddr_o = pmpaddr_q[(CVA6Cfg.NrPMPEntries>0?CVA6Cfg.NrPMPEntries-1 : 0):0]; @@ -314,6 +399,7 @@ module csr_regfile // ---------------- assign mstatus_extended = CVA6Cfg.IS_XLEN64 ? mstatus_q[CVA6Cfg.XLEN-1:0] : {mstatus_q.sd, mstatus_q.wpri3[7:0], mstatus_q[22:0]}; + assign mstatush = {24'h0, mstatus_q.mpv, mstatus_q.gva, mstatus_q.mbe, mstatus_q.sbe, 4'h0}; if (CVA6Cfg.RVH) begin if (CVA6Cfg.IS_XLEN64) begin : gen_vsstatus_64read assign vsstatus_extended = vsstatus_q[CVA6Cfg.XLEN-1:0]; @@ -382,11 +468,41 @@ module csr_regfile riscv::CSR_DSCRATCH1: if (CVA6Cfg.DebugEn) csr_rdata = dscratch1_q; else read_access_exception = 1'b1; - // trigger module registers - riscv::CSR_TSELECT: read_access_exception = 1'b1; // not implemented - riscv::CSR_TDATA1: read_access_exception = 1'b1; // not implemented - riscv::CSR_TDATA2: read_access_exception = 1'b1; // not implemented - riscv::CSR_TDATA3: read_access_exception = 1'b1; // not implemented + // Trigger module registers + riscv::CSR_TSELECT: + if (CVA6Cfg.Sdtrig) csr_rdata = tselect_from_tm; + else read_access_exception = 1'b1; + riscv::CSR_TDATA1: + if (CVA6Cfg.Sdtrig) csr_rdata = tdata1_from_tm; + else read_access_exception = 1'b1; + riscv::CSR_TDATA2: + if (CVA6Cfg.Sdtrig) csr_rdata = tdata2_from_tm; + else read_access_exception = 1'b1; + riscv::CSR_TDATA3: + if (CVA6Cfg.Sdtrig && CVA6Cfg.SdtrigSupportTextra) csr_rdata = tdata3_from_tm; + else read_access_exception = 1'b1; + riscv::CSR_TINFO: begin + if (CVA6Cfg.Sdtrig) begin + // trigger info: the supported types icount = 3, itrigger = 4, etrigger = 5, mcontrol6 = 6, disabled = 15 + csr_rdata = { + {CVA6Cfg.XLEN - 32{1'b0}}, + 8'h1, + 8'h0, + 1'b1, + 8'b0, + CVA6Cfg.SdtrigMcontrol6, + CVA6Cfg.SdtrigEtrigger, + CVA6Cfg.SdtrigItrigger, + CVA6Cfg.SdtrigIcount, + 3'b0 + }; + end else begin + read_access_exception = 1'b1; + end + end + riscv::CSR_SCONTEXT: + if (CVA6Cfg.Sdtrig && CVA6Cfg.SdtrigSupportTextra) csr_rdata = scontext_q; + else read_access_exception = 1'b1; riscv::CSR_VSSTATUS: if (CVA6Cfg.RVH) csr_rdata = vsstatus_extended; else read_access_exception = 1'b1; @@ -465,9 +581,17 @@ module csr_regfile read_access_exception = 1'b1; end end - riscv::CSR_SENVCFG: - if (CVA6Cfg.RVS) csr_rdata = '0 | fiom_q; - else read_access_exception = 1'b1; + riscv::CSR_SENVCFG: begin + if (CVA6Cfg.RVS) begin + csr_rdata = '0 | fiom_q; + if (CVA6Cfg.RVZiCbom) begin + csr_rdata[5:4] = scbie_q; + csr_rdata[6] = scbcfe_q; + end + end else begin + read_access_exception = 1'b1; + end + end // hypervisor mode registers riscv::CSR_HSTATUS: if (CVA6Cfg.RVH) csr_rdata = hstatus_q[CVA6Cfg.XLEN-1:0]; @@ -502,9 +626,17 @@ module csr_regfile riscv::CSR_HGEIP: if (CVA6Cfg.RVH) csr_rdata = '0; else read_access_exception = 1'b1; - riscv::CSR_HENVCFG: - if (CVA6Cfg.RVH) csr_rdata = '0 | {{CVA6Cfg.XLEN - 1{1'b0}}, fiom_q}; - else read_access_exception = 1'b1; + riscv::CSR_HENVCFG: begin + if (CVA6Cfg.RVH) begin + csr_rdata = '0 | {{CVA6Cfg.XLEN - 1{1'b0}}, fiom_q}; + if (CVA6Cfg.RVZiCbom) begin + csr_rdata[5:4] = hcbie_q; + csr_rdata[6] = hcbcfe_q; + end + end else begin + read_access_exception = 1'b1; + end + end riscv::CSR_HGATP: begin if (CVA6Cfg.RVH) begin // intercept reads to HGATP if in HS-Mode and TVM is enabled @@ -521,14 +653,15 @@ module csr_regfile // machine mode registers riscv::CSR_MSTATUS: csr_rdata = mstatus_extended; riscv::CSR_MSTATUSH: - if (CVA6Cfg.XLEN == 32) csr_rdata = '0; + if (CVA6Cfg.IS_XLEN32) csr_rdata = mstatush; else read_access_exception = 1'b1; riscv::CSR_MISA: csr_rdata = IsaCode; riscv::CSR_MEDELEG: if (CVA6Cfg.RVS) csr_rdata = medeleg_q; else read_access_exception = 1'b1; riscv::CSR_MIDELEG: - if (CVA6Cfg.RVS) csr_rdata = mideleg_q; + if (CVA6Cfg.RVS) + csr_rdata = (CVA6Cfg.RVH) ? mideleg_q | HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0] : mideleg_q; else read_access_exception = 1'b1; riscv::CSR_MIE: csr_rdata = mie_q; riscv::CSR_MTVEC: csr_rdata = mtvec_q; @@ -549,16 +682,25 @@ module csr_regfile else read_access_exception = 1'b1; riscv::CSR_MIP: csr_rdata = mip_q; riscv::CSR_MENVCFG: begin - if (CVA6Cfg.RVU) csr_rdata = '0 | fiom_q; - else read_access_exception = 1'b1; + csr_rdata = '0; + if (CVA6Cfg.RVU) begin + csr_rdata = '0 | fiom_q; + end + if (CVA6Cfg.RVZiCbom) begin + csr_rdata[5:4] = mcbie_q; + csr_rdata[6] = mcbcfe_q; + end + if (!CVA6Cfg.RVU && !CVA6Cfg.RVZiCbom) begin + read_access_exception = 1'b1; + end end riscv::CSR_MENVCFGH: begin - if (CVA6Cfg.RVU && CVA6Cfg.XLEN == 32) csr_rdata = '0; + if (CVA6Cfg.RVU && CVA6Cfg.IS_XLEN32) csr_rdata = '0; else read_access_exception = 1'b1; end riscv::CSR_MVENDORID: csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID}; riscv::CSR_MARCHID: csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MARCHID}; - riscv::CSR_MIMPID: csr_rdata = '0; // not implemented + riscv::CSR_MIMPID: csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MIMPID}; riscv::CSR_MHARTID: csr_rdata = hart_id_i; riscv::CSR_MCONFIGPTR: csr_rdata = '0; // not implemented riscv::CSR_MCOUNTINHIBIT: @@ -566,18 +708,18 @@ module csr_regfile // Counters and Timers riscv::CSR_MCYCLE: csr_rdata = cycle_q[CVA6Cfg.XLEN-1:0]; riscv::CSR_MCYCLEH: - if (CVA6Cfg.XLEN == 32) csr_rdata = cycle_q[63:32]; + if (CVA6Cfg.IS_XLEN32) csr_rdata = cycle_q[63:32]; else read_access_exception = 1'b1; riscv::CSR_MINSTRET: csr_rdata = instret_q[CVA6Cfg.XLEN-1:0]; riscv::CSR_MINSTRETH: - if (CVA6Cfg.XLEN == 32) csr_rdata = instret_q[63:32]; + if (CVA6Cfg.IS_XLEN32) csr_rdata = instret_q[63:32]; else read_access_exception = 1'b1; riscv::CSR_CYCLE: if (CVA6Cfg.RVZicntr) csr_rdata = cycle_q[CVA6Cfg.XLEN-1:0]; else read_access_exception = 1'b1; riscv::CSR_CYCLEH: if (CVA6Cfg.RVZicntr) - if (CVA6Cfg.XLEN == 32) csr_rdata = cycle_q[63:32]; + if (CVA6Cfg.IS_XLEN32) csr_rdata = cycle_q[63:32]; else read_access_exception = 1'b1; else read_access_exception = 1'b1; riscv::CSR_INSTRET: @@ -585,7 +727,7 @@ module csr_regfile else read_access_exception = 1'b1; riscv::CSR_INSTRETH: if (CVA6Cfg.RVZicntr) - if (CVA6Cfg.XLEN == 32) csr_rdata = instret_q[63:32]; + if (CVA6Cfg.IS_XLEN32) csr_rdata = instret_q[63:32]; else read_access_exception = 1'b1; else read_access_exception = 1'b1; //Event Selector @@ -680,7 +822,7 @@ module csr_regfile riscv::CSR_MHPM_COUNTER_29H, riscv::CSR_MHPM_COUNTER_30H, riscv::CSR_MHPM_COUNTER_31H : - if (CVA6Cfg.XLEN == 32) csr_rdata = perf_data_i; + if (CVA6Cfg.IS_XLEN32) csr_rdata = perf_data_i; else read_access_exception = 1'b1; // Performance counters (User Mode - R/O Shadows) @@ -749,7 +891,7 @@ module csr_regfile riscv::CSR_HPM_COUNTER_30H, riscv::CSR_HPM_COUNTER_31H : if (CVA6Cfg.RVZihpm) begin - if (CVA6Cfg.XLEN == 32) csr_rdata = perf_data_i; + if (CVA6Cfg.IS_XLEN32) csr_rdata = perf_data_i; else read_access_exception = 1'b1; end else begin read_access_exception = 1'b1; @@ -784,11 +926,13 @@ module csr_regfile riscv::CSR_PMPCFG14, riscv::CSR_PMPCFG15: begin // index is calculated using PMPCFG0 as the offset - automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPCFG0; + automatic logic [3:0] index = csr_addr.address[11:0] - riscv::CSR_PMPCFG0; // if index is not even and XLEN==64, raise exception - if (CVA6Cfg.XLEN == 64 && index[0] == 1'b1) read_access_exception = 1'b1; + if (CVA6Cfg.IS_XLEN64 && index[0] == 1'b1) read_access_exception = 1'b1; else begin + // The following line has no effect. It's here just to prevent the synthesizer from crashing + if (CVA6Cfg.IS_XLEN64) index = (index >> 1) << 1; csr_rdata = pmpcfg_q[index*4+:CVA6Cfg.XLEN/8]; end end @@ -881,6 +1025,8 @@ module csr_regfile automatic hgatp_t hgatp; automatic logic [63:0] instret; + mtval_d = '0; + if (CVA6Cfg.RVS) begin satp = satp_q; end @@ -897,6 +1043,8 @@ module csr_regfile // -------------------- cycle_d = cycle_q; instret_d = instret_q; + dcache_d = dcache_q; + if (!(CVA6Cfg.DebugEn && debug_mode_q)) begin // increase instruction retired counter for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin @@ -910,6 +1058,18 @@ module csr_regfile else cycle_d = cycle_q; end + dcache_d.eccPresent = CVA6Cfg.DcacheEccEnable; + dcache_d.eccScrubberPresent = CVA6Cfg.DcacheEccEnable && CVA6Cfg.DcacheEccScrubberEnable; + if (CVA6Cfg.DcacheEccEnable) begin + if (dcache_dat_cor_err_i && (dcache_q.datCorErr != '1)) dcache_d.datCorErr++; + if (dcache_dat_unc_err_i && (dcache_q.datUncErr != '1)) dcache_d.datUncErr++; + if (dcache_dir_cor_err_i && (dcache_q.dirCorErr != '1)) dcache_d.dirCorErr++; + if (dcache_dir_unc_err_i && (dcache_q.dirUncErr != '1)) dcache_d.dirUncErr++; + if (CVA6Cfg.DcacheEccScrubberEnable) begin + if (dcache_scrub_cycle_i && (dcache_q.scrubCycles != '1)) dcache_d.scrubCycles++; + end + end + eret_o = 1'b0; flush_o = 1'b0; update_access_exception = 1'b0; @@ -956,20 +1116,20 @@ module csr_regfile medeleg_d = medeleg_q; mideleg_d = mideleg_q; end - mip_d = mip_q; - mie_d = mie_q; - mepc_d = mepc_q; - mcause_d = mcause_q; + mip_d = mip_q; + mie_d = mie_q; + mepc_d = ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_etrigger_context_saved_valid && mret) ? sdtrig_etrigger_context_mepc : mepc_q; + mcause_d = ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_etrigger_context_saved_valid && mret) ? sdtrig_etrigger_context_mcause : mcause_q; mcounteren_d = mcounteren_q; - mscratch_d = mscratch_q; - if (CVA6Cfg.TvalEn) mtval_d = mtval_q; + mscratch_d = mscratch_q; + if (CVA6Cfg.TvalEn) + mtval_d = ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_etrigger_context_saved_valid && mret) ? sdtrig_etrigger_context_mtval : mtval_q; if (CVA6Cfg.RVH) begin mtinst_d = mtinst_q; mtval2_d = mtval2_q; end fiom_d = fiom_q; - dcache_d = dcache_q; icache_d = icache_q; acc_cons_d = acc_cons_q; @@ -1006,6 +1166,26 @@ module csr_regfile pmpcfg_d = pmpcfg_q; pmpaddr_d = pmpaddr_q; + mcbie_d = mcbie_q; + scbie_d = scbie_q; + hcbie_d = hcbie_q; + + mcbcfe_d = mcbcfe_q; + scbcfe_d = scbcfe_q; + hcbcfe_d = hcbcfe_q; + + // trigger module defaults + tdata1_to_tm = '0; + tdata2_to_tm = '0; + tdata3_to_tm = '0; + tselect_to_tm = '0; + tselect_we = 1'b0; + tdata1_we = 1'b0; + tdata2_we = 1'b0; + tdata3_we = 1'b0; + + if (CVA6Cfg.Sdtrig) scontext_d = scontext_q; + // check for correct access rights and that we are writing if (csr_we) begin unique case (conv_csr_addr.address) @@ -1060,6 +1240,20 @@ module csr_regfile dcsr_d.nmip = 1'b0; dcsr_d.stopcount = 1'b0; dcsr_d.stoptime = 1'b0; + // dcsr.prv is WARL over supported privilege modes + // preserve the previous value on an unsupported write + if (dcsr_d.prv != riscv::PRIV_LVL_M && + !(CVA6Cfg.RVS && dcsr_d.prv == riscv::PRIV_LVL_S) && + !(CVA6Cfg.RVU && dcsr_d.prv == riscv::PRIV_LVL_U)) begin + dcsr_d.prv = dcsr_q.prv; + end + // dcsr.v is WARL: clear it without H or when DRET returns to M-mode + if (!CVA6Cfg.RVH || dcsr_d.prv == riscv::PRIV_LVL_M) dcsr_d.v = 1'b0; + // dcsr.cause is written by hardware only, preserve on a software write + dcsr_d.cause = dcsr_q.cause; + // reserved fields are hardwired to zero + dcsr_d.zero1 = 1'b0; + dcsr_d.zero2 = '0; end else begin update_access_exception = 1'b1; end @@ -1081,11 +1275,52 @@ module csr_regfile update_access_exception = 1'b1; end end - // trigger module CSRs - riscv::CSR_TSELECT: update_access_exception = 1'b1; // not implemented - riscv::CSR_TDATA1: update_access_exception = 1'b1; // not implemented - riscv::CSR_TDATA2: update_access_exception = 1'b1; // not implemented - riscv::CSR_TDATA3: update_access_exception = 1'b1; // not implemented + // Trigger module CSRs + riscv::CSR_TSELECT: begin + if (CVA6Cfg.Sdtrig) begin + tselect_to_tm = csr_wdata; + tselect_we = csr_we; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_TDATA1: begin + if (CVA6Cfg.Sdtrig) begin + tdata1_to_tm = csr_wdata; + tdata1_we = csr_we; + flush_o = flush_from_tm; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_TDATA2: begin + if (CVA6Cfg.Sdtrig) begin + tdata2_to_tm = csr_wdata; + tdata2_we = csr_we; + flush_o = flush_from_tm; + end else begin + update_access_exception = 1'b1; + end + end + riscv::CSR_TDATA3: begin + if (CVA6Cfg.Sdtrig && CVA6Cfg.SdtrigSupportTextra) begin + tdata3_to_tm = csr_wdata; + tdata3_we = csr_we; + end else begin + update_access_exception = 1'b1; + end + end + // tinfo has only read-only fields: a write is ignored + riscv::CSR_TINFO: begin + if (!CVA6Cfg.Sdtrig) update_access_exception = 1'b1; + end + riscv::CSR_SCONTEXT: begin + if (CVA6Cfg.Sdtrig && CVA6Cfg.SdtrigSupportTextra) begin + scontext_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]}; + end else begin + update_access_exception = 1'b1; + end + end // virtual supervisor registers riscv::CSR_VSSTATUS: begin if (CVA6Cfg.RVH) begin @@ -1125,7 +1360,9 @@ module csr_regfile if (CVA6Cfg.RVH) vsscratch_d = csr_wdata; else update_access_exception = 1'b1; riscv::CSR_VSEPC: - if (CVA6Cfg.RVH) vsepc_d = {csr_wdata[CVA6Cfg.XLEN-1:1], 1'b0}; + // bit[1] stays writable only with RVC; without RVC (IALIGN=32) vsepc[1:0] are always zero + if (CVA6Cfg.RVH) + vsepc_d = {csr_wdata[CVA6Cfg.XLEN-1:2], csr_wdata[1] & CVA6Cfg.RVC, 1'b0}; else update_access_exception = 1'b1; riscv::CSR_VSCAUSE: if (CVA6Cfg.RVH) vscause_d = csr_wdata; @@ -1211,7 +1448,9 @@ module csr_regfile if (CVA6Cfg.RVS) sscratch_d = csr_wdata; else update_access_exception = 1'b1; riscv::CSR_SEPC: - if (CVA6Cfg.RVS) sepc_d = {csr_wdata[CVA6Cfg.XLEN-1:1], 1'b0}; + // bit[1] stays writable only with RVC; without RVC (IALIGN=32) sepc[1:0] are always zero + if (CVA6Cfg.RVS) + sepc_d = {csr_wdata[CVA6Cfg.XLEN-1:2], csr_wdata[1] & CVA6Cfg.RVC, 1'b0}; else update_access_exception = 1'b1; riscv::CSR_SCAUSE: if (CVA6Cfg.RVS) scause_d = csr_wdata; @@ -1240,9 +1479,22 @@ module csr_regfile update_access_exception = 1'b1; end end - riscv::CSR_SENVCFG: - if (CVA6Cfg.RVU) fiom_d = csr_wdata[0]; - else update_access_exception = 1'b1; + riscv::CSR_SENVCFG: begin + if (CVA6Cfg.RVS) begin + fiom_d = csr_wdata[0]; + if (CVA6Cfg.RVZiCbom) begin + unique case (csr_wdata[5:4]) + 2'b00: scbie_d = riscv::CBIE_ILLEGAL; + 2'b01: scbie_d = riscv::CBIE_FLUSH; + 2'b11: scbie_d = riscv::CBIE_INVAL; + default: scbie_d = scbie_q; + endcase + scbcfe_d = csr_wdata[6]; + end + end else begin + update_access_exception = 1'b1; + end + end //hypervisor mode registers riscv::CSR_HSTATUS: begin if (CVA6Cfg.RVH) begin @@ -1313,7 +1565,7 @@ module csr_regfile end riscv::CSR_HTVAL: begin if (CVA6Cfg.RVH) begin - htval_d = csr_wdata; + htval_d = {{CVA6Cfg.XLEN - CVA6Cfg.GPLEN + 2{1'b0}}, csr_wdata[CVA6Cfg.GPLEN-3:0]}; end else begin update_access_exception = 1'b1; end @@ -1342,10 +1594,11 @@ module csr_regfile hgatp[1:0] = 2'b0; // only make VMID_LEN - 1 bit stick, that way software can figure out how many VMID bits are supported hgatp.vmid = hgatp.vmid & {{(CVA6Cfg.VMIDW - CVA6Cfg.VMID_WIDTH) {1'b0}}, {CVA6Cfg.VMID_WIDTH{1'b1}}}; - // only update if we actually support this mode - if (config_pkg::vm_mode_t'(hgatp.mode) == config_pkg::ModeOff || - config_pkg::vm_mode_t'(hgatp.mode) == CVA6Cfg.MODE_SV) - hgatp_d = hgatp; + // Preserve the current mode if the written mode is unsupported. + if (config_pkg::vm_mode_t'(hgatp.mode) != config_pkg::ModeOff && + config_pkg::vm_mode_t'(hgatp.mode) != CVA6Cfg.MODE_SV) + hgatp.mode = hgatp_q.mode; + hgatp_d = hgatp; end // changing the mode can have side-effects on address translation (e.g.: other instructions), re-fetch // the next instruction by executing a flush @@ -1354,9 +1607,22 @@ module csr_regfile update_access_exception = 1'b1; end end - riscv::CSR_HENVCFG: - if (CVA6Cfg.RVH) fiom_d = csr_wdata[0]; - else update_access_exception = 1'b1; + riscv::CSR_HENVCFG: begin + if (CVA6Cfg.RVH) begin + fiom_d = csr_wdata[0]; + if (CVA6Cfg.RVZiCbom) begin + unique case (csr_wdata[5:4]) + 2'b00: hcbie_d = riscv::CBIE_ILLEGAL; + 2'b01: hcbie_d = riscv::CBIE_FLUSH; + 2'b11: hcbie_d = riscv::CBIE_INVAL; + default: hcbie_d = hcbie_q; + endcase + hcbcfe_d = csr_wdata[6]; + end + end else begin + update_access_exception = 1'b1; + end + end riscv::CSR_MSTATUS: begin mstatus_d = {{64 - CVA6Cfg.XLEN{1'b0}}, csr_wdata}; mstatus_d.xs = riscv::Off; @@ -1379,20 +1645,38 @@ module csr_regfile mstatus_d.tw = riscv::Off; mstatus_d.mprv = riscv::Off; end - if ((!CVA6Cfg.RVH & mstatus_d.mpp == riscv::PRIV_LVL_HS) | + if (!CVA6Cfg.RVH) begin + mstatus_d.mpv = 1'b0; + mstatus_d.gva = 1'b0; + end + if ((mstatus_d.mpp == riscv::PRIV_LVL_HS) | (!CVA6Cfg.RVS & mstatus_d.mpp == riscv::PRIV_LVL_S) | (!CVA6Cfg.RVU & mstatus_d.mpp == riscv::PRIV_LVL_U)) begin mstatus_d.mpp = mstatus_q.mpp; end mstatus_d.wpri3 = 9'b0; + mstatus_d.wpri4 = '0; mstatus_d.wpri1 = 1'b0; mstatus_d.wpri2 = 1'b0; mstatus_d.wpri0 = 1'b0; - mstatus_d.ube = 1'b0; // CVA6 is little-endian + // Mirror MBE + mstatus_d.sbe = mstatus_d.mbe; + mstatus_d.ube = mstatus_d.mbe; // this register has side-effects on other registers, flush the pipeline flush_o = 1'b1; end - riscv::CSR_MSTATUSH: if (CVA6Cfg.XLEN != 32) update_access_exception = 1'b1; + riscv::CSR_MSTATUSH: begin + if (CVA6Cfg.IS_XLEN32) begin + mstatus_d.mbe = ((csr_wdata & riscv::MSTATUSH_MBE) != 0); + // Mirror MBE + mstatus_d.sbe = mstatus_d.mbe; + mstatus_d.ube = mstatus_d.mbe; + // this register has side-effects on other registers, flush the pipeline + flush_o = 1'b1; + end else begin + update_access_exception = 1'b1; + end + end // MISA is WARL (Write Any Value, Reads Legal Value) riscv::CSR_MISA: ; // machine exception delegation register @@ -1483,16 +1767,22 @@ module csr_regfile end riscv::CSR_MSCRATCH: mscratch_d = csr_wdata; - riscv::CSR_MEPC: mepc_d = {csr_wdata[CVA6Cfg.XLEN-1:1], 1'b0}; - riscv::CSR_MCAUSE: mcause_d = csr_wdata; + riscv::CSR_MEPC: + // bit[1] stays writable only with RVC; without RVC (IALIGN=32) mepc[1:0] are always zero + mepc_d = ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_etrigger_context_saved_valid && mret) ? sdtrig_etrigger_context_mepc + : {csr_wdata[CVA6Cfg.XLEN-1:2], csr_wdata[1] & CVA6Cfg.RVC, 1'b0}; + riscv::CSR_MCAUSE: + mcause_d = ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_etrigger_context_saved_valid && mret) ? sdtrig_etrigger_context_mcause : {csr_wdata[CVA6Cfg.XLEN - 1], {CVA6Cfg.XLEN - 6{1'b0}}, csr_wdata[4:0]}; riscv::CSR_MTVAL: begin - if (CVA6Cfg.TvalEn) mtval_d = csr_wdata; + if (CVA6Cfg.TvalEn) + mtval_d = ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_etrigger_context_saved_valid && mret) ? sdtrig_etrigger_context_mtval : csr_wdata; end riscv::CSR_MTINST: if (CVA6Cfg.RVH) mtinst_d = {{CVA6Cfg.XLEN - 32{1'b0}}, csr_wdata[31:0]}; else update_access_exception = 1'b1; riscv::CSR_MTVAL2: - if (CVA6Cfg.RVH) mtval2_d = csr_wdata; + if (CVA6Cfg.RVH) + mtval2_d = {{CVA6Cfg.XLEN - CVA6Cfg.GPLEN + 2{1'b0}}, csr_wdata[CVA6Cfg.GPLEN-3:0]}; else update_access_exception = 1'b1; riscv::CSR_MIP: begin if (CVA6Cfg.RVH) begin @@ -1509,9 +1799,22 @@ module csr_regfile end mip_d = (mip_q & ~mask) | (csr_wdata & mask); end - riscv::CSR_MENVCFG: if (CVA6Cfg.RVU) fiom_d = csr_wdata[0]; + riscv::CSR_MENVCFG: begin + if (CVA6Cfg.RVU) begin + fiom_d = csr_wdata[0]; + end + if (CVA6Cfg.RVZiCbom) begin + unique case (csr_wdata[5:4]) + 2'b00: mcbie_d = riscv::CBIE_ILLEGAL; + 2'b01: mcbie_d = riscv::CBIE_FLUSH; + 2'b11: mcbie_d = riscv::CBIE_INVAL; + default: mcbie_d = mcbie_q; + endcase + mcbcfe_d = csr_wdata[6]; + end + end riscv::CSR_MENVCFGH: begin - if (!CVA6Cfg.RVU || CVA6Cfg.XLEN != 32) update_access_exception = 1'b1; + if (!CVA6Cfg.RVU || !CVA6Cfg.IS_XLEN32) update_access_exception = 1'b1; end riscv::CSR_MCOUNTINHIBIT: if (CVA6Cfg.PerfCounterEn) @@ -1520,11 +1823,11 @@ module csr_regfile // performance counters riscv::CSR_MCYCLE: cycle_d[CVA6Cfg.XLEN-1:0] = csr_wdata; riscv::CSR_MCYCLEH: - if (CVA6Cfg.XLEN == 32) cycle_d[63:32] = csr_wdata; + if (CVA6Cfg.IS_XLEN32) cycle_d[63:32] = csr_wdata; else update_access_exception = 1'b1; riscv::CSR_MINSTRET: instret_d[CVA6Cfg.XLEN-1:0] = csr_wdata; riscv::CSR_MINSTRETH: - if (CVA6Cfg.XLEN == 32) instret_d[63:32] = csr_wdata; + if (CVA6Cfg.IS_XLEN32) instret_d[63:32] = csr_wdata; else update_access_exception = 1'b1; //Event Selector riscv::CSR_MHPM_EVENT_3, @@ -1623,11 +1926,11 @@ module csr_regfile riscv::CSR_MHPM_COUNTER_30H, riscv::CSR_MHPM_COUNTER_31H : begin perf_we_o = 1'b1; - if (CVA6Cfg.XLEN == 32) perf_data_o = csr_wdata; + if (CVA6Cfg.IS_XLEN32) perf_data_o = csr_wdata; else update_access_exception = 1'b1; end - riscv::CSR_DCACHE: dcache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit + riscv::CSR_DCACHE: dcache_d = csr_wdata; // enable bit riscv::CSR_ICACHE: icache_d = {{CVA6Cfg.XLEN - 1{1'b0}}, csr_wdata[0]}; // enable bit riscv::CSR_ACC_CONS: begin if (CVA6Cfg.EnableAccelerator) begin @@ -1660,7 +1963,7 @@ module csr_regfile automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPCFG0; // if index is not even and XLEN==64, raise exception - if (CVA6Cfg.XLEN == 64 && index[0] == 1'b1) update_access_exception = 1'b1; + if (CVA6Cfg.IS_XLEN64 && index[0] == 1'b1) update_access_exception = 1'b1; else begin for (int i = 0; i < CVA6Cfg.XLEN / 8; i++) begin if (!pmpcfg_q[index*4+i].locked) pmpcfg_d[index*4+i] = csr_wdata[i*8+:8]; @@ -1734,16 +2037,24 @@ module csr_regfile // index is calculated using PMPADDR0 as the offset automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPADDR0; // check if the entry or the entry above is locked - if (!pmpcfg_q[index].locked && !(pmpcfg_q[index+1].locked && pmpcfg_q[index+1].addr_mode == riscv::TOR)) begin - pmpaddr_d[index] = csr_wdata[CVA6Cfg.PLEN-3:0]; + if (!pmpcfg_q[index].locked) begin + if (index < 63) begin + if (!(pmpcfg_q[index+1].locked && pmpcfg_q[index+1].addr_mode == riscv::TOR)) begin + pmpaddr_d[index] = csr_wdata[CVA6Cfg.PLEN-3:0]; + end + end else begin + pmpaddr_d[index] = csr_wdata[CVA6Cfg.PLEN-3:0]; + end end end default: update_access_exception = 1'b1; endcase end if (CVA6Cfg.IS_XLEN64) begin - mstatus_d.sxl = riscv::XLEN_64; - mstatus_d.uxl = riscv::XLEN_64; + if (CVA6Cfg.RVS) mstatus_d.sxl = riscv::XLEN_64; + else mstatus_d.sxl = riscv::XLEN_NA; + if (CVA6Cfg.RVU) mstatus_d.uxl = riscv::XLEN_64; + else mstatus_d.uxl = riscv::XLEN_NA; end if (!CVA6Cfg.RVU) begin mstatus_d.mpp = riscv::PRIV_LVL_M; @@ -1766,12 +2077,12 @@ module csr_regfile end // hardwired extension registers if (CVA6Cfg.RVS || CVA6Cfg.RVF) begin - mstatus_d.sd = (mstatus_q.xs == riscv::Dirty) | (mstatus_q.fs == riscv::Dirty); + mstatus_d.sd = (mstatus_d.xs == riscv::Dirty) | (mstatus_d.fs == riscv::Dirty); end else begin mstatus_d.sd = riscv::Off; end if (CVA6Cfg.RVH) begin - vsstatus_d.sd = (vsstatus_q.xs == riscv::Dirty) | (vsstatus_q.fs == riscv::Dirty); + vsstatus_d.sd = (vsstatus_d.xs == riscv::Dirty) | (vsstatus_d.fs == riscv::Dirty); end // reserve PMPCFG bits 5 and 6 (hardwire to 0) @@ -1811,7 +2122,7 @@ module csr_regfile trap_to_v = 1'b0; // Exception is taken and we are not in debug mode // exceptions in debug mode don't update any fields - if ((CVA6Cfg.DebugEn && !debug_mode_q && ex_i.cause != riscv::DEBUG_REQUEST && ex_i.valid) || (!CVA6Cfg.DebugEn && ex_i.valid)) begin + if ((CVA6Cfg.DebugEn && !debug_mode_q && !(ex_i.cause inside {riscv::DEBUG_REQUEST, riscv::DEBUG_TRIGGER}) && ex_i.valid) || (!CVA6Cfg.DebugEn && ex_i.valid)) begin // do not flush, flush is reserved for CSR writes with side effects flush_o = 1'b0; // figure out where to trap to @@ -1853,12 +2164,12 @@ module csr_regfile // set epc vsepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; // set vstval - vstval_d = (ariane_pkg::ZERO_TVAL + vstval_d = ((ariane_pkg::ZERO_TVAL && (ex_i.cause inside { riscv::ILLEGAL_INSTR, riscv::BREAKPOINT, riscv::ENV_CALL_UMODE - } || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : ex_i.tval; + })) || ex_i.cause[CVA6Cfg.XLEN-1]) ? '0 : ex_i.tval; end else begin // update sstatus mstatus_d.sie = 1'b0; @@ -1870,14 +2181,14 @@ module csr_regfile // set epc sepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; // set mtval or stval - stval_d = (ariane_pkg::ZERO_TVAL + stval_d = ((ariane_pkg::ZERO_TVAL && (ex_i.cause inside { riscv::ILLEGAL_INSTR, riscv::BREAKPOINT, riscv::ENV_CALL_UMODE, riscv::ENV_CALL_SMODE, riscv::ENV_CALL_MMODE - } || ex_i.cause[CVA6Cfg.XLEN-1])) ? '0 : ex_i.tval; + })) || ex_i.cause[CVA6Cfg.XLEN-1]) ? '0 : ex_i.tval; if (CVA6Cfg.RVH) begin htinst_d = (ariane_pkg::ZERO_TVAL && (ex_i.cause inside { @@ -1904,21 +2215,23 @@ module csr_regfile mstatus_d.mpie = mstatus_q.mie; // save the previous privilege mode mstatus_d.mpp = priv_lvl_q; - mcause_d = ex_i.cause; - // set epc - mepc_d = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; + //set cause and epc adapted to etrigger + mcause_d = ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_etrigger_context_saved_valid && mret) ? sdtrig_etrigger_context_mcause : ex_i.cause; + mepc_d = ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_etrigger_context_saved_valid && mret) ? sdtrig_etrigger_context_mepc : {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{pc_i[CVA6Cfg.VLEN-1]}}, pc_i}; // set mtval or stval if (CVA6Cfg.TvalEn) begin - mtval_d = (ariane_pkg::ZERO_TVAL - && (ex_i.cause inside { - riscv::ILLEGAL_INSTR, - riscv::BREAKPOINT, - riscv::ENV_CALL_UMODE, - riscv::ENV_CALL_SMODE, - riscv::ENV_CALL_MMODE - } || ex_i.cause[CVA6Cfg.GPLEN-1])) ? '0 : ex_i.tval; - end else begin - mtval_d = '0; + if ((CVA6Cfg.SdtrigEtrigger || CVA6Cfg.SdtrigItrigger) && sdtrig_etrigger_context_saved_valid && mret) begin + mtval_d = sdtrig_etrigger_context_mtval; + end else begin + mtval_d = ((ariane_pkg::ZERO_TVAL + && (ex_i.cause inside { + riscv::ILLEGAL_INSTR, + riscv::BREAKPOINT, + riscv::ENV_CALL_UMODE, + riscv::ENV_CALL_SMODE, + riscv::ENV_CALL_MMODE + })) || ex_i.cause[CVA6Cfg.XLEN-1]) ? '0 : ex_i.tval; + end end if (CVA6Cfg.RVH) begin @@ -1962,7 +2275,6 @@ module csr_regfile dcsr_d.prv = priv_lvl_o; // save virtualization mode bit dcsr_d.v = (!CVA6Cfg.RVH) ? 1'b0 : v_q; - // trigger module fired // caused by a breakpoint if (ex_i.valid && ex_i.cause == riscv::BREAKPOINT) begin @@ -1995,7 +2307,7 @@ module csr_regfile end // we've got a debug request - if (ex_i.valid && ex_i.cause == riscv::DEBUG_REQUEST) begin + if (ex_i.valid && ex_i.cause inside {riscv::DEBUG_REQUEST, riscv::DEBUG_TRIGGER}) begin dcsr_d.prv = priv_lvl_o; dcsr_d.v = (!CVA6Cfg.RVH) ? 1'b0 : v_q; // save the PC @@ -2004,8 +2316,8 @@ module csr_regfile debug_mode_d = 1'b1; // jump to the base address set_debug_pc_o = 1'b1; - // save the cause as external debug request - dcsr_d.cause = ariane_pkg::CauseRequest; + // save the cause: a trigger or an external debug request + dcsr_d.cause = (ex_i.cause == riscv::DEBUG_TRIGGER) ? ariane_pkg::CauseTrigger : ariane_pkg::CauseRequest; end // single step enable and we just retired an instruction @@ -2113,12 +2425,12 @@ module csr_regfile end // set mpie to 1 mstatus_d.mpie = 1'b1; + if (mstatus_q.mpp != riscv::PRIV_LVL_M) mstatus_d.mprv = 1'b0; if (CVA6Cfg.RVH) begin - // set virtualization mode - v_d = mstatus_q.mpv; + // MPV is ignored when returning to M-mode. + v_d = (mstatus_q.mpp == riscv::PRIV_LVL_M) ? 1'b0 : mstatus_q.mpv; //set mstatus mpv to false mstatus_d.mpv = 1'b0; - if (mstatus_q.mpp != riscv::PRIV_LVL_M) mstatus_d.mprv = 1'b0; end end @@ -2133,12 +2445,12 @@ module csr_regfile mstatus_d.spp = 1'b0; // set spie to 1 mstatus_d.spie = 1'b1; + mstatus_d.mprv = 1'b0; if (CVA6Cfg.RVH) begin // set virtualization mode - v_d = hstatus_q.spv; + v_d = hstatus_q.spv; //set hstatus spv to false - hstatus_d.spv = 1'b0; - mstatus_d.mprv = 1'b0; + hstatus_d.spv = 1'b0; end end @@ -2166,7 +2478,7 @@ module csr_regfile priv_lvl_d = riscv::priv_lvl_t'(dcsr_q.prv); if (CVA6Cfg.RVH) begin // restore the previous virtualization mode - v_d = dcsr_q.v; + v_d = (dcsr_q.prv == riscv::PRIV_LVL_M) ? 1'b0 : dcsr_q.v; end // actually return from debug mode debug_mode_d = 1'b0; @@ -2266,7 +2578,7 @@ module csr_regfile // counter address range is C00 to C1F if (CVA6Cfg.RVZihpm) begin if (csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3 : riscv::CSR_HPM_COUNTER_31]} | - csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3H : riscv::CSR_HPM_COUNTER_31H]}) begin + (CVA6Cfg.IS_XLEN32 && csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3H : riscv::CSR_HPM_COUNTER_31H]})) begin if (curr_priv == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin virtual_privilege_violation = v_q & mcounteren_q[sel_cnt_en] & ~hcounteren_q[sel_cnt_en]; privilege_violation = ~mcounteren_q[sel_cnt_en]; @@ -2284,7 +2596,7 @@ module csr_regfile end if (CVA6Cfg.RVZicntr) begin if (csr_addr_i inside {[riscv::CSR_CYCLE : riscv::CSR_INSTRET]} | - csr_addr_i inside {[riscv::CSR_CYCLEH : riscv::CSR_INSTRETH]}) begin + (CVA6Cfg.IS_XLEN32 && csr_addr_i inside {[riscv::CSR_CYCLEH : riscv::CSR_INSTRETH]})) begin if (curr_priv == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin virtual_privilege_violation = v_q & mcounteren_q[sel_cnt_en] & ~hcounteren_q[sel_cnt_en]; privilege_violation = ~mcounteren_q[sel_cnt_en]; @@ -2320,7 +2632,7 @@ module csr_regfile // counter address range is C00 to C1F if (CVA6Cfg.RVZihpm) begin if (csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3 : riscv::CSR_HPM_COUNTER_31]} | - csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3H : riscv::CSR_HPM_COUNTER_31H]}) begin + (CVA6Cfg.IS_XLEN32 && csr_addr_i inside {[riscv::CSR_HPM_COUNTER_3H : riscv::CSR_HPM_COUNTER_31H]})) begin if (priv_lvl_o == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin privilege_violation = ~mcounteren_q[csr_addr_i[4:0]]; end else if (priv_lvl_o == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin @@ -2332,7 +2644,7 @@ module csr_regfile end if (CVA6Cfg.RVZicntr) begin if (csr_addr_i inside {[riscv::CSR_CYCLE : riscv::CSR_INSTRET]} | - csr_addr_i inside {[riscv::CSR_CYCLEH : riscv::CSR_INSTRETH]}) begin + (CVA6Cfg.IS_XLEN32 && csr_addr_i inside {[riscv::CSR_CYCLEH : riscv::CSR_INSTRETH]})) begin if (priv_lvl_o == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin privilege_violation = ~mcounteren_q[csr_addr_i[4:0]]; end else if (priv_lvl_o == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin @@ -2387,7 +2699,7 @@ module csr_regfile wfi_d = 1'b0; // or alternatively if there is no exception pending and we are not in debug mode wait here // for the interrupt - end else if (((CVA6Cfg.DebugEn && !debug_mode_q) && csr_op_i == WFI && !ex_i.valid) || (!CVA6Cfg.DebugEn && csr_op_i == WFI && !ex_i.valid)) begin + end else if (((CVA6Cfg.DebugEn && !debug_mode_q && !dcsr_q.step) && csr_op_i == WFI && !ex_i.valid) || (!CVA6Cfg.DebugEn && csr_op_i == WFI && !ex_i.valid)) begin wfi_d = 1'b1; end end @@ -2487,6 +2799,14 @@ module csr_regfile assign sum_o = mstatus_q.sum; assign vs_sum_o = CVA6Cfg.RVH ? vsstatus_q.sum : '0; assign hu_o = CVA6Cfg.RVH ? hstatus_q.hu : '0; + + assign mcbie_o = CVA6Cfg.RVZiCbom ? mcbie_q : riscv::CBIE_ILLEGAL; + assign scbie_o = CVA6Cfg.RVZiCbom ? scbie_q : riscv::CBIE_ILLEGAL; + assign hcbie_o = CVA6Cfg.RVZiCbom ? hcbie_q : riscv::CBIE_ILLEGAL; + + assign mcbcfe_o = CVA6Cfg.RVZiCbom ? mcbcfe_q : 1'b0; + assign scbcfe_o = CVA6Cfg.RVZiCbom ? scbcfe_q : 1'b0; + assign hcbcfe_o = CVA6Cfg.RVZiCbom ? hcbcfe_q : 1'b0; // we support bare memory addressing and SV39 if (CVA6Cfg.RVH) begin assign en_translation_o = (((config_pkg::vm_mode_t'(satp_q.mode) == CVA6Cfg.MODE_SV && !v_q) || (config_pkg::vm_mode_t'(vsatp_q.mode) == CVA6Cfg.MODE_SV && v_q)) && @@ -2524,15 +2844,19 @@ module csr_regfile `else assign icache_en_o = icache_q[0] & ~(CVA6Cfg.DebugEn && debug_mode_q); `endif - assign dcache_en_o = dcache_q[0]; + assign dcache_en_o = dcache_q.cacheEn; + assign dcache_scrub_en_o = dcache_q.scrubEn; + assign dcache_scrub_period_o = dcache_q.scrubPeriod; assign acc_cons_en_o = CVA6Cfg.EnableAccelerator ? acc_cons_q[0] : 1'b0; // determine if mprv needs to be considered if in debug mode assign mprv = (CVA6Cfg.DebugEn && debug_mode_q && !dcsr_q.mprven) ? 1'b0 : mstatus_q.mprv; - assign debug_mode_o = debug_mode_q; + assign debug_mode_o = CVA6Cfg.DebugEn ? debug_mode_q : 1'b0; assign single_step_o = CVA6Cfg.DebugEn ? dcsr_q.step : 1'b0; assign mcountinhibit_o = {{29 - MHPMCounterNum{1'b0}}, mcountinhibit_q}; + assign mbe_o = mstatus_q.mbe; + // sequential process always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin @@ -2563,21 +2887,29 @@ module csr_regfile mscratch_q <= {CVA6Cfg.XLEN{1'b0}}; if (CVA6Cfg.TvalEn) mtval_q <= {CVA6Cfg.XLEN{1'b0}}; fiom_q <= '0; - dcache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; + dcache_q <= '{cacheEn: 1'b1, default: '0}; icache_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, 1'b1}; mcountinhibit_q <= '0; acc_cons_q <= {{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.EnableAccelerator}; + if (CVA6Cfg.RVZiCbom) begin + mcbie_q <= riscv::CBIE_INVAL; + mcbcfe_q <= 1'b1; + end // supervisor mode registers if (CVA6Cfg.RVS) begin - medeleg_q <= {CVA6Cfg.XLEN{1'b0}}; - mideleg_q <= {CVA6Cfg.XLEN{1'b0}}; - sepc_q <= {CVA6Cfg.XLEN{1'b0}}; - scause_q <= {CVA6Cfg.XLEN{1'b0}}; - stvec_q <= {CVA6Cfg.XLEN{1'b0}}; + medeleg_q <= {CVA6Cfg.XLEN{1'b0}}; + mideleg_q <= (CVA6Cfg.RVH) ? CVA6Cfg.XLEN'(HS_DELEG_INTERRUPTS[CVA6Cfg.XLEN-1:0]) : {CVA6Cfg.XLEN{1'b0}}; + sepc_q <= {CVA6Cfg.XLEN{1'b0}}; + scause_q <= {CVA6Cfg.XLEN{1'b0}}; + stvec_q <= {CVA6Cfg.XLEN{1'b0}}; scounteren_q <= {CVA6Cfg.XLEN{1'b0}}; - sscratch_q <= {CVA6Cfg.XLEN{1'b0}}; - stval_q <= {CVA6Cfg.XLEN{1'b0}}; - satp_q <= {CVA6Cfg.XLEN{1'b0}}; + sscratch_q <= {CVA6Cfg.XLEN{1'b0}}; + stval_q <= {CVA6Cfg.XLEN{1'b0}}; + satp_q <= {CVA6Cfg.XLEN{1'b0}}; + if (CVA6Cfg.RVZiCbom) begin + scbie_q <= riscv::CBIE_INVAL; + scbcfe_q <= 1'b1; + end end if (CVA6Cfg.RVH) begin @@ -2601,6 +2933,13 @@ module csr_regfile vstval_q <= {CVA6Cfg.XLEN{1'b0}}; vsatp_q <= {CVA6Cfg.XLEN{1'b0}}; en_ld_st_g_translation_q <= 1'b0; + if (CVA6Cfg.RVZiCbom) begin + hcbie_q <= riscv::CBIE_INVAL; + hcbcfe_q <= 1'b1; + end + end + if (CVA6Cfg.Sdtrig) begin + scontext_q <= '0; end // timer and counters cycle_q <= 64'b0; @@ -2650,6 +2989,10 @@ module csr_regfile icache_q <= icache_d; mcountinhibit_q <= mcountinhibit_d; acc_cons_q <= acc_cons_d; + if (CVA6Cfg.RVZiCbom) begin + mcbie_q <= mcbie_d; + mcbcfe_q <= mcbcfe_d; + end // supervisor mode registers if (CVA6Cfg.RVS) begin medeleg_q <= medeleg_d; @@ -2661,6 +3004,10 @@ module csr_regfile sscratch_q <= sscratch_d; if (CVA6Cfg.TvalEn) stval_q <= stval_d; satp_q <= satp_d; + if (CVA6Cfg.RVZiCbom) begin + scbie_q <= scbie_d; + scbcfe_q <= scbcfe_d; + end end if (CVA6Cfg.RVH) begin v_q <= v_d; @@ -2684,6 +3031,13 @@ module csr_regfile vstval_q <= vstval_d; vsatp_q <= vsatp_d; en_ld_st_g_translation_q <= en_ld_st_g_translation_d; + if (CVA6Cfg.RVZiCbom) begin + hcbie_q <= hcbie_d; + hcbcfe_q <= hcbcfe_d; + end + end + if (CVA6Cfg.Sdtrig) begin + scontext_q <= scontext_d; end // timer and counters cycle_q <= cycle_d; @@ -2698,6 +3052,8 @@ module csr_regfile end end + assign sdtrig_commit_std_exception_valid_o = sdtrig_commit_std_exception_valid; + // write logic pmp always_comb begin : write for (int i = 0; i < 64; i++) begin @@ -2728,6 +3084,90 @@ module csr_regfile end end + //------------- + // Trigger Module + //------------- + generate + if (CVA6Cfg.Sdtrig) begin : tm_gen + trigger_module #( + .CVA6Cfg (CVA6Cfg), + .exception_t(exception_t) + ) trigger_module_i ( + .clk_i, + .rst_ni, + .commit_ack_i (commit_ack_i), + .ex_i (ex_i), + .sdtrig_lsu_inputs_vaddr_i (sdtrig_lsu_inputs_vaddr_i), + .fetch_sdtrig_instr_i (fetch_sdtrig_instr_i), + .sdtrig_lsu_inputs_data_i (sdtrig_lsu_inputs_data_i), + .sdtrig_lsu_inputs_fu_i (sdtrig_lsu_inputs_fu_i), + .sdtrig_lsu_inputs_op_i (sdtrig_lsu_inputs_op_i), + .sdtrig_lsu_inputs_valid_i (sdtrig_lsu_inputs_valid_i), + .sdtrig_load_data_i (sdtrig_load_data_i), + .sdtrig_load_valid_i (sdtrig_load_valid_i), + .priv_lvl_i (priv_lvl_o), + .debug_mode_i (debug_mode_q), + .mret_i (mret), + .sret_i (sret), + .mstatus_mie_i (mstatus_q.mie), + .mstatus_sie_i (mstatus_q.sie), + .medeleg_breakpoint_i (medeleg_q[$clog2(CVA6Cfg.XLEN)'(riscv::BREAKPOINT)]), + .scontext_i (scontext_q), + .tselect_i (tselect_to_tm), + .tdata1_i (tdata1_to_tm), + .tdata2_i (tdata2_to_tm), + .tdata3_i (tdata3_to_tm), + .tselect_we (tselect_we), + .tdata1_we (tdata1_we), + .tdata2_we (tdata2_we), + .tdata3_we (tdata3_we), + .tselect_o (tselect_from_tm), + .tdata1_o (tdata1_from_tm), + .tdata2_o (tdata2_from_tm), + .tdata3_o (tdata3_from_tm), + .flush_o (flush_from_tm), + .mepc_i (mepc_d), + .mcause_i (mcause_d), + .mtval_i (mtval_d), + .etrigger_context_saved_valid_o (sdtrig_etrigger_context_saved_valid), + .etrigger_context_mepc_o (sdtrig_etrigger_context_mepc), + .etrigger_context_mcause_o (sdtrig_etrigger_context_mcause), + .etrigger_context_mtval_o (sdtrig_etrigger_context_mtval), + .sdtrig_commit_std_exception_valid_o(sdtrig_commit_std_exception_valid), + .fetch_sdtrig_pc_i (fetch_sdtrig_pc_i), + .sdtrig_decoder_action_o (sdtrig_decoder_action_o), + .sdtrig_load_stall_o (sdtrig_load_stall_o), + .sdtrig_load_cancel_o (sdtrig_load_cancel_o), + .sdtrig_load_action_o (sdtrig_load_action_o), + .sdtrig_store_stall_o (sdtrig_store_stall_o), + .sdtrig_store_action_o (sdtrig_store_action_o), + .sdtrig_commit_icount_valid_o (sdtrig_commit_icount_valid_o), + .sdtrig_commit_action_o (sdtrig_commit_action_o), + .sdtrig_commit_icount_nr_instr_o (sdtrig_commit_icount_nr_instr_o) + ); + end else begin + assign tdata1_from_tm = '0; + assign tdata2_from_tm = '0; + assign tdata3_from_tm = '0; + assign tselect_from_tm = '0; + assign flush_from_tm = 0; + assign sdtrig_commit_std_exception_valid = '0; + assign sdtrig_etrigger_context_saved_valid = '0; + assign sdtrig_etrigger_context_mepc = '0; + assign sdtrig_etrigger_context_mcause = '0; + assign sdtrig_etrigger_context_mtval = '0; + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) assign sdtrig_decoder_action_o[i] = '0; + assign sdtrig_load_stall_o = '0; + assign sdtrig_load_cancel_o = '0; + assign sdtrig_load_action_o = '0; + assign sdtrig_store_stall_o = '0; + assign sdtrig_store_action_o = '0; + assign sdtrig_commit_icount_valid_o = '0; + assign sdtrig_commit_action_o = '0; + assign sdtrig_commit_icount_nr_instr_o = '0; + end + endgenerate + //------------- // Assertions //------------- diff --git a/core/cva6.sv b/core/cva6.sv index e42e6c389c4..f1f416dfea7 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -35,11 +35,12 @@ module cva6 // this is the struct which we will inject into the pipeline to guide the various // units towards the correct branch decision and resolve localparam type branchpredict_sbe_t = struct packed { + logic valid; // valid control flow prediction cf_t cf; // type of control flow prediction logic [CVA6Cfg.VLEN-1:0] predict_address; // target address at which to jump, or not }, - localparam type exception_t = struct packed { + parameter type exception_t = struct packed { logic [CVA6Cfg.XLEN-1:0] cause; // cause of exception logic [CVA6Cfg.XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it), // address of LD/ST fault @@ -47,6 +48,8 @@ module cva6 logic [31:0] tinst; // transformed instruction information logic gva; // signals when a guest virtual address is written to tval logic valid; + //timing of exception, timing = 0 : break immediately or timing = 1 break immediatemy AFTER (let current instruction commit but only this one) + logic timing; }, // cache request ports @@ -164,8 +167,13 @@ module cva6 fu_t fu; fu_op operation; logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; + logic is_speculative_load; + logic is_speculative_load_miss; }, + + localparam type cbo_t = logic [7:0], + localparam type fu_data_t = struct packed { fu_t fu; fu_op operation; @@ -179,7 +187,7 @@ module cva6 logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] way; // way to replace logic [CVA6Cfg.PLEN-1:0] paddr; // physical address logic nc; // noncacheable - logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // thread id (used as transaction id in Ariane) }, localparam type icache_rtrn_t = struct packed { wt_cache_pkg::icache_in_t rtype; // see definitions above @@ -191,7 +199,7 @@ module cva6 logic [CVA6Cfg.ICACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] way; // way to invalidate } inv; // invalidation vector - logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid; // thread id (used as transaction id in Ariane) }, // D$ data requests @@ -207,6 +215,7 @@ module cva6 logic [CVA6Cfg.DcacheIdWidth-1:0] data_id; logic kill_req; logic tag_valid; + cbo_t cbo_op; }, localparam type dcache_req_o_t = struct packed { @@ -215,8 +224,17 @@ module cva6 logic [CVA6Cfg.DcacheIdWidth-1:0] data_rid; logic [CVA6Cfg.XLEN-1:0] data_rdata; logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_ruser; + logic data_error; }, + // Accelerator - CVA6 + parameter type accelerator_req_t = logic, + parameter type accelerator_resp_t = logic, + + // Accelerator - CVA6's MMU + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic, + // AXI types parameter type axi_ar_chan_t = struct packed { logic [CVA6Cfg.AxiIdWidth-1:0] id; @@ -292,13 +310,13 @@ module cva6 parameter type hartid_t = `HARTID_T(CVA6Cfg), parameter type x_compressed_req_t = `X_COMPRESSED_REQ_T(CVA6Cfg, hartid_t), parameter type x_compressed_resp_t = `X_COMPRESSED_RESP_T(CVA6Cfg), - parameter type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartit_t, id_t), + parameter type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartid_t, id_t), parameter type x_issue_resp_t = `X_ISSUE_RESP_T(CVA6Cfg, writeregflags_t, readregflags_t), parameter type x_register_t = `X_REGISTER_T(CVA6Cfg, hartid_t, id_t, readregflags_t), parameter type x_commit_t = `X_COMMIT_T(CVA6Cfg, hartid_t, id_t), parameter type x_result_t = `X_RESULT_T(CVA6Cfg, hartid_t, id_t, writeregflags_t), parameter type cvxif_req_t = - `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t), + `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_t, x_commit_t), parameter type cvxif_resp_t = `CVXIF_RESP_T(CVA6Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t) ) ( @@ -344,30 +362,31 @@ module cva6 }; localparam interrupts_t INTERRUPTS = '{ - S_SW: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_SOFT), - VS_SW: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_VS_SOFT), - M_SW: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_SOFT), - S_TIMER: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_TIMER), - VS_TIMER: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_VS_TIMER), - M_TIMER: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_TIMER), - S_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_EXT), - VS_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_VS_EXT), - M_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_EXT), - HS_EXT: (1 << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_HS_EXT) + S_SW: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_SOFT), + VS_SW: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_VS_SOFT), + M_SW: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_SOFT), + S_TIMER: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_TIMER), + VS_TIMER: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_VS_TIMER), + M_TIMER: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_TIMER), + S_EXT: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_S_EXT), + VS_EXT: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_VS_EXT), + M_EXT: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_M_EXT), + HS_EXT: (CVA6Cfg.XLEN'(1) << (CVA6Cfg.XLEN - 1)) | CVA6Cfg.XLEN'(riscv::IRQ_HS_EXT) }; // ------------------------------------------ // Global Signals // Signals connecting more than one module // ------------------------------------------ - riscv::priv_lvl_t priv_lvl; - logic v; - exception_t ex_commit; // exception from commit stage - bp_resolve_t resolved_branch; - logic [ CVA6Cfg.VLEN-1:0] pc_commit; - logic eret; - logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack; - logic [CVA6Cfg.NrCommitPorts-1:0] commit_macro_ack; + riscv::priv_lvl_t priv_lvl; + logic v; + exception_t ex_commit; // exception from commit stage + bp_resolve_t resolved_branch; + logic [CVA6Cfg.VLEN-1:0] pc_commit; + logic eret; + logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack; + logic [CVA6Cfg.NrCommitPorts-1:0] commit_macro_ack; + logic mbe; // determines the data endian-ness of the processor localparam NumPorts = 4; @@ -422,6 +441,7 @@ module cva6 logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2; fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_id_ex; + alu_bypass_t alu_bypass_id_ex; logic [CVA6Cfg.VLEN-1:0] pc_id_ex; logic zcmt_id_ex; logic is_compressed_instr_id_ex; @@ -434,6 +454,8 @@ module cva6 exception_t flu_exception_ex_id; // ALU logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_id_ex; + logic [5:0] orig_instr_aes; + logic [CVA6Cfg.NrIssuePorts-1:0] aes_valid_id_ex; // Branches and Jumps logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_id_ex; @@ -463,6 +485,7 @@ module cva6 logic [CVA6Cfg.XLEN-1:0] fpu_result_ex_id; logic fpu_valid_ex_id; exception_t fpu_exception_ex_id; + logic fpu_early_valid_ex_id; // ALU2 logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_id_ex; // Accelerator @@ -505,10 +528,16 @@ module cva6 logic stall_st_pending_ex; logic no_st_pending_ex; logic no_st_pending_commit; + logic shared_tlb_flush_busy_ex; logic amo_valid_commit; // ACCEL Commit logic acc_valid_acc_ex; // -------------- + // EX <-> ACC_DISP + // -------------- + acc_mmu_req_t acc_mmu_req; + acc_mmu_resp_t acc_mmu_resp; + // -------------- // ID <-> COMMIT // -------------- scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_id_commit; @@ -563,17 +592,42 @@ module cva6 logic tsr_csr_id; logic hu; irq_ctrl_t irq_ctrl_csr_id; - logic dcache_en_csr_nbdcache; + logic dcache_en_csr; + logic dcache_scrub_en_csr; + logic [5:0] dcache_scrub_period_csr; + logic dcache_scrub_cycle_csr; + logic dcache_dat_cor_err_csr; + logic dcache_dat_unc_err_csr; + logic dcache_dir_cor_err_csr; + logic dcache_dir_unc_err_csr; logic csr_write_fflags_commit_cs; logic icache_en_csr; logic acc_cons_en_csr; logic debug_mode; logic single_step_csr_commit; - riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg; - logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr; + riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg; + logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr; logic [31:0] mcountinhibit_csr_perf; //jvt jvt_t jvt; + // trigger module + logic + sdtrig_commit_std_exception_valid, + sdtrig_sb_std_exception_valid, + sdtrig_load_stall, + sdtrig_load_cancel, + sdtrig_store_stall; + logic [CVA6Cfg.XLEN-1:0] sdtrig_decoder_action[CVA6Cfg.NrIssuePorts]; + logic [CVA6Cfg.XLEN-1:0] sdtrig_load_action, sdtrig_store_action, sdtrig_commit_action; + logic [CVA6Cfg.VLEN-1:0] sdtrig_lsu_inputs_operand_a; + logic [CVA6Cfg.XLEN-1:0] sdtrig_lsu_inputs_operand_c; + logic sdtrig_lsu_inputs_we, sdtrig_lsu_inputs_valid; + fu_op sdtrig_lsu_inputs_op; + logic sdtrig_commit_icount_valid; + logic [$clog2(CVA6Cfg.NrCommitPorts)-1:0] sdtrig_commit_icount_nr_instr; + + riscv::cbie_t mcbie, scbie, hcbie; + logic mcbcfe, scbcfe, hcbcfe; // ---------------------------- // Performance Counters <-> * // ---------------------------- @@ -607,6 +661,7 @@ module cva6 logic hfence_vvma_commit_controller; logic hfence_gvma_commit_controller; logic halt_ctrl; + logic halt_frontend; logic halt_csr_ctrl; logic dcache_flush_ctrl_cache; logic dcache_flush_ack_cache_ctrl; @@ -659,9 +714,11 @@ module cva6 .clk_i, .rst_ni, .boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]), - .flush_bp_i (1'b0), - .flush_i (flush_ctrl_if), // not entirely correct + .flush_bp_i ((CVA6Cfg.RVU || CVA6Cfg.RVS) ? flush_ctrl_bp : 1'b0), + // below line is not entirely correct + .flush_i (flush_ctrl_if), .halt_i (halt_ctrl), + .halt_frontend_i (halt_frontend), .set_pc_commit_i (set_pc_ctrl_pcgen), .pc_commit_i (pc_commit), .ex_valid_i (ex_commit.valid), @@ -714,29 +771,37 @@ module cva6 .rvfi_is_compressed_o(rvfi_is_compressed), - .priv_lvl_i (priv_lvl), - .v_i (v), - .fs_i (fs), - .vfs_i (vfs), - .frm_i (frm_csr_id_issue_ex), - .vs_i (vs), - .irq_i (irq_i), - .irq_ctrl_i (irq_ctrl_csr_id), - .debug_mode_i (debug_mode), - .tvm_i (tvm_csr_id), - .tw_i (tw_csr_id), - .vtw_i (vtw_csr_id), - .tsr_i (tsr_csr_id), - .hu_i (hu), - .hart_id_i (hart_id_i), - .compressed_ready_i(x_compressed_ready), - .compressed_resp_i (x_compressed_resp), - .compressed_valid_o(x_compressed_valid), - .compressed_req_o (x_compressed_req), - .jvt_i (jvt), + .priv_lvl_i (priv_lvl), + .v_i (v), + .fs_i (fs), + .vfs_i (vfs), + .frm_i (frm_csr_id_issue_ex), + .vs_i (vs), + .irq_i (irq_i), + .irq_ctrl_i (irq_ctrl_csr_id), + .debug_mode_i (debug_mode), + .tvm_i (tvm_csr_id), + .tw_i (tw_csr_id), + .vtw_i (vtw_csr_id), + .tsr_i (tsr_csr_id), + .hu_i (hu), + .mcbie_i (mcbie), + .scbie_i (scbie), + .hcbie_i (hcbie), + .mcbcfe_i (mcbcfe), + .scbcfe_i (scbcfe), + .hcbcfe_i (hcbcfe), + .hart_id_i (hart_id_i), + .compressed_ready_i (x_compressed_ready), + .compressed_resp_i (x_compressed_resp), + .compressed_valid_o (x_compressed_valid), + .compressed_req_o (x_compressed_req), + .jvt_i (jvt), // DCACHE interfaces - .dcache_req_ports_i(dcache_req_ports_cache_id), - .dcache_req_ports_o(dcache_req_ports_id_cache) + .dcache_req_ports_i (dcache_req_ports_cache_id), + .dcache_req_ports_o (dcache_req_ports_id_cache), + //Trigger Module command signal + .sdtrig_decoder_action_i(sdtrig_decoder_action) ); logic [CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_ex_id; @@ -764,17 +829,18 @@ module cva6 assign ex_ex_ex_id[FPU_WB] = fpu_exception_ex_id; assign wt_valid_ex_id[FPU_WB] = fpu_valid_ex_id; - always_comb begin : gen_cvxif_input_assignement - x_compressed_ready = cvxif_resp_i.compressed_ready; - x_compressed_resp = cvxif_resp_i.compressed_resp; - x_issue_ready = cvxif_resp_i.issue_ready; - x_issue_resp = cvxif_resp_i.issue_resp; - x_register_ready = cvxif_resp_i.register_ready; - x_result_valid = cvxif_resp_i.result_valid; - x_result = cvxif_resp_i.result; - end if (CVA6Cfg.CvxifEn) begin - always_comb begin : gen_cvxif_output_assignement + always_comb begin : gen_cvxif_input_assignment + x_compressed_ready = cvxif_resp_i.compressed_ready; + x_compressed_resp = cvxif_resp_i.compressed_resp; + x_issue_ready = cvxif_resp_i.issue_ready; + x_issue_resp = cvxif_resp_i.issue_resp; + x_register_ready = cvxif_resp_i.register_ready; + x_result_valid = cvxif_resp_i.result_valid; + x_result = cvxif_resp_i.result; + end + + always_comb begin : gen_cvxif_output_assignment cvxif_req.compressed_valid = x_compressed_valid; cvxif_req.compressed_req = x_compressed_req; cvxif_req.issue_valid = x_issue_valid; @@ -797,6 +863,13 @@ module cva6 assign wt_valid_ex_id[ACC_WB] = acc_valid_ex_id; end else begin assign cvxif_req = '0; + assign x_compressed_ready = '0; + assign x_compressed_resp = '0; + assign x_issue_ready = '0; + assign x_issue_resp = '0; + assign x_register_ready = '0; + assign x_result_valid = '0; + assign x_result = '0; end if (CVA6Cfg.CvxifEn && CVA6Cfg.EnableAccelerator) begin : gen_err_xif_and_acc @@ -836,6 +909,7 @@ module cva6 .rs1_forwarding_o (rs1_forwarding_id_ex), .rs2_forwarding_o (rs2_forwarding_id_ex), .fu_data_o (fu_data_id_ex), + .alu_bypass_o (alu_bypass_id_ex), .pc_o (pc_id_ex), .is_zcmt_o (zcmt_id_ex), .is_compressed_instr_o (is_compressed_instr_id_ex), @@ -844,6 +918,7 @@ module cva6 .flu_ready_i (flu_ready_ex_id), // ALU .alu_valid_o (alu_valid_id_ex), + .aes_valid_o (aes_valid_id_ex), // Branches and Jumps .branch_valid_o (branch_valid_id_ex), // branch is valid .branch_predict_o (branch_predict_id_ex), // branch predict to ex @@ -858,6 +933,7 @@ module cva6 .fpu_valid_o (fpu_valid_id_ex), .fpu_fmt_o (fpu_fmt_id_ex), .fpu_rm_o (fpu_rm_id_ex), + .fpu_early_valid_i (fpu_early_valid_ex_id), // ALU2 .alu2_valid_o (alu2_valid_id_ex), // CSR @@ -902,7 +978,8 @@ module cva6 .rvfi_issue_pointer_o (rvfi_issue_pointer), .rvfi_commit_pointer_o(rvfi_commit_pointer), .rvfi_rs1_o (rvfi_rs1), - .rvfi_rs2_o (rvfi_rs2) + .rvfi_rs2_o (rvfi_rs2), + .orig_instr_aes_bits (orig_instr_aes) ); // --------- @@ -921,7 +998,10 @@ module cva6 .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), .lsu_ctrl_t(lsu_ctrl_t), - .x_result_t(x_result_t) + .x_result_t(x_result_t), + .acc_mmu_req_t(acc_mmu_req_t), + .acc_mmu_resp_t(acc_mmu_resp_t), + .cbo_t(cbo_t) ) ex_stage_i ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -930,6 +1010,7 @@ module cva6 .rs1_forwarding_i(rs1_forwarding_id_ex), .rs2_forwarding_i(rs2_forwarding_id_ex), .fu_data_i(fu_data_id_ex), + .alu_bypass_i(alu_bypass_id_ex), .pc_i(pc_id_ex), .is_zcmt_i(zcmt_id_ex), .is_compressed_instr_i(is_compressed_instr_id_ex), @@ -942,6 +1023,8 @@ module cva6 .flu_ready_o(flu_ready_ex_id), // ALU .alu_valid_i(alu_valid_id_ex), + .orig_instr_aes_i(orig_instr_aes), + .aes_valid_i(aes_valid_id_ex), // Branches and Jumps .branch_valid_i(branch_valid_id_ex), .branch_predict_i(branch_predict_id_ex), // branch predict to ex @@ -968,81 +1051,98 @@ module cva6 .store_valid_o (store_valid_ex_id), .store_exception_o(store_exception_ex_id), - .lsu_commit_i (lsu_commit_commit_ex), // from commit - .lsu_commit_ready_o (lsu_commit_ready_ex_commit), // to commit - .commit_tran_id_i (lsu_commit_trans_id), // from commit - .stall_st_pending_i (stall_st_pending_ex), - .no_st_pending_o (no_st_pending_ex), + .lsu_commit_i (lsu_commit_commit_ex), // from commit + .lsu_commit_ready_o (lsu_commit_ready_ex_commit), // to commit + .commit_tran_id_i (lsu_commit_trans_id), // from commit + .stall_st_pending_i (stall_st_pending_ex), + .shared_tlb_flush_busy_o (shared_tlb_flush_busy_ex), + .no_st_pending_o (no_st_pending_ex), // FPU - .fpu_ready_o (fpu_ready_ex_id), - .fpu_valid_i (fpu_valid_id_ex), - .fpu_fmt_i (fpu_fmt_id_ex), - .fpu_rm_i (fpu_rm_id_ex), - .fpu_frm_i (frm_csr_id_issue_ex), - .fpu_prec_i (fprec_csr_ex), - .fpu_trans_id_o (fpu_trans_id_ex_id), - .fpu_result_o (fpu_result_ex_id), - .fpu_valid_o (fpu_valid_ex_id), - .fpu_exception_o (fpu_exception_ex_id), + .fpu_ready_o (fpu_ready_ex_id), + .fpu_valid_i (fpu_valid_id_ex), + .fpu_fmt_i (fpu_fmt_id_ex), + .fpu_rm_i (fpu_rm_id_ex), + .fpu_frm_i (frm_csr_id_issue_ex), + .fpu_prec_i (fprec_csr_ex), + .fpu_trans_id_o (fpu_trans_id_ex_id), + .fpu_result_o (fpu_result_ex_id), + .fpu_valid_o (fpu_valid_ex_id), + .fpu_exception_o (fpu_exception_ex_id), + .fpu_early_valid_o (fpu_early_valid_ex_id), // ALU2 - .alu2_valid_i (alu2_valid_id_ex), - .amo_valid_commit_i (amo_valid_commit), - .amo_req_o (amo_req), - .amo_resp_i (amo_resp), + .alu2_valid_i (alu2_valid_id_ex), + .amo_valid_commit_i (amo_valid_commit), + .amo_req_o (amo_req), + .amo_resp_i (amo_resp), // CoreV-X-Interface - .x_valid_i (x_issue_valid_id_ex), - .x_ready_o (x_issue_ready_ex_id), - .x_off_instr_i (x_off_instr_id_ex), - .x_transaction_rejected_i(x_transaction_rejected), - .x_trans_id_o (x_trans_id_ex_id), - .x_exception_o (x_exception_ex_id), - .x_result_o (x_result_ex_id), - .x_valid_o (x_valid_ex_id), - .x_we_o (x_we_ex_id), - .x_rd_o (x_rd_ex_id), - .x_result_valid_i (x_result_valid), - .x_result_i (x_result), - .x_result_ready_o (x_result_ready), + .x_valid_i (x_issue_valid_id_ex), + .x_ready_o (x_issue_ready_ex_id), + .x_off_instr_i (x_off_instr_id_ex), + .x_transaction_rejected_i (x_transaction_rejected), + .x_trans_id_o (x_trans_id_ex_id), + .x_exception_o (x_exception_ex_id), + .x_result_o (x_result_ex_id), + .x_valid_o (x_valid_ex_id), + .x_we_o (x_we_ex_id), + .x_rd_o (x_rd_ex_id), + .x_result_valid_i (x_result_valid), + .x_result_i (x_result), + .x_result_ready_o (x_result_ready), // Accelerator - .acc_valid_i (acc_valid_acc_ex), + .acc_valid_i (acc_valid_acc_ex), + // Accelerator MMU access + .acc_mmu_req_i (acc_mmu_req), + .acc_mmu_resp_o (acc_mmu_resp), // Performance counters - .itlb_miss_o (itlb_miss_ex_perf), - .dtlb_miss_o (dtlb_miss_ex_perf), + .itlb_miss_o (itlb_miss_ex_perf), + .dtlb_miss_o (dtlb_miss_ex_perf), // Memory Management - .enable_translation_i (enable_translation_csr_ex), // from CSR - .enable_g_translation_i (enable_g_translation_csr_ex), // from CSR - .en_ld_st_translation_i (en_ld_st_translation_csr_ex), - .en_ld_st_g_translation_i(en_ld_st_g_translation_csr_ex), - .flush_tlb_i (flush_tlb_ctrl_ex), - .flush_tlb_vvma_i (flush_tlb_vvma_ctrl_ex), - .flush_tlb_gvma_i (flush_tlb_gvma_ctrl_ex), - .priv_lvl_i (priv_lvl), // from CSR - .v_i (v), // from CSR - .ld_st_priv_lvl_i (ld_st_priv_lvl_csr_ex), // from CSR - .ld_st_v_i (ld_st_v_csr_ex), // from CSR - .sum_i (sum_csr_ex), // from CSR - .vs_sum_i (vs_sum_csr_ex), // from CSR - .mxr_i (mxr_csr_ex), // from CSR - .vmxr_i (vmxr_csr_ex), // from CSR - .satp_ppn_i (satp_ppn_csr_ex), // from CSR - .asid_i (asid_csr_ex), // from CSR - .vsatp_ppn_i (vsatp_ppn_csr_ex), // from CSR - .vs_asid_i (vs_asid_csr_ex), // from CSR - .hgatp_ppn_i (hgatp_ppn_csr_ex), // from CSR - .vmid_i (vmid_csr_ex), // from CSR - .icache_areq_i (icache_areq_cache_ex), - .icache_areq_o (icache_areq_ex_cache), + .enable_translation_i (enable_translation_csr_ex), // from CSR + .enable_g_translation_i (enable_g_translation_csr_ex), // from CSR + .en_ld_st_translation_i (en_ld_st_translation_csr_ex), + .en_ld_st_g_translation_i (en_ld_st_g_translation_csr_ex), + .flush_tlb_i (flush_tlb_ctrl_ex), + .flush_tlb_vvma_i (flush_tlb_vvma_ctrl_ex), + .flush_tlb_gvma_i (flush_tlb_gvma_ctrl_ex), + .priv_lvl_i (priv_lvl), // from CSR + .mbe_i (mbe), // from CSR + .v_i (v), // from CSR + .ld_st_priv_lvl_i (ld_st_priv_lvl_csr_ex), // from CSR + .ld_st_v_i (ld_st_v_csr_ex), // from CSR + .sum_i (sum_csr_ex), // from CSR + .vs_sum_i (vs_sum_csr_ex), // from CSR + .mxr_i (mxr_csr_ex), // from CSR + .vmxr_i (vmxr_csr_ex), // from CSR + .satp_ppn_i (satp_ppn_csr_ex), // from CSR + .asid_i (asid_csr_ex), // from CSR + .vsatp_ppn_i (vsatp_ppn_csr_ex), // from CSR + .vs_asid_i (vs_asid_csr_ex), // from CSR + .hgatp_ppn_i (hgatp_ppn_csr_ex), // from CSR + .vmid_i (vmid_csr_ex), // from CSR + .icache_areq_i (icache_areq_cache_ex), + .icache_areq_o (icache_areq_ex_cache), // DCACHE interfaces - .dcache_req_ports_i (dcache_req_ports_cache_ex), - .dcache_req_ports_o (dcache_req_ports_ex_cache), - .dcache_wbuffer_empty_i (dcache_commit_wbuffer_empty), - .dcache_wbuffer_not_ni_i (dcache_commit_wbuffer_not_ni), + .dcache_req_ports_i (dcache_req_ports_cache_ex), + .dcache_req_ports_o (dcache_req_ports_ex_cache), + .dcache_wbuffer_empty_i (dcache_commit_wbuffer_empty), + .dcache_wbuffer_not_ni_i (dcache_commit_wbuffer_not_ni), // PMP - .pmpcfg_i (pmpcfg), - .pmpaddr_i (pmpaddr), + .pmpcfg_i (pmpcfg), + .pmpaddr_i (pmpaddr), //RVFI - .rvfi_lsu_ctrl_o (rvfi_lsu_ctrl), - .rvfi_mem_paddr_o (rvfi_mem_paddr) + .rvfi_lsu_ctrl_o (rvfi_lsu_ctrl), + .rvfi_mem_paddr_o (rvfi_mem_paddr), + //Trigger module command signals + .sdtrig_load_stall_i (sdtrig_load_stall), + .sdtrig_load_cancel_i (sdtrig_load_cancel), + .sdtrig_load_action_i (sdtrig_load_action), + .sdtrig_store_stall_i (sdtrig_store_stall), + .sdtrig_store_action_i (sdtrig_store_action), + .sdtrig_lsu_inputs_operand_a_o(sdtrig_lsu_inputs_operand_a), + .sdtrig_lsu_inputs_operand_c_o(sdtrig_lsu_inputs_operand_c), + .sdtrig_lsu_inputs_we_o (sdtrig_lsu_inputs_we), + .sdtrig_lsu_inputs_op_o (sdtrig_lsu_inputs_op), + .sdtrig_lsu_inputs_valid_o (sdtrig_lsu_inputs_valid) ); // --------- @@ -1060,38 +1160,43 @@ module cva6 ) commit_stage_i ( .clk_i, .rst_ni, - .halt_i (halt_ctrl), - .flush_dcache_i (dcache_flush_ctrl_cache), - .exception_o (ex_commit), - .dirty_fp_state_o (dirty_fp_state), - .single_step_i (single_step_csr_commit || single_step_acc_commit), - .commit_instr_i (commit_instr_id_commit), - .commit_drop_i (commit_drop_id_commit), - .commit_ack_o (commit_ack_commit_id), - .commit_macro_ack_o(commit_macro_ack), - .waddr_o (waddr_commit_id), - .wdata_o (wdata_commit_id), - .we_gpr_o (we_gpr_commit_id), - .we_fpr_o (we_fpr_commit_id), - .amo_resp_i (amo_resp), - .pc_o (pc_commit), - .csr_op_o (csr_op_commit_csr), - .csr_wdata_o (csr_wdata_commit_csr), - .csr_rdata_i (csr_rdata_csr_commit), - .csr_write_fflags_o(csr_write_fflags_commit_cs), - .csr_exception_i (csr_exception_csr_commit), - .commit_lsu_o (lsu_commit_commit_ex), - .commit_lsu_ready_i(lsu_commit_ready_ex_commit), - .commit_tran_id_o (lsu_commit_trans_id), - .amo_valid_commit_o(amo_valid_commit), - .no_st_pending_i (no_st_pending_commit), - .commit_csr_o (csr_commit_commit_ex), - .fence_i_o (fence_i_commit_controller), - .fence_o (fence_commit_controller), - .flush_commit_o (flush_commit), - .sfence_vma_o (sfence_vma_commit_controller), - .hfence_vvma_o (hfence_vvma_commit_controller), - .hfence_gvma_o (hfence_gvma_commit_controller) + .halt_i (halt_ctrl), + .flush_dcache_i (dcache_flush_ctrl_cache), + .exception_o (ex_commit), + .dirty_fp_state_o (dirty_fp_state), + .single_step_i (single_step_csr_commit || single_step_acc_commit), + .commit_instr_i (commit_instr_id_commit), + .commit_drop_i (commit_drop_id_commit), + .commit_ack_o (commit_ack_commit_id), + .commit_macro_ack_o (commit_macro_ack), + .waddr_o (waddr_commit_id), + .wdata_o (wdata_commit_id), + .we_gpr_o (we_gpr_commit_id), + .we_fpr_o (we_fpr_commit_id), + .amo_resp_i (amo_resp), + .pc_o (pc_commit), + .csr_op_o (csr_op_commit_csr), + .csr_wdata_o (csr_wdata_commit_csr), + .csr_rdata_i (csr_rdata_csr_commit), + .csr_write_fflags_o (csr_write_fflags_commit_cs), + .csr_exception_i (csr_exception_csr_commit), + .commit_lsu_o (lsu_commit_commit_ex), + .commit_lsu_ready_i (lsu_commit_ready_ex_commit), + .commit_tran_id_o (lsu_commit_trans_id), + .amo_valid_commit_o (amo_valid_commit), + .no_st_pending_i (no_st_pending_commit), + .shared_tlb_flush_busy_i (shared_tlb_flush_busy_ex), + .commit_csr_o (csr_commit_commit_ex), + .fence_i_o (fence_i_commit_controller), + .fence_o (fence_commit_controller), + .flush_commit_o (flush_commit), + .sfence_vma_o (sfence_vma_commit_controller), + .hfence_vvma_o (hfence_vvma_commit_controller), + .hfence_gvma_o (hfence_gvma_commit_controller), + .sdtrig_commit_std_exception_valid_i(sdtrig_commit_std_exception_valid), + .sdtrig_commit_icount_valid_i (sdtrig_commit_icount_valid), + .sdtrig_commit_action_i (sdtrig_commit_action), + .sdtrig_commit_icount_nr_instr_i (sdtrig_commit_icount_nr_instr) ); assign commit_ack = commit_macro_ack & ~commit_drop_id_commit; @@ -1099,6 +1204,15 @@ module cva6 // --------- // CSR // --------- + + //Trigger Module assignments + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] fetch_sdtrig_pc; + logic [CVA6Cfg.NrIssuePorts-1:0][31:0] fetch_sdtrig_instr; + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; ++i) begin + assign fetch_sdtrig_pc[i] = CVA6Cfg.SdtrigMcontrol6ExecAddr ? fetch_entry_if_id[i].address : '0; + assign fetch_sdtrig_instr[i] = CVA6Cfg.SdtrigMcontrol6ExecData ? fetch_entry_if_id[i].instruction : '0; + end + csr_regfile #( .CVA6Cfg (CVA6Cfg), .exception_t (exception_t), @@ -1111,77 +1225,114 @@ module cva6 .clk_i, .rst_ni, .time_irq_i, - .flush_o (flush_csr_ctrl), - .halt_csr_o (halt_csr_ctrl), - .commit_instr_i (commit_instr_id_commit[0]), - .commit_ack_i (commit_ack), - .boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]), - .hart_id_i (hart_id_i[CVA6Cfg.XLEN-1:0]), - .ex_i (ex_commit), - .csr_op_i (csr_op_commit_csr), - .csr_addr_i (csr_addr_ex_csr), - .csr_wdata_i (csr_wdata_commit_csr), - .csr_rdata_o (csr_rdata_csr_commit), - .dirty_fp_state_i (dirty_fp_state), - .csr_write_fflags_i (csr_write_fflags_commit_cs), - .dirty_v_state_i (dirty_v_state), - .pc_i (pc_commit), - .csr_exception_o (csr_exception_csr_commit), - .epc_o (epc_commit_pcgen), - .eret_o (eret), - .trap_vector_base_o (trap_vector_base_commit_pcgen), - .priv_lvl_o (priv_lvl), - .v_o (v), - .acc_fflags_ex_i (acc_resp_fflags), - .acc_fflags_ex_valid_i (acc_resp_fflags_valid), - .fs_o (fs), - .vfs_o (vfs), - .fflags_o (fflags_csr_commit), - .frm_o (frm_csr_id_issue_ex), - .fprec_o (fprec_csr_ex), - .vs_o (vs), - .irq_ctrl_o (irq_ctrl_csr_id), - .en_translation_o (enable_translation_csr_ex), - .en_g_translation_o (enable_g_translation_csr_ex), - .en_ld_st_translation_o (en_ld_st_translation_csr_ex), - .en_ld_st_g_translation_o(en_ld_st_g_translation_csr_ex), - .ld_st_priv_lvl_o (ld_st_priv_lvl_csr_ex), - .ld_st_v_o (ld_st_v_csr_ex), - .csr_hs_ld_st_inst_i (csr_hs_ld_st_inst_ex), - .sum_o (sum_csr_ex), - .vs_sum_o (vs_sum_csr_ex), - .mxr_o (mxr_csr_ex), - .vmxr_o (vmxr_csr_ex), - .satp_ppn_o (satp_ppn_csr_ex), - .asid_o (asid_csr_ex), - .vsatp_ppn_o (vsatp_ppn_csr_ex), - .vs_asid_o (vs_asid_csr_ex), - .hgatp_ppn_o (hgatp_ppn_csr_ex), - .vmid_o (vmid_csr_ex), + .flush_o (flush_csr_ctrl), + .halt_csr_o (halt_csr_ctrl), + .commit_instr_i (commit_instr_id_commit[0]), + .commit_ack_i (commit_ack), + .boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]), + .hart_id_i (hart_id_i[CVA6Cfg.XLEN-1:0]), + .ex_i (ex_commit), + .csr_op_i (csr_op_commit_csr), + .csr_addr_i (csr_addr_ex_csr), + .csr_wdata_i (csr_wdata_commit_csr), + .csr_rdata_o (csr_rdata_csr_commit), + .dirty_fp_state_i (dirty_fp_state), + .csr_write_fflags_i (csr_write_fflags_commit_cs), + .dirty_v_state_i (dirty_v_state), + .pc_i (pc_commit), + .csr_exception_o (csr_exception_csr_commit), + .epc_o (epc_commit_pcgen), + .eret_o (eret), + .trap_vector_base_o (trap_vector_base_commit_pcgen), + .priv_lvl_o (priv_lvl), + .mbe_o (mbe), + .v_o (v), + .acc_fflags_ex_i (acc_resp_fflags), + .acc_fflags_ex_valid_i (acc_resp_fflags_valid), + .fs_o (fs), + .vfs_o (vfs), + .fflags_o (fflags_csr_commit), + .frm_o (frm_csr_id_issue_ex), + .fprec_o (fprec_csr_ex), + .vs_o (vs), + .irq_ctrl_o (irq_ctrl_csr_id), + .en_translation_o (enable_translation_csr_ex), + .en_g_translation_o (enable_g_translation_csr_ex), + .en_ld_st_translation_o (en_ld_st_translation_csr_ex), + .en_ld_st_g_translation_o (en_ld_st_g_translation_csr_ex), + .ld_st_priv_lvl_o (ld_st_priv_lvl_csr_ex), + .ld_st_v_o (ld_st_v_csr_ex), + .csr_hs_ld_st_inst_i (csr_hs_ld_st_inst_ex), + .sum_o (sum_csr_ex), + .vs_sum_o (vs_sum_csr_ex), + .mxr_o (mxr_csr_ex), + .vmxr_o (vmxr_csr_ex), + .satp_ppn_o (satp_ppn_csr_ex), + .asid_o (asid_csr_ex), + .vsatp_ppn_o (vsatp_ppn_csr_ex), + .vs_asid_o (vs_asid_csr_ex), + .hgatp_ppn_o (hgatp_ppn_csr_ex), + .vmid_o (vmid_csr_ex), .irq_i, .ipi_i, .debug_req_i, - .set_debug_pc_o (set_debug_pc), - .tvm_o (tvm_csr_id), - .tw_o (tw_csr_id), - .vtw_o (vtw_csr_id), - .tsr_o (tsr_csr_id), - .hu_o (hu), - .debug_mode_o (debug_mode), - .single_step_o (single_step_csr_commit), - .icache_en_o (icache_en_csr), - .dcache_en_o (dcache_en_csr_nbdcache), - .acc_cons_en_o (acc_cons_en_csr), - .perf_addr_o (addr_csr_perf), - .perf_data_o (data_csr_perf), - .perf_data_i (data_perf_csr), - .perf_we_o (we_csr_perf), - .pmpcfg_o (pmpcfg), - .pmpaddr_o (pmpaddr), - .mcountinhibit_o (mcountinhibit_csr_perf), - .jvt_o (jvt), + .set_debug_pc_o (set_debug_pc), + .tvm_o (tvm_csr_id), + .tw_o (tw_csr_id), + .vtw_o (vtw_csr_id), + .tsr_o (tsr_csr_id), + .hu_o (hu), + .debug_mode_o (debug_mode), + .single_step_o (single_step_csr_commit), + .icache_en_o (icache_en_csr), + .dcache_en_o (dcache_en_csr), + .dcache_scrub_en_o (dcache_scrub_en_csr), + .dcache_scrub_period_o (dcache_scrub_period_csr), + .dcache_scrub_cycle_i (dcache_scrub_cycle_csr), + .dcache_dat_cor_err_i (dcache_dat_cor_err_csr), + .dcache_dat_unc_err_i (dcache_dat_unc_err_csr), + .dcache_dir_cor_err_i (dcache_dir_cor_err_csr), + .dcache_dir_unc_err_i (dcache_dir_unc_err_csr), + .acc_cons_en_o (acc_cons_en_csr), + .perf_addr_o (addr_csr_perf), + .perf_data_o (data_csr_perf), + .perf_data_i (data_perf_csr), + .perf_we_o (we_csr_perf), + .pmpcfg_o (pmpcfg), + .pmpaddr_o (pmpaddr), + .mcountinhibit_o (mcountinhibit_csr_perf), + .mcbie_o (mcbie), + .scbie_o (scbie), + .hcbie_o (hcbie), + .mcbcfe_o (mcbcfe), + .scbcfe_o (scbcfe), + .hcbcfe_o (hcbcfe), + .jvt_o (jvt), //RVFI - .rvfi_csr_o (rvfi_csr) + .rvfi_csr_o (rvfi_csr), + // Trigger Signals + .sdtrig_commit_std_exception_valid_o(sdtrig_commit_std_exception_valid), + //Decoder/FE <-> Trigger Module + .fetch_sdtrig_pc_i (fetch_sdtrig_pc), + .fetch_sdtrig_instr_i (fetch_sdtrig_instr), + .sdtrig_decoder_action_o (sdtrig_decoder_action), + //Load/Store Unit <-> Trigger Module + .sdtrig_lsu_inputs_vaddr_i (sdtrig_lsu_inputs_operand_a), + .sdtrig_lsu_inputs_data_i (sdtrig_lsu_inputs_operand_c), + .sdtrig_lsu_inputs_fu_i (sdtrig_lsu_inputs_we), + .sdtrig_lsu_inputs_op_i (sdtrig_lsu_inputs_op), + .sdtrig_lsu_inputs_valid_i (sdtrig_lsu_inputs_valid), + .sdtrig_load_data_i (load_result_ex_id), + .sdtrig_load_valid_i (load_valid_ex_id), + .sdtrig_load_stall_o (sdtrig_load_stall), + .sdtrig_load_cancel_o (sdtrig_load_cancel), + .sdtrig_load_action_o (sdtrig_load_action), + .sdtrig_store_stall_o (sdtrig_store_stall), + .sdtrig_store_action_o (sdtrig_store_action), + //Commit <- Trigger module + .sdtrig_commit_icount_valid_o (sdtrig_commit_icount_valid), + .sdtrig_commit_action_o (sdtrig_commit_action), + .sdtrig_commit_icount_nr_instr_o (sdtrig_commit_icount_nr_instr) ); // ------------------------ @@ -1258,6 +1409,7 @@ module cva6 .flush_tlb_gvma_o (flush_tlb_gvma_ctrl_ex), .halt_csr_i (halt_csr_ctrl), .halt_acc_i (halt_acc_ctrl), + .halt_frontend_o (halt_frontend), .halt_o (halt_ctrl), // control ports .eret_i (eret), @@ -1279,13 +1431,13 @@ module cva6 // ------------------- // Acc dispatcher and store buffer share a dcache request port. - // Store buffer always has priority access over acc dipsatcher. + // Store buffer always has priority access over acc dispatcher. dcache_req_i_t [NumPorts-1:0] dcache_req_to_cache; dcache_req_o_t [NumPorts-1:0] dcache_req_from_cache; // D$ request - // Since ZCMT is only enable for embdeed class so MMU should be disable. - // Cache port 0 is being ultilize in implicit read access in ZCMT extension. + // Since ZCMT is only enabled for embedded class so MMU should be disabled. + // Cache port 0 is being utilized in implicit read access in ZCMT extension. if (CVA6Cfg.RVZCMT & ~(CVA6Cfg.MmuPresent)) begin assign dcache_req_to_cache[0] = dcache_req_ports_id_cache; end else begin @@ -1297,8 +1449,8 @@ module cva6 dcache_req_ports_acc_cache[1]; // D$ response - // Since ZCMT is only enable for embdeed class so MMU should be disable. - // Cache port 0 is being ultilized in implicit read access in ZCMT extension. + // Since ZCMT is only enabled for embedded class so MMU should be disabled. + // Cache port 0 is being utilized in implicit read access in ZCMT extension. if (CVA6Cfg.RVZCMT & ~(CVA6Cfg.MmuPresent)) begin assign dcache_req_ports_cache_id = dcache_req_from_cache[0]; assign dcache_req_ports_cache_ex[0] = '0; @@ -1345,12 +1497,13 @@ module cva6 .icache_dreq_i (icache_dreq_if_cache), .icache_dreq_o (icache_dreq_cache_if), // D$ - .dcache_enable_i (dcache_en_csr_nbdcache), + .dcache_enable_i (dcache_en_csr), .dcache_flush_i (dcache_flush_ctrl_cache), .dcache_flush_ack_o(dcache_flush_ack_cache_ctrl), // to commit stage .dcache_amo_req_i (amo_req), .dcache_amo_resp_o (amo_resp), + .mbe_i (mbe), // from PTW, Load Unit and Store Unit .dcache_miss_o (dcache_miss_cache_perf), .miss_vld_bits_o (miss_vld_bits), @@ -1366,10 +1519,16 @@ module cva6 .inval_valid_i (inval_valid), .inval_ready_o (inval_ready) ); - end else if (CVA6Cfg.DCacheType inside { - config_pkg::HPDCACHE_WT, - config_pkg::HPDCACHE_WB, - config_pkg::HPDCACHE_WT_WB}) + assign dcache_scrub_cycle_csr = 1'b0; + assign dcache_dat_cor_err_csr = 1'b0; + assign dcache_dat_unc_err_csr = 1'b0; + assign dcache_dir_cor_err_csr = 1'b0; + assign dcache_dir_unc_err_csr = 1'b0; + end else if ( + CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT || + CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WB || + CVA6Cfg.DCacheType == config_pkg::HPDCACHE_WT_WB + ) begin : gen_cache_hpd cva6_hpdcache_subsystem #( .CVA6Cfg (CVA6Cfg), @@ -1388,9 +1547,7 @@ module cva6 .axi_b_chan_t (b_chan_t), .axi_r_chan_t (r_chan_t), .noc_req_t (noc_req_t), - .noc_resp_t(noc_resp_t), - .cmo_req_t (logic /*FIXME*/), - .cmo_rsp_t (logic /*FIXME*/) + .noc_resp_t(noc_resp_t) ) i_cache_subsystem ( .clk_i (clk_i), .rst_ni(rst_ni), @@ -1403,17 +1560,21 @@ module cva6 .icache_dreq_i (icache_dreq_if_cache), .icache_dreq_o (icache_dreq_cache_if), - .dcache_enable_i (dcache_en_csr_nbdcache), - .dcache_flush_i (dcache_flush_ctrl_cache), - .dcache_flush_ack_o(dcache_flush_ack_cache_ctrl), - .dcache_miss_o (dcache_miss_cache_perf), + .dcache_enable_i (dcache_en_csr), + .dcache_flush_i (dcache_flush_ctrl_cache), + .dcache_flush_ack_o (dcache_flush_ack_cache_ctrl), + .dcache_miss_o (dcache_miss_cache_perf), + .dcache_scrub_enable_i(dcache_scrub_en_csr), + .dcache_scrub_period_i(dcache_scrub_period_csr), + .dcache_scrub_cycle_o (dcache_scrub_cycle_csr), + .dcache_dat_cor_err_o (dcache_dat_cor_err_csr), + .dcache_dat_unc_err_o (dcache_dat_unc_err_csr), + .dcache_dir_cor_err_o (dcache_dir_cor_err_csr), + .dcache_dir_unc_err_o (dcache_dir_unc_err_csr), .dcache_amo_req_i (amo_req), .dcache_amo_resp_o(amo_resp), - .dcache_cmo_req_i ('0 /*FIXME*/), - .dcache_cmo_resp_o( /*FIXME*/), - .dcache_req_ports_i(dcache_req_to_cache), .dcache_req_ports_o(dcache_req_from_cache), @@ -1434,7 +1595,8 @@ module cva6 .noc_req_o (noc_req_o), .noc_resp_i(noc_resp_i) ); - assign inval_ready = 1'b1; + assign inval_ready = 1'b1; + assign miss_vld_bits = '0; end else begin : gen_cache_wb std_cache_subsystem #( // note: this only works with one cacheable region @@ -1469,7 +1631,7 @@ module cva6 .icache_dreq_i (icache_dreq_if_cache), .icache_dreq_o (icache_dreq_cache_if), // D$ - .dcache_enable_i (dcache_en_csr_nbdcache), + .dcache_enable_i (dcache_en_csr), .dcache_flush_i (dcache_flush_ctrl_cache), .dcache_flush_ack_o(dcache_flush_ack_cache_ctrl), // to commit stage @@ -1486,7 +1648,13 @@ module cva6 .axi_resp_i (noc_resp_i) ); assign dcache_commit_wbuffer_not_ni = 1'b1; + assign dcache_scrub_cycle_csr = 1'b0; + assign dcache_dat_cor_err_csr = 1'b0; + assign dcache_dat_unc_err_csr = 1'b0; + assign dcache_dir_cor_err_csr = 1'b0; + assign dcache_dir_unc_err_csr = 1'b0; assign inval_ready = 1'b1; + assign miss_vld_bits = '0; end // ---------------- @@ -1504,7 +1672,11 @@ module cva6 .acc_cfg_t (acc_cfg_t), .AccCfg (AccCfg), .acc_req_t (cvxif_req_t), - .acc_resp_t (cvxif_resp_t) + .acc_resp_t (cvxif_resp_t), + .accelerator_req_t (accelerator_req_t), + .accelerator_resp_t(accelerator_resp_t), + .acc_mmu_req_t (acc_mmu_req_t), + .acc_mmu_resp_t (acc_mmu_resp_t) ) i_acc_dispatcher ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -1520,6 +1692,7 @@ module cva6 .pmpcfg_i (pmpcfg), .pmpaddr_i (pmpaddr), .fcsr_frm_i (frm_csr_id_issue_ex), + .acc_mmu_en_i (enable_translation_csr_ex), .dirty_v_state_o (dirty_v_state), .issue_instr_i (issue_instr_id_acc), .issue_instr_hs_i (issue_instr_hs_id_acc), @@ -1536,6 +1709,8 @@ module cva6 .acc_stall_st_pending_o(stall_st_pending_ex), .acc_no_st_pending_i (no_st_pending_commit), .dcache_req_ports_i (dcache_req_ports_ex_cache), + .acc_mmu_req_o (acc_mmu_req), + .acc_mmu_resp_i (acc_mmu_resp), .ctrl_halt_o (halt_acc_ctrl), .csr_addr_i (csr_addr_ex_csr), .acc_dcache_req_ports_o(dcache_req_ports_acc_cache), @@ -1565,6 +1740,9 @@ module cva6 // D$ connection is unused assign dcache_req_ports_acc_cache = '0; + // MMU access is unused + assign acc_mmu_req = '0; + // No invalidation interface assign inval_valid = '0; assign inval_addr = '0; @@ -1594,7 +1772,7 @@ module cva6 logic [CVA6Cfg.NrCommitPorts-1:0] pc_pop, pc_empty; for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_pc_fifo - fifo_v3 #( + cva6_fifo_v3 #( .DATA_WIDTH(64), .DEPTH(PC_QUEUE_DEPTH), .FPGA_EN(CVA6Cfg.FpgaEn) @@ -1632,6 +1810,18 @@ module cva6 `endif // PITON_ARIANE `ifndef VERILATOR + + logic [ 31:0] fetch_instructions [CVA6Cfg.NrIssuePorts-1:0]; + logic [CVA6Cfg.NrCommitPorts-1:0][63:0] wdata_commit_id_padded; + + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; ++i) begin + assign fetch_instructions[i] = fetch_entry_if_id[i].instruction; + end + + for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; ++i) begin + assign wdata_commit_id_padded[i] = {{(64 - CVA6Cfg.XLEN) {1'b0}}, wdata_commit_id[i]}; + end + instr_tracer #( .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), @@ -1645,17 +1835,18 @@ module cva6 .rstn(rst_ni), .flush_unissued(flush_unissued_instr_ctrl_id), .flush_all(flush_ctrl_ex), - .instruction(id_stage_i.fetch_entry_i[0].instruction), - .fetch_valid(id_stage_i.fetch_entry_valid_i[0]), - .fetch_ack(id_stage_i.fetch_entry_ready_o[0]), + .instruction(fetch_instructions), + .fetch_valid(id_stage_i.fetch_entry_valid_i), + .fetch_ack(id_stage_i.fetch_entry_ready_o), .issue_ack(issue_stage_i.i_scoreboard.issue_ack_i), .issue_sbe(issue_stage_i.i_scoreboard.issue_instr_o), .waddr(waddr_commit_id), - .wdata(wdata_commit_id), + .wdata(wdata_commit_id_padded), .we_gpr(we_gpr_commit_id), .we_fpr(we_fpr_commit_id), .commit_instr(commit_instr_id_commit), - .commit_ack(commit_ack), + .commit_ack(commit_ack_commit_id), + .commit_drop(commit_drop_id_commit), .st_valid(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i), .st_paddr(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i), .ld_valid(ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid), @@ -1737,6 +1928,7 @@ module cva6 .exception_t (exception_t), .scoreboard_entry_t (scoreboard_entry_t), .lsu_ctrl_t (lsu_ctrl_t), + .bp_resolve_t (bp_resolve_t), .rvfi_probes_instr_t(rvfi_probes_instr_t), .rvfi_probes_csr_t (rvfi_probes_csr_t), .rvfi_probes_t (rvfi_probes_t) @@ -1772,7 +1964,8 @@ module cva6 .csr_i(rvfi_csr), .irq_i(irq_i), - + .resolved_branch_i(resolved_branch), + .flu_trans_id_ex_id_i(flu_trans_id_ex_id), .rvfi_probes_o(rvfi_probes_o) ); diff --git a/core/cva6_fifo_v3.sv b/core/cva6_fifo_v3.sv index d1faa01b3a2..631ce226513 100644 --- a/core/cva6_fifo_v3.sv +++ b/core/cva6_fifo_v3.sv @@ -1,5 +1,5 @@ // Copyright 2018 ETH Zurich and University of Bologna. -// Copyright 2024 - PlanV Technologies for additionnal contribution. +// Copyright 2024 - PlanV Technologies for additional contribution. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at diff --git a/core/cva6_mmu/cva6_mmu.sv b/core/cva6_mmu/cva6_mmu.sv index 53822799384..ef7099a1f5d 100644 --- a/core/cva6_mmu/cva6_mmu.sv +++ b/core/cva6_mmu/cva6_mmu.sv @@ -18,7 +18,7 @@ // Description: Memory Management Unit for CVA6, contains TLB and // address translation unit. SV32 SV39 and SV39x4 as defined in RISC-V // privilege specification 1.11-WIP. -// This module is an merge of the MMU Sv39 developed +// This module is a merge of the MMU Sv39 developed // by Florian Zaruba, the MMU Sv32 developed by Sebastien Jacq and the MMU Sv39x4 developed by Bruno Sá. @@ -59,9 +59,14 @@ module cva6_mmu // Cycle 0 output logic lsu_dtlb_hit_o, // sent in same cycle as the request if translation hits in DTLB output logic [CVA6Cfg.PPNW-1:0] lsu_dtlb_ppn_o, // ppn (send same cycle as hit) - // Cycle 1 + // Cycle 1 response output logic lsu_valid_o, // translation is valid output logic [CVA6Cfg.PLEN-1:0] lsu_paddr_o, // translated address + // Metadata for the same response transaction as lsu_valid_o, lsu_paddr_o, + // and lsu_exception_o. + output logic [CVA6Cfg.VLEN-1:0] lsu_vaddr_o, + output logic lsu_is_store_o, + output logic lsu_hlvx_inst_o, output exception_t lsu_exception_o, // address translation threw an exception // General control signals input riscv::priv_lvl_t priv_lvl_i, @@ -72,6 +77,7 @@ module cva6_mmu input logic vs_sum_i, input logic mxr_i, input logic vmxr_i, + input logic mbe_i, input logic hlvx_inst_i, input logic hs_ld_st_inst_i, // input logic flag_mprv_i, @@ -91,6 +97,9 @@ module cva6_mmu input logic flush_tlb_vvma_i, input logic flush_tlb_gvma_i, + // Shared TLB is busy processing a multi-cycle flush + output logic shared_tlb_flush_busy_o, + // Performance counters output logic itlb_miss_o, output logic dtlb_miss_o, @@ -100,13 +109,14 @@ module cva6_mmu // PMP - input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, - input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i ); // memory management, pte for cva6 localparam type pte_cva6_t = struct packed { - logic [9:0] reserved; + logic n; + logic [8:0] reserved; logic [CVA6Cfg.PPNW-1:0] ppn; // PPN length for logic [1:0] rsw; logic d; @@ -120,14 +130,15 @@ module cva6_mmu }; localparam type tlb_update_cva6_t = struct packed { - logic valid; + logic valid; + logic is_napot_64k; // Svnapot: Flag indicating a 64KiB NAPOT page logic [CVA6Cfg.PtLevels-2:0][HYP_EXT:0] is_page; - logic [CVA6Cfg.VpnLen-1:0] vpn; - logic [CVA6Cfg.ASID_WIDTH-1:0] asid; - logic [CVA6Cfg.VMID_WIDTH-1:0] vmid; - logic [HYP_EXT*2:0] v_st_enbl; // v_i,g-stage enabled, s-stage enabled - pte_cva6_t content; - pte_cva6_t g_content; + logic [CVA6Cfg.VpnLen-1:0] vpn; + logic [CVA6Cfg.ASID_WIDTH-1:0] asid; + logic [CVA6Cfg.VMID_WIDTH-1:0] vmid; + logic [HYP_EXT*2:0] v_st_enbl; // v_i,g-stage enabled, s-stage enabled + pte_cva6_t content; + pte_cva6_t g_content; }; logic iaccess_err; // insufficient privilege to access this instruction page @@ -143,6 +154,7 @@ module cva6_mmu logic ptw_access_exception; // PTW threw an access exception (PMPs) logic [CVA6Cfg.PLEN-1:0] ptw_bad_paddr; // PTW page fault bad physical addr logic [CVA6Cfg.GPLEN-1:0] ptw_bad_gpaddr; // PTW guest page fault bad guest physical addr + logic [CVA6Cfg.PPNW-1:0] final_fetch_ppn; logic [CVA6Cfg.VLEN-1:0] update_vaddr, shared_tlb_vaddr; @@ -170,7 +182,7 @@ module cva6_mmu // Assignments assign itlb_lu_access = icache_areq_i.fetch_req; - assign dtlb_lu_access = lsu_req_i; + assign dtlb_lu_access = lsu_req_i & !misaligned_ex_i.valid; assign itlb_lu_asid = v_i ? vs_asid_i : asid_i; assign dtlb_lu_asid = (ld_st_v_i || flush_tlb_vvma_i) ? vs_asid_i : asid_i; @@ -223,7 +235,7 @@ module cva6_mmu .v_i (ld_st_v_i), .update_i (update_dtlb), .lu_access_i (dtlb_lu_access), - .lu_asid_i (itlb_lu_asid), + .lu_asid_i (dtlb_lu_asid), .lu_vmid_i (vmid_i), .lu_vaddr_i (lsu_vaddr_i), .lu_gpaddr_o (dtlb_gpaddr), @@ -270,10 +282,14 @@ module cva6_mmu .dtlb_hit_i (dtlb_lu_hit), .dtlb_vaddr_i (lsu_vaddr_i), + .asid_to_be_flushed_i(asid_to_be_flushed_i), + .vaddr_to_be_flushed_i(vaddr_to_be_flushed_i), + .vmid_to_be_flushed_i(vmid_to_be_flushed_i), + .gpaddr_to_be_flushed_i(gpaddr_to_be_flushed_i), // to TLBs, update logic .itlb_update_o(update_itlb), .dtlb_update_o(update_dtlb), - + .flush_busy_o(shared_tlb_flush_busy_o), // Performance counters .itlb_miss_o(itlb_miss_o), .dtlb_miss_o(dtlb_miss_o), @@ -341,7 +357,7 @@ module cva6_mmu .hgatp_ppn_i, .mxr_i, .vmxr_i, - + .mbe_i(mbe_i), // Performance counters .shared_tlb_miss_o(shared_tlb_miss), //open for now @@ -356,12 +372,15 @@ module cva6_mmu // Instruction Interface //----------------------- localparam int PPNWMin = (CVA6Cfg.PPNW - 1 > 29) ? 29 : CVA6Cfg.PPNW - 1; + // Width of the mid-level (2M) superpage PPN substitution for PtLevels == 3. + // Evaluates to 9 for Sv39 and (unused but elaboration-legal) 1 for Sv32. + localparam int unsigned MegaPageSubstWidth = PPNWMin - (CVA6Cfg.VpnLen / CVA6Cfg.PtLevels) - 8 - CVA6Cfg.PtLevels; // The instruction interface is a simple request response interface always_comb begin : instr_interface // MMU disabled: just pass through icache_areq_o.fetch_valid = icache_areq_i.fetch_req; - icache_areq_o.fetch_paddr = CVA6Cfg.PLEN'(icache_areq_i.fetch_vaddr[((CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? CVA6Cfg.VLEN -1: CVA6Cfg.PLEN -1 ):0]); + icache_areq_o.fetch_paddr = CVA6Cfg.PLEN'(icache_areq_i.fetch_vaddr[((CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? CVA6Cfg.VLEN -1: CVA6Cfg.PLEN -1 ):0]); // two potential exception sources: // 1. HPTW threw an exception -> signal with a page fault exception // 2. We got an access error because of insufficient permissions -> throw an access exception @@ -378,9 +397,12 @@ module cva6_mmu // AXI decode error), or when PTW performs walk due to ITLB miss and raises // an error. if ((enable_translation_i || enable_g_translation_i)) begin - // we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal - if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)) begin - + // If second-level address translation is enabled: + // - in VS stage, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal + // - in pure G stage (SV39x4 mode), [CVA6Cfg.VLEN-1:CVA6Cfg.GPLEN] must be zero. + // - in pure G stage (SV32x4 mode), no check is needed. + if ((enable_translation_i && (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0))) + || (enable_g_translation_i && !enable_translation_i && CVA6Cfg.IS_XLEN64 && (|icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.GPLEN] != 1'b0))) begin icache_areq_o.fetch_exception.cause = riscv::INSTR_PAGE_FAULT; icache_areq_o.fetch_exception.valid = 1'b1; if (CVA6Cfg.TvalEn) @@ -394,13 +416,13 @@ module cva6_mmu icache_areq_o.fetch_valid = 1'b0; - icache_areq_o.fetch_paddr = { - (enable_g_translation_i && CVA6Cfg.RVH) ? itlb_g_content.ppn : itlb_content.ppn, - icache_areq_i.fetch_vaddr[11:0] - }; + final_fetch_ppn = (enable_g_translation_i && CVA6Cfg.RVH)? itlb_g_content.ppn : itlb_content.ppn; + icache_areq_o.fetch_paddr = {final_fetch_ppn, icache_areq_i.fetch_vaddr[11:0]}; if (CVA6Cfg.PtLevels == 3 && itlb_is_page[CVA6Cfg.PtLevels-2]) begin + // strange 9+PtLevels to avoid CI errors on (purely syntactic) checks on Sv32, where + // `PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)` equals `11` and would lead to `icache_areq_i.fetch_vaddr[11:12]` icache_areq_o.fetch_paddr[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels] = icache_areq_i.fetch_vaddr[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels]; end @@ -453,7 +475,7 @@ module cva6_mmu if (CVA6Cfg.TvalEn) icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(update_vaddr); if (CVA6Cfg.RVH) begin icache_areq_o.fetch_exception.tval2 = ptw_bad_gpaddr[CVA6Cfg.GPLEN-1:0]; - icache_areq_o.fetch_exception.tinst=(ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0); + icache_areq_o.fetch_exception.tinst = (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0); icache_areq_o.fetch_exception.gva = v_i; end end else begin @@ -469,7 +491,7 @@ module cva6_mmu end else begin icache_areq_o.fetch_exception.cause = riscv::INSTR_ACCESS_FAULT; icache_areq_o.fetch_exception.valid = 1'b1; - if (CVA6Cfg.TvalEn) //To confirm this is the right TVAL + if (CVA6Cfg.TvalEn) // To confirm this is the right TVAL icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(update_vaddr); if (CVA6Cfg.RVH) begin icache_areq_o.fetch_exception.tval2 = '0; @@ -489,12 +511,20 @@ module cva6_mmu logic [CVA6Cfg.GPLEN-1:0] lsu_gpaddr_n, lsu_gpaddr_q; logic [31:0] lsu_tinst_n, lsu_tinst_q; logic hs_ld_st_inst_n, hs_ld_st_inst_q; + logic hlvx_inst_n, hlvx_inst_q; + logic g_load_exec_as_read_ok; + logic g_load_access_ok; pte_cva6_t dtlb_pte_n, dtlb_pte_q; pte_cva6_t dtlb_gpte_n, dtlb_gpte_q; logic lsu_req_n, lsu_req_q; logic lsu_is_store_n, lsu_is_store_q; logic dtlb_hit_n, dtlb_hit_q; logic [CVA6Cfg.PtLevels-2:0] dtlb_is_page_n, dtlb_is_page_q; + exception_t misaligned_ex_n, misaligned_ex_q; + + assign lsu_vaddr_o = lsu_vaddr_q; + assign lsu_is_store_o = lsu_is_store_q; + assign lsu_hlvx_inst_o = CVA6Cfg.RVH ? hlvx_inst_q : 1'b0; // check if we need to do translation or if we are always ready (e.g.: we are not translating anything) assign lsu_dtlb_hit_o = (en_ld_st_translation_i || en_ld_st_g_translation_i) ? dtlb_lu_hit : 1'b1; @@ -509,13 +539,17 @@ module cva6_mmu dtlb_hit_n = dtlb_lu_hit; lsu_is_store_n = lsu_is_store_i; dtlb_is_page_n = dtlb_is_page; + misaligned_ex_n = misaligned_ex_i; lsu_valid_o = lsu_req_q; - lsu_exception_o = misaligned_ex_i; + lsu_exception_o = misaligned_ex_q; + + // mute misaligned exceptions if there is no request otherwise they will throw accidental exceptions + misaligned_ex_n.valid = misaligned_ex_i.valid & lsu_req_i; // we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal to bit [CVA6Cfg.SV] - canonical_addr_check = (lsu_req_i && en_ld_st_translation_i && - !((&lsu_vaddr_i[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|lsu_vaddr_i[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)); + canonical_addr_check = (lsu_req_q && en_ld_st_translation_i && + !((&lsu_vaddr_q[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|lsu_vaddr_q[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)); // Check if the User flag is set, then we may only access it in supervisor mode // if SUM is enabled @@ -526,9 +560,21 @@ module cva6_mmu if (CVA6Cfg.RVH) begin lsu_tinst_n = lsu_tinst_i; hs_ld_st_inst_n = hs_ld_st_inst_i; - lsu_gpaddr_n[(CVA6Cfg.XLEN == 32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0] = dtlb_gpaddr[(CVA6Cfg.XLEN == 32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0]; + hlvx_inst_n = hlvx_inst_i; + lsu_gpaddr_n[(CVA6Cfg.IS_XLEN32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0] = dtlb_gpaddr[(CVA6Cfg.IS_XLEN32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0]; csr_hs_ld_st_inst_o = hs_ld_st_inst_i || hs_ld_st_inst_q; - d_g_st_access_err = en_ld_st_g_translation_i && !dtlb_gpte_q.u; + // The PTW path has its own permission checks while populating translation + // state. Once a G-stage translation is cached and a later LSU access hits in + // the DTLB, the hit path still has to re-check permissions against the + // current access type. In particular, a prior HLVX hit must not cause a + // later plain HLV load to inherit execute-only permission. + g_load_exec_as_read_ok = dtlb_gpte_q.x && (mxr_i || hlvx_inst_q); + g_load_access_ok = dtlb_gpte_q.r || g_load_exec_as_read_ok; + d_g_st_access_err = en_ld_st_g_translation_i && ( + !dtlb_gpte_q.u || + !dtlb_gpte_q.a || + (!lsu_is_store_q && !g_load_access_ok) + ); dtlb_gpte_n = dtlb_g_content; end @@ -536,25 +582,32 @@ module cva6_mmu lsu_dtlb_ppn_o = (CVA6Cfg.PPNW)'(lsu_vaddr_n[((CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? CVA6Cfg.VLEN -1: CVA6Cfg.PLEN -1 ):12]); // translation is enabled and no misaligned exception occurred - if ((en_ld_st_translation_i || en_ld_st_g_translation_i) && !misaligned_ex_i.valid) begin + if ((en_ld_st_translation_i || en_ld_st_g_translation_i) && !misaligned_ex_q.valid) begin lsu_valid_o = 1'b0; - lsu_dtlb_ppn_o = (en_ld_st_g_translation_i && CVA6Cfg.RVH)? dtlb_g_content.ppn :dtlb_content.ppn; + lsu_dtlb_ppn_o = (en_ld_st_g_translation_i && CVA6Cfg.RVH) ? dtlb_g_content.ppn : dtlb_content.ppn; lsu_paddr_o = { (en_ld_st_g_translation_i && CVA6Cfg.RVH) ? dtlb_gpte_q.ppn : dtlb_pte_q.ppn, lsu_vaddr_q[11:0] }; if (CVA6Cfg.PtLevels == 3 && dtlb_is_page_q[CVA6Cfg.PtLevels-2]) begin + // Strange 9+PtLevels to avoid CI errors on (purely syntactic) checks on Sv32, where + // `PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)` equals `11` and would lead to `lsu_paddr_o[11:12]` lsu_paddr_o[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels] = lsu_vaddr_q[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels]; - lsu_dtlb_ppn_o[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels] = lsu_vaddr_n[PPNWMin-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):9+CVA6Cfg.PtLevels]; + end + if (CVA6Cfg.PtLevels == 3 && dtlb_is_page_n[CVA6Cfg.PtLevels-2]) begin + lsu_dtlb_ppn_o[0+:MegaPageSubstWidth] = lsu_vaddr_n[(9+CVA6Cfg.PtLevels)+:MegaPageSubstWidth]; end + if (dtlb_is_page_q[0]) begin - lsu_dtlb_ppn_o[PPNWMin:12] = lsu_vaddr_n[PPNWMin:12]; lsu_paddr_o[PPNWMin:12] = lsu_vaddr_q[PPNWMin:12]; end + if (dtlb_is_page_n[0]) begin + lsu_dtlb_ppn_o[PPNWMin-12:0] = lsu_vaddr_n[PPNWMin:12]; + end // --------- @@ -579,7 +632,7 @@ module cva6_mmu {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q }; if (CVA6Cfg.RVH) begin - lsu_exception_o.tval2= CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]); + lsu_exception_o.tval2 = CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.IS_XLEN32 ? CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]); lsu_exception_o.tinst = '0; lsu_exception_o.gva = ld_st_v_i; end @@ -606,7 +659,7 @@ module cva6_mmu {CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q }; if (CVA6Cfg.RVH) begin - lsu_exception_o.tval2= CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]); + lsu_exception_o.tval2 = CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.IS_XLEN32 ? CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]); lsu_exception_o.tinst = '0; lsu_exception_o.gva = ld_st_v_i; end @@ -647,7 +700,7 @@ module cva6_mmu }; if (CVA6Cfg.RVH) begin lsu_exception_o.tval2 = ptw_bad_gpaddr[CVA6Cfg.GPLEN-1:0]; - lsu_exception_o.tinst= (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0); + lsu_exception_o.tinst = (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0); lsu_exception_o.gva = ld_st_v_i; end end else begin @@ -673,7 +726,7 @@ module cva6_mmu }; if (CVA6Cfg.RVH) begin lsu_exception_o.tval2 = ptw_bad_gpaddr[CVA6Cfg.GPLEN-1:0]; - lsu_exception_o.tinst= (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0); + lsu_exception_o.tinst = (ptw_err_at_g_int_st ? (CVA6Cfg.IS_XLEN64 ? riscv::READ_64_PSEUDOINSTRUCTION : riscv::READ_32_PSEUDOINSTRUCTION) : '0); lsu_exception_o.gva = ld_st_v_i; end end else begin @@ -736,17 +789,21 @@ module cva6_mmu dtlb_is_page_q <= '0; lsu_tinst_q <= '0; hs_ld_st_inst_q <= '0; + hlvx_inst_q <= '0; + misaligned_ex_q <= '0; end else begin - lsu_vaddr_q <= lsu_vaddr_n; - lsu_req_q <= lsu_req_n; - dtlb_pte_q <= dtlb_pte_n; - dtlb_hit_q <= dtlb_hit_n; - lsu_is_store_q <= lsu_is_store_n; - dtlb_is_page_q <= dtlb_is_page_n; + lsu_vaddr_q <= lsu_vaddr_n; + lsu_req_q <= lsu_req_n; + dtlb_pte_q <= dtlb_pte_n; + dtlb_hit_q <= dtlb_hit_n; + lsu_is_store_q <= lsu_is_store_n; + dtlb_is_page_q <= dtlb_is_page_n; + misaligned_ex_q <= misaligned_ex_n; if (CVA6Cfg.RVH) begin lsu_tinst_q <= lsu_tinst_n; hs_ld_st_inst_q <= hs_ld_st_inst_n; + hlvx_inst_q <= hlvx_inst_n; dtlb_gpte_q <= dtlb_gpte_n; lsu_gpaddr_q <= lsu_gpaddr_n; end diff --git a/core/cva6_mmu/cva6_ptw.sv b/core/cva6_mmu/cva6_ptw.sv index a5fef76fcce..52a4ba5ec68 100644 --- a/core/cva6_mmu/cva6_ptw.sv +++ b/core/cva6_mmu/cva6_ptw.sv @@ -15,8 +15,8 @@ // Author: Angela Gonzalez, PlanV Technology // Date: 26/02/2024 // Description: Hardware-PTW (Page-Table-Walker) for CVA6 supporting sv32, sv39 and sv39x4. -// This module is an merge of the PTW Sv39 developed by Florian Zaruba, -// the PTW Sv32 developed by Sebastien Jacq and the PTW Sv39x4 by Bruno Sá. +// This module is a merge of the PTW Sv39 developed by Florian Zaruba, +// the PTW Sv32 developed by Sebastien Jacq and the PTW Sv39x4 by Bruno Sá. /* verilator lint_off WIDTH */ @@ -40,7 +40,7 @@ module cva6_ptw output logic ptw_error_o, // set when an error occurred output logic ptw_error_at_g_st_o, // set when an error occurred at the G-Stage output logic ptw_err_at_g_int_st_o, // set when an error occurred at the G-Stage during S-Stage translation - output logic ptw_access_exception_o, // set when an PMP access exception occured + output logic ptw_access_exception_o, // set when a PMP access exception occurred input logic enable_translation_i, // CSRs indicate to enable SV39 VS-Stage translation input logic enable_g_translation_i, // CSRs indicate to enable SV39 G-Stage translation input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores @@ -49,9 +49,9 @@ module cva6_ptw input logic ld_st_v_i, // load/store virtualization mode bit input logic hlvx_inst_i, // is a HLVX load/store instruction - input logic lsu_is_store_i, // this translation was triggered by a store + input logic lsu_is_store_i, // this translation was triggered by a store // PTW memory interface - input dcache_req_o_t req_port_i, + input dcache_req_o_t req_port_i, output dcache_req_i_t req_port_o, @@ -74,17 +74,18 @@ module cva6_ptw // from CSR file input logic [CVA6Cfg.PPNW-1:0] satp_ppn_i, // ppn from satp - input logic [CVA6Cfg.PPNW-1:0] vsatp_ppn_i, // ppn from satp + input logic [CVA6Cfg.PPNW-1:0] vsatp_ppn_i, // ppn from vsatp input logic [CVA6Cfg.PPNW-1:0] hgatp_ppn_i, // ppn from hgatp input logic mxr_i, input logic vmxr_i, + input logic mbe_i, // Performance counters output logic shared_tlb_miss_o, // PMP - input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, - input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, output logic [CVA6Cfg.PLEN-1:0] bad_paddr_o, output logic [CVA6Cfg.GPLEN-1:0] bad_gpaddr_o ); @@ -96,6 +97,10 @@ module cva6_ptw pte_cva6_t pte; // register to perform context switch between stages pte_cva6_t gpte_q, gpte_d; + + //Field for SVNAPOT + logic is_napot_64k; + assign pte = pte_cva6_t'(data_rdata_q); enum logic [2:0] { @@ -105,11 +110,13 @@ module cva6_ptw WAIT_RVALID, PROPAGATE_ERROR, PROPAGATE_ACCESS_ERROR, + KILL_REQ, LATENCY } state_q, state_d; logic [CVA6Cfg.PtLevels-2:0] misaligned_page; + logic shared_tlb_update_valid; logic [HYP_EXT:0][CVA6Cfg.PtLevels-2:0] ptw_lvl_n, ptw_lvl_q; // define 3 PTW stages to be used in sv39x4. sv32 and sv39 are always in S_STAGE @@ -128,6 +135,8 @@ module cva6_ptw logic global_mapping_q, global_mapping_n; // latched tag signal logic tag_valid_n, tag_valid_q; + // latched kill signal + logic kill_req_n, kill_req_q; // register the ASID logic [CVA6Cfg.ASID_WIDTH-1:0] tlb_update_asid_q, tlb_update_asid_n; // register the VMID @@ -150,12 +159,14 @@ module cva6_ptw // directly output the correct physical address assign req_port_o.address_index = ptw_pptr_q[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]; assign req_port_o.address_tag = ptw_pptr_q[CVA6Cfg.DCACHE_INDEX_WIDTH+CVA6Cfg.DCACHE_TAG_WIDTH-1:CVA6Cfg.DCACHE_INDEX_WIDTH]; - // we are never going to kill this request - assign req_port_o.kill_req = '0; // we are never going to write with the HPTW assign req_port_o.data_wdata = '0; // we only issue one single request at a time assign req_port_o.data_id = '0; + // user field not used + assign req_port_o.data_wuser = '0; + // not a write + assign req_port_o.cbo_op = ariane_pkg::CBO_NONE; // ----------- // TLB Update @@ -163,7 +174,6 @@ module cva6_ptw assign gpaddr_base = {pte.ppn[CVA6Cfg.GPPNW-1:0], vaddr_q[11:0]}; assign gpaddr[CVA6Cfg.PtLevels-1] = gpaddr_base; - assign shared_tlb_update_o.vpn = CVA6Cfg.VpnLen'(vaddr_q[CVA6Cfg.SV+HYP_EXT*2-1:12]); genvar z, w; generate @@ -174,16 +184,16 @@ module cva6_ptw // exception. assign misaligned_page[z] = (ptw_lvl_q[0] == (z)) && (pte.ppn[(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-1-z)-1:0] != '0); - //record the vaddr corresponding to each level + // record the vaddr corresponding to each level for (w = 0; w < HYP_EXT * 2 + 1; w++) begin - assign vaddr_lvl[w][z] = w==0 ? vaddr_q[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-2))] : - w==1 ? gptw_pptr_q[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-2))]: - gpaddr_q[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-2))]; + assign vaddr_lvl[w][z] = w==0 ? vaddr_q[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-2))]: + w==1 ? gptw_pptr_q[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-2))]: + gpaddr_q[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(CVA6Cfg.PtLevels-z-2))]; end if (CVA6Cfg.RVH) begin - assign gpaddr[z][CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):0]= (ptw_lvl_q[0] == z) ? vaddr_q[CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):0] : gpaddr_base[CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):0]; - assign gpaddr[z][CVA6Cfg.VpnLen:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)+1]= (ptw_lvl_q[0] == 0) ? vaddr_q[CVA6Cfg.VpnLen:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)+1] : gpaddr_base[CVA6Cfg.VpnLen:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)+1]; + assign gpaddr[z][CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):0] = (ptw_lvl_q[0] == z) ? vaddr_q[CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):0] : gpaddr_base[CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels):0]; + assign gpaddr[z][CVA6Cfg.VpnLen:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)+1] = (ptw_lvl_q[0] == 0) ? vaddr_q[CVA6Cfg.VpnLen:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)+1] : gpaddr_base[CVA6Cfg.VpnLen:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)+1]; assign gpaddr[z][CVA6Cfg.GPLEN-1:CVA6Cfg.VpnLen+1] = gpaddr_base[CVA6Cfg.GPLEN-1:CVA6Cfg.VpnLen+1]; end @@ -192,14 +202,20 @@ module cva6_ptw endgenerate always_comb begin : tlb_update + shared_tlb_update_o.valid = shared_tlb_update_valid; + shared_tlb_update_o.is_napot_64k = is_napot_64k; + // update the correct page table level for (int unsigned y = 0; y < HYP_EXT + 1; y++) begin for (int unsigned x = 0; x < CVA6Cfg.PtLevels - 1; x++) begin - if((enable_g_translation_i && enable_translation_i) || (en_ld_st_g_translation_i && en_ld_st_translation_i) && CVA6Cfg.RVH) begin - shared_tlb_update_o.is_page[x][y] = (ptw_lvl_q[y==HYP_EXT?0 : 1] == x); + if(((enable_g_translation_i && enable_translation_i) || (en_ld_st_g_translation_i && en_ld_st_translation_i)) && CVA6Cfg.RVH) begin + // VS + G-Translation + shared_tlb_update_o.is_page[x][y] = (ptw_lvl_q[y==1?0 : 1] == x); end else if (enable_translation_i || en_ld_st_translation_i || !CVA6Cfg.RVH) begin + // non-V, S-Translation shared_tlb_update_o.is_page[x][y] = y == 0 ? (ptw_lvl_q[0] == x) : 1'b0; end else begin + // G-Translation shared_tlb_update_o.is_page[x][y] = y != 0 ? (ptw_lvl_q[0] == x) : 1'b0; end end @@ -207,7 +223,7 @@ module cva6_ptw // set the global mapping bit if ((enable_g_translation_i || en_ld_st_g_translation_i) && CVA6Cfg.RVH) begin - shared_tlb_update_o.content = gpte_q | (global_mapping_q << 5); + shared_tlb_update_o.content = (gpte_q | (global_mapping_q << 5)); shared_tlb_update_o.g_content = pte; end else begin shared_tlb_update_o.content = (pte | (global_mapping_q << 5)); @@ -216,7 +232,8 @@ module cva6_ptw // output the correct ASIDs shared_tlb_update_o.asid = tlb_update_asid_q; - shared_tlb_update_o.vmid = tlb_update_vmid_q; + shared_tlb_update_o.vmid = CVA6Cfg.RVH ? tlb_update_vmid_q : '0; + shared_tlb_update_o.vpn = vaddr_q[12+CVA6Cfg.VpnLen-1:12]; bad_paddr_o = ptw_access_exception_o ? ptw_pptr_q : 'b0; if (CVA6Cfg.RVH) @@ -224,8 +241,10 @@ module cva6_ptw end assign req_port_o.tag_valid = tag_valid_q; + assign req_port_o.kill_req = (state_q == KILL_REQ); logic allow_access; + logic hlvx_eff; @@ -244,9 +263,14 @@ module cva6_ptw ); - assign req_port_o.data_be = CVA6Cfg.XLEN == 32 ? be_gen_32( + assign req_port_o.data_be = CVA6Cfg.IS_XLEN32 ? be_gen_32( req_port_o.address_index[1:0], req_port_o.data_size ) : '1; + // The HLVX permission rule (allow read via execute-only pages) applies only to the + // *original* access. For an implicit page-table read performed while G-stage-translating + // a VS-stage PTE address (G_INTERMED_STAGE), the access must be checked as an ordinary + // implicit load, so HLVX must not apply here. + assign hlvx_eff = hlvx_inst_i && !(CVA6Cfg.RVH && ptw_stage_q == G_INTERMED_STAGE); @@ -258,8 +282,8 @@ module cva6_ptw // PAGESIZE=2^12 and LEVELS=3.) // 2. Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE. (For // Sv32, PTESIZE=4.) - // 3. If pte.v = 0, or if pte.r = 0 and pte.w = 1, or if any bits or encodings - // that are reserved for future standard use are set within pte, stop and raise + // 3. If pte.v = 0, or if pte.r = 0 and pte.w = 1, or if any bits or encodings + // that are reserved for future standard use are set within pte, stop and raise // a page-fault exception corresponding to the original access type. // 4. Otherwise, the PTE is valid. If pte.r = 1 or pte.x = 1, go to step 5. // Otherwise, this PTE is a pointer to the next level of the page table. @@ -276,34 +300,36 @@ module cva6_ptw // - pa.ppn[LEVELS-1:i] = pte.ppn[LEVELS-1:i]. always_comb begin : ptw automatic logic [CVA6Cfg.PLEN-1:0] pptr; - // automatic logic [CVA6Cfg.GPLEN-1:0] gpaddr; // default assignments // PTW memory interface - tag_valid_n = 1'b0; - req_port_o.data_req = 1'b0; - req_port_o.data_size = 2'(CVA6Cfg.PtLevels); - req_port_o.data_we = 1'b0; - ptw_error_o = 1'b0; - ptw_error_at_g_st_o = 1'b0; - ptw_err_at_g_int_st_o = 1'b0; - ptw_access_exception_o = 1'b0; - shared_tlb_update_o.valid = 1'b0; - is_instr_ptw_n = is_instr_ptw_q; - ptw_lvl_n = ptw_lvl_q; - ptw_pptr_n = ptw_pptr_q; - state_d = state_q; - ptw_stage_d = ptw_stage_q; - global_mapping_n = global_mapping_q; + tag_valid_n = 1'b0; + kill_req_n = kill_req_q; + req_port_o.data_req = 1'b0; + req_port_o.data_size = 2'(CVA6Cfg.PtLevels); + req_port_o.data_we = 1'b0; + ptw_error_o = 1'b0; + ptw_error_at_g_st_o = 1'b0; + ptw_err_at_g_int_st_o = 1'b0; + ptw_access_exception_o = 1'b0; + shared_tlb_update_valid = 1'b0; + is_napot_64k = 1'b0; + is_instr_ptw_n = is_instr_ptw_q; + ptw_lvl_n = ptw_lvl_q; + ptw_pptr_n = ptw_pptr_q; + state_d = state_q; + gpte_d = '0; + ptw_stage_d = ptw_stage_q; + global_mapping_n = global_mapping_q; // input registers - tlb_update_asid_n = tlb_update_asid_q; - tlb_update_vmid_n = tlb_update_vmid_q; - vaddr_n = vaddr_q; - pptr = ptw_pptr_q; + tlb_update_asid_n = tlb_update_asid_q; + vaddr_n = vaddr_q; + pptr = ptw_pptr_q; if (CVA6Cfg.RVH) begin gpaddr_n = gpaddr_q; gptw_pptr_n = gptw_pptr_q; gpte_d = gpte_q; + tlb_update_vmid_n = tlb_update_vmid_q; end shared_tlb_miss_o = 1'b0; @@ -385,10 +411,17 @@ module cva6_ptw if (req_port_i.data_gnt) begin // send the tag valid signal one cycle later tag_valid_n = 1'b1; - state_d = PTE_LOOKUP; + // if the request has been flushed, kill it one cycle later + state_d = (kill_req_q || flush_i) ? KILL_REQ : PTE_LOOKUP; end end + KILL_REQ: begin + kill_req_n = 1'b0; + // even when killed, the request sends a response + state_d = WAIT_RVALID; + end + PTE_LOOKUP: begin // we wait for the valid signal if (data_rvalid_q) begin @@ -400,16 +433,26 @@ module cva6_ptw // Invalid PTE // ------------- // If pte.v = 0, or if pte.r = 0 and pte.w = 1, or if pte.reserved !=0 in sv39 and sv39x4, stop and raise a page-fault exception. - if (!pte.v || (!pte.r && pte.w) || (|pte.reserved && CVA6Cfg.XLEN == 64)) + if (!pte.v || (!pte.r && pte.w) || (|pte.reserved && CVA6Cfg.IS_XLEN64) || (!CVA6Cfg.SvnapotEn && pte.n) || (CVA6Cfg.SvnapotEn && !(pte.r || pte.x) && pte.n)) state_d = PROPAGATE_ERROR; // ----------- // Valid PTE // ----------- else begin state_d = LATENCY; - // it is a valid PTE - // if pte.r = 1 or pte.x = 1 it is a valid PTE + // if pte.r = 1 or pte.x = 1 it is a valid leaf PTE if (pte.r || pte.x) begin + // A 64KiB NAPOT page is identified by the N-bit being set and PPN[3:0] encoding '1000' + if (CVA6Cfg.SvnapotEn && pte.n) begin + // Svnapot: Check if the leaf PTE represents a 64KiB NAPOT page + is_napot_64k = (pte.ppn[3:0] == 4'b1000) && (ptw_lvl_q[0] == 2); + // Svnapot: Any other encoding with the N-bit set is a reserved format and must cause a page fault + // Additionally, fault if N is set on a megapage or gigapage + if (!is_napot_64k) begin + state_d = PROPAGATE_ERROR; + end + end + if (CVA6Cfg.RVH) begin case (ptw_stage_q) S_STAGE: begin @@ -421,7 +464,7 @@ module cva6_ptw gpaddr_n = gpaddr[ptw_lvl_q[0]]; ptw_pptr_n = { hgatp_ppn_i[CVA6Cfg.PPNW-1:2], - gpaddr[ptw_lvl_q[0]][CVA6Cfg.SV+HYP_EXT*2-1:CVA6Cfg.SV-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)], + gpaddr[ptw_lvl_q[0]][CVA6Cfg.GPLEN-1:CVA6Cfg.SV-(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)], (CVA6Cfg.PtLevels)'(0) }; ptw_lvl_n[0] = '0; @@ -431,7 +474,7 @@ module cva6_ptw state_d = WAIT_GRANT; ptw_stage_d = S_STAGE; ptw_lvl_n[0] = ptw_lvl_q[HYP_EXT]; - pptr = {pte.ppn[CVA6Cfg.GPPNW-1:0], gptw_pptr_q[11:0]}; + pptr = {pte.ppn, gptw_pptr_q[11:0]}; if (ptw_lvl_q[0] == 1) pptr[20:0] = gptw_pptr_q[20:0]; if (ptw_lvl_q[0] == 0) pptr[29:0] = gptw_pptr_q[29:0]; ptw_pptr_n = pptr; @@ -447,11 +490,12 @@ module cva6_ptw // If page is not executable, we can directly raise an error. This // doesn't put a useless entry into the TLB. The same idea applies // to the access flag since we let the access flag be managed by SW. - if (!pte.x || !pte.a) begin + if ((!pte.x && (!CVA6Cfg.RVH || ptw_stage_q != G_INTERMED_STAGE)) || !pte.a + || (CVA6Cfg.RVH && ptw_stage_q == G_INTERMED_STAGE && !pte.r)) begin state_d = PROPAGATE_ERROR; if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; - end else if (CVA6Cfg.RVH && ((ptw_stage_q == G_FINAL_STAGE) || !enable_g_translation_i) || !CVA6Cfg.RVH) - shared_tlb_update_o.valid = 1'b1; + end else if ((CVA6Cfg.RVH && ((ptw_stage_q == G_FINAL_STAGE) || !enable_g_translation_i)) || !CVA6Cfg.RVH) + shared_tlb_update_valid = 1'b1; end else begin // ------------ @@ -462,35 +506,37 @@ module cva6_ptw // If page is not readable (there are no write-only pages) // we can directly raise an error. This doesn't put a useless // entry into the TLB. - if (pte.a && ((pte.r && !hlvx_inst_i) || (pte.x && (mxr_i || hlvx_inst_i || (ptw_stage_q == S_STAGE && vmxr_i && ld_st_v_i && CVA6Cfg.RVH))))) begin - if (CVA6Cfg.RVH && ((ptw_stage_q == G_FINAL_STAGE) || !en_ld_st_g_translation_i) || !CVA6Cfg.RVH) - shared_tlb_update_o.valid = 1'b1; + if ( + (pte.a && ((pte.r && !hlvx_eff) || (pte.x && (mxr_i || hlvx_eff || (ptw_stage_q == S_STAGE && vmxr_i && ld_st_v_i && CVA6Cfg.RVH))))) + // Request is a store: perform some additional checks + // If the request was a store and the page is not write-able, raise an error + // the same applies if the dirty flag is not set + // g-intermediate nodes however never need write-permission + && (!lsu_is_store_i || (pte.w && pte.d) || (ptw_stage_q == G_INTERMED_STAGE && CVA6Cfg.RVH)) + ) begin + if ((CVA6Cfg.RVH && ((ptw_stage_q == G_FINAL_STAGE) || !en_ld_st_g_translation_i)) || !CVA6Cfg.RVH) + shared_tlb_update_valid = 1'b1; end else begin state_d = PROPAGATE_ERROR; if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; end - // Request is a store: perform some additional checks - // If the request was a store and the page is not write-able, raise an error - // the same applies if the dirty flag is not set - if (lsu_is_store_i && (!pte.w || !pte.d)) begin - shared_tlb_update_o.valid = 1'b0; - state_d = PROPAGATE_ERROR; - if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; - end end - //if there is a misaligned page, propagate error + if (CVA6Cfg.SvnapotEn && pte.n && !is_napot_64k) shared_tlb_update_valid = 1'b0; + + // if there is a misaligned page, propagate error if (|misaligned_page) begin state_d = PROPAGATE_ERROR; if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; - shared_tlb_update_o.valid = 1'b0; + shared_tlb_update_valid = 1'b0; end // check if 63:41 are all zeros if (CVA6Cfg.RVH) begin - if (((v_i && is_instr_ptw_q) || (ld_st_v_i && !is_instr_ptw_q)) && ptw_stage_q == S_STAGE && !((|pte.ppn[CVA6Cfg.PPNW-1:CVA6Cfg.GPPNW-1+HYP_EXT]) == 1'b0)) begin + if (((v_i && is_instr_ptw_q) || (ld_st_v_i && !is_instr_ptw_q)) && ptw_stage_q == S_STAGE && !((|pte.ppn[CVA6Cfg.PPNW-1:CVA6Cfg.GPPNW]) == 1'b0)) begin state_d = PROPAGATE_ERROR; ptw_stage_d = G_FINAL_STAGE; + shared_tlb_update_valid = 1'b0; end end // this is a pointer to the next TLB level @@ -513,7 +559,6 @@ module cva6_ptw S_STAGE: begin if (CVA6Cfg.RVH && ((is_instr_ptw_q && enable_g_translation_i) || (!is_instr_ptw_q && en_ld_st_g_translation_i))) begin ptw_stage_d = G_INTERMED_STAGE; - if (CVA6Cfg.RVH) gpte_d = pte; ptw_lvl_n[HYP_EXT] = ptw_lvl_q[0] + 1; pptr = {pte.ppn, vaddr_lvl[0][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0)}; gptw_pptr_n = pptr; @@ -537,29 +582,30 @@ module cva6_ptw pte.ppn, vaddr_lvl[HYP_EXT*2][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0) }; end + default: ; endcase end else ptw_pptr_n = {pte.ppn, vaddr_lvl[0][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0)}; - if (CVA6Cfg.RVH && (pte.a || pte.d || pte.u)) begin + if (pte.a || pte.d || pte.u) begin state_d = PROPAGATE_ERROR; - ptw_stage_d = ptw_stage_q; + if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; end end // check if 63:41 are all zeros if (CVA6Cfg.RVH) begin - if (((v_i && is_instr_ptw_q) || (ld_st_v_i && !is_instr_ptw_q)) && ptw_stage_q == S_STAGE && !((|pte.ppn[CVA6Cfg.PPNW-1:CVA6Cfg.GPPNW-1+HYP_EXT]) == 1'b0)) begin + if (((v_i && is_instr_ptw_q) || (ld_st_v_i && !is_instr_ptw_q)) && ptw_stage_q == S_STAGE && !((|pte.ppn[CVA6Cfg.PPNW-1:CVA6Cfg.GPPNW]) == 1'b0)) begin state_d = PROPAGATE_ERROR; - ptw_stage_d = ptw_stage_q; + ptw_stage_d = G_FINAL_STAGE; end end end end - // Check if this access was actually allowed from a PMP perspective + // check if this access was actually allowed from a PMP perspective if (!allow_access) begin - shared_tlb_update_o.valid = 1'b0; + shared_tlb_update_valid = 1'b0; // we have to return the failed address in bad_addr ptw_pptr_n = ptw_pptr_q; if (CVA6Cfg.RVH) ptw_stage_d = ptw_stage_q; @@ -602,12 +648,21 @@ module cva6_ptw // 1. in the PTE Lookup check whether we still need to wait for an rvalid // 2. waiting for a grant, if so: wait for it // if not, go back to idle - if (((state_q inside {PTE_LOOKUP, WAIT_RVALID}) && !data_rvalid_q) || ((state_q == WAIT_GRANT) && req_port_i.data_gnt)) - state_d = WAIT_RVALID; - else state_d = LATENCY; + if ((state_q inside {PTE_LOOKUP, WAIT_RVALID}) && !data_rvalid_q) state_d = WAIT_RVALID; + else if (state_q != WAIT_GRANT) state_d = LATENCY; + + kill_req_n = (state_q == WAIT_GRANT); end end + // Big Endian Capability Additions + // req_port_i.data_rdata is the data coming into the Page Table Walker from Data Memory. If mbe=1 meaning the processor is in Big Endian data mode, then we need to reverse the byte order to correctly view this data. + // Otherwise, this page table walker would not be able to understand a page table stored in Big Endian byte order. + logic [CVA6Cfg.XLEN-1:0] endian_data; + logic [CVA6Cfg.XLEN-1:0] byteSwapped_data; + assign byteSwapped_data = {<<8{req_port_i.data_rdata}}; + assign endian_data = mbe_i ? byteSwapped_data : req_port_i.data_rdata; + // sequential process always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin @@ -615,18 +670,19 @@ module cva6_ptw is_instr_ptw_q <= 1'b0; ptw_lvl_q <= '0; tag_valid_q <= 1'b0; + kill_req_q <= 1'b0; tlb_update_asid_q <= '0; - tlb_update_vmid_q <= '0; vaddr_q <= '0; ptw_pptr_q <= '0; global_mapping_q <= 1'b0; data_rdata_q <= '0; data_rvalid_q <= 1'b0; if (CVA6Cfg.RVH) begin - gpaddr_q <= '0; - gptw_pptr_q <= '0; - ptw_stage_q <= S_STAGE; - gpte_q <= '0; + gpaddr_q <= '0; + gptw_pptr_q <= '0; + ptw_stage_q <= S_STAGE; + gpte_q <= '0; + tlb_update_vmid_q <= '0; end end else begin state_q <= state_d; @@ -634,10 +690,12 @@ module cva6_ptw is_instr_ptw_q <= is_instr_ptw_n; ptw_lvl_q <= ptw_lvl_n; tag_valid_q <= tag_valid_n; + kill_req_q <= kill_req_n; tlb_update_asid_q <= tlb_update_asid_n; vaddr_q <= vaddr_n; global_mapping_q <= global_mapping_n; - data_rdata_q <= req_port_i.data_rdata; + //data_rdata_q <= req_port_i.data_rdata; + data_rdata_q <= endian_data; data_rvalid_q <= req_port_i.data_rvalid; if (CVA6Cfg.RVH) begin diff --git a/core/cva6_mmu/cva6_shared_tlb.sv b/core/cva6_mmu/cva6_shared_tlb.sv index 729d2194c50..a8065881d57 100644 --- a/core/cva6_mmu/cva6_shared_tlb.sv +++ b/core/cva6_mmu/cva6_shared_tlb.sv @@ -56,6 +56,11 @@ module cva6_shared_tlb #( input logic shared_tlb_miss_i, + input logic [CVA6Cfg.ASID_WIDTH-1:0] asid_to_be_flushed_i, //control inputs for flush + input logic [CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed_i, + input logic [CVA6Cfg.VMID_WIDTH-1:0] vmid_to_be_flushed_i, + input logic [CVA6Cfg.GPLEN-1:0] gpaddr_to_be_flushed_i, + // to TLBs, update logic output tlb_update_cva6_t itlb_update_o, output tlb_update_cva6_t dtlb_update_o, @@ -64,6 +69,8 @@ module cva6_shared_tlb #( output logic itlb_miss_o, output logic dtlb_miss_o, + output logic flush_busy_o, + output logic shared_tlb_access_o, output logic shared_tlb_hit_o, output logic [CVA6Cfg.VLEN-1:0] shared_tlb_vaddr_o, @@ -89,11 +96,41 @@ module cva6_shared_tlb #( logic [CVA6Cfg.PtLevels+HYP_EXT-1:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] vpn; logic [CVA6Cfg.PtLevels-2:0][HYP_EXT:0] is_page; logic [HYP_EXT*2:0] v_st_enbl; // v_i,g-stage enabled, s-stage enabled + logic is_napot_64k; // Svnapot: Flag indicating a 64KiB NAPOT page } shared_tag_t; shared_tag_t shared_tag_wr; shared_tag_t [SHARED_TLB_WAYS-1:0] shared_tag_rd; + typedef enum logic [1:0] { + FLUSH_SFENCE, + FLUSH_VVMA, + FLUSH_GVMA + } flush_kind_e; + flush_kind_e flush_kind_q, flush_kind_d; + + typedef enum logic [1:0] { + IDLE, + FLUSH_READ, + FLUSH_APPLY + } flush_state_e; //flushing states + flush_state_e flush_state_q, flush_state_d; + + // flushing + logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] flush_idx_q, flush_idx_d; + logic [CVA6Cfg.ASID_WIDTH-1:0] flush_asid_q, flush_asid_d; + logic [CVA6Cfg.VLEN-1:0] flush_vaddr_q, flush_vaddr_d; + logic [CVA6Cfg.VMID_WIDTH-1:0] flush_vmid_q, flush_vmid_d; + logic [CVA6Cfg.GPLEN-1:0] flush_gpaddr_q, flush_gpaddr_d; + + logic [SHARED_TLB_WAYS-1:0] sfence_match_way; + logic [SHARED_TLB_WAYS-1:0] vvma_match_way; + logic [SHARED_TLB_WAYS-1:0] gvma_match_way; + logic [SHARED_TLB_WAYS-1:0] flush_match_way; + + logic flush_vmid_is0; + logic flush_gpaddr_is0; + logic [CVA6Cfg.SharedTlbDepth-1:0][SHARED_TLB_WAYS-1:0] shared_tag_valid_q, shared_tag_valid_d; logic [ SHARED_TLB_WAYS-1:0] shared_tag_valid; @@ -143,6 +180,11 @@ module cva6_shared_tlb #( logic shared_tlb_hit_d; logic [CVA6Cfg.VLEN-1:0] shared_tlb_vaddr_q, shared_tlb_vaddr_d; + logic [ CVA6Cfg.VpnLen-1:0] lu_vpn; + logic [SHARED_TLB_WAYS-1:0] vpn0_napot_match; + logic [SHARED_TLB_WAYS-1:0] napot_tag_match; + pte_cva6_t patched_pte; + logic itlb_req_d, itlb_req_q; logic dtlb_req_d, dtlb_req_q; @@ -164,47 +206,61 @@ module cva6_shared_tlb #( assign shared_tlb_vaddr_o = shared_tlb_vaddr_q; assign itlb_req_o = itlb_req_q; assign v_st_enbl = {{v_i, g_st_enbl_i, s_st_enbl_i}, {ld_st_v_i, g_ld_st_enbl_i, s_ld_st_enbl_i}}; + assign lu_vpn = itlb_req_q ? itlb_vpn_q : dtlb_vpn_q; + + assign flush_vmid_is0 = ~(|flush_vmid_q); + assign flush_gpaddr_is0 = ~(|flush_gpaddr_q); + assign flush_match_way = (flush_kind_q == FLUSH_SFENCE)? sfence_match_way: (flush_kind_q == FLUSH_VVMA)? vvma_match_way: gvma_match_way; + + assign shared_tag_wr.asid = shared_tlb_update_i.asid; + assign shared_tag_wr.vmid = shared_tlb_update_i.vmid; + assign shared_tag_wr.is_page = shared_tlb_update_i.is_page; + assign shared_tag_wr.v_st_enbl = v_st_enbl[i_req_q][HYP_EXT*2:0]; - genvar i, x; + genvar i_gen, x_gen; generate - for (i = 0; i < SHARED_TLB_WAYS; i++) begin : gen_match_tlb_ways + for (i_gen = 0; i_gen < SHARED_TLB_WAYS; i_gen++) begin : gen_match_tlb_ways //identify page_match for all TLB Entries - for (x = 0; x < CVA6Cfg.PtLevels; x++) begin : gen_match - assign page_match[i][x] = x==0 ? 1 :((HYP_EXT==0 || x==(CVA6Cfg.PtLevels-1)) ? // PAGE_MATCH CONTAINS THE MATCH INFORMATION FOR EACH TAG OF is_1G and is_2M in sv39x4. HIGHER LEVEL (Giga page), THEN THERE IS THE Mega page AND AT THE LOWER LEVEL IS ALWAYS 1 - &(shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x] | (~v_st_enbl[i_req_q][HYP_EXT:0])): + for (x_gen = 0; x_gen < CVA6Cfg.PtLevels; x_gen++) begin : gen_match + assign page_match[i_gen][x_gen] = x_gen==0 ? 1 :((HYP_EXT==0 || x_gen==(CVA6Cfg.PtLevels-1)) ? // PAGE_MATCH CONTAINS THE MATCH INFORMATION FOR EACH TAG OF is_1G and is_2M in sv39x4. HIGHER LEVEL (Giga page), THEN THERE IS THE Mega page AND AT THE LOWER LEVEL IS ALWAYS 1 + &(shared_tag_rd[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen] | (~v_st_enbl[i_req_q][HYP_EXT:0])): ((&v_st_enbl[i_req_q][HYP_EXT:0]) ? - ((shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][0] && (shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-2-x][HYP_EXT] || shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT])) - || (shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT] && (shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-2-x][0] || shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][0]))): - shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][0] && v_st_enbl[i_req_q][0] || shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT] && v_st_enbl[i_req_q][HYP_EXT])); + ((shared_tag_rd[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][0] && (shared_tag_rd[i_gen].is_page[CVA6Cfg.PtLevels-2-x_gen][HYP_EXT] || shared_tag_rd[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][HYP_EXT])) + || (shared_tag_rd[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][HYP_EXT] && (shared_tag_rd[i_gen].is_page[CVA6Cfg.PtLevels-2-x_gen][0] || shared_tag_rd[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][0]))): + shared_tag_rd[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][0] && v_st_enbl[i_req_q][0] || shared_tag_rd[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][HYP_EXT] && v_st_enbl[i_req_q][HYP_EXT])); //identify if vpn matches at all PT levels for all TLB entries - assign vpn_match[i][x] = (HYP_EXT==1 && x==(CVA6Cfg.PtLevels-1) && ~v_st_enbl[i_req_q][0]) ? // - vpn_q[x] == shared_tag_rd[i].vpn[x] && vpn_q[x+HYP_EXT][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-HYP_EXT:0] == shared_tag_rd[i].vpn[x+HYP_EXT][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-HYP_EXT:0]: // - vpn_q[x] == shared_tag_rd[i].vpn[x]; + assign vpn_match[i_gen][x_gen] = (HYP_EXT==1 && x_gen==(CVA6Cfg.PtLevels-1) && ~v_st_enbl[i_req_q][0]) ? // + vpn_q[x_gen] == shared_tag_rd[i_gen].vpn[x_gen] && vpn_q[x_gen+HYP_EXT][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-HYP_EXT:0] == shared_tag_rd[i_gen].vpn[x_gen+HYP_EXT][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-HYP_EXT:0]: // + vpn_q[x_gen] == shared_tag_rd[i_gen].vpn[x_gen]; //identify if there is a hit at each PT level for all TLB entries - assign level_match[i][x] = &vpn_match[i][CVA6Cfg.PtLevels-1:x] && page_match[i][x]; + assign level_match[i_gen][x_gen] = &vpn_match[i_gen][CVA6Cfg.PtLevels-1:x_gen] && page_match[i_gen][x_gen]; end + assign vpn0_napot_match[i_gen] = lu_vpn[(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1 : 4] == shared_tag_rd[i_gen].vpn[0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1 : 4]; + assign napot_tag_match[i_gen] = (CVA6Cfg.SvnapotEn && shared_tag_rd[i_gen].is_napot_64k) ? + (vpn_match[i_gen][2] && vpn_match[i_gen][1] && vpn0_napot_match[i_gen]) : 1'b0; end endgenerate - genvar w; + genvar w_gen; generate - for (w = 0; w < CVA6Cfg.PtLevels; w++) begin - assign vpn_d[w] = ((|v_st_enbl[1][HYP_EXT:0]) && itlb_access_i && ~itlb_hit_i && ~dtlb_access_i) ? // - itlb_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(w+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*w)] : // + for (w_gen = 0; w_gen < CVA6Cfg.PtLevels; w_gen++) begin + assign vpn_d[w_gen] = ((|v_st_enbl[1][HYP_EXT:0]) && itlb_access_i && ~itlb_hit_i && ~dtlb_access_i) ? // + itlb_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(w_gen+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*w_gen)] : // (((|v_st_enbl[0][HYP_EXT:0]) && dtlb_access_i && ~dtlb_hit_i) ? // - dtlb_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(w+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*w)] : vpn_q[w]); + dtlb_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(w_gen+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*w_gen)] : vpn_q[w_gen]); end endgenerate if (CVA6Cfg.RVH) //THIS UPDATES THE EXTRA BITS OF VPN IN SV39x4 - assign vpn_d[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0] = ((|v_st_enbl[1][HYP_EXT:0]) && itlb_access_i && ~itlb_hit_i && ~dtlb_access_i) ? // - itlb_vaddr_i[CVA6Cfg.VpnLen-1:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)] : // + assign vpn_d[CVA6Cfg.PtLevels] = ((|v_st_enbl[1][HYP_EXT:0]) && itlb_access_i && ~itlb_hit_i && ~dtlb_access_i) ? // + {{(((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels))){1'b0}}, itlb_vaddr_i[CVA6Cfg.VpnLen-1:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)]} : // (((|v_st_enbl[0][HYP_EXT:0]) && dtlb_access_i && ~dtlb_hit_i) ? // - dtlb_vaddr_i[CVA6Cfg.VpnLen-1: CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)] : vpn_q[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0]); + {{(((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels))){1'b0}}, dtlb_vaddr_i[CVA6Cfg.VpnLen-1: CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)]} : // + {{(((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels))){1'b0}}, vpn_q[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0]}); /////////////////////////////////////////////////////// // tag comparison, hit generation @@ -229,8 +285,16 @@ module cva6_shared_tlb #( pte_rd_addr = '0; i_req_d = i_req_q; - // if we got an ITLB miss - if ((|v_st_enbl[1][HYP_EXT:0]) & itlb_access_i & ~itlb_hit_i & ~dtlb_access_i) begin + //owning read ports while flush walker is active + if (flush_state_q == FLUSH_READ) begin + tag_rd_en = '1; + pte_rd_en = '1; + tag_rd_addr = flush_idx_q; + pte_rd_addr = flush_idx_q; + end else if ((flush_state_q != IDLE) || flush_i || flush_vvma_i || flush_gvma_i) begin + //minimal approach holding lookup quiet during flush + // if we got an ITLB miss + end else if ((|v_st_enbl[1][HYP_EXT:0]) & itlb_access_i & ~itlb_hit_i & ~dtlb_access_i) begin tag_rd_en = '1; tag_rd_addr = itlb_vaddr_i[12+:$clog2(CVA6Cfg.SharedTlbDepth)]; pte_rd_en = '1; @@ -283,6 +347,7 @@ module cva6_shared_tlb #( itlb_update_o.v_st_enbl = v_st_enbl[i_req_q][HYP_EXT*2:0]; itlb_update_o.asid = shared_tlb_update_i.asid; itlb_update_o.vmid = shared_tlb_update_i.vmid; + itlb_update_o.is_napot_64k = shared_tlb_update_i.is_napot_64k; end else if (dtlb_req_q) begin dtlb_update_o.valid = 1'b1; @@ -293,6 +358,7 @@ module cva6_shared_tlb #( dtlb_update_o.v_st_enbl = v_st_enbl[i_req_q][HYP_EXT*2:0]; dtlb_update_o.asid = shared_tlb_update_i.asid; dtlb_update_o.vmid = shared_tlb_update_i.vmid; + dtlb_update_o.is_napot_64k = shared_tlb_update_i.is_napot_64k; end end end else begin @@ -310,27 +376,35 @@ module cva6_shared_tlb #( // check if translation is a: S-Stage and G-Stage, S-Stage only or G-Stage only translation and virtualization mode is on/off match_stage[i] = shared_tag_rd[i].v_st_enbl == v_st_enbl[i_req_q][HYP_EXT*2:0]; - if (shared_tag_valid[i] && match_asid && match_vmid && match_stage[i]) begin - if (|level_match[i]) begin + if (shared_tag_valid[i] && match_asid[i] && match_vmid[i] && match_stage[i]) begin + if (|level_match[i] || napot_tag_match[i]) begin shared_tlb_hit_d = 1'b1; + // Prepare PTE with NAPOT patching if needed + patched_pte = pte[i][0]; // take the S‑stage PTE only + if (shared_tag_rd[i].is_napot_64k && CVA6Cfg.SvnapotEn) begin + // replace PPN[3:0] with vaddr[15:12] (equiv. lu_vpn[3:0]) + patched_pte.ppn[3:0] = lu_vpn[3:0]; + end if (itlb_req_q) begin itlb_update_o.valid = 1'b1; itlb_update_o.vpn = itlb_vpn_q; itlb_update_o.is_page = shared_tag_rd[i].is_page; - itlb_update_o.content = pte[i][0]; + itlb_update_o.content = patched_pte; itlb_update_o.g_content = pte[i][HYP_EXT]; itlb_update_o.v_st_enbl = shared_tag_rd[i].v_st_enbl; itlb_update_o.asid = tlb_update_asid_q; itlb_update_o.vmid = tlb_update_vmid_q; + itlb_update_o.is_napot_64k = CVA6Cfg.SvnapotEn ? shared_tag_rd[i].is_napot_64k : 1'b0; end else if (dtlb_req_q) begin dtlb_update_o.valid = 1'b1; dtlb_update_o.vpn = dtlb_vpn_q; dtlb_update_o.is_page = shared_tag_rd[i].is_page; - dtlb_update_o.content = pte[i][0]; + dtlb_update_o.content = patched_pte; dtlb_update_o.g_content = pte[i][HYP_EXT]; dtlb_update_o.v_st_enbl = shared_tag_rd[i].v_st_enbl; dtlb_update_o.asid = tlb_update_asid_q; dtlb_update_o.vmid = tlb_update_vmid_q; + dtlb_update_o.is_napot_64k = CVA6Cfg.SvnapotEn ? shared_tag_rd[i].is_napot_64k : 1'b0; end end end @@ -344,7 +418,6 @@ module cva6_shared_tlb #( itlb_vpn_q <= '0; dtlb_vpn_q <= '0; tlb_update_asid_q <= '{default: 0}; - tlb_update_vmid_q <= '{default: 0}; shared_tlb_access_q <= '0; shared_tlb_vaddr_q <= '0; shared_tag_valid_q <= '0; @@ -353,6 +426,14 @@ module cva6_shared_tlb #( dtlb_req_q <= '0; i_req_q <= 0; shared_tag_valid <= '0; + flush_state_q <= IDLE; + flush_idx_q <= '0; + flush_asid_q <= '0; + flush_vaddr_q <= '0; + flush_kind_q <= FLUSH_SFENCE; + flush_vmid_q <= '0; + flush_gpaddr_q <= '0; + end else begin itlb_vpn_q <= itlb_vaddr_i[CVA6Cfg.SV-1:12]; dtlb_vpn_q <= dtlb_vaddr_i[CVA6Cfg.SV-1:12]; @@ -365,53 +446,311 @@ module cva6_shared_tlb #( dtlb_req_q <= dtlb_req_d; i_req_q <= i_req_d; shared_tag_valid <= shared_tag_valid_q[tag_rd_addr]; + flush_state_q <= flush_state_d; + flush_idx_q <= flush_idx_d; + flush_asid_q <= flush_asid_d; + flush_vaddr_q <= flush_vaddr_d; + flush_kind_q <= flush_kind_d; + flush_vmid_q <= flush_vmid_d; + flush_gpaddr_q <= flush_gpaddr_d; - if (CVA6Cfg.RVH) tlb_update_vmid_q <= tlb_update_vmid_d; + end + end + + if (CVA6Cfg.RVH) begin + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + tlb_update_vmid_q <= '{default: 0}; + end else begin + tlb_update_vmid_q <= tlb_update_vmid_d; + end end end // ------------------ // Update and Flush // ------------------ + + logic [CVA6Cfg.VpnLen-1:0] vpn_to_store; + logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] vpn_index; + //flushing signals + logic flush_asid_is0; + logic flush_vaddr_is0; + logic flush_last_set; + + // When storing the VPN in the shared TLB, if NAPOT is used, the lower bits of the VPN are zeroed + // This way, when searching for a match, we can compare the full VPN if NAPOT is not used + // or only the upper bits if NAPOT is used (the lower bits are don't care) + // The actual PPN is stored in the PTE, with the lower bits patched if NAPOT is used + // This is done in the tag comparison logic above + + assign vpn_to_store = + (shared_tlb_update_i.is_napot_64k && CVA6Cfg.SvnapotEn) + ? {shared_tlb_update_i.vpn[CVA6Cfg.VpnLen-1:4], 4'b0} + : shared_tlb_update_i.vpn; + + always_comb begin : flush_fsm + flush_state_d = flush_state_q; + flush_idx_d = flush_idx_q; + flush_asid_d = flush_asid_q; + flush_vaddr_d = flush_vaddr_q; + flush_kind_d = flush_kind_q; + flush_vmid_d = flush_vmid_q; + flush_gpaddr_d = flush_gpaddr_q; + + unique case (flush_state_q) + IDLE: begin + if (flush_i) begin + flush_state_d = FLUSH_READ; + flush_idx_d = '0; + flush_asid_d = asid_to_be_flushed_i; + flush_vaddr_d = vaddr_to_be_flushed_i; + flush_kind_d = FLUSH_SFENCE; + flush_vmid_d = '0; + flush_gpaddr_d = '0; + end else if (flush_vvma_i) begin + flush_state_d = FLUSH_READ; + flush_idx_d = '0; + flush_asid_d = asid_to_be_flushed_i; + flush_vaddr_d = vaddr_to_be_flushed_i; + flush_kind_d = FLUSH_VVMA; + flush_vmid_d = lu_vmid_i; + flush_gpaddr_d = '0; + end else if (flush_gvma_i) begin + flush_state_d = FLUSH_READ; + flush_idx_d = '0; + flush_asid_d = '0; + flush_vaddr_d = '0; + flush_kind_d = FLUSH_GVMA; + flush_vmid_d = vmid_to_be_flushed_i; + flush_gpaddr_d = gpaddr_to_be_flushed_i; + end + end + + FLUSH_READ: begin + flush_state_d = FLUSH_APPLY; + end + + FLUSH_APPLY: begin + if (flush_last_set) begin + flush_state_d = IDLE; + flush_idx_d = '0; + end else begin + flush_idx_d = flush_idx_q + 1'b1; + flush_state_d = FLUSH_READ; + end + end + + default: begin + flush_state_d = IDLE; + end + endcase + end + + localparam int unsigned VPN_SEG_W = CVA6Cfg.VpnLen / CVA6Cfg.PtLevels; + always_comb begin : sfence_match_logic + sfence_match_way = '0; + + for (int unsigned i = 0; i < SHARED_TLB_WAYS; i++) begin + logic [CVA6Cfg.PtLevels-1:0] flush_vpn_match; + logic [CVA6Cfg.PtLevels-1:0] flush_level_match; + logic flush_addr_matches; + logic flush_addr_napot_matches; + logic upper_levels_match; + + flush_vpn_match = '0; + flush_level_match = '0; + flush_addr_matches = 1'b0; + flush_addr_napot_matches = 1'b0; + upper_levels_match = 1'b0; + + for (int unsigned level = 0; level < CVA6Cfg.PtLevels; level++) begin + flush_vpn_match[level] = flush_vaddr_q[12 + VPN_SEG_W*level +: VPN_SEG_W] == shared_tag_rd[i].vpn[level]; + end + //comparing the flush VA with stored VPN level by level_match + for (int unsigned level = 0; level < CVA6Cfg.PtLevels; level++) begin + upper_levels_match = 1'b1; + for (int unsigned k = level; k < CVA6Cfg.PtLevels; k++) begin + upper_levels_match &= flush_vpn_match[k]; + end + flush_level_match[level] = upper_levels_match && ((level==0)? 1'b1: shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-level][0]); + end + + if (CVA6Cfg.SvnapotEn && shared_tag_rd[i].is_napot_64k) begin + //VA matching NAPOT tag + flush_addr_napot_matches = ((CVA6Cfg.PtLevels > 1)? (&flush_vpn_match[CVA6Cfg.PtLevels-1:1]): 1'b1) && (flush_vaddr_q[12+VPN_SEG_W-1: 16] == shared_tag_rd[i].vpn[0][VPN_SEG_W-1: 4]); + end + + flush_addr_matches = (|flush_level_match) || flush_addr_napot_matches; + + if (shared_tag_valid[i] && ((HYP_EXT == 0) || !shared_tag_rd[i].v_st_enbl[HYP_EXT*2])) begin + if (flush_asid_is0 && flush_vaddr_is0) begin //SFENCE.VMA x0, x0 + sfence_match_way[i] = 1'b1; + end else if(flush_asid_is0 && flush_addr_matches && !flush_vaddr_is0) begin //SFENCE.VMA vaddr, x0 + sfence_match_way[i] = 1'b1; + end else if(!pte[i][0].g && flush_addr_matches && (flush_asid_q == shared_tag_rd[i].asid) && !flush_vaddr_is0 && !flush_asid_is0) begin //SFENCE.VMA vaddr, asid + sfence_match_way[i] = 1'b1; + end else if(!pte[i][0].g && flush_vaddr_is0 &&(flush_asid_q == shared_tag_rd[i].asid) && !flush_asid_is0)begin + sfence_match_way[i] = 1'b1; + end + end + end + end + + always_comb begin : vvma_match_logic + vvma_match_way = '0; + + for (int unsigned i = 0; i < SHARED_TLB_WAYS; i++) begin + logic [CVA6Cfg.PtLevels-1:0] flush_vpn_match; + logic [CVA6Cfg.PtLevels-1:0] flush_level_match; + logic flush_addr_matches; + logic flush_addr_napot_matches; + logic upper_levels_match; + logic current_vmid_matches; + + flush_vpn_match = '0; + flush_level_match = '0; + flush_addr_matches = 1'b0; + flush_addr_napot_matches = 1'b0; + upper_levels_match = 1'b0; + + for (int unsigned level = 0; level < CVA6Cfg.PtLevels; level++) begin + flush_vpn_match[level] = flush_vaddr_q[12 + VPN_SEG_W*level +: VPN_SEG_W] == shared_tag_rd[i].vpn[level]; + end + for (int unsigned level = 0; level < CVA6Cfg.PtLevels; level++) begin + upper_levels_match = 1'b1; + for (int unsigned k = level; k < CVA6Cfg.PtLevels; k++) begin + upper_levels_match &= flush_vpn_match[k]; + end + flush_level_match[level] = upper_levels_match && ((level==0) ? 1'b1: shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-level][0]); + end + + if (CVA6Cfg.SvnapotEn && shared_tag_rd[i].is_napot_64k) begin + flush_addr_napot_matches = ((CVA6Cfg.PtLevels > 1) ? (&flush_vpn_match[CVA6Cfg.PtLevels-1:1]) : 1'b1) && (flush_vaddr_q[12+VPN_SEG_W-1:16]==shared_tag_rd[i].vpn[0][VPN_SEG_W-1:4]); + end + + flush_addr_matches = (|flush_level_match) || flush_addr_napot_matches; + + current_vmid_matches = ((shared_tag_rd[i].v_st_enbl[HYP_EXT] && (flush_vmid_q == shared_tag_rd[i].vmid)) ||!shared_tag_rd[i].v_st_enbl[HYP_EXT]); + + if(CVA6Cfg.RVH && shared_tag_valid[i] && shared_tag_rd[i].v_st_enbl[HYP_EXT*2] && shared_tag_rd[i].v_st_enbl[0]) begin + if (flush_asid_is0 && flush_vaddr_is0 && current_vmid_matches) begin + vvma_match_way[i] = 1'b1; + end else if (flush_asid_is0 && flush_addr_matches && !flush_vaddr_is0 && current_vmid_matches) begin + vvma_match_way[i] = 1'b1; + end else if(!pte[i][0].g && flush_addr_matches && (flush_asid_q == shared_tag_rd[i].asid) && !flush_vaddr_is0 && !flush_asid_is0 && current_vmid_matches) begin + vvma_match_way[i] = 1'b1; + end else if(!pte[i][0].g && flush_vaddr_is0 && (flush_asid_q == shared_tag_rd[i].asid) && !flush_asid_is0 && current_vmid_matches) begin + vvma_match_way[i] = 1'b1; + end + end + end + end + + always_comb begin : gvma_match_logic + gvma_match_way = '0; + + for (int unsigned i = 0; i < SHARED_TLB_WAYS; i++) begin + logic [CVA6Cfg.VpnLen-1:0] gppn_i; + logic [CVA6Cfg.PtLevels-1:0] gpaddr_vpn_match; + logic [CVA6Cfg.PtLevels-1:0] gpaddr_level_match; + logic upper_levels_match; + + gppn_i = '0; + gpaddr_vpn_match = '0; + gpaddr_level_match = '0; + upper_levels_match = '0; + + if (CVA6Cfg.RVH) begin + if (shared_tag_rd[i].v_st_enbl[0]) begin + gppn_i[CVA6Cfg.GPPNW-1:0] = pte[i][0].ppn[CVA6Cfg.GPPNW-1:0]; + + if (shared_tag_rd[i].is_page[1][0]) gppn_i[VPN_SEG_W-1:0] = shared_tag_rd[i].vpn[0]; + if (shared_tag_rd[i].is_page[0][0]) + gppn_i[2*VPN_SEG_W-1:0] = {shared_tag_rd[i].vpn[1], shared_tag_rd[i].vpn[0]}; + end else begin + gppn_i[CVA6Cfg.VpnLen-1:0] = CVA6Cfg.VpnLen'({shared_tag_rd[i].vpn}); + end + + for (int unsigned level = 0; level < CVA6Cfg.PtLevels; level++) begin + gpaddr_vpn_match[level] = flush_gpaddr_q[12 + VPN_SEG_W*level +: VPN_SEG_W] == gppn_i[VPN_SEG_W*level +: VPN_SEG_W]; + end + + for (int unsigned level = 0; level < CVA6Cfg.PtLevels; level++) begin + upper_levels_match = 1'b1; + for (int unsigned k = level; k < CVA6Cfg.PtLevels; k++) begin + upper_levels_match &= gpaddr_vpn_match[k]; + end + gpaddr_level_match[level] = upper_levels_match && ((level == 0) ? 1'b1 : shared_tag_rd[i].is_page[CVA6Cfg.PtLevels-1-level][HYP_EXT]); + end + if (shared_tag_valid[i] && shared_tag_rd[i].v_st_enbl[HYP_EXT]) begin + if (flush_vmid_is0 && flush_gpaddr_is0) begin + gvma_match_way[i] = 1'b1; + end else if (flush_vmid_is0 && (|gpaddr_level_match) && !flush_gpaddr_is0) begin + gvma_match_way[i] = 1'b1; + end else if ((|gpaddr_level_match) && (flush_vmid_q == shared_tag_rd[i].vmid) && !flush_gpaddr_is0 && !flush_vmid_is0) begin + gvma_match_way[i] = 1'b1; + end else if (flush_gpaddr_is0 && (flush_vmid_q == shared_tag_rd[i].vmid) && !flush_vmid_is0) begin + gvma_match_way[i] = 1'b1; + end + end + end + end + end + always_comb begin : update_flush shared_tag_valid_d = shared_tag_valid_q; tag_wr_en = '0; pte_wr_en = '0; - if (flush_i || flush_vvma_i || flush_gvma_i) begin - shared_tag_valid_d = '0; - end else if (shared_tlb_update_i.valid) begin + if (flush_state_q == FLUSH_APPLY) begin + for (int unsigned i = 0; i < SHARED_TLB_WAYS; i++) begin + if (flush_match_way[i]) begin + shared_tag_valid_d[flush_idx_q][i] = 1'b0; + end + end + end + + if ((flush_state_q == IDLE) && !flush_i && !flush_vvma_i && !flush_gvma_i && shared_tlb_update_i.valid) begin for (int unsigned i = 0; i < SHARED_TLB_WAYS; i++) begin if (repl_way_oh_d[i]) begin - shared_tag_valid_d[shared_tlb_update_i.vpn[$clog2(CVA6Cfg.SharedTlbDepth)-1:0]][i] = 1'b1; + shared_tag_valid_d[vpn_index][i] = 1'b1; tag_wr_en[i] = 1'b1; pte_wr_en[i] = 1'b1; end end end - end //update_flush + end + //update_flush - assign shared_tag_wr.asid = shared_tlb_update_i.asid; - assign shared_tag_wr.vmid = shared_tlb_update_i.vmid; - assign shared_tag_wr.is_page = shared_tlb_update_i.is_page; - assign shared_tag_wr.v_st_enbl = v_st_enbl[i_req_q][HYP_EXT*2:0]; + assign flush_asid_is0 = ~(|flush_asid_q); + assign flush_vaddr_is0 = ~(|flush_vaddr_q); + assign flush_last_set = (flush_idx_q == CVA6Cfg.SharedTlbDepth - 1); + assign flush_busy_o = (CVA6Cfg.UseSharedTlb) && (flush_state_q != IDLE); - genvar z; + assign shared_tag_wr.is_napot_64k = shared_tlb_update_i.is_napot_64k; // Svnapot: Propagate the NAPOT flag from the update packet into the tag structure to be stored + genvar z_gen; generate - for (z = 0; z < CVA6Cfg.PtLevels; z++) begin : gen_shared_tag - assign shared_tag_wr.vpn[z] = shared_tlb_update_i.vpn[((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(z+1))-1:((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*z)]; + for (z_gen = 0; z_gen < CVA6Cfg.PtLevels; z_gen++) begin : gen_shared_tag + assign shared_tag_wr.vpn[z_gen] = vpn_to_store[((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(z_gen+1))-1:((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*z_gen)]; end if (CVA6Cfg.RVH) begin : gen_shared_tag_hyp //THIS UPDATES THE EXTRA BITS OF VPN IN SV39x4 - assign shared_tag_wr.vpn[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0] = shared_tlb_update_i.vpn[CVA6Cfg.VpnLen-1: CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)]; + assign shared_tag_wr.vpn[CVA6Cfg.PtLevels] = { + {(((CVA6Cfg.VpnLen / CVA6Cfg.PtLevels) - (CVA6Cfg.VpnLen % CVA6Cfg.PtLevels))) {1'b0}}, + shared_tlb_update_i.vpn[CVA6Cfg.VpnLen-1:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)] + }; end endgenerate - assign tag_wr_addr = shared_tlb_update_i.vpn[$clog2(CVA6Cfg.SharedTlbDepth)-1:0]; assign tag_wr_data = shared_tag_wr; - assign pte_wr_addr = shared_tlb_update_i.vpn[$clog2(CVA6Cfg.SharedTlbDepth)-1:0]; + // derive the set index from bits [4 +: clog2] of the (possibly masked) VPN + assign vpn_index = shared_tlb_update_i.vpn[$clog2(CVA6Cfg.SharedTlbDepth)-1:0]; + // write the new entry into that set + assign tag_wr_addr = vpn_index; + assign pte_wr_addr = vpn_index; assign pte_wr_data[0] = shared_tlb_update_i.content[CVA6Cfg.XLEN-1:0]; assign pte_wr_data[1] = shared_tlb_update_i.g_content[CVA6Cfg.XLEN-1:0]; @@ -495,6 +834,8 @@ module cva6_shared_tlb #( ); assign pte[i][a] = pte_cva6_t'(pte_rd_data[i][a]); end + end else begin + assign shared_tag_rd[i] = '0; end end endmodule diff --git a/core/cva6_mmu/cva6_tlb.sv b/core/cva6_mmu/cva6_tlb.sv index 68083f3e22d..7151e0a7510 100644 --- a/core/cva6_mmu/cva6_tlb.sv +++ b/core/cva6_mmu/cva6_tlb.sv @@ -15,9 +15,9 @@ // Author: Angela Gonzalez PlanV Technology // Date: 26/02/2024 // -// Description: Translation Lookaside Buffer, parameterizable to Sv32 or Sv39 , +// Description: Translation Lookaside Buffer, parameterizable to Sv32 or Sv39, // or sv39x4 fully set-associative -// This module is an merge of the Sv32 TLB developed by Sebastien +// This module is a merge of the Sv32 TLB developed by Sebastien // Jacq (Thales Research & Technology), the Sv39 TLB developed // by Florian Zaruba and David Schaffenrath and the Sv39x4 by Bruno Sá. @@ -33,10 +33,10 @@ module cva6_tlb input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic flush_i, // Flush normal translations signal - input logic flush_vvma_i, // Flush vs stage signal - input logic flush_gvma_i, // Flush g stage signal - input logic s_st_enbl_i, // s-stage enabled - input logic g_st_enbl_i, // g-stage enabled + input logic flush_vvma_i, // Flush VS stage signal + input logic flush_gvma_i, // Flush G stage signal + input logic s_st_enbl_i, // S-stage enabled + input logic g_st_enbl_i, // G-stage enabled input logic v_i, // virtualization mode // Update TLB input tlb_update_cva6_t update_i, @@ -55,21 +55,26 @@ module cva6_tlb output logic [CVA6Cfg.PtLevels-2:0] lu_is_page_o, output logic lu_hit_o ); - localparam GPPN2 = (CVA6Cfg.XLEN == 32) ? CVA6Cfg.VLEN - 33 : 10; // SV39 defines three levels of page tables struct packed { logic [CVA6Cfg.ASID_WIDTH-1:0] asid; logic [CVA6Cfg.VMID_WIDTH-1:0] vmid; + // VPN is: + // [0] -> VPN0 + // [1] -> VPN1 + // [2] -> VPN2 + // [3] -> 2-bit supplementary PPN2 in case of GPA logic [CVA6Cfg.PtLevels+HYP_EXT-1:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] vpn; logic [CVA6Cfg.PtLevels-2:0][HYP_EXT:0] is_page; - logic [HYP_EXT*2:0] v_st_enbl; // v_i,g-stage enabled, s-stage enabled + logic [HYP_EXT*2:0] v_st_enbl; // v_i, g-stage enabled, s-stage enabled logic valid; + logic is_napot_64k; // Svnapot: Flag indicating a 64KiB NAPOT page } [TLB_ENTRIES-1:0] tags_q, tags_n; struct packed { - pte_cva6_t pte; - pte_cva6_t gpte; + pte_cva6_t pte; // S or VS-stage Page Table Entry structure + pte_cva6_t gpte; // G-stage Page Table Entry structure } [TLB_ENTRIES-1:0] content_q, content_n; @@ -87,56 +92,91 @@ module cva6_tlb logic [TLB_ENTRIES-1:0] match_stage; pte_cva6_t g_content; logic [TLB_ENTRIES-1:0][(CVA6Cfg.GPPNW-1):0] gppn; - logic [2:0] v_st_enbl; + logic [HYP_EXT*2:0] v_st_enbl; + logic [TLB_ENTRIES-1:0] napot_tag_match; + pte_cva6_t patched_pte; + logic [TLB_ENTRIES-1:0] vpn0_napot_match; assign v_st_enbl = (CVA6Cfg.RVH) ? {v_i, g_st_enbl_i, s_st_enbl_i} : '1; //------------- // Translation //------------- - genvar i, x, z, w; + genvar i_gen, x_gen, z_gen, w_gen; generate - for (i = 0; i < TLB_ENTRIES; i++) begin - for (x = 0; x < CVA6Cfg.PtLevels; x++) begin - //identify page_match for all TLB Entries - assign page_match[i][x] = x==0 ? 1 :((HYP_EXT==0 || x==(CVA6Cfg.PtLevels-1)) ? // PAGE_MATCH CONTAINS THE MATCH INFORMATION FOR EACH TAG OF is_1G and is_2M in sv39x4. HIGHER LEVEL (Giga page), THEN THERE IS THE Mega page AND AT THE LOWER LEVEL IS ALWAYS 1 - &(tags_q[i].is_page[CVA6Cfg.PtLevels-1-x] | (~v_st_enbl[HYP_EXT:0])): - ((&v_st_enbl[HYP_EXT:0]) ? - ((tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][0] && (tags_q[i].is_page[CVA6Cfg.PtLevels-2-x][HYP_EXT] || tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT])) - || (tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT] && (tags_q[i].is_page[CVA6Cfg.PtLevels-2-x][0] || tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][0]))): - tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][0] && s_st_enbl_i || tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][HYP_EXT] && g_st_enbl_i)); - - //identify if vpn matches at all PT levels for all TLB entries - assign vpn_match[i][x] = (CVA6Cfg.RVH && x == (CVA6Cfg.PtLevels - 1) && ~s_st_enbl_i) ? // - lu_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x)] == tags_q[i].vpn[x] && lu_vaddr_i[12+HYP_EXT*(CVA6Cfg.VpnLen-1): 12+HYP_EXT*(CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels))] == tags_q[i].vpn[x+HYP_EXT][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-HYP_EXT:0]: // - lu_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x)] == tags_q[i].vpn[x]; - - //identify if there is a hit at each PT level for all TLB entries - assign level_match[i][x] = &vpn_match[i][CVA6Cfg.PtLevels-1:x] && page_match[i][x]; - - //identify vpage_match for all TLB Entries and vaddr_level match (if there is a hit at each PT level for all TLB entries on the vaddr) - for (z = 0; z < HYP_EXT + 1; z++) begin - assign vpage_match[i][z][x] = x == 0 ? 1 : tags_q[i].is_page[CVA6Cfg.PtLevels-1-x][z]; - assign vaddr_level_match[i][z][x]= &vaddr_vpn_match[i][z][CVA6Cfg.PtLevels-1:x] && vpage_match[i][z][x]; + for (i_gen = 0; i_gen < TLB_ENTRIES; i_gen++) begin + for (x_gen = 0; x_gen < CVA6Cfg.PtLevels; x_gen++) begin + // WARNING: `x` goes in the order {0 = 4K, 1 = 2M, 2 = 1G}. + + // Identify page_match for all TLB Entries: + // `page_match[i][x] == 1` if the entry `i` represents a page of (non-strictly) bigger length than + // requested. + // 4K is always a match + // In case of H-mode, the length of a page in the TLB is the smallest of S-translation and + // G-translation + if (x_gen == 0) begin + assign page_match[i_gen][x_gen] = 1; + end else begin + if (HYP_EXT == 0 || x_gen == (CVA6Cfg.PtLevels - 1)) begin + // No H-mode or Giga page. Then both condition must be true: + // - G-stage translation is *not* enabled or G-entry is a matching page (bit 1) + // - S-translation is *not* enabled or S-entry i is a matching page (bit 0) + assign page_match[i_gen][x_gen] = &(tags_q[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][HYP_EXT:0] | (~v_st_enbl[HYP_EXT:0])); + end else begin + // Other cases: H-mode and mega page + assign page_match[i_gen][x_gen] = (&v_st_enbl[HYP_EXT:0]) ? + // If S-translation and G-translation are active, then either: + // - S-translation matches and G-translation is Mega or Giga + // - G-translation matches and S-translation is Mega or Giga + ((tags_q[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][0] && (tags_q[i_gen].is_page[CVA6Cfg.PtLevels-2-x_gen][HYP_EXT] || tags_q[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][HYP_EXT])) + || (tags_q[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][HYP_EXT] && (tags_q[i_gen].is_page[CVA6Cfg.PtLevels-2-x_gen][0] || tags_q[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][0]))) + : // Else, either S or G-level must match depending which is active + ((tags_q[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][0] && s_st_enbl_i) || (tags_q[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][HYP_EXT] && g_st_enbl_i)); + end + end + + // Identify if VPN matches at levels `x` for TLB entry `i` + if (CVA6Cfg.RVH && x_gen == (CVA6Cfg.PtLevels - 1)) begin + // H-mode: extend the check on last level (Giga page) to include the supplementary bits in + // GPA (cfg.GPPNW = 29 bits in Sv39x4, compared to 27 bits in Sv39) + // /!\ Only in cases G-translation is active and not S-translation + assign vpn_match[i_gen][x_gen] = lu_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x_gen+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x_gen)] == tags_q[i_gen].vpn[x_gen] + && (s_st_enbl_i || lu_vaddr_i[12+CVA6Cfg.GPPNW-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x_gen+1))] == tags_q[i_gen].vpn[x_gen+HYP_EXT][(CVA6Cfg.GPPNW%(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels))-1:0]); + + end else begin + // Standard match + assign vpn_match[i_gen][x_gen] = lu_vaddr_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x_gen+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x_gen)] == tags_q[i_gen].vpn[x_gen]; + end + + // Identify if there is a hit at level `x`: VPN and page length must match + assign level_match[i_gen][x_gen] = &vpn_match[i_gen][CVA6Cfg.PtLevels-1:x_gen] && page_match[i_gen][x_gen]; + // Identify `vpage_match` (matching page type) and deduce `vaddr_level` match (hit at all level on the virtual addr to be flushed + // and matching page type). + for (z_gen = 0; z_gen < HYP_EXT + 1; z_gen++) begin + assign vpage_match [i_gen][z_gen][x_gen] = x_gen == 0 ? 1 : tags_q[i_gen].is_page[CVA6Cfg.PtLevels-1-x_gen][z_gen]; + assign vaddr_level_match[i_gen][z_gen][x_gen] = &vaddr_vpn_match[i_gen][z_gen][CVA6Cfg.PtLevels-1:x_gen] && vpage_match[i_gen][z_gen][x_gen]; end - //identify if virtual address vpn matches at all PT levels for all TLB entries - assign vaddr_vpn_match[i][0][x] = vaddr_to_be_flushed_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x)] == tags_q[i].vpn[x]; + // Identify if virtual address vpn matches at all PT levels for all TLB entries + assign vaddr_vpn_match[i_gen][0][x_gen] = vaddr_to_be_flushed_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x_gen+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x_gen)] == tags_q[i_gen].vpn[x_gen]; end - + // Identify if the input virtual address matches a stored NAPOT tag + assign vpn0_napot_match[i_gen] = lu_vaddr_i[12 + (CVA6Cfg.VpnLen / CVA6Cfg.PtLevels) - 1 : 16] == tags_q[i_gen].vpn[0][(CVA6Cfg.VpnLen / CVA6Cfg.PtLevels)-1 : 4]; + assign napot_tag_match[i_gen] = (CVA6Cfg.SvnapotEn && tags_q[i_gen].is_napot_64k) ? vpn_match[i_gen][2] && vpn_match[i_gen][1] && vpn0_napot_match[i_gen] : 1'b0; if (CVA6Cfg.RVH) begin - //identify if GPADDR matches the GPPN - assign vaddr_vpn_match[i][HYP_EXT][0] = (gpaddr_to_be_flushed_i[20:12] == gppn[i][8:0]); - assign vaddr_vpn_match[i][HYP_EXT][HYP_EXT] = (gpaddr_to_be_flushed_i[29:21] == gppn[i][17:9]); - assign vaddr_vpn_match[i][HYP_EXT][HYP_EXT*2] = (gpaddr_to_be_flushed_i[30+GPPN2:30] == gppn[i][18+GPPN2:18]); - + for (x_gen = 0; x_gen < CVA6Cfg.PtLevels; x_gen++) begin + // Identify if GPADDR matches the GPPN + assign vaddr_vpn_match[i_gen][HYP_EXT][x_gen] = gpaddr_to_be_flushed_i[12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x_gen+1))-1:12+((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x_gen)] == + gppn[i_gen][ (CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*(x_gen+1)-1 : (CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)*x_gen]; + end end - for (w = 0; w < CVA6Cfg.PtLevels - 1; w++) begin - assign is_page_o[i][w] = page_match[i][CVA6Cfg.PtLevels - 1 - w]; //THIS REORGANIZES THE PAGES TO MATCH THE OUTPUT STRUCTURE (2M,1G) + // Reorganise the output structure to match `is_page` tag order: [1G, 2M] + for (w_gen = 0; w_gen < CVA6Cfg.PtLevels - 1; w_gen++) begin + assign is_page_o[i_gen][w_gen] = page_match[i_gen][CVA6Cfg.PtLevels-1-w_gen]; end end endgenerate @@ -156,7 +196,7 @@ module cva6_tlb lu_gpaddr_o = '{default: 0}; for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin - // first level match, this may be a giga page, check the ASID flags as well + // First level match, this may be a giga page, check the ASID flags as well // if the entry is associated to a global address, don't match the ASID (ASID is don't care) match_asid[i] = ((lu_asid_i == tags_q[i].asid || content_q[i].pte.g) && s_st_enbl_i) || !s_st_enbl_i; @@ -164,30 +204,64 @@ module cva6_tlb match_vmid[i] = (lu_vmid_i == tags_q[i].vmid && g_st_enbl_i) || !g_st_enbl_i; end - // check if translation is a: S-Stage and G-Stage, S-Stage only or G-Stage only translation and virtualization mode is on/off + // Check if that S-stage and G-stage modes corresponds, and that + // and virtualization mode is on/off match_stage[i] = tags_q[i].v_st_enbl[HYP_EXT*2:0] == v_st_enbl[HYP_EXT*2:0]; - if (tags_q[i].valid && match_asid[i] && match_vmid[i] && match_stage[i]) begin - - if (CVA6Cfg.RVH && vpn_match[i][HYP_EXT*2]) begin + // There was a match, i.e.: + // - tag is valid + // - asid matches + // - vmid matches + // - virtualisations / S-stage / G-stage matches + // - there exists a PT level for which and entry exists and corresponding VPN(s) match + if (tags_q[i].valid && match_asid[i] && match_vmid[i] && match_stage[i] && (|level_match[i] || napot_tag_match[i])) begin + lu_is_page_o = is_page_o[i]; + lu_content_o = content_q[i].pte; + lu_hit_o = 1'b1; + lu_hit[i] = 1'b1; + // Translate S-stage to GPA: use `content_q[i].pte` to get PPN and use offset + // from input `lu_vaddr_i`. In case of mega/giga pages, PTE PPN must be aligned, + // so we should not overwrite any useful bits. + if (CVA6Cfg.RVH) begin if (s_st_enbl_i) begin + // S-stage Normal page lu_gpaddr_o = {content_q[i].pte.ppn[(CVA6Cfg.GPPNW-1):0], lu_vaddr_i[11:0]}; - // Giga page + // S-stage Mega page + if (tags_q[i].is_page[1][0]) + lu_gpaddr_o[12+(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:12] = lu_vaddr_i[12+(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:12]; + // S-stage Giga page if (tags_q[i].is_page[0][0]) - lu_gpaddr_o[12+2*CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:12] = lu_vaddr_i[12+2*CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:12]; - // Mega page - if (tags_q[i].is_page[HYP_EXT][0]) - lu_gpaddr_o[12+CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:12] = lu_vaddr_i[12+CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:12]; + lu_gpaddr_o[12+2*(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:12] = lu_vaddr_i[12+2*(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:12]; end else begin - lu_gpaddr_o =CVA6Cfg.GPLEN'(lu_vaddr_i[(CVA6Cfg.XLEN == 32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0]); + lu_gpaddr_o = CVA6Cfg.GPLEN'(lu_vaddr_i[(CVA6Cfg.IS_XLEN32 ? CVA6Cfg.VLEN:CVA6Cfg.GPLEN)-1:0]); end - end - if (|level_match[i]) begin + // G-translation (if requested), depending on `content[i].gpte` page type + if (g_st_enbl_i) begin + // Compute G-Stage PPN based on the GPA + // in case of mega/giga pages, GPTE PPN must be aligned so + // here again, we should not overwrite useful bits. + lu_g_content_o = content_q[i].gpte; + // Mega page + if (tags_q[i].is_page[1][HYP_EXT]) + lu_g_content_o.ppn[(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] = lu_gpaddr_o[12+(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:12]; + // Giga page + if (tags_q[i].is_page[0][HYP_EXT]) + lu_g_content_o.ppn[2*(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] = lu_gpaddr_o[12+2*(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:12]; + end + end + if (|level_match[i] || napot_tag_match[i]) begin lu_is_page_o = is_page_o[i]; - lu_content_o = content_q[i].pte; lu_hit_o = 1'b1; lu_hit[i] = 1'b1; + // Patch the PPN on every TLB hit if this entry is a 64 KiB Svnapot page + if (tags_q[i].is_napot_64k && CVA6Cfg.SvnapotEn) begin + patched_pte = content_q[i].pte; + patched_pte.ppn[3:0] = lu_vaddr_i[15:12]; + lu_content_o = patched_pte; + end else begin + lu_content_o = content_q[i].pte; + end if (CVA6Cfg.RVH) begin // Compute G-Stage PPN based on the gpaddr @@ -202,10 +276,16 @@ module cva6_tlb end end - logic [HYP_EXT:0]asid_to_be_flushed_is0; // indicates that the ASID provided by SFENCE.VMA (rs2)is 0, active high - logic [HYP_EXT:0] vaddr_to_be_flushed_is0; // indicates that the VADDR provided by SFENCE.VMA (rs1)is 0, active high + logic [HYP_EXT:0] asid_to_be_flushed_is0; // indicates that the ASID provided by SFENCE.VMA (rs2) is 0, active high + logic [HYP_EXT:0] vaddr_to_be_flushed_is0; // indicates that the VADDR provided by SFENCE.VMA (rs1) is 0, active high logic vmid_to_be_flushed_is0; // indicates that the VMID provided is 0, active high logic gpaddr_to_be_flushed_is0; // indicates that the GPADDR provided is 0, active high + logic flush_addr_napot_match; + logic flush_addr_matches; + logic [CVA6Cfg.VpnLen-1:0] temp_stored_vpn; + logic [CVA6Cfg.VpnLen-1:0] flush_vpn_masked; + logic [CVA6Cfg.VpnLen-1:0] stored_vpn_masked; + logic [CVA6Cfg.VpnLen-1:0] vpn_to_store; assign asid_to_be_flushed_is0 = ~(|asid_to_be_flushed_i); assign vaddr_to_be_flushed_is0 = ~(|vaddr_to_be_flushed_i); @@ -226,17 +306,27 @@ module cva6_tlb if (tags_q[i].v_st_enbl[0]) begin gppn[i] = content_q[i].pte.ppn[(CVA6Cfg.GPPNW-1):0]; - if (tags_q[i].is_page[HYP_EXT][0]) + // Mega Page + if (tags_q[i].is_page[1][0]) gppn[i][CVA6Cfg.VpnLen/CVA6Cfg.PtLevels-1:0] = tags_q[i].vpn[0]; + // Giga Page if (tags_q[i].is_page[0][0]) - gppn[i][2*(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] = { - tags_q[i].vpn[HYP_EXT], tags_q[i].vpn[0] - }; + gppn[i][2*(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] = {tags_q[i].vpn[1], tags_q[i].vpn[0]}; end else begin gppn[i][CVA6Cfg.VpnLen-1:0] = CVA6Cfg.VpnLen'(tags_q[i].vpn); end end + if (tags_q[i].is_napot_64k && CVA6Cfg.SvnapotEn) begin + temp_stored_vpn = {tags_q[i].vpn[2], tags_q[i].vpn[1], tags_q[i].vpn[0]}; + // Mask the lower 4 bits of the VPN (addr[15:12]) for comparison + flush_vpn_masked = vaddr_to_be_flushed_i[CVA6Cfg.VpnLen+11:12] & ~'hF; + stored_vpn_masked = temp_stored_vpn & ~'hF; + flush_addr_napot_match = (flush_vpn_masked == stored_vpn_masked); + end else begin + flush_addr_napot_match = 1'b0; + end + flush_addr_matches = |vaddr_level_match[i][0] || flush_addr_napot_match; if (flush_i) begin if (!tags_q[i].v_st_enbl[HYP_EXT*2] || HYP_EXT == 0) begin @@ -244,10 +334,10 @@ module cva6_tlb // flush everything if ASID is 0 and vaddr is 0 ("SFENCE.VMA x0 x0" case) if (asid_to_be_flushed_is0 && vaddr_to_be_flushed_is0) tags_n[i].valid = 1'b0; // flush vaddr in all addressing space ("SFENCE.VMA vaddr x0" case), it should happen only for leaf pages - else if (asid_to_be_flushed_is0 && (|vaddr_level_match[i][0] ) && (~vaddr_to_be_flushed_is0)) + else if (asid_to_be_flushed_is0 && (flush_addr_matches) && (~vaddr_to_be_flushed_is0)) tags_n[i].valid = 1'b0; // the entry is flushed if it's not global and asid and vaddr both matches with the entry to be flushed ("SFENCE.VMA vaddr asid" case) - else if ((!content_q[i].pte.g) && (|vaddr_level_match[i][0]) && (asid_to_be_flushed_i == tags_q[i].asid ) && (!vaddr_to_be_flushed_is0) && (!asid_to_be_flushed_is0)) + else if ((!content_q[i].pte.g) && (flush_addr_matches) && (asid_to_be_flushed_i == tags_q[i].asid ) && (!vaddr_to_be_flushed_is0) && (!asid_to_be_flushed_is0)) tags_n[i].valid = 1'b0; // the entry is flushed if it's not global, and the asid matches and vaddr is 0. ("SFENCE.VMA 0 asid" case) else if ((!content_q[i].pte.g) && (vaddr_to_be_flushed_is0) && (asid_to_be_flushed_i == tags_q[i].asid ) && (!asid_to_be_flushed_is0)) @@ -260,10 +350,10 @@ module cva6_tlb if (asid_to_be_flushed_is0 && vaddr_to_be_flushed_is0 && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) tags_n[i].valid = 1'b0; // flush vaddr in all addressing space if current VMID matches ("SFENCE.VMA/HFENCE.VVMA vaddr x0" case), it should happen only for leaf pages - else if (asid_to_be_flushed_is0 && (|vaddr_level_match[i][0]) && (~vaddr_to_be_flushed_is0) && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) + else if (asid_to_be_flushed_is0 && (flush_addr_matches) && (~vaddr_to_be_flushed_is0) && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) tags_n[i].valid = 1'b0; // the entry is flushed if it's not global and asid and vaddr and current VMID matches with the entry to be flushed ("SFENCE.VMA/HFENCE.VVMA vaddr asid" case) - else if ((!content_q[i].pte.g) && (|vaddr_level_match[i][0]) && (asid_to_be_flushed_i == tags_q[i].asid && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) && (!vaddr_to_be_flushed_is0) && (!asid_to_be_flushed_is0)) + else if ((!content_q[i].pte.g) && (flush_addr_matches) && (asid_to_be_flushed_i == tags_q[i].asid && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) && (!vaddr_to_be_flushed_is0) && (!asid_to_be_flushed_is0)) tags_n[i].valid = 1'b0; // the entry is flushed if it's not global, and the asid and the current VMID matches and vaddr is 0. ("SFENCE.VMA/HFENCE.VVMA 0 asid" case) else if ((!content_q[i].pte.g) && (vaddr_to_be_flushed_is0) && (asid_to_be_flushed_i == tags_q[i].asid && ((tags_q[i].v_st_enbl[HYP_EXT] && lu_vmid_i == tags_q[i].vmid) || !tags_q[i].v_st_enbl[HYP_EXT])) && (!asid_to_be_flushed_is0)) @@ -275,9 +365,9 @@ module cva6_tlb // flush everything if vmid is 0 and addr is 0 ("HFENCE.GVMA x0 x0" case) if (vmid_to_be_flushed_is0 && gpaddr_to_be_flushed_is0) tags_n[i].valid = 1'b0; // flush gpaddr in all addressing space ("HFENCE.GVMA gpaddr x0" case), it should happen only for leaf pages - else if (vmid_to_be_flushed_is0 && (|vaddr_level_match[i][HYP_EXT] ) && (~gpaddr_to_be_flushed_is0)) + else if (vmid_to_be_flushed_is0 && (|vaddr_level_match[i][HYP_EXT]) && (~gpaddr_to_be_flushed_is0)) tags_n[i].valid = 1'b0; - // the entry vmid and gpaddr both matches with the entry to be flushed ("HFENCE.GVMA gpaddr vmid" case) + // the entry vmid and gpaddr both match with the entry to be flushed ("HFENCE.GVMA gpaddr vmid" case) else if ((|vaddr_level_match[i][HYP_EXT]) && (vmid_to_be_flushed_i == tags_q[i].vmid) && (~gpaddr_to_be_flushed_is0) && (~vmid_to_be_flushed_is0)) tags_n[i].valid = 1'b0; // the entry is flushed if the vmid matches and gpaddr is 0. ("HFENCE.GVMA 0 vmid" case) @@ -286,14 +376,22 @@ module cva6_tlb end // normal replacement end else if (update_i.valid & replace_en[i] & !lu_hit_o) begin + vpn_to_store = update_i.vpn; + if (update_i.is_napot_64k && CVA6Cfg.SvnapotEn) begin + // Svnapot: For a NAPOT entry, normalize the VPN by clearing the lower bits before storage + // This ensures that any address within the 64KiB range will match the same stored tag + vpn_to_store[3:0] = 4'b0; + end //update tag tags_n[i] = { update_i.asid, update_i.vmid, - ((CVA6Cfg.PtLevels + HYP_EXT) * (CVA6Cfg.VpnLen / CVA6Cfg.PtLevels))'(update_i.vpn), + // Zero-extended VPN to fit the tag width + ((CVA6Cfg.PtLevels + HYP_EXT) * (CVA6Cfg.VpnLen / CVA6Cfg.PtLevels))'(vpn_to_store), update_i.is_page, update_i.v_st_enbl, - 1'b1 + 1'b1, + CVA6Cfg.SvnapotEn ? update_i.is_napot_64k : 1'b0 // Svnapot: Propagate the NAPOT flag into the TLB entry }; // update content as well content_n[i].pte = update_i.content; @@ -311,27 +409,27 @@ module cva6_tlb // The PLRU-tree indexing: // lvl0 0 // / \ -// / \ -// lvl1 1 2 -// / \ / \ -// lvl2 3 4 5 6 -// / \ /\/\ /\ -// ... ... ... ... -// Just predefine which nodes will be set/cleared -// E.g. for a TLB with 8 entries, the for-loop is semantically -// equivalent to the following pseudo-code: -// unique case (1'b1) -// lu_hit[7]: plru_tree_n[0, 2, 6] = {1, 1, 1}; -// lu_hit[6]: plru_tree_n[0, 2, 6] = {1, 1, 0}; -// lu_hit[5]: plru_tree_n[0, 2, 5] = {1, 0, 1}; -// lu_hit[4]: plru_tree_n[0, 2, 5] = {1, 0, 0}; -// lu_hit[3]: plru_tree_n[0, 1, 4] = {0, 1, 1}; -// lu_hit[2]: plru_tree_n[0, 1, 4] = {0, 1, 0}; -// lu_hit[1]: plru_tree_n[0, 1, 3] = {0, 0, 1}; -// lu_hit[0]: plru_tree_n[0, 1, 3] = {0, 0, 0}; -// default: begin /* No hit */ end -// endcase -for ( + // / \ + // lvl1 1 2 + // / \ / \ + // lvl2 3 4 5 6 + // / \ /\/\ /\ + // ... ... ... ... + // Just predefine which nodes will be set/cleared + // E.g. for a TLB with 8 entries, the for-loop is semantically + // equivalent to the following pseudo-code: + // unique case (1'b1) + // lu_hit[7]: plru_tree_n[0, 2, 6] = {1, 1, 1}; + // lu_hit[6]: plru_tree_n[0, 2, 6] = {1, 1, 0}; + // lu_hit[5]: plru_tree_n[0, 2, 5] = {1, 0, 1}; + // lu_hit[4]: plru_tree_n[0, 2, 5] = {1, 0, 0}; + // lu_hit[3]: plru_tree_n[0, 1, 4] = {0, 1, 1}; + // lu_hit[2]: plru_tree_n[0, 1, 4] = {0, 1, 0}; + // lu_hit[1]: plru_tree_n[0, 1, 3] = {0, 0, 1}; + // lu_hit[0]: plru_tree_n[0, 1, 3] = {0, 0, 0}; + // default: begin /* No hit */ end + // endcase + for ( int unsigned i = 0; i < TLB_ENTRIES; i++ ) begin automatic int unsigned idx_base, shift, new_index; diff --git a/core/cva6_mmu/xsim.dir/work/work.rlx b/core/cva6_mmu/xsim.dir/work/work.rlx new file mode 100644 index 00000000000..eef64dcee9e --- /dev/null +++ b/core/cva6_mmu/xsim.dir/work/work.rlx @@ -0,0 +1,5 @@ +0.7 +2020.2 +May 22 2024 +18:54:44 +/tmp/nvim.derumigny/J8Bv2a/1/cva6_mmu.sv,1748272014,systemVerilog,,,,,,,,,,,, diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv index 4b4f863e4d5..f6b1ec549fd 100644 --- a/core/cva6_rvfi.sv +++ b/core/cva6_rvfi.sv @@ -17,7 +17,8 @@ module cva6_rvfi parameter type rvfi_csr_t = logic, parameter type rvfi_probes_instr_t = logic, parameter type rvfi_probes_csr_t = logic, - parameter type rvfi_probes_t = logic + parameter type rvfi_probes_t = logic, + parameter type rvfi_to_iti_t = logic ) ( @@ -26,8 +27,8 @@ module cva6_rvfi input rvfi_probes_t rvfi_probes_i, output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr_o, + output rvfi_to_iti_t rvfi_to_iti_o, output rvfi_csr_t rvfi_csr_o - ); localparam logic [CVA6Cfg.XLEN-1:0] IsaCode = @@ -44,10 +45,186 @@ module cva6_rvfi | (CVA6Cfg.XLEN'(CVA6Cfg.RVU) << 20) // U - User mode implemented | (CVA6Cfg.XLEN'(CVA6Cfg.RVV) << 21) // V - Vector extension | (CVA6Cfg.XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present - | ((CVA6Cfg.XLEN == 64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL + | ((CVA6Cfg.IS_XLEN64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL localparam logic [CVA6Cfg.XLEN-1:0] hart_id_i = '0; + // Function to compute AMO write value for RVFI logging + // This mirrors the AMO ALU behaviour so the tracer sees the value actually written + // back to memory. This is post-alignment data (lower bytes contain the payload) so + // the tracer can rotate it using the write mask and address offset. + function automatic logic [CVA6Cfg.XLEN-1:0] compute_amo_wdata( + input fu_op amo_op, input logic [CVA6Cfg.XLEN-1:0] mem_old_val, + input logic [CVA6Cfg.XLEN-1:0] reg_val); + ariane_pkg::amo_t amo_kind; + logic is_word_op; + logic [63:0] operand_a_sext, operand_b_sext; + logic [63:0] operand_a_zext, operand_b_zext; + logic [63:0] result64; + logic [64:0] adder_operand_a, adder_operand_b, adder_sum; + + // Decode functional unit opcode into AMO class and width information + amo_kind = AMO_NONE; + is_word_op = 1'b0; + unique case (amo_op) + AMO_LRW: begin + amo_kind = AMO_LR; + is_word_op = 1'b1; + end + AMO_LRD: begin + amo_kind = AMO_LR; + is_word_op = 1'b0; + end + AMO_SCW: begin + amo_kind = AMO_SC; + is_word_op = 1'b1; + end + AMO_SCD: begin + amo_kind = AMO_SC; + is_word_op = 1'b0; + end + AMO_SWAPW: begin + amo_kind = AMO_SWAP; + is_word_op = 1'b1; + end + AMO_SWAPD: begin + amo_kind = AMO_SWAP; + is_word_op = 1'b0; + end + AMO_ADDW: begin + amo_kind = AMO_ADD; + is_word_op = 1'b1; + end + AMO_ADDD: begin + amo_kind = AMO_ADD; + is_word_op = 1'b0; + end + AMO_ANDW: begin + amo_kind = AMO_AND; + is_word_op = 1'b1; + end + AMO_ANDD: begin + amo_kind = AMO_AND; + is_word_op = 1'b0; + end + AMO_ORW: begin + amo_kind = AMO_OR; + is_word_op = 1'b1; + end + AMO_ORD: begin + amo_kind = AMO_OR; + is_word_op = 1'b0; + end + AMO_XORW: begin + amo_kind = AMO_XOR; + is_word_op = 1'b1; + end + AMO_XORD: begin + amo_kind = AMO_XOR; + is_word_op = 1'b0; + end + AMO_MAXW: begin + amo_kind = AMO_MAX; + is_word_op = 1'b1; + end + AMO_MAXD: begin + amo_kind = AMO_MAX; + is_word_op = 1'b0; + end + AMO_MAXWU: begin + amo_kind = AMO_MAXU; + is_word_op = 1'b1; + end + AMO_MAXDU: begin + amo_kind = AMO_MAXU; + is_word_op = 1'b0; + end + AMO_MINW: begin + amo_kind = AMO_MIN; + is_word_op = 1'b1; + end + AMO_MIND: begin + amo_kind = AMO_MIN; + is_word_op = 1'b0; + end + AMO_MINWU: begin + amo_kind = AMO_MINU; + is_word_op = 1'b1; + end + AMO_MINDU: begin + amo_kind = AMO_MINU; + is_word_op = 1'b0; + end + default: begin + amo_kind = AMO_NONE; + is_word_op = 1'b0; + end + endcase + + // Create signed and unsigned 64-bit views of the operands (word ops use 32-bit payloads) + if (is_word_op) begin + operand_a_sext = {{32{mem_old_val[31]}}, mem_old_val[31:0]}; + operand_b_sext = {{32{reg_val[31]}}, reg_val[31:0]}; + operand_a_zext = {32'b0, mem_old_val[31:0]}; + operand_b_zext = {32'b0, reg_val[31:0]}; + end else begin + operand_a_sext = $signed(mem_old_val); + operand_b_sext = $signed(reg_val); + operand_a_zext = $unsigned(mem_old_val); + operand_b_zext = $unsigned(reg_val); + end + + // Default to returning the register operand (SWAP/SC path) + result64 = operand_b_zext; + adder_operand_a = {operand_a_sext[63], operand_a_sext}; + adder_operand_b = {operand_b_sext[63], operand_b_sext}; + adder_sum = '0; + + unique case (amo_kind) + AMO_SC, AMO_SWAP: begin + result64 = operand_b_zext; + end + AMO_ADD: begin + adder_sum = adder_operand_a + adder_operand_b; + result64 = adder_sum[63:0]; + end + AMO_AND: result64 = operand_a_zext & operand_b_zext; + AMO_OR: result64 = operand_a_zext | operand_b_zext; + AMO_XOR: result64 = operand_a_zext ^ operand_b_zext; + AMO_MAX: begin + adder_operand_b = -{operand_b_sext[63], operand_b_sext}; + adder_sum = adder_operand_a + adder_operand_b; + result64 = adder_sum[64] ? operand_b_zext : operand_a_zext; + end + AMO_MIN: begin + adder_operand_b = -{operand_b_sext[63], operand_b_sext}; + adder_sum = adder_operand_a + adder_operand_b; + result64 = adder_sum[64] ? operand_a_zext : operand_b_zext; + end + AMO_MAXU: begin + adder_operand_a = {1'b0, operand_a_zext}; + adder_operand_b = -{1'b0, operand_b_zext}; + adder_sum = adder_operand_a + adder_operand_b; + result64 = adder_sum[64] ? operand_b_zext : operand_a_zext; + end + AMO_MINU: begin + adder_operand_a = {1'b0, operand_a_zext}; + adder_operand_b = -{1'b0, operand_b_zext}; + adder_sum = adder_operand_a + adder_operand_b; + result64 = adder_sum[64] ? operand_a_zext : operand_b_zext; + end + default: begin + result64 = operand_b_zext; + end + endcase + + if (is_word_op) begin + return {{CVA6Cfg.XLEN - 32{1'b0}}, result64[31:0]}; + end else begin + return result64[CVA6Cfg.XLEN-1:0]; + end + endfunction + localparam logic [63:0] SMODE_STATUS_READ_MASK = ariane_pkg::smode_status_read_mask(CVA6Cfg); logic flush; @@ -81,6 +258,14 @@ module cva6_rvfi logic [CVA6Cfg.XLEN-1:0] ex_commit_cause; logic ex_commit_valid; + logic [CVA6Cfg.NrCommitPorts-1:0] valid_iti; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.VLEN-1:0] pc_iti; + ariane_pkg::fu_op [CVA6Cfg.NrCommitPorts-1:0] op_iti; + logic branch_valid_iti; + logic is_taken_iti; + logic [CVA6Cfg.XLEN-1:0] tval_iti; + logic [63:0] time_iti; + riscv::priv_lvl_t priv_lvl; logic [CVA6Cfg.VLEN-1:0] lsu_ctrl_vaddr; @@ -99,6 +284,8 @@ module cva6_rvfi logic [(CVA6Cfg.XLEN/8)-1:0] lsu_wmask; logic [CVA6Cfg.TRANS_ID_BITS-1:0] lsu_addr_trans_id; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] branch_trans_id; + riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d; rvfi_probes_csr_t csr; @@ -147,6 +334,14 @@ module cva6_rvfi assign ex_commit_cause = instr.ex_commit_cause; assign ex_commit_valid = instr.ex_commit_valid; + assign valid_iti = instr.commit_ack; + assign pc_iti = instr.commit_instr_pc; + assign op_iti = instr.commit_instr_op; + assign branch_valid_iti = instr.branch_valid; + assign is_taken_iti = instr.is_taken; + assign tval_iti = instr.tval; + assign time_iti = csr.cycle_q; + assign priv_lvl = instr.priv_lvl; assign wbdata = instr.wbdata; @@ -159,6 +354,8 @@ module cva6_rvfi assign lsu_rmask = instr.lsu_ctrl_fu == LOAD ? instr.lsu_ctrl_be : '0; assign lsu_wmask = instr.lsu_ctrl_fu == STORE ? instr.lsu_ctrl_be : '0; assign lsu_addr_trans_id = instr.lsu_ctrl_trans_id; + assign branch_trans_id = instr.branch_trans_id; + //ID STAGE @@ -170,6 +367,7 @@ module cva6_rvfi typedef struct packed { logic valid; logic [31:0] instr; + logic is_compressed; } issue_struct_t; issue_struct_t [CVA6Cfg.NrIssuePorts-1:0] issue_n, issue_q; logic took0; @@ -187,6 +385,7 @@ module cva6_rvfi if (!issue_n[CVA6Cfg.NrIssuePorts-1].valid) begin issue_n[CVA6Cfg.NrIssuePorts-1].valid = fetch_entry_valid[0]; issue_n[CVA6Cfg.NrIssuePorts-1].instr = truncated[0]; + issue_n[CVA6Cfg.NrIssuePorts-1].is_compressed = is_compressed[0]; took0 = 1'b1; end @@ -199,9 +398,11 @@ module cva6_rvfi if (took0) begin issue_n[CVA6Cfg.NrIssuePorts-1].valid = fetch_entry_valid[CVA6Cfg.NrIssuePorts-1]; issue_n[CVA6Cfg.NrIssuePorts-1].instr = truncated[CVA6Cfg.NrIssuePorts-1]; + issue_n[CVA6Cfg.NrIssuePorts-1].is_compressed = is_compressed[CVA6Cfg.NrIssuePorts-1]; end else begin issue_n[CVA6Cfg.NrIssuePorts-1].valid = fetch_entry_valid[0]; issue_n[CVA6Cfg.NrIssuePorts-1].instr = truncated[0]; + issue_n[CVA6Cfg.NrIssuePorts-1].is_compressed = is_compressed[0]; end end @@ -231,6 +432,9 @@ module cva6_rvfi logic [(CVA6Cfg.XLEN/8)-1:0] lsu_wmask; logic [CVA6Cfg.XLEN-1:0] lsu_wdata; logic [31:0] instr; + logic branch_valid; + logic is_taken; + logic is_compressed; } sb_mem_t; sb_mem_t [CVA6Cfg.NR_SB_ENTRIES-1:0] mem_q, mem_n; @@ -246,11 +450,17 @@ module cva6_rvfi lsu_rmask: '0, lsu_wmask: '0, lsu_wdata: '0, - instr: issue_q[i].instr + instr: issue_q[i].instr, + branch_valid: 1'b0, + is_taken: 1'b0, + is_compressed: issue_q[i].is_compressed }; end end - + if (branch_valid_iti) begin + mem_n[branch_trans_id].branch_valid = branch_valid_iti; + mem_n[branch_trans_id].is_taken = is_taken_iti; + end if (lsu_rmask != 0) begin mem_n[lsu_addr_trans_id].lsu_addr = lsu_addr; mem_n[lsu_addr_trans_id].lsu_rmask = lsu_rmask; @@ -300,7 +510,7 @@ module cva6_rvfi rvfi_instr_o[i].cause <= ex_commit_cause; rvfi_instr_o[i].mode <= (CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl; - rvfi_instr_o[i].ixl <= CVA6Cfg.XLEN == 64 ? 2 : 1; + rvfi_instr_o[i].ixl <= CVA6Cfg.IS_XLEN64 ? 2 : 1; rvfi_instr_o[i].rs1_addr <= commit_instr_rs1[i]; rvfi_instr_o[i].rs2_addr <= commit_instr_rs2[i]; rvfi_instr_o[i].rd_addr <= commit_instr_rd[i]; @@ -312,126 +522,146 @@ module cva6_rvfi // So far, only write paddr is reported. TODO: read paddr rvfi_instr_o[i].mem_paddr <= mem_paddr; rvfi_instr_o[i].mem_wmask <= mem_q[commit_pointer[i]].lsu_wmask; - rvfi_instr_o[i].mem_wdata <= mem_q[commit_pointer[i]].lsu_wdata; + + // For AMO operations, compute the actual write value + // Note: AMO operations write a computed value to memory, not the original register value + if (is_amo(commit_instr_op[i])) begin + rvfi_instr_o[i].mem_wdata <= compute_amo_wdata( + commit_instr_op[i], // AMO operation type + wdata[i], // Old memory value (the value returned to rd) + mem_q[commit_pointer[i]].rs2_rdata // Register operand (rs2) + ); + end else begin + rvfi_instr_o[i].mem_wdata <= mem_q[commit_pointer[i]].lsu_wdata; + end + rvfi_instr_o[i].mem_rmask <= mem_q[commit_pointer[i]].lsu_rmask; rvfi_instr_o[i].mem_rdata <= commit_instr_result[i]; rvfi_instr_o[i].rs1_rdata <= mem_q[commit_pointer[i]].rs1_rdata; rvfi_instr_o[i].rs2_rdata <= mem_q[commit_pointer[i]].rs2_rdata; + rvfi_to_iti_o.branch_valid[i] <= mem_q[commit_pointer[i]].branch_valid; + rvfi_to_iti_o.is_taken[i] <= mem_q[commit_pointer[i]].is_taken; + rvfi_to_iti_o.is_compressed[i] <= mem_q[commit_pointer[i]].is_compressed; + rvfi_to_iti_o.valid[i] <= valid_iti[i]; + rvfi_to_iti_o.pc[i] <= pc_iti[i]; + rvfi_to_iti_o.op[i] <= op_iti[i]; end + rvfi_to_iti_o.ex_valid <= ex_commit_valid; + rvfi_to_iti_o.cycles <= time_iti; + rvfi_to_iti_o.cause <= ex_commit_cause; + rvfi_to_iti_o.tval <= tval_iti; + rvfi_to_iti_o.priv_lvl <= priv_lvl; end //---------------------------------------------------------------------------------------------------------- // CSR //---------------------------------------------------------------------------------------------------------- - - `define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, - CSR_SOURCE_NAME) \ - always_ff @(posedge clk_i) begin \ - if (CSR_ENABLE_COND) begin \ - rvfi_csr_o.``CSR_NAME``.rdata <= {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}; \ - end \ - end \ - assign rvfi_csr_o.``CSR_NAME``.wdata = CSR_ENABLE_COND ? { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} } : 0; \ - assign rvfi_csr_o.``CSR_NAME``.rmask = CSR_ENABLE_COND ? 1 : 0; \ - assign rvfi_csr_o.``CSR_NAME``.wmask = (rvfi_csr_o.``CSR_NAME``.rdata != {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}) && CSR_ENABLE_COND; - - `define COMMA , + // Changing verible formating to fix vivado synthesis errors and warnings + // verilog_format: off + `define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, CSR_SOURCE_NAME) \ + always_ff @(posedge clk_i) begin \ + if (CSR_ENABLE_COND) begin \ + rvfi_csr_o.``CSR_NAME``.rdata <= {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}; \ + end \ + end \ + assign rvfi_csr_o.``CSR_NAME``.wdata = CSR_ENABLE_COND ? { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} } : 0; \ + assign rvfi_csr_o.``CSR_NAME``.rmask = CSR_ENABLE_COND ? 1 : 0; \ + assign rvfi_csr_o.``CSR_NAME``.wmask = (rvfi_csr_o.``CSR_NAME``.rdata != {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}) && CSR_ENABLE_COND; `define CONNECT_RVFI_SAME(CSR_ENABLE_COND, CSR_NAME) \ - `CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, csr.``CSR_NAME``_q) + `CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, csr.``CSR_NAME``_q) - `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_q.fflags) - `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_q.frm) - `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, { csr.fcsr_q.frm `COMMA csr.fcsr_q.fflags}) + if ($bits(rvfi_csr_o) != 1) begin + `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_q.fflags) + `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_q.frm) + `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, {csr.fcsr_q.frm, csr.fcsr_q.fflags}) - `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_q.fprec) - `CONNECT_RVFI_SAME(CVA6Cfg.FpPresent, dcsr) + `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_q.fprec) + `CONNECT_RVFI_SAME(CVA6Cfg.FpPresent, dcsr) - `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dpc) + `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dpc) - `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch0) - `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch1) + `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch0) + `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch1) - `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus, - csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus, csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sie, csr.mie_q & csr.mideleg_q) - `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sip, csr.mip_q & csr.mideleg_q) + `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sie, csr.mie_q & csr.mideleg_q) + `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sip, csr.mip_q & csr.mideleg_q) - `CONNECT_RVFI_SAME(CVA6Cfg.RVS, stvec) + `CONNECT_RVFI_SAME(CVA6Cfg.RVS, stvec) - `CONNECT_RVFI_SAME(CVA6Cfg.RVS, scounteren) + `CONNECT_RVFI_SAME(CVA6Cfg.RVS, scounteren) - `CONNECT_RVFI_SAME(CVA6Cfg.RVS, sscratch) - `CONNECT_RVFI_SAME(CVA6Cfg.RVS, sepc) + `CONNECT_RVFI_SAME(CVA6Cfg.RVS, sscratch) + `CONNECT_RVFI_SAME(CVA6Cfg.RVS, sepc) - `CONNECT_RVFI_SAME(CVA6Cfg.RVS, scause) + `CONNECT_RVFI_SAME(CVA6Cfg.RVS, scause) - `CONNECT_RVFI_SAME(CVA6Cfg.RVS, stval) - `CONNECT_RVFI_SAME(CVA6Cfg.RVS, satp) + `CONNECT_RVFI_SAME(CVA6Cfg.RVS, stval) + `CONNECT_RVFI_SAME(CVA6Cfg.RVS, satp) - `CONNECT_RVFI_FULL(1'b1, mstatus, csr.mstatus_extended) + `CONNECT_RVFI_FULL(1'b1, mstatus, csr.mstatus_extended) - bit [31:0] mstatush_q; - `CONNECT_RVFI_FULL(1'b1, mstatush, mstatush_q) + bit [31:0] mstatush_q; + `CONNECT_RVFI_FULL(1'b1, mstatush, mstatush_q) - `CONNECT_RVFI_FULL(1'b1, misa, IsaCode) + `CONNECT_RVFI_FULL(1'b1, misa, IsaCode) - `CONNECT_RVFI_SAME(CVA6Cfg.RVS, medeleg) - `CONNECT_RVFI_SAME(CVA6Cfg.RVS, mideleg) + `CONNECT_RVFI_SAME(CVA6Cfg.RVS, medeleg) + `CONNECT_RVFI_SAME(CVA6Cfg.RVS, mideleg) - `CONNECT_RVFI_SAME(1'b1, mie) - `CONNECT_RVFI_SAME(1'b1, mtvec) - `CONNECT_RVFI_SAME(1'b1, mcounteren) + `CONNECT_RVFI_SAME(1'b1, mie) + `CONNECT_RVFI_SAME(1'b1, mtvec) + `CONNECT_RVFI_SAME(1'b1, mcounteren) - `CONNECT_RVFI_SAME(1'b1, mscratch) + `CONNECT_RVFI_SAME(1'b1, mscratch) - `CONNECT_RVFI_SAME(1'b1, mepc) - `CONNECT_RVFI_SAME(1'b1, mcause) - `CONNECT_RVFI_SAME(1'b1, mtval) - `CONNECT_RVFI_SAME(1'b1, mip) + `CONNECT_RVFI_SAME(1'b1, mepc) + `CONNECT_RVFI_SAME(1'b1, mcause) + `CONNECT_RVFI_SAME(1'b1, mtval) + `CONNECT_RVFI_SAME(1'b1, mip) - `CONNECT_RVFI_FULL(1'b1, menvcfg, csr.fiom_q) + `CONNECT_RVFI_FULL(1'b1, menvcfg, csr.fiom_q) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, menvcfgh, 32'h0) + `CONNECT_RVFI_FULL(CVA6Cfg.IS_XLEN32, menvcfgh, 32'h0) - `CONNECT_RVFI_FULL(1'b1, mvendorid, OPENHWGROUP_MVENDORID) - `CONNECT_RVFI_FULL(1'b1, marchid, ARIANE_MARCHID) - `CONNECT_RVFI_FULL(1'b1, mhartid, hart_id_i) + `CONNECT_RVFI_FULL(1'b1, mvendorid, OPENHWGROUP_MVENDORID) + `CONNECT_RVFI_FULL(1'b1, marchid, ARIANE_MARCHID) + `CONNECT_RVFI_FULL(1'b1, mhartid, hart_id_i) - `CONNECT_RVFI_SAME(1'b1, mcountinhibit) + `CONNECT_RVFI_SAME(1'b1, mcountinhibit) - `CONNECT_RVFI_FULL(1'b1, mcycle, csr.cycle_q[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, mcycleh, csr.cycle_q[63:32]) + `CONNECT_RVFI_FULL(1'b1, mcycle, csr.cycle_q[CVA6Cfg.XLEN-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.IS_XLEN32, mcycleh, csr.cycle_q[63:32]) - `CONNECT_RVFI_FULL(1'b1, minstret, csr.instret_q[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, minstreth, csr.instret_q[63:32]) + `CONNECT_RVFI_FULL(1'b1, minstret, csr.instret_q[CVA6Cfg.XLEN-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.IS_XLEN32, minstreth, csr.instret_q[63:32]) - `CONNECT_RVFI_FULL(1'b1, cycle, csr.cycle_q[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, cycleh, csr.cycle_q[63:32]) + `CONNECT_RVFI_FULL(1'b1, cycle, csr.cycle_q[CVA6Cfg.XLEN-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.IS_XLEN32, cycleh, csr.cycle_q[63:32]) - `CONNECT_RVFI_FULL(1'b1, instret, csr.instret_q[CVA6Cfg.XLEN-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, instreth, csr.instret_q[63:32]) + `CONNECT_RVFI_FULL(1'b1, instret, csr.instret_q[CVA6Cfg.XLEN-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.IS_XLEN32, instreth, csr.instret_q[63:32]) - `CONNECT_RVFI_SAME(1'b1, dcache) - `CONNECT_RVFI_SAME(1'b1, icache) + `CONNECT_RVFI_SAME(1'b1, dcache) + `CONNECT_RVFI_SAME(1'b1, icache) - `CONNECT_RVFI_SAME(CVA6Cfg.EnableAccelerator, acc_cons) - `CONNECT_RVFI_SAME(CVA6Cfg.RVZCMT, jvt) - `CONNECT_RVFI_FULL(1'b1, pmpcfg0, csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg1, csr.pmpcfg_q[7:4]) + `CONNECT_RVFI_SAME(CVA6Cfg.EnableAccelerator, acc_cons) + `CONNECT_RVFI_SAME(CVA6Cfg.RVZCMT, jvt) + `CONNECT_RVFI_FULL(1'b1, pmpcfg0, csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0]) + `CONNECT_RVFI_FULL(CVA6Cfg.IS_XLEN32, pmpcfg1, csr.pmpcfg_q[7:4]) - `CONNECT_RVFI_FULL(1'b1, pmpcfg2, csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8]) - `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg3, csr.pmpcfg_q[15:12]) + `CONNECT_RVFI_FULL(1'b1, pmpcfg2, csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8]) + `CONNECT_RVFI_FULL(CVA6Cfg.IS_XLEN32, pmpcfg3, csr.pmpcfg_q[15:12]) - bit [CVA6Cfg.XLEN-1:0] pmpaddr_q; - genvar i; - generate + bit [CVA6Cfg.XLEN-1:0] pmpaddr_q; + genvar i; for (i = 0; i < 16; i++) begin - `CONNECT_RVFI_FULL(1'b1, pmpaddr[i], csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]) + `CONNECT_RVFI_FULL(1'b1, pmpaddr[i], {csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1], pmpcfg_q[i].addr_mode[1]}) end - endgenerate - ; - + ; + end + // verilog_format: on endmodule diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index 34b865d8d96..fabe18c903d 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -16,6 +16,7 @@ module cva6_rvfi_probes parameter type exception_t = logic, parameter type scoreboard_entry_t = logic, parameter type lsu_ctrl_t = logic, + parameter type bp_resolve_t = logic, parameter type rvfi_probes_instr_t = logic, parameter type rvfi_probes_csr_t = logic, parameter type rvfi_probes_t = logic @@ -52,6 +53,8 @@ module cva6_rvfi_probes input rvfi_probes_csr_t csr_i, input logic [1:0] irq_i, + input bp_resolve_t resolved_branch_i, + input [CVA6Cfg.TRANS_ID_BITS-1:0] flu_trans_id_ex_id_i, output rvfi_probes_t rvfi_probes_o ); @@ -81,6 +84,11 @@ module cva6_rvfi_probes instr.ex_commit_cause = ex_commit_i.cause; instr.ex_commit_valid = ex_commit_i.valid; + if (CVA6Cfg.TvalEn) begin + instr.tval = ex_commit_i.tval; + end else begin + instr.tval = '0; + end instr.priv_lvl = priv_lvl_i; @@ -109,6 +117,10 @@ module cva6_rvfi_probes instr.commit_ack = commit_ack_i; instr.wdata = wdata_i; + instr.branch_valid = resolved_branch_i.valid; + instr.is_taken = resolved_branch_i.is_taken; + instr.branch_trans_id = flu_trans_id_ex_id_i; + csr = csr_i; csr.mip_q = csr_i.mip_q | ({{CVA6Cfg.XLEN - 1{1'b0}}, CVA6Cfg.RVS && irq_i[1]} << riscv::IRQ_S_EXT); diff --git a/core/cvfpu b/core/cvfpu index 3116391bf66..3eb6afeab2c 160000 --- a/core/cvfpu +++ b/core/cvfpu @@ -1 +1 @@ -Subproject commit 3116391bf66660f806b45e212b9949c528b4e270 +Subproject commit 3eb6afeab2cb33f7d8689222955d0171aeb3a801 diff --git a/core/cvxif_fu.sv b/core/cvxif_fu.sv index cf6ee152156..c0186fdc7b9 100644 --- a/core/cvxif_fu.sv +++ b/core/cvxif_fu.sv @@ -22,6 +22,8 @@ module cvxif_fu input logic clk_i, // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, + // Virtualization mode state - CSR_REGFILE + input logic v_i, // CVXIF instruction is valid - ISSUE_STAGE input logic x_valid_i, // Transaction ID - ISSUE_STAGE @@ -54,7 +56,7 @@ module cvxif_fu assign result_ready_o = 1'b1; - assign x_ready_o = 1'b1; // Readyness of cvxif_fu is determined in issue stage by CVXIF issue interface + assign x_ready_o = 1'b1; // Readiness of cvxif_fu is determined in issue stage by CVXIF issue interface // Result signals assign x_valid_o = x_illegal_i || result_valid_i; assign x_result_o = result_i.data; @@ -68,6 +70,10 @@ module cvxif_fu x_exception_o.cause = x_illegal_i ? riscv::ILLEGAL_INSTR : '0; if (CVA6Cfg.TvalEn) x_exception_o.tval = x_off_instr_i; // TODO Optimization : Set exception in IRO. + // Hypervisor exception fields + x_exception_o.tval2 = {CVA6Cfg.GPLEN{1'b0}}; + x_exception_o.tinst = '0; + x_exception_o.gva = 1'b0; end endmodule diff --git a/core/cvxif_issue_register_commit_if_driver.sv b/core/cvxif_issue_register_commit_if_driver.sv index 88efc0002d0..be720a4a5a3 100644 --- a/core/cvxif_issue_register_commit_if_driver.sv +++ b/core/cvxif_issue_register_commit_if_driver.sv @@ -38,8 +38,8 @@ module cvxif_issue_register_commit_if_driver #( input [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0][CVA6Cfg.XLEN-1:0] register_i, input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i ); - // X_ISSUE_REGISTER_SPLIT = 0 : Issue and register transactions are synchrone - // Mandatory assignement + // X_ISSUE_REGISTER_SPLIT = 0 : Issue and register transactions are synchronous + // Mandatory assignment assign register_valid_o = issue_valid_o; assign register_o.hartid = issue_req_o.hartid; assign register_o.id = issue_req_o.id; diff --git a/core/decoder.sv b/core/decoder.sv index de52e7f2325..eed632cb558 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -54,7 +54,7 @@ module decoder input logic [CVA6Cfg.XLEN-1:0] jump_address_i, // Is a branch predict instruction - FRONTEND input branchpredict_sbe_t branch_predict_i, - // If an exception occured in fetch stage - FRONTEND + // If an exception occurred in fetch stage - FRONTEND input exception_t ex_i, // Level sensitive (async) interrupts - SUBSYSTEM input logic [1:0] irq_i, @@ -84,12 +84,26 @@ module decoder input logic tsr_i, // Hypervisor user mode - CSR_REGFILE input logic hu_i, + // machine-mode cache block invalidate enable - CSR_REGFILE + input riscv::cbie_t mcbie_i, + // supervisor-mode cache block invalidate enable - CSR_REGFILE + input riscv::cbie_t scbie_i, + // hypervisor-mode cache block invalidate enable - CSR_REGFILE + input riscv::cbie_t hcbie_i, + // machine-mode clean/flush cache block invalidate enable - CSR_REGFILE + input logic mcbcfe_i, + // supervisor-mode clean/flush cache block invalidate enable - CSR_REGFILE + input logic scbcfe_i, + // hypervisor-mode clean/flush cache block invalidate enable - CSR_REGFILE + input logic hcbcfe_i, // Instruction to be added to scoreboard entry - ISSUE_STAGE output scoreboard_entry_t instruction_o, // Instruction - ISSUE_STAGE output logic [31:0] orig_instr_o, // Is a control flow instruction - ISSUE_STAGE - output logic is_control_flow_instr_o + output logic is_control_flow_instr_o, + // Exception request - TRIGGER MODULE + input logic [CVA6Cfg.XLEN-1:0] sdtrig_decoder_action_i ); logic illegal_instr; logic illegal_instr_bm; @@ -186,6 +200,7 @@ module decoder ecall = 1'b0; ebreak = 1'b0; check_fprm = 1'b0; + tinst = 32'h0; if (~ex_i.valid) begin case (instr.rtype.opcode) @@ -197,7 +212,7 @@ module decoder unique case (instr.itype.funct3) 3'b000: begin - // check if the RD and and RS1 fields are zero, this may be reset for the SENCE.VMA instruction + // check if the RD and and RS1 fields are zero, this may be reset for the SFENCE.VMA instruction if (instr.itype.rs1 != '0 || instr.itype.rd != '0) begin if (CVA6Cfg.RVH && v_i) begin virtual_illegal_instr = 1'b1; @@ -205,7 +220,7 @@ module decoder illegal_instr = 1'b1; end end - // decode the immiediate field + // decode the immediate field case (instr.itype.imm) // ECALL -> inject exception 12'b0: ecall = 1'b1; @@ -286,6 +301,7 @@ module decoder // only if S mode is supported // otherwise decode an illegal instruction if (CVA6Cfg.RVH && v_i) begin + illegal_instr = (instr.itype.rd == '0) ? illegal_instr : 1'b1; virtual_illegal_instr = (priv_lvl_i == riscv::PRIV_LVL_S) ? 1'b0 : 1'b1; end else begin illegal_instr = (CVA6Cfg.RVS && (priv_lvl_i inside {riscv::PRIV_LVL_M, riscv::PRIV_LVL_S}) && instr.itype.rd == '0) ? 1'b0 : 1'b1; @@ -303,7 +319,7 @@ module decoder if (v_i) begin virtual_illegal_instr = 1'b1; end else begin - illegal_instr = (priv_lvl_i inside {riscv::PRIV_LVL_M, riscv::PRIV_LVL_S}) ? 1'b0 : 1'b1; + illegal_instr = ((priv_lvl_i inside {riscv::PRIV_LVL_M, riscv::PRIV_LVL_S}) && instr.itype.rd == '0) ? 1'b0 : 1'b1; end instruction_o.op = ariane_pkg::HFENCE_VVMA; end else if (instr.instr[31:25] == 7'b110001) begin @@ -312,7 +328,7 @@ module decoder if (v_i) begin virtual_illegal_instr = 1'b1; end else begin - illegal_instr = (priv_lvl_i inside {riscv::PRIV_LVL_M, riscv::PRIV_LVL_S}) ? 1'b0 : 1'b1; + illegal_instr = ((priv_lvl_i inside {riscv::PRIV_LVL_M, riscv::PRIV_LVL_S}) && instr.itype.rd == '0) ? 1'b0 : 1'b1; end instruction_o.op = ariane_pkg::HFENCE_GVMA; // check TVM flag and intercept HFENCE.GVMA call if necessary @@ -454,6 +470,85 @@ module decoder 3'b000: instruction_o.op = ariane_pkg::FENCE; // FENCE.I 3'b001: instruction_o.op = ariane_pkg::FENCE_I; + // CBO - optional + 3'b010: begin + if (CVA6Cfg.RVZiCbom) begin + instruction_o.fu = STORE; + instruction_o.rs1[4:0] = instr.itype.rs1; + // not used - zero + instruction_o.rs2[4:0] = '0; + unique case (instr.itype.imm) + // CBO.INVAL + 12'b000000000000: instruction_o.op = ariane_pkg::CBO_INVAL; + // CBO.CLEAN + 12'b000000000001: instruction_o.op = ariane_pkg::CBO_CLEAN; + // CBO.FLUSH + 12'b000000000010: instruction_o.op = ariane_pkg::CBO_FLUSH; + default: illegal_instr = 1'b1; + endcase + + if (instruction_o.op == ariane_pkg::CBO_INVAL) begin + // CBO.INVAL permission checks + if ((priv_lvl_i != riscv::PRIV_LVL_M && + mcbie_i == riscv::CBIE_ILLEGAL) || + (!v_i && CVA6Cfg.RVU && + priv_lvl_i == riscv::PRIV_LVL_U && + scbie_i == riscv::CBIE_ILLEGAL)) begin + illegal_instr = 1'b1; + end else if ( + CVA6Cfg.RVH && v_i && + ((priv_lvl_i == riscv::PRIV_LVL_S && + hcbie_i == riscv::CBIE_ILLEGAL) || + (priv_lvl_i == riscv::PRIV_LVL_U && + (hcbie_i == riscv::CBIE_ILLEGAL || + scbie_i == riscv::CBIE_ILLEGAL)))) begin + virtual_illegal_instr = 1'b1; + end else if ( + (priv_lvl_i != riscv::PRIV_LVL_M && + mcbie_i == riscv::CBIE_FLUSH) || + (!v_i && CVA6Cfg.RVU && + priv_lvl_i == riscv::PRIV_LVL_U && + scbie_i == riscv::CBIE_FLUSH) || + (CVA6Cfg.RVH && v_i && + ((priv_lvl_i == riscv::PRIV_LVL_S && + hcbie_i == riscv::CBIE_FLUSH) || + (priv_lvl_i == riscv::PRIV_LVL_U && + (hcbie_i == riscv::CBIE_FLUSH || + scbie_i == riscv::CBIE_FLUSH))))) begin + // Execute CBO.INVAL as a flush. + instruction_o.op = ariane_pkg::CBO_FLUSH; + end + end + + // CBCFE controls genuine CBO.CLEAN/CBO.FLUSH instructions. + // An original CBO.INVAL remains governed by CBIE even when + // CBIE makes the operation perform a flush. + if ((instruction_o.op inside { + ariane_pkg::CBO_CLEAN, ariane_pkg::CBO_FLUSH + }) && instr.itype.imm != 12'b000000000000) begin + if ((priv_lvl_i != riscv::PRIV_LVL_M && !mcbcfe_i) || + (!v_i && CVA6Cfg.RVU && + priv_lvl_i == riscv::PRIV_LVL_U && !scbcfe_i)) begin + illegal_instr = 1'b1; + end else if ( + CVA6Cfg.RVH && v_i && + ((priv_lvl_i == riscv::PRIV_LVL_S && !hcbcfe_i) || + (priv_lvl_i == riscv::PRIV_LVL_U && + !(hcbcfe_i && scbcfe_i)))) begin + virtual_illegal_instr = 1'b1; + end + end + end else begin + illegal_instr = 1'b1; + end + + if (CVA6Cfg.RVH) begin + tinst = { + instr.itype.imm, 5'b00000, instr.stype.funct3, 5'b00000, instr.stype.opcode + }; + end + end + default: illegal_instr = 1'b1; endcase @@ -466,7 +561,7 @@ module decoder // -------------------------------------------- // Vectorial Floating-Point Reg-Reg Operations // -------------------------------------------- - if (instr.rvftype.funct2 == 2'b10) begin // Prefix 10 for all Xfvec ops + if (!CVA6Cfg.ZKN && instr.rvftype.funct2 == 2'b10) begin // Prefix 10 for all Xfvec ops // only generate decoder if FP extensions are enabled (static) if (CVA6Cfg.FpPresent && CVA6Cfg.XFVec && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin automatic logic allow_replication; // control honoring of replication flag @@ -537,7 +632,7 @@ module decoder 5'b001??: begin instruction_o.op = ariane_pkg::FCVT_F2F; // vfcvt.vfmt.vfmt - Vectorial FP to FP Conversion instruction_o.rs2 = instr.rvftype.rd; // set rs2 = rd as target vector for conversion - imm_select = IIMM; // rs2 holds part of the intruction + imm_select = IIMM; // rs2 holds part of the instruction // TODO CHECK R bit for valid fmt combinations // determine source format unique case (instr.rvftype.rs2[21:20]) @@ -787,6 +882,18 @@ module decoder if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; //packh else illegal_instr_bm = 1'b1; end + { + 7'b001_0100, 3'b100 + } : begin + if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::XPERM8; // xperm8 + else illegal_instr_bm = 1'b1; + end + { + 7'b001_0100, 3'b010 + } : begin + if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::XPERM4; // xperm4 + else illegal_instr_bm = 1'b1; + end // Zero Extend Op RV32 encoding { 7'b000_0100, 3'b100 @@ -796,6 +903,150 @@ module decoder else if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK; // pack else illegal_instr_bm = 1'b1; end + { + 7'b001_1001, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::AES64ES; // aes64es + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b001_1011, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::AES64ESM; // aes64esm + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b011_1111, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::AES64KS2; // aes64ks2 + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b0010001, 3'b000 + }, { + 7'b0110001, 3'b000 + }, { + 7'b1010001, 3'b000 + }, { + 7'b1110001, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::AES32ESI; // aes32esi + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b0010011, 3'b000 + }, { + 7'b0110011, 3'b000 + }, { + 7'b1010011, 3'b000 + }, { + 7'b1110011, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::AES32ESMI; // aes32esmi + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b0010101, 3'b000 + }, { + 7'b0110101, 3'b000 + }, { + 7'b1010101, 3'b000 + }, { + 7'b1110101, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::AES32DSI; // aes32dsi + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b0010111, 3'b000 + }, { + 7'b0110111, 3'b000 + }, { + 7'b1010111, 3'b000 + }, { + 7'b1110111, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::AES32DSMI; // aes32dsmi + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b001_1101, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::AES64DS; // aes64ds + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b001_1111, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::AES64DSM; // aes64dsm + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b010_1110, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::SHA512SIG0H; // sha512sig0h + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b010_1010, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::SHA512SIG0L; // sha512sig0l + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b010_1111, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::SHA512SIG1H; // sha512sig1h + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b010_1011, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::SHA512SIG1L; // sha512sig1l + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b010_1000, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::SHA512SUM0R; // sha512sum0r + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end + { + 7'b010_1001, 3'b000 + } : begin + if (CVA6Cfg.ZKN) begin + instruction_o.op = ariane_pkg::SHA512SUM1R; // sha512sum1r + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; + end default: begin illegal_instr_bm = 1'b1; end @@ -900,7 +1151,7 @@ module decoder 3'b001: begin instruction_o.op = ariane_pkg::SLL; // Shift Left Logical by Immediate if (instr.instr[31:26] != 6'b0) illegal_instr_non_bm = 1'b1; - if (instr.instr[25] != 1'b0 && CVA6Cfg.XLEN == 32) illegal_instr_non_bm = 1'b1; + if (instr.instr[25] != 1'b0 && CVA6Cfg.IS_XLEN32) illegal_instr_non_bm = 1'b1; end 3'b101: begin @@ -909,7 +1160,7 @@ module decoder else if (instr.instr[31:26] == 6'b010_000) instruction_o.op = ariane_pkg::SRA; // Shift Right Arithmetically by Immediate else illegal_instr_non_bm = 1'b1; - if (instr.instr[25] != 1'b0 && CVA6Cfg.XLEN == 32) illegal_instr_non_bm = 1'b1; + if (instr.instr[25] != 1'b0 && CVA6Cfg.IS_XLEN32) illegal_instr_non_bm = 1'b1; end endcase if (CVA6Cfg.RVB) begin @@ -934,9 +1185,39 @@ module decoder instruction_o.op = ariane_pkg::BSETI; else if (CVA6Cfg.IS_XLEN32 && instr.instr[31:25] == 7'b0010100) instruction_o.op = ariane_pkg::BSETI; - else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000010001111) + else if (CVA6Cfg.ZKN && CVA6Cfg.IS_XLEN32 && instr.instr[31:20] == 12'b000010001111) instruction_o.op = ariane_pkg::ZIP; - else illegal_instr_bm = 1'b1; + else if (CVA6Cfg.ZKN && instr.instr[31:24] == 8'b00110001) begin + instruction_o.op = ariane_pkg::AES64KS1I; + instruction_o.fu = AES; + end else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b001100000000) begin + instruction_o.op = ariane_pkg::AES64IM; + instruction_o.fu = AES; + end else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000100000010) begin + instruction_o.op = ariane_pkg::SHA256SIG0; + instruction_o.fu = AES; + end else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000100000011) begin + instruction_o.op = ariane_pkg::SHA256SIG1; + instruction_o.fu = AES; + end else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000100000000) begin + instruction_o.op = ariane_pkg::SHA256SUM0; + instruction_o.fu = AES; + end else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000100000001) begin + instruction_o.op = ariane_pkg::SHA256SUM1; + instruction_o.fu = AES; + end else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000100000110) begin + instruction_o.op = ariane_pkg::SHA512SIG0; + instruction_o.fu = AES; + end else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000100000111) begin + instruction_o.op = ariane_pkg::SHA512SIG1; + instruction_o.fu = AES; + end else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000100000100) begin + instruction_o.op = ariane_pkg::SHA512SUM0; + instruction_o.fu = AES; + end else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000100000101) begin + instruction_o.op = ariane_pkg::SHA512SUM1; + instruction_o.fu = AES; + end else illegal_instr_bm = 1'b1; end 3'b101: begin if (instr.instr[31:20] == 12'b001010000111) instruction_o.op = ariane_pkg::ORCB; @@ -954,7 +1235,7 @@ module decoder instruction_o.op = ariane_pkg::RORI; else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b011010000111) instruction_o.op = ariane_pkg::BREV8; - else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000010001111) + else if (CVA6Cfg.ZKN && CVA6Cfg.IS_XLEN32 && instr.instr[31:20] == 12'b000010001111) instruction_o.op = ariane_pkg::UNZIP; else illegal_instr_bm = 1'b1; end @@ -994,9 +1275,9 @@ module decoder unique case (instr.itype.funct3) 3'b001: begin if (instr.instr[31:25] == 7'b0110000) begin - if (instr.instr[21:20] == 2'b10) instruction_o.op = ariane_pkg::CPOPW; - else if (instr.instr[21:20] == 2'b00) instruction_o.op = ariane_pkg::CLZW; - else if (instr.instr[21:20] == 2'b01) instruction_o.op = ariane_pkg::CTZW; + if (instr.instr[24:20] == 5'b00010) instruction_o.op = ariane_pkg::CPOPW; + else if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::CLZW; + else if (instr.instr[24:20] == 5'b00001) instruction_o.op = ariane_pkg::CTZW; else illegal_instr_bm = 1'b1; end else if (instr.instr[31:26] == 6'b000010) begin instruction_o.op = ariane_pkg::SLLIUW; // Shift Left Logic by Immediate (Unsigned Word) @@ -1029,7 +1310,7 @@ module decoder 3'b001: instruction_o.op = ariane_pkg::SH; 3'b010: instruction_o.op = ariane_pkg::SW; 3'b011: - if (CVA6Cfg.XLEN == 64) instruction_o.op = ariane_pkg::SD; + if (CVA6Cfg.IS_XLEN64) instruction_o.op = ariane_pkg::SD; else illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase @@ -1052,10 +1333,10 @@ module decoder 3'b100: instruction_o.op = ariane_pkg::LBU; 3'b101: instruction_o.op = ariane_pkg::LHU; 3'b110: - if (CVA6Cfg.XLEN == 64) instruction_o.op = ariane_pkg::LWU; + if (CVA6Cfg.IS_XLEN64) instruction_o.op = ariane_pkg::LWU; else illegal_instr = 1'b1; 3'b011: - if (CVA6Cfg.XLEN == 64) instruction_o.op = ariane_pkg::LD; + if (CVA6Cfg.IS_XLEN64) instruction_o.op = ariane_pkg::LD; else illegal_instr = 1'b1; default: illegal_instr = 1'b1; endcase @@ -1164,7 +1445,7 @@ module decoder if (check_fprm) begin unique case (instr.rftype.rm) inside [3'b000 : 3'b100]: ; //legal rounding modes - 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 + 3'b101: begin // Alternative Half-Precision encoded as fmt=10 and rm=101 if (~CVA6Cfg.XF16ALT || instr.rftype.fmt != 2'b10) illegal_instr = 1'b1; unique case (frm_i) inside // actual rounding mode from frm csr [3'b000 : 3'b100]: ; //legal rounding modes @@ -1237,7 +1518,7 @@ module decoder 5'b01000: begin instruction_o.op = ariane_pkg::FCVT_F2F; // fcvt.fmt.fmt - FP to FP Conversion instruction_o.rs2 = instr.rvftype.rs1; // tie rs2 to rs1 to be safe (vectors use rs2) - imm_select = IIMM; // rs2 holds part of the intruction + imm_select = IIMM; // rs2 holds part of the instruction if (|instr.rftype.rs2[24:23]) illegal_instr = 1'b1; // bits [22:20] used, other bits must be 0 // check source format @@ -1266,12 +1547,14 @@ module decoder imm_select = IIMM; // rs2 holds part of the instruction if (|instr.rftype.rs2[24:22]) illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0 + if (CVA6Cfg.IS_XLEN32 && instr.rftype.rs2[21]) illegal_instr = 1'b1; end 5'b11010: begin instruction_o.op = ariane_pkg::FCVT_I2F; // fcvt.fmt.ifmt - Int to FP Conversion imm_select = IIMM; // rs2 holds part of the instruction if (|instr.rftype.rs2[24:22]) illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0 + if (CVA6Cfg.IS_XLEN32 && instr.rftype.rs2[21]) illegal_instr = 1'b1; end 5'b11100: begin instruction_o.rs2 = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit @@ -1310,7 +1593,7 @@ module decoder if (check_fprm) begin unique case (instr.rftype.rm) inside [3'b000 : 3'b100]: ; //legal rounding modes - 3'b101: begin // Alternative Half-Precsision encded as fmt=10 and rm=101 + 3'b101: begin // Alternative Half-Precision encoded as fmt=10 and rm=101 if (~CVA6Cfg.XF16ALT || instr.rftype.fmt != 2'b10) illegal_instr = 1'b1; unique case (frm_i) inside // actual rounding mode from frm csr [3'b000 : 3'b100]: ; //legal rounding modes @@ -1505,7 +1788,7 @@ module decoder imm_u_type = { {CVA6Cfg.XLEN - 32{instruction_i[31]}}, instruction_i[31:12], 12'b0 }; // JAL, AUIPC, sign extended to 64 bit - // if zcmt then xlen jump address assign to immidiate + // if zcmt then xlen jump address assign to immediate if (CVA6Cfg.RVZCMT && is_zcmt_i) begin imm_uj_type = {{CVA6Cfg.XLEN - 32{jump_address_i[31]}}, jump_address_i[31:0]}; end else begin @@ -1577,12 +1860,23 @@ module decoder interrupt_cause = '0; instruction_o.ex = ex_i; orig_instr_o = '0; - // look if we didn't already get an exception in any previous - // stage - we should not overwrite it as we retain order regarding the exception - if (~ex_i.valid) begin + + if ((CVA6Cfg.SdtrigMcontrol6ExecAddr || CVA6Cfg.SdtrigMcontrol6ExecData) && (sdtrig_decoder_action_i != '0)) begin + // this exception is valid + instruction_o.ex.valid = 1'b1; + // set cause + instruction_o.ex.cause = sdtrig_decoder_action_i; + // set tval + instruction_o.ex.tval = (CVA6Cfg.TvalEn) ? instruction_o.pc : '0; + // set gva bit + if (CVA6Cfg.RVH) instruction_o.ex.gva = v_i; + else instruction_o.ex.gva = 1'b0; + end // look if we didn't already get an exception in any previous + // stage - we should not overwrite it as we retain order regarding the exception + else if (~ex_i.valid) begin // if we didn't already get an exception save the instruction here as we may need it // in the commit stage if we got a access exception to one of the CSR registers - if (CVA6Cfg.CvxifEn || CVA6Cfg.RVF) + if (CVA6Cfg.CvxifEn || CVA6Cfg.RVF || CVA6Cfg.ZKN) orig_instr_o = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i}; if (CVA6Cfg.TvalEn) instruction_o.ex.tval = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i}; @@ -1613,6 +1907,7 @@ module decoder end else if (priv_lvl_i == riscv::PRIV_LVL_M) begin instruction_o.ex.cause = riscv::ENV_CALL_MMODE; end + if (CVA6Cfg.TvalEn) instruction_o.ex.tval = '0; end else if (ebreak) begin // this exception is valid instruction_o.ex.valid = 1'b1; @@ -1621,100 +1916,99 @@ module decoder // set gva bit if (CVA6Cfg.RVH) instruction_o.ex.gva = v_i; else instruction_o.ex.gva = 1'b0; + if (CVA6Cfg.TvalEn) instruction_o.ex.tval = pc_i; end - // ----------------- - // Interrupt Control - // ----------------- - // we decode an interrupt the same as an exception, hence it will be taken if the instruction did not - // throw any previous exception. - // we have three interrupt sources: external interrupts, software interrupts, timer interrupts (order of precedence) - // for two privilege levels: Supervisor and Machine Mode - // Virtual Supervisor Timer Interrupt - if (CVA6Cfg.RVH) begin - if (irq_ctrl_i.mie[riscv::IRQ_VS_TIMER] && irq_ctrl_i.mip[riscv::IRQ_VS_TIMER]) begin - interrupt_cause = INTERRUPTS.VS_TIMER; - end - // Virtual Supervisor Software Interrupt - if (irq_ctrl_i.mie[riscv::IRQ_VS_SOFT] && irq_ctrl_i.mip[riscv::IRQ_VS_SOFT]) begin - interrupt_cause = INTERRUPTS.VS_SW; - end - // Virtual Supervisor External Interrupt - if (irq_ctrl_i.mie[riscv::IRQ_VS_EXT] && (irq_ctrl_i.mip[riscv::IRQ_VS_EXT])) begin - interrupt_cause = INTERRUPTS.VS_EXT; - end - // Hypervisor Guest External Interrupts - if (irq_ctrl_i.mie[riscv::IRQ_HS_EXT] && irq_ctrl_i.mip[riscv::IRQ_HS_EXT]) begin - interrupt_cause = INTERRUPTS.HS_EXT; - end + end + // ----------------- + // Interrupt Control + // ----------------- + // we decode an interrupt the same as an exception, hence it will be taken if the instruction did not + // throw any previous exception. + // we have three interrupt sources: external interrupts, software interrupts, timer interrupts (order of precedence) + // for two privilege levels: Supervisor and Machine Mode + // Virtual Supervisor Timer Interrupt + if (CVA6Cfg.RVH) begin + if (irq_ctrl_i.mie[riscv::IRQ_VS_TIMER] && irq_ctrl_i.mip[riscv::IRQ_VS_TIMER]) begin + interrupt_cause = INTERRUPTS.VS_TIMER; end - if (CVA6Cfg.RVS) begin - // Supervisor Timer Interrupt - if (irq_ctrl_i.mie[riscv::IRQ_S_TIMER] && irq_ctrl_i.mip[riscv::IRQ_S_TIMER]) begin - interrupt_cause = INTERRUPTS.S_TIMER; - end - // Supervisor Software Interrupt - if (irq_ctrl_i.mie[riscv::IRQ_S_SOFT] && irq_ctrl_i.mip[riscv::IRQ_S_SOFT]) begin - interrupt_cause = INTERRUPTS.S_SW; - end - // Supervisor External Interrupt - // The logical-OR of the software-writable bit and the signal from the external interrupt controller is - // used to generate external interrupts to the supervisor - if (irq_ctrl_i.mie[riscv::IRQ_S_EXT] && (irq_ctrl_i.mip[riscv::IRQ_S_EXT] | irq_i[ariane_pkg::SupervisorIrq])) begin - interrupt_cause = INTERRUPTS.S_EXT; - end + // Virtual Supervisor Software Interrupt + if (irq_ctrl_i.mie[riscv::IRQ_VS_SOFT] && irq_ctrl_i.mip[riscv::IRQ_VS_SOFT]) begin + interrupt_cause = INTERRUPTS.VS_SW; end - // Machine Timer Interrupt - if (irq_ctrl_i.mip[riscv::IRQ_M_TIMER] && irq_ctrl_i.mie[riscv::IRQ_M_TIMER]) begin - interrupt_cause = INTERRUPTS.M_TIMER; + // Virtual Supervisor External Interrupt + if (irq_ctrl_i.mie[riscv::IRQ_VS_EXT] && (irq_ctrl_i.mip[riscv::IRQ_VS_EXT])) begin + interrupt_cause = INTERRUPTS.VS_EXT; end - if (CVA6Cfg.SoftwareInterruptEn) begin - // Machine Mode Software Interrupt - if (irq_ctrl_i.mip[riscv::IRQ_M_SOFT] && irq_ctrl_i.mie[riscv::IRQ_M_SOFT]) begin - interrupt_cause = INTERRUPTS.M_SW; - end + // Hypervisor Guest External Interrupts + if (irq_ctrl_i.mie[riscv::IRQ_HS_EXT] && irq_ctrl_i.mip[riscv::IRQ_HS_EXT]) begin + interrupt_cause = INTERRUPTS.HS_EXT; + end + end + if (CVA6Cfg.RVS) begin + // Supervisor Timer Interrupt + if (irq_ctrl_i.mie[riscv::IRQ_S_TIMER] && irq_ctrl_i.mip[riscv::IRQ_S_TIMER]) begin + interrupt_cause = INTERRUPTS.S_TIMER; end - // Machine Mode External Interrupt - if (irq_ctrl_i.mip[riscv::IRQ_M_EXT] && irq_ctrl_i.mie[riscv::IRQ_M_EXT]) begin - interrupt_cause = INTERRUPTS.M_EXT; + // Supervisor Software Interrupt + if (irq_ctrl_i.mie[riscv::IRQ_S_SOFT] && irq_ctrl_i.mip[riscv::IRQ_S_SOFT]) begin + interrupt_cause = INTERRUPTS.S_SW; end + // Supervisor External Interrupt + // The logical-OR of the software-writable bit and the signal from the external interrupt controller is + // used to generate external interrupts to the supervisor + if (irq_ctrl_i.mie[riscv::IRQ_S_EXT] && (irq_ctrl_i.mip[riscv::IRQ_S_EXT] | irq_i[ariane_pkg::SupervisorIrq])) begin + interrupt_cause = INTERRUPTS.S_EXT; + end + end + // Machine Timer Interrupt + if (irq_ctrl_i.mip[riscv::IRQ_M_TIMER] && irq_ctrl_i.mie[riscv::IRQ_M_TIMER]) begin + interrupt_cause = INTERRUPTS.M_TIMER; + end + if (CVA6Cfg.SoftwareInterruptEn) begin + // Machine Mode Software Interrupt + if (irq_ctrl_i.mip[riscv::IRQ_M_SOFT] && irq_ctrl_i.mie[riscv::IRQ_M_SOFT]) begin + interrupt_cause = INTERRUPTS.M_SW; + end + end + // Machine Mode External Interrupt + if (irq_ctrl_i.mip[riscv::IRQ_M_EXT] && irq_ctrl_i.mie[riscv::IRQ_M_EXT]) begin + interrupt_cause = INTERRUPTS.M_EXT; + end - if (interrupt_cause[CVA6Cfg.XLEN-1] && irq_ctrl_i.global_enable) begin - // However, if bit i in mideleg is set, interrupts are considered to be globally enabled if the hart’s current privilege - // mode equals the delegated privilege mode (S or U) and that mode’s interrupt enable bit - // (SIE or UIE in mstatus) is set, or if the current privilege mode is less than the delegated privilege mode. - if (irq_ctrl_i.mideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin - if (CVA6Cfg.RVH) begin : hyp_int_gen - if (v_i && irq_ctrl_i.hideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin - if ((irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_U) begin - instruction_o.ex.valid = 1'b1; - instruction_o.ex.cause = interrupt_cause; - end - end else if (v_i && ~irq_ctrl_i.hideleg[interrupt_cause[$clog2( - CVA6Cfg.XLEN - )-1:0]]) begin - instruction_o.ex.valid = 1'b1; - instruction_o.ex.cause = interrupt_cause; - end else if (!v_i && ((irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_U) && ~irq_ctrl_i.hideleg[interrupt_cause[$clog2( - CVA6Cfg.XLEN - )-1:0]]) begin - instruction_o.ex.valid = 1'b1; - instruction_o.ex.cause = interrupt_cause; - end - end else begin - if ((CVA6Cfg.RVS && irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U)) begin + if (interrupt_cause[CVA6Cfg.XLEN-1] && irq_ctrl_i.global_enable) begin + // However, if bit i in mideleg is set, interrupts are considered to be globally enabled if the hart’s current privilege + // mode equals the delegated privilege mode (S or U) and that mode’s interrupt enable bit + // (SIE or UIE in mstatus) is set, or if the current privilege mode is less than the delegated privilege mode. + if (irq_ctrl_i.mideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin + if (CVA6Cfg.RVH) begin : hyp_int_gen + if (v_i && irq_ctrl_i.hideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin + if ((irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_U) begin instruction_o.ex.valid = 1'b1; instruction_o.ex.cause = interrupt_cause; end + end else if (v_i && ~irq_ctrl_i.hideleg[interrupt_cause[$clog2(CVA6Cfg.XLEN)-1:0]]) begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = interrupt_cause; + end else if (!v_i && ((irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || priv_lvl_i == riscv::PRIV_LVL_U) && ~irq_ctrl_i.hideleg[interrupt_cause[$clog2( + CVA6Cfg.XLEN + )-1:0]]) begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = interrupt_cause; end end else begin - instruction_o.ex.valid = 1'b1; - instruction_o.ex.cause = interrupt_cause; + if ((CVA6Cfg.RVS && irq_ctrl_i.sie && priv_lvl_i == riscv::PRIV_LVL_S) || (CVA6Cfg.RVU && priv_lvl_i == riscv::PRIV_LVL_U)) begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = interrupt_cause; + end end + end else begin + instruction_o.ex.valid = 1'b1; + instruction_o.ex.cause = interrupt_cause; end end // a debug request has precendece over everything else - if (CVA6Cfg.DebugEn && debug_req_i && !debug_mode_i) begin + if ((CVA6Cfg.DebugEn && debug_req_i && !debug_mode_i)) begin instruction_o.ex.valid = 1'b1; instruction_o.ex.cause = riscv::DEBUG_REQUEST; end diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 4bd3a822b25..4c7cf7d5513 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -29,7 +29,10 @@ module ex_stage parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, parameter type lsu_ctrl_t = logic, - parameter type x_result_t = logic + parameter type x_result_t = logic, + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic, + parameter type cbo_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -45,6 +48,8 @@ module ex_stage input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_i, // FU data useful to execute instruction - ISSUE_STAGE input fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_i, + // ALU to ALU bypass control - ISSUE_STAGE + input alu_bypass_t alu_bypass_i, // PC of the current instruction - ISSUE_STAGE input logic [CVA6Cfg.VLEN-1:0] pc_i, // Is_zcmt instruction - ISSUE_STAGE @@ -65,6 +70,8 @@ module ex_stage output logic flu_valid_o, // ALU instruction is valid - ISSUE_STAGE input logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_i, + // AES instruction is valid - ISSUE_STAGE + input logic [CVA6Cfg.NrIssuePorts-1:0] aes_valid_i, // Branch unit instruction is valid - ISSUE_STAGE input logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_i, // Information of branch prediction - ISSUE_STAGE @@ -111,6 +118,8 @@ module ex_stage input logic stall_st_pending_i, // TO_BE_COMPLETED - COMMIT_STAGE output logic no_st_pending_o, + // Shared TLB is busy processing a multi-cycle flush + output logic shared_tlb_flush_busy_o, // Atomic result is valid - COMMIT_STAGE input logic amo_valid_commit_i, // FU is ready - ISSUE_STAGE @@ -133,6 +142,8 @@ module ex_stage output logic fpu_valid_o, // FPU exception - ISSUE_STAGE output exception_t fpu_exception_o, + // FPU early valid - ISSUE_STAGE + output logic fpu_early_valid_o, // ALU2 instruction is valid - ISSUE_STAGE input logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_i, // CVXIF instruction is valid - ISSUE_STAGE @@ -161,6 +172,9 @@ module ex_stage input logic x_transaction_rejected_i, // accelerate port result is valid - ACC_DISPATCHER input logic acc_valid_i, + // Accelerator MMU access + input acc_mmu_req_t acc_mmu_req_i, + output acc_mmu_resp_t acc_mmu_resp_o, // Enable virtual memory translation - CSR_REGFILE input logic enable_translation_i, // Enable G-Stage memory translation - CSR_REGFILE @@ -175,6 +189,8 @@ module ex_stage input logic flush_tlb_gvma_i, // Privilege mode - CSR_REGFILE input riscv::priv_lvl_t priv_lvl_i, + // Data endianness - CSR REGFILE + input logic mbe_i, // Virtualization mode - CSR_REGFILE input logic v_i, // Privilege level at which load and stores should happen - CSR_REGFILE @@ -207,7 +223,7 @@ module ex_stage input icache_arsp_t icache_areq_i, // icache translation request - CACHE output icache_areq_t icache_areq_o, - // Data cache request ouput - CACHE + // Data cache request output - CACHE input dcache_req_o_t [2:0] dcache_req_ports_i, // Data cache request input - CACHE output dcache_req_i_t [2:0] dcache_req_ports_o, @@ -224,13 +240,26 @@ module ex_stage // To count the data TLB misses - PERF_COUNTERS output logic dtlb_miss_o, // Report the PMP configuration - CSR_REGFILE - input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, // Report the PMP addresses - CSR_REGFILE - input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, // Information dedicated to RVFI - RVFI output lsu_ctrl_t rvfi_lsu_ctrl_o, // Information dedicated to RVFI - RVFI - output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o + output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o, + // Original instruction AES bits + input logic [5:0] orig_instr_aes_i, + //Trigger module communication + output logic [CVA6Cfg.VLEN-1:0] sdtrig_lsu_inputs_operand_a_o, + output logic [CVA6Cfg.XLEN-1:0] sdtrig_lsu_inputs_operand_c_o, + output logic sdtrig_lsu_inputs_we_o, + output fu_op sdtrig_lsu_inputs_op_o, + output logic sdtrig_lsu_inputs_valid_o, + input logic sdtrig_load_stall_i, + input logic sdtrig_load_cancel_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_load_action_i, + input logic sdtrig_store_stall_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_store_action_i ); // ------------------------- @@ -266,14 +295,18 @@ module ex_stage // from ALU to branch unit logic alu_branch_res; // branch comparison result - logic [CVA6Cfg.XLEN-1:0] alu_result, csr_result, mult_result; + logic [CVA6Cfg.NrALUs-1:0][CVA6Cfg.XLEN-1:0] alu_result; + logic [CVA6Cfg.XLEN-1:0] csr_result, mult_result, aes_result; logic [CVA6Cfg.VLEN-1:0] branch_result; + bp_resolve_t resolved_branch; logic csr_ready, mult_ready; logic [CVA6Cfg.TRANS_ID_BITS-1:0] mult_trans_id; logic mult_valid; + fu_data_t [CVA6Cfg.NrALUs-1:0] alu_data; + logic [CVA6Cfg.NrIssuePorts-1:0] one_cycle_select; - assign one_cycle_select = alu_valid_i | branch_valid_i | csr_valid_i; + assign one_cycle_select = alu_valid_i | branch_valid_i | csr_valid_i | aes_valid_i; fu_data_t one_cycle_data; logic [CVA6Cfg.VLEN-1:0] rs1_forwarding; @@ -293,15 +326,27 @@ module ex_stage end end - // 1. ALU (combinatorial) - alu #( + // 1. ALU(s) (combinatorial) + assign alu_data[0] = one_cycle_data; + + if (CVA6Cfg.SuperscalarEn) begin : gen_alu2_data_sel + always_comb begin + unique case (1'b1) + alu2_valid_i[1]: alu_data[1] = fu_data_i[1]; + alu2_valid_i[0]: alu_data[1] = fu_data_i[0]; + default: alu_data[1] = '0; + endcase + end + end + + alu_wrapper #( .CVA6Cfg (CVA6Cfg), - .HasBranch(1'b1), .fu_data_t(fu_data_t) - ) alu_i ( + ) alu_wrapper_i ( .clk_i, .rst_ni, - .fu_data_i (one_cycle_data), + .alu_bypass_i (alu_bypass_i), + .fu_data_i (alu_data), .result_o (alu_result), .alu_branch_res_o(alu_branch_res) ); @@ -328,10 +373,11 @@ module ex_stage .branch_comp_res_i (alu_branch_res), .branch_result_o (branch_result), .branch_predict_i, - .resolved_branch_o, + .resolved_branch_o (resolved_branch), .resolve_branch_o, .branch_exception_o(flu_exception_o) ); + assign resolved_branch_o = resolved_branch; // 3. CSR (sequential) csr_buffer #( @@ -358,13 +404,15 @@ module ex_stage flu_trans_id_o = one_cycle_data.trans_id; // ALU result if (|alu_valid_i) begin - flu_result_o = alu_result; + flu_result_o = alu_result[0]; // CSR result end else if (|csr_valid_i) begin flu_result_o = csr_result; end else if (mult_valid) begin flu_result_o = mult_result; flu_trans_id_o = mult_trans_id; + end else if (|aes_valid_i) begin + flu_result_o = aes_result; end end @@ -406,8 +454,6 @@ module ex_stage logic fpu_valid; logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id; logic [CVA6Cfg.XLEN-1:0] fpu_result; - logic alu2_valid; - logic [CVA6Cfg.XLEN-1:0] alu2_result; generate if (CVA6Cfg.FpPresent) begin : fpu_gen @@ -439,56 +485,30 @@ module ex_stage .fpu_trans_id_o(fpu_trans_id), .result_o(fpu_result), .fpu_valid_o(fpu_valid), - .fpu_exception_o + .fpu_exception_o, + .fpu_early_valid_o ); end else begin : no_fpu_gen - assign fpu_ready_o = '0; - assign fpu_trans_id = '0; - assign fpu_result = '0; - assign fpu_valid = '0; - assign fpu_exception_o = '0; + assign fpu_ready_o = '0; + assign fpu_trans_id = '0; + assign fpu_result = '0; + assign fpu_valid = '0; + assign fpu_exception_o = '0; + assign fpu_early_valid_o = '0; end endgenerate - // ---------------- - // ALU2 - // ---------------- - fu_data_t alu2_data; - if (CVA6Cfg.SuperscalarEn) begin : alu2_gen - always_comb begin - alu2_data = alu2_valid_i[0] ? fu_data_i[0] : '0; - if (alu2_valid_i[1]) begin - alu2_data = fu_data_i[1]; - end - end - - alu #( - .CVA6Cfg (CVA6Cfg), - .HasBranch(1'b0), - .fu_data_t(fu_data_t) - ) alu2_i ( - .clk_i, - .rst_ni, - .fu_data_i (alu2_data), - .result_o (alu2_result), - .alu_branch_res_o( /* this ALU does not handle branching */) - ); - end else begin - assign alu2_data = '0; - assign alu2_result = '0; - end - // result MUX // This is really explicit so that synthesis tools can elide unused signals if (CVA6Cfg.SuperscalarEn) begin if (CVA6Cfg.FpPresent) begin assign fpu_valid_o = fpu_valid || |alu2_valid_i; - assign fpu_result_o = fpu_valid ? fpu_result : alu2_result; - assign fpu_trans_id_o = fpu_valid ? fpu_trans_id : alu2_data.trans_id; + assign fpu_result_o = fpu_valid ? fpu_result : alu_result[1]; + assign fpu_trans_id_o = fpu_valid ? fpu_trans_id : alu_data[1].trans_id; end else begin assign fpu_valid_o = |alu2_valid_i; - assign fpu_result_o = alu2_result; - assign fpu_trans_id_o = alu2_data.trans_id; + assign fpu_result_o = alu_result[1]; + assign fpu_trans_id_o = alu_data[1].trans_id; end end else begin if (CVA6Cfg.FpPresent) begin @@ -507,14 +527,19 @@ module ex_stage // ---------------- fu_data_t lsu_data; logic [31:0] lsu_tinst; + logic speculative_load; always_comb begin - lsu_data = lsu_valid_i[0] ? fu_data_i[0] : '0; + lsu_data = lsu_valid_i[0] ? fu_data_i[0] : '0; lsu_tinst = tinst_i[0]; + speculative_load = 1'b0; if (CVA6Cfg.SuperscalarEn) begin if (lsu_valid_i[1]) begin lsu_data = fu_data_i[1]; lsu_tinst = tinst_i[1]; + if (CVA6Cfg.SpeculativeSb) begin + speculative_load = branch_valid_i[0]; + end end end end @@ -529,16 +554,22 @@ module ex_stage .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), - .lsu_ctrl_t(lsu_ctrl_t) + .lsu_ctrl_t(lsu_ctrl_t), + .cbo_t(cbo_t), + .acc_mmu_req_t(acc_mmu_req_t), + .acc_mmu_resp_t(acc_mmu_resp_t), + .bp_resolve_t(bp_resolve_t) ) lsu_i ( .clk_i, .rst_ni, .flush_i, .stall_st_pending_i, .no_st_pending_o, - .fu_data_i (lsu_data), + .shared_tlb_flush_busy_o(shared_tlb_flush_busy_o), + .fu_data_i (lsu_data), .lsu_ready_o, - .lsu_valid_i (|lsu_valid_i), + .lsu_valid_i (|lsu_valid_i), + .speculative_load_i (speculative_load), .load_trans_id_o, .load_result_o, .load_valid_o, @@ -547,16 +578,20 @@ module ex_stage .store_result_o, .store_valid_o, .store_exception_o, - .commit_i (lsu_commit_i), - .commit_ready_o (lsu_commit_ready_o), + .commit_i (lsu_commit_i), + .commit_ready_o (lsu_commit_ready_o), .commit_tran_id_i, + .resolved_branch_i (resolved_branch), .enable_translation_i, .enable_g_translation_i, .en_ld_st_translation_i, .en_ld_st_g_translation_i, + .acc_mmu_req_i, + .acc_mmu_resp_o, .icache_areq_i, .icache_areq_o, .priv_lvl_i, + .mbe_i, .v_i, .ld_st_priv_lvl_i, .ld_st_v_i, @@ -570,11 +605,11 @@ module ex_stage .hgatp_ppn_i, .asid_i, .vs_asid_i, - .asid_to_be_flushed_i (asid_to_be_flushed), + .asid_to_be_flushed_i (asid_to_be_flushed), .vmid_i, - .vmid_to_be_flushed_i (vmid_to_be_flushed), - .vaddr_to_be_flushed_i (vaddr_to_be_flushed), - .gpaddr_to_be_flushed_i(gpaddr_to_be_flushed), + .vmid_to_be_flushed_i (vmid_to_be_flushed), + .vaddr_to_be_flushed_i (vaddr_to_be_flushed), + .gpaddr_to_be_flushed_i (gpaddr_to_be_flushed), .flush_tlb_i, .flush_tlb_vvma_i, .flush_tlb_gvma_i, @@ -587,13 +622,34 @@ module ex_stage .amo_valid_commit_i, .amo_req_o, .amo_resp_i, - .tinst_i (lsu_tinst), + .tinst_i (lsu_tinst), .pmpcfg_i, .pmpaddr_i, .rvfi_lsu_ctrl_o, - .rvfi_mem_paddr_o + .rvfi_mem_paddr_o, + //Trigger module command signals + .sdtrig_load_stall_i (sdtrig_load_stall_i), + .sdtrig_load_cancel_i (sdtrig_load_cancel_i), + .sdtrig_load_action_i (sdtrig_load_action_i), + .sdtrig_store_stall_i (sdtrig_store_stall_i), + .sdtrig_store_action_i (sdtrig_store_action_i) ); + //Sdtrig + if(CVA6Cfg.SdtrigMcontrol6Store || CVA6Cfg.SdtrigMcontrol6LoadAddr || CVA6Cfg.SdtrigMcontrol6LoadData) begin + assign sdtrig_lsu_inputs_operand_a_o = CVA6Cfg.VLEN'(lsu_data.operand_a + lsu_data.imm); + assign sdtrig_lsu_inputs_operand_c_o = lsu_data.operand_b; + assign sdtrig_lsu_inputs_we_o = lsu_data.fu == STORE; + assign sdtrig_lsu_inputs_op_o = lsu_data.operation; + assign sdtrig_lsu_inputs_valid_o = |lsu_valid_i; + end else begin + assign sdtrig_lsu_inputs_operand_a_o = '0; + assign sdtrig_lsu_inputs_operand_c_o = '0; + assign sdtrig_lsu_inputs_we_o = '0; + assign sdtrig_lsu_inputs_op_o = ADD; + assign sdtrig_lsu_inputs_valid_o = '0; + end + if (CVA6Cfg.CvxifEn) begin : gen_cvxif fu_data_t cvxif_data; always_comb begin @@ -612,6 +668,7 @@ module ex_stage ) cvxif_fu_i ( .clk_i, .rst_ni, + .v_i, .x_valid_i(|x_valid_i), .x_trans_id_i(cvxif_data.trans_id), .x_illegal_i(x_transaction_rejected_i), @@ -633,6 +690,8 @@ module ex_stage assign x_exception_o = '0; assign x_result_o = '0; assign x_valid_o = '0; + assign x_we_o = '0; + assign x_rd_o = '0; end if (CVA6Cfg.RVS) begin @@ -683,7 +742,7 @@ module ex_stage // if the current instruction in EX_STAGE is a sfence.vma, in the next cycle no writes will happen end else if ((~(current_instruction_is_sfence_vma || current_instruction_is_hfence_vvma || current_instruction_is_hfence_gvma)) && (~((fu_data_i[0].operation == SFENCE_VMA || fu_data_i[0].operation == HFENCE_VVMA || fu_data_i[0].operation == HFENCE_GVMA ) && |csr_valid_i))) begin vaddr_to_be_flushed <= rs1_forwarding; - gpaddr_to_be_flushed <= {2'b00, rs1_forwarding[CVA6Cfg.GPLEN-1:2]}; + gpaddr_to_be_flushed <= {rs1_forwarding[CVA6Cfg.GPLEN-3:0], 2'b00}; asid_to_be_flushed <= rs2_forwarding[CVA6Cfg.ASID_WIDTH-1:0]; vmid_to_be_flushed <= rs2_forwarding[CVA6Cfg.VMID_WIDTH-1:0]; end @@ -713,4 +772,24 @@ module ex_stage assign gpaddr_to_be_flushed = '0; end + // ---------------- + // Scalar Cryptography Unit + // ---------------- + generate + if (CVA6Cfg.ZKN) begin : aes_gen + aes #( + .CVA6Cfg (CVA6Cfg), + .fu_data_t(fu_data_t) + ) aes_i ( + .clk_i, + .rst_ni, + .fu_data_i (one_cycle_data), + .result_o (aes_result), + .orig_instr_aes(orig_instr_aes_i) + ); + end else begin : no_aes_gen + assign aes_result = '0; + end + endgenerate + endmodule diff --git a/core/fpu_wrap.sv b/core/fpu_wrap.sv index c30033463fd..474005f8e64 100644 --- a/core/fpu_wrap.sv +++ b/core/fpu_wrap.sv @@ -34,7 +34,8 @@ module fpu_wrap output logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id_o, output logic [ CVA6Cfg.FLen-1:0] result_o, output logic fpu_valid_o, - output exception_t fpu_exception_o + output exception_t fpu_exception_o, + output logic fpu_early_valid_o ); // this is a workaround @@ -553,15 +554,19 @@ module fpu_wrap .tag_o (fpu_trans_id_o), .out_valid_o (fpu_out_valid), .out_ready_i (fpu_out_ready), - .busy_o ( /* unused */) + .busy_o ( /* unused */), + .early_valid_o (fpu_early_valid_o) ); // Pack status flag into exception cause, tval ignored in wb, exception is always invalid assign fpu_exception_o.cause = {59'h0, fpu_status}; assign fpu_exception_o.valid = 1'b0; assign fpu_exception_o.tval = '0; + assign fpu_exception_o.tval2 = '0; + assign fpu_exception_o.tinst = '0; + assign fpu_exception_o.gva = '0; - // Donwstream write port is dedicated to FPU and always ready + // Downstream write port is dedicated to FPU and always ready assign fpu_out_ready = 1'b1; // Downstream valid from unit diff --git a/core/frontend/bht.sv b/core/frontend/bht.sv index e95c536770e..9d4c195f798 100644 --- a/core/frontend/bht.sv +++ b/core/frontend/bht.sv @@ -1,6 +1,6 @@ // Copyright 2018 - 2019 ETH Zurich and University of Bologna. -// Copyright 2023 - Thales for additionnal contribution. -// Copyright 2024 - PlanV Technologies for additionnal contribution. +// Copyright 2023 - Thales for additional contribution. +// Copyright 2024 - PlanV Technologies for additional contribution. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 2.0 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at @@ -16,7 +16,7 @@ // Date: 09.06.2018 // FPGA optimization: Sebastien Jacq, Thales // Date: 2023-01-30 -// FPGA optimization for Altera: Angela Gonzalez, PlanV Technolgies +// FPGA optimization for Altera: Angela Gonzalez, PlanV Technologies // Date: 2024-10-16 // branch history table - 2 bit saturation counter diff --git a/core/frontend/bht2lvl.sv b/core/frontend/bht2lvl.sv new file mode 100644 index 00000000000..26ab2cbf195 --- /dev/null +++ b/core/frontend/bht2lvl.sv @@ -0,0 +1,131 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Original author: Gianmarco Ottavi, University of Bologna +// Description: Private history BHT + +module bht2lvl #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bht_update_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic flush_i, + input logic [ CVA6Cfg.VLEN-1:0] vpc_i, + input bht_update_t bht_update_i, + // we potentially need INSTR_PER_FETCH predictions/cycle + output ariane_pkg::bht_prediction_t [CVA6Cfg.INSTR_PER_FETCH-1:0] bht_prediction_o +); + + // the last bit is always zero, we don't need it for indexing + localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2; + // re-shape the branch history table + localparam NR_ROWS = CVA6Cfg.BHTEntries / CVA6Cfg.INSTR_PER_FETCH; + // number of bits needed to index the row + localparam ROW_ADDR_BITS = $clog2(CVA6Cfg.INSTR_PER_FETCH); + localparam ROW_INDEX_BITS = CVA6Cfg.RVC == 1'b1 ? $clog2(CVA6Cfg.INSTR_PER_FETCH) : 1; + // number of bits we should use for prediction + localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS; + + typedef struct packed { + logic valid; + logic [CVA6Cfg.BHTHist-1:0] hist; + logic [2**CVA6Cfg.BHTHist-1:0][1:0] saturation_counter; + } bht_entry_t; + + // This parameter is needed to reset all saturation + // counters to 2'b10 while circumventing the Verilator + // limitation of unsupported delayed assignment to array + // inside for loops + localparam bht_entry_t BHT_RST_VALUE = '{ + valid: 1'b0, + hist: '0, + saturation_counter: {2 ** CVA6Cfg.BHTHist{2'b10}} + }; + + bht_entry_t bht_d[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0]; + bht_entry_t bht_q[NR_ROWS-1:0][CVA6Cfg.INSTR_PER_FETCH-1:0]; + + + logic [$clog2(NR_ROWS)-1:0] index, update_pc; + logic [CVA6Cfg.BHTHist-1:0] update_hist; + logic [ ROW_INDEX_BITS-1:0] update_row_index; + + assign index = vpc_i[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + assign update_pc = bht_update_i.pc[PREDICTION_BITS-1:ROW_ADDR_BITS+OFFSET]; + assign update_hist = bht_q[update_pc][update_row_index].hist; + + if (CVA6Cfg.RVC) begin : gen_update_row_index + assign update_row_index = bht_update_i.pc[ROW_ADDR_BITS+OFFSET-1:OFFSET]; + end else begin + assign update_row_index = '0; + end + + + logic [1:0] saturation_counter; + + // Get the current history of the entry + logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.BHTHist-1:0] read_history; + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin + assign read_history[i] = bht_q[index][i].hist; + end + + // prediction assignment + for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_bht_output + assign bht_prediction_o[i].valid = bht_q[index][i].valid; + assign bht_prediction_o[i].taken = bht_q[index][i].saturation_counter[read_history[i]][1] == 1'b1; + end + + always_comb begin : update_bht + bht_d = bht_q; + saturation_counter = bht_q[update_pc][update_row_index].saturation_counter[update_hist]; + + if (bht_update_i.valid) begin + bht_d[update_pc][update_row_index].valid = 1'b1; + + if (saturation_counter == 2'b11) begin + // we can safely decrease it + if (!bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter - 1; + // then check if it saturated in the negative regime e.g.: branch not taken + end else if (saturation_counter == 2'b00) begin + // we can safely increase it + if (bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter + 1; + end else begin // otherwise we are not in any boundaries and can decrease or increase it + if (bht_update_i.taken) + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter + 1; + else + bht_d[update_pc][update_row_index].saturation_counter[update_hist] = saturation_counter - 1; + end + + bht_d[update_pc][update_row_index].hist = { + update_hist[CVA6Cfg.BHTHist-2:0], bht_update_i.taken + }; + end + end + + for (genvar i = 0; i < NR_ROWS; i++) begin : gen_ff_rows + for (genvar j = 0; j < CVA6Cfg.INSTR_PER_FETCH; j++) begin : gen_ff_cols + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + bht_q[i][j] <= BHT_RST_VALUE; + end else begin + if (flush_i) begin + bht_q[i][j] <= BHT_RST_VALUE; + end else begin + bht_q[i][j] <= bht_d[i][j]; + end + end + end + end + end + +endmodule diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 1505140e8c8..f95b38354a6 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -36,6 +36,8 @@ module frontend input logic flush_i, // Halt requested by WFI and Accelerate port - CONTROLLER input logic halt_i, + // Halt frontend - CONTROLLER (in the case of fence_i to avoid fetching an old instruction) + input logic halt_frontend_i, // Set COMMIT PC as next PC requested by FENCE, CSR side-effect and Accelerate port - CONTROLLER input logic set_pc_commit_i, // COMMIT PC - COMMIT @@ -150,6 +152,7 @@ module frontend // Instruction FIFO logic [ CVA6Cfg.VLEN-1:0] predict_address; cf_t [CVA6Cfg.INSTR_PER_FETCH-1:0] cf_type; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] cf_valid; logic [CVA6Cfg.INSTR_PER_FETCH-1:0] taken_rvi_cf; logic [CVA6Cfg.INSTR_PER_FETCH-1:0] taken_rvc_cf; @@ -195,10 +198,9 @@ module frontend end ; - // for the return address stack it doens't matter as we have the + // for the return address stack it doesn't matter as we have the // address of the call/return already logic bp_valid; - logic [CVA6Cfg.INSTR_PER_FETCH-1:0] is_branch; logic [CVA6Cfg.INSTR_PER_FETCH-1:0] is_call; logic [CVA6Cfg.INSTR_PER_FETCH-1:0] is_jump; @@ -225,6 +227,7 @@ module frontend predict_address = '0; for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) cf_type[i] = ariane_pkg::NoCF; + for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) cf_valid[i] = 1'b0; ras_push = 1'b0; ras_pop = 1'b0; @@ -238,11 +241,12 @@ module frontend 4'b0000: ; // regular instruction e.g.: no branch // unconditional jump to register, we need the BTB to resolve this 4'b0001: begin - ras_pop = 1'b0; + ras_pop = 1'b0; ras_push = 1'b0; + cf_type[i] = ariane_pkg::JumpR; if (CVA6Cfg.BTBEntries != 0 && btb_prediction_shifted[i].valid) begin predict_address = btb_prediction_shifted[i].target_address; - cf_type[i] = ariane_pkg::JumpR; + cf_valid[i] = 1'b1; end end // its an unconditional jump to an immediate @@ -252,6 +256,7 @@ module frontend taken_rvi_cf[i] = rvi_jump[i]; taken_rvc_cf[i] = rvc_jump[i]; cf_type[i] = ariane_pkg::Jump; + cf_valid[i] = rvi_jump[i] || rvc_jump[i]; end // return 4'b0100: begin @@ -260,6 +265,7 @@ module frontend ras_push = 1'b0; predict_address = ras_predict.ra; cf_type[i] = ariane_pkg::Return; + cf_valid[i] = ras_predict.valid; end // branch prediction 4'b1000: begin @@ -276,7 +282,8 @@ module frontend taken_rvc_cf[i] = rvc_branch[i] & rvc_imm[i][CVA6Cfg.VLEN-1]; end if (taken_rvi_cf[i] || taken_rvc_cf[i]) begin - cf_type[i] = ariane_pkg::Branch; + cf_type[i] = ariane_pkg::Branch; + cf_valid[i] = 1'b1; end end default: ; @@ -294,20 +301,14 @@ module frontend end end end - // or reduce struct - always_comb begin - bp_valid = 1'b0; - // BP cannot be valid if we have a return instruction and the RAS is not giving a valid address - // Check that we encountered a control flow and that for a return the RAS - // contains a valid prediction. - for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) - bp_valid |= ((cf_type[i] != NoCF & cf_type[i] != Return) | ((cf_type[i] == Return) & ras_predict.valid)); - end + // Or reduce struct + assign bp_valid = |cf_valid; assign is_mispredict = resolved_branch_i.valid & resolved_branch_i.is_mispredict; // Cache interface - assign icache_dreq_o.req = instr_queue_ready; - assign if_ready = icache_dreq_i.ready & instr_queue_ready; + // Gate ICache requests and NPC updates during fence.i + assign icache_dreq_o.req = instr_queue_ready & ~halt_frontend_i; + assign if_ready = icache_dreq_i.ready & instr_queue_ready & ~halt_frontend_i; // We need to flush the cache pipeline if: // 1. We mispredicted // 2. Want to flush the whole processor front-end @@ -510,7 +511,7 @@ module frontend if (CVA6Cfg.BHTEntries == 0) begin assign bht_prediction = '0; - end else begin : bht_gen + end else if (CVA6Cfg.BPType == config_pkg::BHT) begin : bht_gen bht #( .CVA6Cfg (CVA6Cfg), .bht_update_t(bht_update_t), @@ -524,6 +525,18 @@ module frontend .bht_update_i (bht_update), .bht_prediction_o(bht_prediction) ); + end else if (CVA6Cfg.BPType == config_pkg::PH_BHT) begin : bht2lvl_gen + bht2lvl #( + .CVA6Cfg (CVA6Cfg), + .bht_update_t(bht_update_t) + ) i_bht ( + .clk_i, + .rst_ni, + .flush_i (flush_bp_i), + .vpc_i (icache_vaddr_q), + .bht_update_i (bht_update), + .bht_prediction_o(bht_prediction) + ); end // we need to inspect up to CVA6Cfg.INSTR_PER_FETCH instructions for branches @@ -565,6 +578,7 @@ module frontend .exception_gva_i (icache_gva_q), .predict_address_i (predict_address), .cf_type_i (cf_type), + .cf_valid_i (cf_valid), .valid_i (instruction_valid), // from re-aligner .consumed_o (instr_queue_consumed), .ready_o (instr_queue_ready), diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index 28254e4708c..e0369ae69f2 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -63,7 +63,7 @@ module instr_queue input logic [CVA6Cfg.INSTR_PER_FETCH-1:0] valid_i, // Handshake’s ready with CACHE - CACHE output logic ready_o, - // Indicates instructions consummed, or popped by ID_STAGE - FRONTEND + // Indicates instructions consumed, or popped by ID_STAGE - FRONTEND output logic [CVA6Cfg.INSTR_PER_FETCH-1:0] consumed_o, // Exception (which is page-table fault) - CACHE input ariane_pkg::frontend_exception_t exception_i, @@ -74,9 +74,11 @@ module instr_queue input logic exception_gva_i, // Branch predict - FRONTEND input logic [CVA6Cfg.VLEN-1:0] predict_address_i, - // Instruction predict address - FRONTEND + // Instruction control-flow prediction type - FRONTEND input ariane_pkg::cf_t [CVA6Cfg.INSTR_PER_FETCH-1:0] cf_type_i, - // Replay instruction because one of the FIFO was full - FRONTEND + // Instruction control-flow prediction valid - FRONTEND + input logic [CVA6Cfg.INSTR_PER_FETCH-1:0] cf_valid_i, + // Replay instruction because one of the FIFO was full - FRONTEND output logic replay_o, // Address at which to replay the fetch - FRONTEND output logic [CVA6Cfg.VLEN-1:0] replay_addr_o, @@ -93,7 +95,8 @@ module instr_queue typedef struct packed { logic [31:0] instr; // instruction word - ariane_pkg::cf_t cf; // branch was taken + ariane_pkg::cf_t cf; // branch prediction type + logic cf_valid; // valid branch prediction ariane_pkg::frontend_exception_t ex; // exception happened logic [CVA6Cfg.VLEN-1:0] ex_vaddr; // lower VLEN bits of tval for exception logic [CVA6Cfg.GPLEN-1:0] ex_gpaddr; // lower GPLEN bits of tval2 for exception @@ -143,6 +146,7 @@ module instr_queue logic [CVA6Cfg.INSTR_PER_FETCH-1:0] fifo_pos; logic [CVA6Cfg.INSTR_PER_FETCH*2-1:0][31:0] instr; ariane_pkg::cf_t [CVA6Cfg.INSTR_PER_FETCH*2-1:0] cf; + logic [CVA6Cfg.INSTR_PER_FETCH*2-1:0] cf_valid; // replay interface logic [CVA6Cfg.INSTR_PER_FETCH-1:0] instr_overflow_fifo; @@ -151,7 +155,7 @@ module instr_queue if (CVA6Cfg.RVC) begin : gen_multiple_instr_per_fetch_with_C for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_unpack_taken - assign taken[i] = cf_type_i[i] != ariane_pkg::NoCF; + assign taken[i] = cf_valid_i[i]; end // calculate a branch mask, e.g.: get the first taken branch @@ -208,6 +212,8 @@ module instr_queue assign instr[i+CVA6Cfg.INSTR_PER_FETCH] = instr_i[i]; assign cf[i] = cf_type_i[i]; assign cf[i+CVA6Cfg.INSTR_PER_FETCH] = cf_type_i[i]; + assign cf_valid[i] = cf_valid_i[i]; + assign cf_valid[i+CVA6Cfg.INSTR_PER_FETCH] = cf_valid_i[i]; end // shift the inputs @@ -215,6 +221,7 @@ module instr_queue /* verilator lint_off WIDTH */ assign instr_data_in[i].instr = instr[CVA6Cfg.INSTR_PER_FETCH+i-idx_is_q]; assign instr_data_in[i].cf = cf[CVA6Cfg.INSTR_PER_FETCH+i-idx_is_q]; + assign instr_data_in[i].cf_valid = cf_valid[CVA6Cfg.INSTR_PER_FETCH+i-idx_is_q]; assign instr_data_in[i].ex = exception_i; // exceptions hold for the whole fetch packet assign instr_data_in[i].ex_vaddr = exception_addr_i; if (CVA6Cfg.RVH) begin : gen_hyp_ex_with_C @@ -330,8 +337,10 @@ module instr_queue fetch_entry_o[i].ex.tval2 = '0; fetch_entry_o[i].ex.gva = 1'b0; fetch_entry_o[i].ex.tinst = '0; + fetch_entry_o[i].ex.timing = '0; fetch_entry_o[i].branch_predict.predict_address = address_out; fetch_entry_o[i].branch_predict.cf = ariane_pkg::NoCF; + fetch_entry_o[i].branch_predict.valid = 1'b0; end // output mux select @@ -357,6 +366,7 @@ module instr_queue fetch_entry_o[0].ex.gva = instr_data_out[i].ex_gva; end fetch_entry_o[0].branch_predict.cf = instr_data_out[i].cf; + fetch_entry_o[0].branch_predict.valid = instr_data_out[i].cf_valid; pop_instr[i] = fetch_entry_fire[0]; end @@ -371,6 +381,7 @@ module instr_queue fetch_entry_o[NID].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE; fetch_entry_o[NID].ex.tval = {{64 - CVA6Cfg.VLEN{1'b0}}, instr_data_out[i].ex_vaddr}; fetch_entry_o[NID].branch_predict.cf = instr_data_out[i].cf; + fetch_entry_o[NID].branch_predict.valid = instr_data_out[i].cf_valid; // Cannot output two CF the same cycle. pop_instr[i] = fetch_entry_fire[NID]; end @@ -413,13 +424,14 @@ module instr_queue fetch_entry_o[0].branch_predict.predict_address = address_out; fetch_entry_o[0].branch_predict.cf = instr_data_out[0].cf; + fetch_entry_o[0].branch_predict.valid = instr_data_out[0].cf_valid; pop_instr[0] = fetch_entry_valid_o[0] & fetch_entry_ready_i[0]; end end for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin - assign fetch_entry_is_cf[i] = fetch_entry_o[i].branch_predict.cf != ariane_pkg::NoCF; + assign fetch_entry_is_cf[i] = fetch_entry_o[i].branch_predict.valid; assign fetch_entry_fire[i] = fetch_entry_valid_o[i] & fetch_entry_ready_i[i]; end @@ -485,7 +497,7 @@ module instr_queue push_address = 1'b0; // check if we are pushing a ctrl flow change, if so save the address for (int i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin - push_address |= push_instr[i] & (instr_data_in[i].cf != ariane_pkg::NoCF); + push_address |= push_instr[i] & instr_data_in[i].cf_valid; end end diff --git a/core/frontend/instr_scan.sv b/core/frontend/instr_scan.sv index 69e45ff69ef..11915145994 100644 --- a/core/frontend/instr_scan.sv +++ b/core/frontend/instr_scan.sv @@ -70,7 +70,7 @@ module instr_scan #( endfunction logic rv32_rvc_jal; - assign rv32_rvc_jal = (CVA6Cfg.XLEN == 32) & ((instr_i[15:13] == riscv::OpcodeC1Jal) & (instr_i[1:0] == riscv::OpcodeC1)); + assign rv32_rvc_jal = CVA6Cfg.IS_XLEN32 & ((instr_i[15:13] == riscv::OpcodeC1Jal) & (instr_i[1:0] == riscv::OpcodeC1)); logic is_xret; assign is_xret = logic'(instr_i[31:30] == 2'b00) & logic'(instr_i[28:0] == 29'b10000001000000000000001110011); @@ -78,7 +78,7 @@ module instr_scan #( // check that rs1 is either x1 or x5 and that rd is not rs1 assign rvi_return_o = rvi_jalr_o & ((instr_i[19:15] == 5'd1) | instr_i[19:15] == 5'd5) & (instr_i[19:15] != instr_i[11:7]); - // Opocde is JAL[R] and destination register is either x1 or x5 + // Opcode is JAL[R] and destination register is either x1 or x5 assign rvi_call_o = (rvi_jalr_o | rvi_jump_o) & ((instr_i[11:7] == 5'd1) | instr_i[11:7] == 5'd5); // differentiates between JAL and BRANCH opcode, JALR comes from BHT assign rvi_imm_o = is_xret ? '0 : (instr_i[3]) ? uj_imm(instr_i) : sb_imm(instr_i); @@ -92,6 +92,7 @@ module instr_scan #( // always links to register 0 logic is_jal_r; assign is_jal_r = (instr_i[15:13] == riscv::OpcodeC2JalrMvAdd) + & (instr_i[11:7] != 5'b00000) & (instr_i[6:2] == 5'b00000) & (instr_i[1:0] == riscv::OpcodeC2); assign rvc_jr_o = is_jal_r & ~instr_i[12]; diff --git a/core/id_stage.sv b/core/id_stage.sv index d37554db4f1..5c5cdbdf358 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -51,7 +51,7 @@ module id_stage #( output logic [CVA6Cfg.NrIssuePorts-1:0] issue_entry_valid_o, // Report if instruction is a control flow instruction - ISSUE output logic [CVA6Cfg.NrIssuePorts-1:0] is_ctrl_flow_o, - // Handshake's acknowlege between decode and issue - ISSUE + // Handshake's acknowledge between decode and issue - ISSUE input logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_ack_i, // Information dedicated to RVFI - RVFI output logic [CVA6Cfg.NrIssuePorts-1:0] rvfi_is_compressed_o, @@ -83,6 +83,18 @@ module id_stage #( input logic tsr_i, // Hypervisor user mode - CSR_REGFILE input logic hu_i, + // machine-mode cache block invalidate enable - CSR_REGFILE + input riscv::cbie_t mcbie_i, + // supervisor-mode cache block invalidate enable - CSR_REGFILE + input riscv::cbie_t scbie_i, + // hypervisor-mode cache block invalidate enable - CSR_REGFILE + input riscv::cbie_t hcbie_i, + // machine-mode clean/flush cache block invalidate enable - CSR_REGFILE + input logic mcbcfe_i, + // supervisor-mode clean/flush cache block invalidate enable - CSR_REGFILE + input logic scbcfe_i, + // hypervisor-mode clean/flush cache block invalidate enable - CSR_REGFILE + input logic hcbcfe_i, // CVXIF Compressed interface input logic [CVA6Cfg.XLEN-1:0] hart_id_i, input logic compressed_ready_i, @@ -91,6 +103,8 @@ module id_stage #( input x_compressed_resp_t compressed_resp_i, output logic compressed_valid_o, output x_compressed_req_t compressed_req_o, + // mcontrol6 address match breakpoint exc. generation request from trigg. module + input logic [CVA6Cfg.XLEN-1:0] sdtrig_decoder_action_i[CVA6Cfg.NrIssuePorts], // Data cache request ouput - CACHE input dcache_req_o_t dcache_req_ports_i, // Data cache request input - CACHE @@ -236,7 +250,7 @@ module id_stage #( assign is_illegal_cvxif_i = is_zcmt_instr[0] ? is_illegal_zcmt : is_illegal_zcmp; assign is_compressed_cvxif_i = is_zcmt_instr[0] ? is_compressed_zcmt : is_compressed_zcmp; assign stall_macro_deco = is_zcmt_instr[0] ? stall_macro_deco_zcmt : stall_macro_deco_zcmp; - end else begin // Do not instantiate the mux which is not optimized cross-bondaries + end else begin // Do not instantiate the mux which is not optimized cross-boundaries assign instruction_cvxif_i = instruction_zcmp; assign is_illegal_cvxif_i = is_illegal_zcmp; assign is_compressed_cvxif_i = is_compressed_zcmp; @@ -269,6 +283,13 @@ module id_stage #( end else begin assign stall_instr_fetch[0] = stall_macro_deco; end + end else begin + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign is_illegal_rvc[i] = 1'b0; + assign instruction_rvc[i] = fetch_entry_i[i].instruction; + assign is_compressed_rvc[i] = 1'b0; + assign stall_instr_fetch[i] = 1'b0; + end end // --------------------------------------------------------- @@ -280,14 +301,16 @@ module id_stage #( is_illegal_deco = is_illegal_rvc; instruction_deco = instruction_rvc; is_compressed_deco = is_compressed_rvc; - if (CVA6Cfg.CvxifEn) begin - is_illegal_deco[0] = is_illegal_cvxif_o; - instruction_deco[0] = instruction_cvxif_o; - is_compressed_deco[0] = is_compressed_cvxif_o; - end else if (!CVA6Cfg.CvxifEn && (CVA6Cfg.RVZCMP || CVA6Cfg.RVZCMT)) begin - is_illegal_deco[0] = is_illegal_cvxif_i; - instruction_deco[0] = instruction_cvxif_i; - is_compressed_deco[0] = is_compressed_cvxif_i; + if (CVA6Cfg.RVC) begin + if (CVA6Cfg.CvxifEn) begin + is_illegal_deco[0] = is_illegal_cvxif_o; + instruction_deco[0] = instruction_cvxif_o; + is_compressed_deco[0] = is_compressed_cvxif_o; + end else if (CVA6Cfg.RVZCMP || CVA6Cfg.RVZCMT) begin + is_illegal_deco[0] = is_illegal_cvxif_i; + instruction_deco[0] = instruction_cvxif_i; + is_compressed_deco[0] = is_compressed_cvxif_i; + end end end @@ -330,9 +353,16 @@ module id_stage #( .vtw_i, .tsr_i, .hu_i, + .mcbie_i, + .scbie_i, + .hcbie_i, + .mcbcfe_i, + .scbcfe_i, + .hcbcfe_i, .instruction_o (decoded_instruction[i]), .orig_instr_o (orig_instr[i]), - .is_control_flow_instr_o (is_control_flow_instr[i]) + .is_control_flow_instr_o (is_control_flow_instr[i]), + .sdtrig_decoder_action_i (sdtrig_decoder_action_i[i]) ); end @@ -419,7 +449,7 @@ module id_stage #( // Clear the valid flag if issue has acknowledged the instruction if (issue_instr_ack_i[0]) issue_n[0].valid = 1'b0; - // TODO: refaire + // TODO: redo // if we have a space in the register and the fetch is valid, go get it // or the issue stage is currently acknowledging an instruction, which means that we will have space // for a new instruction diff --git a/core/include/aes_pkg.sv b/core/include/aes_pkg.sv new file mode 100644 index 00000000000..c5217f336de --- /dev/null +++ b/core/include/aes_pkg.sv @@ -0,0 +1,219 @@ +// Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Author: Munail Waqar, 10xEngineers +// Date: 03.05.2025 +// Description: The Zkn extension including its subsets accelerates cryptographic workloads by introducing dedicated +// scalar instructions compliant with the RISC-V Scalar Cryptography specification. The subsets include: +// Zknd (AES Decryption and related instructions), Zkne (AES Encryption support, including AES rounds and key expansion steps), +// Zknh (SHA-256 and SHA-512 hash functions for secure hashing operations). +// +package aes_pkg; + + // ---------------------- + // AES functions + // ---------------------- + + // AES MixColumns Forward + function automatic [31:0] aes_mixcolumn_fwd(input [31:0] x); + begin + aes_mixcolumn_fwd = { + (((x[7:0] << 1) ^ ((x[7]) ? 8'h1B : 8'h00)) ^ x[7:0]) ^ x[15:8] ^ x[23:16] ^ ((x[31:24] << 1) ^ ((x[31]) ? 8'h1B : 8'h00)), + x[7:0] ^ x[15:8] ^ ((x[23:16] << 1) ^ ((x[23]) ? 8'h1B : 8'h00)) ^ (((x[31:24] << 1) ^ ((x[31]) ? 8'h1B : 8'h00)) ^ x[31:24]), + x[7:0] ^ ((x[15:8] << 1) ^ ((x[15]) ? 8'h1B : 8'h00)) ^ (((x[23:16] << 1) ^ ((x[23]) ? 8'h1B : 8'h00)) ^ x[23:16]) ^ x[31:24], + ((x[7:0] << 1) ^ ((x[7]) ? 8'h1B : 8'h00)) ^ (((x[15:8] << 1) ^ ((x[15]) ? 8'h1B : 8'h00)) ^ x[15:8]) ^ x[23:16] ^ x[31:24] + }; + end + endfunction + // AES subword Forward + function automatic [31:0] aes_subword_fwd(input [31:0] word); + aes_subword_fwd = { + aes_sbox_fwd(word[31:24]), + aes_sbox_fwd(word[23:16]), + aes_sbox_fwd(word[15:8]), + aes_sbox_fwd(word[7:0]) + }; + endfunction + // AES Round Constant + function automatic [31:0] aes_decode_rcon(input [3:0] r); + case (r) + 4'h0: aes_decode_rcon = 32'h00000001; + 4'h1: aes_decode_rcon = 32'h00000002; + 4'h2: aes_decode_rcon = 32'h00000004; + 4'h3: aes_decode_rcon = 32'h00000008; + 4'h4: aes_decode_rcon = 32'h00000010; + 4'h5: aes_decode_rcon = 32'h00000020; + 4'h6: aes_decode_rcon = 32'h00000040; + 4'h7: aes_decode_rcon = 32'h00000080; + 4'h8: aes_decode_rcon = 32'h0000001b; + 4'h9: aes_decode_rcon = 32'h00000036; + 4'hA: aes_decode_rcon = 32'h00000000; + 4'hB: aes_decode_rcon = 32'h00000000; + 4'hC: aes_decode_rcon = 32'h00000000; + 4'hD: aes_decode_rcon = 32'h00000000; + 4'hE: aes_decode_rcon = 32'h00000000; + 4'hF: aes_decode_rcon = 32'h00000000; + default: aes_decode_rcon = 32'h00000000; + endcase + endfunction + // AES MixColumns Inverse + function automatic logic [31:0] aes_mixcolumn_inv(input logic [31:0] x); + aes_mixcolumn_inv = { + (gfmul(x[7:0], 4'hB) ^ gfmul(x[15:8], 4'hD) ^ gfmul(x[23:16], 4'h9) ^ gfmul(x[31:24], 4'hE)), + (gfmul(x[7:0], 4'hD) ^ gfmul(x[15:8], 4'h9) ^ gfmul(x[23:16], 4'hE) ^ gfmul(x[31:24], 4'hB)), + (gfmul(x[7:0], 4'h9) ^ gfmul(x[15:8], 4'hE) ^ gfmul(x[23:16], 4'hB) ^ gfmul(x[31:24], 4'hD)), + (gfmul(x[7:0], 4'hE) ^ gfmul(x[15:8], 4'hB) ^ gfmul(x[23:16], 4'hD) ^ gfmul(x[31:24], 4'h9)) + }; + endfunction + // GF multiplication + function automatic logic [7:0] gfmul(input logic [7:0] x, input logic [3:0] y); + logic [7:0] result, temp; + result = 8'h00; + if (y[0]) result ^= x; + if (y[1]) begin + result ^= ((x << 1) ^ ((x[7]) ? 8'h1B : 8'h00)); + end + if (y[2]) begin + temp = (x << 1) ^ ((x[7]) ? 8'h1B : 8'h00); + result ^= (temp << 1) ^ ((temp[7]) ? 8'h1B : 8'h00); + end + if (y[3]) begin + temp = (x << 1) ^ ((x[7]) ? 8'h1B : 8'h00); + temp = (temp << 1) ^ ((temp[7]) ? 8'h1B : 8'h00); + result ^= (temp << 1) ^ ((temp[7]) ? 8'h1B : 8'h00); + end + return result; + endfunction + // AES Sbox implementation based on https://github.com/riscv/riscv-crypto + // AES Sbox Forward + function automatic logic [7:0] aes_sbox_fwd(input logic [7:0] in_byte); + logic [20:0] expanded; + logic [17:0] non_linear; + logic [ 7:0] compressed; + expanded = linear_top_layer(in_byte); + non_linear = non_linear_layer(expanded); + compressed = linear_bottom_layer(non_linear); + aes_sbox_fwd = compressed; + endfunction + // AES Sbox Inverse + function automatic logic [7:0] aes_sbox_inv(input logic [7:0] in_byte); + logic [20:0] expanded; + logic [17:0] non_linear; + logic [ 7:0] compressed; + expanded = aes_sbox_inv_top(in_byte); + non_linear = non_linear_layer(expanded); + compressed = aes_sbox_inv_out(non_linear); + aes_sbox_inv = compressed; + endfunction + // AES Sbox Forward Top Layer + function automatic logic [20:0] linear_top_layer(input logic [7:0] x); + return { + ((x[7] ^ x[4]) ^ (x[5] ^ x[2])), + (((x[7] ^ x[4]) ^ ((x[6] ^ x[5]) ^ (x[4] ^ x[0]))) ^ ((x[0] ^ (x[6] ^ x[5])) ^ ((x[3] ^ x[1]) ^ (x[5] ^ x[2])))), + ((x[7] ^ x[2]) ^ (((x[7] ^ x[4]) ^ (x[3] ^ x[1])) ^ (x[6] ^ x[5]))), + ((x[7] ^ x[2]) ^ ((x[6] ^ x[5]) ^ (x[1] ^ x[0]))), + ((x[6] ^ x[5]) ^ (x[1] ^ x[0])), + ((x[7] ^ x[4]) ^ ((x[6] ^ x[5]) ^ (x[4] ^ x[0]))), + ((x[6] ^ x[5]) ^ (x[4] ^ x[0])), + ((x[0] ^ (x[6] ^ x[5])) ^ ((x[3] ^ x[1]) ^ (x[5] ^ x[2]))), + ((x[3] ^ x[1]) ^ (x[5] ^ x[2])), + ((x[3] ^ x[1]) ^ (x[6] ^ x[2])), + (((x[7] ^ x[4]) ^ (x[3] ^ x[1])) ^ (x[6] ^ x[2])), + ((x[7] ^ x[1]) ^ (x[4] ^ x[2])), + (((x[7] ^ x[4]) ^ (x[3] ^ x[1])) ^ (x[6] ^ x[5])), + (x[0] ^ (x[6] ^ x[5])), + (x[0] ^ ((x[7] ^ x[4]) ^ (x[3] ^ x[1]))), + ((x[7] ^ x[4]) ^ (x[3] ^ x[1])), + (x[4] ^ x[2]), + (x[7] ^ x[1]), + (x[7] ^ x[2]), + (x[7] ^ x[4]), + (x[0]) + }; + endfunction + // AES Sbox Middle Layer + function automatic logic [17:0] non_linear_layer(input logic [20:0] x); + logic t1, t2, t3, t4, t5; + logic [17:0] y; + t1 = (((x[10] ^ (x[9] & x[5])) ^ (x[17] & x[6])) ^ ((x[4] & x[20]) ^ (x[1] & x[11]))); + t2 = ((((x[14] & x[0]) ^ (x[9] & x[5])) ^ x[18]) ^ ((x[2] & x[8]) ^ (x[1] & x[11]))); + t3 = ((((x[3] ^ x[12]) ^ (x[3] & x[12])) ^ (x[16] & x[7])) ^ ((x[4] & x[20]) ^ (x[1] & x[11]))); + t4 = ((((x[15] & x[13]) ^ (x[3] & x[12])) ^ ((x[2] & x[8]) ^ (x[1] & x[11]))) ^ x[19]); + t5 = ((((t1 ^ t2) & (t1 & t4)) ^ ((t1 ^ t2) ^ (t3 & t1))) ^ (((t3 ^ t4) & (t2 & t3)) ^ ((t3 ^ t4) ^ (t3 & t1)))); + + y[0] = (((t1 ^ t2) & (t1 & t4)) ^ ((t1 ^ t2) ^ (t3 & t1))) & x[7]; + y[1] = (t2 ^ ((t4 ^ (t3 & t1)) & (t1 ^ t2))) & x[13]; + y[2] = ((t2 ^ ((t4 ^ (t3 & t1)) & (t1 ^ t2))) ^ (t4 ^ ((t2 ^ (t3 & t1)) & (t3 ^ t4)))) & x[11]; + y[3] = (((t2 ^ ((t4 ^ (t3 & t1)) & (t1 ^ t2))) ^ (t4 ^ ((t2 ^ (t3 & t1)) & (t3 ^ t4)))) ^ t5) & x[20]; + y[4] = t5 & x[8]; + y[5] = ((t4 ^ ((t2 ^ (t3 & t1)) & (t3 ^ t4))) ^ (((t3 ^ t4) & (t2 & t3)) ^ ((t3 ^ t4) ^ (t3 & t1)))) & x[9]; + y[6] = (((t3 ^ t4) & (t2 & t3)) ^ ((t3 ^ t4) ^ (t3 & t1))) & x[17]; + y[7] = (t4 ^ ((t2 ^ (t3 & t1)) & (t3 ^ t4))) & x[14]; + y[8] = ((t2 ^ ((t4 ^ (t3 & t1)) & (t1 ^ t2))) ^ (((t1 ^ t2) & (t1 & t4)) ^ ((t1 ^ t2) ^ (t3 & t1)))) & x[3]; + y[9] = (((t1 ^ t2) & (t1 & t4)) ^ ((t1 ^ t2) ^ (t3 & t1))) & x[16]; + y[10] = (t2 ^ ((t4 ^ (t3 & t1)) & (t1 ^ t2))) & x[15]; + y[11] = ((t2 ^ ((t4 ^ (t3 & t1)) & (t1 ^ t2))) ^ (t4 ^ ((t2 ^ (t3 & t1)) & (t3 ^ t4)))) & x[1]; + y[12] = (((t2 ^ ((t4 ^ (t3 & t1)) & (t1 ^ t2))) ^ (t4 ^ ((t2 ^ (t3 & t1)) & (t3 ^ t4)))) ^ t5) & x[4]; + y[13] = t5 & x[2]; + y[14] = ((t4 ^ ((t2 ^ (t3 & t1)) & (t3 ^ t4))) ^ (((t3 ^ t4) & (t2 & t3)) ^ ((t3 ^ t4) ^ (t3 & t1)))) & x[5]; + y[15] = (((t3 ^ t4) & (t2 & t3)) ^ ((t3 ^ t4) ^ (t3 & t1))) & x[6]; + y[16] = (t4 ^ ((t2 ^ (t3 & t1)) & (t3 ^ t4))) & x[0]; + y[17] = ((t2 ^ ((t4 ^ (t3 & t1)) & (t1 ^ t2))) ^ (((t1 ^ t2) & (t1 & t4)) ^ ((t1 ^ t2) ^ (t3 & t1)))) & x[12]; + return y; + endfunction + // AES Sbox Forward Bottom Layer + function automatic logic [7:0] linear_bottom_layer(input logic [17:0] x); + logic [7:0] y; + y[0] = ((x[12] ^ (x[17] ^ x[11])) ^~ ((x[8] ^ (x[1] ^ x[9])) ^ (x[14] ^ x[16]))); + y[1] = ((x[0] ^ (x[11] ^ x[12])) ^~ ((x[1] ^ x[9]) ^ (x[3] ^ (x[4] ^ x[8])))); + y[2] = (((x[12] ^ (x[17] ^ x[11])) ^ (x[3] ^ (x[4] ^ x[8]))) ^ ((x[10] ^ (x[14] ^ x[16])) ^ (x[7] ^ (x[0] ^ x[6])))); + y[3] = (((x[11] ^ x[12]) ^ (x[0] ^ x[6])) ^ ((x[15] ^ x[5]) ^ (x[16] ^ x[1]))); + y[4] = ((x[12] ^ (x[17] ^ x[11])) ^ ((x[0] ^ x[6]) ^ (x[14] ^ (x[15] ^ x[5])))); + y[5] = ((x[13] ^ (x[4] ^ x[8])) ^~ ((x[10] ^ (x[14] ^ x[16])) ^ (x[2] ^ x[11]))); + y[6] = ((x[6] ^ (x[11] ^ x[12])) ^~ ((x[14] ^ (x[15] ^ x[5])) ^ (x[2] ^ x[3]))); + y[7] = ((x[12] ^ (x[17] ^ x[11])) ^ ((x[5] ^ (x[0] ^ x[6])) ^ (x[2] ^ x[3]))); + return y; + endfunction + // AES Sbox Inverse Top Layer + function automatic logic [20:0] aes_sbox_inv_top(input logic [7:0] x); + return { + ((x[4] ^ x[3]) ^ (x[2] ^~ x[1])), + (x[5] ^~ (x[4] ^ x[3])), + (x[3] ^~ x[0]), + (x[7] ^ x[4]), + (x[6] ^~ x[4]), + ((x[3] ^~ x[0]) ^ (x[6] ^ x[1])), + ((x[6] ^~ x[4]) ^ (x[1] ^ x[0])), + (x[5] ^~ ((x[6] ^~ x[4]) ^ (x[1] ^ x[0]))), + ((x[6] ^ x[1]) ^ (x[5] ^~ x[3])), + (((x[7] ^~ x[6]) ^ (x[3] ^~ x[0])) ^ ((x[4] ^ x[3]) ^ (x[2] ^~ x[1]))), + (((x[7] ^~ x[6]) ^ (x[3] ^~ x[0])) ^ (x[2] ^~ x[1])), + ((x[7] ^~ x[6]) ^ (x[1] ^ x[0])), + ((x[7] ^~ x[6]) ^ (x[3] ^~ x[0])), + (x[0] ^~ (x[4] ^ x[3])), + (x[6] ^~ (x[7] ^ x[4])), + ((x[6] ^~ x[4]) ^ (x[5] ^~ x[2])), + (x[3] ^ (x[6] ^~ (x[7] ^ x[4]))), + ((x[4] ^ x[3]) ^ (x[1] ^ x[0])), + (x[7] ^~ x[6]), + (x[4] ^ x[3]), + (x[7] ^ (x[5] ^~ x[2])) + }; + endfunction + // AES Sbox Inverse Bottom Layer + function automatic logic [7:0] aes_sbox_inv_out(input logic [17:0] x); + logic [7:0] y; + y[0] = ((x[5] ^ x[13]) ^ (x[7] ^ x[11])); + y[1] = ((x[17] ^ x[12]) ^ (((x[2] ^ x[11]) ^ (x[8] ^ x[9])) ^ (x[0] ^ x[3]))); + y[2] = (((x[4] ^ x[12]) ^ (x[15] ^ x[0])) ^ ((x[14] ^ x[1]) ^ ((x[2] ^ x[11]) ^ (x[8] ^ x[9])))); + y[3] = ((((x[2] ^ x[11]) ^ (x[8] ^ x[9])) ^ (x[0] ^ x[3])) ^ ((x[7] ^ (x[16] ^ x[6])) ^ (x[13] ^ (x[14] ^ x[1])))); + y[4] = ((x[14] ^ x[16]) ^ ((x[4] ^ x[12]) ^ ((x[2] ^ x[11]) ^ (x[8] ^ x[9])))); + y[5] = ((x[8] ^ (x[4] ^ x[12])) ^ (((x[2] ^ x[11]) ^ (x[15] ^ x[0])) ^ ((x[17] ^ x[10]) ^ (x[7] ^ (x[16] ^ x[6]))))); + y[6] = (((x[5] ^ x[13]) ^ ((x[2] ^ x[11]) ^ (x[15] ^ x[0]))) ^ ((x[4] ^ x[9]) ^ ((x[16] ^ x[6]) ^ (x[17] ^ x[10])))); + y[7] = ((x[17] ^ x[1]) ^ ((x[4] ^ x[12]) ^ ((x[2] ^ x[11]) ^ (x[8] ^ x[9])))); + return y; + endfunction + +endpackage diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 254721b2001..48736329e3e 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -39,7 +39,7 @@ package ariane_pkg; // we could in principle do without the commit queue in this case, but the timing degrades if we do that due // to longer paths into the commit stage // if CVA6Cfg.DCacheType = cva6_config_pkg::WB - // allocate more space for the commit buffer to be on the save side, this needs to be a power of two + // allocate more space for the commit buffer to be on the safe side, this needs to be a power of two localparam logic [2:0] DEPTH_COMMIT = 'd4; // Transprecision float unit @@ -54,6 +54,7 @@ package ariane_pkg; localparam logic [31:0] OPENHWGROUP_MVENDORID = 32'h0602; localparam logic [31:0] ARIANE_MARCHID = 32'd3; + localparam logic [31:0] ARIANE_MIMPID = 32'd0; // 32 registers localparam REG_ADDR_SIZE = 5; @@ -108,11 +109,12 @@ package ariane_pkg; localparam bit ZERO_TVAL = 1'b0; `endif - // read mask for SSTATUS over MMSTATUS + // read mask for SSTATUS over MSTATUS function automatic logic [63:0] smode_status_read_mask(config_pkg::cva6_cfg_t Cfg); return riscv::SSTATUS_UIE | riscv::SSTATUS_SIE | riscv::SSTATUS_SPIE + | riscv::SSTATUS_UBE | riscv::SSTATUS_SPP | riscv::SSTATUS_FS | riscv::SSTATUS_XS @@ -196,7 +198,8 @@ package ariane_pkg; FPU, // 7 FPU_VEC, // 8 CVXIF, // 9 - ACCEL // 10 + ACCEL, // 10 + AES // 11 } fu_t; // Index of writeback ports @@ -252,6 +255,7 @@ package ariane_pkg; localparam int unsigned ICACHE_SET_ASSOC = `CONFIG_L1I_ASSOCIATIVITY; localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(`CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN - ICACHE_INDEX_WIDTH; + localparam int unsigned AXI_USER_WIDTH = 64; localparam int unsigned ICACHE_USER_LINE_WIDTH = (AXI_USER_WIDTH == 1) ? 4 : 128; // in bit // D$ localparam int unsigned DCACHE_LINE_WIDTH = `CONFIG_L1D_CACHELINE_WIDTH; @@ -361,6 +365,11 @@ package ariane_pkg; AMO_MAXDU, AMO_MIND, AMO_MINDU, + // cache block operations (CBO) + CBO_CLEAN, + CBO_FLUSH, + CBO_INVAL, + CBO_NONE, // Multiplications MUL, MULH, @@ -496,9 +505,46 @@ package ariane_pkg; BREV8, // Zip instructions UNZIP, - ZIP + ZIP, + // Xperm instructions + XPERM8, + XPERM4, + // AES Encryption instructions + AES32ESI, + AES32ESMI, + AES64ES, + AES64ESM, + // AES Decryption instructions + AES32DSI, + AES32DSMI, + AES64DS, + AES64DSM, + AES64IM, + // AES Key-Schedule instructions + AES64KS1I, + AES64KS2, + // Hashing instructions + SHA256SIG0, + SHA256SIG1, + SHA256SUM0, + SHA256SUM1, + SHA512SIG0H, + SHA512SIG0L, + SHA512SIG1H, + SHA512SIG1L, + SHA512SUM0R, + SHA512SUM1R, + SHA512SIG0, + SHA512SIG1, + SHA512SUM0, + SHA512SUM1 } fu_op; + typedef struct packed { + logic rs1_from_rd; + logic rs2_from_rd; + } alu_bypass_t; + function automatic logic op_is_branch(input fu_op op); unique case (op) inside EQ, NE, LTS, GES, LTU, GEU: return 1'b1; @@ -534,7 +580,7 @@ package ariane_pkg; [FSD : FSB], // FP Stores [FADD : FMIN_MAX], // Computational Operations (no sqrt) [FMADD : FNMADD], // Fused Computational Operations - FCVT_F2F, // Vectorial F2F Conversions requrie target + FCVT_F2F, // Vectorial F2F Conversions require target [FSGNJ : FMV_F2X], // Sign Injections and moves mapped to SGNJ FCMP, // Comparisons [VFMIN : VFCPKCD_D]: @@ -574,6 +620,17 @@ package ariane_pkg; endcase endfunction + function automatic logic fd_changes_rd_state(input fu_op op); + unique case (op) inside + FSD, FSW, FSH, FSB, // stores + FCVT_F2I, // conversion to int + FMV_F2X, // move as-is to int + FCLASS: // classification (writes output to integer register) + return 1'b0; // floating-point registers are only read + default: return 1'b1; // other ops - floating-point registers are written as well + endcase + endfunction + function automatic logic is_amo(fu_op op); case (op) inside [AMO_LRW : AMO_MINDU]: begin @@ -753,6 +810,7 @@ package ariane_pkg; end LH, LHU, HLV_H, HLV_HU, HLVX_HU, SH, HSV_H, FLH, FSH: return 2'b01; LB, LBU, HLV_B, HLV_BU, SB, HSV_B, FLB, FSB: return 2'b00; + CBO_CLEAN, CBO_FLUSH, CBO_INVAL: return 2'b00; default: return 2'b11; endcase endfunction @@ -807,4 +865,12 @@ package ariane_pkg; return gppn; endfunction : make_gppn + // ---------------------- + // Helper functions + // ---------------------- + // Avoid negative array slices when defining parametrized sizes + function automatic int unsigned avoid_neg(int n); + return (n < 0) ? 0 : n; + endfunction : avoid_neg + endpackage diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index dae76f63c25..baa0a556880 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -26,20 +26,20 @@ package build_config_pkg; int unsigned DCACHE_OFFSET_WIDTH = $clog2(CVA6Cfg.DcacheLineWidth / 8); // MMU - int unsigned VpnLen = (CVA6Cfg.XLEN == 64) ? (CVA6Cfg.RVH ? 29 : 27) : 20; - int unsigned PtLevels = (CVA6Cfg.XLEN == 64) ? 3 : 2; + int unsigned VpnLen = IS_XLEN64 ? (CVA6Cfg.RVH ? 29 : 27) : 20; + int unsigned PtLevels = IS_XLEN64 ? 3 : 2; config_pkg::cva6_cfg_t cfg; cfg.XLEN = CVA6Cfg.XLEN; cfg.VLEN = CVA6Cfg.VLEN; - cfg.PLEN = (CVA6Cfg.XLEN == 32) ? 34 : 56; - cfg.GPLEN = (CVA6Cfg.XLEN == 32) ? 34 : 41; + cfg.PLEN = IS_XLEN32 ? 34 : 56; + cfg.GPLEN = IS_XLEN32 ? 34 : 41; cfg.IS_XLEN32 = IS_XLEN32; cfg.IS_XLEN64 = IS_XLEN64; cfg.XLEN_ALIGN_BYTES = $clog2(CVA6Cfg.XLEN / 8); - cfg.ASID_WIDTH = (CVA6Cfg.XLEN == 64) ? 16 : 1; - cfg.VMID_WIDTH = (CVA6Cfg.XLEN == 64) ? 14 : 1; + cfg.ASID_WIDTH = IS_XLEN64 ? 16 : 1; + cfg.VMID_WIDTH = IS_XLEN64 ? 14 : 1; cfg.FpgaEn = CVA6Cfg.FpgaEn; cfg.FpgaAlteraEn = CVA6Cfg.FpgaAlteraEn; @@ -50,6 +50,9 @@ package build_config_pkg; cfg.NrIssuePorts = unsigned'(CVA6Cfg.SuperscalarEn ? 2 : 1); cfg.SpeculativeSb = CVA6Cfg.SuperscalarEn; + cfg.NrALUs = CVA6Cfg.SuperscalarEn ? unsigned'(2) : unsigned'(1); + cfg.ALUBypass = CVA6Cfg.SuperscalarEn ? bit'(CVA6Cfg.ALUBypass) : bit'(0); + cfg.NrLoadPipeRegs = CVA6Cfg.NrLoadPipeRegs; cfg.NrStorePipeRegs = CVA6Cfg.NrStorePipeRegs; cfg.AxiAddrWidth = CVA6Cfg.AxiAddrWidth; @@ -64,7 +67,7 @@ package build_config_pkg; cfg.XF16ALT = CVA6Cfg.XF16ALT; cfg.XF8 = CVA6Cfg.XF8; cfg.RVA = CVA6Cfg.RVA; - cfg.RVB = CVA6Cfg.RVB; + cfg.RVB = CVA6Cfg.RVB || CVA6Cfg.ZKN; // ZKN requires RVB cfg.ZKN = CVA6Cfg.ZKN; cfg.RVV = CVA6Cfg.RVV; cfg.RVC = CVA6Cfg.RVC; @@ -74,7 +77,9 @@ package build_config_pkg; cfg.RVZCMP = CVA6Cfg.RVZCMP; cfg.XFVec = CVA6Cfg.XFVec; cfg.CvxifEn = CVA6Cfg.CvxifEn; + cfg.CoproType = CVA6Cfg.CoproType; cfg.RVZiCond = CVA6Cfg.RVZiCond; + cfg.RVZiCbom = CVA6Cfg.RVZiCbom; cfg.RVZicntr = CVA6Cfg.RVZicntr; cfg.RVZihpm = CVA6Cfg.RVZihpm; cfg.NR_SB_ENTRIES = CVA6Cfg.NrScoreboardEntries; @@ -102,7 +107,9 @@ package build_config_pkg; cfg.ExceptionAddress = CVA6Cfg.ExceptionAddress; cfg.RASDepth = CVA6Cfg.RASDepth; cfg.BTBEntries = CVA6Cfg.BTBEntries; + cfg.BPType = CVA6Cfg.BPType; cfg.BHTEntries = CVA6Cfg.BHTEntries; + cfg.BHTHist = CVA6Cfg.BHTHist; cfg.DmBaseAddress = CVA6Cfg.DmBaseAddress; cfg.TvalEn = CVA6Cfg.TvalEn; cfg.DirectVecOnly = CVA6Cfg.DirectVecOnly; @@ -123,6 +130,23 @@ package build_config_pkg; cfg.CachedRegionLength = CVA6Cfg.CachedRegionLength; cfg.MaxOutstandingStores = CVA6Cfg.MaxOutstandingStores; cfg.DebugEn = CVA6Cfg.DebugEn; + + cfg.Sdtrig = CVA6Cfg.Sdtrig; + cfg.SdtrigMcontrol6 = CVA6Cfg.Sdtrig ? CVA6Cfg.SdtrigMcontrol6 : 1'b0; + cfg.SdtrigIcount = CVA6Cfg.Sdtrig ? CVA6Cfg.SdtrigIcount : 1'b0; + cfg.SdtrigEtrigger = CVA6Cfg.Sdtrig ? CVA6Cfg.SdtrigEtrigger : 1'b0; + cfg.SdtrigItrigger = CVA6Cfg.Sdtrig ? CVA6Cfg.SdtrigItrigger : 1'b0; + cfg.SdtrigNrTriggers = CVA6Cfg.Sdtrig ? CVA6Cfg.SdtrigNrTriggers : 32'd0; + cfg.SdtrigMcontrol6ExecAddr = CVA6Cfg.SdtrigMcontrol6 ? CVA6Cfg.SdtrigMcontrol6ExecAddr : 1'b0; + cfg.SdtrigMcontrol6ExecData = CVA6Cfg.SdtrigMcontrol6 ? CVA6Cfg.SdtrigMcontrol6ExecData : 1'b0; + cfg.SdtrigMcontrol6Store = CVA6Cfg.SdtrigMcontrol6 ? CVA6Cfg.SdtrigMcontrol6Store : 1'b0; + cfg.SdtrigMcontrol6LoadAddr = CVA6Cfg.SdtrigMcontrol6 ? CVA6Cfg.SdtrigMcontrol6LoadAddr : 1'b0; + cfg.SdtrigMcontrol6LoadData = CVA6Cfg.SdtrigMcontrol6 ? CVA6Cfg.SdtrigMcontrol6LoadData : 1'b0; + cfg.SdtrigTriggerChaining = CVA6Cfg.SdtrigMcontrol6 ? CVA6Cfg.SdtrigTriggerChaining : 1'b0; + cfg.SdtrigSupportedActions = CVA6Cfg.Sdtrig ? (CVA6Cfg.DebugEn ? CVA6Cfg.SdtrigSupportedActions : 2'b01) : 2'b00; + cfg.SdtrigSupportedMatch = CVA6Cfg.Sdtrig ? CVA6Cfg.SdtrigSupportedMatch : 10'b00_0000_0000; + cfg.SdtrigSupportTextra = CVA6Cfg.Sdtrig ? CVA6Cfg.SdtrigSupportTextra : 1'b0; + cfg.NonIdemPotenceEn = (CVA6Cfg.NrNonIdempotentRules > 0) && (CVA6Cfg.NonIdempotentLength > 0); cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn; @@ -149,8 +173,12 @@ package build_config_pkg; cfg.DCACHE_MAX_TX = unsigned'(2 ** CVA6Cfg.MemTidWidth); cfg.DcacheFlushOnFence = CVA6Cfg.DcacheFlushOnFence; + cfg.DcacheFlushOnFenceI = CVA6Cfg.DcacheFlushOnFenceI; cfg.DcacheInvalidateOnFlush = CVA6Cfg.DcacheInvalidateOnFlush; + cfg.DcacheEccEnable = CVA6Cfg.DcacheEccEnable; + cfg.DcacheEccScrubberEnable = CVA6Cfg.DcacheEccScrubberEnable; + cfg.DATA_USER_EN = CVA6Cfg.DataUserEn; cfg.WtDcacheWbufDepth = CVA6Cfg.WtDcacheWbufDepth; cfg.FETCH_USER_WIDTH = CVA6Cfg.FetchUserWidth; @@ -162,17 +190,18 @@ package build_config_pkg; cfg.INSTR_PER_FETCH = cfg.FETCH_WIDTH / (CVA6Cfg.RVC ? 16 : 32); cfg.LOG2_INSTR_PER_FETCH = cfg.INSTR_PER_FETCH > 1 ? $clog2(cfg.INSTR_PER_FETCH) : 1; - cfg.ModeW = (CVA6Cfg.XLEN == 32) ? 1 : 4; - cfg.ASIDW = (CVA6Cfg.XLEN == 32) ? 9 : 16; - cfg.VMIDW = (CVA6Cfg.XLEN == 32) ? 7 : 14; - cfg.PPNW = (CVA6Cfg.XLEN == 32) ? 22 : 44; - cfg.GPPNW = (CVA6Cfg.XLEN == 32) ? 22 : 29; - cfg.MODE_SV = (CVA6Cfg.XLEN == 32) ? config_pkg::ModeSv32 : config_pkg::ModeSv39; + cfg.ModeW = IS_XLEN32 ? 1 : 4; + cfg.ASIDW = IS_XLEN32 ? 9 : 16; + cfg.VMIDW = IS_XLEN32 ? 7 : 14; + cfg.PPNW = IS_XLEN32 ? 22 : 44; + cfg.GPPNW = IS_XLEN32 ? 22 : 29; + cfg.MODE_SV = IS_XLEN32 ? config_pkg::ModeSv32 : config_pkg::ModeSv39; cfg.SV = (cfg.MODE_SV == config_pkg::ModeSv32) ? 32 : 39; cfg.SVX = (cfg.MODE_SV == config_pkg::ModeSv32) ? 34 : 41; cfg.InstrTlbEntries = CVA6Cfg.InstrTlbEntries; cfg.DataTlbEntries = CVA6Cfg.DataTlbEntries; cfg.UseSharedTlb = CVA6Cfg.UseSharedTlb; + cfg.SvnapotEn = CVA6Cfg.SvnapotEn; cfg.SharedTlbDepth = CVA6Cfg.SharedTlbDepth; cfg.VpnLen = VpnLen; cfg.PtLevels = PtLevels; diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 3396088024d..a68b2c14ea7 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -35,6 +35,12 @@ package config_pkg; HPDCACHE_WT_WB = 4 } cache_type_t; + /// Branch predictor parameter + typedef enum logic { + BHT = 0, // Bimodal predictor + PH_BHT = 1 // Private History Bimodal predictor + } bp_type_t; + /// Data and Address length typedef enum logic [3:0] { ModeOff = 0, @@ -45,6 +51,12 @@ package config_pkg; ModeSv64 = 11 } vm_mode_t; + /// Coprocessor type parameter + typedef enum { + COPRO_NONE, + COPRO_EXAMPLE + } copro_type_t; + localparam NrMaxRules = 16; typedef struct packed { @@ -56,7 +68,7 @@ package config_pkg; bit RVA; // Bit manipulation RISC-V extension bit RVB; - // Scalar Cryptography RISC-V entension + // Scalar Cryptography RISC-V extension bit ZKN; // Vector RISC-V extension bit RVV; @@ -72,6 +84,8 @@ package config_pkg; bit RVZCMT; // Zicond RISC-V extension bit RVZiCond; + // Zicbom RISC-V extension (cache management / CBO) + bit RVZiCbom; // Zicntr RISC-V extension bit RVZicntr; // Zihpm RISC-V extension @@ -106,6 +120,22 @@ package config_pkg; logic [63:0] HaltAddress; // Address to jump when exception logic [63:0] ExceptionAddress; + // Trigger Module Sdtrig Extension + bit Sdtrig; + bit SdtrigMcontrol6; + bit SdtrigMcontrol6ExecAddr; + bit SdtrigMcontrol6ExecData; + bit SdtrigMcontrol6Store; + bit SdtrigMcontrol6LoadAddr; + bit SdtrigMcontrol6LoadData; + bit SdtrigIcount; + bit SdtrigEtrigger; + bit SdtrigItrigger; + int SdtrigNrTriggers; + bit SdtrigTriggerChaining; + logic [1:0] SdtrigSupportedActions; + logic [9:0] SdtrigSupportedMatch; + bit SdtrigSupportTextra; // Tval Support Enable bit TvalEn; // MTVEC CSR supports only direct mode @@ -140,6 +170,8 @@ package config_pkg; logic [NrMaxRules-1:0][63:0] CachedRegionLength; // CV-X-IF coprocessor interface enable bit CvxifEn; + // Coprocessor type + copro_type_t CoproType; // NOC bus type noc_type_e NOCType; // AXI address width @@ -170,52 +202,81 @@ package config_pkg; int unsigned DcacheSetAssoc; // Data cache line width int unsigned DcacheLineWidth; - // Data cache flush on fence - bit DcacheFlushOnFence; - // Data cache invalidate on flush - bit DcacheInvalidateOnFlush; + // three configurations for cache coherency after flush: + // DcacheFlushOnFence causes dcache flush for every fence instruction + // DcacheFlushOnFenceI causes dcache flush for every fence.I instruction + // DcacheInvalidateOnFlush causes dcache to also be invalidated when flushed + // tradeoff between coherence and efficiency, depending on remaining configuration: + + // DcacheFlushOnFenceI is required for write-back caches - otherwise, + // no way to reliably write instruction memory with store instructions, + // as data and instruction cache are currently not coherent + // DcacheFlushOnFence is required for write-back caches to ensure coherency + // with other harts or DMA devices --> a fence forces all stores to commit to memory + // DcacheInvalidateOnFlush causes all dcache entries to become invalid, forcing the CPU + // to fetch data from memory after each fence --> make writes from other harts or DMAs + // visible to the CPU + // thus, DcacheFlushOnFence and DcacheInvalidateOnFlush can ensure DMA coherency at high performance cost + // using RVZiCbom can achieve the same effect at significantly lower performance cost + // hence, on uniprocessor or not cache-coherent multiprocessor SoCs, one might want to disable both and use + // explicit CBO operations for better overall performance + bit DcacheFlushOnFence; + bit DcacheFlushOnFenceI; + bit DcacheInvalidateOnFlush; + // Is Error Detection and Correction enabled in the L1D ? + bit DcacheEccEnable; + // Is Error Detection and Correction scrubber integrated in the L1D ? + bit DcacheEccScrubberEnable; // User field on data bus enable - int unsigned DataUserEn; + int unsigned DataUserEn; // Write-through data cache write buffer depth - int unsigned WtDcacheWbufDepth; + int unsigned WtDcacheWbufDepth; // User field on fetch bus enable - int unsigned FetchUserEn; + int unsigned FetchUserEn; // Width of fetch user field - int unsigned FetchUserWidth; + int unsigned FetchUserWidth; // Is FPGA optimization of CV32A6 for Xilinx and Altera - bit FpgaEn; + bit FpgaEn; // Is FPGA optimization for Altera FPGA - bit FpgaAlteraEn; - // Is Techno Cut instanciated - bit TechnoCut; + bit FpgaAlteraEn; + // Is Techno Cut instantiated + bit TechnoCut; // Enable superscalar* with 2 issue ports and 2 commit ports. - bit SuperscalarEn; + bit SuperscalarEn; + // Enable ALU-ALU bypass (superscalar mode only) + bit ALUBypass; // Number of commit ports. Forced to 2 if SuperscalarEn. - int unsigned NrCommitPorts; + int unsigned NrCommitPorts; // Load cycle latency number - int unsigned NrLoadPipeRegs; + int unsigned NrLoadPipeRegs; // Store cycle latency number - int unsigned NrStorePipeRegs; + int unsigned NrStorePipeRegs; // Scoreboard length - int unsigned NrScoreboardEntries; + int unsigned NrScoreboardEntries; // Load buffer entry buffer - int unsigned NrLoadBufEntries; + int unsigned NrLoadBufEntries; // Maximum number of outstanding stores - int unsigned MaxOutstandingStores; + int unsigned MaxOutstandingStores; // Return address stack depth - int unsigned RASDepth; + int unsigned RASDepth; // Branch target buffer entries - int unsigned BTBEntries; + int unsigned BTBEntries; + // Branch predictor type + bp_type_t BPType; // Branch history entries - int unsigned BHTEntries; + int unsigned BHTEntries; + // Branch history bits + int unsigned BHTHist; // MMU instruction TLB entries - int unsigned InstrTlbEntries; + int unsigned InstrTlbEntries; // MMU data TLB entries - int unsigned DataTlbEntries; + int unsigned DataTlbEntries; // MMU option to use shared TLB - bit unsigned UseSharedTlb; + bit unsigned UseSharedTlb; // MMU depth of shared TLB - int unsigned SharedTlbDepth; + int unsigned SharedTlbDepth; + // Option to enable Svnapot extension + bit SvnapotEn; } cva6_user_cfg_t; typedef struct packed { @@ -238,6 +299,9 @@ package config_pkg; int unsigned NrIssuePorts; bit SpeculativeSb; + int unsigned NrALUs; + bit ALUBypass; + int unsigned NrLoadPipeRegs; int unsigned NrStorePipeRegs; /// AXI parameters. @@ -263,7 +327,9 @@ package config_pkg; bit RVZCMT; bit XFVec; bit CvxifEn; + copro_type_t CoproType; bit RVZiCond; + bit RVZiCbom; bit RVZicntr; bit RVZihpm; @@ -290,36 +356,54 @@ package config_pkg; logic [63:0] ExceptionAddress; int unsigned RASDepth; int unsigned BTBEntries; + bp_type_t BPType; int unsigned BHTEntries; + int unsigned BHTHist; int unsigned InstrTlbEntries; int unsigned DataTlbEntries; bit unsigned UseSharedTlb; + bit SvnapotEn; int unsigned SharedTlbDepth; int unsigned VpnLen; int unsigned PtLevels; - logic [63:0] DmBaseAddress; - bit TvalEn; - bit DirectVecOnly; - int unsigned NrPMPEntries; - logic [63:0][63:0] PMPCfgRstVal; - logic [63:0][63:0] PMPAddrRstVal; - bit [63:0] PMPEntryReadOnly; - bit PMPNapotEn; - noc_type_e NOCType; - int unsigned NrNonIdempotentRules; + logic [63:0] DmBaseAddress; + bit TvalEn; + bit DirectVecOnly; + int unsigned NrPMPEntries; + logic [63:0][63:0] PMPCfgRstVal; + logic [63:0][63:0] PMPAddrRstVal; + bit [63:0] PMPEntryReadOnly; + bit PMPNapotEn; + noc_type_e NOCType; + int unsigned NrNonIdempotentRules; logic [NrMaxRules-1:0][63:0] NonIdempotentAddrBase; logic [NrMaxRules-1:0][63:0] NonIdempotentLength; - int unsigned NrExecuteRegionRules; + int unsigned NrExecuteRegionRules; logic [NrMaxRules-1:0][63:0] ExecuteRegionAddrBase; logic [NrMaxRules-1:0][63:0] ExecuteRegionLength; - int unsigned NrCachedRegionRules; + int unsigned NrCachedRegionRules; logic [NrMaxRules-1:0][63:0] CachedRegionAddrBase; logic [NrMaxRules-1:0][63:0] CachedRegionLength; - int unsigned MaxOutstandingStores; - bit DebugEn; - bit NonIdemPotenceEn; // Currently only used by V extension (Ara) - bit AxiBurstWriteEn; + int unsigned MaxOutstandingStores; + bit DebugEn; + bit NonIdemPotenceEn; // Currently only used by V extension (Ara) + bit AxiBurstWriteEn; + bit Sdtrig; + bit SdtrigMcontrol6; + bit SdtrigMcontrol6ExecAddr; + bit SdtrigMcontrol6ExecData; + bit SdtrigMcontrol6Store; + bit SdtrigMcontrol6LoadAddr; + bit SdtrigMcontrol6LoadData; + bit SdtrigIcount; + bit SdtrigEtrigger; + bit SdtrigItrigger; + int SdtrigNrTriggers; + bit SdtrigTriggerChaining; + logic [1:0] SdtrigSupportedActions; + logic [9:0] SdtrigSupportedMatch; + bit SdtrigSupportTextra; int unsigned ICACHE_SET_ASSOC; int unsigned ICACHE_SET_ASSOC_WIDTH; @@ -342,8 +426,12 @@ package config_pkg; int unsigned DCACHE_MAX_TX; bit DcacheFlushOnFence; + bit DcacheFlushOnFenceI; bit DcacheInvalidateOnFlush; + bit DcacheEccEnable; + bit DcacheEccScrubberEnable; + int unsigned DATA_USER_EN; int unsigned WtDcacheWbufDepth; int unsigned FETCH_USER_WIDTH; @@ -391,7 +479,6 @@ package config_pkg; assert (Cfg.NrExecuteRegionRules <= NrMaxRules); assert (Cfg.NrCachedRegionRules <= NrMaxRules); assert (Cfg.NrPMPEntries <= 64); - assert (!(Cfg.SuperscalarEn && Cfg.RVF)); assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64) else $fatal(1, "[frontend] fetch width != not supported"); // Support for disabling MIP.MSIP and MIE.MSIE in Hypervisor and Supervisor mode is not supported @@ -399,6 +486,12 @@ package config_pkg; assert (!(Cfg.RVS && !Cfg.SoftwareInterruptEn)); assert (!(Cfg.RVH && !Cfg.SoftwareInterruptEn)); assert (!(Cfg.RVZCMT && ~Cfg.MmuPresent)); + // Zcmp is incompatible with Zcd (compressed double-precision FP loads/stores, + // automatically present whenever both C and D are implemented), due to + // opcode collisions. + if (Cfg.RVZCMP && Cfg.RVC && Cfg.RVD) begin + $fatal(1, "[config] RVZCMP (Zcmp) and RVC+RVD (Zcd = C+D) are mutually exclusive"); + end // pragma translate_on endfunction diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index d7543d38213..faf8d1f8120 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -25,6 +25,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), TechnoCut: bit'(1), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(1), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -48,7 +49,9 @@ package cva6_config_pkg; RVZCMP: bit'(0), XFVec: bit'(0), CvxifEn: bit'(1), + CoproType: config_pkg::COPRO_EXAMPLE, RVZiCond: bit'(0), + RVZiCbom: bit'(0), RVZicntr: bit'(0), RVZihpm: bit'(0), NrScoreboardEntries: unsigned'(4), @@ -61,11 +64,13 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(2), BTBEntries: unsigned'(0), + BPType: config_pkg::BHT, BHTEntries: unsigned'(32), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(0), DirectVecOnly: bit'(1), - NrPMPEntries: unsigned'(8), + NrPMPEntries: unsigned'(0), PMPCfgRstVal: {64{64'h0}}, PMPAddrRstVal: {64{64'h0}}, PMPEntryReadOnly: 64'd0, @@ -82,6 +87,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(0), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(2048), IcacheSetAssoc: unsigned'(2), @@ -91,7 +111,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(2), DcacheLineWidth: unsigned'(128), DcacheFlushOnFence: bit'(0), + DcacheFlushOnFenceI: bit'(0), DcacheInvalidateOnFlush: bit'(0), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(1), WtDcacheWbufDepth: int'(8), FetchUserWidth: unsigned'(32), @@ -99,6 +122,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(2), DataTlbEntries: int'(2), UseSharedTlb: bit'(1), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(0), NrStorePipeRegs: int'(0), diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index f68b382d628..686f09a3187 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -25,6 +25,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), TechnoCut: bit'(1), SuperscalarEn: bit'(1), + ALUBypass: bit'(1), NrCommitPorts: unsigned'(1), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -48,7 +49,9 @@ package cva6_config_pkg; RVZCMP: bit'(0), XFVec: bit'(0), CvxifEn: bit'(1), + CoproType: config_pkg::COPRO_EXAMPLE, RVZiCond: bit'(0), + RVZiCbom: bit'(0), RVZicntr: bit'(0), RVZihpm: bit'(0), NrScoreboardEntries: unsigned'(8), @@ -61,7 +64,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(2), BTBEntries: unsigned'(0), + BPType: config_pkg::BHT, BHTEntries: unsigned'(32), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(0), DirectVecOnly: bit'(1), @@ -82,6 +87,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(0), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(2048), IcacheSetAssoc: unsigned'(2), @@ -91,7 +111,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(2), DcacheLineWidth: unsigned'(128), DcacheFlushOnFence: bit'(0), + DcacheFlushOnFenceI: bit'(0), DcacheInvalidateOnFlush: bit'(0), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(1), WtDcacheWbufDepth: int'(8), FetchUserWidth: unsigned'(32), @@ -99,6 +122,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(2), DataTlbEntries: int'(2), UseSharedTlb: bit'(1), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(0), NrStorePipeRegs: int'(0), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index fffd4c8aba6..c9321babc5b 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 32; localparam CVA6ConfigRVF = 0; + localparam CVA6ConfigRVD = 0; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -77,6 +78,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(1), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -85,7 +87,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -100,7 +102,9 @@ package cva6_config_pkg; RVZCMP: bit'(CVA6ConfigZcmpExtEn), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(0), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -113,7 +117,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: unsigned'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -134,6 +140,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -143,7 +164,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: bit'(0), + DcacheFlushOnFenceI: bit'(0), DcacheInvalidateOnFlush: bit'(0), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -151,6 +175,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(2), DataTlbEntries: int'(2), UseSharedTlb: bit'(1), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index b55345369a3..d0824c0b820 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 32; localparam CVA6ConfigRVF = 0; + localparam CVA6ConfigRVD = 0; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -76,6 +77,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -84,7 +86,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -99,7 +101,9 @@ package cva6_config_pkg; RVZCMP: bit'(CVA6ConfigZcmpExtEn), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(0), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -112,7 +116,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -133,6 +139,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -142,7 +163,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: bit'(0), + DcacheFlushOnFenceI: bit'(0), DcacheInvalidateOnFlush: bit'(0), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -150,6 +174,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(2), DataTlbEntries: int'(2), UseSharedTlb: bit'(1), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a60ax_config_pkg.sv b/core/include/cv64a60ax_config_pkg.sv new file mode 100644 index 00000000000..33f25973e14 --- /dev/null +++ b/core/include/cv64a60ax_config_pkg.sv @@ -0,0 +1,140 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales +// +// Copyright 2023 Commissariat a l'Energie Atomique et aux Energies +// Alternatives (CEA) +// +// Author: Tanuj Khandelwal - CEA +// Date: January, 2025 +// Description: CVA6 configuration package using the HPDcache as cache subsystem + + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 64; + localparam CVA6ConfigRvfiTrace = 1; + + localparam CVA6ConfigAxiIdWidth = 4; + localparam CVA6ConfigAxiAddrWidth = 39; + localparam CVA6ConfigAxiDataWidth = 128; + localparam CVA6ConfigDataUserWidth = 12; + + +localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + VLEN: unsigned'(64), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) + TechnoCut: bit'(0), + SuperscalarEn: bit'(0), + ALUBypass: bit'(0), + NrCommitPorts: unsigned'(2), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigAxiIdWidth), + NrLoadBufEntries: unsigned'(8), + RVF: bit'(1), + RVD: bit'(1), + XF16: bit'(0), + XF16ALT: bit'(0), + XF8: bit'(0), + RVA: bit'(1), + RVB: bit'(1), + ZKN: bit'(0), + RVV: bit'(0), + RVC: bit'(1), + RVH: bit'(0), + RVZCMT: bit'(0), + RVZCB: bit'(1), + RVZCMP: bit'(0), + XFVec: bit'(0), + CvxifEn: bit'(1), + CoproType: config_pkg::COPRO_EXAMPLE, + RVZiCond: bit'(1), + RVZicntr: bit'(1), + RVZiCbom: bit'(1), + RVZihpm: bit'(1), + NrScoreboardEntries: unsigned'(8), + PerfCounterEn: bit'(1), + MmuPresent: bit'(1), + RVS: bit'(1), + RVU: bit'(1), + SoftwareInterruptEn: bit'(1), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(2), + BTBEntries: unsigned'(16), + BPType: config_pkg::BHT, + BHTEntries: unsigned'(64), + BHTHist: unsigned'(3), + DmBaseAddress: 64'h300_0000, + TvalEn: bit'(1), + DirectVecOnly: bit'(0), + NrPMPEntries: unsigned'(8), + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(6), + ExecuteRegionAddrBase: 1024'({64'h1_0000_0000, 64'h8000_0000, 64'h300_0000, 64'h0, 64'h2000_0000, 64'h8_0000_0000, 64'h4_0000_0000}), + ExecuteRegionLength: 1024'({64'h2_0000_0000, 64'h1_0000, 64'h1000, 64'h1_0000, 64'h2000_0000, 64'h7_FFFF_FFFF, 64'h3_FFFF_FFFF}), + NrCachedRegionRules: unsigned'(2), + CachedRegionAddrBase: 1024'({64'h1_0000_0000, 64'h8000_0000}), + CachedRegionLength: 1024'({64'h2_0000_0000, 64'h1_0000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(32768), + IcacheSetAssoc: unsigned'(8), + IcacheLineWidth: unsigned'(512), + DCacheType: config_pkg::HPDCACHE_WT, + DcacheByteSize: unsigned'(32768), + DcacheSetAssoc: unsigned'(8), + DcacheLineWidth: unsigned'(512), + DcacheFlushOnFence: bit'(0), + DcacheFlushOnFenceI: bit'(0), + DcacheInvalidateOnFlush: bit'(0), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), + DataUserEn: unsigned'(0), + WtDcacheWbufDepth: int'(8), + FetchUserWidth: unsigned'(32), + FetchUserEn: unsigned'(0), + InstrTlbEntries: int'(16), + DataTlbEntries: int'(16), + UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(0), + NrStorePipeRegs: int'(0), + DcacheIdWidth: int'(3) +}; + +endpackage diff --git a/core/include/cv64a60ax_config_pkg_cvfpu-uvm.sv b/core/include/cv64a60ax_config_pkg_cvfpu-uvm.sv new file mode 100644 index 00000000000..46c1e01a5be --- /dev/null +++ b/core/include/cv64a60ax_config_pkg_cvfpu-uvm.sv @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2025 CEA* + * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + * + * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you + * may not use this file except in compliance with the License, or, at your + * option, the Apache License version 2.0. You may obtain a copy of the + * License at + * + * https://solderpad.org/licenses/SHL-2.1/ + * + * Unless required by applicable law or agreed to in writing, any work + * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + */ + + + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 64; + localparam CVA6ConfigRvfiTrace = 1; + + localparam CVA6ConfigAxiIdWidth = 4; + localparam CVA6ConfigAxiAddrWidth = 39; + localparam CVA6ConfigAxiDataWidth = 128; + localparam CVA6ConfigDataUserWidth = 12; + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + VLEN: unsigned'(64), + FpgaEn: bit'(0), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) + TechnoCut: bit'(0), + SuperscalarEn: bit'(0), + ALUBypass: bit'(0), + NrCommitPorts: unsigned'(2), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigAxiIdWidth), + NrLoadBufEntries: unsigned'(8), + RVF: bit'(1), + RVD: bit'(1), + XF16: bit'(1), + XF16ALT: bit'(1), + XF8: bit'(1), + RVA: bit'(1), + RVB: bit'(1), + ZKN: bit'(0), + RVV: bit'(0), + RVC: bit'(1), + RVH: bit'(0), + RVZCMT: bit'(0), + RVZCB: bit'(1), + RVZCMP: bit'(0), + XFVec: bit'(0), + CvxifEn: bit'(1), + CoproType: config_pkg::COPRO_EXAMPLE, + RVZiCond: bit'(1), + RVZicntr: bit'(1), + RVZiCbom: bit'(1), + RVZihpm: bit'(1), + NrScoreboardEntries: unsigned'(8), + PerfCounterEn: bit'(1), + MmuPresent: bit'(1), + RVS: bit'(1), + RVU: bit'(1), + SoftwareInterruptEn: bit'(1), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(2), + BTBEntries: unsigned'(16), + BPType: config_pkg::BHT, + BHTEntries: unsigned'(64), + BHTHist: unsigned'(3), + DmBaseAddress: 64'h300_0000, + TvalEn: bit'(1), + DirectVecOnly: bit'(0), + NrPMPEntries: unsigned'(8), + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(6), + ExecuteRegionAddrBase: + 1024'( + {64'h1_0000_0000, 64'h8000_0000, 64'h300_0000, 64'h0, 64'h2000_0000, 64'h8_0000_0000} + ), + ExecuteRegionLength: + 1024'( + {64'h2_0000_0000, 64'h1_0000, 64'h1000, 64'h1_0000, 64'h2000_0000, 64'h7_FFFF_FFFF} + ), + NrCachedRegionRules: unsigned'(2), + CachedRegionAddrBase: 1024'({64'h1_0000_0000, 64'h8000_0000}), + CachedRegionLength: 1024'({64'h2_0000_0000, 64'h1_0000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + SDTRIG: bit'(0), + Mcontrol6: bit'(0), + Icount: bit'(0), + Etrigger: bit'(0), + Itrigger: bit'(0), + AxiBurstWriteEn: bit'(1), + IcacheByteSize: unsigned'(32768), + IcacheSetAssoc: unsigned'(8), + IcacheLineWidth: unsigned'(512), + DCacheType: config_pkg::HPDCACHE_WT, + DcacheByteSize: unsigned'(32768), + DcacheSetAssoc: unsigned'(8), + DcacheLineWidth: unsigned'(512), + DcacheFlushOnFence: bit'(0), + DcacheFlushOnFenceI: bit'(0), + DcacheInvalidateOnFlush: bit'(0), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), + DataUserEn: unsigned'(0), + WtDcacheWbufDepth: int'(8), + FetchUserWidth: unsigned'(32), + FetchUserEn: unsigned'(0), + InstrTlbEntries: int'(16), + DataTlbEntries: int'(16), + UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(0), + NrStorePipeRegs: int'(0), + DcacheIdWidth: int'(3) + }; + +endpackage diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index fc6fc92bc32..707ecc1d9b6 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -44,6 +45,7 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheLineWidth = 128; localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b0; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 1; @@ -80,6 +82,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -88,7 +91,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -103,7 +106,9 @@ package cva6_config_pkg; RVZCMP: bit'(CVA6ConfigZcmpExtEn), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(0), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -116,7 +121,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -137,6 +144,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -146,7 +168,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -154,6 +179,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(16), DataTlbEntries: int'(16), UseSharedTlb: bit'(0), + SvnapotEn: bit'(1), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index 57615a1648b..7d48c655d30 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -20,6 +20,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -51,6 +52,7 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheLineWidth = 128; localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b0; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 3; @@ -87,6 +89,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -95,7 +98,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -110,7 +113,9 @@ package cva6_config_pkg; RVZCMT: bit'(0), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(1), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -123,7 +128,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -144,6 +151,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -153,7 +175,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -161,6 +186,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(16), DataTlbEntries: int'(16), UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv index 57c52b40237..7014a4c0e28 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv @@ -20,6 +20,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -49,8 +50,11 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheByteSize = 32768; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; - - localparam CVA6ConfigDcacheFlushOnFence = 1'b1; + // do not flush Dcache for EVERY fence - dramatic performance impact + // use RVZiCbom to synchronize caches with DMA devices instead + // CAUTION - a configuration with CVA6ConfigDcacheFlushOnFence might be required for different SoCs, e.g., cache-coherent SMP configurations + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b1; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 3; @@ -87,6 +91,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -95,7 +100,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -110,7 +115,9 @@ package cva6_config_pkg; RVZCMT: bit'(0), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(1), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -123,7 +130,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -144,6 +153,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -153,7 +177,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -161,6 +188,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(16), DataTlbEntries: int'(16), UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index ff1b792768d..a07c1537b26 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -44,6 +45,7 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheLineWidth = 128; localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b0; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 1; @@ -80,6 +82,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -88,7 +91,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -103,7 +106,9 @@ package cva6_config_pkg; RVZCMP: bit'(CVA6ConfigZcmpExtEn), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(0), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -116,7 +121,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -137,6 +144,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -146,7 +168,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -154,6 +179,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(16), DataTlbEntries: int'(16), UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index e66d5ca1562..b021d724403 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -43,7 +44,8 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheSetAssoc = 8; localparam CVA6ConfigDcacheLineWidth = 128; - localparam CVA6ConfigDcacheFlushOnFence = 1'b1; + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b1; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 1; @@ -80,6 +82,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -88,7 +91,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -103,7 +106,9 @@ package cva6_config_pkg; RVZCMP: bit'(CVA6ConfigZcmpExtEn), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(0), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -116,7 +121,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -137,6 +144,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -146,7 +168,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -154,6 +179,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(16), DataTlbEntries: int'(16), UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index 8a53b4618e4..51ea04765b8 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -44,6 +45,7 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheLineWidth = 128; localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b0; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 1; @@ -80,6 +82,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -88,7 +91,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -103,7 +106,9 @@ package cva6_config_pkg; RVZCMP: bit'(CVA6ConfigZcmpExtEn), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(0), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -116,7 +121,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -137,6 +144,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -146,7 +168,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -154,6 +179,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(16), DataTlbEntries: int'(16), UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index 1ddf24413e7..e611887d234 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -44,6 +45,7 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheLineWidth = 128; localparam CVA6ConfigDcacheFlushOnFence = 1'b1; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b1; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 1; @@ -80,6 +82,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -88,7 +91,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -103,7 +106,9 @@ package cva6_config_pkg; RVZCMP: bit'(CVA6ConfigZcmpExtEn), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(0), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -116,7 +121,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -137,6 +144,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -146,7 +168,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -154,6 +179,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(16), DataTlbEntries: int'(16), UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 39277797814..dfa951d3a90 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -12,7 +12,10 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; + localparam CVA6ConfigNrCommitPorts = 2; + localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -32,18 +35,19 @@ package cva6_config_pkg; localparam CVA6ConfigAxiAddrWidth = 64; localparam CVA6ConfigAxiDataWidth = 64; localparam CVA6ConfigFetchUserEn = 0; - localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigFetchUserWidth = 1; // Just not to raise warnings localparam CVA6ConfigDataUserEn = 0; localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; - localparam CVA6ConfigIcacheByteSize = 16384; + localparam CVA6ConfigIcacheByteSize = 4096; localparam CVA6ConfigIcacheSetAssoc = 4; localparam CVA6ConfigIcacheLineWidth = 128; - localparam CVA6ConfigDcacheByteSize = 16384; + localparam CVA6ConfigDcacheByteSize = 8192; localparam CVA6ConfigDcacheSetAssoc = 4; - localparam CVA6ConfigDcacheLineWidth = 128; + localparam CVA6ConfigDcacheLineWidth = 256; localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b0; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 1; @@ -80,7 +84,8 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), - NrCommitPorts: unsigned'(1), + ALUBypass: bit'(0), + NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), @@ -88,7 +93,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -103,7 +108,9 @@ package cva6_config_pkg; RVZCMT: bit'(0), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZiCbom: bit'(0), RVZicntr: bit'(1), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), @@ -116,7 +123,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -137,6 +146,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6Store: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(4), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b01}}, + SdtrigSupportedMatch: {10{10'b00_0000_0001}}, + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -145,7 +169,10 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), + DcacheEccEnable: bit'(0), + DcacheEccScrubberEnable: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), @@ -154,6 +181,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(16), DataTlbEntries: int'(16), UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cvxif_types.svh b/core/include/cvxif_types.svh index 211742e05a4..d1cdf35c558 100644 --- a/core/include/cvxif_types.svh +++ b/core/include/cvxif_types.svh @@ -16,7 +16,7 @@ logic accept; /*Is the offloaded compressed instruction (id) accepted by the coprocessor?*/ \ } -`define X_ISSUE_REQ_T(Cfg, hartit_t, id_t) struct packed { \ +`define X_ISSUE_REQ_T(Cfg, hartid_t, id_t) struct packed { \ logic [31:0] instr; /*Offloaded instruction*/ \ hartid_t hartid; /*Identification of the hart offloading the instruction*/ \ id_t id; /*Identification of the offloaded instruction*/ \ @@ -48,7 +48,7 @@ writeregflags_t we; /*Register file write enable(s)*/ \ } -`define CVXIF_REQ_T(Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t) struct packed { \ +`define CVXIF_REQ_T(Cfg, x_compressed_req_t, x_issue_req_t, x_register_t, x_commit_t) struct packed { \ logic compressed_valid; \ x_compressed_req_t compressed_req; \ logic issue_valid; \ diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/deprecated_packages/cv32a6_embedded_config_pkg_deprecated.sv similarity index 85% rename from core/include/cv32a6_embedded_config_pkg_deprecated.sv rename to core/include/deprecated_packages/cv32a6_embedded_config_pkg_deprecated.sv index e51c532ff24..7ce334a3f9c 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/deprecated_packages/cv32a6_embedded_config_pkg_deprecated.sv @@ -12,6 +12,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 32; localparam CVA6ConfigRVF = 0; + localparam CVA6ConfigRVD = 0; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -43,6 +44,7 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheLineWidth = 128; localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b0; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 1; @@ -87,7 +89,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -102,8 +104,10 @@ package cva6_config_pkg; XFVec: bit'(CVA6ConfigFVecEn), RVZCMT: bit'(0), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), RVZicntr: bit'(1), + RVZiCbom: bit'(0), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), @@ -115,7 +119,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -136,6 +142,22 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(0), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6StoreAddr: bit'(0), + SdtrigMcontrol6StoreData: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(0), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b00}}, //bit0: breakpoint except., bit1: debug request + SdtrigSupportedMatch: {3{3'b000}}, //bit0: equal, bit1: napot, bit2: not equal + SdtrigSupportTextra: bit'(0), AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -145,6 +167,7 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: unsigned'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), @@ -153,6 +176,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(2), DataTlbEntries: int'(2), UseSharedTlb: bit'(1), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/deprecated_packages/cv32a6_imac_sv0_config_pkg.sv similarity index 87% rename from core/include/cv32a6_imac_sv0_config_pkg.sv rename to core/include/deprecated_packages/cv32a6_imac_sv0_config_pkg.sv index 9caf64ab6be..8ddef340f9b 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/deprecated_packages/cv32a6_imac_sv0_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 32; localparam CVA6ConfigRVF = 0; + localparam CVA6ConfigRVD = 0; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -77,6 +78,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -85,7 +87,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -100,8 +102,10 @@ package cva6_config_pkg; RVZCMP: bit'(CVA6ConfigZcmpExtEn), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), RVZicntr: bit'(1), + RVZiCbom: bit'(0), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), @@ -113,7 +117,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: unsigned'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -134,6 +140,22 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + SDTRIG: bit'(0), + SDTRIG_AsicOpt: bit'(0), + Mcontrol6 : bit'(0), + M6ExecAddr : bit'(0), + M6ExecData : bit'(0), + M6StoreAddr: bit'(0), + M6StoreData: bit'(0), + M6LoadAddr : bit'(0), + M6LoadData : bit'(0), + Icount: bit'(0), + Etrigger: bit'(0), + Itrigger: bit'(0), + N_Triggers: int'(0), + TriggerChaining: bit'(0), + SupportedActions: {2{2'b00}}, //bit0: breakpoint except., bit1: debug request + SupportedMatch : {3{3'b000}}, //bit0: equal, bit1: napot, bit2: not equal AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -143,6 +165,7 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: bit'(0), + DcacheFlushOnFenceI: bit'(0), DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), @@ -151,6 +174,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(2), DataTlbEntries: int'(2), UseSharedTlb: bit'(1), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/deprecated_packages/cv32a6_imafc_sv32_config_pkg.sv similarity index 87% rename from core/include/cv32a6_imafc_sv32_config_pkg.sv rename to core/include/deprecated_packages/cv32a6_imafc_sv32_config_pkg.sv index 8cc23f1387d..e9a6ba097b1 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/deprecated_packages/cv32a6_imafc_sv32_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 32; localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 0; localparam CVA6ConfigF16En = 0; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -77,6 +78,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -85,7 +87,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -100,8 +102,10 @@ package cva6_config_pkg; RVZCMT: bit'(0), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), RVZicntr: bit'(1), + RVZiCbom: bit'(0), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), @@ -113,7 +117,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -134,6 +140,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6StoreAddr: bit'(0), + SdtrigMcontrol6StoreData: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(0), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b00}}, + SdtrigSupportedMatch: {3{3'b000}}, AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -143,6 +164,7 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: bit'(0), + DcacheFlushOnFenceI: bit'(0), DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), @@ -151,6 +173,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(2), DataTlbEntries: int'(2), UseSharedTlb: bit'(1), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/deprecated_packages/cv64a6_imadfcv_sv39_polara_config_pkg.sv similarity index 86% rename from core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv rename to core/include/deprecated_packages/cv64a6_imadfcv_sv39_polara_config_pkg.sv index c0ea9019222..5a532cb9403 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/deprecated_packages/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -13,6 +13,7 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigRVD = 1; localparam CVA6ConfigF16En = 1; localparam CVA6ConfigF16AltEn = 0; localparam CVA6ConfigF8En = 0; @@ -44,6 +45,7 @@ package cva6_config_pkg; localparam CVA6ConfigDcacheLineWidth = 128; localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheFlushOnFenceI = 1'b0; localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; localparam CVA6ConfigDcacheIdWidth = 1; @@ -80,6 +82,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), // for Altera (only) TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(2), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -88,7 +91,7 @@ package cva6_config_pkg; MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVD), XF16: bit'(CVA6ConfigF16En), XF16ALT: bit'(CVA6ConfigF16AltEn), XF8: bit'(CVA6ConfigF8En), @@ -103,8 +106,10 @@ package cva6_config_pkg; RVZCMT: bit'(0), XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(CVA6ConfigRVZiCond), RVZicntr: bit'(1), + RVZiCbom: bit'(0), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), @@ -116,7 +121,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(CVA6ConfigRASDepth), BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BPType: config_pkg::BHT, BHTEntries: unsigned'(CVA6ConfigBHTEntries), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(CVA6ConfigTvalEn), DirectVecOnly: bit'(0), @@ -137,6 +144,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6StoreAddr: bit'(0), + SdtrigMcontrol6StoreData: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(0), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b00}}, + SdtrigSupportedMatch: {3{3'b000}}, AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), @@ -146,6 +168,7 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), DcacheFlushOnFence: bit'(CVA6ConfigDcacheFlushOnFence), + DcacheFlushOnFenceI: bit'(CVA6ConfigDcacheFlushOnFenceI), DcacheInvalidateOnFlush: bit'(CVA6ConfigDcacheInvalidateOnFlush), DataUserEn: unsigned'(CVA6ConfigDataUserEn), WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), @@ -154,6 +177,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(16), DataTlbEntries: int'(16), UseSharedTlb: bit'(0), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/deprecated_packages/cv64a6_mmu_config_pkg.sv similarity index 83% rename from core/include/cv64a6_mmu_config_pkg.sv rename to core/include/deprecated_packages/cv64a6_mmu_config_pkg.sv index c0f1954319d..93d5e996535 100644 --- a/core/include/cv64a6_mmu_config_pkg.sv +++ b/core/include/deprecated_packages/cv64a6_mmu_config_pkg.sv @@ -32,6 +32,7 @@ package cva6_config_pkg; FpgaAlteraEn: bit'(0), TechnoCut: bit'(0), SuperscalarEn: bit'(0), + ALUBypass: bit'(0), NrCommitPorts: unsigned'(1), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -55,8 +56,10 @@ package cva6_config_pkg; RVZCMT: bit'(0), XFVec: bit'(0), CvxifEn: bit'(1), + CoproType: config_pkg::COPRO_NONE, RVZiCond: bit'(0), RVZicntr: bit'(1), + RVZiCbom: bit'(0), RVZihpm: bit'(1), NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), PerfCounterEn: bit'(0), @@ -68,7 +71,9 @@ package cva6_config_pkg; ExceptionAddress: 64'h808, RASDepth: unsigned'(2), BTBEntries: unsigned'(0), + BPType: config_pkg::BHT, BHTEntries: unsigned'(32), + BHTHist: unsigned'(3), DmBaseAddress: 64'h0, TvalEn: bit'(0), DirectVecOnly: bit'(1), @@ -89,6 +94,21 @@ package cva6_config_pkg; CachedRegionLength: 1024'({64'h40000000}), MaxOutstandingStores: unsigned'(7), DebugEn: bit'(1), + Sdtrig: bit'(0), + SdtrigMcontrol6: bit'(0), + SdtrigMcontrol6ExecAddr: bit'(0), + SdtrigMcontrol6ExecData: bit'(0), + SdtrigMcontrol6StoreAddr: bit'(0), + SdtrigMcontrol6StoreData: bit'(0), + SdtrigMcontrol6LoadAddr: bit'(0), + SdtrigMcontrol6LoadData: bit'(0), + SdtrigIcount: bit'(0), + SdtrigEtrigger: bit'(0), + SdtrigItrigger: bit'(0), + SdtrigNrTriggers: int'(0), + SdtrigTriggerChaining: bit'(0), + SdtrigSupportedActions: {2{2'b00}}, + SdtrigSupportedMatch: {3{3'b000}}, AxiBurstWriteEn: bit'(0), IcacheByteSize: unsigned'(2048), IcacheSetAssoc: unsigned'(2), @@ -98,6 +118,7 @@ package cva6_config_pkg; DcacheSetAssoc: unsigned'(8), DcacheLineWidth: unsigned'(128), DcacheFlushOnFence: bit'(0), + DcacheFlushOnFenceI: bit'(0), DcacheInvalidateOnFlush: bit'(0), DataUserEn: unsigned'(0), WtDcacheWbufDepth: int'(2), @@ -106,6 +127,7 @@ package cva6_config_pkg; InstrTlbEntries: int'(2), DataTlbEntries: int'(2), UseSharedTlb: bit'(1), + SvnapotEn: bit'(0), SharedTlbDepth: int'(64), NrLoadPipeRegs: int'(0), NrStorePipeRegs: int'(0), diff --git a/core/include/dummy_l15_pkg.sv b/core/include/dummy_l15_pkg.sv new file mode 100644 index 00000000000..179e4edfa83 --- /dev/null +++ b/core/include/dummy_l15_pkg.sv @@ -0,0 +1,116 @@ +// Attention: this is a dummy package for local compilation. +// The real package, with properly defined parameters, is in OpenPiton. + +package l15_pkg; + + parameter int unsigned L15_PADDR_WIDTH = 40; // Physical address bus in OpenPiton is 40 + parameter int unsigned L15_WORD_WIDTH = 64; + parameter int unsigned L15_DATA_BUS_WIDTH = 256; // Hardcoded for the moment, changed on parametric cachelines + parameter int unsigned L15_DATA_BUS_WORDS = L15_DATA_BUS_WIDTH / L15_WORD_WIDTH; + parameter int unsigned L15_BE_WIDTH = L15_DATA_BUS_WIDTH / 8; + parameter int unsigned L15_TID_WIDTH = 2; + parameter int unsigned L15_SET_ASSOC = 4; + parameter int unsigned L15_WAY_WIDTH = $clog2(L15_SET_ASSOC); + parameter int unsigned L15_TLB_CSM_WIDTH = 33; + + typedef enum logic [4:0] { + L15_LOAD_RQ = 5'b00000, // load request + L15_IMISS_RQ = 5'b10000, // instruction fill request + L15_STORE_RQ = 5'b00001, // store request + L15_ATOMIC_RQ = 5'b00110, // atomic op + //L15_CAS1_RQ = 5'b00010, // compare and swap1 packet (OpenSparc atomics) + //L15_CAS2_RQ = 5'b00011, // compare and swap2 packet (OpenSparc atomics) + //L15_SWAP_RQ = 5'b00110, // swap packet (OpenSparc atomics) + L15_STRLOAD_RQ = 5'b00100, // unused + L15_STRST_RQ = 5'b00101, // unused + L15_STQ_RQ = 5'b00111, // unused + L15_INT_RQ = 5'b01001, // interrupt request + L15_FWD_RQ = 5'b01101, // unused + L15_FWD_RPY = 5'b01110, // unused + L15_RSVD_RQ = 5'b11111 // unused + } l15_reqtypes_e; + + typedef enum logic [3:0] { + L15_LOAD_RET = 4'b0000, // load packet + //L15_INV_RET = 4'b0011, // invalidate packet, not unique... + L15_ST_ACK = 4'b0100, // store ack packet + //L15_AT_ACK = 4'b0011, // unused, not unique... + L15_INT_RET = 4'b0111, // interrupt packet + L15_TEST_RET = 4'b0101, // unused + L15_FP_RET = 4'b1000, // unused + L15_IFILL_RET = 4'b0001, // instruction fill packet + L15_EVICT_REQ = 4'b0011, // eviction request + L15_ERR_RET = 4'b1100, // unused + L15_STRLOAD_RET = 4'b0010, // unused + L15_STRST_ACK = 4'b0110, // unused + L15_FWD_RQ_RET = 4'b1010, // unused + L15_FWD_RPY_RET = 4'b1011, // unused + L15_RSVD_RET = 4'b1111, // unused + L15_CPX_RESTYPE_ATOMIC_RES = 4'b1110 // custom type for atomic responses + } l15_rtrntypes_e; + + typedef enum logic [3:0] { + AMO_NONE = 4'b0000, + AMO_LR = 4'b0001, + AMO_SC = 4'b0010, + AMO_SWAP = 4'b0011, + AMO_ADD = 4'b0100, + AMO_AND = 4'b0101, + AMO_OR = 4'b0110, + AMO_XOR = 4'b0111, + AMO_MAX = 4'b1000, + AMO_MAXU = 4'b1001, + AMO_MIN = 4'b1010, + AMO_MINU = 4'b1011, + AMO_CAS1 = 4'b1100, // unused, not part of riscv spec, but provided in OpenPiton + AMO_CAS2 = 4'b1101 // unused, not part of riscv spec, but provided in OpenPiton + } l15_amo_e; + + typedef struct packed { + logic l15_val; // valid signal, asserted with request + logic l15_req_ack; // ack for response + l15_reqtypes_e l15_rqtype; // see below for encoding + logic l15_nc; // non-cacheable bit + logic [2:0] l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) + logic [L15_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1 + logic l15_prefetch; // unused in openpiton + logic l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment + logic l15_blockstore; // unused in openpiton + logic l15_blockinitstore; // unused in openpiton + logic [L15_WAY_WIDTH-1:0] l15_l1rplway; // way to replace + logic [L15_PADDR_WIDTH-1:0] l15_address; // physical address + logic [L15_WORD_WIDTH-1:0] l15_data; // word to write + logic [L15_WORD_WIDTH-1:0] l15_data_next_entry; // unused in Ariane (only used for CAS atomic requests) + logic [L15_TLB_CSM_WIDTH-1:0] l15_csm_data; // unused in Ariane + l15_amo_e l15_amo_op; // atomic operation type + logic [L15_BE_WIDTH-1:0] l15_be; + } l15_req_t; + + typedef struct packed { + logic l15_ack; // ack for request struct + logic l15_header_ack; // ack for request struct + logic l15_val; // valid signal for return struct + l15_rtrntypes_e l15_returntype; // see below for encoding + logic l15_l2miss; // unused in Ariane + logic [1:0] l15_error; // unused in openpiton + logic l15_noncacheable; // non-cacheable bit + logic l15_atomic; // asserted in load return and store ack packets of atomic tx + logic [L15_TID_WIDTH-1:0] l15_threadid; // used as transaction ID + logic l15_prefetch; // unused in openpiton + logic l15_f4b; // 4byte instruction fill from I/O space (nc). + logic [L15_WORD_WIDTH-1:0] l15_data_0; // used for both caches + logic [L15_WORD_WIDTH-1:0] l15_data_1; // used for both caches + logic [L15_WORD_WIDTH-1:0] l15_data_2; // currently only used for I$ + logic [L15_WORD_WIDTH-1:0] l15_data_3; // currently only used for I$ + logic l15_inval_icache_all_way; // invalidate all ways + logic l15_inval_dcache_all_way; // unused in openpiton + logic [L15_PADDR_WIDTH-1:0] l15_inval_address; // invalidate selected cacheline + logic l15_cross_invalidate; // unused in openpiton + logic [L15_WAY_WIDTH-1:0] l15_cross_invalidate_way; // unused in openpiton + logic l15_inval_dcache_inval; // invalidate selected cacheline and way + logic l15_inval_icache_inval; // unused in openpiton + logic [L15_WAY_WIDTH-1:0] l15_inval_way; // way to invalidate + logic l15_blockinitstore; // unused in openpiton + } l15_rtrn_t; + +endpackage diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv index e9dbc65a189..20e81f8fbc2 100644 --- a/core/include/riscv_pkg.sv +++ b/core/include/riscv_pkg.sv @@ -37,6 +37,7 @@ package riscv; // type which holds xlen typedef enum logic [1:0] { + XLEN_NA = 2'b00, // Used for mstatus.{S/U}XL when {S/U} not implemented XLEN_32 = 2'b01, XLEN_64 = 2'b10, XLEN_128 = 2'b11 @@ -49,6 +50,13 @@ package riscv; Dirty = 2'b11 } xs_t; + typedef enum logic [1:0] { + CBIE_ILLEGAL = 2'b00, // execution of CBO.INVAL in lower privilege mode causes illegal instruction / virtual instruction exception + CBIE_FLUSH = 2'b01, // CBO.INVAL causes flush + CBIE_RSVD = 2'b10, // reserved + CBIE_INVAL = 2'b11 // CBO.INVAL causes invalidate + } cbie_t; + typedef struct packed { logic sd; // signal dirty state - read-only logic [62:34] wpri6; // writes preserved reads ignored @@ -341,11 +349,13 @@ package riscv; localparam logic [XLEN-1:0] INSTR_PAGE_FAULT = 12; // Instruction page fault localparam logic [XLEN-1:0] LOAD_PAGE_FAULT = 13; // Load page fault localparam logic [XLEN-1:0] STORE_PAGE_FAULT = 15; // Store page fault + localparam logic [XLEN-1:0] HARDWARE_ERROR = 19; // Transient error (e.g., bit-flip error in caches' SRAMs) localparam logic [XLEN-1:0] INSTR_GUEST_PAGE_FAULT = 20; // Instruction guest-page fault localparam logic [XLEN-1:0] LOAD_GUEST_PAGE_FAULT = 21; // Load guest-page fault localparam logic [XLEN-1:0] VIRTUAL_INSTRUCTION = 22; // virtual instruction localparam logic [XLEN-1:0] STORE_GUEST_PAGE_FAULT = 23; // Store guest-page fault localparam logic [XLEN-1:0] DEBUG_REQUEST = 24; // Debug request + localparam logic [XLEN-1:0] DEBUG_TRIGGER = 25; // Debug request from a trigger with action=1 localparam int unsigned IRQ_S_SOFT = 1; localparam int unsigned IRQ_VS_SOFT = 2; @@ -643,6 +653,8 @@ package riscv; CSR_TDATA2 = 12'h7A2, CSR_TDATA3 = 12'h7A3, CSR_TINFO = 12'h7A4, + CSR_MCONTEXT = 12'h7A8, + CSR_SCONTEXT = 12'h5A8, // Debug CSR CSR_DCSR = 12'h7b0, CSR_DPC = 12'h7b1, @@ -719,6 +731,7 @@ package riscv; localparam logic [63:0] SSTATUS_UIE = 'h00000001; localparam logic [63:0] SSTATUS_SIE = 'h00000002; localparam logic [63:0] SSTATUS_SPIE = 'h00000020; + localparam logic [63:0] SSTATUS_UBE = 'h00000040; localparam logic [63:0] SSTATUS_SPP = 'h00000100; localparam logic [63:0] SSTATUS_FS = 'h00006000; localparam logic [63:0] SSTATUS_XS = 'h00018000; @@ -749,7 +762,8 @@ package riscv; localparam logic [63:0] MSTATUS_MIE = 'h00000008; localparam logic [63:0] MSTATUS_UPIE = 'h00000010; localparam logic [63:0] MSTATUS_SPIE = 'h00000020; - localparam logic [63:0] MSTATUS_HPIE = 'h00000040; + localparam logic [63:0] MSTATUS_UBE = 'h00000040; + localparam logic [63:0] MSTATUS_HPIE = 'h00000040; // TODO - delete old version of H extension localparam logic [63:0] MSTATUS_MPIE = 'h00000080; localparam logic [63:0] MSTATUS_SPP = 'h00000100; localparam logic [63:0] MSTATUS_HPP = 'h00000600; @@ -762,6 +776,8 @@ package riscv; localparam logic [63:0] MSTATUS_TVM = 'h00100000; localparam logic [63:0] MSTATUS_TW = 'h00200000; localparam logic [63:0] MSTATUS_TSR = 'h00400000; + localparam logic [63:0] MSTATUS_SBE = 64'h1000000000; + localparam logic [63:0] MSTATUS_MBE = 64'h2000000000; function automatic logic [63:0] mstatus_uxl(logic IS_XLEN64); return {30'h0000000, IS_XLEN64, IS_XLEN64, 32'h00000000}; endfunction @@ -771,6 +787,8 @@ package riscv; function automatic logic [63:0] mstatus_sd(logic IS_XLEN64); return {IS_XLEN64, 31'h00000000, ~IS_XLEN64, 31'h00000000}; endfunction + localparam logic [63:0] MSTATUSH_SBE = 'h10; + localparam logic [63:0] MSTATUSH_MBE = 'h20; localparam logic [63:0] MENVCFG_FIOM = 'h00000001; localparam logic [63:0] MENVCFG_CBIE = 'h00000030; diff --git a/core/include/rvfi_types.svh b/core/include/rvfi_types.svh index 69c552e7a31..771169f5697 100644 --- a/core/include/rvfi_types.svh +++ b/core/include/rvfi_types.svh @@ -126,6 +126,10 @@ logic [Cfg.PLEN-1:0] mem_paddr; \ logic debug_mode; \ logic [Cfg.NrCommitPorts-1:0][Cfg.XLEN-1:0] wdata; \ + logic branch_valid; \ + logic is_taken; \ + logic [Cfg.XLEN-1:0] tval; \ + logic [Cfg.TRANS_ID_BITS-1:0] branch_trans_id; \ } `define RVFI_PROBES_CSR_T(Cfg) struct packed { \ @@ -164,4 +168,18 @@ logic [63:0][Cfg.PLEN-3:0] pmpaddr_q; \ } +`define RVFI_TO_ITI_T(Cfg) struct packed { \ + logic [Cfg.NrCommitPorts-1:0] valid; \ + logic [Cfg.NrCommitPorts-1:0][Cfg.VLEN-1:0] pc; \ + ariane_pkg::fu_op [Cfg.NrCommitPorts-1:0] op; \ + logic [Cfg.NrCommitPorts-1:0] is_compressed; \ + logic [Cfg.NrCommitPorts-1:0] branch_valid; \ + logic [Cfg.NrCommitPorts-1:0] is_taken; \ + logic ex_valid; \ + logic [Cfg.XLEN-1:0] tval; \ + logic [Cfg.XLEN-1:0] cause; \ + riscv::priv_lvl_t priv_lvl; \ + logic [63:0] cycles; \ +} + `endif // RVFI_TYPES_SVH diff --git a/core/include/triggers_pkg.sv b/core/include/triggers_pkg.sv new file mode 100644 index 00000000000..3b6ad257c3c --- /dev/null +++ b/core/include/triggers_pkg.sv @@ -0,0 +1,146 @@ +package triggers_pkg; + // Triggers + typedef struct packed { + logic [31:28] t_type; // type 3 for icount + logic dmode; + logic vs; + logic vu; + logic hit; + logic [23:10] count; + logic m; + logic pending; + logic s; + logic u; + logic [5:0] action; + } icount32_tdata1_t; + + typedef struct packed { + logic [31:26] mhvalue; + logic [25:23] mhselect; + logic [22:20] zeroes; + logic [19:18] sbytemask; + logic [17:2] svalue; + logic [1:0] sselect; + } textra32_tdata3_t; + + typedef struct packed { + logic [63:51] mhvalue; + logic [50:48] mhselect; + logic [47:40] zeroes; + logic [39:36] sbytemask; + logic [35:34] zero_field; + logic [33:2] svalue; + logic [1:0] sselect; + } textra64_tdata3_t; + + typedef struct packed { + logic [31:28] t_type; // type 6 for mcontrol6 + logic dmode; + logic uncertain; + logic hit1; + logic vs; + logic vu; + logic hit0; + logic select; + logic [20:19] zeroes; + logic [18:16] size; + logic [15:12] action; + logic chain; + logic [10:7] match; + logic m; + logic uncertainen; + logic s; + logic u; + logic execute; + logic store; + logic load; + } mcontrol6_32_tdata1_t; + + typedef struct packed { + logic [31:28] t_type; // type 4 for etrigger + logic dmode; + logic hit; + logic [25:13] zeroed; + logic vs; + logic vu; + logic nmi; + logic m; + logic zero; + logic s; + logic u; + logic [5:0] action; + } itrigger32_tdata1_t; + + typedef struct packed { + logic [31:28] t_type; // type 5 for etrigger + logic dmode; + logic hit; + logic [25:13] zeroes; + logic vs; + logic vu; + logic zeroed; + logic m; + logic zero; + logic s; + logic u; + logic [5:0] action; + } etrigger32_tdata1_t; + + typedef union packed { + logic [31:0] tdata1_type; + mcontrol6_32_tdata1_t mc6_type; + etrigger32_tdata1_t etrigger_type; + itrigger32_tdata1_t itrigger_type; + icount32_tdata1_t icount_type; + } trigger_32_tdata1_type; + + function automatic logic napot_match32(logic [31:0] base, logic [31:0] value); + logic [31:0] mask; + + mask = ~(base ^ (base + 1)); + return (value & mask) == (base & mask); + endfunction + + function automatic logic napot_match64(logic [63:0] base, logic [63:0] value); + logic [63:0] mask; + + mask = ~(base ^ (base + 1)); + return (value & mask) == (base & mask); + endfunction + + function automatic logic match_scontext32(input logic [31:0] scontext, input logic [1:0] sselect, + input logic [1:0] sbytemask, input logic [15:0] svalue, + input logic flag); + logic match; + int max_bytes = 0; + match = 1'b1; + if (sselect == 2'd1) begin + max_bytes = (flag) ? 4 : 2; + for (int b = 0; b < max_bytes; b++) begin + if (!sbytemask[b]) begin + if (scontext[8*b+:8] != svalue[8*b+:8]) match = 1'b0; + end + end + end + return match; + endfunction + + function automatic logic match_scontext64(input logic [31:0] scontext, input logic [1:0] sselect, + input logic [3:0] sbytemask, input logic [31:0] svalue, + input logic flag); + logic match; + int max_bytes = 0; + match = 1'b1; + if (sselect == 2'd1) begin + max_bytes = (flag) ? 4 : 2; + for (int b = 0; b < max_bytes; b++) begin + if (!sbytemask[b]) begin + if (scontext[8*b+:8] != svalue[8*b+:8]) match = 1'b0; + end + end + end + return match; + endfunction + + +endpackage diff --git a/core/include/wt_cache_pkg.sv b/core/include/wt_cache_pkg.sv index 38ea500e126..d35a7c97a57 100644 --- a/core/include/wt_cache_pkg.sv +++ b/core/include/wt_cache_pkg.sv @@ -15,31 +15,8 @@ // this is needed to propagate the // configuration in case Ariane is // instantiated in OpenPiton -`ifdef PITON_ARIANE -`include "l15.tmp.h" -`include "define.tmp.h" -`endif - package wt_cache_pkg; - // these parames need to coincide with the - // L1.5 parameterization, do not change -`ifdef PITON_ARIANE - -`ifndef CONFIG_L15_ASSOCIATIVITY - `define CONFIG_L15_ASSOCIATIVITY 4 -`endif - -`ifndef TLB_CSM_WIDTH - `define TLB_CSM_WIDTH 33 -`endif - - localparam L15_SET_ASSOC = `CONFIG_L15_ASSOCIATIVITY; - localparam L15_TLB_CSM_WIDTH = `TLB_CSM_WIDTH; -`else - localparam L15_TLB_CSM_WIDTH = 33; -`endif - // FIFO depths of L15 adapter localparam ADAPTER_REQ_FIFO_DEPTH = 2; localparam ADAPTER_RTRN_FIFO_DEPTH = 2; @@ -70,46 +47,7 @@ package wt_cache_pkg; ICACHE_IFILL_ACK } icache_in_t; - // taken from iop.h in openpiton - // to l1.5 (only marked subset is used) - typedef enum logic [4:0] { - L15_LOAD_RQ = 5'b00000, // load request - L15_IMISS_RQ = 5'b10000, // instruction fill request - L15_STORE_RQ = 5'b00001, // store request - L15_ATOMIC_RQ = 5'b00110, // atomic op - //L15_CAS1_RQ = 5'b00010, // compare and swap1 packet (OpenSparc atomics) - //L15_CAS2_RQ = 5'b00011, // compare and swap2 packet (OpenSparc atomics) - //L15_SWAP_RQ = 5'b00110, // swap packet (OpenSparc atomics) - L15_STRLOAD_RQ = 5'b00100, // unused - L15_STRST_RQ = 5'b00101, // unused - L15_STQ_RQ = 5'b00111, // unused - L15_INT_RQ = 5'b01001, // interrupt request - L15_FWD_RQ = 5'b01101, // unused - L15_FWD_RPY = 5'b01110, // unused - L15_RSVD_RQ = 5'b11111 // unused - } l15_reqtypes_t; - - // from l1.5 (only marked subset is used) - typedef enum logic [3:0] { - L15_LOAD_RET = 4'b0000, // load packet - // L15_INV_RET = 4'b0011, // invalidate packet, not unique... - L15_ST_ACK = 4'b0100, // store ack packet - //L15_AT_ACK = 4'b0011, // unused, not unique... - L15_INT_RET = 4'b0111, // interrupt packet - L15_TEST_RET = 4'b0101, // unused - L15_FP_RET = 4'b1000, // unused - L15_IFILL_RET = 4'b0001, // instruction fill packet - L15_EVICT_REQ = 4'b0011, // eviction request - L15_ERR_RET = 4'b1100, // unused - L15_STRLOAD_RET = 4'b0010, // unused - L15_STRST_ACK = 4'b0110, // unused - L15_FWD_RQ_RET = 4'b1010, // unused - L15_FWD_RPY_RET = 4'b1011, // unused - L15_RSVD_RET = 4'b1111, // unused - L15_CPX_RESTYPE_ATOMIC_RES = 4'b1110 // custom type for atomic responses - } l15_rtrntypes_t; - - // swap endianess in a 64bit word + // swap endianness in a 64bit word function automatic logic [63:0] swendian64(input logic [63:0] in); automatic logic [63:0] out; for (int k = 0; k < 64; k += 8) begin diff --git a/core/instr_realign.sv b/core/instr_realign.sv index 3aae6ff9229..3b40ae81040 100644 --- a/core/instr_realign.sv +++ b/core/instr_realign.sv @@ -137,7 +137,6 @@ module instr_realign unaligned_d = unaligned_q; // last instruction was unaligned - // TODO how are jumps + unaligned managed? if (unaligned_q) begin // for 64 bit there exist the following options: // 64 48 32 16 0 @@ -250,7 +249,6 @@ module instr_realign end // this means the previous instruction was either compressed or unaligned // in any case we don't care - // TODO input is actually right-shifted so the code below is wrong 2'b01: begin // 64 48 32 16 0 // | 3 | 2 | 1 | 0 | <- instruction slot diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index 8f70016f071..7523d346708 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -50,6 +50,8 @@ module issue_read_operands input forwarding_t fwd_i, // FU data useful to execute instruction - EX_STAGE output fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_o, + // ALU to ALU bypass control - EX_STAGE + output alu_bypass_t alu_bypass_o, // Unregistered version of fu_data_o.operanda - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_o, // Unregistered version of fu_data_o.operandb - EX_STAGE @@ -64,6 +66,8 @@ module issue_read_operands input logic flu_ready_i, // ALU output is valid - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_o, + // AES output is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] aes_valid_o, // Branch unit is valid - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o, // Transformed trap instruction - EX_STAGE @@ -78,6 +82,8 @@ module issue_read_operands output logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_o, // FPU FU is ready - EX_STAGE input logic fpu_ready_i, + // FPU FU will perform a writeback in the next cycle - EX_STAGE + input logic fpu_early_valid_i, // FPU FU is valid - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_o, // FPU fmt field - EX_STAGE @@ -126,17 +132,18 @@ module issue_read_operands // Information dedicated to RVFI - RVFI output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs1_o, // Information dedicated to RVFI - RVFI - output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2_o - + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2_o, + // Original instruction bits for AES + output logic [5:0] orig_instr_aes_bits ); localparam OPERANDS_PER_INSTR = CVA6Cfg.NrRgprPorts / CVA6Cfg.NrIssuePorts; typedef struct packed { - logic none, load, store, alu, alu2, ctrl_flow, mult, csr, fpu, fpu_vec, cvxif, accel; + logic none, load, store, alu, alu2, ctrl_flow, mult, csr, fpu, fpu_vec, cvxif, accel, aes; } fus_busy_t; - logic [CVA6Cfg.NrIssuePorts-1:0] stall_raw, stall_waw, stall_rs1, stall_rs2, stall_rs3; + logic [CVA6Cfg.NrIssuePorts-1:0] stall_raw, stall_rs1, stall_rs2, stall_rs3; logic [CVA6Cfg.NrIssuePorts-1:0] fu_busy; // functional unit is busy fus_busy_t [CVA6Cfg.NrIssuePorts-1:0] fus_busy; // which functional units are considered busy logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack; @@ -147,12 +154,13 @@ module issue_read_operands rs3_len_t operand_c_fpr; // output flipflop (ID <-> EX) fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_n, fu_data_q; - logic [CVA6Cfg.VLEN-1:0] pc_n; - logic is_compressed_instr_n; - branchpredict_sbe_t branch_predict_n; - logic [CVA6Cfg.XLEN-1:0] imm_forward_rs3; + logic [ CVA6Cfg.VLEN-1:0] pc_n; + logic is_compressed_instr_n; + branchpredict_sbe_t branch_predict_n; + logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] imm_forward_rs3; logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_n, alu_valid_q; + logic [CVA6Cfg.NrIssuePorts-1:0] aes_valid_n, aes_valid_q; logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_n, mult_valid_q; logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_n, fpu_valid_q; logic [1:0] fpu_fmt_n, fpu_fmt_q; @@ -163,37 +171,45 @@ module issue_read_operands logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_n, branch_valid_q; logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_n, cvxif_valid_q; logic [31:0] cvxif_off_instr_n, cvxif_off_instr_q; - logic cvxif_instruction_valid; + logic cvxif_instruction_valid; - //fwd logic - logic [CVA6Cfg.NrIssuePorts-1:0] rs1_has_raw; - logic [CVA6Cfg.NrIssuePorts-1:0] rs2_has_raw; - logic [CVA6Cfg.NrIssuePorts-1:0] rs3_has_raw; + //RAW detection + logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.TRANS_ID_BITS-1:0] idx_hzd_rs1; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs1_raw_check; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs1_has_raw; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs1_fpr; - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs3; - logic [CVA6Cfg.NrIssuePorts-1:0] rs3_fpr; + logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.TRANS_ID_BITS-1:0] idx_hzd_rs2; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs2_raw_check; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs2_has_raw; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs2_fpr; - logic [CVA6Cfg.NrIssuePorts-1:0] rs1_valid; - logic [CVA6Cfg.NrIssuePorts-1:0] rs2_valid; - logic [CVA6Cfg.NrIssuePorts-1:0] rs3_valid; + logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.TRANS_ID_BITS-1:0] idx_hzd_rs3; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs3_raw_check; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs3_has_raw; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs3_fpr; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs3_gpr_cvxif; - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_res; - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_res; - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs3_res; - // clobber - fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_gpr, rd_clobber_fpr; - logic [2**ariane_pkg::REG_ADDR_SIZE-1:0][CVA6Cfg.NR_SB_ENTRIES:0] gpr_clobber_vld; - logic [2**ariane_pkg::REG_ADDR_SIZE-1:0][CVA6Cfg.NR_SB_ENTRIES:0] fpr_clobber_vld; - ariane_pkg::fu_t [ CVA6Cfg.NR_SB_ENTRIES:0] clobber_fu; + logic [CVA6Cfg.NR_SB_ENTRIES-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] rd_list; + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] rd_fpr; + + //fwd logic + logic [CVA6Cfg.NR_SB_ENTRIES-1:0][ CVA6Cfg.XLEN-1:0] fwd_res; + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] fwd_res_valid; - //forward logic - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0] - rs1_fwd_req, rs2_fwd_req, rs3_fwd_req; - logic [CVA6Cfg.NrIssuePorts-1:0] rs1_is_not_gpr0, rs2_is_not_gpr0, rs3_is_not_gpr0; - logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] rs_data; - logic [CVA6Cfg.NrIssuePorts-1:0] rs1_available, rs2_available, rs3_available; + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] rs1_is_not_csr; + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] rs2_is_not_csr; + logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs3; + + logic [ CVA6Cfg.NrIssuePorts-1:0] rs1_valid; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs2_valid; + logic [ CVA6Cfg.NrIssuePorts-1:0] rs3_valid; + + logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs1_res; + logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs2_res; + logic [ CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs3_res; logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_n, tinst_q; // transformed instruction @@ -201,8 +217,15 @@ module issue_read_operands logic [CVA6Cfg.NrIssuePorts-1:0] forward_rs1, forward_rs2, forward_rs3; // original instruction - riscv::instruction_t orig_instr; - assign orig_instr = riscv::instruction_t'(orig_instr_i[0]); + riscv::instruction_t [CVA6Cfg.NrIssuePorts-1:0] orig_instr; + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign orig_instr[i] = riscv::instruction_t'(orig_instr_i[i]); + end + + // ALU-ALU bypass signals + alu_bypass_t alu_bypass, alu_bypass_n, alu_bypass_q; + logic is_alu_bypass; + logic [1:0] use_alu2; // CVXIF Signals logic cvxif_req_allowed; @@ -246,7 +269,7 @@ module issue_read_operands // TODO check only for 1st instruction ?? // Allow a cvxif transaction if we WaW condition are ok. - assign cvxif_req_allowed = (issue_instr_i[0].fu == CVXIF) && !stall_waw[0]; + assign cvxif_req_allowed = (issue_instr_i[0].fu == CVXIF); assign cvxif_instruction_valid = !issue_instr_i[0].ex.valid && issue_instr_valid_i[0] && cvxif_req_allowed; assign x_transaction_accepted_o = x_issue_valid_o && x_issue_ready_i && x_issue_resp_i.accept; assign x_transaction_rejected = x_issue_valid_o && x_issue_ready_i && ~x_issue_resp_i.accept; @@ -262,8 +285,10 @@ module issue_read_operands assign rvfi_rs2_o[i] = fu_data_n[i].operand_b; end + assign alu_bypass_o = alu_bypass_q; assign fu_data_o = fu_data_q; assign alu_valid_o = alu_valid_q; + assign aes_valid_o = aes_valid_q; assign branch_valid_o = branch_valid_q; assign lsu_valid_o = lsu_valid_q; assign csr_valid_o = csr_valid_q; @@ -276,6 +301,28 @@ module issue_read_operands assign cvxif_off_instr_o = CVA6Cfg.CvxifEn ? cvxif_off_instr_q : '0; assign stall_issue_o = stall_raw[0]; assign tinst_o = CVA6Cfg.RVH ? tinst_q : '0; + + // ALU bypass signals + if (CVA6Cfg.ALUBypass) begin + // If it is a ALU -> ALU, we can fuse all operation beside CPOP (maybe can be optimized OP -> CPOP, to explore) + assign is_alu_bypass = + (issue_instr_i[0].fu == ALU && issue_instr_i[1].fu == ALU) && + !((issue_instr_i[0].op inside {CPOP, CPOPW}) || (issue_instr_i[1].op inside {CPOP, CPOPW})); + end else begin + assign is_alu_bypass = 1'b0; + end + + if (CVA6Cfg.SuperscalarEn) begin + // When a bypass is possible or an FPU instruction is present on the second issue port, + // an instruction uses `alu2` only when `alu` is already busy + // In all other scenarios `alu2` is preferred over `alu`, unless it is busy + for (genvar i = 0; i < 2; i++) begin + assign use_alu2[i] = is_alu_bypass || (issue_instr_i[1].fu inside {FPU, FPU_VEC}) ? fus_busy[i].alu : !fus_busy[i].alu2; + end + end else begin + assign use_alu2 = '0; + end + // --------------- // Issue Stage // --------------- @@ -287,6 +334,7 @@ module issue_read_operands // Since we can not have two CVXIF instruction on 1st issue port, CVXIF is always ready for the pending instruction. if (!flu_ready_i) begin fus_busy[0].alu = 1'b1; + fus_busy[0].aes = 1'b1; fus_busy[0].ctrl_flow = 1'b1; fus_busy[0].csr = 1'b1; fus_busy[0].mult = 1'b1; @@ -296,6 +344,7 @@ module issue_read_operands // otherwise we will get contentions on the fixed latency bus if (|mult_valid_q) begin fus_busy[0].alu = 1'b1; + fus_busy[0].aes = 1'b1; fus_busy[0].ctrl_flow = 1'b1; fus_busy[0].csr = 1'b1; end @@ -303,7 +352,6 @@ module issue_read_operands if (CVA6Cfg.FpPresent && !fpu_ready_i) begin fus_busy[0].fpu = 1'b1; fus_busy[0].fpu_vec = 1'b1; - if (CVA6Cfg.SuperscalarEn) fus_busy[0].alu2 = 1'b1; end if (!lsu_ready_i) begin @@ -312,6 +360,11 @@ module issue_read_operands end if (CVA6Cfg.SuperscalarEn) begin + + if (fpu_early_valid_i) begin + fus_busy[0].alu2 = 1'b1; + end + fus_busy[1] = fus_busy[0]; // Never issue CSR instruction on second issue port. @@ -327,8 +380,6 @@ module issue_read_operands fus_busy[1].alu = 1'b1; fus_busy[1].ctrl_flow = 1'b1; fus_busy[1].csr = 1'b1; - // Speculative non-idempotent loads are not supported yet - fus_busy[1].load = 1'b1; // The store buffer cannot be partially flushed yet fus_busy[1].store = 1'b1; end else begin @@ -344,12 +395,8 @@ module issue_read_operands end end ALU: begin - if (CVA6Cfg.SuperscalarEn && !fus_busy[0].alu2) begin + if (use_alu2[0]) begin fus_busy[1].alu2 = 1'b1; - // TODO is there a minimum float execution time? - // If so we could issue FPU & ALU2 the same cycle - fus_busy[1].fpu = 1'b1; - fus_busy[1].fpu_vec = 1'b1; end else begin fus_busy[1].alu = 1'b1; fus_busy[1].ctrl_flow = 1'b1; @@ -364,10 +411,18 @@ module issue_read_operands FPU, FPU_VEC: begin fus_busy[1].fpu = 1'b1; fus_busy[1].fpu_vec = 1'b1; + if (issue_instr_i[1].op inside {[FLD : FSB]}) begin + fus_busy[1].load = 1'b1; + fus_busy[1].store = 1'b1; + end end LOAD, STORE: begin fus_busy[1].load = 1'b1; fus_busy[1].store = 1'b1; + if (issue_instr_i[0].op inside {[FLD : FSB]}) begin + fus_busy[1].fpu = 1'b1; + fus_busy[1].fpu_vec = 1'b1; + end end CVXIF: ; default: ; @@ -382,7 +437,7 @@ module issue_read_operands unique case (issue_instr_i[i].fu) NONE: fu_busy[i] = fus_busy[i].none; ALU: begin - if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin + if (CVA6Cfg.SuperscalarEn && use_alu2[i]) begin fu_busy[i] = fus_busy[i].alu2; end else begin fu_busy[i] = fus_busy[i].alu; @@ -394,6 +449,7 @@ module issue_read_operands LOAD: fu_busy[i] = fus_busy[i].load; STORE: fu_busy[i] = fus_busy[i].store; CVXIF: fu_busy[i] = fus_busy[i].cvxif; + AES: fu_busy[i] = fus_busy[i].aes; default: if (CVA6Cfg.FpPresent) begin unique case (issue_instr_i[i].fu) @@ -408,226 +464,105 @@ module issue_read_operands end end - // ------------------- - // RD clobber process - // ------------------- - // rd_clobber output: output currently clobbered destination registers - - always_comb begin : clobber_assign - gpr_clobber_vld = '0; - fpr_clobber_vld = '0; - - // default (highest entry hast lowest prio in arbiter tree below) - clobber_fu[CVA6Cfg.NR_SB_ENTRIES] = ariane_pkg::NONE; - for (int unsigned i = 0; i < 2 ** ariane_pkg::REG_ADDR_SIZE; i++) begin - gpr_clobber_vld[i][CVA6Cfg.NR_SB_ENTRIES] = 1'b1; - fpr_clobber_vld[i][CVA6Cfg.NR_SB_ENTRIES] = 1'b1; - end - - // check for all valid entries and set the clobber accordingly - - for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin - gpr_clobber_vld[fwd_i.sbe[i].rd][i] = fwd_i.still_issued[i] & ~(CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - fwd_i.sbe[i].op)); - fpr_clobber_vld[fwd_i.sbe[i].rd][i] = fwd_i.still_issued[i] & (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - fwd_i.sbe[i].op)); - clobber_fu[i] = fwd_i.sbe[i].fu; - end + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign rs1_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr(issue_instr_i[i].op)); + assign rs2_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr(issue_instr_i[i].op)); + assign rs3_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(issue_instr_i[i].op)); + assign rs3_gpr_cvxif[i] = CVA6Cfg.CvxifEn && (OPERANDS_PER_INSTR == 3) + && issue_instr_i[i].op == OFFLOAD; + end - // GPR[0] is always free - gpr_clobber_vld[0] = '0; + // ---------------------------------- + // Renaming + // ---------------------------------- + for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + assign rd_list[i] = fwd_i.sbe[i].rd; + assign rd_fpr[i] = CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(fwd_i.sbe[i].op); end - for (genvar k = 0; k < 2 ** ariane_pkg::REG_ADDR_SIZE; k++) begin : gen_sel_clobbers - // get fu that is going to clobber this register (there should be only one) - rr_arb_tree #( - .NumIn(CVA6Cfg.NR_SB_ENTRIES + 1), - .DataType(ariane_pkg::fu_t), - .ExtPrio(1'b1), - .AxiVldRdy(1'b1) - ) i_sel_gpr_clobbers ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .flush_i(1'b0), - .rr_i ('0), - .req_i (gpr_clobber_vld[k]), - .gnt_o (), - .data_i (clobber_fu), - .gnt_i (1'b1), - .req_o (), - .data_o (rd_clobber_gpr[k]), - .idx_o () + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin : gen_raw_checks + raw_checker #( + .CVA6Cfg(CVA6Cfg) + ) i_rs1_last_raw ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .rs_i(issue_instr_i[i].rs1), + .rs_fpr_i(rs1_fpr[i]), + .rd_i(rd_list), + .rd_fpr_i(rd_fpr), + .still_issued_i(fwd_i.still_issued), + .issue_pointer_i(fwd_i.issue_pointer), + .idx_o(idx_hzd_rs1[i]), + .valid_o(rs1_raw_check[i]) ); - if (CVA6Cfg.FpPresent) begin - rr_arb_tree #( - .NumIn(CVA6Cfg.NR_SB_ENTRIES + 1), - .DataType(ariane_pkg::fu_t), - .ExtPrio(1'b1), - .AxiVldRdy(1'b1) - ) i_sel_fpr_clobbers ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .flush_i(1'b0), - .rr_i ('0), - .req_i (fpr_clobber_vld[k]), - .gnt_o (), - .data_i (clobber_fu), - .gnt_i (1'b1), - .req_o (), - .data_o (rd_clobber_fpr[k]), - .idx_o () - ); - end else begin - assign rd_clobber_fpr[k] = NONE; - end + assign rs1_has_raw[i] = rs1_raw_check[i] && !issue_instr_i[i].use_zimm; + + raw_checker #( + .CVA6Cfg(CVA6Cfg) + ) i_rs2_last_raw ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .rs_i(issue_instr_i[i].rs2), + .rs_fpr_i(rs2_fpr[i]), + .rd_i(rd_list), + .rd_fpr_i(rd_fpr), + .still_issued_i(fwd_i.still_issued), + .issue_pointer_i(fwd_i.issue_pointer), + .idx_o(idx_hzd_rs2[i]), + .valid_o(rs2_raw_check[i]) + ); + assign rs2_has_raw[i] = rs2_raw_check[i]; + + raw_checker #( + .CVA6Cfg(CVA6Cfg) + ) i_rs3_last_raw ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .rs_i(issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]), + .rs_fpr_i(rs3_fpr[i]), + .rd_i(rd_list), + .rd_fpr_i(rd_fpr), + .still_issued_i(fwd_i.still_issued), + .issue_pointer_i(fwd_i.issue_pointer), + .idx_o(idx_hzd_rs3[i]), + .valid_o(rs3_raw_check[i]) + ); + assign rs3_has_raw[i] = rs3_raw_check[i] && (rs3_fpr[i] || rs3_gpr_cvxif[i]); end // ---------------------------------- // Read Operands (a.k.a forwarding) // ---------------------------------- - // read operand interface: same logic as register file - - // WB ports have higher prio than entries - for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin - for (genvar k = 0; unsigned'(k) < CVA6Cfg.NrWbPorts; k++) begin : gen_rs_wb - - assign rs1_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].rs1) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - fwd_i.sbe[fwd_i.wb[k].trans_id].op - )) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr( - issue_instr_i[i].op - ))); - - assign rs2_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].rs2) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - fwd_i.sbe[fwd_i.wb[k].trans_id].op - )) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr( - issue_instr_i[i].op - ))); - - assign rs3_fwd_req[i][k] = (fwd_i.sbe[fwd_i.wb[k].trans_id].rd == issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]) & (fwd_i.still_issued[fwd_i.wb[k].trans_id]) & fwd_i.wb[k].valid & (~fwd_i.wb[k].ex_valid) & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - fwd_i.sbe[fwd_i.wb[k].trans_id].op - )) == (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr( - issue_instr_i[i].op - ))); - - assign rs_data[i][k] = fwd_i.wb[k].data; + always_comb begin + for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + fwd_res[i] = fwd_i.sbe[i].result; + fwd_res_valid[i] = fwd_i.sbe[i].valid & (~fwd_i.sbe[i].ex.valid); end - - for (genvar k = 0; unsigned'(k) < CVA6Cfg.NR_SB_ENTRIES; k++) begin : gen_rs_entries - - assign rs1_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].rs1) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - fwd_i.sbe[k].op - )) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr( - issue_instr_i[i].op - ))); - - assign rs2_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].rs2) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - fwd_i.sbe[k].op - )) == (CVA6Cfg.FpPresent && ariane_pkg::is_rs2_fpr( - issue_instr_i[i].op - ))); - - assign rs3_fwd_req[i][k+CVA6Cfg.NrWbPorts] = (fwd_i.sbe[k].rd == issue_instr_i[i].result[ariane_pkg::REG_ADDR_SIZE-1:0]) & fwd_i.still_issued[k] & fwd_i.sbe[k].valid & ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - fwd_i.sbe[k].op - )) == (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr( - issue_instr_i[i].op - ))); - - assign rs_data[i][k+CVA6Cfg.NrWbPorts] = fwd_i.sbe[k].result; + for (int unsigned i = 0; i < CVA6Cfg.NrWbPorts; i++) begin + if (fwd_i.wb[i].valid && !fwd_i.wb[i].ex_valid) begin + fwd_res[fwd_i.wb[i].trans_id] = fwd_i.wb[i].data; + fwd_res_valid[fwd_i.wb[i].trans_id] = 1'b1; + end end + end - // use fixed prio here - // this implicitly gives higher prio to WB ports - rr_arb_tree #( - .NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts), - .DataWidth(CVA6Cfg.XLEN), - .ExtPrio(1'b1), - .AxiVldRdy(1'b1) - ) i_sel_rs1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .flush_i(1'b0), - .rr_i ('0), - .req_i (rs1_fwd_req[i]), - .gnt_o (), - .data_i (rs_data[i]), - .gnt_i (1'b1), - .req_o (rs1_available[i]), - .data_o (rs1_res[i]), - .idx_o () - ); - - rr_arb_tree #( - .NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts), - .DataWidth(CVA6Cfg.XLEN), - .ExtPrio(1'b1), - .AxiVldRdy(1'b1) - ) i_sel_rs2 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .flush_i(1'b0), - .rr_i ('0), - .req_i (rs2_fwd_req[i]), - .gnt_o (), - .data_i (rs_data[i]), - .gnt_i (1'b1), - .req_o (rs2_available[i]), - .data_o (rs2_res[i]), - .idx_o () - ); + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign rs1_res[i] = fwd_res[idx_hzd_rs1[i]]; + assign rs1_is_not_csr[i] = rs1_fpr[i] || (fwd_i.sbe[idx_hzd_rs1[i]].fu != ariane_pkg::CSR) || (CVA6Cfg.RVS && issue_instr_i[i].op == ariane_pkg::SFENCE_VMA); + assign rs1_valid[i] = fwd_res_valid[idx_hzd_rs1[i]] && rs1_is_not_csr[i]; + assign rs2_res[i] = fwd_res[idx_hzd_rs2[i]]; + assign rs2_is_not_csr[i] = rs2_fpr[i] || (fwd_i.sbe[idx_hzd_rs2[i]].fu != ariane_pkg::CSR) || (CVA6Cfg.RVS && issue_instr_i[i].op == ariane_pkg::SFENCE_VMA); + assign rs2_valid[i] = fwd_res_valid[idx_hzd_rs2[i]] && rs2_is_not_csr[i]; - rr_arb_tree #( - .NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts), - .DataWidth(CVA6Cfg.XLEN), - .ExtPrio(1'b1), - .AxiVldRdy(1'b1) - ) i_sel_rs3 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .flush_i(1'b0), - .rr_i ('0), - .req_i (rs3_fwd_req[i]), - .gnt_o (), - .data_i (rs_data[i]), - .gnt_i (1'b1), - .req_o (rs3_available[i]), - .data_o (rs3[i]), - .idx_o () - ); + assign rs3[i] = fwd_res[idx_hzd_rs3[i]]; + assign rs3_valid[i] = fwd_res_valid[idx_hzd_rs3[i]]; - if (CVA6Cfg.NrRgprPorts == 3) begin : gen_gp_three_port - assign rs3_res[i] = rs3[i][riscv::XLEN-1:0]; - end else begin : gen_fp_three_port + if (CVA6Cfg.NrRgprPorts == 3) begin + assign rs3_res[i] = rs3[i][CVA6Cfg.XLEN-1:0]; + end else begin assign rs3_res[i] = rs3[i][CVA6Cfg.FLen-1:0]; end - - assign rs1_has_raw[i] = !issue_instr_i[i].use_zimm && ((CVA6Cfg.FpPresent && is_rs1_fpr( - issue_instr_i[i].op - )) ? rd_clobber_fpr[issue_instr_i[i].rs1] != NONE : - rd_clobber_gpr[issue_instr_i[i].rs1] != NONE); - - assign rs1_valid[i] = rs1_available[i] && (CVA6Cfg.FpPresent && is_rs1_fpr( - issue_instr_i[i].op - ) ? 1'b1 : ((rd_clobber_gpr[issue_instr_i[i].rs1] != CSR) || - (CVA6Cfg.RVS && issue_instr_i[i].op == SFENCE_VMA))); - - assign rs2_has_raw[i] = ((CVA6Cfg.FpPresent && is_rs2_fpr( - issue_instr_i[i].op - )) ? rd_clobber_fpr[issue_instr_i[i].rs2] != NONE : - rd_clobber_gpr[issue_instr_i[i].rs2] != NONE); - - assign rs2_valid[i] = rs2_available[i] && (CVA6Cfg.FpPresent && is_rs2_fpr( - issue_instr_i[i].op - ) ? 1'b1 : ((rd_clobber_gpr[issue_instr_i[i].rs2] != CSR) || - (CVA6Cfg.RVS && issue_instr_i[i].op == SFENCE_VMA))); - - assign rs3_has_raw[i] = ((CVA6Cfg.FpPresent && is_imm_fpr( - issue_instr_i[i].op - )) ? rd_clobber_fpr[issue_instr_i[i].result[REG_ADDR_SIZE-1:0]] != NONE : 0); - - assign rs3_valid[i] = rs3_available[i]; - assign rs3_fpr[i] = (CVA6Cfg.FpPresent && ariane_pkg::is_imm_fpr(issue_instr_i[i].op)); - end // --------------- @@ -636,6 +571,8 @@ module issue_read_operands // check that all operands are available, otherwise stall // forward corresponding register always_comb begin : operands_available + alu_bypass = '0; + stall_raw = '{default: stall_i}; stall_rs1 = '{default: stall_i}; stall_rs2 = '{default: stall_i}; @@ -643,7 +580,7 @@ module issue_read_operands // operand forwarding signals forward_rs1 = '0; forward_rs2 = '0; - forward_rs3 = '0; // FPR only + forward_rs3 = '0; // FPR and CV-X-IF only for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin if (rs1_has_raw[i]) begin @@ -664,7 +601,7 @@ module issue_read_operands end end - if (rs3_has_raw[i] && rs3_fpr[i]) begin + if (rs3_has_raw[i]) begin if (rs3_valid[i]) begin forward_rs3[i] = 1'b1; end else begin // the operand is not available -> stall @@ -675,7 +612,7 @@ module issue_read_operands end if (CVA6Cfg.CvxifEn) begin - // Remove unecessary forward and stall in case source register is not needed by coprocessor. + // Remove unnecessary forward and stall in case source register is not needed by coprocessor. if (x_issue_valid_o && x_issue_resp_i.accept) begin if (~x_issue_resp_i.register_read[0]) begin forward_rs1[0] = 1'b0; @@ -699,7 +636,11 @@ module issue_read_operands ) == is_rd_fpr( issue_instr_i[0].op ))) && issue_instr_i[1].rs1 == issue_instr_i[0].rd && issue_instr_i[1].rs1 != '0) begin - stall_raw[1] = 1'b1; + if (is_alu_bypass) begin + alu_bypass.rs1_from_rd = 1'b1; + end else begin + stall_raw[1] = 1'b1; // RS1[1] NEEDS RD[0] + end end if ((!CVA6Cfg.FpPresent || (is_rs2_fpr( @@ -707,7 +648,11 @@ module issue_read_operands ) == is_rd_fpr( issue_instr_i[0].op ))) && issue_instr_i[1].rs2 == issue_instr_i[0].rd && issue_instr_i[1].rs2 != '0) begin - stall_raw[1] = 1'b1; + if (is_alu_bypass) begin + alu_bypass.rs2_from_rd = 1'b1; + end else begin + stall_raw[1] = 1'b1; // RS2[1] NEEDS RD[0] + end end // Only check clobbered gpr for OFFLOADED instruction @@ -724,10 +669,12 @@ module issue_read_operands end // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3 - if (OPERANDS_PER_INSTR == 3) begin : gen_gp_rs3 - assign imm_forward_rs3 = rs3_res[0]; - end else begin : gen_fp_rs3 - assign imm_forward_rs3 = {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, rs3_res[0]}; + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + if (OPERANDS_PER_INSTR == 3) begin : gen_gp_rs3 + assign imm_forward_rs3[i] = rs3_res[i]; + end else begin : gen_fp_rs3 + assign imm_forward_rs3[i] = {{CVA6Cfg.XLEN - CVA6Cfg.FLen{1'b0}}, rs3_res[i]}; + end end // Forwarding/Output MUX @@ -762,7 +709,7 @@ module issue_read_operands fu_data_n[i].operand_b = rs2_res[i]; end if ((CVA6Cfg.FpPresent || (CVA6Cfg.CvxifEn && OPERANDS_PER_INSTR == 3)) && forward_rs3[i]) begin - fu_data_n[i].imm = imm_forward_rs3; + fu_data_n[i].imm = imm_forward_rs3[i]; end // use the PC as operand a @@ -789,6 +736,7 @@ module issue_read_operands always_comb begin alu_valid_n = '0; + aes_valid_n = '0; lsu_valid_n = '0; mult_valid_n = '0; fpu_valid_n = '0; @@ -801,7 +749,7 @@ module issue_read_operands if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin case (issue_instr_i[i].fu) ALU: begin - if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin + if (CVA6Cfg.SuperscalarEn && use_alu2[i]) begin alu2_valid_n[i] = 1'b1; end else begin alu_valid_n[i] = 1'b1; @@ -819,15 +767,18 @@ module issue_read_operands CSR: begin csr_valid_n[i] = 1'b1; end + AES: begin + aes_valid_n[i] = 1'b1; + end default: begin if (issue_instr_i[i].fu == FPU && CVA6Cfg.FpPresent) begin fpu_valid_n[i] = 1'b1; - fpu_fmt_n = orig_instr.rftype.fmt; // fmt bits from instruction - fpu_rm_n = orig_instr.rftype.rm; // rm bits from instruction + fpu_fmt_n = orig_instr[i].rftype.fmt; // fmt bits from instruction + fpu_rm_n = orig_instr[i].rftype.rm; // rm bits from instruction end else if (issue_instr_i[i].fu == FPU_VEC && CVA6Cfg.FpPresent) begin fpu_valid_n[i] = 1'b1; - fpu_fmt_n = orig_instr.rvftype.vfmt; // vfmt bits from instruction - fpu_rm_n = {2'b0, orig_instr.rvftype.repl}; // repl bit from instruction + fpu_fmt_n = orig_instr[i].rvftype.vfmt; // vfmt bits from instruction + fpu_rm_n = {2'b0, orig_instr[i].rvftype.repl}; // repl bit from instruction end end endcase @@ -837,6 +788,7 @@ module issue_read_operands // functional unit with the wrong inputs if (flush_i) begin alu_valid_n = '0; + aes_valid_n = '0; lsu_valid_n = '0; mult_valid_n = '0; fpu_valid_n = '0; @@ -846,10 +798,11 @@ module issue_read_operands end end // FU select, assert the correct valid out signal (in the next cycle) - // This needs to be like this to make verilator happy. I know its ugly. + // This needs to be like this to make verilator happy. I know it's ugly. always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin alu_valid_q <= '0; + aes_valid_q <= '0; lsu_valid_q <= '0; mult_valid_q <= '0; fpu_valid_q <= '0; @@ -860,6 +813,7 @@ module issue_read_operands branch_valid_q <= '0; end else begin alu_valid_q <= alu_valid_n; + aes_valid_q <= aes_valid_n; lsu_valid_q <= lsu_valid_n; mult_valid_q <= mult_valid_n; fpu_valid_q <= fpu_valid_n; @@ -880,7 +834,7 @@ module issue_read_operands case (issue_instr_i[i].fu) CVXIF: begin cvxif_valid_n[i] = 1'b1; - cvxif_off_instr_n = orig_instr[i]; + cvxif_off_instr_n = orig_instr_i[i]; end default: ; endcase @@ -902,40 +856,6 @@ module issue_read_operands end end - always_comb begin : gen_check_waw_dependencies - stall_waw = '1; - for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin - if (issue_instr_valid_i[i] && !fu_busy[i]) begin - // ----------------------------------------- - // WAW - Write After Write Dependency Check - // ----------------------------------------- - // no other instruction has the same destination register -> issue the instruction - if ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - issue_instr_i[i].op - )) ? (rd_clobber_fpr[issue_instr_i[i].rd] == NONE) : - (rd_clobber_gpr[issue_instr_i[i].rd] == NONE)) begin - stall_waw[i] = 1'b0; - end - // or check that the target destination register will be written in this cycle by the - // commit stage - for (int unsigned c = 0; c < CVA6Cfg.NrCommitPorts; c++) begin - if ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( - issue_instr_i[i].op - )) ? (we_fpr_i[c] && waddr_i[c] == issue_instr_i[i].rd) : - (we_gpr_i[c] && waddr_i[c] == issue_instr_i[i].rd)) begin - stall_waw[i] = 1'b0; - end - end - if (i > 0) begin - if ((issue_instr_i[i].rd == issue_instr_i[i-1].rd) && (issue_instr_i[i].rd != '0)) begin - stall_waw[i] = 1'b1; - end - end - end - end - end - - // We can issue an instruction if we do not detect that any other instruction is writing the same // destination register. // We also need to check if there is an unresolved branch in the scoreboard. @@ -946,7 +866,7 @@ module issue_read_operands // check that the instruction we got is valid // and that the functional unit we need is not busy if (issue_instr_valid_i[i] && !fu_busy[i]) begin - if (!stall_raw[i] && !stall_waw[i]) begin + if (!stall_raw[i]) begin issue_ack[i] = 1'b1; end if (issue_instr_i[i].ex.valid) begin @@ -956,7 +876,7 @@ module issue_read_operands end issue_ack_o = issue_ack; - // Do not acknoledge the issued instruction if transaction is not completed. + // Do not acknowledge the issued instruction if transaction is not completed. if (issue_instr_i[0].fu == CVXIF && !(x_transaction_accepted_o || x_transaction_rejected)) begin issue_ack_o[0] = issue_instr_i[0].ex.valid && issue_instr_valid_i[0]; end @@ -978,7 +898,7 @@ module issue_read_operands logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_pack; logic [CVA6Cfg.NrCommitPorts-1:0] we_pack; - //adjust address to read from register file (when synchronous RAM is used reads take one cycle, so we advance the address) + //adjust address to read from register file (when synchronous RAM is used reads take one cycle, so we advance the address) for (genvar i = 0; i <= CVA6Cfg.NrIssuePorts - 1; i++) begin assign raddr_pack[i*OPERANDS_PER_INSTR+0] = CVA6Cfg.FpgaEn && CVA6Cfg.FpgaAlteraEn ? issue_instr_i_prev[i].rs1[4:0] : issue_instr_i[i].rs1[4:0]; assign raddr_pack[i*OPERANDS_PER_INSTR+1] = CVA6Cfg.FpgaEn && CVA6Cfg.FpgaAlteraEn ? issue_instr_i_prev[i].rs2[4:0] : issue_instr_i[i].rs2[4:0]; @@ -1041,7 +961,7 @@ module issue_read_operands }; if (CVA6Cfg.SuperscalarEn) begin - if (!(issue_instr_i[0].fu inside {FPU, FPU_VEC})) begin + if (!(issue_instr_i[0].fu inside {FPU, FPU_VEC} || issue_instr_i[0].op inside {[FLD:FSB]})) begin fp_raddr_pack = { issue_instr_i[1].result[4:0], issue_instr_i[1].rs2[4:0], issue_instr_i[1].rs1[4:0] }; @@ -1140,6 +1060,7 @@ module issue_read_operands end end + assign alu_bypass_n = &issue_ack_o ? alu_bypass : '0; always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin @@ -1152,29 +1073,24 @@ module issue_read_operands is_compressed_instr_o <= 1'b0; branch_predict_o <= {cf_t'(0), {CVA6Cfg.VLEN{1'b0}}}; x_transaction_rejected_o <= 1'b0; + alu_bypass_q <= '0; end else begin fu_data_q <= fu_data_n; + alu_bypass_q <= alu_bypass_n; + if (CVA6Cfg.ZKN) begin + orig_instr_aes_bits <= {orig_instr_i[0][31:30], orig_instr_i[0][23:20]}; + end if (CVA6Cfg.RVH) begin tinst_q <= tinst_n; end - if (CVA6Cfg.SuperscalarEn) begin - if (issue_instr_i[1].fu == CTRL_FLOW) begin - pc_o <= issue_instr_i[1].pc; - is_compressed_instr_o <= issue_instr_i[1].is_compressed; - branch_predict_o <= issue_instr_i[1].bp; - end - end + pc_o <= pc_n; + is_compressed_instr_o <= is_compressed_instr_n; + branch_predict_o <= branch_predict_n; if (issue_instr_i[0].fu == CTRL_FLOW) begin - pc_o <= issue_instr_i[0].pc; - is_compressed_instr_o <= issue_instr_i[0].is_compressed; - branch_predict_o <= issue_instr_i[0].bp; if (CVA6Cfg.RVZCMT) is_zcmt_o <= issue_instr_i[0].is_zcmt; else is_zcmt_o <= '0; end - x_transaction_rejected_o <= 1'b0; - if (issue_instr_i[0].fu == CVXIF) begin - x_transaction_rejected_o <= x_transaction_rejected; - end + x_transaction_rejected_o <= x_transaction_rejected_n; end end @@ -1188,20 +1104,6 @@ module issue_read_operands ); end - // FPU does not declare that it will return a result the subsequent cycle so - // it is not possible for issue stage to know when ALU2 can be used if there - // is an FPU. As there are discussions to change the FPU, I did not explore - // its architecture to create this "FPU returns next cycle" signal. Also, a - // "lookahead" optimization should be added to be performant with FPU: when - // issue port 2 is issuing to FPU, issue port 1 should issue to ALU1 instead - // of ALU2 so that FPU is not busy. However, if FPU has a minimum execution - // time of 2 cycles, it is possible to simply not raise fus_busy[1].alu2. - initial begin - assert (!(CVA6Cfg.SuperscalarEn && CVA6Cfg.FpPresent)) - else - $fatal(1, "FPU is not yet supported in superscalar CVA6, see comments above this assertion."); - end - for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin assert property (@(posedge clk_i) (branch_valid_q) |-> (!$isunknown( fu_data_q[i].operand_a diff --git a/core/issue_stage.sv b/core/issue_stage.sv index 4ffc5382e89..09cbeeb862f 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -50,7 +50,7 @@ module issue_stage input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i, // Is instruction a control flow instruction - ID_STAGE input logic [CVA6Cfg.NrIssuePorts-1:0] is_ctrl_flow_i, - // Handshake's acknowlege with decode stage - ID_STAGE + // Handshake's acknowledge with decode stage - ID_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_o, // rs1 forwarding - EX_STAGE output [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_o, @@ -58,6 +58,8 @@ module issue_stage output [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_o, // FU data useful to execute instruction - EX_STAGE output fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_o, + // ALU to ALU bypass control - EX_STAGE + output alu_bypass_t alu_bypass_o, // Program Counter - EX_STAGE output logic [CVA6Cfg.VLEN-1:0] pc_o, // Is zcmt instruction - EX_STAGE @@ -70,6 +72,8 @@ module issue_stage input logic flu_ready_i, // ALU output is valid - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_o, + // AES output is valid - EX_STAGE + output logic [CVA6Cfg.NrIssuePorts-1:0] aes_valid_o, // Branch unit is valid - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o, // Information of branch prediction - EX_STAGE @@ -90,6 +94,8 @@ module issue_stage output logic [1:0] fpu_fmt_o, // FPU rm field - EX_STAGE output logic [2:0] fpu_rm_o, + // FPU early valid - EX_STAGE + input logic fpu_early_valid_i, // ALU2 FU is valid - EX_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_o, // CSR is valid - EX_STAGE @@ -163,7 +169,9 @@ module issue_stage // Information dedicated to RVFI - RVFI output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs1_o, // Information dedicated to RVFI - RVFI - output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2_o + output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rvfi_rs2_o, + // Original instruction bits for AES + output logic [5:0] orig_instr_aes_bits ); // --------------------------------------------------- // Scoreboard (SB) <-> Issue and Read Operands (IRO) @@ -258,6 +266,7 @@ module issue_stage .issue_ack_o (issue_ack_iro_sb), .fwd_i (fwd), .fu_data_o (fu_data_o), + .alu_bypass_o (alu_bypass_o), .rs1_forwarding_o (rs1_forwarding_o), .rs2_forwarding_o (rs2_forwarding_o), .pc_o, @@ -265,6 +274,7 @@ module issue_stage .is_compressed_instr_o, .flu_ready_i (flu_ready_i), .alu_valid_o (alu_valid_o), + .aes_valid_o (aes_valid_o), .branch_valid_o (branch_valid_o), .tinst_o (tinst_o), .branch_predict_o, @@ -275,6 +285,7 @@ module issue_stage .fpu_valid_o, .fpu_fmt_o, .fpu_rm_o, + .fpu_early_valid_i, .alu2_valid_o, .csr_valid_o, .cvxif_valid_o (xfu_valid_o), @@ -300,7 +311,8 @@ module issue_stage .we_fpr_i, .stall_issue_o, .rvfi_rs1_o (rvfi_rs1_o), - .rvfi_rs2_o (rvfi_rs2_o) + .rvfi_rs2_o (rvfi_rs2_o), + .orig_instr_aes_bits (orig_instr_aes_bits) ); endmodule diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 0fec645319a..12562063e62 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -25,7 +25,11 @@ module load_store_unit parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, - parameter type lsu_ctrl_t = logic + parameter type lsu_ctrl_t = logic, + parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_resp_t = logic, + parameter type cbo_t = logic, + parameter type bp_resolve_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -37,6 +41,8 @@ module load_store_unit input logic stall_st_pending_i, // TO_BE_COMPLETED - TO_BE_COMPLETED output logic no_st_pending_o, + // Shared TLB is busy processing a multi-cycle flush + output logic shared_tlb_flush_busy_o, // TO_BE_COMPLETED - TO_BE_COMPLETED input logic amo_valid_commit_i, // TO_BE_COMPLETED - TO_BE_COMPLETED @@ -47,6 +53,8 @@ module load_store_unit output logic lsu_ready_o, // Load Store Unit instruction is valid - ISSUE_STAGE input logic lsu_valid_i, + // Signals speculative loads for non-idempotent load handling - EX_STAGE + input logic speculative_load_i, // Load transaction ID - ISSUE_STAGE output logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_o, @@ -72,7 +80,8 @@ module load_store_unit output logic commit_ready_o, // Commit transaction ID - TO_BE_COMPLETED input logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_tran_id_i, - + // Result from branch unit - EX_STAGE + input bp_resolve_t resolved_branch_i, // Enable virtual memory translation - TO_BE_COMPLETED input logic enable_translation_i, // Enable G-Stage memory translation - TO_BE_COMPLETED @@ -82,6 +91,10 @@ module load_store_unit // Enable G-Stage memory translation for load/stores - TO_BE_COMPLETED input logic en_ld_st_g_translation_i, + // Accelerator request for CVA6's MMU + input acc_mmu_req_t acc_mmu_req_i, + output acc_mmu_resp_t acc_mmu_resp_o, + // Instruction cache input request - CACHES input icache_arsp_t icache_areq_i, // Instruction cache output request - CACHES @@ -89,6 +102,8 @@ module load_store_unit // Current privilege mode - CSR_REGFILE input riscv::priv_lvl_t priv_lvl_i, + // Data Endian mode - CSR_REGFILE + input logic mbe_i, // Current virtualization mode - CSR_REGFILE input logic v_i, // Privilege level at which load and stores should happen - CSR_REGFILE @@ -148,37 +163,43 @@ module load_store_unit input amo_resp_t amo_resp_i, // PMP configuration - CSR_REGFILE - input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, // PMP address - CSR_REGFILE - input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i, - // RVFI inforamtion - RVFI + // RVFI information - RVFI output lsu_ctrl_t rvfi_lsu_ctrl_o, // RVFI information - RVFI - output logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o + output logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o, + //Trigger module communication + input logic sdtrig_load_stall_i, + input logic sdtrig_load_cancel_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_load_action_i, + input logic sdtrig_store_stall_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_store_action_i ); // data is misaligned - logic data_misaligned; + logic data_misaligned; // -------------------------------------- // 1st register stage - (stall registers) // -------------------------------------- // those are the signals which are always correct // e.g.: they keep the value in the stall case - lsu_ctrl_t lsu_ctrl; + lsu_ctrl_t lsu_ctrl, lsu_ctrl_byp; - logic pop_st; - logic pop_ld; + logic pop_st; + logic pop_ld; // ------------------------------ // Address Generation Unit (AGU) // ------------------------------ // virtual address as calculated by the AGU in the first cycle - logic [ CVA6Cfg.VLEN-1:0] vaddr_i; - logic [ CVA6Cfg.XLEN-1:0] vaddr_xlen; - logic overflow; - logic g_overflow; - logic [(CVA6Cfg.XLEN/8)-1:0] be_i; + logic [ CVA6Cfg.VLEN-1:0] vaddr_i; + logic [ CVA6Cfg.XLEN-1:0] vaddr_xlen; + logic overflow; + logic g_overflow; + logic [(CVA6Cfg.XLEN/8)-1:0] be_i; assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a)); assign vaddr_i = vaddr_xlen[CVA6Cfg.VLEN-1:0]; @@ -190,10 +211,10 @@ module load_store_unit assign g_overflow = 1'b0; end - logic st_valid_i; - logic ld_valid_i; - logic ld_translation_req; - logic st_translation_req; + logic st_valid_i; + logic ld_valid_i; + logic ld_translation_req; + logic st_translation_req, cva6_st_translation_req, acc_st_translation_req; logic [CVA6Cfg.VLEN-1:0] ld_vaddr; logic [ 31:0] ld_tinst; logic ld_hs_ld_st_inst; @@ -202,41 +223,44 @@ module load_store_unit logic [ 31:0] st_tinst; logic st_hs_ld_st_inst; logic st_hlvx_inst; - logic translation_req; - logic translation_valid; - logic [CVA6Cfg.VLEN-1:0] mmu_vaddr; - logic [CVA6Cfg.PLEN-1:0] mmu_paddr, lsu_paddr; - logic [ 31:0] mmu_tinst; - logic mmu_hs_ld_st_inst; - logic mmu_hlvx_inst; - exception_t mmu_exception; - exception_t pmp_exception; - icache_areq_t pmp_icache_areq_i; - logic pmp_translation_valid; - logic dtlb_hit; - logic [ CVA6Cfg.PPNW-1:0] dtlb_ppn; - - logic ld_valid; - logic [CVA6Cfg.TRANS_ID_BITS-1:0] ld_trans_id; - logic [ CVA6Cfg.XLEN-1:0] ld_result; - logic st_valid; - logic [CVA6Cfg.TRANS_ID_BITS-1:0] st_trans_id; - logic [ CVA6Cfg.XLEN-1:0] st_result; - - logic [ 11:0] page_offset; - logic page_offset_matches; - - exception_t misaligned_exception; - exception_t ld_ex; - exception_t st_ex; - - logic hs_ld_st_inst; - logic hlvx_inst; - + logic translation_req, cva6_translation_req, acc_translation_req; + logic translation_valid, cva6_translation_valid; + logic [CVA6Cfg.VLEN-1:0] mmu_vaddr, cva6_mmu_vaddr, acc_mmu_vaddr; + logic [CVA6Cfg.PLEN-1:0] mmu_paddr, cva6_mmu_paddr, acc_mmu_paddr, lsu_paddr; + logic [CVA6Cfg.VLEN-1:0] pmp_vaddr_q; + logic pmp_is_store_q; + logic pmp_hlvx_inst_q; + logic [ 31:0] mmu_tinst; + logic mmu_hs_ld_st_inst; + logic mmu_hlvx_inst; + exception_t mmu_exception, cva6_mmu_exception, acc_mmu_exception; + exception_t pmp_exception; + icache_areq_t pmp_icache_areq_i; + logic pmp_translation_valid; + logic dtlb_hit, cva6_dtlb_hit, acc_dtlb_hit; + logic [CVA6Cfg.PPNW-1:0] dtlb_ppn, cva6_dtlb_ppn, acc_dtlb_ppn; + + logic ld_valid; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] ld_trans_id; + logic [ CVA6Cfg.XLEN-1:0] ld_result; + logic st_valid; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] st_trans_id; + logic [ CVA6Cfg.XLEN-1:0] st_result; + + logic [ 11:0] page_offset; + logic page_offset_matches; + + exception_t misaligned_exception, cva6_misaligned_exception, acc_misaligned_exception; + exception_t ld_ex; + exception_t st_ex; + + logic hs_ld_st_inst; + logic hlvx_inst; logic [1:0] sum, mxr; logic [CVA6Cfg.PPNW-1:0] satp_ppn[2:0]; logic [CVA6Cfg.ASID_WIDTH-1:0] asid[2:0], asid_to_be_flushed[1:0]; logic [CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed[1:0]; + // ------------------- // MMU e.g.: TLBs/PTW // ------------------- @@ -276,6 +300,9 @@ module load_store_unit .lsu_valid_o (pmp_translation_valid), .lsu_paddr_o (lsu_paddr), + .lsu_vaddr_o (pmp_vaddr_q), + .lsu_is_store_o (pmp_is_store_q), + .lsu_hlvx_inst_o(pmp_hlvx_inst_q), .lsu_exception_o(pmp_exception), .priv_lvl_i (priv_lvl_i), @@ -286,6 +313,7 @@ module load_store_unit .vs_sum_i, .mxr_i, .vmxr_i, + .mbe_i (mbe_i), .hlvx_inst_i (mmu_hlvx_inst), .hs_ld_st_inst_i(mmu_hs_ld_st_inst), @@ -305,6 +333,7 @@ module load_store_unit .itlb_miss_o(itlb_miss_o), .dtlb_miss_o(dtlb_miss_o), + .shared_tlb_flush_busy_o(shared_tlb_flush_busy_o), .req_port_i(dcache_req_ports_i[0]), .req_port_o(dcache_req_ports_o[0]), @@ -315,6 +344,7 @@ module load_store_unit end else begin : gen_no_mmu // icache request without MMU, virtual and physical address are identical assign pmp_icache_areq_i.fetch_valid = icache_areq_i.fetch_req; + assign shared_tlb_flush_busy_o = 1'b0; //default 0 for shared_tlb flush if (CVA6Cfg.VLEN >= CVA6Cfg.PLEN) begin : gen_virtual_physical_address_instruction_vlen_greater assign pmp_icache_areq_i.fetch_paddr = icache_areq_i.fetch_vaddr[CVA6Cfg.PLEN-1:0]; end else begin : gen_virtual_physical_address_instruction_plen_greater @@ -326,6 +356,9 @@ module load_store_unit always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin lsu_paddr <= '0; + pmp_vaddr_q <= '0; + pmp_is_store_q <= 1'b0; + pmp_hlvx_inst_q <= 1'b0; pmp_exception <= '0; pmp_translation_valid <= 1'b0; end else begin @@ -334,6 +367,9 @@ module load_store_unit end else begin lsu_paddr <= CVA6Cfg.PLEN'(mmu_vaddr); end + pmp_vaddr_q <= mmu_vaddr; + pmp_is_store_q <= st_translation_req; + pmp_hlvx_inst_q <= mmu_hlvx_inst; pmp_exception <= misaligned_exception; pmp_translation_valid <= translation_req; end @@ -347,6 +383,7 @@ module load_store_unit assign dcache_req_ports_o[0].data_be = '1; assign dcache_req_ports_o[0].data_size = 2'b11; assign dcache_req_ports_o[0].data_we = 1'b0; + assign dcache_req_ports_o[0].data_wuser = '0; assign dcache_req_ports_o[0].kill_req = '0; assign dcache_req_ports_o[0].tag_valid = 1'b0; @@ -373,9 +410,10 @@ module load_store_unit .icache_fetch_vaddr_i(icache_areq_i.fetch_vaddr), .lsu_valid_i (pmp_translation_valid), .lsu_paddr_i (lsu_paddr), - .lsu_vaddr_i (mmu_vaddr), + .lsu_vaddr_i (pmp_vaddr_q), .lsu_exception_i (pmp_exception), - .lsu_is_store_i (st_translation_req), + .lsu_is_store_i (pmp_is_store_q), + .lsu_hlvx_inst_i (pmp_hlvx_inst_q), .lsu_valid_o (translation_valid), .lsu_paddr_o (mmu_paddr), .lsu_exception_o (mmu_exception), @@ -387,6 +425,108 @@ module load_store_unit .pmpaddr_i (pmpaddr_i) ); + // ------------------ + // External MMU port + // ------------------ + + if (CVA6Cfg.EnableAccelerator) begin + // The MMU can be connected to CVA6 or the ACCELERATOR + enum logic { + CVA6, + ACC + } + mmu_state_d, mmu_state_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (~rst_ni) begin + mmu_state_q <= CVA6; + end else begin + mmu_state_q <= mmu_state_d; + end + end + // Straightforward and slow-reactive MMU arbitration logic + // This logic can be optimized to reduce answer latency and contention + always_comb begin + // Maintain state + mmu_state_d = mmu_state_q; + // Serve CVA6 and gate the accelerator by default + // MMU input + misaligned_exception = cva6_misaligned_exception; + st_translation_req = cva6_st_translation_req; + translation_req = cva6_translation_req; + mmu_vaddr = cva6_mmu_vaddr; + // MMU output + cva6_translation_valid = translation_valid; + cva6_mmu_paddr = mmu_paddr; + cva6_mmu_exception = mmu_exception; + cva6_dtlb_hit = dtlb_hit; + cva6_dtlb_ppn = dtlb_ppn; + acc_mmu_resp_o.acc_mmu_valid = '0; + acc_mmu_resp_o.acc_mmu_paddr = '0; + acc_mmu_resp_o.acc_mmu_exception = '0; + acc_mmu_resp_o.acc_mmu_dtlb_hit = '0; + acc_mmu_resp_o.acc_mmu_dtlb_ppn = '0; + unique case (mmu_state_q) + CVA6: begin + // Only the accelerator is requesting, and the lsu bypass queue is empty. + if (acc_mmu_req_i.acc_mmu_req && !lsu_valid_i && lsu_ready_o) begin + // Lock the MMU to the accelerator. + // If the issue stage is firing a mem op in this cycle, + // the bypass queue will buffer it. + mmu_state_d = ACC; + end + // Make this a mealy FSM to cut some latency. + // It should be okay timing-wise since cva6's requests already + // depend on lsu_valid_i. Moreover, lsu_ready_o is sequentially + // generated by the bypass and, in this first implementation, + // the acc request already depends combinatorially upon acc_mmu_req_i.acc_mmu_req. + end + ACC: begin + // MMU input + misaligned_exception = acc_mmu_req_i.acc_mmu_misaligned_ex; + st_translation_req = acc_mmu_req_i.acc_mmu_is_store; + translation_req = acc_mmu_req_i.acc_mmu_req; + mmu_vaddr = acc_mmu_req_i.acc_mmu_vaddr; + // MMU output + acc_mmu_resp_o.acc_mmu_valid = translation_valid; + acc_mmu_resp_o.acc_mmu_paddr = mmu_paddr; + acc_mmu_resp_o.acc_mmu_exception = mmu_exception; + acc_mmu_resp_o.acc_mmu_dtlb_hit = dtlb_hit; + acc_mmu_resp_o.acc_mmu_dtlb_ppn = dtlb_ppn; + cva6_translation_valid = '0; + cva6_mmu_paddr = '0; + cva6_mmu_exception = '0; + cva6_dtlb_hit = '0; + cva6_dtlb_ppn = '0; + // Get back to CVA6 after the translation + if (translation_valid) mmu_state_d = CVA6; + end + default: mmu_state_d = CVA6; + endcase + end + always_comb begin + // Feed forward + lsu_ctrl = lsu_ctrl_byp; + // Mask the lsu valid so that cva6's req gets buffered in the + // bypass queue when the MMU is being used by the accelerator. + lsu_ctrl.valid = (mmu_state_q == ACC) ? 1'b0 : lsu_ctrl_byp.valid; + end + end else begin + // MMU input + assign misaligned_exception = cva6_misaligned_exception; + assign st_translation_req = cva6_st_translation_req; + assign translation_req = cva6_translation_req; + assign mmu_vaddr = cva6_mmu_vaddr; + // MMU output + assign cva6_translation_valid = translation_valid; + assign cva6_mmu_paddr = mmu_paddr; + assign cva6_mmu_exception = mmu_exception; + assign cva6_dtlb_hit = dtlb_hit; + assign cva6_dtlb_ppn = dtlb_ppn; + // No accelerator + assign acc_mmu_resp_o = '0; + // Feed forward the lsu_ctrl bypass + assign lsu_ctrl = lsu_ctrl_byp; + end logic store_buffer_empty; // ------------------ @@ -397,7 +537,8 @@ module load_store_unit .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), .exception_t(exception_t), - .lsu_ctrl_t(lsu_ctrl_t) + .lsu_ctrl_t(lsu_ctrl_t), + .cbo_t(cbo_t) ) i_store_unit ( .clk_i, .rst_ni, @@ -412,21 +553,22 @@ module load_store_unit .commit_i, .commit_ready_o, .amo_valid_commit_i, + .mbe_i (mbe_i), .valid_o (st_valid), .trans_id_o (st_trans_id), .result_o (st_result), .ex_o (st_ex), // MMU port - .translation_req_o (st_translation_req), + .translation_req_o (cva6_st_translation_req), .vaddr_o (st_vaddr), .rvfi_mem_paddr_o (rvfi_mem_paddr_o), .tinst_o (st_tinst), .hs_ld_st_inst_o (st_hs_ld_st_inst), .hlvx_inst_o (st_hlvx_inst), - .paddr_i (mmu_paddr), - .ex_i (mmu_exception), - .dtlb_hit_i (dtlb_hit), + .paddr_i (cva6_mmu_paddr), + .ex_i (cva6_mmu_exception), + .dtlb_hit_i (cva6_dtlb_hit), // Load Unit .page_offset_i (page_offset), .page_offset_matches_o(page_offset_matches), @@ -435,7 +577,10 @@ module load_store_unit .amo_resp_i, // to memory arbiter .req_port_i (dcache_req_ports_i[2]), - .req_port_o (dcache_req_ports_o[2]) + .req_port_o (dcache_req_ports_o[2]), + //Trigger module + .sdtrig_store_stall_i (sdtrig_store_stall_i), + .sdtrig_store_action_i(sdtrig_store_action_i) ); // ------------------ @@ -459,16 +604,17 @@ module load_store_unit .trans_id_o (ld_trans_id), .result_o (ld_result), .ex_o (ld_ex), + .mbe_i (mbe_i), // MMU port .translation_req_o (ld_translation_req), .vaddr_o (ld_vaddr), .tinst_o (ld_tinst), .hs_ld_st_inst_o (ld_hs_ld_st_inst), .hlvx_inst_o (ld_hlvx_inst), - .paddr_i (mmu_paddr), - .ex_i (mmu_exception), - .dtlb_hit_i (dtlb_hit), - .dtlb_ppn_i (dtlb_ppn), + .paddr_i (cva6_mmu_paddr), + .ex_i (cva6_mmu_exception), + .dtlb_hit_i (cva6_dtlb_hit), + .dtlb_ppn_i (cva6_dtlb_ppn), // to store unit .page_offset_o (page_offset), .page_offset_matches_i(page_offset_matches), @@ -477,7 +623,11 @@ module load_store_unit // to memory arbiter .req_port_i (dcache_req_ports_i[1]), .req_port_o (dcache_req_ports_o[1]), - .dcache_wbuffer_not_ni_i + .dcache_wbuffer_not_ni_i, + //sdtrig + .sdtrig_load_stall_i (sdtrig_load_stall_i), + .sdtrig_load_cancel_i (sdtrig_load_cancel_i), + .sdtrig_load_action_i (sdtrig_load_action_i) ); // ---------------------------- @@ -510,22 +660,22 @@ module load_store_unit // determine whether this is a load or store always_comb begin : which_op - ld_valid_i = 1'b0; - st_valid_i = 1'b0; + ld_valid_i = 1'b0; + st_valid_i = 1'b0; - translation_req = 1'b0; - mmu_vaddr = {CVA6Cfg.VLEN{1'b0}}; - mmu_tinst = {32{1'b0}}; - mmu_hs_ld_st_inst = 1'b0; - mmu_hlvx_inst = 1'b0; + cva6_translation_req = 1'b0; + cva6_mmu_vaddr = {CVA6Cfg.VLEN{1'b0}}; + mmu_tinst = {32{1'b0}}; + mmu_hs_ld_st_inst = 1'b0; + mmu_hlvx_inst = 1'b0; // check the operation to activate the right functional unit accordingly unique case (lsu_ctrl.fu) // all loads go here LOAD: begin - ld_valid_i = lsu_ctrl.valid; - translation_req = ld_translation_req; - mmu_vaddr = ld_vaddr; + ld_valid_i = lsu_ctrl.valid; + cva6_translation_req = ld_translation_req; + cva6_mmu_vaddr = ld_vaddr; if (CVA6Cfg.RVH) begin mmu_tinst = ld_tinst; mmu_hs_ld_st_inst = ld_hs_ld_st_inst; @@ -534,9 +684,9 @@ module load_store_unit end // all stores go here STORE: begin - st_valid_i = lsu_ctrl.valid; - translation_req = st_translation_req; - mmu_vaddr = st_vaddr; + st_valid_i = lsu_ctrl.valid; + cva6_translation_req = st_translation_req; + cva6_mmu_vaddr = st_vaddr; if (CVA6Cfg.RVH) begin mmu_tinst = st_tinst; mmu_hs_ld_st_inst = st_hs_ld_st_inst; @@ -594,7 +744,7 @@ module load_store_unit // the misaligned exception is passed to the functional unit via the MMU, which in case // can augment the exception if other memory related exceptions like a page fault or access errors always_comb begin : data_misaligned_detection - misaligned_exception = { + cva6_misaligned_exception = { {CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.XLEN{1'b0}}, {CVA6Cfg.GPLEN{1'b0}}, {32{1'b0}}, 1'b0, 1'b0 }; data_misaligned = 1'b0; @@ -640,26 +790,26 @@ module load_store_unit if (data_misaligned) begin case (lsu_ctrl.fu) LOAD: begin - misaligned_exception.cause = riscv::LD_ADDR_MISALIGNED; - misaligned_exception.valid = 1'b1; + cva6_misaligned_exception.cause = riscv::LD_ADDR_MISALIGNED; + cva6_misaligned_exception.valid = 1'b1; if (CVA6Cfg.TvalEn) - misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; if (CVA6Cfg.RVH) begin - misaligned_exception.tval2 = '0; - misaligned_exception.tinst = lsu_ctrl.tinst; - misaligned_exception.gva = ld_st_v_i; + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; end end STORE: begin - misaligned_exception.cause = riscv::ST_ADDR_MISALIGNED; - misaligned_exception.valid = 1'b1; + cva6_misaligned_exception.cause = riscv::ST_ADDR_MISALIGNED; + cva6_misaligned_exception.valid = 1'b1; if (CVA6Cfg.TvalEn) - misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; if (CVA6Cfg.RVH) begin - misaligned_exception.tval2 = '0; - misaligned_exception.tinst = lsu_ctrl.tinst; - misaligned_exception.gva = ld_st_v_i; + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; end end default: ; @@ -670,25 +820,25 @@ module load_store_unit case (lsu_ctrl.fu) LOAD: begin - misaligned_exception.cause = riscv::LOAD_PAGE_FAULT; - misaligned_exception.valid = 1'b1; + cva6_misaligned_exception.cause = riscv::LOAD_PAGE_FAULT; + cva6_misaligned_exception.valid = 1'b1; if (CVA6Cfg.TvalEn) - misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; if (CVA6Cfg.RVH) begin - misaligned_exception.tval2 = '0; - misaligned_exception.tinst = lsu_ctrl.tinst; - misaligned_exception.gva = ld_st_v_i; + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; end end STORE: begin - misaligned_exception.cause = riscv::STORE_PAGE_FAULT; - misaligned_exception.valid = 1'b1; + cva6_misaligned_exception.cause = riscv::STORE_PAGE_FAULT; + cva6_misaligned_exception.valid = 1'b1; if (CVA6Cfg.TvalEn) - misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; if (CVA6Cfg.RVH) begin - misaligned_exception.tval2 = '0; - misaligned_exception.tinst = lsu_ctrl.tinst; - misaligned_exception.gva = ld_st_v_i; + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; end end default: ; @@ -699,25 +849,25 @@ module load_store_unit case (lsu_ctrl.fu) LOAD: begin - misaligned_exception.cause = riscv::LOAD_GUEST_PAGE_FAULT; - misaligned_exception.valid = 1'b1; + cva6_misaligned_exception.cause = riscv::LOAD_GUEST_PAGE_FAULT; + cva6_misaligned_exception.valid = 1'b1; if (CVA6Cfg.TvalEn) - misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; if (CVA6Cfg.RVH) begin - misaligned_exception.tval2 = '0; - misaligned_exception.tinst = lsu_ctrl.tinst; - misaligned_exception.gva = ld_st_v_i; + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; end end STORE: begin - misaligned_exception.cause = riscv::STORE_GUEST_PAGE_FAULT; - misaligned_exception.valid = 1'b1; + cva6_misaligned_exception.cause = riscv::STORE_GUEST_PAGE_FAULT; + cva6_misaligned_exception.valid = 1'b1; if (CVA6Cfg.TvalEn) - misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; + cva6_misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr}; if (CVA6Cfg.RVH) begin - misaligned_exception.tval2 = '0; - misaligned_exception.tinst = lsu_ctrl.tinst; - misaligned_exception.gva = ld_st_v_i; + cva6_misaligned_exception.tval2 = '0; + cva6_misaligned_exception.tinst = lsu_ctrl.tinst; + cva6_misaligned_exception.gva = ld_st_v_i; end end default: ; @@ -744,12 +894,15 @@ module load_store_unit be_i, fu_data_i.fu, fu_data_i.operation, - fu_data_i.trans_id + fu_data_i.trans_id, + speculative_load_i, + 1'b0 }; lsu_bypass #( .CVA6Cfg(CVA6Cfg), - .lsu_ctrl_t(lsu_ctrl_t) + .lsu_ctrl_t(lsu_ctrl_t), + .bp_resolve_t(bp_resolve_t) ) lsu_bypass_i ( .clk_i, .rst_ni, @@ -758,13 +911,12 @@ module load_store_unit .lsu_req_valid_i(lsu_valid_i), .pop_ld_i (pop_ld), .pop_st_i (pop_st), + .resolved_branch_i, - .lsu_ctrl_o(lsu_ctrl), + .lsu_ctrl_o(lsu_ctrl_byp), .ready_o (lsu_ready_o) ); assign rvfi_lsu_ctrl_o = lsu_ctrl; endmodule - - diff --git a/core/load_unit.sv b/core/load_unit.sv index 0a66c51062e..f0c5cd3bf07 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -47,6 +47,8 @@ module load_unit output logic [CVA6Cfg.XLEN-1:0] result_o, // Load exception - ISSUE_STAGE output exception_t ex_o, + // Data Endian mode - CSR_REGFILE + input logic mbe_i, // Request address translation - MMU output logic translation_req_o, // Virtual address - MMU @@ -78,7 +80,12 @@ module load_unit // Data cache request in - CACHES output dcache_req_i_t req_port_o, // Presence of non-idempotent operations in the D$ write buffer - CACHES - input logic dcache_wbuffer_not_ni_i + input logic dcache_wbuffer_not_ni_i, + + //Trigger module + input logic sdtrig_load_stall_i, + input logic sdtrig_load_cancel_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_load_action_i ); enum logic [3:0] { IDLE, @@ -89,16 +96,17 @@ module load_unit ABORT_TRANSACTION_NI, WAIT_TRANSLATION, WAIT_FLUSH, - WAIT_WB_EMPTY + WAIT_WB_EMPTY, + WAIT_SPEC_LOAD } state_d, state_q; // in order to decouple the response interface from the request interface, // we need a a buffer which can hold all inflight memory load requests typedef struct packed { - logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; // scoreboard identifier - logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] address_offset; // least significant bits of the address - fu_op operation; // type of load + logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; // scoreboard identifier + logic [CVA6Cfg.VLEN-1:0] vaddr; // virtual address + fu_op operation; // type of load } ldbuf_t; @@ -153,10 +161,6 @@ module load_unit ldbuf_flushed_d = ldbuf_flushed_q; ldbuf_valid_d = ldbuf_valid_q; - // In case of flush, raise the flushed flag in all slots. - if (flush_i) begin - ldbuf_flushed_d = '1; - end // Free read entry (in the case of fall-through mode, free the entry // only if there is no pending load) if (ldbuf_r && (!LDBUF_FALLTHROUGH || !ldbuf_w)) begin @@ -167,6 +171,15 @@ module load_unit ldbuf_flushed_d[ldbuf_windex] = 1'b0; ldbuf_valid_d[ldbuf_windex] = 1'b1; end + // In case of flush, raise the flushed flag in all slots, including any + // slot just allocated by ldbuf_w in the same cycle. This branch must + // appear after ldbuf_w so that flush_i wins the lexical priority contest + // for the newly written slot; if it appeared before, a simultaneous + // data_gnt would clear flushed_d[windex] back to 0 and the slot would + // survive the flush, later producing a phantom valid_o writeback. + if (flush_i) begin + ldbuf_flushed_d = '1; + end end always_ff @(posedge clk_i or negedge rst_ni) begin : ldbuf_ff @@ -196,10 +209,9 @@ module load_unit // this is a read-only interface so set the write enable to 0 assign req_port_o.data_we = 1'b0; assign req_port_o.data_wdata = '0; + assign req_port_o.cbo_op = ariane_pkg::CBO_NONE; // compose the load buffer write data, control is handled in the FSM - assign ldbuf_wdata = { - lsu_ctrl_i.trans_id, lsu_ctrl_i.vaddr[CVA6Cfg.XLEN_ALIGN_BYTES-1:0], lsu_ctrl_i.operation - }; + assign ldbuf_wdata = {lsu_ctrl_i.trans_id, lsu_ctrl_i.vaddr, lsu_ctrl_i.operation}; // output address // we can now output the lower 12 bit as the index to the cache assign req_port_o.address_index = lsu_ctrl_i.vaddr[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]; @@ -209,12 +221,8 @@ module load_unit CVA6Cfg.DCACHE_INDEX_WIDTH]; // request id = index of the load buffer's entry assign req_port_o.data_id = ldbuf_windex; - // directly forward exception fields (valid bit is set below) - assign ex_o.cause = ex_i.cause; - assign ex_o.tval = ex_i.tval; - assign ex_o.tval2 = CVA6Cfg.RVH ? ex_i.tval2 : '0; - assign ex_o.tinst = CVA6Cfg.RVH ? ex_i.tinst : '0; - assign ex_o.gva = CVA6Cfg.RVH ? ex_i.gva : 1'b0; + // user field not used + assign req_port_o.data_wuser = '0; // Check that NI operations follow the necessary conditions logic paddr_ni; @@ -226,7 +234,7 @@ module load_unit ); assign not_commit_time = commit_tran_id_i != lsu_ctrl_i.trans_id; assign inflight_stores = (!dcache_wbuffer_not_ni_i || !store_buffer_empty_i); - assign stall_ni = (inflight_stores || not_commit_time) && (paddr_ni && CVA6Cfg.NonIdemPotenceEn); + assign stall_ni = (inflight_stores || not_commit_time) && (paddr_ni && CVA6Cfg.NonIdemPotenceEn) || sdtrig_load_stall_i; // --------------- // Load Control @@ -249,166 +257,210 @@ module load_unit // when the load buffer is not full or if there is a response and the // load buffer is in fall-through mode accept_req = (valid_i && (!ldbuf_full || (LDBUF_FALLTHROUGH && ldbuf_r))); + if (sdtrig_load_cancel_i) begin + //cancel any possible memory access + req_port_o.data_req = 1'b0; + req_port_o.tag_valid = 1'b0; + req_port_o.kill_req = 1'b1; + translation_req_o = 1'b0; + pop_ld_o = 1'b0; + //stall load unit + state_d = IDLE; + end else begin - case (state_q) - IDLE: begin - if (accept_req) begin - // start the translation process even though we do not know if the addresses match - // this should ease timing - translation_req_o = 1'b1; - // check if the page offset matches with a store, if it does then stall and wait - if (!page_offset_matches_i) begin - // make a load request to memory - req_port_o.data_req = 1'b1; - // we got no data grant so wait for the grant before sending the tag - if (!req_port_i.data_gnt) begin - state_d = WAIT_GNT; + case (state_q) + IDLE: begin + if (accept_req) begin + if (sdtrig_load_stall_i) begin + //Stalls the load unit + req_port_o.data_req = 1'b0; + pop_ld_o = 1'b0; + state_d = IDLE; end else begin - if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin - state_d = ABORT_TRANSACTION; - end else begin - if (!stall_ni) begin - // we got a grant and a hit on the DTLB so we can send the tag in the next cycle - state_d = SEND_TAG; - pop_ld_o = 1'b1; - // translation valid but this is to NC and the WB is not yet empty. - end else if (CVA6Cfg.NonIdemPotenceEn) begin - state_d = ABORT_TRANSACTION_NI; + // start the translation process even though we do not know if the addresses match this should ease timing + // don't start the translation for speculative loads that miss on tlb + translation_req_o = (!CVA6Cfg.SpeculativeSb || dtlb_hit_i || !lsu_ctrl_i.is_speculative_load); + // check if load is speculative and non idempotent, if it is then stall and wait for branch result + if (!CVA6Cfg.SpeculativeSb || !lsu_ctrl_i.is_speculative_load || (dtlb_hit_i && !paddr_ni)) begin + // check if the page offset matches with a store, if it does then stall and wait + if (!page_offset_matches_i) begin + // make a load request to memory + req_port_o.data_req = 1'b1; + // we got no data grant so wait for the grant before sending the tag + if (!req_port_i.data_gnt) begin + state_d = WAIT_GNT; + end else begin + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = ABORT_TRANSACTION; + end else begin + if (!stall_ni) begin + // we got a grant and a hit on the DTLB so we can send the tag in the next cycle + state_d = SEND_TAG; + pop_ld_o = 1'b1; + // translation valid but this is to NC and the WB is not yet empty. + end else if (CVA6Cfg.NonIdemPotenceEn) begin + state_d = ABORT_TRANSACTION_NI; + end + end + end + end else begin + // wait for the store buffer to train and the page offset to not match anymore + state_d = WAIT_PAGE_OFFSET; end + end else begin + // check branch result on the next cycle + state_d = WAIT_SPEC_LOAD; end end - end else begin - // wait for the store buffer to train and the page offset to not match anymore - state_d = WAIT_PAGE_OFFSET; end end - end - // wait here for the page offset to not match anymore - WAIT_PAGE_OFFSET: begin - // we make a new request as soon as the page offset does not match anymore - if (!page_offset_matches_i) begin - state_d = WAIT_GNT; + // wait here for the page offset to not match anymore + WAIT_PAGE_OFFSET: begin + // we make a new request as soon as the page offset does not match anymore + if (!page_offset_matches_i) begin + state_d = WAIT_GNT; + end end - end - WAIT_GNT: begin - // keep the translation request up - translation_req_o = 1'b1; - // keep the request up - req_port_o.data_req = 1'b1; - // we finally got a data grant - if (req_port_i.data_gnt) begin - // so we send the tag in the next cycle - if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin - state_d = ABORT_TRANSACTION; - end else begin - if (!stall_ni) begin - // we got a grant and a hit on the DTLB so we can send the tag in the next cycle - state_d = SEND_TAG; + WAIT_SPEC_LOAD: begin + // if we have a misspredicted speculative load + if (CVA6Cfg.SpeculativeSb && lsu_ctrl_i.is_speculative_load_miss) begin + // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction + if (!req_port_i.data_rvalid) begin + state_d = IDLE; pop_ld_o = 1'b1; - // translation valid but this is to NC and the WB is not yet empty. - end else if (CVA6Cfg.NonIdemPotenceEn) begin - state_d = ABORT_TRANSACTION_NI; end + // if we have a correct prediction this is now a regular load + end else begin + state_d = IDLE; end - end - // otherwise we keep waiting on our grant - end - // we know for sure that the tag we want to send is valid - SEND_TAG: begin - req_port_o.tag_valid = 1'b1; - state_d = IDLE; - - if (accept_req) begin - // start the translation process even though we do not know if the addresses match - // this should ease timing - translation_req_o = 1'b1; - // check if the page offset matches with a store, if it does stall and wait - if (!page_offset_matches_i) begin - // make a load request to memory - req_port_o.data_req = 1'b1; - // we got no data grant so wait for the grant before sending the tag - if (!req_port_i.data_gnt) begin - state_d = WAIT_GNT; + + WAIT_GNT: begin + // keep the translation request up + translation_req_o = 1'b1; + // keep the request up + req_port_o.data_req = 1'b1; + // we finally got a data grant + if (req_port_i.data_gnt) begin + // so we send the tag in the next cycle + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = ABORT_TRANSACTION; end else begin - // we got a grant so we can send the tag in the next cycle - if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin - state_d = ABORT_TRANSACTION; - end else begin - if (!stall_ni) begin - // we got a grant and a hit on the DTLB so we can send the tag in the next cycle - state_d = SEND_TAG; - pop_ld_o = 1'b1; - // translation valid but this is to NC and the WB is not yet empty. - end else if (CVA6Cfg.NonIdemPotenceEn) begin - state_d = ABORT_TRANSACTION_NI; - end + if (!stall_ni) begin + // we got a grant and a hit on the DTLB so we can send the tag in the next cycle + state_d = SEND_TAG; + pop_ld_o = 1'b1; + // translation valid but this is to NC and the WB is not yet empty. + end else if (CVA6Cfg.NonIdemPotenceEn) begin + state_d = ABORT_TRANSACTION_NI; end end - end else begin - // wait for the store buffer to train and the page offset to not match anymore - state_d = WAIT_PAGE_OFFSET; + end + // otherwise we keep waiting on our grant end - // ---------- - // Exception - // ---------- - // if we got an exception we need to kill the request immediately - if (ex_i.valid) begin - req_port_o.kill_req = 1'b1; - end - end + // we know for sure that the tag we want to send is valid + SEND_TAG: begin + req_port_o.tag_valid = 1'b1; + state_d = IDLE; - WAIT_FLUSH: begin - // the D$ arbiter will take care of presenting this to the memory only in case we - // have an outstanding request - req_port_o.kill_req = 1'b1; - req_port_o.tag_valid = 1'b1; - // we've killed the current request so we can go back to idle - state_d = IDLE; - end + if (accept_req) begin + // start the translation process even though we do not know if the addresses match this should ease timing + // don't start the translation for speculative loads that miss on tlb + translation_req_o = (!CVA6Cfg.SpeculativeSb || dtlb_hit_i || !lsu_ctrl_i.is_speculative_load); + // check if load is speculative and non idempotent, if it is then stall and wait for branch result + if (!CVA6Cfg.SpeculativeSb || !lsu_ctrl_i.is_speculative_load || (dtlb_hit_i && !paddr_ni)) begin + // check if the page offset matches with a store, if it does stall and wait + if (!page_offset_matches_i) begin + // make a load request to memory + req_port_o.data_req = 1'b1; + // we got no data grant so wait for the grant before sending the tag + if (!req_port_i.data_gnt) begin + state_d = WAIT_GNT; + end else begin + // we got a grant so we can send the tag in the next cycle + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = ABORT_TRANSACTION; + end else begin + if (!stall_ni) begin + // we got a grant and a hit on the DTLB so we can send the tag in the next cycle + state_d = SEND_TAG; + pop_ld_o = 1'b1; + // translation valid but this is to NC and the WB is not yet empty. + end else if (CVA6Cfg.NonIdemPotenceEn) begin + state_d = ABORT_TRANSACTION_NI; + end + end + end + end else begin + // wait for the store buffer to train and the page offset to not match anymore + state_d = WAIT_PAGE_OFFSET; + end + end else begin + // check branch result on the next cycle + state_d = WAIT_SPEC_LOAD; + end + end + // ---------- + // Exception + // ---------- + // if we got an exception we need to kill the request immediately + if (ex_i.valid) begin + req_port_o.kill_req = 1'b1; + end + end - default: begin - // abort the previous request - free the D$ arbiter - // we are here because of a TLB miss, we need to abort the current request and give way for the - // PTW walker to satisfy the TLB miss - if (state_q == ABORT_TRANSACTION && CVA6Cfg.MmuPresent) begin - req_port_o.kill_req = 1'b1; - req_port_o.tag_valid = 1'b1; - // wait until the WB is empty - state_d = WAIT_TRANSLATION; - end else if (state_q == ABORT_TRANSACTION_NI && CVA6Cfg.NonIdemPotenceEn) begin + WAIT_FLUSH: begin + // the D$ arbiter will take care of presenting this to the memory only in case we + // have an outstanding request req_port_o.kill_req = 1'b1; req_port_o.tag_valid = 1'b1; - // re-do the request - state_d = WAIT_WB_EMPTY; - end else if (state_q == WAIT_WB_EMPTY && CVA6Cfg.NonIdemPotenceEn && dcache_wbuffer_not_ni_i) begin - // Wait until the write-back buffer is empty in the data cache. - // the write buffer is empty, so lets go and re-do the translation. - state_d = WAIT_TRANSLATION; - end else if(state_q == WAIT_TRANSLATION && (CVA6Cfg.MmuPresent || CVA6Cfg.NonIdemPotenceEn)) begin - translation_req_o = 1'b1; - // we've got a hit and we can continue with the request process - if (dtlb_hit_i) state_d = WAIT_GNT; - - // we got an exception - if (ex_i.valid) begin - // the next state will be the idle state - state_d = IDLE; - // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction - pop_ld_o = ~req_port_i.data_rvalid; - end - end else begin + // we've killed the current request so we can go back to idle state_d = IDLE; end - end - endcase - // if we just flushed and the queue is not empty or we are getting an rvalid this cycle wait in a extra stage - if (flush_i) begin - state_d = WAIT_FLUSH; + default: begin + // abort the previous request - free the D$ arbiter + // we are here because of a TLB miss, we need to abort the current request and give way for the + // PTW walker to satisfy the TLB miss + if (state_q == ABORT_TRANSACTION && CVA6Cfg.MmuPresent) begin + req_port_o.kill_req = 1'b1; + req_port_o.tag_valid = 1'b1; + // wait until the WB is empty + state_d = WAIT_TRANSLATION; + end else if (state_q == ABORT_TRANSACTION_NI && CVA6Cfg.NonIdemPotenceEn) begin + req_port_o.kill_req = 1'b1; + req_port_o.tag_valid = 1'b1; + // re-do the request + state_d = WAIT_WB_EMPTY; + end else if (state_q == WAIT_WB_EMPTY && CVA6Cfg.NonIdemPotenceEn && dcache_wbuffer_not_ni_i) begin + // Wait until the write-back buffer is empty in the data cache. + // the write buffer is empty, so let's go and re-do the translation. + state_d = WAIT_TRANSLATION; + end else if(state_q == WAIT_TRANSLATION && (CVA6Cfg.MmuPresent || CVA6Cfg.NonIdemPotenceEn)) begin + translation_req_o = 1'b1; + // we've got a hit and we can continue with the request process + if (dtlb_hit_i) state_d = WAIT_GNT; + + // we got an exception + if (ex_i.valid) begin + // the next state will be the idle state + state_d = IDLE; + // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction + pop_ld_o = ~req_port_i.data_rvalid; + end + end else begin + state_d = IDLE; + end + end + endcase + + // if we just flushed and the queue is not empty or we are getting an rvalid this cycle wait in an extra stage + if (flush_i) begin + state_d = WAIT_FLUSH; + end end end @@ -418,27 +470,46 @@ module load_unit // --------------- // Retire Load // --------------- - assign ldbuf_rindex = (CVA6Cfg.NrLoadBufEntries > 1) ? ldbuf_id_t'(req_port_i.data_rid) : 1'b0, - ldbuf_rdata = ldbuf_q[ldbuf_rindex]; + assign ldbuf_rindex = (CVA6Cfg.NrLoadBufEntries > 1) ? ldbuf_id_t'(req_port_i.data_rid) : 1'b0; + assign ldbuf_rdata = ldbuf_q[ldbuf_rindex]; // decoupled rvalid process always_comb begin : rvalid_output // read the pending load buffer - ldbuf_r = req_port_i.data_rvalid; + ldbuf_r = req_port_i.data_rvalid; trans_id_o = ldbuf_q[ldbuf_rindex].trans_id; - valid_o = 1'b0; - ex_o.valid = 1'b0; + valid_o = 1'b0; - // we got an rvalid and it's corresponding request was not flushed + // directly forward exception fields (valid bit is set below) + ex_o.valid = 1'b0; + ex_o.cause = (sdtrig_load_action_i != '0) ? sdtrig_load_action_i : ex_i.cause; + ex_o.tval = (CVA6Cfg.TvalEn && (sdtrig_load_action_i != '0)) ? lsu_ctrl_i.vaddr : ex_i.tval; + ex_o.tval2 = CVA6Cfg.RVH ? ex_i.tval2 : '0; + ex_o.tinst = CVA6Cfg.RVH ? ex_i.tinst : '0; + ex_o.gva = CVA6Cfg.RVH ? ex_i.gva : 1'b0; + ex_o.timing = (sdtrig_load_stall_i && req_port_i.data_rvalid && sdtrig_load_action_i != '0) ? 1'b1 : 1'b0; + + // we got an rvalid and its corresponding request was not flushed if (req_port_i.data_rvalid && !ldbuf_flushed_q[ldbuf_rindex]) begin // if the response corresponds to the last request, check that we are not killing it - if ((ldbuf_last_id_q != ldbuf_rindex) || !req_port_o.kill_req) valid_o = 1'b1; + if ((ldbuf_last_id_q != ldbuf_rindex) || !req_port_o.kill_req) begin + valid_o = 1'b1; + ex_o.valid = req_port_i.data_error; + ex_o.cause = riscv::HARDWARE_ERROR; + if (CVA6Cfg.TvalEn) begin + ex_o.tval = ldbuf_rdata.vaddr; + end + end // the output is also valid if we got an exception. An exception arrives one cycle after // dtlb_hit_i is asserted, i.e. when we are in SEND_TAG. Otherwise, the exception // corresponds to the next request that is already being translated (see below). - if (ex_i.valid && (state_q == SEND_TAG)) begin + if ((state_q == SEND_TAG) && (ex_i.valid || req_port_i.data_error)) begin valid_o = 1'b1; ex_o.valid = 1'b1; + ex_o.cause = req_port_i.data_error ? riscv::HARDWARE_ERROR : ex_i.cause; + if (CVA6Cfg.TvalEn && req_port_i.data_error) begin + ex_o.tval = ldbuf_rdata.vaddr; + end end end @@ -446,11 +517,18 @@ module load_unit // exceptions can retire out-of-order -> but we need to give priority to non-excepting load and stores // so we simply check if we got an rvalid if so we prioritize it by not retiring the exception - we simply go for another // round in the load FSM - if ((CVA6Cfg.MmuPresent || CVA6Cfg.NonIdemPotenceEn) && (state_q == WAIT_TRANSLATION) && !req_port_i.data_rvalid && ex_i.valid && valid_i) begin + if (sdtrig_load_cancel_i || (CVA6Cfg.MmuPresent || CVA6Cfg.NonIdemPotenceEn) && (state_q == WAIT_TRANSLATION) && !req_port_i.data_rvalid && ex_i.valid && valid_i) begin trans_id_o = lsu_ctrl_i.trans_id; valid_o = 1'b1; ex_o.valid = 1'b1; end + + // raise valid when removing a misspredicted speculative load + if (CVA6Cfg.SpeculativeSb && (state_q == WAIT_SPEC_LOAD) && lsu_ctrl_i.is_speculative_load_miss && !req_port_i.data_rvalid && valid_i) begin + trans_id_o = lsu_ctrl_i.trans_id; + valid_o = 1'b1; + ex_o.valid = 1'b0; + end end @@ -467,11 +545,16 @@ module load_unit // Sign Extend // --------------- logic [CVA6Cfg.XLEN-1:0] shifted_data; + logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] ldbuf_addroff; + + assign ldbuf_addroff = ldbuf_rdata.vaddr[CVA6Cfg.XLEN_ALIGN_BYTES-1:0]; // realign as needed - assign shifted_data = req_port_i.data_rdata >> {ldbuf_rdata.address_offset, 3'b000}; + // ldbuf_rdata.address_offset is just the last three bits of the load address which select the byte address within the word + assign shifted_data = req_port_i.data_rdata >> {ldbuf_addroff, 3'b000}; - /* // result mux (leaner code, but more logic stages. + // The code here is legacy - from the days before CVA6 was Big Endian Capable :) + /*// result mux (leaner code, but more logic stages. // can be used instead of the code below (in between //result mux fast) if timing is not so critical) always_comb begin unique case (ldbuf_rdata.operation) @@ -485,6 +568,50 @@ module load_unit endcase end */ + /* + // BIG ENDIAN CAPABLE result mux + // Can be used instead of the code below (in between "BIG ENDIAN CAPABLE result mux fast" and "end BIG ENDIAN CAPABLE result mux fast") if timing is not so critical. + // This code has been tested and is functionally identical to "BIG ENDIAN CAPABLE result mux fast", and while commented out it still aids in the readability of load_unit.sv. + always_comb begin + unique case (ldbuf_rdata.operation) + LWU: result_o = 64'(unsigned'(mbe_i ? {<<8{shifted_data[31:0]}} : shifted_data[31:0])); + LHU: result_o = 64'(unsigned'(mbe_i ? {<<8{shifted_data[15:0]}} : shifted_data[15:0])); + LBU: result_o = 64'(unsigned'(shifted_data[7:0])); + LW: result_o = 64'(signed'(mbe_i ? {<<8{shifted_data[31:0]}} : shifted_data[31:0])); + LH: result_o = 64'(signed'(mbe_i ? {<<8{shifted_data[15:0]}} : shifted_data[15:0])); + LB: result_o = 64'(signed'(shifted_data[ 7:0])); + default: result_o = mbe_i ? {<<8{shifted_data}} : shifted_data; + endcase + end + */ + + // BIG ENDIAN CAPABLE result mux fast + logic [CVA6Cfg.XLEN-1:0] endian_data; + + // Reversing the order of the Bytes in the data loaded from memory if mbe=1 -> which comes from the CSRregfile meaning the processor is in Big Endian Mode. + // If mbe=1 then the processor should treat Data memory as Big Endian. The internals of CVA6 are Little endian, so we achieve this by Reversing the Byte Order to Little Endian when it enters the processor through a Load. + always_comb begin + endian_data = shifted_data; + if (mbe_i) begin + case (ldbuf_rdata.operation) + LB, LBU, HLV_B, HLV_BU, FLB: begin + // If we are just loading a byte, then this needs not be touched + endian_data[7:0] = {shifted_data[7:0]}; + end + LH, LHU, HLV_H, HLV_HU, HLVX_HU, FLH: begin + endian_data[15:0] = {<<8{shifted_data[15:0]}}; + end + LW, LWU, HLV_W, HLV_WU, HLVX_WU, FLW, AMO_LRW, AMO_SCW, AMO_SWAPW, AMO_ADDW, + AMO_ANDW, AMO_ORW, AMO_XORW, AMO_MAXW, AMO_MAXWU, AMO_MINW, AMO_MINWU: begin + endian_data[31:0] = {<<8{shifted_data[31:0]}}; + end + default: begin + endian_data[CVA6Cfg.XLEN-1:0] = {<<8{shifted_data[CVA6Cfg.XLEN-1:0]}}; + end + endcase + end + end + // result mux fast logic [ (CVA6Cfg.XLEN/8)-1:0] rdata_sign_bits; logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] rdata_offset; @@ -494,9 +621,10 @@ module load_unit // prepare these signals for faster selection in the next cycle assign rdata_is_signed = ldbuf_rdata.operation inside {ariane_pkg::LW, ariane_pkg::LH, ariane_pkg::LB, ariane_pkg::HLV_W, ariane_pkg::HLV_H, ariane_pkg::HLV_B}; assign rdata_is_fp_signed = ldbuf_rdata.operation inside {ariane_pkg::FLW, ariane_pkg::FLH, ariane_pkg::FLB}; - assign rdata_offset = ((ldbuf_rdata.operation inside {ariane_pkg::LW, ariane_pkg::FLW, ariane_pkg::HLV_W}) & CVA6Cfg.IS_XLEN64) ? ldbuf_rdata.address_offset + 3 : - ( ldbuf_rdata.operation inside {ariane_pkg::LH, ariane_pkg::FLH, ariane_pkg::HLV_H}) ? ldbuf_rdata.address_offset + 1 : - ldbuf_rdata.address_offset; + // If we are in Big Endian Mode, we don't need to add anything to the address offset to find the byte that contains the sign bit, as it is always the lowest addressed byte that has the sign bit. + assign rdata_offset = ((ldbuf_rdata.operation inside {ariane_pkg::LW, ariane_pkg::FLW, ariane_pkg::HLV_W}) && CVA6Cfg.IS_XLEN64 && (~mbe_i)) ? ldbuf_addroff + 3 : + ( ldbuf_rdata.operation inside {ariane_pkg::LH, ariane_pkg::FLH, ariane_pkg::HLV_H} && (~mbe_i)) ? ldbuf_addroff + 1 : + ldbuf_addroff; for (genvar i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : gen_sign_bits assign rdata_sign_bits[i] = req_port_i.data_rdata[(i+1)*8-1]; @@ -505,41 +633,41 @@ module load_unit // select correct sign bit in parallel to result shifter above // pull to 0 if unsigned - assign rdata_sign_bit = rdata_is_signed & rdata_sign_bits[rdata_offset] | (CVA6Cfg.FpPresent && rdata_is_fp_signed); + assign rdata_sign_bit = (rdata_is_signed && rdata_sign_bits[rdata_offset]) || (CVA6Cfg.FpPresent && rdata_is_fp_signed); // result mux always_comb begin unique case (ldbuf_rdata.operation) ariane_pkg::LW, ariane_pkg::LWU, ariane_pkg::HLV_W, ariane_pkg::HLV_WU, ariane_pkg::HLVX_WU: - result_o = {{CVA6Cfg.XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]}; + result_o = {{CVA6Cfg.XLEN - 32{rdata_sign_bit}}, endian_data[31:0]}; ariane_pkg::LH, ariane_pkg::LHU, ariane_pkg::HLV_H, ariane_pkg::HLV_HU, ariane_pkg::HLVX_HU: - result_o = {{CVA6Cfg.XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]}; + result_o = {{CVA6Cfg.XLEN - 32 + 16{rdata_sign_bit}}, endian_data[15:0]}; ariane_pkg::LB, ariane_pkg::LBU, ariane_pkg::HLV_B, ariane_pkg::HLV_BU: - result_o = {{CVA6Cfg.XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]}; + result_o = {{CVA6Cfg.XLEN - 32 + 24{rdata_sign_bit}}, endian_data[7:0]}; default: begin // FLW, FLH and FLB have been defined here in default case to improve Code Coverage if (CVA6Cfg.FpPresent) begin unique case (ldbuf_rdata.operation) ariane_pkg::FLW: begin - result_o = {{CVA6Cfg.XLEN - 32{rdata_sign_bit}}, shifted_data[31:0]}; + result_o = {{CVA6Cfg.XLEN - 32{rdata_sign_bit}}, endian_data[31:0]}; end ariane_pkg::FLH: begin - result_o = {{CVA6Cfg.XLEN - 32 + 16{rdata_sign_bit}}, shifted_data[15:0]}; + result_o = {{CVA6Cfg.XLEN - 32 + 16{rdata_sign_bit}}, endian_data[15:0]}; end ariane_pkg::FLB: begin - result_o = {{CVA6Cfg.XLEN - 32 + 24{rdata_sign_bit}}, shifted_data[7:0]}; + result_o = {{CVA6Cfg.XLEN - 32 + 24{rdata_sign_bit}}, endian_data[7:0]}; end default: begin - result_o = shifted_data[CVA6Cfg.XLEN-1:0]; + result_o = endian_data[CVA6Cfg.XLEN-1:0]; end endcase end else begin - result_o = shifted_data[CVA6Cfg.XLEN-1:0]; + result_o = endian_data[CVA6Cfg.XLEN-1:0]; end end endcase end - // end result mux fast + // end BIG ENDIAN CAPABLE result mux fast /////////////////////////////////////////////////////// // assertions @@ -552,15 +680,18 @@ module load_unit // check invalid offsets, but only issue a warning as these conditions actually trigger a load address misaligned exception addr_offset0 : assert property (@(posedge clk_i) disable iff (~rst_ni) - ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LW, ariane_pkg::LWU}) |-> ldbuf_wdata.address_offset < 5) - else $fatal(1, "invalid address offset used with {LW, LWU}"); + ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LW, ariane_pkg::LWU}) + |-> ldbuf_wdata.vaddr[CVA6Cfg.XLEN_ALIGN_BYTES-1:0] < 5) + else $warning("invalid address offset used with {LW, LWU}"); addr_offset1 : assert property (@(posedge clk_i) disable iff (~rst_ni) - ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LH, ariane_pkg::LHU}) |-> ldbuf_wdata.address_offset < 7) - else $fatal(1, "invalid address offset used with {LH, LHU}"); + ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LH, ariane_pkg::LHU}) + |-> ldbuf_wdata.vaddr[CVA6Cfg.XLEN_ALIGN_BYTES-1:0] < 7) + else $warning("invalid address offset used with {LH, LHU}"); addr_offset2 : assert property (@(posedge clk_i) disable iff (~rst_ni) - ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LB, ariane_pkg::LBU}) |-> ldbuf_wdata.address_offset < 8) + ldbuf_w |-> (ldbuf_wdata.operation inside {ariane_pkg::LB, ariane_pkg::LBU}) + |-> ldbuf_wdata.vaddr[CVA6Cfg.XLEN_ALIGN_BYTES-1:0] < 8) else $fatal(1, "invalid address offset used with {LB, LBU}"); //pragma translate_on diff --git a/core/lsu_bypass.sv b/core/lsu_bypass.sv index 2b9f2aaa6fa..f184a4d26a8 100644 --- a/core/lsu_bypass.sv +++ b/core/lsu_bypass.sv @@ -16,8 +16,8 @@ // ------------------ // LSU Control // ------------------ -// The LSU consists of two independent block which share a common address translation block. -// The one block is the load unit, the other one is the store unit. They will signal their readiness +// The LSU consists of two independent blocks which share a common address translation block. +// One block is the load unit, the other one is the store unit. They will signal their readiness // with separate signals. If they are not ready the LSU control should keep the last applied signals stable. // Furthermore it can be the case that another request for one of the two store units arrives in which case // the LSU control should sample it and store it for later application to the units. It does so, by storing it in a @@ -27,7 +27,8 @@ module lsu_bypass import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type lsu_ctrl_t = logic + parameter type lsu_ctrl_t = logic, + parameter type bp_resolve_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -45,6 +46,9 @@ module lsu_bypass // TO_BE_COMPLETED - TO_BE_COMPLETED input logic pop_st_i, + // Result from branch unit - EX_STAGE + input bp_resolve_t resolved_branch_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output lsu_ctrl_t lsu_ctrl_o, // TO_BE_COMPLETED - TO_BE_COMPLETED @@ -73,6 +77,15 @@ module lsu_bypass // we've got a valid LSU request if (lsu_req_valid_i) begin mem_n[write_pointer_q] = lsu_req_i; + if (lsu_req_i.is_speculative_load && resolved_branch_i.valid) begin + if (resolved_branch_i.is_mispredict) begin + // missprediction: mark speculative loads as misspredicted + mem_n[write_pointer_q].is_speculative_load_miss = 1'b1; + end else begin + // correct prediction: the load is no longer speculative + mem_n[write_pointer_q].is_speculative_load = 1'b0; + end + end write_pointer++; status_cnt++; end diff --git a/core/macro_decoder.sv b/core/macro_decoder.sv index 0d695a3372b..a182cf56e48 100644 --- a/core/macro_decoder.sv +++ b/core/macro_decoder.sv @@ -20,14 +20,14 @@ module macro_decoder #( input logic [31:0] instr_i, input logic clk_i, // Clock input logic rst_ni, // Synchronous reset - input logic is_macro_instr_i, // Intruction is of macro extension + input logic is_macro_instr_i, // Instruction is of macro extension input logic illegal_instr_i, // From compressed decoder input logic is_compressed_i, - input logic issue_ack_i, // Check if the intruction is acknowledged + input logic issue_ack_i, // Check if the instruction is acknowledged output logic [31:0] instr_o, output logic illegal_instr_o, output logic is_compressed_o, - output logic fetch_stall_o, //Wait while push/pop/move instructions expand + output logic fetch_stall_o, // Wait while push/pop/move instructions expand output logic is_last_macro_instr_o, output logic is_double_rd_macro_instr_o ); @@ -82,6 +82,11 @@ module macro_decoder #( unique case (instr_i[12:10]) // push or pop 3'b110: begin + if (instr_i[7:4] < 4'b0100) begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + unique case (instr_i[9:8]) 2'b00: begin macro_instr_type = PUSH; @@ -97,6 +102,11 @@ module macro_decoder #( end // popret or popretz 3'b111: begin + if (instr_i[7:4] < 4'b0100) begin + illegal_instr_o = 1'b1; + instr_o_reg = instr_i; + end + unique case (instr_i[9:8]) 2'b00: begin macro_instr_type = POPRETZ; @@ -133,7 +143,7 @@ module macro_decoder #( // Calculate xreg1 & xreg2 for move instructions if (macro_instr_type == MVSA01 || macro_instr_type == MVA01S) begin - if (instr_i[9:7] != instr_i[4:2]) begin + if (macro_instr_type == MVA01S || instr_i[9:7] != instr_i[4:2]) begin xreg1 = {instr_i[9:8] > 0, instr_i[9:8] == 0, instr_i[9:7]}; xreg2 = {instr_i[4:3] > 0, instr_i[4:3] == 0, instr_i[4:2]}; end else begin @@ -162,7 +172,7 @@ module macro_decoder #( default: reg_numbers = '0; endcase - if (CVA6Cfg.XLEN == 32) begin + if (CVA6Cfg.IS_XLEN32) begin unique case (instr_i[7:4]) 4'b0100, 4'b0101, 4'b0110, 4'b0111: begin unique case (instr_i[3:2]) @@ -272,7 +282,7 @@ module macro_decoder #( unique case (state_q) IDLE: begin - if (is_macro_instr_i) begin + if (is_macro_instr_i && !illegal_instr_o) begin reg_numbers_d = reg_numbers - 1'b1; state_d = issue_ack_i ? INIT : IDLE; case (macro_instr_type) @@ -311,7 +321,9 @@ module macro_decoder #( is_double_rd_macro_instr_o = 1; // addi xreg1, a0, 0 instr_o_reg = {12'h0, 5'hA, 3'h0, xreg1, riscv::OpcodeOpImm}; - state_d = MOVE; + if (issue_ack_i) begin + state_d = MOVE; + end end if (macro_instr_type == MVA01S) begin @@ -319,7 +331,9 @@ module macro_decoder #( is_double_rd_macro_instr_o = 1; // addi a0, xreg1, 0 instr_o_reg = {12'h0, xreg1, 3'h0, 5'hA, riscv::OpcodeOpImm}; - state_d = MOVE; + if (issue_ack_i) begin + state_d = MOVE; + end end if (macro_instr_type == PUSH) begin @@ -327,7 +341,7 @@ module macro_decoder #( fetch_stall_o = 1'b1; // stall inst fetch if (reg_numbers == 4'b0001) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { 7'b1111111, 5'h1, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore }; // sd store_reg, -4(sp) @@ -336,11 +350,13 @@ module macro_decoder #( 7'b1111111, 5'h1, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore }; // sw store_reg, -4(sp) end - state_d = PUSH_ADDI; + if (issue_ack_i) begin + state_d = PUSH_ADDI; + end end if (reg_numbers == 4'b0010) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = {7'b1111111, 5'h8, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore}; end else begin instr_o_reg = {7'b1111111, 5'h8, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore}; @@ -348,7 +364,7 @@ module macro_decoder #( end if (reg_numbers == 4'b0011) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = {7'b1111111, 5'h9, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore}; end else begin instr_o_reg = {7'b1111111, 5'h9, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore}; @@ -357,13 +373,13 @@ module macro_decoder #( end if (reg_numbers >= 4 && reg_numbers <= 12) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = {7'b1111111, store_reg, 5'h2, 3'h3, 5'b11000, riscv::OpcodeStore}; end else begin instr_o_reg = {7'b1111111, store_reg, 5'h2, 3'h2, 5'b11100, riscv::OpcodeStore}; end - if (reg_numbers == 12) begin + if (reg_numbers == 12 && issue_ack_i) begin state_d = PUSH_POP_INSTR_2; end end @@ -372,7 +388,7 @@ module macro_decoder #( if ((macro_instr_type == POP || macro_instr_type == POPRETZ || macro_instr_type == POPRET)) begin fetch_stall_o = 1; // stall inst fetch if (reg_numbers == 1) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { offset_reg - 12'h4, 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad }; // ld store_reg, Imm(sp) @@ -381,19 +397,21 @@ module macro_decoder #( offset_reg, 5'h2, 3'h2, 5'h1, riscv::OpcodeLoad }; // lw store_reg, Imm(sp) end - unique case (macro_instr_type) - PUSH, POP, POPRET: begin - state_d = PUSH_ADDI; - end - POPRETZ: begin - state_d = POPRETZ_1; - end - default: ; - endcase + if (issue_ack_i) begin + unique case (macro_instr_type) + PUSH, POP, POPRET: begin + state_d = PUSH_ADDI; + end + POPRETZ: begin + state_d = POPRETZ_1; + end + default: ; + endcase + end end if (reg_numbers == 2) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = {offset_reg - 12'h4, 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad}; end else begin instr_o_reg = {offset_reg, 5'h2, 3'h2, 5'h8, riscv::OpcodeLoad}; @@ -401,7 +419,7 @@ module macro_decoder #( end if (reg_numbers == 3) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = {offset_reg - 12'h4, 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad}; end else begin instr_o_reg = {offset_reg, 5'h2, 3'h2, 5'h9, riscv::OpcodeLoad}; @@ -409,13 +427,13 @@ module macro_decoder #( end if (reg_numbers >= 4 && reg_numbers <= 12) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = {offset_reg - 12'h4, 5'h2, 3'h3, store_reg, riscv::OpcodeLoad}; end else begin instr_o_reg = {offset_reg, 5'h2, 3'h2, store_reg, riscv::OpcodeLoad}; end - if (reg_numbers == 12) begin + if (reg_numbers == 12 && issue_ack_i) begin state_d = PUSH_POP_INSTR_2; end end @@ -426,7 +444,7 @@ module macro_decoder #( fetch_stall_o = is_macro_instr_i; // stall inst fetch if (issue_ack_i && is_macro_instr_i && macro_instr_type == PUSH) begin if (reg_numbers_q == 4'b0001) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { offset_d[11:5], 5'h1, @@ -444,7 +462,7 @@ module macro_decoder #( end if (reg_numbers_q == 4'b0010) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { offset_d[11:5], 5'h8, @@ -459,11 +477,11 @@ module macro_decoder #( instr_o_reg = {offset_d[11:5], 5'h8, 5'h2, 3'h2, offset_d[4:0], riscv::OpcodeStore}; end reg_numbers_d = reg_numbers_q - 1; - offset_d = offset_q + 12'hFFC; // decrement offset by -4 i.e. add 2's compilment of 4 + offset_d = offset_q + 12'hFFC; // decrement offset by -4 i.e. add 2's complement of 4 end if (reg_numbers_q == 4'b0011) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { offset_d[11:5], 5'h9, @@ -482,7 +500,7 @@ module macro_decoder #( end if (reg_numbers_q >= 4 && reg_numbers_q <= 12) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { offset_d[11:5], store_reg_q, @@ -510,7 +528,7 @@ module macro_decoder #( if (issue_ack_i && is_macro_instr_i && (macro_instr_type == POP || macro_instr_type == POPRETZ || macro_instr_type == POPRET)) begin if (reg_numbers_q == 1) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, 5'h1, riscv::OpcodeLoad }; @@ -529,7 +547,7 @@ module macro_decoder #( end if (reg_numbers_q == 2) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, 5'h8, riscv::OpcodeLoad }; @@ -541,7 +559,7 @@ module macro_decoder #( end if (reg_numbers_q == 3) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, 5'h9, riscv::OpcodeLoad }; @@ -553,7 +571,7 @@ module macro_decoder #( end if (reg_numbers_q >= 4 && reg_numbers_q <= 12) begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin instr_o_reg = { offset_d[11:3], 1'b0, offset_d[1:0], 5'h2, 3'h3, store_reg_q, riscv::OpcodeLoad }; @@ -600,7 +618,7 @@ module macro_decoder #( end PUSH_ADDI: begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin if (issue_ack_i && is_macro_instr_i && macro_instr_type == PUSH) begin // addi sp, sp, stack_adj instr_o_reg = {itype_inst.imm - 12'h4, 5'h2, 3'h0, 5'h2, riscv::OpcodeOpImm}; @@ -646,7 +664,7 @@ module macro_decoder #( end PUSH_POP_INSTR_2: begin - if (CVA6Cfg.XLEN == 64) begin + if (CVA6Cfg.IS_XLEN64) begin case (macro_instr_type) PUSH: begin if (issue_ack_i) begin diff --git a/core/multiplier.sv b/core/multiplier.sv index b6c44f7f7b3..7ae4b50af65 100644 --- a/core/multiplier.sv +++ b/core/multiplier.sv @@ -144,6 +144,9 @@ module multiplier clmulr_q <= clmulr_d; end end + end else begin + assign clmul_q = '0; + assign clmulr_q = '0; end // ----------------------- // Output pipeline register diff --git a/core/pmp/README.md b/core/pmp/README.md index bd046dd5be2..0103035a7a9 100644 --- a/core/pmp/README.md +++ b/core/pmp/README.md @@ -1,5 +1,5 @@ # PMP -This repository houses a purely combinatorial and parametrizable physical memory protection (PMP) unit. +This repository houses a purely combinatorial and parameterizable physical memory protection (PMP) unit. __Warning__: The PMP unit does only check the exact byte that is addressed. If the processor wants to load a 8 byte value, then every single byte should get checked. Due to the default granularity of PMPs of 4 bytes, this only comes into play for 8byte RISC-V memory accesses. An easy fix is to increase the granularity to 8 bytes. You can do this by setting the lowest bit of conf_addr_i to 1 if the pmp is in NAPOT mode, or to 0 if the PMP is in TOR mode. \ No newline at end of file diff --git a/core/pmp/src/pmp.sv b/core/pmp/src/pmp.sv index f3498711edf..b6d0dbf2ec9 100644 --- a/core/pmp/src/pmp.sv +++ b/core/pmp/src/pmp.sv @@ -12,7 +12,9 @@ // Date: 2.10.2019 // Description: purely combinatorial PMP unit (with extraction for more complex configs such as NAPOT) -module pmp #( +module pmp + import ariane_pkg::*; +#( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( // Input @@ -20,8 +22,8 @@ module pmp #( input riscv::pmp_access_t access_type_i, input riscv::priv_lvl_t priv_lvl_i, // Configuration - input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] conf_addr_i, - input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] conf_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] conf_addr_i, + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] conf_i, // Output output logic allow_o ); diff --git a/core/pmp/src/pmp_data_if.sv b/core/pmp/src/pmp_data_if.sv index d18149fb29b..a944a2bed58 100644 --- a/core/pmp/src/pmp_data_if.sv +++ b/core/pmp/src/pmp_data_if.sv @@ -27,6 +27,7 @@ module pmp_data_if input logic [CVA6Cfg.VLEN-1:0] lsu_vaddr_i, // virtual address in, for tval only input exception_t lsu_exception_i, // lsu exception coming from MMU, or misaligned exception input logic lsu_is_store_i, // the translation is requested by a store + input logic lsu_hlvx_inst_i, output logic lsu_valid_o, // translation is valid output logic [CVA6Cfg.PLEN-1:0] lsu_paddr_o, // translated address output exception_t lsu_exception_o, // address translation threw an exception @@ -36,8 +37,8 @@ module pmp_data_if input riscv::priv_lvl_t ld_st_priv_lvl_i, input logic ld_st_v_i, // PMP - input riscv::pmpcfg_t [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0] pmpcfg_i, - input logic [(CVA6Cfg.NrPMPEntries > 0 ? CVA6Cfg.NrPMPEntries-1 : 0):0][CVA6Cfg.PLEN-3:0] pmpaddr_i + input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0] pmpcfg_i, + input logic [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i ); // virtual address causing the exception logic [CVA6Cfg.XLEN-1:0] fetch_vaddr_xlen, lsu_vaddr_xlen; @@ -78,18 +79,25 @@ module pmp_data_if // if it didn't match any execute region throw an `Instruction Access Fault` (PMA) // or if PMP reject the access - if (!match_any_execute_region || !pmp_if_allow) begin - icache_areq_o.fetch_exception.cause = riscv::INSTR_ACCESS_FAULT; - icache_areq_o.fetch_exception.valid = 1'b1; - // For exception, the virtual address is required for tval, if no MMU is - // instantiated then it will be equal to physical address - if (CVA6Cfg.TvalEn) begin - icache_areq_o.fetch_exception.tval = fetch_vaddr_xlen; - end - if (CVA6Cfg.RVH) begin - icache_areq_o.fetch_exception.tval2 = '0; - icache_areq_o.fetch_exception.tinst = '0; - icache_areq_o.fetch_exception.gva = v_i; + // Per RISCV privilege spec, a page fault has higher priority than access + // fault, therefore do not change the exception type in case of double + // exception + if (icache_areq_i.fetch_valid) begin + if (icache_areq_o.fetch_exception.cause != riscv::INSTR_PAGE_FAULT) begin + if (!match_any_execute_region || !pmp_if_allow) begin + icache_areq_o.fetch_exception.cause = riscv::INSTR_ACCESS_FAULT; + icache_areq_o.fetch_exception.valid = 1'b1; + // For exception, the virtual address is required for tval, if no MMU is + // instantiated then it will be equal to physical address + if (CVA6Cfg.TvalEn) begin + icache_areq_o.fetch_exception.tval = fetch_vaddr_xlen; + end + if (CVA6Cfg.RVH) begin + icache_areq_o.fetch_exception.tval2 = '0; + icache_areq_o.fetch_exception.tinst = '0; + icache_areq_o.fetch_exception.gva = v_i; + end + end end end end @@ -116,10 +124,20 @@ module pmp_data_if lsu_valid_o = lsu_valid_i; lsu_paddr_o = lsu_paddr_i; lsu_exception_o = lsu_exception_i; - pmp_access_type = lsu_is_store_i ? riscv::ACCESS_WRITE : riscv::ACCESS_READ; + if (lsu_is_store_i) begin + pmp_access_type = riscv::ACCESS_WRITE; + end else if (lsu_hlvx_inst_i) begin + pmp_access_type = riscv::pmp_access_t'(riscv::ACCESS_READ | riscv::ACCESS_EXEC); + end else begin + pmp_access_type = riscv::ACCESS_READ; + end // If translation is not enabled, check the paddr immediately against PMPs - if (lsu_valid_i && !data_allow_o) begin + // A misaligned exception has higher priority than an access fault, so don't + // overwrite it (RISC-V privilege spec, simultaneous trap cause priority). + if (lsu_valid_i && !data_allow_o && + !(lsu_exception_i.valid && + (lsu_exception_i.cause inside {riscv::LD_ADDR_MISALIGNED, riscv::ST_ADDR_MISALIGNED}))) begin lsu_exception_o.valid = 1'b1; if (CVA6Cfg.TvalEn) begin diff --git a/core/pmp/src/pmp_entry.sv b/core/pmp/src/pmp_entry.sv index d024a9a09f3..6101e761f2a 100644 --- a/core/pmp/src/pmp_entry.sv +++ b/core/pmp/src/pmp_entry.sv @@ -29,11 +29,16 @@ module pmp_entry #( output logic match_o ); logic [CVA6Cfg.PLEN-1:0] conf_addr_n; + logic [CVA6Cfg.PLEN-3:0] tor_conf_addr; + logic [CVA6Cfg.PLEN-3:0] tor_conf_addr_prev; logic [$clog2(CVA6Cfg.PLEN)-1:0] trail_ones; logic [CVA6Cfg.PLEN-1:0] base; logic [CVA6Cfg.PLEN-1:0] mask; int unsigned size; assign conf_addr_n = {2'b11, ~conf_addr_i}; + // CVA6 implements G=1. Bit 0 does not participate in either TOR boundary. + assign tor_conf_addr = {conf_addr_i[CVA6Cfg.PLEN-3:1], 1'b0}; + assign tor_conf_addr_prev = {conf_addr_prev_i[CVA6Cfg.PLEN-3:1], 1'b0}; lzc #( .WIDTH(CVA6Cfg.PLEN), .MODE (1'b0) @@ -51,15 +56,15 @@ module pmp_entry #( size = '0; // check that the requested address is in between the two // configuration addresses - if (addr_i >= ({2'b0, conf_addr_prev_i} << 2) && addr_i < ({2'b0, conf_addr_i} << 2)) begin + if (addr_i >= ({2'b0, tor_conf_addr_prev} << 2) && addr_i < ({2'b0, tor_conf_addr} << 2)) begin match_o = 1'b1; end else match_o = 1'b0; // synthesis translate_off if (match_o == 0) begin - assert (addr_i >= ({2'b0, conf_addr_i} << 2) || addr_i < ({2'b0, conf_addr_prev_i} << 2)); + assert (addr_i >= ({2'b0, tor_conf_addr} << 2) || addr_i < ({2'b0, tor_conf_addr_prev} << 2)); end else begin - assert (addr_i < ({2'b0, conf_addr_i} << 2) && addr_i >= ({2'b0, conf_addr_prev_i} << 2)); + assert (addr_i < ({2'b0, tor_conf_addr} << 2) && addr_i >= ({2'b0, tor_conf_addr_prev} << 2)); end // synthesis translate_on diff --git a/core/raw_checker.sv b/core/raw_checker.sv new file mode 100644 index 00000000000..01337cad9e3 --- /dev/null +++ b/core/raw_checker.sv @@ -0,0 +1,73 @@ +// Copyright 2024 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 0.51 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Junheng Zheng - Thales + +module raw_checker + import ariane_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +) ( + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Register source of the instruction to check RAW dependencies - SCOREBOARD + input logic [REG_ADDR_SIZE-1:0] rs_i, + // Type of register source (FPR or GPR) - SCOREBOARD + input logic rs_fpr_i, + // Registers of destination of the instructions already issued in the scoreboard - SCOREBOARD + input logic [CVA6Cfg.NR_SB_ENTRIES-1:0][REG_ADDR_SIZE-1:0] rd_i, + // Type of registers of destination (FPR or GPR) - SCOREBOARD + input logic [CVA6Cfg.NR_SB_ENTRIES-1:0] rd_fpr_i, + // Instructions in the scoreboard are still issued - SCOREBOARD + input logic [CVA6Cfg.NR_SB_ENTRIES-1:0] still_issued_i, + // Issue pointer - SCOREBOARD + input logic [CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_i, + + // Index in the scoreboard of the most recent RAW dependency - SCOREBOARD + output logic [CVA6Cfg.TRANS_ID_BITS-1:0] idx_o, + // Indicates if there is a RAW dependency - SCOREBOARD + output logic valid_o +); + + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] same_rd_as_rs; + + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] same_rd_as_rs_before; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] last_before_idx; + + logic [CVA6Cfg.NR_SB_ENTRIES-1:0] same_rd_as_rs_after; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] last_after_idx; + + logic rs_is_gpr0; + + for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + assign same_rd_as_rs[i] = (rs_fpr_i == rd_fpr_i[i]) && (rs_i == rd_i[i]) && still_issued_i[i]; + assign same_rd_as_rs_before[i] = (i < issue_pointer_i) && same_rd_as_rs[i]; + assign same_rd_as_rs_after[i] = (i >= issue_pointer_i) && same_rd_as_rs[i]; + end + + always_comb begin + last_before_idx = '0; + last_after_idx = '0; + + for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin + if (same_rd_as_rs_before[i]) begin + last_before_idx = i; + end + if (same_rd_as_rs_after[i]) begin + last_after_idx = i; + end + end + end + + assign idx_o = |same_rd_as_rs_before ? last_before_idx : last_after_idx; + + assign rs_is_gpr0 = (rs_i == '0) && !rs_fpr_i; + assign valid_o = |same_rd_as_rs && !rs_is_gpr0; + +endmodule diff --git a/core/scoreboard.sv b/core/scoreboard.sv index 6a1b3d094f2..2768d8e3ad3 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -54,7 +54,7 @@ module scoreboard #( input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_i, // Handshake's valid with decode stage - ID_STAGE input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i, - // Handshake's acknowlege with decode stage - ID_STAGE + // Handshake's acknowledge with decode stage - ID_STAGE output logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_o, // instruction to issue logic, if issue_instr_valid and issue_ready is asserted, advance the issue pointer @@ -146,7 +146,7 @@ module scoreboard #( assign issue_pointer[i+1] = issue_pointer[i] + 'd1; end - // an instruction is ready for issue if we have place in the issue FIFO and it the decoder says it is valid + // an instruction is ready for issue if we have place in the issue FIFO and the decoder says it is valid always_comb begin issue_instr_o = decoded_instr_i; orig_instr_o = orig_instr_i; @@ -166,7 +166,7 @@ module scoreboard #( mem_n = mem_q; num_issue = '0; - // if we got a acknowledge from the issue stage, put this scoreboard entry in the queue + // if we got an acknowledge from the issue stage, put this scoreboard entry in the queue for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin if (decoded_instr_valid_i[i] && decoded_instr_ack_o[i] && !flush_unissued_instr_i) begin // the decoded instruction we put in there is valid (1st bit) @@ -216,7 +216,7 @@ module scoreboard #( else mem_n[trans_id_i[i]].sbe.rd = 5'b0; end // write the exception back if it is valid - if (ex_i[i].valid) mem_n[trans_id_i[i]].sbe.ex = ex_i[i]; + if (ex_i[i].valid || ex_i[i].timing) mem_n[trans_id_i[i]].sbe.ex = ex_i[i]; // write the fflags back from the FPU (exception valid is never set), leave tval intact else if(CVA6Cfg.FpPresent && (mem_q[trans_id_i[i]].sbe.fu == ariane_pkg::FPU || mem_q[trans_id_i[i]].sbe.fu == ariane_pkg::FPU_VEC)) begin mem_n[trans_id_i[i]].sbe.ex.cause = ex_i[i].cause; @@ -294,7 +294,7 @@ module scoreboard #( end assign fwd_o.still_issued = still_issued; - assign fwd_o.issue_pointer = issue_pointer; + assign fwd_o.issue_pointer = issue_pointer[0]; assign fwd_o.wb = wb; for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin assign fwd_o.sbe[i] = mem_q[i].sbe; diff --git a/core/store_buffer.sv b/core/store_buffer.sv index 7c22a97fe2f..aad6f8a8bb0 100644 --- a/core/store_buffer.sv +++ b/core/store_buffer.sv @@ -17,9 +17,10 @@ module store_buffer import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type dcache_req_i_t = logic, - parameter type dcache_req_o_t = logic + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type cbo_t = logic ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -45,6 +46,7 @@ module store_buffer input logic [CVA6Cfg.XLEN-1:0] data_i, // data which is placed in the queue input logic [(CVA6Cfg.XLEN/8)-1:0] be_i, // byte enable in input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write) + input cbo_t cbo_op_i, // type of cache block operation // D$ interface input dcache_req_o_t req_port_i, @@ -59,7 +61,9 @@ module store_buffer logic [CVA6Cfg.XLEN-1:0] data; logic [(CVA6Cfg.XLEN/8)-1:0] be; logic [1:0] data_size; + cbo_t cbo_op; logic valid; // this entry is valid, we need this for checking if the address offset matches + logic wait_rvalid; // need to wait for rvalid... } speculative_queue_n[DEPTH_SPEC-1:0], speculative_queue_q[DEPTH_SPEC-1:0], @@ -96,6 +100,8 @@ module store_buffer speculative_queue_n[speculative_write_pointer_q].be = be_i; speculative_queue_n[speculative_write_pointer_q].data_size = data_size_i; speculative_queue_n[speculative_write_pointer_q].valid = 1'b1; + speculative_queue_n[speculative_write_pointer_q].cbo_op = cbo_op_i; + speculative_queue_n[speculative_write_pointer_q].wait_rvalid = 1'b0; // advance the write pointer speculative_write_pointer_n = speculative_write_pointer_q + 1'b1; speculative_status_cnt++; @@ -166,19 +172,40 @@ module store_buffer commit_queue_n = commit_queue_q; req_port_o.data_req = 1'b0; + req_port_o.cbo_op = commit_queue_q[commit_read_pointer_q].cbo_op; // there should be no commit when we are flushing // if the entry in the commit queue is valid and not speculative anymore we can issue this instruction - if (commit_queue_q[commit_read_pointer_q].valid && !stall_st_pending_i) begin + if (commit_queue_q[commit_read_pointer_q].valid && !stall_st_pending_i && !commit_queue_q[commit_read_pointer_q].wait_rvalid) begin req_port_o.data_req = 1'b1; if (req_port_i.data_gnt) begin - // we can evict it from the commit buffer + if (commit_queue_q[commit_read_pointer_q].cbo_op == ariane_pkg::CBO_NONE || req_port_i.data_rvalid) begin + // not CBO or rvalid as well -> we can evict it from the commit buffer + // check for rvalid is technically superfluous, as CBO latency is >= 1 cycle, but check it anyway just to be safe + commit_queue_n[commit_read_pointer_q].valid = 1'b0; + // advance the read_pointer + commit_read_pointer_n = commit_read_pointer_q + 1'b1; + commit_status_cnt--; + end else if (commit_queue_q[commit_read_pointer_q].cbo_op != ariane_pkg::CBO_NONE) begin + // CBO and have gotten data grant -> proceed to wait for rvalid + commit_queue_n[commit_read_pointer_q].wait_rvalid = 1'b1; + end + end + end + + if(commit_queue_q[commit_read_pointer_q].valid && commit_queue_q[commit_read_pointer_q].wait_rvalid) + begin + // wait for rvalid, but no need to raise another request / wait for grant + if (req_port_i.data_rvalid) begin + // CMO did commit + // we can evict the entry from the commit buffer commit_queue_n[commit_read_pointer_q].valid = 1'b0; // advance the read_pointer commit_read_pointer_n = commit_read_pointer_q + 1'b1; commit_status_cnt--; end end + // we ignore the rvalid signal for now as we assume that the store // happened if we got a grant diff --git a/core/store_unit.sv b/core/store_unit.sv index 141763dda78..82193fb756a 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -20,7 +20,8 @@ module store_unit parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, parameter type exception_t = logic, - parameter type lsu_ctrl_t = logic + parameter type lsu_ctrl_t = logic, + parameter type cbo_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -46,6 +47,8 @@ module store_unit output logic commit_ready_o, // TO_BE_COMPLETED - TO_BE_COMPLETED input logic amo_valid_commit_i, + // Data Endian mode - CSR_REGFILE + input logic mbe_i, // Store result is valid - ISSUE_STAGE output logic valid_o, // Transaction ID - ISSUE_STAGE @@ -83,7 +86,10 @@ module store_unit // Data cache request - CACHES input dcache_req_o_t req_port_i, // Data cache response - CACHES - output dcache_req_i_t req_port_o + output dcache_req_i_t req_port_o, + //Trigger module + input logic sdtrig_store_stall_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_store_action_i ); // align data to address e.g.: shift data to be naturally 64 @@ -135,15 +141,16 @@ module store_unit logic [(CVA6Cfg.XLEN/8)-1:0] st_be_n, st_be_q; logic [1:0] st_data_size_n, st_data_size_q; amo_t amo_op_d, amo_op_q; + cbo_t cbo_op_d, cbo_op_q; logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id_n, trans_id_q; // output assignments - assign vaddr_o = lsu_ctrl_i.vaddr; // virtual address + assign vaddr_o = lsu_ctrl_i.vaddr; // virtual address assign hs_ld_st_inst_o = CVA6Cfg.RVH ? lsu_ctrl_i.hs_ld_st_inst : 1'b0; - assign hlvx_inst_o = CVA6Cfg.RVH ? lsu_ctrl_i.hlvx_inst : 1'b0; - assign tinst_o = CVA6Cfg.RVH ? lsu_ctrl_i.tinst : '0; // transformed instruction - assign trans_id_o = trans_id_q; // transaction id from previous cycle + assign hlvx_inst_o = CVA6Cfg.RVH ? lsu_ctrl_i.hlvx_inst : 1'b0; + assign tinst_o = CVA6Cfg.RVH ? lsu_ctrl_i.tinst : '0; // transformed instruction + assign trans_id_o = (sdtrig_store_stall_i && valid_i) ? lsu_ctrl_i.trans_id : trans_id_q; // transaction id from previous cycle always_comb begin : store_control translation_req_o = 1'b0; @@ -155,93 +162,128 @@ module store_unit trans_id_n = lsu_ctrl_i.trans_id; state_d = state_q; - case (state_q) - // we got a valid store - IDLE: begin - if (valid_i) begin - state_d = VALID_STORE; - translation_req_o = 1'b1; - pop_st_o = 1'b1; - // check if translation was valid and we have space in the store buffer - // otherwise simply stall - if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin - state_d = WAIT_TRANSLATION; - pop_st_o = 1'b0; - end + if (sdtrig_store_stall_i && valid_i) begin + //validation of the store architecturally but do not store any result nor commit it + pop_st_o = 1'b0; + valid_o = 1'b1; + st_valid = 1'b0; + translation_req_o = 1'b0; + //generate exception + ex_o.valid = 1'b1; + ex_o.cause = sdtrig_store_action_i; + ex_o.tval = lsu_ctrl_i.vaddr; + + //stall store unit + state_d = IDLE; + end else begin + case (state_q) + // we got a valid store + IDLE: begin + if (valid_i) begin + state_d = VALID_STORE; + translation_req_o = 1'b1; + pop_st_o = 1'b1; + // check if translation was valid and we have space in the store buffer + // otherwise simply stall + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = WAIT_TRANSLATION; + pop_st_o = 1'b0; + end - if (!st_ready) begin - state_d = WAIT_STORE_READY; - pop_st_o = 1'b0; + if (!st_ready) begin + state_d = WAIT_STORE_READY; + pop_st_o = 1'b0; + end end end - end - VALID_STORE: begin - valid_o = 1'b1; - // post this store to the store buffer if we are not flushing - if (!flush_i) st_valid = 1'b1; + VALID_STORE: begin + valid_o = 1'b1; + // post this store to the store buffer if we are not flushing + if (!flush_i && !sdtrig_store_stall_i) st_valid = 1'b1; - st_valid_without_flush = 1'b1; + st_valid_without_flush = 1'b1; - // we have another request and its not an AMO (the AMO buffer only has depth 1) - if ((valid_i && CVA6Cfg.RVA && !instr_is_amo) || (valid_i && !CVA6Cfg.RVA)) begin + // we have another request and its not an AMO (the AMO buffer only has depth 1) + if ((valid_i && CVA6Cfg.RVA && !instr_is_amo) || (valid_i && !CVA6Cfg.RVA)) begin - translation_req_o = 1'b1; - state_d = VALID_STORE; - pop_st_o = 1'b1; + translation_req_o = 1'b1; + state_d = VALID_STORE; + pop_st_o = 1'b1; - if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin - state_d = WAIT_TRANSLATION; - pop_st_o = 1'b0; - end + if (CVA6Cfg.MmuPresent && !dtlb_hit_i) begin + state_d = WAIT_TRANSLATION; + pop_st_o = 1'b0; + end - if (!st_ready) begin - state_d = WAIT_STORE_READY; - pop_st_o = 1'b0; + if (!st_ready) begin + state_d = WAIT_STORE_READY; + pop_st_o = 1'b0; + end + // if we do not have another request go back to idle + end else begin + state_d = IDLE; end - // if we do not have another request go back to idle - end else begin - state_d = IDLE; end - end - // the store queue is currently full - WAIT_STORE_READY: begin - // keep the translation request high - translation_req_o = 1'b1; + // the store queue is currently full + WAIT_STORE_READY: begin + // keep the translation request high + translation_req_o = 1'b1; - if (st_ready && dtlb_hit_i) begin - state_d = IDLE; + if (st_ready && dtlb_hit_i) begin + state_d = IDLE; + end end - end - default: begin - // we didn't receive a valid translation, wait for one - // but we know that the store queue is not full as we could only have landed here if - // it wasn't full - if (state_q == WAIT_TRANSLATION && CVA6Cfg.MmuPresent) begin - translation_req_o = 1'b1; + default: begin + // we didn't receive a valid translation, wait for one + // but we know that the store queue is not full as we could only have landed here if + // it wasn't full + if (state_q == WAIT_TRANSLATION && CVA6Cfg.MmuPresent) begin + translation_req_o = 1'b1; - if (dtlb_hit_i) begin - state_d = IDLE; + if (dtlb_hit_i) begin + state_d = IDLE; + end end end + endcase + + // ----------------- + // Access Exception + // ----------------- + // we got an address translation exception (access rights, misaligned or page fault) + if (ex_i.valid && (state_q != IDLE)) begin + // the only difference is that we do not want to store this request + pop_st_o = 1'b1; + st_valid = 1'b0; + state_d = IDLE; + valid_o = 1'b1; end - endcase - // ----------------- - // Access Exception - // ----------------- - // we got an address translation exception (access rights, misaligned or page fault) - if (ex_i.valid && (state_q != IDLE)) begin - // the only difference is that we do not want to store this request - pop_st_o = 1'b1; - st_valid = 1'b0; - state_d = IDLE; - valid_o = 1'b1; + if (flush_i) state_d = IDLE; end + end + + // ------------- + // Byte-Swapper + // ------------- + // We need to reverse the byte order of what we intend to Store in Data Memory if we are in Big Endian Mode (mbe defines endianness and comes from CSRregfile). + logic [CVA6Cfg.XLEN-1:0] endian_data; - if (flush_i) state_d = IDLE; + always_comb begin + endian_data = lsu_ctrl_i.data; + if (mbe_i) begin + case (lsu_ctrl_i.operation) + SB, HSV_B, FSB: endian_data[7:0] = {lsu_ctrl_i.data[7:0]}; + SH, HSV_H, FSH: endian_data[15:0] = {<<8{lsu_ctrl_i.data[15:0]}}; + SW, HSV_W, FSW, AMO_LRW, AMO_SCW, AMO_SWAPW, AMO_ADDW, AMO_ANDW, AMO_ORW, AMO_XORW, AMO_MAXW, + AMO_MINW, AMO_MAXWU, AMO_MINWU: + endian_data[31:0] = {<<8{lsu_ctrl_i.data[31:0]}}; + default: endian_data[CVA6Cfg.XLEN-1:0] = {<<8{lsu_ctrl_i.data[CVA6Cfg.XLEN-1:0]}}; + endcase + end end // ----------- @@ -251,8 +293,8 @@ module store_unit always_comb begin st_be_n = lsu_ctrl_i.be; // don't shift the data if we are going to perform an AMO as we still need to operate on this data - st_data_n = (CVA6Cfg.RVA && instr_is_amo) ? lsu_ctrl_i.data[CVA6Cfg.XLEN-1:0] : - data_align(lsu_ctrl_i.vaddr[2:0], {{64 - CVA6Cfg.XLEN{1'b0}}, lsu_ctrl_i.data}); + st_data_n = ((CVA6Cfg.RVA && instr_is_amo) ? endian_data[CVA6Cfg.XLEN-1:0] : + data_align(lsu_ctrl_i.vaddr[2:0], {{64 - CVA6Cfg.XLEN{1'b0}}, endian_data})); st_data_size_n = extract_transfer_size(lsu_ctrl_i.operation); // save AMO op for next cycle if (CVA6Cfg.RVA) begin @@ -273,6 +315,17 @@ module store_unit end else begin amo_op_d = AMO_NONE; end + + if (CVA6Cfg.RVZiCbom) begin + case (lsu_ctrl_i.operation) + ariane_pkg::CBO_INVAL: cbo_op_d = ariane_pkg::CBO_INVAL; + ariane_pkg::CBO_CLEAN: cbo_op_d = ariane_pkg::CBO_CLEAN; + ariane_pkg::CBO_FLUSH: cbo_op_d = ariane_pkg::CBO_FLUSH; + default: cbo_op_d = ariane_pkg::CBO_NONE; + endcase + end else begin + cbo_op_d = ariane_pkg::CBO_NONE; + end end logic store_buffer_valid, amo_buffer_valid; @@ -288,9 +341,10 @@ module store_unit // Store Queue // --------------- store_buffer #( - .CVA6Cfg(CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), - .dcache_req_o_t(dcache_req_o_t) + .dcache_req_o_t(dcache_req_o_t), + .cbo_t (cbo_t) ) store_buffer_i ( .clk_i, .rst_ni, @@ -306,13 +360,14 @@ module store_unit .valid_i (store_buffer_valid), // the flush signal can be critical and we need this valid // signal to check whether the page_offset matches or not, - // functionaly it doesn't make a difference whether we use + // functionally it doesn't make a difference whether we use // the correct valid signal or not as we are flushing // the whole pipeline anyway .valid_without_flush_i(st_valid_without_flush), .paddr_i, .rvfi_mem_paddr_o (rvfi_mem_paddr_o), .data_i (st_data_q), + .cbo_op_i (cbo_op_q), .be_i (st_be_q), .data_size_i (st_data_size_q), .req_port_i (req_port_i), @@ -353,6 +408,7 @@ module store_unit st_data_size_q <= '0; trans_id_q <= '0; amo_op_q <= AMO_NONE; + cbo_op_q <= ariane_pkg::CBO_NONE; end else begin state_q <= state_d; st_be_q <= st_be_n; @@ -360,6 +416,7 @@ module store_unit trans_id_q <= trans_id_n; st_data_size_q <= st_data_size_n; amo_op_q <= amo_op_d; + cbo_op_q <= cbo_op_d; end end diff --git a/core/trigger_module.sv b/core/trigger_module.sv new file mode 100644 index 00000000000..1d4ce371b09 --- /dev/null +++ b/core/trigger_module.sv @@ -0,0 +1,1124 @@ +// Copyright 2026 10x Engineers +// Copyright 2026 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Munail Waqar - 10x Engineers +// Contributors : Mounsaf YOUSFI - Thales DIS + +module trigger_module + import ariane_pkg::*; + import triggers_pkg::*; +#( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + input exception_t ex_i, + input riscv::priv_lvl_t priv_lvl_i, + input logic debug_mode_i, + input logic mret_i, + input logic sret_i, + input logic mstatus_mie_i, + input logic mstatus_sie_i, + input logic medeleg_breakpoint_i, + input logic [CVA6Cfg.VLEN-1:0] sdtrig_lsu_inputs_vaddr_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_lsu_inputs_data_i, + input logic sdtrig_lsu_inputs_fu_i, + input fu_op sdtrig_lsu_inputs_op_i, + input logic sdtrig_lsu_inputs_valid_i, + input logic [CVA6Cfg.XLEN-1:0] sdtrig_load_data_i, + input logic sdtrig_load_valid_i, + + input logic [CVA6Cfg.XLEN-1:0] scontext_i, + + input logic [CVA6Cfg.XLEN-1:0] tdata1_i, + input logic [CVA6Cfg.XLEN-1:0] tdata2_i, + input logic [CVA6Cfg.XLEN-1:0] tdata3_i, + input logic [CVA6Cfg.XLEN-1:0] tselect_i, + input logic tselect_we, + input logic tdata1_we, + input logic tdata2_we, + input logic tdata3_we, + + output logic [CVA6Cfg.XLEN-1:0] tselect_o, + output logic [CVA6Cfg.XLEN-1:0] tdata1_o, + output logic [CVA6Cfg.XLEN-1:0] tdata2_o, + output logic [CVA6Cfg.XLEN-1:0] tdata3_o, + output logic flush_o, + + input logic [CVA6Cfg.XLEN-1:0] mepc_i, + input logic [CVA6Cfg.XLEN-1:0] mcause_i, + input logic [CVA6Cfg.XLEN-1:0] mtval_i, + output logic etrigger_context_saved_valid_o, + output logic [CVA6Cfg.XLEN-1:0] etrigger_context_mepc_o, + output logic [CVA6Cfg.XLEN-1:0] etrigger_context_mcause_o, + output logic [CVA6Cfg.XLEN-1:0] etrigger_context_mtval_o, + + input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] fetch_sdtrig_pc_i, + input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] fetch_sdtrig_instr_i, + output logic [CVA6Cfg.XLEN-1:0] sdtrig_decoder_action_o[CVA6Cfg.NrIssuePorts], + + output logic sdtrig_load_stall_o, + output logic sdtrig_load_cancel_o, + output logic [CVA6Cfg.XLEN-1:0] sdtrig_load_action_o, + output logic sdtrig_store_stall_o, + output logic [CVA6Cfg.XLEN-1:0] sdtrig_store_action_o, + + output logic sdtrig_commit_std_exception_valid_o, + output logic sdtrig_commit_icount_valid_o, + output logic [CVA6Cfg.XLEN-1:0] sdtrig_commit_action_o, + output logic [$clog2(CVA6Cfg.NrCommitPorts)-1:0] sdtrig_commit_icount_nr_instr_o +); + + function automatic logic std_match(input logic [CVA6Cfg.XLEN-1:0] tdata2_ref, + input logic [CVA6Cfg.XLEN-1:0] comp_val, + input logic [3:0] match_type); + logic match = 0; + + unique case (match_type) + 4'd0: + if (CVA6Cfg.SdtrigSupportedMatch[0]) // equal + match = (tdata2_ref == comp_val); + + 4'd1: + if (CVA6Cfg.SdtrigSupportedMatch[1]) begin //napot + if (CVA6Cfg.IS_XLEN32) match = (napot_match32(tdata2_ref, comp_val)); + else if (CVA6Cfg.IS_XLEN64) match = (napot_match64(tdata2_ref, comp_val)); + end + + 4'd2: + if (CVA6Cfg.SdtrigSupportedMatch[2]) //greater or equal than + match = (tdata2_ref[CVA6Cfg.XLEN-1:0] >= comp_val); + + 4'd3: + if (CVA6Cfg.SdtrigSupportedMatch[3]) //lower than + match = (tdata2_ref[CVA6Cfg.XLEN-1:0] < comp_val); + + 4'd4: + if (CVA6Cfg.SdtrigSupportedMatch[4]) //mask low + match = ((tdata2_ref[CVA6Cfg.XLEN-1:(CVA6Cfg.XLEN)/2] & comp_val[(CVA6Cfg.XLEN)/2-1:0]) == tdata2_ref[(CVA6Cfg.XLEN)/2-1:0]); + + 4'd5: + if (CVA6Cfg.SdtrigSupportedMatch[5]) //mask high + match = ((tdata2_ref[CVA6Cfg.XLEN-1:(CVA6Cfg.XLEN)/2] & comp_val[CVA6Cfg.XLEN-1:(CVA6Cfg.XLEN)/2]) == tdata2_ref[(CVA6Cfg.XLEN)/2-1:0]); + + 4'd8: + if (CVA6Cfg.SdtrigSupportedMatch[6]) //not equal + match = (tdata2_ref[CVA6Cfg.XLEN-1:0] != comp_val); + + 4'd9: + if (CVA6Cfg.SdtrigSupportedMatch[7]) begin //not napot + if (CVA6Cfg.IS_XLEN32) match = !(napot_match32(tdata2_ref, comp_val)); + else if (CVA6Cfg.IS_XLEN64) match = !(napot_match64(tdata2_ref, comp_val)); + end + + 4'd12: + if (CVA6Cfg.SdtrigSupportedMatch[8]) //not mask low + match = !((tdata2_ref[CVA6Cfg.XLEN-1:(CVA6Cfg.XLEN)/2] & comp_val[(CVA6Cfg.XLEN)/2-1:0]) == tdata2_ref[(CVA6Cfg.XLEN)/2-1:0]); + + 4'd13: + if (CVA6Cfg.SdtrigSupportedMatch[9]) //not mask high + match = !((tdata2_ref[CVA6Cfg.XLEN-1:(CVA6Cfg.XLEN)/2] & comp_val[CVA6Cfg.XLEN-1:(CVA6Cfg.XLEN)/2]) == tdata2_ref[(CVA6Cfg.XLEN)/2-1:0]); + + default: match = '0; + endcase + + return match; + endfunction + + // tdata1 is WARL. action=1 (enter Debug Mode) is legal only with dmode=1. + // The actions that are not supported become 0 (breakpoint exception). + function automatic logic [5:0] legal_action(input logic [5:0] action, input logic dmode); + return (CVA6Cfg.SdtrigSupportedActions[1] && dmode && action == 6'd1) ? 6'd1 : 6'd0; + endfunction + + // Bit "code" of tdata2 selects the trap with this code. The codes from XLEN up are not selected. + function automatic logic cause_selected(input logic [CVA6Cfg.XLEN-1:0] tdata2, + input logic [CVA6Cfg.XLEN-1:0] cause); + return (cause[CVA6Cfg.XLEN-2:$clog2(CVA6Cfg.XLEN)] == '0) && + tdata2[cause[$clog2(CVA6Cfg.XLEN)-1:0]]; + endfunction + + typedef struct packed { + logic valid; + logic [CVA6Cfg.XLEN-1:0] action; + } fire_req_t; + + // Trigger Module Helpers + logic + trigger_chain_vector_d[CVA6Cfg.SdtrigNrTriggers], + trigger_chain_vector_q[CVA6Cfg.SdtrigNrTriggers]; + logic matchEA, matchED, matchSX, matchLA, matchLD; + //EA = Match Control 6 Exec Address; ED = MC6 Exec Data; SX = MC6 Store (both addr. and data);... + fire_req_t + fire_req_EA[CVA6Cfg.NrIssuePorts], + fire_req_ED[CVA6Cfg.NrIssuePorts], + fire_req_SX, + fire_req_LA, + fire_req_LD, + fire_req_Icount, + fire_req_Etrigger, + fire_req_Itrigger; + logic [$clog2(CVA6Cfg.SdtrigNrTriggers)-1:0] previous_trigg_i; + logic sdtrig_commit_icount_valid_d; + logic [CVA6Cfg.XLEN-1:0] sdtrig_commit_action_d; + logic [CVA6Cfg.XLEN-1:0] sdtrig_load_action_d, sdtrig_load_action_q; + logic [$clog2(CVA6Cfg.NrCommitPorts)-1:0] sdtrig_commit_icount_nr_instr_d; + logic [CVA6Cfg.SdtrigNrTriggers-1:0] e_matched_q, e_matched_d; + logic + sdtrig_commit_std_exception_valid_q, + sdtrig_commit_std_exception_valid_d, + sdtrig_load_stall_s, + sdtrig_load_cancel_d, + sdtrig_load_cancel_q; + logic etrigger_context_saved_valid_q, etrigger_context_saved_valid_d; + logic [CVA6Cfg.XLEN-1:0] etrigger_context_mepc_q, etrigger_context_mepc_d; + logic [CVA6Cfg.XLEN-1:0] etrigger_context_mcause_q, etrigger_context_mcause_d; + logic [CVA6Cfg.XLEN-1:0] etrigger_context_mtval_q, etrigger_context_mtval_d; + + logic [$clog2(CVA6Cfg.SdtrigNrTriggers)-1:0] tselect_q, tselect_d; + logic [3:0] trigger_type_q[CVA6Cfg.SdtrigNrTriggers], trigger_type_d[CVA6Cfg.SdtrigNrTriggers]; + logic [CVA6Cfg.SdtrigNrTriggers-1:0] priv_match, scontext_match; + logic [CVA6Cfg.XLEN-1:0] tdata2_q[CVA6Cfg.SdtrigNrTriggers], tdata2_d[CVA6Cfg.SdtrigNrTriggers]; + trigger_32_tdata1_type + trigger_32_tdata1_q[CVA6Cfg.SdtrigNrTriggers], trigger_32_tdata1_d[CVA6Cfg.SdtrigNrTriggers]; + textra32_tdata3_t + textra32_tdata3_q[CVA6Cfg.SdtrigNrTriggers], textra32_tdata3_d[CVA6Cfg.SdtrigNrTriggers]; + textra64_tdata3_t + textra64_tdata3_q[CVA6Cfg.SdtrigNrTriggers], textra64_tdata3_d[CVA6Cfg.SdtrigNrTriggers]; + + for (genvar i = 0; i < CVA6Cfg.SdtrigNrTriggers; i++) begin + if (!CVA6Cfg.SdtrigSupportTextra) begin + assign textra32_tdata3_d[i] = '0; + assign textra64_tdata3_d[i] = '0; + assign textra32_tdata3_q[i] = '0; + assign textra64_tdata3_q[i] = '0; + end + end + + logic [CVA6Cfg.NrIssuePorts-1:0] fire_req_EA_valid, fire_req_ED_valid; + logic [CVA6Cfg.XLEN-1:0] + fire_req_EA_action[CVA6Cfg.NrIssuePorts], fire_req_ED_action[CVA6Cfg.NrIssuePorts]; + + for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + assign fire_req_EA_valid[i] = fire_req_EA[i].valid; + assign fire_req_ED_valid[i] = fire_req_ED[i].valid; + assign fire_req_EA_action[i] = fire_req_EA[i].action; + assign fire_req_ED_action[i] = fire_req_ED[i].action; + end + + // A trap is taken. A Debug Mode entry is not a trap. An exception in Debug Mode is not a trap. + logic trap_taken; + assign trap_taken = ex_i.valid && !debug_mode_i && !(ex_i.cause inside {riscv::DEBUG_REQUEST, riscv::DEBUG_TRIGGER}); + + // A trigger with action=0 does not match or fire in M-mode while MIE=0, and in S-mode while + // SIE=0 when the breakpoint exceptions go to S-mode (first solution of Native Triggers) + logic native_allowed; + assign native_allowed = !(priv_lvl_i == riscv::PRIV_LVL_M && !mstatus_mie_i) && + !(priv_lvl_i == riscv::PRIV_LVL_S && medeleg_breakpoint_i && !mstatus_sie_i); + + // lr is a load and sc is a store. An AMO is a load and a store. The store unit executes the + // three of them (sdtrig_lsu_inputs_fu_i=1). + logic lsu_load_access, lsu_store_access; + assign lsu_store_access = sdtrig_lsu_inputs_fu_i && !(sdtrig_lsu_inputs_op_i inside {AMO_LRW, AMO_LRD}); + assign lsu_load_access = !sdtrig_lsu_inputs_fu_i || (is_amo( + sdtrig_lsu_inputs_op_i + ) && !(sdtrig_lsu_inputs_op_i inside {AMO_SCW, AMO_SCD})); + + // icount matches on each instruction that retires, or on the trap that is taken + logic [$clog2(CVA6Cfg.NrCommitPorts+1)-1:0] icount_events; + always_comb begin : icount_match_events + icount_events = '0; + if (trap_taken) icount_events = 1; + else if (!ex_i.valid && !debug_mode_i) + for (int p = 0; p < CVA6Cfg.NrCommitPorts; p++) icount_events += commit_ack_i[p]; + end + + // Trigger CSRs write/update logic + always_comb begin : write_path + // defaults + if (CVA6Cfg.SdtrigSupportTextra && CVA6Cfg.IS_XLEN32) textra32_tdata3_d = textra32_tdata3_q; + if (CVA6Cfg.SdtrigSupportTextra && CVA6Cfg.IS_XLEN64) textra64_tdata3_d = textra64_tdata3_q; + + trigger_type_d = trigger_type_q; + trigger_32_tdata1_d = trigger_32_tdata1_q; + tdata2_d = tdata2_q; + tselect_d = tselect_q; + matchEA = 1'b0; + matchED = 1'b0; + matchSX = 1'b0; + matchLA = 1'b0; + matchLD = 1'b0; + sdtrig_load_cancel_d = 1'b0; + sdtrig_load_stall_o = (ex_i.valid) ? 1'b0 : sdtrig_load_stall_s; + sdtrig_store_stall_o = 1'b0; + sdtrig_commit_icount_valid_d = 1'b0; + sdtrig_commit_icount_nr_instr_d = '0; + sdtrig_commit_action_d = '0; + sdtrig_commit_std_exception_valid_d = 1'b0; + sdtrig_load_action_d = sdtrig_load_action_q; + sdtrig_load_action_o = sdtrig_load_cancel_q ? sdtrig_load_action_q : '0; + sdtrig_store_action_o = '0; + flush_o = 1'b0; + + //Break from mcontrol6 from execution is a comb. only signal that + //informs decode stage that the currently decoded PC/instr must generate + //a breakpoint exception or a debug request + for (int i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin + sdtrig_decoder_action_o[i] = '0; + fire_req_EA[i].valid = 1'b0; + fire_req_EA[i].action = '0; + fire_req_ED[i].valid = 1'b0; + fire_req_ED[i].action = '0; + end + + if (ex_i.valid || !CVA6Cfg.SdtrigTriggerChaining) begin + for (int i = 0; i < CVA6Cfg.SdtrigNrTriggers; i++) trigger_chain_vector_d[i] = 1'b0; + end else if (CVA6Cfg.SdtrigTriggerChaining) trigger_chain_vector_d = trigger_chain_vector_q; + + previous_trigg_i = '0; + + //Trigger fire requests reset + fire_req_SX.valid = 1'b0; + fire_req_SX.action = '0; + fire_req_LA.valid = 1'b0; + fire_req_LA.action = '0; + fire_req_LD.valid = 1'b0; + fire_req_LD.action = '0; + fire_req_Icount.valid = 1'b0; + fire_req_Icount.action = '0; + fire_req_Etrigger.valid = 1'b0; + fire_req_Etrigger.action = '0; + fire_req_Itrigger.valid = 1'b0; + fire_req_Itrigger.action = '0; + + etrigger_context_saved_valid_d = (mret_i) ? 1'b0 : etrigger_context_saved_valid_q; + etrigger_context_mepc_d = etrigger_context_mepc_q; + etrigger_context_mcause_d = etrigger_context_mcause_q; + etrigger_context_mtval_d = etrigger_context_mtval_q; + + e_matched_d = e_matched_q; + + if (CVA6Cfg.Sdtrig) begin + // Triggers Match Logic + for (int i = 0; i < CVA6Cfg.SdtrigNrTriggers; i++) begin + matchEA = 1'b0; + matchED = 1'b0; + matchSX = 1'b0; + matchLD = 1'b0; + matchLA = 1'b0; + + if (CVA6Cfg.SdtrigTriggerChaining) + previous_trigg_i = CVA6Cfg.SdtrigNrTriggers'((i - 1 + CVA6Cfg.SdtrigNrTriggers) % CVA6Cfg.SdtrigNrTriggers); + priv_match[i] = 1'b0; + // icount match logic + if (trigger_type_d[i] == 4'd3 && CVA6Cfg.SdtrigIcount) begin + case(priv_lvl_i) // trigger will only fire if current priv lvl is same as the trigger configuration + riscv::PRIV_LVL_M: if (trigger_32_tdata1_d[i].icount_type.m) priv_match[i] = 1'b1; + riscv::PRIV_LVL_S: if (trigger_32_tdata1_d[i].icount_type.s) priv_match[i] = 1'b1; + riscv::PRIV_LVL_U: if (trigger_32_tdata1_d[i].icount_type.u) priv_match[i] = 1'b1; + default: priv_match[i] = 1'b0; + endcase + // Context match check (textra), in all modes + if (CVA6Cfg.SdtrigSupportTextra) begin + if (CVA6Cfg.IS_XLEN32) begin + scontext_match[i] = match_scontext32( + scontext_i, + textra32_tdata3_d[i].sselect, + textra32_tdata3_d[i].sbytemask, + textra32_tdata3_d[i].svalue, + 1'b0 + ); + end else begin + scontext_match[i] = match_scontext64( + scontext_i, + textra64_tdata3_d[i].sselect, + textra64_tdata3_d[i].sbytemask, + textra64_tdata3_d[i].svalue, + 1'b1 + ); + end + priv_match[i] &= scontext_match[i]; + end + if (trigger_32_tdata1_d[i].icount_type.action == '0 && !native_allowed) + priv_match[i] = 1'b0; + // A match in a mode where the trigger is enabled decrements count. + // pending becomes set when count goes to 0. A write of count=0 does not set it. + if (priv_match[i] && icount_events != 0 && trigger_32_tdata1_q[i].icount_type.count != 0) begin + if (trigger_32_tdata1_q[i].icount_type.count > 14'(icount_events)) begin + trigger_32_tdata1_d[i].icount_type.count = trigger_32_tdata1_q[i].icount_type.count - 14'(icount_events); + end else begin + trigger_32_tdata1_d[i].icount_type.count = '0; + trigger_32_tdata1_d[i].icount_type.pending = 1'b1; + end + end + // The commit stage takes the trigger action on the next instruction to execute + // in an enabled mode (count=0), or retires one instruction at a time (count=1). + if (priv_match[i] && !debug_mode_i) begin + if (trigger_32_tdata1_d[i].icount_type.pending || + trigger_32_tdata1_d[i].icount_type.count != 0 && trigger_32_tdata1_d[i].icount_type.count < CVA6Cfg.NrCommitPorts) begin + fire_req_Icount.valid = 1'b1; + sdtrig_commit_icount_nr_instr_d = trigger_32_tdata1_d[i].icount_type.pending ? '0 : + $bits(sdtrig_commit_icount_nr_instr_d)'(trigger_32_tdata1_d[i].icount_type.count); + unique case (trigger_32_tdata1_d[i].icount_type.action) + 6'd0: + if (CVA6Cfg.SdtrigSupportedActions[0]) fire_req_Icount.action = riscv::BREAKPOINT; + 6'd1: + if (CVA6Cfg.SdtrigSupportedActions[1]) + fire_req_Icount.action = riscv::DEBUG_TRIGGER; + default: ; + endcase + end + end + // The trigger fires when the commit stage takes its action. pending is cleared. + if (trigger_32_tdata1_q[i].icount_type.pending && ex_i.valid && sdtrig_commit_icount_valid_o + && sdtrig_commit_icount_nr_instr_o == '0) begin + trigger_32_tdata1_d[i].icount_type.hit = 1'b1; + trigger_32_tdata1_d[i].icount_type.pending = 1'b0; + fire_req_Icount.valid = 1'b0; + fire_req_Icount.action = '0; + end + end + // mcontrol6 match logic + if (trigger_type_d[i] == 4'd6 && CVA6Cfg.SdtrigMcontrol6) begin + case(priv_lvl_i) // trigger will only fire if current priv lvl is same as the trigger configuration + riscv::PRIV_LVL_M: if (trigger_32_tdata1_d[i].mc6_type.m) priv_match[i] = 1'b1; + riscv::PRIV_LVL_S: if (trigger_32_tdata1_d[i].mc6_type.s) priv_match[i] = 1'b1; + riscv::PRIV_LVL_U: if (trigger_32_tdata1_d[i].mc6_type.u) priv_match[i] = 1'b1; + default: priv_match[i] = 1'b0; + endcase + // Context match check (textra), in all modes + if (CVA6Cfg.SdtrigSupportTextra) begin + if (CVA6Cfg.IS_XLEN32) begin + scontext_match[i] = match_scontext32( + scontext_i, + textra32_tdata3_d[i].sselect, + textra32_tdata3_d[i].sbytemask, + textra32_tdata3_d[i].svalue, + 1'b0 + ); + end else if (CVA6Cfg.IS_XLEN64) begin + scontext_match[i] = match_scontext64( + scontext_i, + textra64_tdata3_d[i].sselect, + textra64_tdata3_d[i].sbytemask, + textra64_tdata3_d[i].svalue, + 1'b1 + ); + end + priv_match[i] &= scontext_match[i]; + end + if (trigger_32_tdata1_d[i].mc6_type.action == '0 && !native_allowed) priv_match[i] = 1'b0; + + //Execute triggers + if ((CVA6Cfg.SdtrigMcontrol6ExecAddr || CVA6Cfg.SdtrigMcontrol6ExecData) && trigger_32_tdata1_d[i].mc6_type.execute) begin + for (int n = 0; n < CVA6Cfg.NrIssuePorts; n++) begin + //Execute trigger on address + if (CVA6Cfg.SdtrigMcontrol6ExecAddr) begin + if (!trigger_32_tdata1_d[i].mc6_type.select) begin + matchEA = std_match( + { + {{CVA6Cfg.XLEN - CVA6Cfg.VLEN} {1'b0}}, tdata2_d[i][CVA6Cfg.VLEN-1:0] + }, + { + {{CVA6Cfg.XLEN - CVA6Cfg.VLEN} {1'b0}}, fetch_sdtrig_pc_i[n] + }, + trigger_32_tdata1_d[i].mc6_type.match + ); + end + end + //Execute trigger on data + if (CVA6Cfg.SdtrigMcontrol6ExecData) begin + if (trigger_32_tdata1_d[i].mc6_type.select) begin + matchED = std_match(tdata2_d[i], fetch_sdtrig_instr_i[n], + trigger_32_tdata1_d[i].mc6_type.match); + end + end + //Request fire + if (priv_match[i] && (CVA6Cfg.SdtrigMcontrol6ExecAddr && matchEA || CVA6Cfg.SdtrigMcontrol6ExecData && matchED)) begin + trigger_32_tdata1_d[i].mc6_type.hit0 = 1'b1; //before + trigger_32_tdata1_d[i].mc6_type.hit1 = 1'b0; + if (CVA6Cfg.SdtrigTriggerChaining) begin + if(!trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && trigger_32_tdata1_d[i].mc6_type.chain || trigger_chain_vector_d[previous_trigg_i] && trigger_32_tdata1_d[i].mc6_type.chain) + trigger_chain_vector_d[i] = 1'b1; + if(trigger_chain_vector_d[previous_trigg_i] && !trigger_32_tdata1_d[i].mc6_type.chain || !trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && !trigger_32_tdata1_d[i].mc6_type.chain) begin + if (matchEA && CVA6Cfg.SdtrigMcontrol6ExecAddr) begin + fire_req_EA[n].valid = 1'b1; + + if(CVA6Cfg.SdtrigSupportedActions[0] && trigger_32_tdata1_d[i].mc6_type.action == 4'd0) begin + fire_req_EA[n].action = riscv::BREAKPOINT; + end + else if (CVA6Cfg.SdtrigSupportedActions[1] && trigger_32_tdata1_d[i].mc6_type.action == 4'd1) begin + if (CVA6Cfg.DebugEn && !debug_mode_i) begin + fire_req_EA[n].action = riscv::DEBUG_TRIGGER; + end + end + end + end else begin + fire_req_EA[n].valid = 1'b1; + if(CVA6Cfg.SdtrigSupportedActions[0] && trigger_32_tdata1_d[i].mc6_type.action == 4'd0) begin + fire_req_EA[n].action = riscv::BREAKPOINT; + end + else if (CVA6Cfg.SdtrigSupportedActions[1] && trigger_32_tdata1_d[i].mc6_type.action == 4'd1) begin + if (CVA6Cfg.DebugEn && !debug_mode_i) begin + fire_req_EA[n].action = riscv::DEBUG_TRIGGER; + end + end + end + end else if (matchEA) begin + fire_req_EA[n].valid = 1'b1; + if(CVA6Cfg.SdtrigSupportedActions[0] && trigger_32_tdata1_d[i].mc6_type.action == 4'd0) begin + fire_req_EA[n].action = riscv::BREAKPOINT; + end + else if (CVA6Cfg.SdtrigSupportedActions[1] && trigger_32_tdata1_d[i].mc6_type.action == 4'd1) begin + if (CVA6Cfg.DebugEn && !debug_mode_i) begin + fire_req_EA[n].action = riscv::DEBUG_TRIGGER; + end + end + end + end + if (priv_match[i] && CVA6Cfg.SdtrigMcontrol6ExecData && matchED) begin + trigger_32_tdata1_d[i].mc6_type.hit0 = 1'b1; //before + trigger_32_tdata1_d[i].mc6_type.hit1 = 1'b0; + if (CVA6Cfg.SdtrigTriggerChaining) begin + if(!trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && trigger_32_tdata1_d[i].mc6_type.chain || trigger_chain_vector_d[previous_trigg_i] && trigger_32_tdata1_d[i].mc6_type.chain) + trigger_chain_vector_d[i] = 1'b1; + if(trigger_chain_vector_d[previous_trigg_i] && !trigger_32_tdata1_d[i].mc6_type.chain || !trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && !trigger_32_tdata1_d[i].mc6_type.chain) begin + fire_req_ED[n].valid = 1'b1; + if(CVA6Cfg.SdtrigSupportedActions[0] && trigger_32_tdata1_d[i].mc6_type.action == 4'd0) begin + fire_req_ED[n].action = riscv::BREAKPOINT; + end + else if (CVA6Cfg.SdtrigSupportedActions[1] && trigger_32_tdata1_d[i].mc6_type.action == 4'd1) begin + if (CVA6Cfg.DebugEn && !debug_mode_i) begin + fire_req_ED[n].action = riscv::DEBUG_TRIGGER; + end + end + end + end else begin + fire_req_ED[n].valid = 1'b1; + if(CVA6Cfg.SdtrigSupportedActions[0] && trigger_32_tdata1_d[i].mc6_type.action == 4'd0) begin + fire_req_ED[n].action = riscv::BREAKPOINT; + end + else if (CVA6Cfg.SdtrigSupportedActions[1] && trigger_32_tdata1_d[i].mc6_type.action == 4'd1) begin + if (CVA6Cfg.DebugEn && !debug_mode_i) begin + fire_req_ED[n].action = riscv::DEBUG_TRIGGER; + end + end + end + end + end + end + + //Store triggers + if (CVA6Cfg.SdtrigMcontrol6Store && trigger_32_tdata1_d[i].mc6_type.store) begin + //Store trigger on data + if (CVA6Cfg.SdtrigMcontrol6Store) begin + if (trigger_32_tdata1_d[i].mc6_type.select) begin + if (sdtrig_lsu_inputs_valid_i && lsu_store_access) begin + matchSX = std_match(tdata2_d[i], sdtrig_lsu_inputs_data_i, + trigger_32_tdata1_d[i].mc6_type.match); + end + end + if (!trigger_32_tdata1_d[i].mc6_type.select) begin + if (sdtrig_lsu_inputs_valid_i && lsu_store_access) begin + matchSX = std_match(tdata2_d[i], sdtrig_lsu_inputs_vaddr_i, + trigger_32_tdata1_d[i].mc6_type.match); + end + end + end + //Request fire + if (priv_match[i] && matchSX) begin + trigger_32_tdata1_d[i].mc6_type.hit0 = 1'b1; //before + trigger_32_tdata1_d[i].mc6_type.hit1 = 1'b0; + if (CVA6Cfg.SdtrigTriggerChaining) begin + if(!trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && trigger_32_tdata1_d[i].mc6_type.chain || trigger_chain_vector_d[previous_trigg_i] && trigger_32_tdata1_d[i].mc6_type.chain) + trigger_chain_vector_d[i] = 1'b1; + if(trigger_chain_vector_d[previous_trigg_i] && !trigger_32_tdata1_d[i].mc6_type.chain || !trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && !trigger_32_tdata1_d[i].mc6_type.chain) begin + if (matchSX && CVA6Cfg.SdtrigMcontrol6Store) fire_req_SX.valid = 1'b1; + unique case (trigger_32_tdata1_d[i].mc6_type.action) + 4'd0: + if (CVA6Cfg.SdtrigSupportedActions[0] == 1'b1) begin + if (matchSX && CVA6Cfg.SdtrigMcontrol6Store) + fire_req_SX.action = riscv::BREAKPOINT; + end + 4'd1: + if (CVA6Cfg.SdtrigSupportedActions[1] == 1'b1) + if (CVA6Cfg.DebugEn && !debug_mode_i) begin + if (matchSX && CVA6Cfg.SdtrigMcontrol6Store) + fire_req_SX.action = riscv::DEBUG_TRIGGER; + end + default: ; + endcase + end + end else begin + if (matchSX && CVA6Cfg.SdtrigMcontrol6Store) fire_req_SX.valid = 1'b1; + unique case (trigger_32_tdata1_d[i].mc6_type.action) + 4'd0: + if (CVA6Cfg.SdtrigSupportedActions[0] == 1'b1) begin + if (matchSX && CVA6Cfg.SdtrigMcontrol6Store) + fire_req_SX.action = riscv::BREAKPOINT; + end + 4'd1: + if (CVA6Cfg.SdtrigSupportedActions[1] == 1'b1) + if (CVA6Cfg.DebugEn && !debug_mode_i) begin + if (matchSX && CVA6Cfg.SdtrigMcontrol6Store) + fire_req_SX.action = riscv::DEBUG_TRIGGER; + end + default: ; + endcase + end + end + end + + //Load triggers + if ((CVA6Cfg.SdtrigMcontrol6LoadAddr || CVA6Cfg.SdtrigMcontrol6LoadData) && trigger_32_tdata1_d[i].mc6_type.load) begin + //Load trigger on data + if (CVA6Cfg.SdtrigMcontrol6LoadData) begin + if (trigger_32_tdata1_d[i].mc6_type.select) begin + matchLD = std_match(tdata2_d[i], sdtrig_load_data_i, + trigger_32_tdata1_d[i].mc6_type.match); + //If the load unit result is the data to trigger on, stall load unit so it doesn't make any mem. access + //but do not generate any exception yet as we want this load's data to be saved + if (priv_match[i] && matchLD) begin + trigger_32_tdata1_d[i].mc6_type.hit0 = 1'b1; + trigger_32_tdata1_d[i].mc6_type.hit1 = 1'b1; //immediately after + if (CVA6Cfg.SdtrigTriggerChaining) begin + if(!trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && trigger_32_tdata1_d[i].mc6_type.chain || trigger_chain_vector_d[previous_trigg_i] && trigger_32_tdata1_d[i].mc6_type.chain) + trigger_chain_vector_d[i] = 1'b1; + if(trigger_chain_vector_d[previous_trigg_i] && !trigger_32_tdata1_d[i].mc6_type.chain || !trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && !trigger_32_tdata1_d[i].mc6_type.chain) begin + fire_req_LD.valid = 1'b1; + unique case (trigger_32_tdata1_d[i].mc6_type.action) + 4'd0: + if (CVA6Cfg.SdtrigSupportedActions[0] == 1'b1) + fire_req_LD.action = riscv::BREAKPOINT; + 4'd1: + if (CVA6Cfg.SdtrigSupportedActions[1] == 1'b1 && CVA6Cfg.DebugEn && !debug_mode_i) + fire_req_LD.action = riscv::DEBUG_TRIGGER; + default: ; + endcase + end + end else begin + fire_req_LD.valid = 1'b1; + unique case (trigger_32_tdata1_d[i].mc6_type.action) + 4'd0: + if (CVA6Cfg.SdtrigSupportedActions[0] == 1'b1) + fire_req_LD.action = riscv::BREAKPOINT; + 4'd1: + if (CVA6Cfg.SdtrigSupportedActions[1] == 1'b1 && CVA6Cfg.DebugEn && !debug_mode_i) + fire_req_LD.action = riscv::DEBUG_TRIGGER; + default: ; + endcase + end + end + end + end + //Load trigger on address + if (CVA6Cfg.SdtrigMcontrol6LoadAddr) begin + if (!trigger_32_tdata1_d[i].mc6_type.select) begin + if (sdtrig_lsu_inputs_valid_i && lsu_load_access) begin + matchLA = std_match(tdata2_d[i], sdtrig_lsu_inputs_vaddr_i, + trigger_32_tdata1_d[i].mc6_type.match); + end + //Load trigger on address fire logic + if (priv_match[i] && matchLA) begin + trigger_32_tdata1_d[i].mc6_type.hit0 = 1'b1; //before + trigger_32_tdata1_d[i].mc6_type.hit1 = 1'b0; + if (CVA6Cfg.SdtrigTriggerChaining) begin + if(!trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && trigger_32_tdata1_d[i].mc6_type.chain || trigger_chain_vector_d[previous_trigg_i] && trigger_32_tdata1_d[i].mc6_type.chain) + trigger_chain_vector_d[i] = 1'b1; + if(trigger_chain_vector_d[previous_trigg_i] && !trigger_32_tdata1_d[i].mc6_type.chain || !trigger_32_tdata1_d[previous_trigg_i].mc6_type.chain && !trigger_32_tdata1_d[i].mc6_type.chain) begin + fire_req_LA.valid = 1'b1; + unique case (trigger_32_tdata1_d[i].mc6_type.action) + 4'd0: + if (CVA6Cfg.SdtrigSupportedActions[0] == 1'b1) + fire_req_LA.action = riscv::BREAKPOINT; + 4'd1: + if (CVA6Cfg.SdtrigSupportedActions[1] == 1'b1 && CVA6Cfg.DebugEn && !debug_mode_i) + fire_req_LA.action = riscv::DEBUG_TRIGGER; + default: ; + endcase + end + end else begin + fire_req_LA.valid = 1'b1; + unique case (trigger_32_tdata1_d[i].mc6_type.action) + 4'd0: + if (CVA6Cfg.SdtrigSupportedActions[0] == 1'b1) + fire_req_LA.action = riscv::BREAKPOINT; + 4'd1: + if (CVA6Cfg.SdtrigSupportedActions[1] == 1'b1 && CVA6Cfg.DebugEn && !debug_mode_i) + fire_req_LA.action = riscv::DEBUG_TRIGGER; + default: ; + endcase + end + end + end + end + end + end + // etrigger match logic + if (trigger_type_d[i] == 4'd5 && CVA6Cfg.SdtrigEtrigger) begin + case(priv_lvl_i) // trigger will only fire if current priv lvl is same as the trigger configuration + riscv::PRIV_LVL_M: if (trigger_32_tdata1_d[i].etrigger_type.m) priv_match[i] = 1'b1; + riscv::PRIV_LVL_S: if (trigger_32_tdata1_d[i].etrigger_type.s) priv_match[i] = 1'b1; + riscv::PRIV_LVL_U: if (trigger_32_tdata1_d[i].etrigger_type.u) priv_match[i] = 1'b1; + default: priv_match[i] = 1'b0; + endcase + // Context match check (textra), in all modes + if (CVA6Cfg.SdtrigSupportTextra) begin + if (CVA6Cfg.IS_XLEN32) begin + scontext_match[i] = match_scontext32( + scontext_i, + textra32_tdata3_d[i].sselect, + textra32_tdata3_d[i].sbytemask, + textra32_tdata3_d[i].svalue, + 1'b0 + ); + end else begin + scontext_match[i] = match_scontext64( + scontext_i, + textra64_tdata3_d[i].sselect, + textra64_tdata3_d[i].sbytemask, + textra64_tdata3_d[i].svalue, + 1'b1 + ); + end + priv_match[i] &= scontext_match[i]; + end + // Only an exception matches, not an interrupt + if (trap_taken && !ex_i.cause[CVA6Cfg.XLEN-1] && cause_selected( + tdata2_d[i], ex_i.cause + ) && priv_match[i] && !etrigger_context_saved_valid_q) begin + e_matched_d[i] = 1'b1; + end + if (e_matched_q[i] && trigger_32_tdata1_d[i].etrigger_type.action == '0 && !native_allowed) begin + // The trap handler runs where an action=0 trigger cannot fire: drop the match + e_matched_d[i] = 1'b0; + etrigger_context_saved_valid_d = 1'b0; + end else if (e_matched_q[i]) begin + fire_req_Etrigger.valid = 1'b1; + unique case (trigger_32_tdata1_d[i].etrigger_type.action) + 6'd0: + if (CVA6Cfg.SdtrigSupportedActions[0]) fire_req_Etrigger.action = riscv::BREAKPOINT; + 6'd1: + if (CVA6Cfg.SdtrigSupportedActions[1]) + fire_req_Etrigger.action = riscv::DEBUG_TRIGGER; + default: ; + endcase + end + if (e_matched_q[i] && sdtrig_commit_std_exception_valid_q && (ex_i.valid || debug_mode_i)) begin + trigger_32_tdata1_d[i].etrigger_type.hit = 1'b1; + e_matched_d[i] = 1'b0; + fire_req_Etrigger.valid = 1'b0; + end + if (e_matched_d[i] && ex_i.valid) begin + etrigger_context_saved_valid_d = 1'b1; + etrigger_context_mepc_d = mepc_i; + etrigger_context_mcause_d = mcause_i; + etrigger_context_mtval_d = mtval_i; + end + end + // itrigger match logic + if (trigger_type_d[i] == 4'd4 && CVA6Cfg.SdtrigItrigger) begin + case(priv_lvl_i) // trigger will only fire if current priv lvl is same as the trigger configuration + riscv::PRIV_LVL_M: if (trigger_32_tdata1_d[i].itrigger_type.m) priv_match[i] = 1'b1; + riscv::PRIV_LVL_S: if (trigger_32_tdata1_d[i].itrigger_type.s) priv_match[i] = 1'b1; + riscv::PRIV_LVL_U: if (trigger_32_tdata1_d[i].itrigger_type.u) priv_match[i] = 1'b1; + default: priv_match[i] = 1'b0; + endcase + // Context match check (textra), in all modes + if (CVA6Cfg.SdtrigSupportTextra) begin + if (CVA6Cfg.IS_XLEN32) begin + scontext_match[i] = match_scontext32( + scontext_i, + textra32_tdata3_d[i].sselect, + textra32_tdata3_d[i].sbytemask, + textra32_tdata3_d[i].svalue, + 1'b0 + ); + end else begin + scontext_match[i] = match_scontext64( + scontext_i, + textra64_tdata3_d[i].sselect, + textra64_tdata3_d[i].sbytemask, + textra64_tdata3_d[i].svalue, + 1'b1 + ); + end + priv_match[i] &= scontext_match[i]; + end + // Only an interrupt matches, not an exception. Checking etrigger context valid bit avoids + // conflicts and context loss because of concurrent triggering by different types + if (trap_taken && ex_i.cause[CVA6Cfg.XLEN-1] && cause_selected( + tdata2_d[i], ex_i.cause + ) && priv_match[i] && !etrigger_context_saved_valid_q) begin + e_matched_d[i] = 1'b1; + end + // The trigger fires just before the first instruction of the trap handler + if (e_matched_q[i] && trigger_32_tdata1_d[i].itrigger_type.action == '0 && !native_allowed) begin + // The trap handler runs where an action=0 trigger cannot fire: drop the match + e_matched_d[i] = 1'b0; + etrigger_context_saved_valid_d = 1'b0; + end else if (e_matched_q[i]) begin + fire_req_Itrigger.valid = 1'b1; + case (trigger_32_tdata1_d[i].itrigger_type.action) + 6'd0: + if (CVA6Cfg.SdtrigSupportedActions[0]) fire_req_Itrigger.action = riscv::BREAKPOINT; + 6'd1: + if (CVA6Cfg.SdtrigSupportedActions[1]) + fire_req_Itrigger.action = riscv::DEBUG_TRIGGER; + default: ; + endcase + end + if (e_matched_q[i] && sdtrig_commit_std_exception_valid_q && (ex_i.valid || debug_mode_i)) begin + trigger_32_tdata1_d[i].itrigger_type.hit = 1'b1; + e_matched_d[i] = 1'b0; + fire_req_Itrigger.valid = 1'b0; + end + if (e_matched_d[i] && ex_i.valid) begin + etrigger_context_saved_valid_d = 1'b1; + etrigger_context_mepc_d = mepc_i; + etrigger_context_mcause_d = mcause_i; + etrigger_context_mtval_d = mtval_i; + end + end + end + + + //Trigger fire logic + //Priorities : load data > execute address > execute data > load address/store address/store data + if (CVA6Cfg.SdtrigMcontrol6LoadData && fire_req_LD.valid || CVA6Cfg.SdtrigIcount && fire_req_Icount.valid || CVA6Cfg.SdtrigEtrigger && fire_req_Etrigger.valid || CVA6Cfg.SdtrigItrigger && fire_req_Itrigger.valid) begin + if (fire_req_LD.valid) begin + sdtrig_load_stall_o = 1'b1; + sdtrig_load_action_o = fire_req_LD.action; + end + if (fire_req_Icount.valid) begin + sdtrig_commit_icount_valid_d = 1'b1; + sdtrig_commit_action_d = fire_req_Icount.action; + end + if (fire_req_Etrigger.valid) begin + sdtrig_commit_std_exception_valid_d = 1'b1; + sdtrig_commit_action_d = fire_req_Etrigger.action; + end + if (fire_req_Itrigger.valid) begin + sdtrig_commit_std_exception_valid_d = 1'b1; + sdtrig_commit_action_d = fire_req_Itrigger.action; + end + end else if (CVA6Cfg.SdtrigMcontrol6ExecAddr && |fire_req_EA_valid) begin + sdtrig_decoder_action_o = fire_req_EA_action; + end else if (CVA6Cfg.SdtrigMcontrol6ExecData && |fire_req_ED_valid) begin + sdtrig_decoder_action_o = fire_req_ED_action; + end else + + if (CVA6Cfg.SdtrigMcontrol6LoadAddr && fire_req_LA.valid || CVA6Cfg.SdtrigMcontrol6Store && fire_req_SX.valid) begin + if (CVA6Cfg.SdtrigMcontrol6LoadAddr && fire_req_LA.valid && !sdtrig_lsu_inputs_fu_i) begin + sdtrig_load_cancel_d = (sdtrig_load_cancel_q) ? 1'b0 : 1'b1; + if (!sdtrig_load_cancel_q) sdtrig_load_action_d = fire_req_LA.action; + sdtrig_load_action_o = sdtrig_load_cancel_q ? sdtrig_load_action_q : fire_req_LA.action; + end + // The store unit executes lr and the AMOs: it takes the action of a load address match too + if (CVA6Cfg.SdtrigMcontrol6Store && fire_req_SX.valid) begin + sdtrig_store_action_o = fire_req_SX.action; + sdtrig_store_stall_o = 1'b1; + end else if (CVA6Cfg.SdtrigMcontrol6LoadAddr && fire_req_LA.valid && sdtrig_lsu_inputs_fu_i) begin + sdtrig_store_action_o = fire_req_LA.action; + sdtrig_store_stall_o = 1'b1; + end + end + end + + // Trigger module CSRs + if (tselect_we) begin + tselect_d = (tselect_i < CVA6Cfg.SdtrigNrTriggers) ? + tselect_i[$clog2(CVA6Cfg.SdtrigNrTriggers)-1:0] : tselect_q; + end + if (tdata1_we && (!trigger_32_tdata1_q[tselect_q].tdata1_type[27] || debug_mode_i)) begin + if (CVA6Cfg.IS_XLEN32) begin + if (CVA6Cfg.Sdtrig && CVA6Cfg.SdtrigNrTriggers > 0) begin + if( CVA6Cfg.SdtrigIcount && tdata1_i[31:28] == 4'd3 + || CVA6Cfg.SdtrigMcontrol6 && tdata1_i[31:28] == 4'd6 + || CVA6Cfg.SdtrigEtrigger && tdata1_i[31:28] == 4'd5 + || CVA6Cfg.SdtrigItrigger && tdata1_i[31:28] == 4'd4) begin + trigger_type_d[tselect_q] = tdata1_i[31:28]; + end else begin + // Type 0, type 15 and the types that are not supported disable the trigger + trigger_type_d[tselect_q] = 4'd15; + end + if (trigger_type_d[tselect_q] == 4'd15) begin + trigger_32_tdata1_d[tselect_q] = '0; + trigger_32_tdata1_d[tselect_q].tdata1_type[31:27] = { + 4'd15, debug_mode_i && tdata1_i[27] + }; + flush_o = 1'b1; + end else if (CVA6Cfg.SdtrigIcount && trigger_type_d[tselect_q] == 4'd3) begin + trigger_32_tdata1_d[tselect_q].icount_type.t_type = trigger_type_d[tselect_q]; + trigger_32_tdata1_d[tselect_q].icount_type.dmode = debug_mode_i && tdata1_i[27]; + trigger_32_tdata1_d[tselect_q].icount_type.vs = 0; + trigger_32_tdata1_d[tselect_q].icount_type.vu = 0; + trigger_32_tdata1_d[tselect_q].icount_type.hit = tdata1_i[24]; + trigger_32_tdata1_d[tselect_q].icount_type.count = tdata1_i[23:10]; + trigger_32_tdata1_d[tselect_q].icount_type.m = tdata1_i[9]; + trigger_32_tdata1_d[tselect_q].icount_type.pending = tdata1_i[8]; + trigger_32_tdata1_d[tselect_q].icount_type.s = tdata1_i[7]; + trigger_32_tdata1_d[tselect_q].icount_type.u = tdata1_i[6]; + trigger_32_tdata1_d[tselect_q].icount_type.action = + legal_action(tdata1_i[5:0], debug_mode_i && tdata1_i[27]); + flush_o = 1'b1; + end else if (CVA6Cfg.SdtrigMcontrol6 && trigger_type_d[tselect_q] == 4'd6) begin + trigger_32_tdata1_d[tselect_q].mc6_type.t_type = trigger_type_d[tselect_q]; + trigger_32_tdata1_d[tselect_q].mc6_type.dmode = debug_mode_i && tdata1_i[27]; + trigger_32_tdata1_d[tselect_q].mc6_type.uncertain = 0; + trigger_32_tdata1_d[tselect_q].mc6_type.hit1 = tdata1_i[25]; + trigger_32_tdata1_d[tselect_q].mc6_type.vs = 0; + trigger_32_tdata1_d[tselect_q].mc6_type.vu = 0; + trigger_32_tdata1_d[tselect_q].mc6_type.hit0 = tdata1_i[22]; + trigger_32_tdata1_d[tselect_q].mc6_type.select = tdata1_i[21]; + trigger_32_tdata1_d[tselect_q].mc6_type.zeroes = '0; + trigger_32_tdata1_d[tselect_q].mc6_type.size = tdata1_i[18:16]; + trigger_32_tdata1_d[tselect_q].mc6_type.action = + 4'(legal_action(6'(tdata1_i[15:12]), debug_mode_i && tdata1_i[27])); + trigger_32_tdata1_d[tselect_q].mc6_type.chain = tdata1_i[11]; + trigger_32_tdata1_d[tselect_q].mc6_type.match = tdata1_i[10:7]; + trigger_32_tdata1_d[tselect_q].mc6_type.m = tdata1_i[6]; + trigger_32_tdata1_d[tselect_q].mc6_type.uncertainen = 0; + trigger_32_tdata1_d[tselect_q].mc6_type.s = tdata1_i[4]; + trigger_32_tdata1_d[tselect_q].mc6_type.u = tdata1_i[3]; + trigger_32_tdata1_d[tselect_q].mc6_type.execute = tdata1_i[2]; + trigger_32_tdata1_d[tselect_q].mc6_type.store = tdata1_i[1]; + trigger_32_tdata1_d[tselect_q].mc6_type.load = tdata1_i[0]; + flush_o = 1'b1; + end else if (CVA6Cfg.SdtrigEtrigger && trigger_type_d[tselect_q] == 4'd5) begin + trigger_32_tdata1_d[tselect_q].etrigger_type.t_type = trigger_type_d[tselect_q]; + trigger_32_tdata1_d[tselect_q].etrigger_type.dmode = debug_mode_i && tdata1_i[27]; + trigger_32_tdata1_d[tselect_q].etrigger_type.hit = tdata1_i[26]; + trigger_32_tdata1_d[tselect_q].etrigger_type.zeroes = '0; + trigger_32_tdata1_d[tselect_q].etrigger_type.vs = 0; + trigger_32_tdata1_d[tselect_q].etrigger_type.vu = 0; + trigger_32_tdata1_d[tselect_q].etrigger_type.zeroed = 0; + trigger_32_tdata1_d[tselect_q].etrigger_type.m = tdata1_i[9]; + trigger_32_tdata1_d[tselect_q].etrigger_type.zero = 0; + trigger_32_tdata1_d[tselect_q].etrigger_type.s = tdata1_i[7]; + trigger_32_tdata1_d[tselect_q].etrigger_type.u = tdata1_i[6]; + trigger_32_tdata1_d[tselect_q].etrigger_type.action = + legal_action(tdata1_i[5:0], debug_mode_i && tdata1_i[27]); + end else if (CVA6Cfg.SdtrigItrigger && trigger_type_d[tselect_q] == 4'd4) begin + trigger_32_tdata1_d[tselect_q].itrigger_type.t_type = trigger_type_d[tselect_q]; + trigger_32_tdata1_d[tselect_q].itrigger_type.dmode = debug_mode_i && tdata1_i[27]; + trigger_32_tdata1_d[tselect_q].itrigger_type.hit = tdata1_i[26]; + trigger_32_tdata1_d[tselect_q].itrigger_type.zeroed = '0; + trigger_32_tdata1_d[tselect_q].itrigger_type.vs = 0; + trigger_32_tdata1_d[tselect_q].itrigger_type.vu = 0; + trigger_32_tdata1_d[tselect_q].itrigger_type.nmi = 0; + trigger_32_tdata1_d[tselect_q].itrigger_type.m = tdata1_i[9]; + trigger_32_tdata1_d[tselect_q].itrigger_type.zero = 0; + trigger_32_tdata1_d[tselect_q].itrigger_type.s = tdata1_i[7]; + trigger_32_tdata1_d[tselect_q].itrigger_type.u = tdata1_i[6]; + trigger_32_tdata1_d[tselect_q].itrigger_type.action = + legal_action(tdata1_i[5:0], debug_mode_i && tdata1_i[27]); + end + end + end else if (CVA6Cfg.IS_XLEN64) begin + if (CVA6Cfg.SdtrigIcount && tdata1_i[63:60] == 4'd3) begin + trigger_type_d[tselect_q] = tdata1_i[63:60]; + trigger_32_tdata1_d[tselect_q].icount_type.t_type = (tdata1_i[63:60] == 4'd3 || tdata1_i[63:60] == 4'd15) ? tdata1_i[63:60] : trigger_type_q[tselect_q]; + trigger_32_tdata1_d[tselect_q].icount_type.dmode = debug_mode_i && tdata1_i[59]; + trigger_32_tdata1_d[tselect_q].icount_type.vs = 0; + trigger_32_tdata1_d[tselect_q].icount_type.vu = 0; + trigger_32_tdata1_d[tselect_q].icount_type.hit = tdata1_i[24]; + trigger_32_tdata1_d[tselect_q].icount_type.count = tdata1_i[23:10]; + trigger_32_tdata1_d[tselect_q].icount_type.m = tdata1_i[9]; + trigger_32_tdata1_d[tselect_q].icount_type.pending = tdata1_i[8]; + trigger_32_tdata1_d[tselect_q].icount_type.s = tdata1_i[7]; + trigger_32_tdata1_d[tselect_q].icount_type.u = tdata1_i[6]; + trigger_32_tdata1_d[tselect_q].icount_type.action = + legal_action(tdata1_i[5:0], debug_mode_i && tdata1_i[59]); + flush_o = 1'b1; + end else if (CVA6Cfg.SdtrigMcontrol6 && tdata1_i[63:60] == 4'd6) begin + trigger_type_d[tselect_q] = tdata1_i[63:60]; + trigger_32_tdata1_d[tselect_q].mc6_type.t_type = (tdata1_i[63:60] == 4'd6 || tdata1_i[63:60] == 4'd15) ? tdata1_i[63:60] : trigger_type_q[tselect_q]; + trigger_32_tdata1_d[tselect_q].mc6_type.dmode = debug_mode_i && tdata1_i[59]; + trigger_32_tdata1_d[tselect_q].mc6_type.uncertain = 0; + trigger_32_tdata1_d[tselect_q].mc6_type.hit1 = tdata1_i[25]; + trigger_32_tdata1_d[tselect_q].mc6_type.vs = 0; + trigger_32_tdata1_d[tselect_q].mc6_type.vu = 0; + trigger_32_tdata1_d[tselect_q].mc6_type.hit0 = tdata1_i[22]; + trigger_32_tdata1_d[tselect_q].mc6_type.select = tdata1_i[21]; + trigger_32_tdata1_d[tselect_q].mc6_type.zeroes = '0; + trigger_32_tdata1_d[tselect_q].mc6_type.size = tdata1_i[18:16]; + trigger_32_tdata1_d[tselect_q].mc6_type.action = + 4'(legal_action(6'(tdata1_i[15:12]), debug_mode_i && tdata1_i[59])); + trigger_32_tdata1_d[tselect_q].mc6_type.chain = tdata1_i[11]; + trigger_32_tdata1_d[tselect_q].mc6_type.match = tdata1_i[10:7]; + trigger_32_tdata1_d[tselect_q].mc6_type.m = tdata1_i[6]; + trigger_32_tdata1_d[tselect_q].mc6_type.uncertainen = 0; + trigger_32_tdata1_d[tselect_q].mc6_type.s = tdata1_i[4]; + trigger_32_tdata1_d[tselect_q].mc6_type.u = tdata1_i[3]; + trigger_32_tdata1_d[tselect_q].mc6_type.execute = tdata1_i[2]; + trigger_32_tdata1_d[tselect_q].mc6_type.store = tdata1_i[1]; + trigger_32_tdata1_d[tselect_q].mc6_type.load = tdata1_i[0]; + flush_o = 1'b1; + end else if (CVA6Cfg.SdtrigEtrigger && tdata1_i[63:60] == 4'd5) begin + trigger_type_d[tselect_q] = tdata1_i[63:60]; + trigger_32_tdata1_d[tselect_q].etrigger_type.t_type = (tdata1_i[63:60] == 4'd5 || tdata1_i[63:60] == 4'd15) ? tdata1_i[63:60] : trigger_type_q[tselect_q]; + trigger_32_tdata1_d[tselect_q].etrigger_type.dmode = debug_mode_i && tdata1_i[59]; + trigger_32_tdata1_d[tselect_q].etrigger_type.hit = tdata1_i[58]; + trigger_32_tdata1_d[tselect_q].etrigger_type.zeroes = '0; + trigger_32_tdata1_d[tselect_q].etrigger_type.vs = 0; + trigger_32_tdata1_d[tselect_q].etrigger_type.vu = 0; + trigger_32_tdata1_d[tselect_q].etrigger_type.zeroed = 0; + trigger_32_tdata1_d[tselect_q].etrigger_type.m = tdata1_i[9]; + trigger_32_tdata1_d[tselect_q].etrigger_type.zero = 0; + trigger_32_tdata1_d[tselect_q].etrigger_type.s = tdata1_i[7]; + trigger_32_tdata1_d[tselect_q].etrigger_type.u = tdata1_i[6]; + trigger_32_tdata1_d[tselect_q].etrigger_type.action = + legal_action(tdata1_i[5:0], debug_mode_i && tdata1_i[59]); + end else if (CVA6Cfg.SdtrigItrigger && tdata1_i[63:60] == 4'd4) begin + trigger_type_d[tselect_q] = tdata1_i[63:60]; + trigger_32_tdata1_d[tselect_q].itrigger_type.t_type = (tdata1_i[63:60] == 4'd4 || tdata1_i[63:60] == 4'd15) ? tdata1_i[63:60] : trigger_type_q[tselect_q]; + trigger_32_tdata1_d[tselect_q].itrigger_type.dmode = debug_mode_i && tdata1_i[59]; + trigger_32_tdata1_d[tselect_q].itrigger_type.hit = tdata1_i[58]; + trigger_32_tdata1_d[tselect_q].itrigger_type.zeroed = '0; + trigger_32_tdata1_d[tselect_q].itrigger_type.vs = 0; + trigger_32_tdata1_d[tselect_q].itrigger_type.vu = 0; + trigger_32_tdata1_d[tselect_q].itrigger_type.nmi = 0; + trigger_32_tdata1_d[tselect_q].itrigger_type.m = tdata1_i[9]; + trigger_32_tdata1_d[tselect_q].itrigger_type.zero = 0; + trigger_32_tdata1_d[tselect_q].itrigger_type.s = tdata1_i[7]; + trigger_32_tdata1_d[tselect_q].itrigger_type.u = tdata1_i[6]; + trigger_32_tdata1_d[tselect_q].itrigger_type.action = + legal_action(tdata1_i[5:0], debug_mode_i && tdata1_i[59]); + end else begin + // Type 0, type 15 and the types that are not supported disable the trigger + trigger_type_d[tselect_q] = 4'd15; + trigger_32_tdata1_d[tselect_q] = '0; + trigger_32_tdata1_d[tselect_q].tdata1_type[31:27] = {4'd15, debug_mode_i && tdata1_i[59]}; + flush_o = 1'b1; + end + end + end + if (tdata2_we && (!trigger_32_tdata1_q[tselect_q].tdata1_type[27] || debug_mode_i)) begin + tdata2_d[tselect_q] = tdata2_i; + flush_o = 1'b1; + end + if (CVA6Cfg.SdtrigSupportTextra && tdata3_we && (!trigger_32_tdata1_q[tselect_q].tdata1_type[27] || debug_mode_i)) begin + if (CVA6Cfg.IS_XLEN32) begin + textra32_tdata3_d[tselect_q].mhvalue = '0; + textra32_tdata3_d[tselect_q].mhselect = '0; + textra32_tdata3_d[tselect_q].zeroes = '0; + textra32_tdata3_d[tselect_q].sbytemask = tdata3_i[19:18]; + textra32_tdata3_d[tselect_q].svalue = tdata3_i[17:2]; + textra32_tdata3_d[tselect_q].sselect = (tdata3_i[1:0] == 2'd1) ? 2'd1 : 2'd0; + end + if (CVA6Cfg.IS_XLEN64) begin // textra64 + textra64_tdata3_d[tselect_q].mhvalue = '0; + textra64_tdata3_d[tselect_q].mhselect = '0; + textra64_tdata3_d[tselect_q].zeroes = '0; + textra64_tdata3_d[tselect_q].sbytemask = tdata3_i[39:36]; + textra64_tdata3_d[tselect_q].zero_field = '0; + textra64_tdata3_d[tselect_q].svalue = tdata3_i[33:2]; + textra64_tdata3_d[tselect_q].sselect = (tdata3_i[1:0] == 2'd1) ? 2'd1 : 2'd0; + end + end + end + + always_comb begin : read_path + // TSELECT read + tselect_o = {{(CVA6Cfg.XLEN - CVA6Cfg.SdtrigNrTriggers) {1'b0}}, tselect_q}; + + // TDATA1 read (depends on trigger type) + unique case (trigger_type_q[tselect_q]) + 4'd3: + tdata1_o = (CVA6Cfg.IS_XLEN32) ? trigger_32_tdata1_q[tselect_q] : { trigger_32_tdata1_q[tselect_q].icount_type.t_type, trigger_32_tdata1_q[tselect_q].icount_type.dmode, 32'd0, trigger_32_tdata1_q[tselect_q][26:0] }; + 4'd6: + tdata1_o = (CVA6Cfg.IS_XLEN32) ? trigger_32_tdata1_q[tselect_q] : { trigger_32_tdata1_q[tselect_q].mc6_type.t_type, trigger_32_tdata1_q[tselect_q].mc6_type.dmode, 32'd0, trigger_32_tdata1_q[tselect_q][26:0] }; + 4'd5: + tdata1_o = (CVA6Cfg.IS_XLEN32) ? trigger_32_tdata1_q[tselect_q] : { trigger_32_tdata1_q[tselect_q].etrigger_type.t_type, trigger_32_tdata1_q[tselect_q].etrigger_type.dmode, trigger_32_tdata1_q[tselect_q].etrigger_type.hit, 45'd0, trigger_32_tdata1_q[tselect_q][12:0] }; + 4'd4: + tdata1_o = (CVA6Cfg.IS_XLEN32) ? trigger_32_tdata1_q[tselect_q] : { trigger_32_tdata1_q[tselect_q].itrigger_type.t_type, trigger_32_tdata1_q[tselect_q].itrigger_type.dmode, trigger_32_tdata1_q[tselect_q].itrigger_type.hit, 45'd0, trigger_32_tdata1_q[tselect_q][12:0] }; + 4'd15: + tdata1_o = { + 4'd15, trigger_32_tdata1_q[tselect_q].tdata1_type[27], {(CVA6Cfg.XLEN - 5) {1'b0}} + }; + default: tdata1_o = '0; + endcase + + // TDATA2 read + tdata2_o = {{(CVA6Cfg.XLEN - CVA6Cfg.VLEN) {1'b0}}, tdata2_q[tselect_q]}; + + // TDATA3 read + if (CVA6Cfg.SdtrigSupportTextra) + tdata3_o = (CVA6Cfg.IS_XLEN32) ? textra32_tdata3_q[tselect_q] : textra64_tdata3_q[tselect_q]; + end + + + always_ff @(posedge clk_i or negedge rst_ni) begin : state_update + if (~rst_ni) begin + if (CVA6Cfg.Sdtrig) begin + tselect_q <= '0; + e_matched_q <= '0; + sdtrig_commit_std_exception_valid_q <= 0; + sdtrig_commit_icount_valid_o <= 1'b0; + sdtrig_commit_icount_nr_instr_o <= '0; + sdtrig_commit_action_o <= '0; + sdtrig_load_stall_s <= '0; + sdtrig_load_cancel_q <= '0; + sdtrig_load_action_q <= '0; + etrigger_context_saved_valid_q <= 1'b0; + etrigger_context_mepc_q <= '0; + etrigger_context_mcause_q <= '0; + etrigger_context_mtval_q <= '0; + for (int i = 0; i < CVA6Cfg.SdtrigNrTriggers; ++i) begin + trigger_type_q[i] <= 4'd15; + trigger_32_tdata1_q[i] <= {4'd15, 28'd0}; + if (CVA6Cfg.SdtrigTriggerChaining) trigger_chain_vector_q[i] <= '0; + if (CVA6Cfg.SdtrigSupportTextra && CVA6Cfg.IS_XLEN32) textra32_tdata3_q[i] <= '0; + if (CVA6Cfg.SdtrigSupportTextra && CVA6Cfg.IS_XLEN64) textra64_tdata3_q[i] <= '0; + tdata2_q[i] <= '0; + end + end + end else begin + if (CVA6Cfg.Sdtrig) begin + if (CVA6Cfg.SdtrigSupportTextra && CVA6Cfg.IS_XLEN32) + textra32_tdata3_q <= textra32_tdata3_d; + if (CVA6Cfg.SdtrigSupportTextra && CVA6Cfg.IS_XLEN64) + textra64_tdata3_q <= textra64_tdata3_d; + + trigger_type_q <= trigger_type_d; + trigger_32_tdata1_q <= trigger_32_tdata1_d; + tselect_q <= tselect_d; + tdata2_q <= tdata2_d; + sdtrig_commit_icount_valid_o <= sdtrig_commit_icount_valid_d; + sdtrig_commit_icount_nr_instr_o <= sdtrig_commit_icount_nr_instr_d; + sdtrig_commit_action_o <= sdtrig_commit_action_d; + etrigger_context_saved_valid_q <= etrigger_context_saved_valid_d; + etrigger_context_mepc_q <= etrigger_context_mepc_d; + etrigger_context_mcause_q <= etrigger_context_mcause_d; + etrigger_context_mtval_q <= etrigger_context_mtval_d; + sdtrig_commit_std_exception_valid_q <= sdtrig_commit_std_exception_valid_d; + e_matched_q <= e_matched_d; + sdtrig_load_stall_s <= sdtrig_load_stall_o; + sdtrig_load_cancel_q <= sdtrig_load_cancel_d; + sdtrig_load_action_q <= sdtrig_load_action_d; + if (CVA6Cfg.SdtrigTriggerChaining) trigger_chain_vector_q <= trigger_chain_vector_d; + end + end + end + + // Outputs + assign sdtrig_commit_std_exception_valid_o = sdtrig_commit_std_exception_valid_q; + assign etrigger_context_saved_valid_o = etrigger_context_saved_valid_q; + assign etrigger_context_mepc_o = etrigger_context_mepc_q; + assign etrigger_context_mcause_o = etrigger_context_mcause_q; + if (CVA6Cfg.TvalEn) begin + assign etrigger_context_mtval_o = etrigger_context_mtval_q; + end else begin + assign etrigger_context_mtval_o = '0; + end + assign sdtrig_load_cancel_o = sdtrig_load_cancel_q; + +endmodule diff --git a/core/zcmt_decoder.sv b/core/zcmt_decoder.sv index c37c11fda5b..e02f541aea1 100644 --- a/core/zcmt_decoder.sv +++ b/core/zcmt_decoder.sv @@ -80,15 +80,15 @@ module zcmt_decoder #( IDLE: begin fetch_stall_o = 1'b0; if (is_zcmt_instr_i) begin - if (CVA6Cfg.XLEN == 32) begin //It is only target for 32 bit targets in cva6 with No MMU - table_address = {jvt_i.base, 6'b000000} + {24'h0, instr_i[7:2], 2'b00}; + if (CVA6Cfg.IS_XLEN32) begin //It is only target for 32 bit targets in cva6 with No MMU + table_address = {jvt_i.base, 6'b000000} + {22'h0, instr_i[9:2], 2'b00}; req_port_o.address_index = table_address[9:0]; req_port_o.address_tag = table_address[CVA6Cfg.VLEN-1:10]; // No MMU support state_d = TABLE_JUMP; req_port_o.data_req = 1'b1; fetch_stall_o = 1'b1; end else illegal_instr_o = 1'b1; - // Condition may be extented for 64 bits embedded targets with No MMU + // Condition may be extended for 64 bits embedded targets with No MMU end else begin illegal_instr_o = illegal_instr_i; instr_o = instr_i; @@ -97,16 +97,17 @@ module zcmt_decoder #( end TABLE_JUMP: begin if (req_port_i.data_rvalid) begin - // save the PC relative Xlen table jump address - jump_address_o = $unsigned($signed(req_port_i.data_rdata) - $signed(pc_i)); + // Clear bit 0 of the JVT target before converting it to a PC-relative offset. + jump_address_o = + $unsigned($signed({req_port_i.data_rdata[CVA6Cfg.XLEN-1:1], 1'b0}) - $signed(pc_i)); if (instr_i[9:2] < 32) begin // jal pc_offset, x0 for no return stack instr_o = { 20'h0, 5'h0, riscv::OpcodeJal - }; // immidiate assigned here (0) will be overwrite in decode stage with jump_address_o + }; // immediate assigned here (0) will be overwrite in decode stage with jump_address_o end else if ((instr_i[9:2] >= 32) & (instr_i[9:2] <= 255)) begin //- jal pc_offset, x1 for return stack instr_o = { 20'h0, 5'h1, riscv::OpcodeJal - }; // immidiate assigned here (0) will be overwrite in decode stage with jump_address_o + }; // immediate assigned here (0) will be overwrite in decode stage with jump_address_o end else begin illegal_instr_o = 1'b1; instr_o = instr_i; diff --git a/corev_apu/altera/Makefile b/corev_apu/altera/Makefile index f3f8983f755..e118135c758 100644 --- a/corev_apu/altera/Makefile +++ b/corev_apu/altera/Makefile @@ -52,7 +52,8 @@ all: create_project \ write_source_files \ write_timing_constraints \ generate_ips \ - sta + sta \ + rbf clean: $(RM) -rf *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db incremental_db *.summary *.smsg *.jdi $(ASSIGNMENT_FILES) @@ -72,9 +73,13 @@ create_project: @touch "$(PROJECT).qsf" $(QSYS_PATH)qsys-script --script=ip/interconnect.tcl $(QSYS_PATH)qsys-generate interconnect.qsys --quartus_project=ip/interconnect --synthesis + $(QSYS_PATH)qsys-script --script=ip/hps_cva6_altera.tcl + $(QSYS_PATH)qsys-generate system.qsys --quartus_project=ip/hps_cva6_altera --synthesis rm -f interconnect/*.v rm -f interconnect/*.vhd rm -f interconnect/synth/*.v + rm -f system/*.v + rm -f system/*.vhd write_settings: @echo "Reading from settings.csv and writing to $(PROJECT).qsf with modifications" @@ -108,6 +113,7 @@ write_search_paths: write_source_files: @find ./interconnect -type f -name "*.v" -o -name "*.sv" -o -name "*.svh" >> $(SOURCES_FILE) + @find ./system -type f -name "*.v" -o -name "*.sv" -o -name "*.svh" >> $(SOURCES_FILE) @echo $(var) @echo >> $(SOURCES_FILE) @echo "Reading from $(SOURCES_FILE) and writing to $(PROJECT).qsf with modifications" @@ -159,12 +165,16 @@ sta: asm @echo "Running Quartus Timing Analysis" $(QUARTUS_PATH)quartus_sta $(PROJECT) --do_report_timing +rbf: sta + @echo "Running Quartus Prime Programming File Generator" + $(QUARTUS_PATH)/quartus_pfg -c output_files/*.sof output_files/cva6-hps.rbf -o hps_path=u-boot-spl-dtb.hex + + clean: @echo "Cleaning project files" rm -f $(PROJECT).qsf $(PROJECT).qpf $(PROJECT).map.rpt $(PROJECT).fit.rpt $(PROJECT).asm.rpt $(PROJECT).sta.rpt rm -f interconnect.qsys* rm -f *.backup - rm -f *.hex rm -f *.txt rm -f *.ip rm -f ip/board.info @@ -191,6 +201,7 @@ clean: rm -rf interconnect rm -rf io_pll rm -rf iobuf + rm -rf system $(QUARTUS_PATH)quartus_ipgenerate --clean $(PROJECT) diff --git a/corev_apu/altera/io_standard_constraints.csv b/corev_apu/altera/io_standard_constraints.csv index e4fbc9e30e1..9ac64b8fcc4 100644 --- a/corev_apu/altera/io_standard_constraints.csv +++ b/corev_apu/altera/io_standard_constraints.csv @@ -5,3 +5,71 @@ IO_STANDARD "1.2 V" -to led[3] -entity cva6_altera IO_STANDARD "1.2 V" -to led[2] -entity cva6_altera IO_STANDARD "1.2 V" -to led[1] -entity cva6_altera IO_STANDARD "1.2 V" -to led[0] -entity cva6_altera +IO_STANDARD "1.8-V" -to hps_emac0_MDC -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_MDIO -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_RXD0 -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_RXD1 -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_RXD2 -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_RXD3 -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_RX_CLK -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_RX_CTL -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_TXD0 -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_TXD1 -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_TXD2 -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_TXD3 -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_TX_CLK -entity ghrd +IO_STANDARD "1.8-V" -to hps_emac0_TX_CTL -entity ghrd +IO_STANDARD "1.8-V" -to hps_i2c1_SCL -entity ghrd +IO_STANDARD "1.8-V" -to hps_i2c1_SDA -entity ghrd +IO_STANDARD "1.8-V" -to hps_jtag_tck -entity ghrd +IO_STANDARD "1.8-V" -to hps_jtag_tdo -entity ghrd +IO_STANDARD "1.8-V" -to hps_ref_clk -entity ghrd +IO_STANDARD "1.8 V" -to hps_sdmmc_CMD -entity ghrd +IO_STANDARD "1.8 V" -to hps_sdmmc_CCLK -entity ghrd +IO_STANDARD "1.8 V" -to hps_sdmmc_D0 -entity ghrd +IO_STANDARD "1.8 V" -to hps_sdmmc_D1 -entity ghrd +IO_STANDARD "1.8 V" -to hps_sdmmc_D2 -entity ghrd +IO_STANDARD "1.8 V" -to hps_sdmmc_D3 -entity ghrd +IO_STANDARD "1.8 V" -to hps_uart0_TX -entity ghrd +IO_STANDARD "1.8 V" -to hps_uart0_RX -entity ghrd +IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to fpga_clk_100 -entity ghrd +CURRENT_STRENGTH_NEW 4MA -to hps_emac0_MDC -entity ghrd +CURRENT_STRENGTH_NEW 4MA -to hps_emac0_MDIO -entity ghrd +AUTO_OPEN_DRAIN_PINS ON -to hps_emac0_MDIO -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_emac0_MDIO -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RXD0 -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RXD1 -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RXD2 -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RXD3 -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RX_CLK -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_emac0_RX_CTL -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TXD0 -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TXD1 -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TXD2 -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TXD3 -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TX_CLK -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_emac0_TX_CTL -entity ghrd +CURRENT_STRENGTH_NEW 4MA -to hps_i2c1_SCL -entity ghrd +AUTO_OPEN_DRAIN_PINS ON -to hps_i2c1_SCL -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_i2c1_SCL -entity ghrd +CURRENT_STRENGTH_NEW 4MA -to hps_i2c1_SDA -entity ghrd +AUTO_OPEN_DRAIN_PINS ON -to hps_i2c1_SDA -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_i2c1_SDA -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_jtag_tck -entity ghrd +IO_STANDARD "1.8-V" -to hps_jtag_tdi -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_jtag_tdi -entity ghrd +CURRENT_STRENGTH_NEW 4MA -to hps_jtag_tdo -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_jtag_tms -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_CMD -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_CCLK -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_CMD -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_D0 -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_D0 -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_D1 -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_D1 -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_D2 -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_D2 -entity ghrd +CURRENT_STRENGTH_NEW 8MA -to hps_sdmmc_D3 -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_sdmmc_D3 -entity ghrd +CURRENT_STRENGTH_NEW 4MA -to hps_uart0_TX -entity ghrd +WEAK_PULL_UP_RESISTOR ON -to hps_uart0_RX -entity ghrd \ No newline at end of file diff --git a/corev_apu/altera/ip/emif_cal.tcl b/corev_apu/altera/ip/emif_cal.tcl index 97f7a6f4265..055eb919395 100644 --- a/corev_apu/altera/ip/emif_cal.tcl +++ b/corev_apu/altera/ip/emif_cal.tcl @@ -24,7 +24,7 @@ proc do_create_emif_cal {} { set_instance_parameter_value emif_cal_0 {DIAG_SIM_VERBOSE} {0} set_instance_parameter_value emif_cal_0 {DIAG_SYNTH_FOR_SIM} {0} set_instance_parameter_value emif_cal_0 {ENABLE_DDRT} {0} - set_instance_parameter_value emif_cal_0 {NUM_CALBUS_INTERFACE} {1} + set_instance_parameter_value emif_cal_0 {NUM_CALBUS_INTERFACE} {2} set_instance_parameter_value emif_cal_0 {PHY_DDRT_EXPORT_CLK_STP_IF} {0} set_instance_parameter_value emif_cal_0 {SHORT_QSYS_INTERFACE_NAMES} {1} set_instance_property emif_cal_0 AUTO_EXPORT true diff --git a/corev_apu/altera/ip/hps_cva6_altera.tcl b/corev_apu/altera/ip/hps_cva6_altera.tcl new file mode 100644 index 00000000000..7e667be3647 --- /dev/null +++ b/corev_apu/altera/ip/hps_cva6_altera.tcl @@ -0,0 +1,2542 @@ +package require -exact qsys 24.1 + +# create the system "system" +proc do_create_system {} { + # create the system + create_system system + set_project_property BOARD {default} + set_project_property DEVICE {AGFB014R24B2E2V} + set_project_property DEVICE_FAMILY {Agilex 7} + set_project_property HIDE_FROM_IP_CATALOG {false} + set_use_testbench_naming_pattern 0 {} + + # add HDL parameters + + # add the components + add_component hps ip/system/hps.ip intel_agilex_hps hps 24.0.0 + load_component hps + set_component_parameter_value CLK_MAIN_PLL_SOURCE2 {0} + set_component_parameter_value CLK_PERI_PLL_SOURCE2 {0} + set_component_parameter_value CM_Mode {N/A} + set_component_parameter_value CM_PinMuxing {Unused} + set_component_parameter_value CONFIG_HPS_DIV_GPIO {1} + set_component_parameter_value CTI_Enable {0} + set_component_parameter_value CUSTOM_MPU_CLK {800.0} + set_component_parameter_value DDR_ATB_Enable {0} + set_component_parameter_value DEBUG_APB_Enable {0} + set_component_parameter_value DISABLE_PERI_PLL {0} + set_component_parameter_value DMA_Enable {No No No No No No No No} + set_component_parameter_value EMAC0_CLK {250} + set_component_parameter_value EMAC0_Mode {RGMII_with_MDIO} + set_component_parameter_value EMAC0_PTP {0} + set_component_parameter_value EMAC0_PinMuxing {IO} + set_component_parameter_value EMAC0_SWITCH_Enable {0} + set_component_parameter_value EMAC1_CLK {250} + set_component_parameter_value EMAC1_Mode {N/A} + set_component_parameter_value EMAC1_PTP {0} + set_component_parameter_value EMAC1_PinMuxing {Unused} + set_component_parameter_value EMAC1_SWITCH_Enable {0} + set_component_parameter_value EMAC2_CLK {250} + set_component_parameter_value EMAC2_Mode {N/A} + set_component_parameter_value EMAC2_PTP {0} + set_component_parameter_value EMAC2_PinMuxing {Unused} + set_component_parameter_value EMAC2_SWITCH_Enable {0} + set_component_parameter_value EMAC_PTP_REF_CLK {100} + set_component_parameter_value EMIF_CONDUIT_Enable {1} + set_component_parameter_value EMIF_DDR_WIDTH {64} + set_component_parameter_value F2H_FREE_CLK_Enable {0} + set_component_parameter_value F2H_FREE_CLK_FREQ {200} + set_component_parameter_value F2SINTERRUPT_Enable {0} + set_component_parameter_value F2S_ADDRESS_WIDTH {32} + set_component_parameter_value F2S_Route_config {2} + set_component_parameter_value F2S_Width {3} + set_component_parameter_value F2S_mode {1} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK {2.5} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK {2.5} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK {2.5} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT {125} + set_component_parameter_value FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT {125} + set_component_parameter_value FP_EMIF_CONDUIT_Enable {1} + set_component_parameter_value FP_F2S_Width {0} + set_component_parameter_value GP_Enable {0} + set_component_parameter_value H2F_COLD_RST_Enable {0} + set_component_parameter_value H2F_PENDING_RST_Enable {0} + set_component_parameter_value H2F_USER0_CLK_Enable {0} + set_component_parameter_value H2F_USER0_CLK_FREQ {500} + set_component_parameter_value H2F_USER1_CLK_Enable {0} + set_component_parameter_value H2F_USER1_CLK_FREQ {500} + set_component_parameter_value HNOC_Interface_Mode {0} + set_component_parameter_value HPS_DIV_GPIO_FREQ2 {100} + set_component_parameter_value HPS_IOA_10_open_drain_en {0} + set_component_parameter_value HPS_IOA_11_open_drain_en {0} + set_component_parameter_value HPS_IOA_12_open_drain_en {0} + set_component_parameter_value HPS_IOA_13_open_drain_en {0} + set_component_parameter_value HPS_IOA_14_open_drain_en {0} + set_component_parameter_value HPS_IOA_15_open_drain_en {0} + set_component_parameter_value HPS_IOA_16_open_drain_en {0} + set_component_parameter_value HPS_IOA_17_open_drain_en {0} + set_component_parameter_value HPS_IOA_18_open_drain_en {0} + set_component_parameter_value HPS_IOA_19_open_drain_en {0} + set_component_parameter_value HPS_IOA_1_open_drain_en {0} + set_component_parameter_value HPS_IOA_20_open_drain_en {0} + set_component_parameter_value HPS_IOA_21_open_drain_en {0} + set_component_parameter_value HPS_IOA_22_open_drain_en {0} + set_component_parameter_value HPS_IOA_23_open_drain_en {0} + set_component_parameter_value HPS_IOA_24_open_drain_en {0} + set_component_parameter_value HPS_IOA_2_open_drain_en {0} + set_component_parameter_value HPS_IOA_3_open_drain_en {0} + set_component_parameter_value HPS_IOA_4_open_drain_en {0} + set_component_parameter_value HPS_IOA_5_open_drain_en {0} + set_component_parameter_value HPS_IOA_6_open_drain_en {0} + set_component_parameter_value HPS_IOA_7_open_drain_en {0} + set_component_parameter_value HPS_IOA_8_open_drain_en {0} + set_component_parameter_value HPS_IOA_9_open_drain_en {0} + set_component_parameter_value HPS_IOB_10_open_drain_en {0} + set_component_parameter_value HPS_IOB_11_open_drain_en {0} + set_component_parameter_value HPS_IOB_12_open_drain_en {0} + set_component_parameter_value HPS_IOB_13_open_drain_en {0} + set_component_parameter_value HPS_IOB_14_open_drain_en {0} + set_component_parameter_value HPS_IOB_15_open_drain_en {0} + set_component_parameter_value HPS_IOB_16_open_drain_en {0} + set_component_parameter_value HPS_IOB_17_open_drain_en {0} + set_component_parameter_value HPS_IOB_18_open_drain_en {0} + set_component_parameter_value HPS_IOB_19_open_drain_en {0} + set_component_parameter_value HPS_IOB_1_open_drain_en {0} + set_component_parameter_value HPS_IOB_20_open_drain_en {0} + set_component_parameter_value HPS_IOB_21_open_drain_en {0} + set_component_parameter_value HPS_IOB_22_open_drain_en {0} + set_component_parameter_value HPS_IOB_23_open_drain_en {0} + set_component_parameter_value HPS_IOB_24_open_drain_en {0} + set_component_parameter_value HPS_IOB_2_open_drain_en {0} + set_component_parameter_value HPS_IOB_3_open_drain_en {0} + set_component_parameter_value HPS_IOB_4_open_drain_en {0} + set_component_parameter_value HPS_IOB_5_open_drain_en {0} + set_component_parameter_value HPS_IOB_6_open_drain_en {0} + set_component_parameter_value HPS_IOB_7_open_drain_en {0} + set_component_parameter_value HPS_IOB_8_open_drain_en {0} + set_component_parameter_value HPS_IOB_9_open_drain_en {0} + set_component_parameter_value HPS_IO_Enable {NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE EMAC0:TX_CLK EMAC0:TX_CTL EMAC0:RX_CLK EMAC0:RX_CTL EMAC0:TXD0 EMAC0:TXD1 EMAC0:RXD0 EMAC0:RXD1 EMAC0:TXD2 EMAC0:TXD3 EMAC0:RXD2 EMAC0:RXD3 GPIO NONE UART0:TX UART0:RX NONE NONE I2C1:SDA I2C1:SCL JTAG:TCK JTAG:TMS JTAG:TDO JTAG:TDI SDMMC:D0 SDMMC:CMD SDMMC:CCLK SDMMC:D1 SDMMC:D2 SDMMC:D3 HPS_OSC_CLK NONE NONE NONE MDIO0:MDIO MDIO0:MDC} + set_component_parameter_value I2C0_Mode {N/A} + set_component_parameter_value I2C0_PinMuxing {Unused} + set_component_parameter_value I2C1_Mode {default} + set_component_parameter_value I2C1_PinMuxing {IO} + set_component_parameter_value I2CEMAC0_Mode {N/A} + set_component_parameter_value I2CEMAC0_PinMuxing {Unused} + set_component_parameter_value I2CEMAC1_Mode {N/A} + set_component_parameter_value I2CEMAC1_PinMuxing {Unused} + set_component_parameter_value I2CEMAC2_Mode {N/A} + set_component_parameter_value I2CEMAC2_PinMuxing {Unused} + set_component_parameter_value INTERNAL_OSCILLATOR_ENABLE {60} + set_component_parameter_value IO_INPUT_DELAY0 {0} + set_component_parameter_value IO_INPUT_DELAY1 {0} + set_component_parameter_value IO_INPUT_DELAY10 {0} + set_component_parameter_value IO_INPUT_DELAY11 {0} + set_component_parameter_value IO_INPUT_DELAY12 {0} + set_component_parameter_value IO_INPUT_DELAY13 {0} + set_component_parameter_value IO_INPUT_DELAY14 {0} + set_component_parameter_value IO_INPUT_DELAY15 {0} + set_component_parameter_value IO_INPUT_DELAY16 {0} + set_component_parameter_value IO_INPUT_DELAY17 {0} + set_component_parameter_value IO_INPUT_DELAY18 {0} + set_component_parameter_value IO_INPUT_DELAY19 {0} + set_component_parameter_value IO_INPUT_DELAY2 {0} + set_component_parameter_value IO_INPUT_DELAY20 {0} + set_component_parameter_value IO_INPUT_DELAY21 {0} + set_component_parameter_value IO_INPUT_DELAY22 {0} + set_component_parameter_value IO_INPUT_DELAY23 {0} + set_component_parameter_value IO_INPUT_DELAY24 {0} + set_component_parameter_value IO_INPUT_DELAY25 {0} + set_component_parameter_value IO_INPUT_DELAY26 {0} + set_component_parameter_value IO_INPUT_DELAY27 {0} + set_component_parameter_value IO_INPUT_DELAY28 {0} + set_component_parameter_value IO_INPUT_DELAY29 {0} + set_component_parameter_value IO_INPUT_DELAY3 {0} + set_component_parameter_value IO_INPUT_DELAY30 {0} + set_component_parameter_value IO_INPUT_DELAY31 {0} + set_component_parameter_value IO_INPUT_DELAY32 {0} + set_component_parameter_value IO_INPUT_DELAY33 {0} + set_component_parameter_value IO_INPUT_DELAY34 {0} + set_component_parameter_value IO_INPUT_DELAY35 {0} + set_component_parameter_value IO_INPUT_DELAY36 {0} + set_component_parameter_value IO_INPUT_DELAY37 {0} + set_component_parameter_value IO_INPUT_DELAY38 {0} + set_component_parameter_value IO_INPUT_DELAY39 {0} + set_component_parameter_value IO_INPUT_DELAY4 {0} + set_component_parameter_value IO_INPUT_DELAY40 {0} + set_component_parameter_value IO_INPUT_DELAY41 {0} + set_component_parameter_value IO_INPUT_DELAY42 {0} + set_component_parameter_value IO_INPUT_DELAY43 {0} + set_component_parameter_value IO_INPUT_DELAY44 {0} + set_component_parameter_value IO_INPUT_DELAY45 {0} + set_component_parameter_value IO_INPUT_DELAY46 {0} + set_component_parameter_value IO_INPUT_DELAY47 {0} + set_component_parameter_value IO_INPUT_DELAY5 {0} + set_component_parameter_value IO_INPUT_DELAY6 {0} + set_component_parameter_value IO_INPUT_DELAY7 {0} + set_component_parameter_value IO_INPUT_DELAY8 {0} + set_component_parameter_value IO_INPUT_DELAY9 {0} + set_component_parameter_value IO_OUTPUT_DELAY0 {0} + set_component_parameter_value IO_OUTPUT_DELAY1 {0} + set_component_parameter_value IO_OUTPUT_DELAY10 {0} + set_component_parameter_value IO_OUTPUT_DELAY11 {0} + set_component_parameter_value IO_OUTPUT_DELAY12 {0} + set_component_parameter_value IO_OUTPUT_DELAY13 {0} + set_component_parameter_value IO_OUTPUT_DELAY14 {0} + set_component_parameter_value IO_OUTPUT_DELAY15 {0} + set_component_parameter_value IO_OUTPUT_DELAY16 {0} + set_component_parameter_value IO_OUTPUT_DELAY17 {0} + set_component_parameter_value IO_OUTPUT_DELAY18 {0} + set_component_parameter_value IO_OUTPUT_DELAY19 {0} + set_component_parameter_value IO_OUTPUT_DELAY2 {0} + set_component_parameter_value IO_OUTPUT_DELAY20 {0} + set_component_parameter_value IO_OUTPUT_DELAY21 {0} + set_component_parameter_value IO_OUTPUT_DELAY22 {0} + set_component_parameter_value IO_OUTPUT_DELAY23 {0} + set_component_parameter_value IO_OUTPUT_DELAY24 {0} + set_component_parameter_value IO_OUTPUT_DELAY25 {0} + set_component_parameter_value IO_OUTPUT_DELAY26 {0} + set_component_parameter_value IO_OUTPUT_DELAY27 {0} + set_component_parameter_value IO_OUTPUT_DELAY28 {0} + set_component_parameter_value IO_OUTPUT_DELAY29 {0} + set_component_parameter_value IO_OUTPUT_DELAY3 {0} + set_component_parameter_value IO_OUTPUT_DELAY30 {0} + set_component_parameter_value IO_OUTPUT_DELAY31 {0} + set_component_parameter_value IO_OUTPUT_DELAY32 {0} + set_component_parameter_value IO_OUTPUT_DELAY33 {0} + set_component_parameter_value IO_OUTPUT_DELAY34 {0} + set_component_parameter_value IO_OUTPUT_DELAY35 {0} + set_component_parameter_value IO_OUTPUT_DELAY36 {0} + set_component_parameter_value IO_OUTPUT_DELAY37 {0} + set_component_parameter_value IO_OUTPUT_DELAY38 {0} + set_component_parameter_value IO_OUTPUT_DELAY39 {0} + set_component_parameter_value IO_OUTPUT_DELAY4 {0} + set_component_parameter_value IO_OUTPUT_DELAY40 {0} + set_component_parameter_value IO_OUTPUT_DELAY41 {0} + set_component_parameter_value IO_OUTPUT_DELAY42 {0} + set_component_parameter_value IO_OUTPUT_DELAY43 {0} + set_component_parameter_value IO_OUTPUT_DELAY44 {0} + set_component_parameter_value IO_OUTPUT_DELAY45 {0} + set_component_parameter_value IO_OUTPUT_DELAY46 {0} + set_component_parameter_value IO_OUTPUT_DELAY47 {0} + set_component_parameter_value IO_OUTPUT_DELAY5 {0} + set_component_parameter_value IO_OUTPUT_DELAY6 {0} + set_component_parameter_value IO_OUTPUT_DELAY7 {0} + set_component_parameter_value IO_OUTPUT_DELAY8 {0} + set_component_parameter_value IO_OUTPUT_DELAY9 {0} + set_component_parameter_value IPXACT_Enable {0} + set_component_parameter_value L3_MAIN_FREE_CLK {400} + set_component_parameter_value L4_SYS_FREE_CLK {2} + set_component_parameter_value LWH2F_ADDRESS_WIDTH {21} + set_component_parameter_value LWH2F_Enable {1} + set_component_parameter_value MAINPLL_FDIV_EN {0} + set_component_parameter_value MANUAL_CLK_EMACA_SOURCE {0} + set_component_parameter_value MANUAL_CLK_EMACB_SOURCE {1} + set_component_parameter_value MANUAL_CLK_EMAC_PTP_SOURCE {1} + set_component_parameter_value MANUAL_CLK_GPIO_SOURCE {1} + set_component_parameter_value MANUAL_CLK_MPU_SOURCE {0} + set_component_parameter_value MANUAL_CLK_NOC_SOURCE {1} + set_component_parameter_value MANUAL_CLK_PSI_SOURCE {0} + set_component_parameter_value MANUAL_CLK_S2F_USER0_SOURCE {0} + set_component_parameter_value MANUAL_CLK_S2F_USER1_SOURCE {0} + set_component_parameter_value MANUAL_CLK_SDMMC_SOURCE {1} + set_component_parameter_value MANUAL_CLK_SRC_EN {0} + set_component_parameter_value MANUAL_MAINPLL_C0 {1000.0} + set_component_parameter_value MANUAL_MAINPLL_C2 {500.0} + set_component_parameter_value MANUAL_MAINPLL_C3 {200.0} + set_component_parameter_value MANUAL_MAINPLL_CFREQ_EN {0} + set_component_parameter_value MANUAL_PERPLL_C0 {1200.0} + set_component_parameter_value MANUAL_PERPLL_C2 {480.0} + set_component_parameter_value MANUAL_PERPLL_C3 {200.0} + set_component_parameter_value MANUAL_PERPLL_CFREQ_EN {0} + set_component_parameter_value MPU_EVENTS_Enable {1} + set_component_parameter_value Mem_Interleave_Enable {0} + set_component_parameter_value NAND_Mode {N/A} + set_component_parameter_value NAND_PinMuxing {Unused} + set_component_parameter_value NOCDIV_CS_ATCLK {0} + set_component_parameter_value NOCDIV_CS_PDBGCLK {2} + set_component_parameter_value NOCDIV_CS_TRACECLK {0} + set_component_parameter_value NOCDIV_L4MAINCLK {0} + set_component_parameter_value NOCDIV_L4MPCLK {1} + set_component_parameter_value NOCDIV_L4SPCLK {2} + set_component_parameter_value OVERIDE_PERI_PLL {0} + set_component_parameter_value PERI_PLL_MANUAL_VCO_FREQ {2000} + set_component_parameter_value PERPLL_FDIV_EN {0} + set_component_parameter_value PLL_CLK0 {Unused} + set_component_parameter_value PLL_CLK1 {Unused} + set_component_parameter_value PLL_CLK2 {Unused} + set_component_parameter_value PLL_CLK3 {Unused} + set_component_parameter_value PLL_CLK4 {Unused} + set_component_parameter_value PSI_CLK_FREQ {500} + set_component_parameter_value RUN_INTERNAL_BUILD_CHECKS {0} + set_component_parameter_value S2FINTERRUPT_CLOCKPERIPHERAL_Enable {0} + set_component_parameter_value S2FINTERRUPT_DMA_Enable {0} + set_component_parameter_value S2FINTERRUPT_EMAC0_Enable {0} + set_component_parameter_value S2FINTERRUPT_EMAC1_Enable {0} + set_component_parameter_value S2FINTERRUPT_EMAC2_Enable {0} + set_component_parameter_value S2FINTERRUPT_GPIO_Enable {0} + set_component_parameter_value S2FINTERRUPT_I2C0_Enable {0} + set_component_parameter_value S2FINTERRUPT_I2C1_Enable {0} + set_component_parameter_value S2FINTERRUPT_I2CEMAC0_Enable {0} + set_component_parameter_value S2FINTERRUPT_I2CEMAC1_Enable {0} + set_component_parameter_value S2FINTERRUPT_I2CEMAC2_Enable {0} + set_component_parameter_value S2FINTERRUPT_L4TIMER_Enable {0} + set_component_parameter_value S2FINTERRUPT_NAND_Enable {0} + set_component_parameter_value S2FINTERRUPT_SDMMC_Enable {1} + set_component_parameter_value S2FINTERRUPT_SPIM0_Enable {0} + set_component_parameter_value S2FINTERRUPT_SPIM1_Enable {0} + set_component_parameter_value S2FINTERRUPT_SPIS0_Enable {0} + set_component_parameter_value S2FINTERRUPT_SPIS1_Enable {0} + set_component_parameter_value S2FINTERRUPT_SYSTEMMANAGER_Enable {0} + set_component_parameter_value S2FINTERRUPT_SYSTIMER_Enable {0} + set_component_parameter_value S2FINTERRUPT_UART0_Enable {0} + set_component_parameter_value S2FINTERRUPT_UART1_Enable {0} + set_component_parameter_value S2FINTERRUPT_USB0_Enable {0} + set_component_parameter_value S2FINTERRUPT_USB1_Enable {0} + set_component_parameter_value S2FINTERRUPT_WATCHDOG_Enable {0} + set_component_parameter_value S2F_ADDRESS_WIDTH {32} + set_component_parameter_value S2F_Width {2} + set_component_parameter_value SDMMC_Mode {4-bit} + set_component_parameter_value SDMMC_PinMuxing {IO} + set_component_parameter_value SDMMC_REF_CLK {200} + set_component_parameter_value SMMU_rsb_sid_const {0} + set_component_parameter_value SMMU_rsb_ssd_const {0} + set_component_parameter_value SMMU_sid_config {0} + set_component_parameter_value SMMU_ssd_config {0} + set_component_parameter_value SMMU_wsb_sid_const {0} + set_component_parameter_value SMMU_wsb_ssd_const {0} + set_component_parameter_value SPIM0_Mode {N/A} + set_component_parameter_value SPIM0_PinMuxing {Unused} + set_component_parameter_value SPIM1_Mode {N/A} + set_component_parameter_value SPIM1_PinMuxing {Unused} + set_component_parameter_value SPIS0_Mode {N/A} + set_component_parameter_value SPIS0_PinMuxing {Unused} + set_component_parameter_value SPIS1_Mode {N/A} + set_component_parameter_value SPIS1_PinMuxing {Unused} + set_component_parameter_value STM_Enable {0} + set_component_parameter_value TESTIOCTRL_DEBUGCLKSEL {16} + set_component_parameter_value TESTIOCTRL_MAINCLKSEL {8} + set_component_parameter_value TESTIOCTRL_PERICLKSEL {8} + set_component_parameter_value TEST_Enable {0} + set_component_parameter_value TPIU_Select {HPS Clock Manager} + set_component_parameter_value TRACE_Mode {N/A} + set_component_parameter_value TRACE_PinMuxing {Unused} + set_component_parameter_value UART0_Mode {No_flow_control} + set_component_parameter_value UART0_PinMuxing {IO} + set_component_parameter_value UART1_Mode {N/A} + set_component_parameter_value UART1_PinMuxing {Unused} + set_component_parameter_value USB0_Mode {N/A} + set_component_parameter_value USB0_PinMuxing {Unused} + set_component_parameter_value USB1_Mode {N/A} + set_component_parameter_value USB1_PinMuxing {Unused} + set_component_parameter_value USE_DEFAULT_MPU_CLK {0} + set_component_parameter_value W_RESET_ACTION {0} + set_component_parameter_value eosc1_clk_mhz {25.0} + set_component_parameter_value watchdog_reset {0} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation hps + remove_instantiation_interfaces_and_ports + add_instantiation_interface h2f_mpu_events conduit INPUT + set_instantiation_interface_parameter_value h2f_mpu_events associatedClock {} + set_instantiation_interface_parameter_value h2f_mpu_events associatedReset {} + set_instantiation_interface_parameter_value h2f_mpu_events prSafe {false} + add_instantiation_interface_port h2f_mpu_events h2f_mpu_fpga_eventi fpga_eventi 1 STD_LOGIC Input + add_instantiation_interface_port h2f_mpu_events h2f_mpu_fpga_evento fpga_evento 1 STD_LOGIC Output + add_instantiation_interface_port h2f_mpu_events h2f_mpu_fpga_standbywfe fpga_standbywfe 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_mpu_events h2f_mpu_fpga_standbywfi fpga_standbywfi 4 STD_LOGIC_VECTOR Output + add_instantiation_interface hps_emif conduit INPUT + set_instantiation_interface_parameter_value hps_emif associatedClock {} + set_instantiation_interface_parameter_value hps_emif associatedReset {} + set_instantiation_interface_parameter_value hps_emif prSafe {false} + add_instantiation_interface_port hps_emif hps_emif_emif_to_hps emif_to_hps 4096 STD_LOGIC_VECTOR Input + add_instantiation_interface_port hps_emif hps_emif_hps_to_emif hps_to_emif 4096 STD_LOGIC_VECTOR Output + add_instantiation_interface_port hps_emif hps_emif_emif_to_gp emif_to_gp 1 STD_LOGIC Input + add_instantiation_interface_port hps_emif hps_emif_gp_to_emif gp_to_emif 2 STD_LOGIC_VECTOR Output + add_instantiation_interface h2f_sdmmc_interrupt interrupt INPUT + set_instantiation_interface_parameter_value h2f_sdmmc_interrupt associatedAddressablePoint {} + set_instantiation_interface_parameter_value h2f_sdmmc_interrupt associatedClock {} + set_instantiation_interface_parameter_value h2f_sdmmc_interrupt associatedReset {} + set_instantiation_interface_parameter_value h2f_sdmmc_interrupt bridgedReceiverOffset {0} + set_instantiation_interface_parameter_value h2f_sdmmc_interrupt bridgesToReceiver {} + set_instantiation_interface_parameter_value h2f_sdmmc_interrupt irqScheme {NONE} + add_instantiation_interface_port h2f_sdmmc_interrupt s2f_sdmmc_irq irq 1 STD_LOGIC Output + add_instantiation_interface hps_io conduit INPUT + set_instantiation_interface_parameter_value hps_io associatedClock {} + set_instantiation_interface_parameter_value hps_io associatedReset {} + set_instantiation_interface_parameter_value hps_io prSafe {false} + add_instantiation_interface_port hps_io EMAC0_TX_CLK EMAC0_TX_CLK 1 STD_LOGIC Output + add_instantiation_interface_port hps_io EMAC0_TXD0 EMAC0_TXD0 1 STD_LOGIC Output + add_instantiation_interface_port hps_io EMAC0_TXD1 EMAC0_TXD1 1 STD_LOGIC Output + add_instantiation_interface_port hps_io EMAC0_TXD2 EMAC0_TXD2 1 STD_LOGIC Output + add_instantiation_interface_port hps_io EMAC0_TXD3 EMAC0_TXD3 1 STD_LOGIC Output + add_instantiation_interface_port hps_io EMAC0_RX_CTL EMAC0_RX_CTL 1 STD_LOGIC Input + add_instantiation_interface_port hps_io EMAC0_TX_CTL EMAC0_TX_CTL 1 STD_LOGIC Output + add_instantiation_interface_port hps_io EMAC0_RX_CLK EMAC0_RX_CLK 1 STD_LOGIC Input + add_instantiation_interface_port hps_io EMAC0_RXD0 EMAC0_RXD0 1 STD_LOGIC Input + add_instantiation_interface_port hps_io EMAC0_RXD1 EMAC0_RXD1 1 STD_LOGIC Input + add_instantiation_interface_port hps_io EMAC0_RXD2 EMAC0_RXD2 1 STD_LOGIC Input + add_instantiation_interface_port hps_io EMAC0_RXD3 EMAC0_RXD3 1 STD_LOGIC Input + add_instantiation_interface_port hps_io EMAC0_MDIO EMAC0_MDIO 1 STD_LOGIC Bidir + add_instantiation_interface_port hps_io EMAC0_MDC EMAC0_MDC 1 STD_LOGIC Output + add_instantiation_interface_port hps_io SDMMC_CMD SDMMC_CMD 1 STD_LOGIC Bidir + add_instantiation_interface_port hps_io SDMMC_D0 SDMMC_D0 1 STD_LOGIC Bidir + add_instantiation_interface_port hps_io SDMMC_D1 SDMMC_D1 1 STD_LOGIC Bidir + add_instantiation_interface_port hps_io SDMMC_D2 SDMMC_D2 1 STD_LOGIC Bidir + add_instantiation_interface_port hps_io SDMMC_D3 SDMMC_D3 1 STD_LOGIC Bidir + add_instantiation_interface_port hps_io SDMMC_CCLK SDMMC_CCLK 1 STD_LOGIC Output + add_instantiation_interface_port hps_io UART0_RX UART0_RX 1 STD_LOGIC Input + add_instantiation_interface_port hps_io UART0_TX UART0_TX 1 STD_LOGIC Output + add_instantiation_interface_port hps_io I2C1_SDA I2C1_SDA 1 STD_LOGIC Bidir + add_instantiation_interface_port hps_io I2C1_SCL I2C1_SCL 1 STD_LOGIC Bidir + add_instantiation_interface_port hps_io gpio1_io0 gpio1_io0 1 STD_LOGIC Bidir + add_instantiation_interface_port hps_io jtag_tck jtag_tck 1 STD_LOGIC Input + add_instantiation_interface_port hps_io jtag_tms jtag_tms 1 STD_LOGIC Input + add_instantiation_interface_port hps_io jtag_tdo jtag_tdo 1 STD_LOGIC Output + add_instantiation_interface_port hps_io jtag_tdi jtag_tdi 1 STD_LOGIC Input + add_instantiation_interface_port hps_io hps_osc_clk hps_osc_clk 1 STD_LOGIC Input + add_instantiation_interface h2f_reset reset OUTPUT + set_instantiation_interface_parameter_value h2f_reset associatedClock {} + set_instantiation_interface_parameter_value h2f_reset associatedDirectReset {} + set_instantiation_interface_parameter_value h2f_reset associatedResetSinks {none} + set_instantiation_interface_parameter_value h2f_reset synchronousEdges {NONE} + add_instantiation_interface_port h2f_reset h2f_rst reset 1 STD_LOGIC Output + add_instantiation_interface h2f_axi_clock clock INPUT + set_instantiation_interface_parameter_value h2f_axi_clock clockRate {0} + set_instantiation_interface_parameter_value h2f_axi_clock externallyDriven {false} + set_instantiation_interface_parameter_value h2f_axi_clock ptfSchematicName {} + add_instantiation_interface_port h2f_axi_clock h2f_axi_clk clk 1 STD_LOGIC Input + add_instantiation_interface h2f_axi_reset reset INPUT + set_instantiation_interface_parameter_value h2f_axi_reset associatedClock {h2f_axi_clock} + set_instantiation_interface_parameter_value h2f_axi_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port h2f_axi_reset h2f_axi_rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface h2f_axi_master axi4 OUTPUT + set_instantiation_interface_parameter_value h2f_axi_master associatedClock {h2f_axi_clock} + set_instantiation_interface_parameter_value h2f_axi_master associatedReset {h2f_axi_reset} + set_instantiation_interface_parameter_value h2f_axi_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value h2f_axi_master issuesFIXEDBursts {true} + set_instantiation_interface_parameter_value h2f_axi_master issuesINCRBursts {true} + set_instantiation_interface_parameter_value h2f_axi_master issuesWRAPBursts {true} + set_instantiation_interface_parameter_value h2f_axi_master maximumOutstandingReads {1} + set_instantiation_interface_parameter_value h2f_axi_master maximumOutstandingTransactions {1} + set_instantiation_interface_parameter_value h2f_axi_master maximumOutstandingWrites {1} + set_instantiation_interface_parameter_value h2f_axi_master poison {false} + set_instantiation_interface_parameter_value h2f_axi_master readIssuingCapability {16} + set_instantiation_interface_parameter_value h2f_axi_master traceSignals {false} + set_instantiation_interface_parameter_value h2f_axi_master trustzoneAware {true} + set_instantiation_interface_parameter_value h2f_axi_master uniqueIdSupport {false} + set_instantiation_interface_parameter_value h2f_axi_master wakeupSignals {false} + set_instantiation_interface_parameter_value h2f_axi_master writeIssuingCapability {16} + add_instantiation_interface_port h2f_axi_master h2f_AWID awid 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_AWADDR awaddr 32 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_AWLEN awlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_AWSIZE awsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_AWBURST awburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_AWLOCK awlock 1 STD_LOGIC Output + add_instantiation_interface_port h2f_axi_master h2f_AWCACHE awcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_AWPROT awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_AWVALID awvalid 1 STD_LOGIC Output + add_instantiation_interface_port h2f_axi_master h2f_AWREADY awready 1 STD_LOGIC Input + add_instantiation_interface_port h2f_axi_master h2f_WDATA wdata 64 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_WSTRB wstrb 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_WLAST wlast 1 STD_LOGIC Output + add_instantiation_interface_port h2f_axi_master h2f_WVALID wvalid 1 STD_LOGIC Output + add_instantiation_interface_port h2f_axi_master h2f_WREADY wready 1 STD_LOGIC Input + add_instantiation_interface_port h2f_axi_master h2f_BID bid 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_axi_master h2f_BRESP bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_axi_master h2f_BVALID bvalid 1 STD_LOGIC Input + add_instantiation_interface_port h2f_axi_master h2f_BREADY bready 1 STD_LOGIC Output + add_instantiation_interface_port h2f_axi_master h2f_ARID arid 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_ARADDR araddr 32 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_ARLEN arlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_ARSIZE arsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_ARBURST arburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_ARLOCK arlock 1 STD_LOGIC Output + add_instantiation_interface_port h2f_axi_master h2f_ARCACHE arcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_ARPROT arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_axi_master h2f_ARVALID arvalid 1 STD_LOGIC Output + add_instantiation_interface_port h2f_axi_master h2f_ARREADY arready 1 STD_LOGIC Input + add_instantiation_interface_port h2f_axi_master h2f_RID rid 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_axi_master h2f_RDATA rdata 64 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_axi_master h2f_RRESP rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_axi_master h2f_RLAST rlast 1 STD_LOGIC Input + add_instantiation_interface_port h2f_axi_master h2f_RVALID rvalid 1 STD_LOGIC Input + add_instantiation_interface_port h2f_axi_master h2f_RREADY rready 1 STD_LOGIC Output + add_instantiation_interface h2f_lw_axi_clock clock INPUT + set_instantiation_interface_parameter_value h2f_lw_axi_clock clockRate {0} + set_instantiation_interface_parameter_value h2f_lw_axi_clock externallyDriven {false} + set_instantiation_interface_parameter_value h2f_lw_axi_clock ptfSchematicName {} + add_instantiation_interface_port h2f_lw_axi_clock h2f_lw_axi_clk clk 1 STD_LOGIC Input + add_instantiation_interface h2f_lw_axi_reset reset INPUT + set_instantiation_interface_parameter_value h2f_lw_axi_reset associatedClock {h2f_lw_axi_clock} + set_instantiation_interface_parameter_value h2f_lw_axi_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port h2f_lw_axi_reset h2f_lw_axi_rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface h2f_lw_axi_master axi4 OUTPUT + set_instantiation_interface_parameter_value h2f_lw_axi_master associatedClock {h2f_lw_axi_clock} + set_instantiation_interface_parameter_value h2f_lw_axi_master associatedReset {h2f_lw_axi_reset} + set_instantiation_interface_parameter_value h2f_lw_axi_master combinedIssuingCapability {16} + set_instantiation_interface_parameter_value h2f_lw_axi_master issuesFIXEDBursts {true} + set_instantiation_interface_parameter_value h2f_lw_axi_master issuesINCRBursts {true} + set_instantiation_interface_parameter_value h2f_lw_axi_master issuesWRAPBursts {true} + set_instantiation_interface_parameter_value h2f_lw_axi_master maximumOutstandingReads {1} + set_instantiation_interface_parameter_value h2f_lw_axi_master maximumOutstandingTransactions {1} + set_instantiation_interface_parameter_value h2f_lw_axi_master maximumOutstandingWrites {1} + set_instantiation_interface_parameter_value h2f_lw_axi_master poison {false} + set_instantiation_interface_parameter_value h2f_lw_axi_master readIssuingCapability {16} + set_instantiation_interface_parameter_value h2f_lw_axi_master traceSignals {false} + set_instantiation_interface_parameter_value h2f_lw_axi_master trustzoneAware {true} + set_instantiation_interface_parameter_value h2f_lw_axi_master uniqueIdSupport {false} + set_instantiation_interface_parameter_value h2f_lw_axi_master wakeupSignals {false} + set_instantiation_interface_parameter_value h2f_lw_axi_master writeIssuingCapability {16} + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWID awid 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWADDR awaddr 21 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWLEN awlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWSIZE awsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWBURST awburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWLOCK awlock 1 STD_LOGIC Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWCACHE awcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWPROT awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWVALID awvalid 1 STD_LOGIC Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_AWREADY awready 1 STD_LOGIC Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_WDATA wdata 32 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_WSTRB wstrb 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_WLAST wlast 1 STD_LOGIC Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_WVALID wvalid 1 STD_LOGIC Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_WREADY wready 1 STD_LOGIC Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_BID bid 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_BRESP bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_BVALID bvalid 1 STD_LOGIC Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_BREADY bready 1 STD_LOGIC Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARID arid 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARADDR araddr 21 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARLEN arlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARSIZE arsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARBURST arburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARLOCK arlock 1 STD_LOGIC Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARCACHE arcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARPROT arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARVALID arvalid 1 STD_LOGIC Output + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_ARREADY arready 1 STD_LOGIC Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_RID rid 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_RDATA rdata 32 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_RRESP rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_RLAST rlast 1 STD_LOGIC Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_RVALID rvalid 1 STD_LOGIC Input + add_instantiation_interface_port h2f_lw_axi_master h2f_lw_RREADY rready 1 STD_LOGIC Output + add_instantiation_interface f2h_axi_clock clock INPUT + set_instantiation_interface_parameter_value f2h_axi_clock clockRate {0} + set_instantiation_interface_parameter_value f2h_axi_clock externallyDriven {false} + set_instantiation_interface_parameter_value f2h_axi_clock ptfSchematicName {} + add_instantiation_interface_port f2h_axi_clock f2h_axi_clk clk 1 STD_LOGIC Input + add_instantiation_interface f2h_axi_reset reset INPUT + set_instantiation_interface_parameter_value f2h_axi_reset associatedClock {f2h_axi_clock} + set_instantiation_interface_parameter_value f2h_axi_reset synchronousEdges {DEASSERT} + add_instantiation_interface_port f2h_axi_reset f2h_axi_rst_n reset_n 1 STD_LOGIC Input + add_instantiation_interface f2h_axi_slave acelite INPUT + set_instantiation_interface_parameter_value f2h_axi_slave associatedClock {f2h_axi_clock} + set_instantiation_interface_parameter_value f2h_axi_slave associatedReset {f2h_axi_reset} + set_instantiation_interface_parameter_value f2h_axi_slave bridgesToMaster {} + set_instantiation_interface_parameter_value f2h_axi_slave combinedAcceptanceCapability {16} + set_instantiation_interface_parameter_value f2h_axi_slave dfhFeatureGuid {0} + set_instantiation_interface_parameter_value f2h_axi_slave dfhFeatureId {35} + set_instantiation_interface_parameter_value f2h_axi_slave dfhFeatureMajorVersion {0} + set_instantiation_interface_parameter_value f2h_axi_slave dfhFeatureMinorVersion {0} + set_instantiation_interface_parameter_value f2h_axi_slave dfhFeatureType {3} + set_instantiation_interface_parameter_value f2h_axi_slave dfhGroupId {0} + set_instantiation_interface_parameter_value f2h_axi_slave dfhParameterData {} + set_instantiation_interface_parameter_value f2h_axi_slave dfhParameterDataLength {} + set_instantiation_interface_parameter_value f2h_axi_slave dfhParameterId {} + set_instantiation_interface_parameter_value f2h_axi_slave dfhParameterName {} + set_instantiation_interface_parameter_value f2h_axi_slave dfhParameterVersion {} + set_instantiation_interface_parameter_value f2h_axi_slave maximumOutstandingReads {1} + set_instantiation_interface_parameter_value f2h_axi_slave maximumOutstandingTransactions {1} + set_instantiation_interface_parameter_value f2h_axi_slave maximumOutstandingWrites {1} + set_instantiation_interface_parameter_value f2h_axi_slave poison {false} + set_instantiation_interface_parameter_value f2h_axi_slave readAcceptanceCapability {16} + set_instantiation_interface_parameter_value f2h_axi_slave readDataReorderingDepth {8} + set_instantiation_interface_parameter_value f2h_axi_slave traceSignals {false} + set_instantiation_interface_parameter_value f2h_axi_slave trustzoneAware {true} + set_instantiation_interface_parameter_value f2h_axi_slave uniqueIdSupport {false} + set_instantiation_interface_parameter_value f2h_axi_slave wakeupSignals {false} + set_instantiation_interface_parameter_value f2h_axi_slave writeAcceptanceCapability {16} + add_instantiation_interface_port f2h_axi_slave f2h_AWID awid 5 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWADDR awaddr 32 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWLEN awlen 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWSIZE awsize 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWBURST awburst 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWLOCK awlock 1 STD_LOGIC Input + add_instantiation_interface_port f2h_axi_slave f2h_AWCACHE awcache 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWPROT awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWVALID awvalid 1 STD_LOGIC Input + add_instantiation_interface_port f2h_axi_slave f2h_AWREADY awready 1 STD_LOGIC Output + add_instantiation_interface_port f2h_axi_slave f2h_AWQOS awqos 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_WDATA wdata 128 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_WSTRB wstrb 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_WLAST wlast 1 STD_LOGIC Input + add_instantiation_interface_port f2h_axi_slave f2h_WVALID wvalid 1 STD_LOGIC Input + add_instantiation_interface_port f2h_axi_slave f2h_WREADY wready 1 STD_LOGIC Output + add_instantiation_interface_port f2h_axi_slave f2h_BID bid 5 STD_LOGIC_VECTOR Output + add_instantiation_interface_port f2h_axi_slave f2h_BRESP bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port f2h_axi_slave f2h_BVALID bvalid 1 STD_LOGIC Output + add_instantiation_interface_port f2h_axi_slave f2h_BREADY bready 1 STD_LOGIC Input + add_instantiation_interface_port f2h_axi_slave f2h_ARID arid 5 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARADDR araddr 32 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARLEN arlen 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARSIZE arsize 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARBURST arburst 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARLOCK arlock 1 STD_LOGIC Input + add_instantiation_interface_port f2h_axi_slave f2h_ARCACHE arcache 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARPROT arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARVALID arvalid 1 STD_LOGIC Input + add_instantiation_interface_port f2h_axi_slave f2h_ARREADY arready 1 STD_LOGIC Output + add_instantiation_interface_port f2h_axi_slave f2h_ARQOS arqos 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_RID rid 5 STD_LOGIC_VECTOR Output + add_instantiation_interface_port f2h_axi_slave f2h_RDATA rdata 128 STD_LOGIC_VECTOR Output + add_instantiation_interface_port f2h_axi_slave f2h_RRESP rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port f2h_axi_slave f2h_RLAST rlast 1 STD_LOGIC Output + add_instantiation_interface_port f2h_axi_slave f2h_RVALID rvalid 1 STD_LOGIC Output + add_instantiation_interface_port f2h_axi_slave f2h_RREADY rready 1 STD_LOGIC Input + add_instantiation_interface_port f2h_axi_slave f2h_AWDOMAIN awdomain 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWBAR awbar 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARDOMAIN ardomain 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARBAR arbar 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARSNOOP arsnoop 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWSNOOP awsnoop 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_ARUSER aruser 23 STD_LOGIC_VECTOR Input + add_instantiation_interface_port f2h_axi_slave f2h_AWUSER awuser 23 STD_LOGIC_VECTOR Input + save_instantiation + add_component hps_emif ip/system/hps_emif.ip altera_emif_fm_hps hps_emif 2.7.4 + load_component hps_emif + set_component_parameter_value BOARD_DDR3_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR3_DQS_TO_CK_SKEW_NS {0.02} + set_component_parameter_value BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED {0} + set_component_parameter_value BOARD_DDR3_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDR3_MAX_DQS_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_DDR3_SKEW_BETWEEN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR3_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDR3_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR3_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_RCLK_SLEW_RATE {5.0} + set_component_parameter_value BOARD_DDR3_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_RDATA_SLEW_RATE {2.5} + set_component_parameter_value BOARD_DDR3_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR3_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR3_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDR3_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_DDR3_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_DDR4_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR4_DQS_TO_CK_SKEW_NS {0.02} + set_component_parameter_value BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED {0} + set_component_parameter_value BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED {0} + set_component_parameter_value BOARD_DDR4_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDR4_MAX_DQS_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_DDR4_SKEW_BETWEEN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDR4_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDR4_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR4_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_RCLK_SLEW_RATE {8.0} + set_component_parameter_value BOARD_DDR4_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_RDATA_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR4_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDR4_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDR4_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDR4_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_DDR4_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_DDRT_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_DDRT_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDRT_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDRT_DQS_TO_CK_SKEW_NS {0.02} + set_component_parameter_value BOARD_DDRT_IS_SKEW_WITHIN_AC_DESKEWED {0} + set_component_parameter_value BOARD_DDRT_IS_SKEW_WITHIN_DQS_DESKEWED {1} + set_component_parameter_value BOARD_DDRT_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDRT_MAX_DQS_DELAY_NS {0.6} + set_component_parameter_value BOARD_DDRT_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_DDRT_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDRT_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_DDRT_SKEW_BETWEEN_DQS_NS {0.02} + set_component_parameter_value BOARD_DDRT_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDRT_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDRT_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_RCLK_SLEW_RATE {8.0} + set_component_parameter_value BOARD_DDRT_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_RDATA_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDRT_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_DDRT_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_DDRT_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_DDRT_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_DDRT_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_LPDDR3_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_DQS_TO_CK_SKEW_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED {0} + set_component_parameter_value BOARD_LPDDR3_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_LPDDR3_MAX_DQS_DELAY_NS {0.6} + set_component_parameter_value BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS {0.02} + set_component_parameter_value BOARD_LPDDR3_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_LPDDR3_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_LPDDR3_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_RCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_LPDDR3_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_RDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_LPDDR3_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_LPDDR3_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_LPDDR3_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_QDR2_AC_TO_K_SKEW_NS {0.0} + set_component_parameter_value BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_QDR2_BRD_SKEW_WITHIN_D_NS {0.02} + set_component_parameter_value BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS {0.02} + set_component_parameter_value BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED {0} + set_component_parameter_value BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED {0} + set_component_parameter_value BOARD_QDR2_MAX_K_DELAY_NS {0.6} + set_component_parameter_value BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS {0.02} + set_component_parameter_value BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS {0.02} + set_component_parameter_value BOARD_QDR2_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR2_USER_K_SLEW_RATE {4.0} + set_component_parameter_value BOARD_QDR2_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_RCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_QDR2_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_RDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR2_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR2_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR2_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_QDR2_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_QDR4_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS {0.02} + set_component_parameter_value BOARD_QDR4_DK_TO_CK_SKEW_NS {-0.02} + set_component_parameter_value BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED {1} + set_component_parameter_value BOARD_QDR4_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_QDR4_MAX_DK_DELAY_NS {0.6} + set_component_parameter_value BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS {0.02} + set_component_parameter_value BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_QDR4_SKEW_BETWEEN_DK_NS {0.02} + set_component_parameter_value BOARD_QDR4_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR4_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_QDR4_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_RCLK_SLEW_RATE {5.0} + set_component_parameter_value BOARD_QDR4_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_RDATA_SLEW_RATE {2.5} + set_component_parameter_value BOARD_QDR4_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_QDR4_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_QDR4_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_QDR4_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_QDR4_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value BOARD_RLD3_AC_TO_CK_SKEW_NS {0.0} + set_component_parameter_value BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS {0.02} + set_component_parameter_value BOARD_RLD3_DK_TO_CK_SKEW_NS {-0.02} + set_component_parameter_value BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED {1} + set_component_parameter_value BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED {0} + set_component_parameter_value BOARD_RLD3_MAX_CK_DELAY_NS {0.6} + set_component_parameter_value BOARD_RLD3_MAX_DK_DELAY_NS {0.6} + set_component_parameter_value BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS {0.02} + set_component_parameter_value BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS {0.02} + set_component_parameter_value BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS {0.05} + set_component_parameter_value BOARD_RLD3_SKEW_BETWEEN_DK_NS {0.02} + set_component_parameter_value BOARD_RLD3_USER_AC_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_AC_SLEW_RATE {2.0} + set_component_parameter_value BOARD_RLD3_USER_CK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_RLD3_USER_RCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_RCLK_SLEW_RATE {7.0} + set_component_parameter_value BOARD_RLD3_USER_RDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_RDATA_SLEW_RATE {3.5} + set_component_parameter_value BOARD_RLD3_USER_WCLK_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_WCLK_SLEW_RATE {4.0} + set_component_parameter_value BOARD_RLD3_USER_WDATA_ISI_NS {0.0} + set_component_parameter_value BOARD_RLD3_USER_WDATA_SLEW_RATE {2.0} + set_component_parameter_value BOARD_RLD3_USE_DEFAULT_ISI_VALUES {1} + set_component_parameter_value BOARD_RLD3_USE_DEFAULT_SLEW_RATES {1} + set_component_parameter_value CTRL_DDR3_ADDR_ORDER_ENUM {DDR3_CTRL_ADDR_ORDER_CS_R_B_C} + set_component_parameter_value CTRL_DDR3_AUTO_POWER_DOWN_CYCS {32} + set_component_parameter_value CTRL_DDR3_AUTO_POWER_DOWN_EN {0} + set_component_parameter_value CTRL_DDR3_AUTO_PRECHARGE_EN {0} + set_component_parameter_value CTRL_DDR3_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_DDR3_ECC_AUTO_CORRECTION_EN {0} + set_component_parameter_value CTRL_DDR3_ECC_EN {0} + set_component_parameter_value CTRL_DDR3_ECC_READDATAERROR_EN {1} + set_component_parameter_value CTRL_DDR3_ECC_STATUS_EN {0} + set_component_parameter_value CTRL_DDR3_MMR_EN {0} + set_component_parameter_value CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_REORDER_EN {1} + set_component_parameter_value CTRL_DDR3_SELF_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR3_STARVE_LIMIT {10} + set_component_parameter_value CTRL_DDR3_USER_PRIORITY_EN {0} + set_component_parameter_value CTRL_DDR3_USER_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_ADDR_ORDER_ENUM {DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG} + set_component_parameter_value CTRL_DDR4_AUTO_POWER_DOWN_CYCS {32} + set_component_parameter_value CTRL_DDR4_AUTO_POWER_DOWN_EN {0} + set_component_parameter_value CTRL_DDR4_AUTO_PRECHARGE_EN {0} + set_component_parameter_value CTRL_DDR4_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_ST} + set_component_parameter_value CTRL_DDR4_ECC_AUTO_CORRECTION_EN {1} + set_component_parameter_value CTRL_DDR4_ECC_EN {0} + set_component_parameter_value CTRL_DDR4_ECC_READDATAERROR_EN {0} + set_component_parameter_value CTRL_DDR4_ECC_STATUS_EN {0} + set_component_parameter_value CTRL_DDR4_MAJOR_MODE_EN {0} + set_component_parameter_value CTRL_DDR4_MMR_EN {0} + set_component_parameter_value CTRL_DDR4_POST_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR4_POST_REFRESH_LOWER_LIMIT {0} + set_component_parameter_value CTRL_DDR4_POST_REFRESH_UPPER_LIMIT {2} + set_component_parameter_value CTRL_DDR4_PRE_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR4_PRE_REFRESH_UPPER_LIMIT {1} + set_component_parameter_value CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_REORDER_EN {1} + set_component_parameter_value CTRL_DDR4_SELF_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR4_STARVE_LIMIT {10} + set_component_parameter_value CTRL_DDR4_USER_PRIORITY_EN {0} + set_component_parameter_value CTRL_DDR4_USER_REFRESH_EN {0} + set_component_parameter_value CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_ADDR_INTERLEAVING {COARSE} + set_component_parameter_value CTRL_DDRT_ADDR_ORDER_ENUM {DDRT_CTRL_ADDR_ORDER_CS_R_B_C_BG} + set_component_parameter_value CTRL_DDRT_AUTO_POWER_DOWN_CYCS {32} + set_component_parameter_value CTRL_DDRT_AUTO_POWER_DOWN_EN {0} + set_component_parameter_value CTRL_DDRT_AUTO_PRECHARGE_EN {0} + set_component_parameter_value CTRL_DDRT_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_DDRT_DIMM_DENSITY {128} + set_component_parameter_value CTRL_DDRT_DIMM_VIRAL_FLOW_EN {0} + set_component_parameter_value CTRL_DDRT_ECC_AUTO_CORRECTION_EN {0} + set_component_parameter_value CTRL_DDRT_ECC_EN {0} + set_component_parameter_value CTRL_DDRT_ECC_READDATAERROR_EN {1} + set_component_parameter_value CTRL_DDRT_ECC_STATUS_EN {1} + set_component_parameter_value CTRL_DDRT_ERR_INJECT_EN {0} + set_component_parameter_value CTRL_DDRT_ERR_REPLAY_EN {0} + set_component_parameter_value CTRL_DDRT_EXT_ERR_INJECT_EN {0} + set_component_parameter_value CTRL_DDRT_GNT_TO_GNT_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_GNT_TO_WR_DIFF_CHIP_DELTA_CYCS {1} + set_component_parameter_value CTRL_DDRT_GNT_TO_WR_SAME_CHIP_DELTA_CYCS {1} + set_component_parameter_value CTRL_DDRT_HOST_VIRAL_FLOW_EN {0} + set_component_parameter_value CTRL_DDRT_MMR_EN {0} + set_component_parameter_value CTRL_DDRT_NUM_OF_AXIS_ID {1} + set_component_parameter_value CTRL_DDRT_PARITY_CMD_EN {0} + set_component_parameter_value CTRL_DDRT_PMM_ADR_FLOW_EN {0} + set_component_parameter_value CTRL_DDRT_PMM_WPQ_FLUSH_EN {0} + set_component_parameter_value CTRL_DDRT_POISON_DETECTION_EN {0} + set_component_parameter_value CTRL_DDRT_PORT_AFI_C_WIDTH {2} + set_component_parameter_value CTRL_DDRT_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_REORDER_EN {1} + set_component_parameter_value CTRL_DDRT_SELF_REFRESH_EN {0} + set_component_parameter_value CTRL_DDRT_STARVE_LIMIT {10} + set_component_parameter_value CTRL_DDRT_UPI_EN {0} + set_component_parameter_value CTRL_DDRT_UPI_ID_WIDTH {8} + set_component_parameter_value CTRL_DDRT_USER_PRIORITY_EN {0} + set_component_parameter_value CTRL_DDRT_USER_REFRESH_EN {0} + set_component_parameter_value CTRL_DDRT_WR_ACK_POLICY {POSTED} + set_component_parameter_value CTRL_DDRT_WR_TO_GNT_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_WR_TO_GNT_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_DDRT_ZQ_INTERVAL_MS {3} + set_component_parameter_value CTRL_LPDDR3_ADDR_ORDER_ENUM {LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C} + set_component_parameter_value CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS {32} + set_component_parameter_value CTRL_LPDDR3_AUTO_POWER_DOWN_EN {0} + set_component_parameter_value CTRL_LPDDR3_AUTO_PRECHARGE_EN {0} + set_component_parameter_value CTRL_LPDDR3_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_LPDDR3_MMR_EN {0} + set_component_parameter_value CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_REORDER_EN {1} + set_component_parameter_value CTRL_LPDDR3_SELF_REFRESH_EN {0} + set_component_parameter_value CTRL_LPDDR3_STARVE_LIMIT {10} + set_component_parameter_value CTRL_LPDDR3_USER_PRIORITY_EN {0} + set_component_parameter_value CTRL_LPDDR3_USER_REFRESH_EN {0} + set_component_parameter_value CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS {0} + set_component_parameter_value CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS {0} + set_component_parameter_value CTRL_QDR2_AVL_MAX_BURST_COUNT {4} + set_component_parameter_value CTRL_QDR2_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC {0} + set_component_parameter_value CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC {0} + set_component_parameter_value CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS {0} + set_component_parameter_value CTRL_QDR4_AVL_MAX_BURST_COUNT {4} + set_component_parameter_value CTRL_QDR4_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_QDR4_DEF_RAW_TURNAROUND_DELAY_CYC {4} + set_component_parameter_value CTRL_RLD2_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value CTRL_RLD3_ADDR_ORDER_ENUM {RLD3_CTRL_ADDR_ORDER_CS_R_B_C} + set_component_parameter_value CTRL_RLD3_AVL_PROTOCOL_ENUM {CTRL_AVL_PROTOCOL_MM} + set_component_parameter_value DIAG_ADD_READY_PIPELINE {1} + set_component_parameter_value DIAG_BOARD_DELAY_CONFIG_STR {} + set_component_parameter_value DIAG_DB_RESET_AUTO_RELEASE {avl_release} + set_component_parameter_value DIAG_DDR3_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_DDR3_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_DDR3_CAL_ADDR0 {0} + set_component_parameter_value DIAG_DDR3_CAL_ADDR1 {8} + set_component_parameter_value DIAG_DDR3_CAL_ENABLE_MICRON_AP {0} + set_component_parameter_value DIAG_DDR3_CAL_ENABLE_NON_DES {0} + set_component_parameter_value DIAG_DDR3_CAL_FULL_CAL_ON_RESET {1} + set_component_parameter_value DIAG_DDR3_CA_DESKEW_EN {1} + set_component_parameter_value DIAG_DDR3_CA_LEVEL_EN {1} + set_component_parameter_value DIAG_DDR3_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_DDR3_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_DDR3_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_DDR3_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_DDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_DDR3_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_DDR3_EX_DESIGN_ISSP_EN {0} + set_component_parameter_value DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_DDR3_INTERFACE_ID {0} + set_component_parameter_value DIAG_DDR3_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_DDR3_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_DDR3_SIM_VERBOSE {1} + set_component_parameter_value DIAG_DDR3_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_DDR3_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_DDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_DDR3_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_DDR3_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_DDR3_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_DDR3_USE_TG_HBM {0} + set_component_parameter_value DIAG_DDR4_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_DDR4_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_DDR4_CAL_ADDR0 {0} + set_component_parameter_value DIAG_DDR4_CAL_ADDR1 {8} + set_component_parameter_value DIAG_DDR4_CAL_ENABLE_NON_DES {0} + set_component_parameter_value DIAG_DDR4_CAL_FULL_CAL_ON_RESET {1} + set_component_parameter_value DIAG_DDR4_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_DDR4_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_DDR4_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_DDR4_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_DDR4_EX_DESIGN_ISSP_EN {0} + set_component_parameter_value DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_DDR4_INTERFACE_ID {0} + set_component_parameter_value DIAG_DDR4_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_DDR4_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_DDR4_SIM_VERBOSE {1} + set_component_parameter_value DIAG_DDR4_SKIP_AC_PARITY_CHECK {0} + set_component_parameter_value DIAG_DDR4_SKIP_CA_DESKEW {0} + set_component_parameter_value DIAG_DDR4_SKIP_CA_LEVEL {0} + set_component_parameter_value DIAG_DDR4_SKIP_VREF_CAL {0} + set_component_parameter_value DIAG_DDR4_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_DDR4_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_DDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_DDR4_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_DDR4_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_DDR4_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_DDR4_USE_TG_HBM {0} + set_component_parameter_value DIAG_DDRT_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_DDRT_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_DDRT_CAL_ADDR0 {0} + set_component_parameter_value DIAG_DDRT_CAL_ADDR1 {8} + set_component_parameter_value DIAG_DDRT_CAL_ENABLE_NON_DES {0} + set_component_parameter_value DIAG_DDRT_CAL_FULL_CAL_ON_RESET {1} + set_component_parameter_value DIAG_DDRT_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_DDRT_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_DDRT_EFF_TEST {0} + set_component_parameter_value DIAG_DDRT_ENABLE_DEFAULT_MODE {1} + set_component_parameter_value DIAG_DDRT_ENABLE_DRIVER_MARGINING {0} + set_component_parameter_value DIAG_DDRT_ENABLE_ENHANCED_TESTING {0} + set_component_parameter_value DIAG_DDRT_ENABLE_USER_MODE {0} + set_component_parameter_value DIAG_DDRT_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_DDRT_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_DDRT_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_DDRT_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_DDRT_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_DDRT_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_DDRT_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_DDRT_INTERFACE_ID {0} + set_component_parameter_value DIAG_DDRT_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_DDRT_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_DDRT_SIM_VERBOSE {1} + set_component_parameter_value DIAG_DDRT_SKIP_CA_DESKEW {0} + set_component_parameter_value DIAG_DDRT_SKIP_CA_LEVEL {0} + set_component_parameter_value DIAG_DDRT_SKIP_VREF_CAL {0} + set_component_parameter_value DIAG_DDRT_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_DDRT_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_DDRT_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_DDRT_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_DDRT_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_DDRT_USE_TG_AVL_2 {1} + set_component_parameter_value DIAG_DDRT_USE_TG_HBM {0} + set_component_parameter_value DIAG_ECLIPSE_DEBUG {0} + set_component_parameter_value DIAG_ENABLE_HPS_EMIF_DEBUG {0} + set_component_parameter_value DIAG_ENABLE_JTAG_UART {0} + set_component_parameter_value DIAG_ENABLE_JTAG_UART_HEX {0} + set_component_parameter_value DIAG_EXPORT_PLL_LOCKED {0} + set_component_parameter_value DIAG_EXPORT_PLL_REF_CLK_OUT {0} + set_component_parameter_value DIAG_EXPORT_VJI {0} + set_component_parameter_value DIAG_EXPOSE_DFT_SIGNALS {0} + set_component_parameter_value DIAG_EXPOSE_EARLY_READY {0} + set_component_parameter_value DIAG_EXPOSE_RD_TYPE {0} + set_component_parameter_value DIAG_EXTRA_CONFIGS {} + set_component_parameter_value DIAG_EXT_DOCS {0} + set_component_parameter_value DIAG_EX_DESIGN_ADD_TEST_EMIFS {} + set_component_parameter_value DIAG_EX_DESIGN_SEPARATE_RESETS {0} + set_component_parameter_value DIAG_FAST_SIM_OVERRIDE {FAST_SIM_OVERRIDE_DEFAULT} + set_component_parameter_value DIAG_HMC_HRC {auto} + set_component_parameter_value DIAG_LPDDR3_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_LPDDR3_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_LPDDR3_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_LPDDR3_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_LPDDR3_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_LPDDR3_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_LPDDR3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_LPDDR3_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_LPDDR3_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_LPDDR3_INTERFACE_ID {0} + set_component_parameter_value DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_LPDDR3_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_LPDDR3_SIM_VERBOSE {1} + set_component_parameter_value DIAG_LPDDR3_SKIP_CA_DESKEW {0} + set_component_parameter_value DIAG_LPDDR3_SKIP_CA_LEVEL {0} + set_component_parameter_value DIAG_LPDDR3_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_LPDDR3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_LPDDR3_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_LPDDR3_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_LPDDR3_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_LPDDR3_USE_TG_HBM {0} + set_component_parameter_value DIAG_QDR2_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_QDR2_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_QDR2_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_QDR2_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_QDR2_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_QDR2_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_QDR2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_QDR2_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_QDR2_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_QDR2_INTERFACE_ID {0} + set_component_parameter_value DIAG_QDR2_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_QDR2_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_QDR2_SIM_VERBOSE {1} + set_component_parameter_value DIAG_QDR2_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_QDR2_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_QDR2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_QDR2_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_QDR2_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_QDR2_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_QDR2_USE_TG_HBM {0} + set_component_parameter_value DIAG_QDR4_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_QDR4_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_QDR4_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_QDR4_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_QDR4_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_QDR4_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_QDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_QDR4_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_QDR4_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_QDR4_INTERFACE_ID {0} + set_component_parameter_value DIAG_QDR4_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_QDR4_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_QDR4_SIM_VERBOSE {1} + set_component_parameter_value DIAG_QDR4_SKIP_VREF_CAL {0} + set_component_parameter_value DIAG_QDR4_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_QDR4_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_QDR4_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_QDR4_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_QDR4_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_QDR4_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_QDR4_USE_TG_HBM {0} + set_component_parameter_value DIAG_RLD2_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_RLD2_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_RLD2_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_RLD2_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_RLD2_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_RLD2_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_RLD2_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_RLD2_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_RLD2_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_RLD2_INTERFACE_ID {0} + set_component_parameter_value DIAG_RLD2_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_RLD2_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_RLD2_SIM_VERBOSE {1} + set_component_parameter_value DIAG_RLD2_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_RLD2_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_RLD2_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_RLD2_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_RLD2_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_RLD2_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_RLD2_USE_TG_HBM {0} + set_component_parameter_value DIAG_RLD3_ABSTRACT_PHY {0} + set_component_parameter_value DIAG_RLD3_AC_PARITY_ERR {0} + set_component_parameter_value DIAG_RLD3_CA_DESKEW_EN {1} + set_component_parameter_value DIAG_RLD3_CA_LEVEL_EN {1} + set_component_parameter_value DIAG_RLD3_DISABLE_AFI_P2C_REGISTERS {0} + set_component_parameter_value DIAG_RLD3_EFFICIENCY_MONITOR {EFFMON_MODE_DISABLED} + set_component_parameter_value DIAG_RLD3_ENABLE_DEFAULT_MODE {0} + set_component_parameter_value DIAG_RLD3_ENABLE_USER_MODE {1} + set_component_parameter_value DIAG_RLD3_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN {1} + set_component_parameter_value DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER {0} + set_component_parameter_value DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE {CAL_DEBUG_EXPORT_MODE_DISABLED} + set_component_parameter_value DIAG_RLD3_EXPORT_TG_CFG_AVALON_SLAVE {TG_CFG_AMM_EXPORT_MODE_JTAG} + set_component_parameter_value DIAG_RLD3_EX_DESIGN_ISSP_EN {1} + set_component_parameter_value DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES {1} + set_component_parameter_value DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS {1} + set_component_parameter_value DIAG_RLD3_INTERFACE_ID {0} + set_component_parameter_value DIAG_RLD3_SEPARATE_READ_WRITE_ITFS {0} + set_component_parameter_value DIAG_RLD3_SIM_CAL_MODE_ENUM {SIM_CAL_MODE_SKIP} + set_component_parameter_value DIAG_RLD3_SIM_VERBOSE {1} + set_component_parameter_value DIAG_RLD3_TG2_TEST_DURATION {SHORT} + set_component_parameter_value DIAG_RLD3_USER_SIM_MEMORY_PRELOAD {0} + set_component_parameter_value DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_PRI_EMIF_FILE {EMIF_PRI_PRELOAD.txt} + set_component_parameter_value DIAG_RLD3_USER_SIM_MEMORY_PRELOAD_SEC_EMIF_FILE {EMIF_SEC_PRELOAD.txt} + set_component_parameter_value DIAG_RLD3_USER_USE_SIM_MEMORY_VALIDATION_TG {1} + set_component_parameter_value DIAG_RLD3_USE_NEW_EFFMON_S10 {0} + set_component_parameter_value DIAG_RLD3_USE_TG_AVL_2 {0} + set_component_parameter_value DIAG_RLD3_USE_TG_HBM {0} + set_component_parameter_value DIAG_RS232_UART_BAUDRATE {57600} + set_component_parameter_value DIAG_SEQ_RESET_AUTO_RELEASE {avl} + set_component_parameter_value DIAG_SIM_REGTEST_MODE {0} + set_component_parameter_value DIAG_SOFT_NIOS_CLOCK_FREQUENCY {100} + set_component_parameter_value DIAG_SOFT_NIOS_MODE {SOFT_NIOS_MODE_DISABLED} + set_component_parameter_value DIAG_SYNTH_FOR_SIM {0} + set_component_parameter_value DIAG_TG_AVL_2_NUM_CFG_INTERFACES {0} + set_component_parameter_value DIAG_TIMING_REGTEST_MODE {0} + set_component_parameter_value DIAG_USE_BOARD_DELAY_MODEL {0} + set_component_parameter_value DIAG_USE_RS232_UART {0} + set_component_parameter_value DIAG_VERBOSE_IOAUX {0} + set_component_parameter_value EMIF_0_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_0_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_0_STORED_PARAM {} + set_component_parameter_value EMIF_10_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_10_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_10_STORED_PARAM {} + set_component_parameter_value EMIF_11_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_11_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_11_STORED_PARAM {} + set_component_parameter_value EMIF_12_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_12_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_12_STORED_PARAM {} + set_component_parameter_value EMIF_13_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_13_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_13_STORED_PARAM {} + set_component_parameter_value EMIF_14_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_14_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_14_STORED_PARAM {} + set_component_parameter_value EMIF_15_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_15_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_15_STORED_PARAM {} + set_component_parameter_value EMIF_1_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_1_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_1_STORED_PARAM {} + set_component_parameter_value EMIF_2_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_2_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_2_STORED_PARAM {} + set_component_parameter_value EMIF_3_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_3_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_3_STORED_PARAM {} + set_component_parameter_value EMIF_4_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_4_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_4_STORED_PARAM {} + set_component_parameter_value EMIF_5_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_5_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_5_STORED_PARAM {} + set_component_parameter_value EMIF_6_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_6_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_6_STORED_PARAM {} + set_component_parameter_value EMIF_7_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_7_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_7_STORED_PARAM {} + set_component_parameter_value EMIF_8_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_8_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_8_STORED_PARAM {} + set_component_parameter_value EMIF_9_CONN_TO_CALIP {CALIP_0} + set_component_parameter_value EMIF_9_REF_CLK_SHARING {EXPORTED} + set_component_parameter_value EMIF_9_STORED_PARAM {} + set_component_parameter_value EX_DESIGN_GUI_DDR3_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_DDR3_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_DDR3_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_DDR3_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_DDR3_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_DDR3_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDR3_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDR4_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_DDR4_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_DDR4_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_DDR4_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_DDR4_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_DDR4_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDR4_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDRT_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_DDRT_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_DDRT_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_DDRT_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_DDRT_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_DDRT_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_DDRT_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_DDRT_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_QDR2_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_QDR2_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_QDR2_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_QDR2_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_QDR2_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_QDR2_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_QDR2_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_QDR4_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_QDR4_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_QDR4_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_QDR4_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_QDR4_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_QDR4_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_QDR4_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_RLD2_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_RLD2_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_RLD2_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_RLD2_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_RLD2_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_RLD2_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_RLD2_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_RLD3_GEN_BSI {0} + set_component_parameter_value EX_DESIGN_GUI_RLD3_GEN_CDC {0} + set_component_parameter_value EX_DESIGN_GUI_RLD3_GEN_SIM {1} + set_component_parameter_value EX_DESIGN_GUI_RLD3_GEN_SYNTH {1} + set_component_parameter_value EX_DESIGN_GUI_RLD3_HDL_FORMAT {HDL_FORMAT_VERILOG} + set_component_parameter_value EX_DESIGN_GUI_RLD3_PREV_PRESET {TARGET_DEV_KIT_NONE} + set_component_parameter_value EX_DESIGN_GUI_RLD3_SEL_DESIGN {AVAIL_EX_DESIGNS_GEN_DESIGN} + set_component_parameter_value EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT {TARGET_DEV_KIT_NONE} + set_component_parameter_value INTERNAL_TESTING_MODE {0} + set_component_parameter_value IS_ED_SLAVE {0} + set_component_parameter_value MEM_DDR3_ALERT_N_DQS_GROUP {0} + set_component_parameter_value MEM_DDR3_ALERT_N_PLACEMENT_ENUM {DDR3_ALERT_N_PLACEMENT_AC_LANES} + set_component_parameter_value MEM_DDR3_ASR_ENUM {DDR3_ASR_MANUAL} + set_component_parameter_value MEM_DDR3_ATCL_ENUM {DDR3_ATCL_DISABLED} + set_component_parameter_value MEM_DDR3_BANK_ADDR_WIDTH {3} + set_component_parameter_value MEM_DDR3_BL_ENUM {DDR3_BL_BL8} + set_component_parameter_value MEM_DDR3_BT_ENUM {DDR3_BT_SEQUENTIAL} + set_component_parameter_value MEM_DDR3_CFG_GEN_DBE {0} + set_component_parameter_value MEM_DDR3_CFG_GEN_SBE {0} + set_component_parameter_value MEM_DDR3_CKE_PER_DIMM {1} + set_component_parameter_value MEM_DDR3_CK_WIDTH {1} + set_component_parameter_value MEM_DDR3_COL_ADDR_WIDTH {10} + set_component_parameter_value MEM_DDR3_DISCRETE_CS_WIDTH {1} + set_component_parameter_value MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN {0} + set_component_parameter_value MEM_DDR3_DLL_EN {1} + set_component_parameter_value MEM_DDR3_DM_EN {1} + set_component_parameter_value MEM_DDR3_DQ_PER_DQS {8} + set_component_parameter_value MEM_DDR3_DQ_WIDTH {72} + set_component_parameter_value MEM_DDR3_DRV_STR_ENUM {DDR3_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDR3_FORMAT_ENUM {MEM_FORMAT_UDIMM} + set_component_parameter_value MEM_DDR3_HIDE_ADV_MR_SETTINGS {1} + set_component_parameter_value MEM_DDR3_LRDIMM_EXTENDED_CONFIG {000000000000000000} + set_component_parameter_value MEM_DDR3_MIRROR_ADDRESSING_EN {1} + set_component_parameter_value MEM_DDR3_NUM_OF_DIMMS {1} + set_component_parameter_value MEM_DDR3_PD_ENUM {DDR3_PD_OFF} + set_component_parameter_value MEM_DDR3_RANKS_PER_DIMM {1} + set_component_parameter_value MEM_DDR3_RDIMM_CONFIG {0000000000000000} + set_component_parameter_value MEM_DDR3_ROW_ADDR_WIDTH {15} + set_component_parameter_value MEM_DDR3_RTT_NOM_ENUM {DDR3_RTT_NOM_ODT_DISABLED} + set_component_parameter_value MEM_DDR3_RTT_WR_ENUM {DDR3_RTT_WR_RZQ_4} + set_component_parameter_value MEM_DDR3_R_ODT0_1X1 {off} + set_component_parameter_value MEM_DDR3_R_ODT0_2X2 {off off} + set_component_parameter_value MEM_DDR3_R_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDR3_R_ODT0_4X4 {off off on off} + set_component_parameter_value MEM_DDR3_R_ODT1_2X2 {off off} + set_component_parameter_value MEM_DDR3_R_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDR3_R_ODT1_4X4 {off off off on} + set_component_parameter_value MEM_DDR3_R_ODT2_4X4 {on off off off} + set_component_parameter_value MEM_DDR3_R_ODT3_4X4 {off on off off} + set_component_parameter_value MEM_DDR3_R_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDR3_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDR3_R_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR3_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR3_SPEEDBIN_ENUM {DDR3_SPEEDBIN_2133} + set_component_parameter_value MEM_DDR3_SRT_ENUM {DDR3_SRT_NORMAL} + set_component_parameter_value MEM_DDR3_TCL {14} + set_component_parameter_value MEM_DDR3_TDH_DC_MV {100} + set_component_parameter_value MEM_DDR3_TDH_PS {55} + set_component_parameter_value MEM_DDR3_TDQSCK_PS {180} + set_component_parameter_value MEM_DDR3_TDQSQ_PS {75} + set_component_parameter_value MEM_DDR3_TDQSS_CYC {0.27} + set_component_parameter_value MEM_DDR3_TDSH_CYC {0.18} + set_component_parameter_value MEM_DDR3_TDSS_CYC {0.18} + set_component_parameter_value MEM_DDR3_TDS_AC_MV {135} + set_component_parameter_value MEM_DDR3_TDS_PS {53} + set_component_parameter_value MEM_DDR3_TFAW_NS {25.0} + set_component_parameter_value MEM_DDR3_TIH_DC_MV {100} + set_component_parameter_value MEM_DDR3_TIH_PS {95} + set_component_parameter_value MEM_DDR3_TINIT_US {500} + set_component_parameter_value MEM_DDR3_TIS_AC_MV {135} + set_component_parameter_value MEM_DDR3_TIS_PS {60} + set_component_parameter_value MEM_DDR3_TMRD_CK_CYC {4} + set_component_parameter_value MEM_DDR3_TQH_CYC {0.38} + set_component_parameter_value MEM_DDR3_TQSH_CYC {0.4} + set_component_parameter_value MEM_DDR3_TRAS_NS {33.0} + set_component_parameter_value MEM_DDR3_TRCD_NS {13.09} + set_component_parameter_value MEM_DDR3_TREFI_US {7.8} + set_component_parameter_value MEM_DDR3_TRFC_NS {160.0} + set_component_parameter_value MEM_DDR3_TRP_NS {13.09} + set_component_parameter_value MEM_DDR3_TRRD_CYC {6} + set_component_parameter_value MEM_DDR3_TRTP_CYC {8} + set_component_parameter_value MEM_DDR3_TWLH_PS {125.0} + set_component_parameter_value MEM_DDR3_TWLS_PS {125.0} + set_component_parameter_value MEM_DDR3_TWR_NS {15.0} + set_component_parameter_value MEM_DDR3_TWTR_CYC {8} + set_component_parameter_value MEM_DDR3_USE_DEFAULT_ODT {1} + set_component_parameter_value MEM_DDR3_WTCL {10} + set_component_parameter_value MEM_DDR3_W_ODT0_1X1 {on} + set_component_parameter_value MEM_DDR3_W_ODT0_2X2 {on off} + set_component_parameter_value MEM_DDR3_W_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDR3_W_ODT0_4X4 {on off on off} + set_component_parameter_value MEM_DDR3_W_ODT1_2X2 {off on} + set_component_parameter_value MEM_DDR3_W_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDR3_W_ODT1_4X4 {off on off on} + set_component_parameter_value MEM_DDR3_W_ODT2_4X4 {on off on off} + set_component_parameter_value MEM_DDR3_W_ODT3_4X4 {off on off on} + set_component_parameter_value MEM_DDR3_W_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDR3_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDR3_W_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR3_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR4_AC_PARITY_LATENCY {DDR4_AC_PARITY_LATENCY_DISABLE} + set_component_parameter_value MEM_DDR4_AC_PERSISTENT_ERROR {0} + set_component_parameter_value MEM_DDR4_ALERT_N_AC_LANE {0} + set_component_parameter_value MEM_DDR4_ALERT_N_AC_PIN {0} + set_component_parameter_value MEM_DDR4_ALERT_N_DQS_GROUP {0} + set_component_parameter_value MEM_DDR4_ALERT_N_PLACEMENT_ENUM {DDR4_ALERT_N_PLACEMENT_AUTO} + set_component_parameter_value MEM_DDR4_ALERT_PAR_EN {1} + set_component_parameter_value MEM_DDR4_ASR_ENUM {DDR4_ASR_MANUAL_NORMAL} + set_component_parameter_value MEM_DDR4_ATCL_ENUM {DDR4_ATCL_DISABLED} + set_component_parameter_value MEM_DDR4_BANK_ADDR_WIDTH {2} + set_component_parameter_value MEM_DDR4_BANK_GROUP_WIDTH {2} + set_component_parameter_value MEM_DDR4_BL_ENUM {DDR4_BL_BL8} + set_component_parameter_value MEM_DDR4_BT_ENUM {DDR4_BT_SEQUENTIAL} + set_component_parameter_value MEM_DDR4_CAL_MODE {0} + set_component_parameter_value MEM_DDR4_CFG_GEN_DBE {0} + set_component_parameter_value MEM_DDR4_CFG_GEN_SBE {0} + set_component_parameter_value MEM_DDR4_CHIP_ID_WIDTH {0} + set_component_parameter_value MEM_DDR4_CKE_PER_DIMM {1} + set_component_parameter_value MEM_DDR4_CK_WIDTH {1} + set_component_parameter_value MEM_DDR4_COL_ADDR_WIDTH {10} + set_component_parameter_value MEM_DDR4_DB_DQ_DRV_ENUM {DDR4_DB_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDR4_DB_RTT_NOM_ENUM {DDR4_DB_RTT_NOM_ODT_DISABLED} + set_component_parameter_value MEM_DDR4_DB_RTT_PARK_ENUM {DDR4_DB_RTT_PARK_ODT_DISABLED} + set_component_parameter_value MEM_DDR4_DB_RTT_WR_ENUM {DDR4_DB_RTT_WR_RZQ_3} + set_component_parameter_value MEM_DDR4_DEFAULT_VREFOUT {1} + set_component_parameter_value MEM_DDR4_DISCRETE_CS_WIDTH {1} + set_component_parameter_value MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN {0} + set_component_parameter_value MEM_DDR4_DLL_EN {1} + set_component_parameter_value MEM_DDR4_DM_EN {1} + set_component_parameter_value MEM_DDR4_DQ_PER_DQS {8} + set_component_parameter_value MEM_DDR4_DQ_WIDTH {64} + set_component_parameter_value MEM_DDR4_DRV_STR_ENUM {DDR4_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDR4_FINE_GRANULARITY_REFRESH {DDR4_FINE_REFRESH_FIXED_1X} + set_component_parameter_value MEM_DDR4_FORMAT_ENUM {MEM_FORMAT_RDIMM} + set_component_parameter_value MEM_DDR4_GEARDOWN {DDR4_GEARDOWN_HR} + set_component_parameter_value MEM_DDR4_HIDE_ADV_MR_SETTINGS {1} + set_component_parameter_value MEM_DDR4_INTEL_DEFAULT_TERM {1} + set_component_parameter_value MEM_DDR4_INTERNAL_VREFDQ_MONITOR {0} + set_component_parameter_value MEM_DDR4_LRDIMM_ODT_LESS_BS {0} + set_component_parameter_value MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM {240} + set_component_parameter_value MEM_DDR4_LRDIMM_VREFDQ_VALUE {} + set_component_parameter_value MEM_DDR4_MAX_POWERDOWN {0} + set_component_parameter_value MEM_DDR4_MIRROR_ADDRESSING_EN {1} + set_component_parameter_value MEM_DDR4_MPR_READ_FORMAT {DDR4_MPR_READ_FORMAT_SERIAL} + set_component_parameter_value MEM_DDR4_NUM_OF_DIMMS {1} + set_component_parameter_value MEM_DDR4_ODT_IN_POWERDOWN {1} + set_component_parameter_value MEM_DDR4_PER_DRAM_ADDR {0} + set_component_parameter_value MEM_DDR4_RANKS_PER_DIMM {1} + set_component_parameter_value MEM_DDR4_RCD_CA_IBT_ENUM {DDR4_RCD_CA_IBT_100} + set_component_parameter_value MEM_DDR4_RCD_CKE_IBT_ENUM {DDR4_RCD_CKE_IBT_100} + set_component_parameter_value MEM_DDR4_RCD_CS_IBT_ENUM {DDR4_RCD_CS_IBT_100} + set_component_parameter_value MEM_DDR4_RCD_ODT_IBT_ENUM {DDR4_RCD_ODT_IBT_100} + set_component_parameter_value MEM_DDR4_READ_DBI {1} + set_component_parameter_value MEM_DDR4_READ_PREAMBLE {2} + set_component_parameter_value MEM_DDR4_READ_PREAMBLE_TRAINING {0} + set_component_parameter_value MEM_DDR4_ROW_ADDR_WIDTH {16} + set_component_parameter_value MEM_DDR4_RTT_NOM_ENUM {DDR4_RTT_NOM_RZQ_4} + set_component_parameter_value MEM_DDR4_RTT_PARK {DDR4_RTT_PARK_ODT_DISABLED} + set_component_parameter_value MEM_DDR4_RTT_WR_ENUM {DDR4_RTT_WR_ODT_DISABLED} + set_component_parameter_value MEM_DDR4_R_ODT0_1X1 {off} + set_component_parameter_value MEM_DDR4_R_ODT0_2X2 {off off} + set_component_parameter_value MEM_DDR4_R_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDR4_R_ODT0_4X4 {off off on off} + set_component_parameter_value MEM_DDR4_R_ODT1_2X2 {off off} + set_component_parameter_value MEM_DDR4_R_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDR4_R_ODT1_4X4 {off off off on} + set_component_parameter_value MEM_DDR4_R_ODT2_4X4 {on off off off} + set_component_parameter_value MEM_DDR4_R_ODT3_4X4 {off on off off} + set_component_parameter_value MEM_DDR4_R_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDR4_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDR4_R_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR4_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR4_SELF_RFSH_ABORT {0} + set_component_parameter_value MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB {0} + set_component_parameter_value MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB {0} + set_component_parameter_value MEM_DDR4_SPD_135_RCD_REV {0} + set_component_parameter_value MEM_DDR4_SPD_137_RCD_CA_DRV {101} + set_component_parameter_value MEM_DDR4_SPD_138_RCD_CK_DRV {5} + set_component_parameter_value MEM_DDR4_SPD_139_DB_REV {0} + set_component_parameter_value MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 {29} + set_component_parameter_value MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 {29} + set_component_parameter_value MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 {29} + set_component_parameter_value MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 {29} + set_component_parameter_value MEM_DDR4_SPD_144_DB_VREFDQ {37} + set_component_parameter_value MEM_DDR4_SPD_145_DB_MDQ_DRV {21} + set_component_parameter_value MEM_DDR4_SPD_148_DRAM_DRV {0} + set_component_parameter_value MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM {20} + set_component_parameter_value MEM_DDR4_SPD_152_DRAM_RTT_PARK {39} + set_component_parameter_value MEM_DDR4_SPD_155_DB_VREFDQ_RANGE {0} + set_component_parameter_value MEM_DDR4_SPEEDBIN_ENUM {DDR4_SPEEDBIN_2666} + set_component_parameter_value MEM_DDR4_TCCD_L_CYC {6} + set_component_parameter_value MEM_DDR4_TCCD_S_CYC {4} + set_component_parameter_value MEM_DDR4_TCL {23} + set_component_parameter_value MEM_DDR4_TDIVW_DJ_CYC {0.1} + set_component_parameter_value MEM_DDR4_TDIVW_TOTAL_UI {0.2} + set_component_parameter_value MEM_DDR4_TDQSCK_PS {175} + set_component_parameter_value MEM_DDR4_TDQSQ_PS {66} + set_component_parameter_value MEM_DDR4_TDQSQ_UI {0.14} + set_component_parameter_value MEM_DDR4_TDQSS_CYC {0.27} + set_component_parameter_value MEM_DDR4_TDSH_CYC {0.18} + set_component_parameter_value MEM_DDR4_TDSS_CYC {0.18} + set_component_parameter_value MEM_DDR4_TDVWP_UI {0.72} + set_component_parameter_value MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA {0} + set_component_parameter_value MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE {DDR4_TEMP_CONTROLLED_RFSH_NORMAL} + set_component_parameter_value MEM_DDR4_TEMP_SENSOR_READOUT {0} + set_component_parameter_value MEM_DDR4_TFAW_DLR_CYC {16} + set_component_parameter_value MEM_DDR4_TFAW_NS {21.0} + set_component_parameter_value MEM_DDR4_TIH_DC_MV {75} + set_component_parameter_value MEM_DDR4_TIH_PS {87} + set_component_parameter_value MEM_DDR4_TINIT_US {500} + set_component_parameter_value MEM_DDR4_TIS_AC_MV {100} + set_component_parameter_value MEM_DDR4_TIS_PS {62} + set_component_parameter_value MEM_DDR4_TMRD_CK_CYC {8} + set_component_parameter_value MEM_DDR4_TQH_CYC {0.38} + set_component_parameter_value MEM_DDR4_TQH_UI {0.74} + set_component_parameter_value MEM_DDR4_TQSH_CYC {0.4} + set_component_parameter_value MEM_DDR4_TRAS_NS {32.0} + set_component_parameter_value MEM_DDR4_TRCD_NS {14.16} + set_component_parameter_value MEM_DDR4_TREFI_US {7.8} + set_component_parameter_value MEM_DDR4_TRFC_DLR_NS {90.0} + set_component_parameter_value MEM_DDR4_TRFC_NS {350.0} + set_component_parameter_value MEM_DDR4_TRP_NS {14.16} + set_component_parameter_value MEM_DDR4_TRRD_DLR_CYC {4} + set_component_parameter_value MEM_DDR4_TRRD_L_CYC {6} + set_component_parameter_value MEM_DDR4_TRRD_S_CYC {4} + set_component_parameter_value MEM_DDR4_TWLH_CYC {0.13} + set_component_parameter_value MEM_DDR4_TWLH_PS {0.0} + set_component_parameter_value MEM_DDR4_TWLS_CYC {0.13} + set_component_parameter_value MEM_DDR4_TWLS_PS {0.0} + set_component_parameter_value MEM_DDR4_TWR_NS {15.0} + set_component_parameter_value MEM_DDR4_TWTR_L_CYC {9} + set_component_parameter_value MEM_DDR4_TWTR_S_CYC {3} + set_component_parameter_value MEM_DDR4_USER_VREFDQ_TRAINING_RANGE {DDR4_VREFDQ_TRAINING_RANGE_1} + set_component_parameter_value MEM_DDR4_USER_VREFDQ_TRAINING_VALUE {56.0} + set_component_parameter_value MEM_DDR4_USE_DEFAULT_ODT {1} + set_component_parameter_value MEM_DDR4_VDIVW_TOTAL {130} + set_component_parameter_value MEM_DDR4_WRITE_CRC {0} + set_component_parameter_value MEM_DDR4_WRITE_DBI {0} + set_component_parameter_value MEM_DDR4_WRITE_PREAMBLE {1} + set_component_parameter_value MEM_DDR4_WTCL {18} + set_component_parameter_value MEM_DDR4_W_ODT0_1X1 {on} + set_component_parameter_value MEM_DDR4_W_ODT0_2X2 {on off} + set_component_parameter_value MEM_DDR4_W_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDR4_W_ODT0_4X4 {on off on off} + set_component_parameter_value MEM_DDR4_W_ODT1_2X2 {off on} + set_component_parameter_value MEM_DDR4_W_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDR4_W_ODT1_4X4 {off on off on} + set_component_parameter_value MEM_DDR4_W_ODT2_4X4 {on off on off} + set_component_parameter_value MEM_DDR4_W_ODT3_4X4 {off on off on} + set_component_parameter_value MEM_DDR4_W_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDR4_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDR4_W_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDR4_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDRT_AC_PARITY_LATENCY {DDRT_AC_PARITY_LATENCY_DISABLE} + set_component_parameter_value MEM_DDRT_AC_PERSISTENT_ERROR {0} + set_component_parameter_value MEM_DDRT_ALERT_N_AC_LANE {0} + set_component_parameter_value MEM_DDRT_ALERT_N_AC_PIN {0} + set_component_parameter_value MEM_DDRT_ALERT_N_DQS_GROUP {0} + set_component_parameter_value MEM_DDRT_ALERT_N_PLACEMENT_ENUM {DDRT_ALERT_N_PLACEMENT_AUTO} + set_component_parameter_value MEM_DDRT_ALERT_PAR_EN {1} + set_component_parameter_value MEM_DDRT_ASR_ENUM {DDRT_ASR_MANUAL_NORMAL} + set_component_parameter_value MEM_DDRT_ATCL_ENUM {DDRT_ATCL_DISABLED} + set_component_parameter_value MEM_DDRT_BANK_ADDR_WIDTH {2} + set_component_parameter_value MEM_DDRT_BANK_GROUP_WIDTH {2} + set_component_parameter_value MEM_DDRT_BL_ENUM {DDRT_BL_BL8} + set_component_parameter_value MEM_DDRT_BT_ENUM {DDRT_BT_SEQUENTIAL} + set_component_parameter_value MEM_DDRT_CAL_MODE {0} + set_component_parameter_value MEM_DDRT_CFG_GEN_DBE {0} + set_component_parameter_value MEM_DDRT_CFG_GEN_SBE {0} + set_component_parameter_value MEM_DDRT_CKE_PER_DIMM {1} + set_component_parameter_value MEM_DDRT_COL_ADDR_WIDTH {10} + set_component_parameter_value MEM_DDRT_DB_DQ_DRV_ENUM {DDRT_DB_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDRT_DB_RTT_NOM_ENUM {DDRT_DB_RTT_NOM_ODT_DISABLED} + set_component_parameter_value MEM_DDRT_DB_RTT_PARK_ENUM {DDRT_DB_RTT_PARK_ODT_DISABLED} + set_component_parameter_value MEM_DDRT_DB_RTT_WR_ENUM {DDRT_DB_RTT_WR_RZQ_4} + set_component_parameter_value MEM_DDRT_DEFAULT_ADDED_LATENCY {1} + set_component_parameter_value MEM_DDRT_DEFAULT_PREAMBLE {1} + set_component_parameter_value MEM_DDRT_DEFAULT_VREFOUT {1} + set_component_parameter_value MEM_DDRT_DISCRETE_CS_WIDTH {1} + set_component_parameter_value MEM_DDRT_DISCRETE_MIRROR_ADDRESSING_EN {0} + set_component_parameter_value MEM_DDRT_DLL_EN {1} + set_component_parameter_value MEM_DDRT_DM_EN {0} + set_component_parameter_value MEM_DDRT_DQ_PER_DQS {4} + set_component_parameter_value MEM_DDRT_DQ_WIDTH {72} + set_component_parameter_value MEM_DDRT_DRV_STR_ENUM {DDRT_DRV_STR_RZQ_7} + set_component_parameter_value MEM_DDRT_FINE_GRANULARITY_REFRESH {DDRT_FINE_REFRESH_FIXED_1X} + set_component_parameter_value MEM_DDRT_FORMAT_ENUM {MEM_FORMAT_LRDIMM} + set_component_parameter_value MEM_DDRT_GEARDOWN {DDRT_GEARDOWN_HR} + set_component_parameter_value MEM_DDRT_HIDE_ADV_MR_SETTINGS {1} + set_component_parameter_value MEM_DDRT_HIDE_LATENCY_SETTINGS {1} + set_component_parameter_value MEM_DDRT_I2C_DIMM_0_SA {0} + set_component_parameter_value MEM_DDRT_I2C_DIMM_1_SA {1} + set_component_parameter_value MEM_DDRT_I2C_DIMM_2_SA {2} + set_component_parameter_value MEM_DDRT_I2C_DIMM_3_SA {3} + set_component_parameter_value MEM_DDRT_INTERNAL_VREFDQ_MONITOR {0} + set_component_parameter_value MEM_DDRT_LRDIMM_ODT_LESS_BS {0} + set_component_parameter_value MEM_DDRT_LRDIMM_ODT_LESS_BS_PARK_OHM {240} + set_component_parameter_value MEM_DDRT_LRDIMM_VREFDQ_VALUE {} + set_component_parameter_value MEM_DDRT_MAX_POWERDOWN {0} + set_component_parameter_value MEM_DDRT_MIRROR_ADDRESSING_EN {1} + set_component_parameter_value MEM_DDRT_MPR_READ_FORMAT {DDRT_MPR_READ_FORMAT_SERIAL} + set_component_parameter_value MEM_DDRT_NUM_OF_DIMMS {1} + set_component_parameter_value MEM_DDRT_ODT_IN_POWERDOWN {1} + set_component_parameter_value MEM_DDRT_PARTIAL_WRITES {0} + set_component_parameter_value MEM_DDRT_PERSISTENT_MODE {1} + set_component_parameter_value MEM_DDRT_PER_DRAM_ADDR {0} + set_component_parameter_value MEM_DDRT_PWR_MODE {DDRT_PWR_MODE_12W} + set_component_parameter_value MEM_DDRT_RANKS_PER_DIMM {1} + set_component_parameter_value MEM_DDRT_RCD_CA_IBT_ENUM {DDRT_RCD_CA_IBT_100} + set_component_parameter_value MEM_DDRT_RCD_CKE_IBT_ENUM {DDRT_RCD_CKE_IBT_100} + set_component_parameter_value MEM_DDRT_RCD_CS_IBT_ENUM {DDRT_RCD_CS_IBT_100} + set_component_parameter_value MEM_DDRT_RCD_ODT_IBT_ENUM {DDRT_RCD_ODT_IBT_100} + set_component_parameter_value MEM_DDRT_READ_DBI {0} + set_component_parameter_value MEM_DDRT_READ_PREAMBLE_TRAINING {0} + set_component_parameter_value MEM_DDRT_ROW_ADDR_WIDTH {18} + set_component_parameter_value MEM_DDRT_RTT_NOM_ENUM {DDRT_RTT_NOM_RZQ_4} + set_component_parameter_value MEM_DDRT_RTT_PARK {DDRT_RTT_PARK_ODT_DISABLED} + set_component_parameter_value MEM_DDRT_RTT_WR_ENUM {DDRT_RTT_WR_ODT_DISABLED} + set_component_parameter_value MEM_DDRT_R_ODT0_1X1 {off} + set_component_parameter_value MEM_DDRT_R_ODT0_2X2 {off off} + set_component_parameter_value MEM_DDRT_R_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDRT_R_ODT0_4X4 {off off off off} + set_component_parameter_value MEM_DDRT_R_ODT1_2X2 {off off} + set_component_parameter_value MEM_DDRT_R_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDRT_R_ODT1_4X4 {off off on on} + set_component_parameter_value MEM_DDRT_R_ODT2_4X4 {off off off off} + set_component_parameter_value MEM_DDRT_R_ODT3_4X4 {on on off off} + set_component_parameter_value MEM_DDRT_R_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDRT_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDRT_R_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDRT_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDRT_SELF_RFSH_ABORT {0} + set_component_parameter_value MEM_DDRT_SPD_133_RCD_DB_VENDOR_LSB {0} + set_component_parameter_value MEM_DDRT_SPD_134_RCD_DB_VENDOR_MSB {0} + set_component_parameter_value MEM_DDRT_SPD_135_RCD_REV {0} + set_component_parameter_value MEM_DDRT_SPD_137_RCD_CA_DRV {85} + set_component_parameter_value MEM_DDRT_SPD_138_RCD_CK_DRV {5} + set_component_parameter_value MEM_DDRT_SPD_139_DB_REV {0} + set_component_parameter_value MEM_DDRT_SPD_140_DRAM_VREFDQ_R0 {29} + set_component_parameter_value MEM_DDRT_SPD_141_DRAM_VREFDQ_R1 {29} + set_component_parameter_value MEM_DDRT_SPD_142_DRAM_VREFDQ_R2 {29} + set_component_parameter_value MEM_DDRT_SPD_143_DRAM_VREFDQ_R3 {29} + set_component_parameter_value MEM_DDRT_SPD_144_DB_VREFDQ {25} + set_component_parameter_value MEM_DDRT_SPD_145_DB_MDQ_DRV {21} + set_component_parameter_value MEM_DDRT_SPD_148_DRAM_DRV {0} + set_component_parameter_value MEM_DDRT_SPD_149_DRAM_RTT_WR_NOM {20} + set_component_parameter_value MEM_DDRT_SPD_152_DRAM_RTT_PARK {39} + set_component_parameter_value MEM_DDRT_SPEEDBIN_ENUM {DDRT_SPEEDBIN_2400} + set_component_parameter_value MEM_DDRT_TCCD_L_CYC {6} + set_component_parameter_value MEM_DDRT_TCCD_S_CYC {4} + set_component_parameter_value MEM_DDRT_TCL {15} + set_component_parameter_value MEM_DDRT_TDIVW_DJ_CYC {0.1} + set_component_parameter_value MEM_DDRT_TDIVW_TOTAL_UI {0.2} + set_component_parameter_value MEM_DDRT_TDQSCK_PS {165} + set_component_parameter_value MEM_DDRT_TDQSQ_PS {66} + set_component_parameter_value MEM_DDRT_TDQSQ_UI {0.16} + set_component_parameter_value MEM_DDRT_TDQSS_CYC {0.27} + set_component_parameter_value MEM_DDRT_TDSH_CYC {0.18} + set_component_parameter_value MEM_DDRT_TDSS_CYC {0.18} + set_component_parameter_value MEM_DDRT_TDVWP_UI {0.72} + set_component_parameter_value MEM_DDRT_TEMP_CONTROLLED_RFSH_ENA {0} + set_component_parameter_value MEM_DDRT_TEMP_CONTROLLED_RFSH_RANGE {DDRT_TEMP_CONTROLLED_RFSH_NORMAL} + set_component_parameter_value MEM_DDRT_TEMP_SENSOR_READOUT {0} + set_component_parameter_value MEM_DDRT_TFAW_DLR_CYC {16} + set_component_parameter_value MEM_DDRT_TFAW_NS {21.0} + set_component_parameter_value MEM_DDRT_TIH_DC_MV {75} + set_component_parameter_value MEM_DDRT_TIH_PS {95} + set_component_parameter_value MEM_DDRT_TINIT_US {500} + set_component_parameter_value MEM_DDRT_TIS_AC_MV {100} + set_component_parameter_value MEM_DDRT_TIS_PS {60} + set_component_parameter_value MEM_DDRT_TMRD_CK_CYC {8} + set_component_parameter_value MEM_DDRT_TQH_CYC {0.38} + set_component_parameter_value MEM_DDRT_TQH_UI {0.76} + set_component_parameter_value MEM_DDRT_TQSH_CYC {0.38} + set_component_parameter_value MEM_DDRT_TRAS_NS {32.0} + set_component_parameter_value MEM_DDRT_TRCD_NS {15.0} + set_component_parameter_value MEM_DDRT_TREFI_US {7.8} + set_component_parameter_value MEM_DDRT_TRFC_DLR_NS {90.0} + set_component_parameter_value MEM_DDRT_TRFC_NS {260.0} + set_component_parameter_value MEM_DDRT_TRP_NS {15.0} + set_component_parameter_value MEM_DDRT_TRRD_DLR_CYC {4} + set_component_parameter_value MEM_DDRT_TRRD_L_CYC {6} + set_component_parameter_value MEM_DDRT_TRRD_S_CYC {4} + set_component_parameter_value MEM_DDRT_TWLH_CYC {0.13} + set_component_parameter_value MEM_DDRT_TWLH_PS {0.0} + set_component_parameter_value MEM_DDRT_TWLS_CYC {0.13} + set_component_parameter_value MEM_DDRT_TWLS_PS {0.0} + set_component_parameter_value MEM_DDRT_TWR_NS {15.0} + set_component_parameter_value MEM_DDRT_TWTR_L_CYC {9} + set_component_parameter_value MEM_DDRT_TWTR_S_CYC {3} + set_component_parameter_value MEM_DDRT_USER_READ_PREAMBLE {1} + set_component_parameter_value MEM_DDRT_USER_TCL_ADDED {0} + set_component_parameter_value MEM_DDRT_USER_VREFDQ_TRAINING_RANGE {DDRT_VREFDQ_TRAINING_RANGE_1} + set_component_parameter_value MEM_DDRT_USER_VREFDQ_TRAINING_VALUE {56.0} + set_component_parameter_value MEM_DDRT_USER_WRITE_PREAMBLE {1} + set_component_parameter_value MEM_DDRT_USER_WTCL_ADDED {6} + set_component_parameter_value MEM_DDRT_USE_DEFAULT_ODT {1} + set_component_parameter_value MEM_DDRT_VDIVW_TOTAL {136} + set_component_parameter_value MEM_DDRT_WRITE_CRC {0} + set_component_parameter_value MEM_DDRT_WRITE_DBI {0} + set_component_parameter_value MEM_DDRT_WTCL {18} + set_component_parameter_value MEM_DDRT_W_ODT0_1X1 {on} + set_component_parameter_value MEM_DDRT_W_ODT0_2X2 {on off} + set_component_parameter_value MEM_DDRT_W_ODT0_4X2 {off off on on} + set_component_parameter_value MEM_DDRT_W_ODT0_4X4 {on on off off} + set_component_parameter_value MEM_DDRT_W_ODT1_2X2 {off on} + set_component_parameter_value MEM_DDRT_W_ODT1_4X2 {on on off off} + set_component_parameter_value MEM_DDRT_W_ODT1_4X4 {off off on on} + set_component_parameter_value MEM_DDRT_W_ODT2_4X4 {off off on on} + set_component_parameter_value MEM_DDRT_W_ODT3_4X4 {on on off off} + set_component_parameter_value MEM_DDRT_W_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_DDRT_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_DDRT_W_ODTN_4X2 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_DDRT_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_LPDDR3_BANK_ADDR_WIDTH {3} + set_component_parameter_value MEM_LPDDR3_BL {LPDDR3_BL_BL8} + set_component_parameter_value MEM_LPDDR3_CK_WIDTH {1} + set_component_parameter_value MEM_LPDDR3_COL_ADDR_WIDTH {10} + set_component_parameter_value MEM_LPDDR3_DATA_LATENCY {LPDDR3_DL_RL12_WL6} + set_component_parameter_value MEM_LPDDR3_DISCRETE_CS_WIDTH {1} + set_component_parameter_value MEM_LPDDR3_DM_EN {1} + set_component_parameter_value MEM_LPDDR3_DQODT {LPDDR3_DQODT_DISABLE} + set_component_parameter_value MEM_LPDDR3_DQ_WIDTH {32} + set_component_parameter_value MEM_LPDDR3_DRV_STR {LPDDR3_DRV_STR_40D_40U} + set_component_parameter_value MEM_LPDDR3_PDODT {LPDDR3_PDODT_DISABLED} + set_component_parameter_value MEM_LPDDR3_ROW_ADDR_WIDTH {15} + set_component_parameter_value MEM_LPDDR3_R_ODT0_1X1 {off} + set_component_parameter_value MEM_LPDDR3_R_ODT0_2X2 {off off} + set_component_parameter_value MEM_LPDDR3_R_ODT0_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_R_ODT1_2X2 {off off} + set_component_parameter_value MEM_LPDDR3_R_ODT1_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_R_ODT2_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_R_ODT3_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_R_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_LPDDR3_R_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_LPDDR3_R_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_LPDDR3_SPEEDBIN_ENUM {LPDDR3_SPEEDBIN_1600} + set_component_parameter_value MEM_LPDDR3_TDH_DC_MV {100} + set_component_parameter_value MEM_LPDDR3_TDH_PS {100} + set_component_parameter_value MEM_LPDDR3_TDQSCKDL {614} + set_component_parameter_value MEM_LPDDR3_TDQSQ_PS {135} + set_component_parameter_value MEM_LPDDR3_TDQSS_CYC {1.25} + set_component_parameter_value MEM_LPDDR3_TDSH_CYC {0.2} + set_component_parameter_value MEM_LPDDR3_TDSS_CYC {0.2} + set_component_parameter_value MEM_LPDDR3_TDS_AC_MV {150} + set_component_parameter_value MEM_LPDDR3_TDS_PS {75} + set_component_parameter_value MEM_LPDDR3_TFAW_NS {50.0} + set_component_parameter_value MEM_LPDDR3_TIH_DC_MV {100} + set_component_parameter_value MEM_LPDDR3_TIH_PS {100} + set_component_parameter_value MEM_LPDDR3_TINIT_US {500} + set_component_parameter_value MEM_LPDDR3_TIS_AC_MV {150} + set_component_parameter_value MEM_LPDDR3_TIS_PS {75} + set_component_parameter_value MEM_LPDDR3_TMRR_CK_CYC {4} + set_component_parameter_value MEM_LPDDR3_TMRW_CK_CYC {10} + set_component_parameter_value MEM_LPDDR3_TQH_CYC {0.38} + set_component_parameter_value MEM_LPDDR3_TQSH_CYC {0.38} + set_component_parameter_value MEM_LPDDR3_TRAS_NS {42.5} + set_component_parameter_value MEM_LPDDR3_TRCD_NS {18.0} + set_component_parameter_value MEM_LPDDR3_TREFI_US {3.9} + set_component_parameter_value MEM_LPDDR3_TRFC_NS {210.0} + set_component_parameter_value MEM_LPDDR3_TRP_NS {18.0} + set_component_parameter_value MEM_LPDDR3_TRRD_CYC {8} + set_component_parameter_value MEM_LPDDR3_TRTP_CYC {6} + set_component_parameter_value MEM_LPDDR3_TWLH_PS {175.0} + set_component_parameter_value MEM_LPDDR3_TWLS_PS {175.0} + set_component_parameter_value MEM_LPDDR3_TWR_NS {15.0} + set_component_parameter_value MEM_LPDDR3_TWTR_CYC {6} + set_component_parameter_value MEM_LPDDR3_USE_DEFAULT_ODT {1} + set_component_parameter_value MEM_LPDDR3_W_ODT0_1X1 {on} + set_component_parameter_value MEM_LPDDR3_W_ODT0_2X2 {on on} + set_component_parameter_value MEM_LPDDR3_W_ODT0_4X4 {on on on on} + set_component_parameter_value MEM_LPDDR3_W_ODT1_2X2 {off off} + set_component_parameter_value MEM_LPDDR3_W_ODT1_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_W_ODT2_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_W_ODT3_4X4 {off off off off} + set_component_parameter_value MEM_LPDDR3_W_ODTN_1X1 {Rank\ 0} + set_component_parameter_value MEM_LPDDR3_W_ODTN_2X2 {Rank\ 0 Rank\ 1} + set_component_parameter_value MEM_LPDDR3_W_ODTN_4X4 {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} + set_component_parameter_value MEM_QDR2_ADDR_WIDTH {19} + set_component_parameter_value MEM_QDR2_BL {4} + set_component_parameter_value MEM_QDR2_BWS_EN {1} + set_component_parameter_value MEM_QDR2_DATA_PER_DEVICE {36} + set_component_parameter_value MEM_QDR2_INTERNAL_JITTER_NS {0.08} + set_component_parameter_value MEM_QDR2_SPEEDBIN_ENUM {QDR2_SPEEDBIN_633} + set_component_parameter_value MEM_QDR2_TCCQO_NS {0.45} + set_component_parameter_value MEM_QDR2_TCQDOH_NS {-0.09} + set_component_parameter_value MEM_QDR2_TCQD_NS {0.09} + set_component_parameter_value MEM_QDR2_TCQH_NS {0.71} + set_component_parameter_value MEM_QDR2_THA_NS {0.18} + set_component_parameter_value MEM_QDR2_THD_NS {0.18} + set_component_parameter_value MEM_QDR2_TRL_CYC {2.5} + set_component_parameter_value MEM_QDR2_TSA_NS {0.23} + set_component_parameter_value MEM_QDR2_TSD_NS {0.23} + set_component_parameter_value MEM_QDR2_WIDTH_EXPANDED {0} + set_component_parameter_value MEM_QDR4_AC_ODT_MODE_ENUM {QDR4_ODT_25_PCT} + set_component_parameter_value MEM_QDR4_ADDR_INV_ENA {0} + set_component_parameter_value MEM_QDR4_ADDR_WIDTH {21} + set_component_parameter_value MEM_QDR4_CK_ODT_MODE_ENUM {QDR4_ODT_25_PCT} + set_component_parameter_value MEM_QDR4_DATA_INV_ENA {1} + set_component_parameter_value MEM_QDR4_DATA_ODT_MODE_ENUM {QDR4_ODT_25_PCT} + set_component_parameter_value MEM_QDR4_DQ_PER_PORT_PER_DEVICE {36} + set_component_parameter_value MEM_QDR4_MEM_TYPE_ENUM {MEM_XP} + set_component_parameter_value MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM {QDR4_OUTPUT_DRIVE_25_PCT} + set_component_parameter_value MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM {QDR4_OUTPUT_DRIVE_25_PCT} + set_component_parameter_value MEM_QDR4_SKIP_ODT_SWEEPING {1} + set_component_parameter_value MEM_QDR4_SPEEDBIN_ENUM {QDR4_SPEEDBIN_2133} + set_component_parameter_value MEM_QDR4_TASH_PS {170} + set_component_parameter_value MEM_QDR4_TCKDK_MAX_PS {150} + set_component_parameter_value MEM_QDR4_TCKDK_MIN_PS {-150} + set_component_parameter_value MEM_QDR4_TCKQK_MAX_PS {225} + set_component_parameter_value MEM_QDR4_TCSH_PS {170} + set_component_parameter_value MEM_QDR4_TISH_PS {150} + set_component_parameter_value MEM_QDR4_TQH_CYC {0.4} + set_component_parameter_value MEM_QDR4_TQKQ_MAX_PS {75} + set_component_parameter_value MEM_QDR4_USE_ADDR_PARITY {0} + set_component_parameter_value MEM_QDR4_WIDTH_EXPANDED {0} + set_component_parameter_value MEM_RLD2_ADDR_WIDTH {21} + set_component_parameter_value MEM_RLD2_BANK_ADDR_WIDTH {3} + set_component_parameter_value MEM_RLD2_BL {4} + set_component_parameter_value MEM_RLD2_CONFIG_ENUM {RLD2_CONFIG_TRC_8_TRL_8_TWL_9} + set_component_parameter_value MEM_RLD2_DM_EN {1} + set_component_parameter_value MEM_RLD2_DQ_PER_DEVICE {9} + set_component_parameter_value MEM_RLD2_DRIVE_IMPEDENCE_ENUM {RLD2_DRIVE_IMPEDENCE_INTERNAL_50} + set_component_parameter_value MEM_RLD2_ODT_MODE_ENUM {RLD2_ODT_ON} + set_component_parameter_value MEM_RLD2_REFRESH_INTERVAL_US {0.24} + set_component_parameter_value MEM_RLD2_SPEEDBIN_ENUM {RLD2_SPEEDBIN_18} + set_component_parameter_value MEM_RLD2_TAH_NS {0.3} + set_component_parameter_value MEM_RLD2_TAS_NS {0.3} + set_component_parameter_value MEM_RLD2_TCKDK_MAX_NS {0.3} + set_component_parameter_value MEM_RLD2_TCKDK_MIN_NS {-0.3} + set_component_parameter_value MEM_RLD2_TCKH_CYC {0.45} + set_component_parameter_value MEM_RLD2_TCKQK_MAX_NS {0.2} + set_component_parameter_value MEM_RLD2_TDH_NS {0.17} + set_component_parameter_value MEM_RLD2_TDS_NS {0.17} + set_component_parameter_value MEM_RLD2_TQKH_HCYC {0.9} + set_component_parameter_value MEM_RLD2_TQKQ_MAX_NS {0.12} + set_component_parameter_value MEM_RLD2_TQKQ_MIN_NS {-0.12} + set_component_parameter_value MEM_RLD2_WIDTH_EXPANDED {0} + set_component_parameter_value MEM_RLD3_ADDR_WIDTH {20} + set_component_parameter_value MEM_RLD3_AREF_PROTOCOL_ENUM {RLD3_AREF_BAC} + set_component_parameter_value MEM_RLD3_BANK_ADDR_WIDTH {4} + set_component_parameter_value MEM_RLD3_BL {2} + set_component_parameter_value MEM_RLD3_DATA_LATENCY_MODE_ENUM {RLD3_DL_RL16_WL17} + set_component_parameter_value MEM_RLD3_DEPTH_EXPANDED {0} + set_component_parameter_value MEM_RLD3_DM_EN {1} + set_component_parameter_value MEM_RLD3_DQ_PER_DEVICE {36} + set_component_parameter_value MEM_RLD3_ODT_MODE_ENUM {RLD3_ODT_40} + set_component_parameter_value MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM {RLD3_OUTPUT_DRIVE_40} + set_component_parameter_value MEM_RLD3_SPEEDBIN_ENUM {RLD3_SPEEDBIN_093E} + set_component_parameter_value MEM_RLD3_TCKDK_MAX_CYC {0.27} + set_component_parameter_value MEM_RLD3_TCKDK_MIN_CYC {-0.27} + set_component_parameter_value MEM_RLD3_TCKQK_MAX_PS {135} + set_component_parameter_value MEM_RLD3_TDH_DC_MV {100} + set_component_parameter_value MEM_RLD3_TDH_PS {5} + set_component_parameter_value MEM_RLD3_TDS_AC_MV {150} + set_component_parameter_value MEM_RLD3_TDS_PS {-30} + set_component_parameter_value MEM_RLD3_TIH_DC_MV {100} + set_component_parameter_value MEM_RLD3_TIH_PS {65} + set_component_parameter_value MEM_RLD3_TIS_AC_MV {150} + set_component_parameter_value MEM_RLD3_TIS_PS {85} + set_component_parameter_value MEM_RLD3_TQH_CYC {0.38} + set_component_parameter_value MEM_RLD3_TQKQ_MAX_PS {75} + set_component_parameter_value MEM_RLD3_T_RC_MODE_ENUM {RLD3_TRC_9} + set_component_parameter_value MEM_RLD3_WIDTH_EXPANDED {0} + set_component_parameter_value MEM_RLD3_WRITE_PROTOCOL_ENUM {RLD3_WRITE_1BANK} + set_component_parameter_value NUM_IPS {1} + set_component_parameter_value PHY_DDR3_CAL_ADDR0 {0} + set_component_parameter_value PHY_DDR3_CAL_ADDR1 {8} + set_component_parameter_value PHY_DDR3_CAL_ENABLE_NON_DES {0} + set_component_parameter_value PHY_DDR3_CONFIG_ENUM {CONFIG_PHY_AND_HARD_CTRL} + set_component_parameter_value PHY_DDR3_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_DDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_DDR3_DEFAULT_IO {1} + set_component_parameter_value PHY_DDR3_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_DDR3_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_DDR3_IO_VOLTAGE {1.5} + set_component_parameter_value PHY_DDR3_MEM_CLK_FREQ_MHZ {1066.667} + set_component_parameter_value PHY_DDR3_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_DDR3_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_DDR3_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_DDR3_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_DDR3_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_DDR3_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_DDR3_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDR3_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_DDR4_ALLOW_72_DQ_WIDTH {0} + set_component_parameter_value PHY_DDR4_CONFIG_ENUM {CONFIG_PHY_AND_HARD_CTRL} + set_component_parameter_value PHY_DDR4_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_DDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_DDR4_DEFAULT_IO {0} + set_component_parameter_value PHY_DDR4_DEFAULT_REF_CLK_FREQ {0} + set_component_parameter_value PHY_DDR4_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_DDR4_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_DDR4_MEM_CLK_FREQ_MHZ {1200.0} + set_component_parameter_value PHY_DDR4_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_DDR4_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_DDR4_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_DDR4_USER_AC_DEEMPHASIS_ENUM {DEEMPHASIS_MODE_OFF} + set_component_parameter_value PHY_DDR4_USER_AC_IO_STD_ENUM {IO_STD_SSTL_12} + set_component_parameter_value PHY_DDR4_USER_AC_MODE_ENUM {OUT_OCT_40_CAL} + set_component_parameter_value PHY_DDR4_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_DDR4_USER_CK_DEEMPHASIS_ENUM {DEEMPHASIS_MODE_OFF} + set_component_parameter_value PHY_DDR4_USER_CK_IO_STD_ENUM {IO_STD_SSTL_12} + set_component_parameter_value PHY_DDR4_USER_CK_MODE_ENUM {OUT_OCT_40_CAL} + set_component_parameter_value PHY_DDR4_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR4_USER_CLAMSHELL_EN {0} + set_component_parameter_value PHY_DDR4_USER_DATA_IN_MODE_ENUM {IN_OCT_60_CAL} + set_component_parameter_value PHY_DDR4_USER_DATA_IO_STD_ENUM {IO_STD_POD_12} + set_component_parameter_value PHY_DDR4_USER_DATA_OUT_DEEMPHASIS_ENUM {DEEMPHASIS_MODE_HIGH} + set_component_parameter_value PHY_DDR4_USER_DATA_OUT_MODE_ENUM {OUT_OCT_40_CAL} + set_component_parameter_value PHY_DDR4_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDR4_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_DDR4_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM {IO_STD_TRUE_DIFF_SIGNALING} + set_component_parameter_value PHY_DDR4_USER_REF_CLK_FREQ_MHZ {33.333} + set_component_parameter_value PHY_DDR4_USER_RZQ_IO_STD_ENUM {IO_STD_CMOS_12} + set_component_parameter_value PHY_DDR4_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_DDRT_2CH_EN {0} + set_component_parameter_value PHY_DDRT_CONFIG_ENUM {CONFIG_PHY_AND_SOFT_CTRL} + set_component_parameter_value PHY_DDRT_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_DDRT_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_DDRT_DEFAULT_IO {1} + set_component_parameter_value PHY_DDRT_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_DDRT_EXPORT_CLK_STP_IF {0} + set_component_parameter_value PHY_DDRT_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_DDRT_I2C_USE_SMC {0} + set_component_parameter_value PHY_DDRT_IC_EN {1} + set_component_parameter_value PHY_DDRT_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_DDRT_MEM_CLK_FREQ_MHZ {1200.0} + set_component_parameter_value PHY_DDRT_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_DDRT_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_DDRT_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_DDRT_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AC_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_DDRT_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_DLL_CORE_UPDN_EN {0} + set_component_parameter_value PHY_DDRT_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_DDRT_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_DDRT_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_DDRT_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_DDRT_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_DDRT_USE_OLD_SMBUS_MULTICOL {0} + set_component_parameter_value PHY_LPDDR3_CONFIG_ENUM {CONFIG_PHY_AND_HARD_CTRL} + set_component_parameter_value PHY_LPDDR3_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_LPDDR3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_LPDDR3_DEFAULT_IO {1} + set_component_parameter_value PHY_LPDDR3_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_LPDDR3_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_LPDDR3_MEM_CLK_FREQ_MHZ {800.0} + set_component_parameter_value PHY_LPDDR3_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_LPDDR3_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_LPDDR3_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_LPDDR3_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_LPDDR3_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_LPDDR3_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_LPDDR3_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_LPDDR3_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_QDR2_CONFIG_ENUM {CONFIG_PHY_AND_SOFT_CTRL} + set_component_parameter_value PHY_QDR2_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_QDR2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_QDR2_DEFAULT_IO {1} + set_component_parameter_value PHY_QDR2_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_QDR2_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_QDR2_IO_VOLTAGE {1.5} + set_component_parameter_value PHY_QDR2_MEM_CLK_FREQ_MHZ {633.333} + set_component_parameter_value PHY_QDR2_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_QDR2_RATE_ENUM {RATE_HALF} + set_component_parameter_value PHY_QDR2_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_QDR2_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_QDR2_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_QDR2_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_QDR2_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR2_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_QDR4_CONFIG_ENUM {CONFIG_PHY_AND_SOFT_CTRL} + set_component_parameter_value PHY_QDR4_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_QDR4_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_QDR4_DEFAULT_IO {1} + set_component_parameter_value PHY_QDR4_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_QDR4_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_QDR4_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_QDR4_MEM_CLK_FREQ_MHZ {1066.667} + set_component_parameter_value PHY_QDR4_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_QDR4_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_QDR4_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_QDR4_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_QDR4_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_QDR4_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_QDR4_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_QDR4_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_RLD2_CONFIG_ENUM {CONFIG_PHY_AND_SOFT_CTRL} + set_component_parameter_value PHY_RLD2_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_RLD2_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_RLD2_DEFAULT_IO {1} + set_component_parameter_value PHY_RLD2_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_RLD2_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_RLD2_IO_VOLTAGE {1.8} + set_component_parameter_value PHY_RLD2_MEM_CLK_FREQ_MHZ {533.333} + set_component_parameter_value PHY_RLD2_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_RLD2_RATE_ENUM {RATE_HALF} + set_component_parameter_value PHY_RLD2_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_RLD2_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_RLD2_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_RLD2_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_RLD2_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD2_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PHY_RLD3_CONFIG_ENUM {CONFIG_PHY_ONLY} + set_component_parameter_value PHY_RLD3_CORE_CLKS_SHARING_ENUM {CORE_CLKS_SHARING_DISABLED} + set_component_parameter_value PHY_RLD3_CORE_CLKS_SHARING_EXPOSE_SLAVE_OUT {0} + set_component_parameter_value PHY_RLD3_DEFAULT_IO {1} + set_component_parameter_value PHY_RLD3_DEFAULT_REF_CLK_FREQ {1} + set_component_parameter_value PHY_RLD3_HPS_ENABLE_EARLY_RELEASE {0} + set_component_parameter_value PHY_RLD3_IO_VOLTAGE {1.2} + set_component_parameter_value PHY_RLD3_MEM_CLK_FREQ_MHZ {1066.667} + set_component_parameter_value PHY_RLD3_MIMIC_HPS_EMIF {0} + set_component_parameter_value PHY_RLD3_RATE_ENUM {RATE_QUARTER} + set_component_parameter_value PHY_RLD3_REF_CLK_JITTER_PS {10.0} + set_component_parameter_value PHY_RLD3_USER_AC_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_AC_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_AC_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_AC_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN {1} + set_component_parameter_value PHY_RLD3_USER_CK_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_CK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_CK_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_CK_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_IN_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_OUT_DEEMPHASIS_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_OUT_MODE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DATA_OUT_SLEW_RATE_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_DLL_CORE_UPDN_EN {1} + set_component_parameter_value PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM {PERIODIC_OCT_RECAL_AUTO} + set_component_parameter_value PHY_RLD3_USER_PING_PONG_EN {0} + set_component_parameter_value PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_REF_CLK_FREQ_MHZ {-1.0} + set_component_parameter_value PHY_RLD3_USER_RZQ_IO_STD_ENUM {unset} + set_component_parameter_value PHY_RLD3_USER_STARTING_VREFIN {70.0} + set_component_parameter_value PLL_ADD_EXTRA_CLKS {0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 {50.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 {0.0} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 {ps} + set_component_parameter_value PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 {ps} + set_component_parameter_value PLL_USER_NUM_OF_EXTRA_CLKS {0} + set_component_parameter_value PROTOCOL_ENUM {PROTOCOL_DDR4} + set_component_parameter_value SHORT_QSYS_INTERFACE_NAMES {1} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation hps_emif + remove_instantiation_interfaces_and_ports + add_instantiation_interface pll_ref_clk clock INPUT + set_instantiation_interface_parameter_value pll_ref_clk clockRate {0} + set_instantiation_interface_parameter_value pll_ref_clk externallyDriven {false} + set_instantiation_interface_parameter_value pll_ref_clk ptfSchematicName {} + add_instantiation_interface_port pll_ref_clk pll_ref_clk clk 1 STD_LOGIC Input + add_instantiation_interface oct conduit INPUT + set_instantiation_interface_parameter_value oct associatedClock {} + set_instantiation_interface_parameter_value oct associatedReset {} + set_instantiation_interface_parameter_value oct prSafe {false} + add_instantiation_interface_port oct oct_rzqin oct_rzqin 1 STD_LOGIC Input + add_instantiation_interface mem conduit INPUT + set_instantiation_interface_parameter_value mem associatedClock {} + set_instantiation_interface_parameter_value mem associatedReset {} + set_instantiation_interface_parameter_value mem prSafe {false} + add_instantiation_interface_port mem mem_ck mem_ck 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_ck_n mem_ck_n 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_a mem_a 17 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_act_n mem_act_n 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_ba mem_ba 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_bg mem_bg 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_cke mem_cke 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_cs_n mem_cs_n 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_odt mem_odt 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_reset_n mem_reset_n 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_par mem_par 1 STD_LOGIC_VECTOR Output + add_instantiation_interface_port mem mem_alert_n mem_alert_n 1 STD_LOGIC_VECTOR Input + add_instantiation_interface_port mem mem_dqs mem_dqs 8 STD_LOGIC_VECTOR Bidir + add_instantiation_interface_port mem mem_dqs_n mem_dqs_n 8 STD_LOGIC_VECTOR Bidir + add_instantiation_interface_port mem mem_dq mem_dq 64 STD_LOGIC_VECTOR Bidir + add_instantiation_interface_port mem mem_dbi_n mem_dbi_n 8 STD_LOGIC_VECTOR Bidir + add_instantiation_interface hps_emif conduit INPUT + set_instantiation_interface_parameter_value hps_emif associatedClock {} + set_instantiation_interface_parameter_value hps_emif associatedReset {} + set_instantiation_interface_parameter_value hps_emif prSafe {false} + add_instantiation_interface_port hps_emif hps_to_emif hps_to_emif 4096 STD_LOGIC_VECTOR Input + add_instantiation_interface_port hps_emif emif_to_hps emif_to_hps 4096 STD_LOGIC_VECTOR Output + add_instantiation_interface_port hps_emif hps_to_emif_gp gp_to_emif 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port hps_emif emif_to_hps_gp emif_to_gp 1 STD_LOGIC_VECTOR Output + add_instantiation_interface emif_calbus conduit INPUT + set_instantiation_interface_parameter_value emif_calbus associatedClock {emif_calbus_clk} + set_instantiation_interface_parameter_value emif_calbus associatedReset {} + set_instantiation_interface_parameter_value emif_calbus prSafe {false} + add_instantiation_interface_port emif_calbus calbus_read calbus_read 1 STD_LOGIC Input + add_instantiation_interface_port emif_calbus calbus_write calbus_write 1 STD_LOGIC Input + add_instantiation_interface_port emif_calbus calbus_address calbus_address 20 STD_LOGIC_VECTOR Input + add_instantiation_interface_port emif_calbus calbus_wdata calbus_wdata 32 STD_LOGIC_VECTOR Input + add_instantiation_interface_port emif_calbus calbus_rdata calbus_rdata 32 STD_LOGIC_VECTOR Output + add_instantiation_interface_port emif_calbus calbus_seq_param_tbl calbus_seq_param_tbl 4096 STD_LOGIC_VECTOR Output + add_instantiation_interface emif_calbus_clk clock INPUT + set_instantiation_interface_parameter_value emif_calbus_clk clockRate {0} + set_instantiation_interface_parameter_value emif_calbus_clk externallyDriven {false} + set_instantiation_interface_parameter_value emif_calbus_clk ptfSchematicName {} + add_instantiation_interface_port emif_calbus_clk calbus_clk clk 1 STD_LOGIC Input + save_instantiation + add_component init_done ip/system/init_done.ip altera_s10_user_rst_clkgate init_done 19.4.7 + load_component init_done + set_component_parameter_value outputType {Conduit Interface} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation init_done + remove_instantiation_interfaces_and_ports + add_instantiation_interface ninit_done conduit INPUT + set_instantiation_interface_parameter_value ninit_done associatedClock {} + set_instantiation_interface_parameter_value ninit_done associatedReset {} + set_instantiation_interface_parameter_value ninit_done prSafe {false} + add_instantiation_interface_port ninit_done ninit_done ninit_done 1 STD_LOGIC Output + save_instantiation + add_component system_intel_cache_coherency_translator ip/system/system_intel_cache_coherency_translator.ip intel_cache_coherency_translator system_intel_cache_coherency_translator 1.0.3 + load_component system_intel_cache_coherency_translator + set_component_parameter_value ADDR_WIDTH {32} + set_component_parameter_value ARBAR_OVERRIDE {0} + set_component_parameter_value ARCACHE_OVERRIDE {0} + set_component_parameter_value ARCACHE_OVERRIDE_EN {1} + set_component_parameter_value ARDOMAIN_OVERRIDE {1} + set_component_parameter_value ARSNOOP_OVERRIDE {0} + set_component_parameter_value AWBAR_OVERRIDE {0} + set_component_parameter_value AWCACHE_OVERRIDE {0} + set_component_parameter_value AWCACHE_OVERRIDE_EN {1} + set_component_parameter_value AWDOMAIN_OVERRIDE {1} + set_component_parameter_value AWSNOOP_OVERRIDE {0} + set_component_parameter_value AXM_ID_WIDTH {5} + set_component_parameter_value AXS_ID_WIDTH {5} + set_component_parameter_value AxPROT_OVERRIDE {3} + set_component_parameter_value AxPROT_OVERRIDE_EN {1} + set_component_parameter_value AxUSER_SELECTION {0} + set_component_parameter_value CONTROL_INTERFACE {0} + set_component_parameter_value CombinedIssuingCapability {16} + set_component_parameter_value DATA_WIDTH {128} + set_component_parameter_value ReadIssuingCapability {8} + set_component_parameter_value WriteIssuingCapability {8} + set_component_project_property HIDE_FROM_IP_CATALOG {false} + save_component + load_instantiation system_intel_cache_coherency_translator + remove_instantiation_interfaces_and_ports + add_instantiation_interface clock clock INPUT + set_instantiation_interface_parameter_value clock clockRate {0} + set_instantiation_interface_parameter_value clock externallyDriven {false} + set_instantiation_interface_parameter_value clock ptfSchematicName {} + add_instantiation_interface_port clock clk clk 1 STD_LOGIC Input + add_instantiation_interface reset reset INPUT + set_instantiation_interface_parameter_value reset associatedClock {clock} + set_instantiation_interface_parameter_value reset synchronousEdges {DEASSERT} + add_instantiation_interface_port reset reset reset 1 STD_LOGIC Input + add_instantiation_interface m0 acelite OUTPUT + set_instantiation_interface_parameter_value m0 associatedClock {clock} + set_instantiation_interface_parameter_value m0 associatedReset {reset} + set_instantiation_interface_parameter_value m0 combinedIssuingCapability {1} + set_instantiation_interface_parameter_value m0 issuesFIXEDBursts {true} + set_instantiation_interface_parameter_value m0 issuesINCRBursts {true} + set_instantiation_interface_parameter_value m0 issuesWRAPBursts {true} + set_instantiation_interface_parameter_value m0 maximumOutstandingReads {1} + set_instantiation_interface_parameter_value m0 maximumOutstandingTransactions {1} + set_instantiation_interface_parameter_value m0 maximumOutstandingWrites {1} + set_instantiation_interface_parameter_value m0 poison {false} + set_instantiation_interface_parameter_value m0 readIssuingCapability {1} + set_instantiation_interface_parameter_value m0 traceSignals {false} + set_instantiation_interface_parameter_value m0 trustzoneAware {true} + set_instantiation_interface_parameter_value m0 uniqueIdSupport {false} + set_instantiation_interface_parameter_value m0 wakeupSignals {false} + set_instantiation_interface_parameter_value m0 writeIssuingCapability {1} + add_instantiation_interface_port m0 axm_m0_araddr araddr 32 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_arburst arburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_arcache arcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_arid arid 5 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_arlen arlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_arlock arlock 1 STD_LOGIC Output + add_instantiation_interface_port m0 axm_m0_arprot arprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_arqos arqos 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_arready arready 1 STD_LOGIC Input + add_instantiation_interface_port m0 axm_m0_arsize arsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_arvalid arvalid 1 STD_LOGIC Output + add_instantiation_interface_port m0 axm_m0_arsnoop arsnoop 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_ardomain ardomain 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_arbar arbar 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_aruser aruser 23 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awaddr awaddr 32 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awburst awburst 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awcache awcache 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awid awid 5 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awlen awlen 8 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awlock awlock 1 STD_LOGIC Output + add_instantiation_interface_port m0 axm_m0_awprot awprot 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awready awready 1 STD_LOGIC Input + add_instantiation_interface_port m0 axm_m0_awsize awsize 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awvalid awvalid 1 STD_LOGIC Output + add_instantiation_interface_port m0 axm_m0_awqos awqos 4 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awuser awuser 23 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_bid bid 5 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 axm_m0_bready bready 1 STD_LOGIC Output + add_instantiation_interface_port m0 axm_m0_bresp bresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 axm_m0_bvalid bvalid 1 STD_LOGIC Input + add_instantiation_interface_port m0 axm_m0_rdata rdata 128 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 axm_m0_rid rid 5 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 axm_m0_rlast rlast 1 STD_LOGIC Input + add_instantiation_interface_port m0 axm_m0_rready rready 1 STD_LOGIC Output + add_instantiation_interface_port m0 axm_m0_rresp rresp 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port m0 axm_m0_rvalid rvalid 1 STD_LOGIC Input + add_instantiation_interface_port m0 axm_m0_wdata wdata 128 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_wlast wlast 1 STD_LOGIC Output + add_instantiation_interface_port m0 axm_m0_wready wready 1 STD_LOGIC Input + add_instantiation_interface_port m0 axm_m0_wstrb wstrb 16 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_wvalid wvalid 1 STD_LOGIC Output + add_instantiation_interface_port m0 axm_m0_awsnoop awsnoop 3 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awdomain awdomain 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port m0 axm_m0_awbar awbar 2 STD_LOGIC_VECTOR Output + add_instantiation_interface s0 axi4 INPUT + set_instantiation_interface_parameter_value s0 associatedClock {clock} + set_instantiation_interface_parameter_value s0 associatedReset {reset} + set_instantiation_interface_parameter_value s0 bridgesToMaster {m0} + set_instantiation_interface_parameter_value s0 combinedAcceptanceCapability {1} + set_instantiation_interface_parameter_value s0 dfhFeatureGuid {0} + set_instantiation_interface_parameter_value s0 dfhFeatureId {35} + set_instantiation_interface_parameter_value s0 dfhFeatureMajorVersion {0} + set_instantiation_interface_parameter_value s0 dfhFeatureMinorVersion {0} + set_instantiation_interface_parameter_value s0 dfhFeatureType {3} + set_instantiation_interface_parameter_value s0 dfhGroupId {0} + set_instantiation_interface_parameter_value s0 dfhParameterData {} + set_instantiation_interface_parameter_value s0 dfhParameterDataLength {} + set_instantiation_interface_parameter_value s0 dfhParameterId {} + set_instantiation_interface_parameter_value s0 dfhParameterName {} + set_instantiation_interface_parameter_value s0 dfhParameterVersion {} + set_instantiation_interface_parameter_value s0 maximumOutstandingReads {1} + set_instantiation_interface_parameter_value s0 maximumOutstandingTransactions {1} + set_instantiation_interface_parameter_value s0 maximumOutstandingWrites {1} + set_instantiation_interface_parameter_value s0 poison {false} + set_instantiation_interface_parameter_value s0 readAcceptanceCapability {1} + set_instantiation_interface_parameter_value s0 readDataReorderingDepth {8} + set_instantiation_interface_parameter_value s0 traceSignals {false} + set_instantiation_interface_parameter_value s0 trustzoneAware {true} + set_instantiation_interface_parameter_value s0 uniqueIdSupport {false} + set_instantiation_interface_parameter_value s0 wakeupSignals {false} + set_instantiation_interface_parameter_value s0 writeAcceptanceCapability {1} + set_instantiation_interface_sysinfo_parameter_value s0 address_map {} + set_instantiation_interface_sysinfo_parameter_value s0 address_width {} + set_instantiation_interface_sysinfo_parameter_value s0 max_slave_data_width {} + add_instantiation_interface_port s0 axs_s0_araddr araddr 32 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_arburst arburst 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_arcache arcache 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_arid arid 5 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_arlen arlen 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_arlock arlock 1 STD_LOGIC Input + add_instantiation_interface_port s0 axs_s0_arprot arprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_arready arready 1 STD_LOGIC Output + add_instantiation_interface_port s0 axs_s0_arsize arsize 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_arvalid arvalid 1 STD_LOGIC Input + add_instantiation_interface_port s0 axs_s0_awaddr awaddr 32 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_awburst awburst 2 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_awcache awcache 4 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_awid awid 5 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_awlen awlen 8 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_awlock awlock 1 STD_LOGIC Input + add_instantiation_interface_port s0 axs_s0_awprot awprot 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_awready awready 1 STD_LOGIC Output + add_instantiation_interface_port s0 axs_s0_awsize awsize 3 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_awvalid awvalid 1 STD_LOGIC Input + add_instantiation_interface_port s0 axs_s0_bid bid 5 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 axs_s0_bready bready 1 STD_LOGIC Input + add_instantiation_interface_port s0 axs_s0_bresp bresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 axs_s0_bvalid bvalid 1 STD_LOGIC Output + add_instantiation_interface_port s0 axs_s0_rdata rdata 128 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 axs_s0_rid rid 5 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 axs_s0_rlast rlast 1 STD_LOGIC Output + add_instantiation_interface_port s0 axs_s0_rready rready 1 STD_LOGIC Input + add_instantiation_interface_port s0 axs_s0_rresp rresp 2 STD_LOGIC_VECTOR Output + add_instantiation_interface_port s0 axs_s0_rvalid rvalid 1 STD_LOGIC Output + add_instantiation_interface_port s0 axs_s0_wdata wdata 128 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_wlast wlast 1 STD_LOGIC Input + add_instantiation_interface_port s0 axs_s0_wready wready 1 STD_LOGIC Output + add_instantiation_interface_port s0 axs_s0_wstrb wstrb 16 STD_LOGIC_VECTOR Input + add_instantiation_interface_port s0 axs_s0_wvalid wvalid 1 STD_LOGIC Input + save_instantiation + + # add wirelevel expressions + + # preserve ports for debug + + # add the connections + add_connection hps_emif.hps_emif/hps.hps_emif + set_connection_parameter_value hps_emif.hps_emif/hps.hps_emif endPort {} + set_connection_parameter_value hps_emif.hps_emif/hps.hps_emif endPortLSB {0} + set_connection_parameter_value hps_emif.hps_emif/hps.hps_emif startPort {} + set_connection_parameter_value hps_emif.hps_emif/hps.hps_emif startPortLSB {0} + set_connection_parameter_value hps_emif.hps_emif/hps.hps_emif width {0} + add_connection system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave addressMapSysInfo {} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave addressWidthSysInfo {} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave arbitrationPriority {1} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave baseAddress {0x0000} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave defaultConnection {0} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave domainAlias {} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.burstAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.clockCrossingAdapter {HANDSHAKE} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.enableAllPipelines {FALSE} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.enableEccProtection {FALSE} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.enableInstrumentation {FALSE} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.enableOutOfOrderSupport {FALSE} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.insertDefaultSlave {FALSE} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.interconnectResetSource {DEFAULT} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.interconnectType {STANDARD} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.maxAdditionalLatency {1} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.optimizeRdFifoSize {FALSE} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.piplineType {PIPELINE_STAGE} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.responseFifoType {REGISTER_BASED} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.syncResets {TRUE} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave qsys_mm.widthAdapterImplementation {GENERIC_CONVERTER} + set_connection_parameter_value system_intel_cache_coherency_translator.m0/hps.f2h_axi_slave slaveDataWidthSysInfo {-1} + + # add the exports + set_interface_property hps_h2f_sdmmc_interrupt EXPORT_OF hps.h2f_sdmmc_interrupt + set_interface_property hps_hps_io EXPORT_OF hps.hps_io + set_interface_property h2f_reset EXPORT_OF hps.h2f_reset + set_interface_property hps_h2f_axi_clock EXPORT_OF hps.h2f_axi_clock + set_interface_property hps_h2f_axi_reset EXPORT_OF hps.h2f_axi_reset + set_interface_property hps_h2f_axi_master EXPORT_OF hps.h2f_axi_master + set_interface_property hps_h2f_lw_axi_clock EXPORT_OF hps.h2f_lw_axi_clock + set_interface_property hps_h2f_lw_axi_reset EXPORT_OF hps.h2f_lw_axi_reset + set_interface_property hps_h2f_lw_axi_master EXPORT_OF hps.h2f_lw_axi_master + set_interface_property hps_f2h_axi_clock EXPORT_OF hps.f2h_axi_clock + set_interface_property hps_f2h_axi_reset EXPORT_OF hps.f2h_axi_reset + set_interface_property hps_emif_pll_ref_clk EXPORT_OF hps_emif.pll_ref_clk + set_interface_property hps_emif_oct EXPORT_OF hps_emif.oct + set_interface_property hps_emif_mem EXPORT_OF hps_emif.mem + set_interface_property hps_emif_emif_calbus EXPORT_OF hps_emif.emif_calbus + set_interface_property hps_emif_emif_calbus_clk EXPORT_OF hps_emif.emif_calbus_clk + set_interface_property ninit_done EXPORT_OF init_done.ninit_done + set_interface_property system_intel_cache_coherency_translator_clock EXPORT_OF system_intel_cache_coherency_translator.clock + set_interface_property system_intel_cache_coherency_translator_reset EXPORT_OF system_intel_cache_coherency_translator.reset + set_interface_property system_intel_cache_coherency_translator_s0 EXPORT_OF system_intel_cache_coherency_translator.s0 + + # set values for exposed HDL parameters + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.burstAdapterImplementation GENERIC_CONVERTER + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.clockCrossingAdapter HANDSHAKE + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.enableAllPipelines FALSE + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.enableEccProtection FALSE + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.enableInstrumentation FALSE + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.enableOutOfOrderSupport FALSE + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.insertDefaultSlave FALSE + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.interconnectResetSource DEFAULT + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.interconnectType STANDARD + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.maxAdditionalLatency 1 + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.optimizeRdFifoSize FALSE + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.piplineType PIPELINE_STAGE + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.responseFifoType REGISTER_BASED + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.syncResets TRUE + set_domain_assignment system_intel_cache_coherency_translator.m0 qsys_mm.widthAdapterImplementation GENERIC_CONVERTER + + # set the the module properties + set_module_property BONUS_DATA { + + + + + + + + + + + + + + + + + + + + +} + set_module_property FILE {system.qsys} + set_module_property GENERATION_ID {0x00000000} + set_module_property NAME {system} + + # save the system + sync_sysinfo_parameters + save_system system +} + +proc do_set_exported_interface_sysinfo_parameters {} { +} + +# create all the systems, from bottom up +do_create_system + +# set system info parameters on exported interface, from bottom up +do_set_exported_interface_sysinfo_parameters diff --git a/corev_apu/altera/ip/io_pll.tcl b/corev_apu/altera/ip/io_pll.tcl index ea1e4b29869..c67e16ae36b 100644 --- a/corev_apu/altera/ip/io_pll.tcl +++ b/corev_apu/altera/ip/io_pll.tcl @@ -143,7 +143,7 @@ proc do_create_io_pll {} { set_instance_parameter_value iopll_0 {gui_new_mif_file_path} {~/pll.mif} set_instance_parameter_value iopll_0 {gui_number_of_clocks} {5} set_instance_parameter_value iopll_0 {gui_operation_mode} {direct} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {200.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {100.0} set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {125.0} set_instance_parameter_value iopll_0 {gui_output_clock_frequency10} {100.0} set_instance_parameter_value iopll_0 {gui_output_clock_frequency11} {100.0} @@ -161,7 +161,7 @@ proc do_create_io_pll {} { set_instance_parameter_value iopll_0 {gui_output_clock_frequency7} {100.0} set_instance_parameter_value iopll_0 {gui_output_clock_frequency8} {100.0} set_instance_parameter_value iopll_0 {gui_output_clock_frequency9} {100.0} - set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {5000.0} + set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {10000.0} set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {8000.0} set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps10} {10000.0} set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps11} {10000.0} diff --git a/corev_apu/altera/ip_files.csv b/corev_apu/altera/ip_files.csv index 9bdb7ff77e2..4b5063b2742 100644 --- a/corev_apu/altera/ip_files.csv +++ b/corev_apu/altera/ip_files.csv @@ -7,3 +7,7 @@ ./emif_cal.ip ./vJTAG.ip ./cva6_intel_jtag_uart_0.ip +./ip/system/hps.ip +./ip/system/hps_emif.ip +./ip/system/init_done.ip +./ip/system/system_intel_cache_coherency_translator.ip diff --git a/corev_apu/altera/loc_constraints.csv b/corev_apu/altera/loc_constraints.csv index 0ac21bf1c04..72b60fe972e 100644 --- a/corev_apu/altera/loc_constraints.csv +++ b/corev_apu/altera/loc_constraints.csv @@ -137,3 +137,134 @@ PIN_N34 -to ddr4_act_n PIN_P33 -to ddr4_reset_n PIN_AA6 -to tx PIN_F1 -to rx +PIN_L10 -to emif_hps_pll_ref_clk_p +PIN_M9 -to emif_hps_oct_oct_rzqin +PIN_T17 -to emif_hps_mem_mem_a[0] +PIN_V17 -to emif_hps_mem_mem_a[1] +PIN_U16 -to emif_hps_mem_mem_a[2] +PIN_W16 -to emif_hps_mem_mem_a[3] +PIN_T15 -to emif_hps_mem_mem_a[4] +PIN_V15 -to emif_hps_mem_mem_a[5] +PIN_U14 -to emif_hps_mem_mem_a[6] +PIN_W14 -to emif_hps_mem_mem_a[7] +PIN_T13 -to emif_hps_mem_mem_a[8] +PIN_V13 -to emif_hps_mem_mem_a[9] +PIN_U12 -to emif_hps_mem_mem_a[10] +PIN_W12 -to emif_hps_mem_mem_a[11] +PIN_P9 -to emif_hps_mem_mem_a[12] +PIN_L8 -to emif_hps_mem_mem_a[13] +PIN_N8 -to emif_hps_mem_mem_a[14] +PIN_M7 -to emif_hps_mem_mem_a[15] +PIN_P7 -to emif_hps_mem_mem_a[16] +PIN_N6 -to emif_hps_mem_mem_ba[0] +PIN_M5 -to emif_hps_mem_mem_ba[1] +PIN_P5 -to emif_hps_mem_mem_bg[0] +PIN_N16 -to emif_hps_mem_mem_act_n +PIN_L6 -to emif_hps_mem_mem_alert_n +PIN_M13 -to emif_hps_mem_mem_ck[0] +PIN_P13 -to emif_hps_mem_mem_ck_n[0] +PIN_L14 -to emif_hps_mem_mem_cke[0] +PIN_L16 -to emif_hps_mem_mem_cs_n[0] +PIN_M15 -to emif_hps_mem_mem_odt[0] +PIN_N12 -to emif_hps_mem_mem_par +PIN_P17 -to emif_hps_mem_mem_reset_n +PIN_A8 -to emif_hps_mem_mem_dqs[0] +PIN_G8 -to emif_hps_mem_mem_dqs[1] +PIN_F15 -to emif_hps_mem_mem_dqs[2] +PIN_B15 -to emif_hps_mem_mem_dqs[3] +PIN_U22 -to emif_hps_mem_mem_dqs[4] +PIN_L22 -to emif_hps_mem_mem_dqs[5] +PIN_M29 -to emif_hps_mem_mem_dqs[6] +PIN_T29 -to emif_hps_mem_mem_dqs[7] +PIN_U8 -to emif_hps_mem_mem_dqs[8] +PIN_C8 -to emif_hps_mem_mem_dqs_n[0] +PIN_J8 -to emif_hps_mem_mem_dqs_n[1] +PIN_H15 -to emif_hps_mem_mem_dqs_n[2] +PIN_D15 -to emif_hps_mem_mem_dqs_n[3] +PIN_W22 -to emif_hps_mem_mem_dqs_n[4] +PIN_N22 -to emif_hps_mem_mem_dqs_n[5] +PIN_P29 -to emif_hps_mem_mem_dqs_n[6] +PIN_V29 -to emif_hps_mem_mem_dqs_n[7] +PIN_W8 -to emif_hps_mem_mem_dqs_n[8] +PIN_B7 -to emif_hps_mem_mem_dbi_n[0] +PIN_F7 -to emif_hps_mem_mem_dbi_n[1] +PIN_G14 -to emif_hps_mem_mem_dbi_n[2] +PIN_A14 -to emif_hps_mem_mem_dbi_n[3] +PIN_T21 -to emif_hps_mem_mem_dbi_n[4] +PIN_M21 -to emif_hps_mem_mem_dbi_n[5] +PIN_L28 -to emif_hps_mem_mem_dbi_n[6] +PIN_U28 -to emif_hps_mem_mem_dbi_n[7] +PIN_T7 -to emif_hps_mem_mem_dbi_n[8] +PIN_A10 -to emif_hps_mem_mem_dq[0] +PIN_C10 -to emif_hps_mem_mem_dq[1] +PIN_B9 -to emif_hps_mem_mem_dq[2] +PIN_D9 -to emif_hps_mem_mem_dq[3] +PIN_A6 -to emif_hps_mem_mem_dq[4] +PIN_B5 -to emif_hps_mem_mem_dq[5] +PIN_C6 -to emif_hps_mem_mem_dq[6] +PIN_D5 -to emif_hps_mem_mem_dq[7] +PIN_G10 -to emif_hps_mem_mem_dq[8] +PIN_J10 -to emif_hps_mem_mem_dq[9] +PIN_F9 -to emif_hps_mem_mem_dq[10] +PIN_H9 -to emif_hps_mem_mem_dq[11] +PIN_G6 -to emif_hps_mem_mem_dq[12] +PIN_J6 -to emif_hps_mem_mem_dq[13] +PIN_F5 -to emif_hps_mem_mem_dq[14] +PIN_H5 -to emif_hps_mem_mem_dq[15] +PIN_F17 -to emif_hps_mem_mem_dq[16] +PIN_H17 -to emif_hps_mem_mem_dq[17] +PIN_G16 -to emif_hps_mem_mem_dq[18] +PIN_J16 -to emif_hps_mem_mem_dq[19] +PIN_F13 -to emif_hps_mem_mem_dq[20] +PIN_J12 -to emif_hps_mem_mem_dq[21] +PIN_H13 -to emif_hps_mem_mem_dq[22] +PIN_G12 -to emif_hps_mem_mem_dq[23] +PIN_B17 -to emif_hps_mem_mem_dq[24] +PIN_D17 -to emif_hps_mem_mem_dq[25] +PIN_A16 -to emif_hps_mem_mem_dq[26] +PIN_C16 -to emif_hps_mem_mem_dq[27] +PIN_B13 -to emif_hps_mem_mem_dq[28] +PIN_D13 -to emif_hps_mem_mem_dq[29] +PIN_A12 -to emif_hps_mem_mem_dq[30] +PIN_C12 -to emif_hps_mem_mem_dq[31] +PIN_U24 -to emif_hps_mem_mem_dq[32] +PIN_W24 -to emif_hps_mem_mem_dq[33] +PIN_T23 -to emif_hps_mem_mem_dq[34] +PIN_V23 -to emif_hps_mem_mem_dq[35] +PIN_U20 -to emif_hps_mem_mem_dq[36] +PIN_W20 -to emif_hps_mem_mem_dq[37] +PIN_T19 -to emif_hps_mem_mem_dq[38] +PIN_V19 -to emif_hps_mem_mem_dq[39] +PIN_L24 -to emif_hps_mem_mem_dq[40] +PIN_N24 -to emif_hps_mem_mem_dq[41] +PIN_M23 -to emif_hps_mem_mem_dq[42] +PIN_P23 -to emif_hps_mem_mem_dq[43] +PIN_L20 -to emif_hps_mem_mem_dq[44] +PIN_P19 -to emif_hps_mem_mem_dq[45] +PIN_N20 -to emif_hps_mem_mem_dq[46] +PIN_M19 -to emif_hps_mem_mem_dq[47] +PIN_M31 -to emif_hps_mem_mem_dq[48] +PIN_P31 -to emif_hps_mem_mem_dq[49] +PIN_L30 -to emif_hps_mem_mem_dq[50] +PIN_N30 -to emif_hps_mem_mem_dq[51] +PIN_M27 -to emif_hps_mem_mem_dq[52] +PIN_P27 -to emif_hps_mem_mem_dq[53] +PIN_L26 -to emif_hps_mem_mem_dq[54] +PIN_N26 -to emif_hps_mem_mem_dq[55] +PIN_T31 -to emif_hps_mem_mem_dq[56] +PIN_V31 -to emif_hps_mem_mem_dq[57] +PIN_U30 -to emif_hps_mem_mem_dq[58] +PIN_W30 -to emif_hps_mem_mem_dq[59] +PIN_T27 -to emif_hps_mem_mem_dq[60] +PIN_W26 -to emif_hps_mem_mem_dq[61] +PIN_V27 -to emif_hps_mem_mem_dq[62] +PIN_U26 -to emif_hps_mem_mem_dq[63] +PIN_U10 -to emif_hps_mem_mem_dq[64] +PIN_W10 -to emif_hps_mem_mem_dq[65] +PIN_T9 -to emif_hps_mem_mem_dq[66] +PIN_V9 -to emif_hps_mem_mem_dq[67] +PIN_U6 -to emif_hps_mem_mem_dq[68] +PIN_W6 -to emif_hps_mem_mem_dq[69] +PIN_T5 -to emif_hps_mem_mem_dq[70] +PIN_V5 -to emif_hps_mem_mem_dq[71] +PIN_M17 -to emif_hps_mem_mem_bg[1] -comment IOBANK_3D diff --git a/corev_apu/altera/settings.csv b/corev_apu/altera/settings.csv index b069925db44..9ee2e8d1486 100644 --- a/corev_apu/altera/settings.csv +++ b/corev_apu/altera/settings.csv @@ -43,3 +43,24 @@ FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS GLOBAL_PLACEMENT_EFFORT "MAXIMUM EFFORT" QII_AUTO_PACKED_REGISTERS SPARSE OPTIMIZATION_TECHNIQUE SPEED +AUTO_RESTART_CONFIGURATION OFF +USE_PWRMGT_SCL SDM_IO14 +USE_PWRMGT_SDA SDM_IO11 +USE_CONF_DONE SDM_IO16 +USE_INIT_DONE SDM_IO0 +USE_CVP_CONFDONE SDM_IO10 +POWER_APPLY_THERMAL_MARGIN ADDITIONAL +PWRMGT_BUS_SPEED_MODE "100 KHZ" +PWRMGT_SLAVE_DEVICE_TYPE ED8401 +PWRMGT_SLAVE_DEVICE0_ADDRESS 47 +PWRMGT_SLAVE_DEVICE1_ADDRESS 00 +PWRMGT_SLAVE_DEVICE2_ADDRESS 00 +PWRMGT_SLAVE_DEVICE3_ADDRESS 00 +PWRMGT_SLAVE_DEVICE4_ADDRESS 00 +PWRMGT_SLAVE_DEVICE5_ADDRESS 00 +PWRMGT_SLAVE_DEVICE6_ADDRESS 00 +PWRMGT_SLAVE_DEVICE7_ADDRESS 00 +PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS +PWRMGT_PAGE_COMMAND_ENABLE OFF +PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" +PWRMGT_LINEAR_FORMAT_N "-13" \ No newline at end of file diff --git a/corev_apu/altera/src/cva6_altera.sv b/corev_apu/altera/src/cva6_altera.sv index f047c330679..226a4cb767d 100644 --- a/corev_apu/altera/src/cva6_altera.sv +++ b/corev_apu/altera/src/cva6_altera.sv @@ -44,7 +44,57 @@ module cva6_altera ( input logic [ 0:0] ddr4_alert_n, input logic oct_rzqin , - output logic [ 3:0] led + output logic [ 3:0] led , + //HPS +// HPS EMIF +output wire [0:0] emif_hps_mem_mem_ck, +output wire [0:0] emif_hps_mem_mem_ck_n, +output wire [16:0] emif_hps_mem_mem_a, +output wire [0:0] emif_hps_mem_mem_act_n, +output wire [1:0] emif_hps_mem_mem_ba, +output wire [1:0] emif_hps_mem_mem_bg, +output wire [0:0] emif_hps_mem_mem_cke, +output wire [0:0] emif_hps_mem_mem_cs_n, +output wire [0:0] emif_hps_mem_mem_odt, +output wire [0:0] emif_hps_mem_mem_reset_n, +output wire [0:0] emif_hps_mem_mem_par, +input wire [0:0] emif_hps_mem_mem_alert_n, +input wire emif_hps_oct_oct_rzqin, +input wire emif_hps_pll_ref_clk_p, +inout wire [8-1:0] emif_hps_mem_mem_dbi_n, +inout wire [64-1:0] emif_hps_mem_mem_dq, +inout wire [8-1:0] emif_hps_mem_mem_dqs, +inout wire [8-1:0] emif_hps_mem_mem_dqs_n, +input wire hps_jtag_tck, +input wire hps_jtag_tms, +output wire hps_jtag_tdo, +input wire hps_jtag_tdi, +output wire hps_sdmmc_CCLK, +inout wire hps_sdmmc_CMD, +inout wire hps_sdmmc_D0, +inout wire hps_sdmmc_D1, +inout wire hps_sdmmc_D2, +inout wire hps_sdmmc_D3, +output wire hps_emac0_TX_CLK, +input wire hps_emac0_RX_CLK, +output wire hps_emac0_TX_CTL, +input wire hps_emac0_RX_CTL, +output wire hps_emac0_TXD0, +output wire hps_emac0_TXD1, +input wire hps_emac0_RXD0, +input wire hps_emac0_RXD1, +output wire hps_emac0_TXD2, +output wire hps_emac0_TXD3, +input wire hps_emac0_RXD2, +input wire hps_emac0_RXD3, +inout wire hps_emac0_MDIO, +output wire hps_emac0_MDC, +input wire hps_uart0_RX, +output wire hps_uart0_TX, +inout wire hps_i2c1_SDA, +inout wire hps_i2c1_SCL, +inout wire hps_gpio1_io0, +input wire hps_ref_clk ); // CVA6 Intel configuration @@ -99,7 +149,7 @@ AXI_BUS #( .AXI_DATA_WIDTH ( AxiDataWidth ), .AXI_ID_WIDTH ( AxiIdWidthSlaves ), .AXI_USER_WIDTH ( AxiUserWidth ) -) master[ariane_soc::NB_PERIPHERALS-1:0](); +) master[ariane_soc::NB_PERIPHERALS:0](); AXI_BUS #( .AXI_ADDR_WIDTH ( CVA6Cfg.XLEN ), @@ -170,7 +220,7 @@ assign rst = ~ddr_sync_reset; // AXI Xbar // --------------- -axi_pkg::xbar_rule_64_t [ariane_soc::NB_PERIPHERALS-1:0] addr_map; +axi_pkg::xbar_rule_64_t [ariane_soc::NB_PERIPHERALS:0] addr_map; assign addr_map = '{ '{ idx: ariane_soc::Debug, start_addr: ariane_soc::DebugBase, end_addr: ariane_soc::DebugBase + ariane_soc::DebugLength }, @@ -182,12 +232,13 @@ assign addr_map = '{ '{ idx: ariane_soc::SPI, start_addr: ariane_soc::SPIBase, end_addr: ariane_soc::SPIBase + ariane_soc::SPILength }, '{ idx: ariane_soc::Ethernet, start_addr: ariane_soc::EthernetBase, end_addr: ariane_soc::EthernetBase + ariane_soc::EthernetLength }, '{ idx: ariane_soc::GPIO, start_addr: ariane_soc::GPIOBase, end_addr: ariane_soc::GPIOBase + ariane_soc::GPIOLength }, - '{ idx: ariane_soc::DRAM, start_addr: ariane_soc::DRAMBase, end_addr: ariane_soc::DRAMBase + ariane_soc::DRAMLength } + '{ idx: ariane_soc::DRAM, start_addr: ariane_soc::DRAMBase, end_addr: ariane_soc::DRAMBase + ariane_soc::DRAMLength }, + '{ idx: ariane_soc::HPS, start_addr: ariane_soc::HPSBase, end_addr: ariane_soc::HPSBase + ariane_soc::HPSLength } }; localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{ NoSlvPorts: ariane_soc::NrSlaves, - NoMstPorts: ariane_soc::NB_PERIPHERALS, + NoMstPorts: ariane_soc::NB_PERIPHERALS+1, MaxMstTrans: 1, // Probably requires update MaxSlvTrans: 1, // Probably requires update FallThrough: 1'b0, @@ -197,7 +248,7 @@ localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{ UniqueIds: 1'b0, AxiAddrWidth: AxiAddrWidth, AxiDataWidth: AxiDataWidth, - NoAddrRules: ariane_soc::NB_PERIPHERALS + NoAddrRules: ariane_soc::NB_PERIPHERALS+1 }; axi_xbar_intf #( @@ -339,7 +390,7 @@ axi2mem #( .data_i ( dm_slave_rdata ) ); -if (CVA6Cfg.XLEN==32 ) begin +if (CVA6Cfg.IS_XLEN32) begin assign master_to_dm[0].aw_user = '0; assign master_to_dm[0].w_user = '0; @@ -437,60 +488,60 @@ if (CVA6Cfg.XLEN==32 ) begin end else begin - assign master[ariane_soc::Debug].aw_id = master_to_dm[0].aw_id; - assign master[ariane_soc::Debug].aw_addr = master_to_dm[0].aw_addr; - assign master[ariane_soc::Debug].aw_len = master_to_dm[0].aw_len; - assign master[ariane_soc::Debug].aw_size = master_to_dm[0].aw_size; - assign master[ariane_soc::Debug].aw_burst = master_to_dm[0].aw_burst; - assign master[ariane_soc::Debug].aw_lock = master_to_dm[0].aw_lock; - assign master[ariane_soc::Debug].aw_cache = master_to_dm[0].aw_cache; - assign master[ariane_soc::Debug].aw_prot = master_to_dm[0].aw_prot; - assign master[ariane_soc::Debug].aw_qos = master_to_dm[0].aw_qos; - assign master[ariane_soc::Debug].aw_atop = master_to_dm[0].aw_atop; - assign master[ariane_soc::Debug].aw_region = master_to_dm[0].aw_region; - assign master[ariane_soc::Debug].aw_user = master_to_dm[0].aw_user; - assign master[ariane_soc::Debug].aw_valid = master_to_dm[0].aw_valid; - - assign master_to_dm[0].aw_ready =master[ariane_soc::Debug].aw_ready; - - assign master[ariane_soc::Debug].w_data = master_to_dm[0].w_data; - assign master[ariane_soc::Debug].w_strb = master_to_dm[0].w_strb; - assign master[ariane_soc::Debug].w_last = master_to_dm[0].w_last; - assign master[ariane_soc::Debug].w_user = master_to_dm[0].w_user; - assign master[ariane_soc::Debug].w_valid = master_to_dm[0].w_valid; - - assign master_to_dm[0].w_ready =master[ariane_soc::Debug].w_ready; - - assign master_to_dm[0].b_id =master[ariane_soc::Debug].b_id; - assign master_to_dm[0].b_resp =master[ariane_soc::Debug].b_resp; - assign master_to_dm[0].b_user =master[ariane_soc::Debug].b_user; - assign master_to_dm[0].b_valid =master[ariane_soc::Debug].b_valid; - - assign master[ariane_soc::Debug].b_ready = master_to_dm[0].b_ready; - - assign master[ariane_soc::Debug].ar_id = master_to_dm[0].ar_id; - assign master[ariane_soc::Debug].ar_addr = master_to_dm[0].ar_addr; - assign master[ariane_soc::Debug].ar_len = master_to_dm[0].ar_len; - assign master[ariane_soc::Debug].ar_size = master_to_dm[0].ar_size; - assign master[ariane_soc::Debug].ar_burst = master_to_dm[0].ar_burst; - assign master[ariane_soc::Debug].ar_lock = master_to_dm[0].ar_lock; - assign master[ariane_soc::Debug].ar_cache = master_to_dm[0].ar_cache; - assign master[ariane_soc::Debug].ar_prot = master_to_dm[0].ar_prot; - assign master[ariane_soc::Debug].ar_qos = master_to_dm[0].ar_qos; - assign master[ariane_soc::Debug].ar_region = master_to_dm[0].ar_region; - assign master[ariane_soc::Debug].ar_user = master_to_dm[0].ar_user; - assign master[ariane_soc::Debug].ar_valid = master_to_dm[0].ar_valid; - - assign master_to_dm[0].ar_ready =master[ariane_soc::Debug].ar_ready; - - assign master_to_dm[0].r_id =master[ariane_soc::Debug].r_id; - assign master_to_dm[0].r_data =master[ariane_soc::Debug].r_data; - assign master_to_dm[0].r_resp =master[ariane_soc::Debug].r_resp; - assign master_to_dm[0].r_last =master[ariane_soc::Debug].r_last; - assign master_to_dm[0].r_user =master[ariane_soc::Debug].r_user; - assign master_to_dm[0].r_valid =master[ariane_soc::Debug].r_valid; - - assign master[ariane_soc::Debug].r_ready = master_to_dm[0].r_ready; + assign master_to_dm[0].aw_id = master[ariane_soc::Debug].aw_id; + assign master_to_dm[0].aw_addr = master[ariane_soc::Debug].aw_addr; + assign master_to_dm[0].aw_len = master[ariane_soc::Debug].aw_len; + assign master_to_dm[0].aw_size = master[ariane_soc::Debug].aw_size; + assign master_to_dm[0].aw_burst= master[ariane_soc::Debug].aw_burst; + assign master_to_dm[0].aw_lock = master[ariane_soc::Debug].aw_lock; + assign master_to_dm[0].aw_cache= master[ariane_soc::Debug].aw_cache; + assign master_to_dm[0].aw_prot = master[ariane_soc::Debug].aw_prot; + assign master_to_dm[0].aw_qos = master[ariane_soc::Debug].aw_qos; + assign master_to_dm[0].aw_atop = master[ariane_soc::Debug].aw_atop; + assign master_to_dm[0].aw_region = master[ariane_soc::Debug].aw_region; + assign master_to_dm[0].aw_user = master[ariane_soc::Debug].aw_user; + assign master_to_dm[0].aw_valid= master[ariane_soc::Debug].aw_valid; + + assign master[ariane_soc::Debug].aw_ready = master_to_dm[0].aw_ready; + + assign master_to_dm[0].w_data = master[ariane_soc::Debug].w_data; + assign master_to_dm[0].w_strb = master[ariane_soc::Debug].w_strb; + assign master_to_dm[0].w_last = master[ariane_soc::Debug].w_last; + assign master_to_dm[0].w_user = master[ariane_soc::Debug].w_user; + assign master_to_dm[0].w_valid= master[ariane_soc::Debug].w_valid; + + assign master[ariane_soc::Debug].w_ready = master_to_dm[0].w_ready; + + assign master[ariane_soc::Debug].b_id = master_to_dm[0].b_id; + assign master[ariane_soc::Debug].b_resp = master_to_dm[0].b_resp; + assign master[ariane_soc::Debug].b_user = master_to_dm[0].b_user; + assign master[ariane_soc::Debug].b_valid= master_to_dm[0].b_valid; + + assign master_to_dm[0].b_ready = master[ariane_soc::Debug].b_ready; + + assign master_to_dm[0].ar_id = master[ariane_soc::Debug].ar_id; + assign master_to_dm[0].ar_addr = master[ariane_soc::Debug].ar_addr; + assign master_to_dm[0].ar_len = master[ariane_soc::Debug].ar_len; + assign master_to_dm[0].ar_size = master[ariane_soc::Debug].ar_size; + assign master_to_dm[0].ar_burst = master[ariane_soc::Debug].ar_burst; + assign master_to_dm[0].ar_lock = master[ariane_soc::Debug].ar_lock; + assign master_to_dm[0].ar_cache = master[ariane_soc::Debug].ar_cache; + assign master_to_dm[0].ar_prot = master[ariane_soc::Debug].ar_prot; + assign master_to_dm[0].ar_qos = master[ariane_soc::Debug].ar_qos; + assign master_to_dm[0].ar_region = master[ariane_soc::Debug].ar_region; + assign master_to_dm[0].ar_user = master[ariane_soc::Debug].ar_user; + assign master_to_dm[0].ar_valid = master[ariane_soc::Debug].ar_valid; + + assign master[ariane_soc::Debug].ar_ready = master_to_dm[0].ar_ready; + + assign master[ariane_soc::Debug].r_id = master_to_dm[0].r_id; + assign master[ariane_soc::Debug].r_data = master_to_dm[0].r_data; + assign master[ariane_soc::Debug].r_resp = master_to_dm[0].r_resp; + assign master[ariane_soc::Debug].r_last = master_to_dm[0].r_last; + assign master[ariane_soc::Debug].r_user = master_to_dm[0].r_user; + assign master[ariane_soc::Debug].r_valid = master_to_dm[0].r_valid; + + assign master_to_dm[0].r_ready = master[ariane_soc::Debug].r_ready; end @@ -498,7 +549,7 @@ end logic [1:0] axi_adapter_size; -assign axi_adapter_size = (CVA6Cfg.XLEN == 64) ? 2'b11 : 2'b10; +assign axi_adapter_size = CVA6Cfg.IS_XLEN64 ? 2'b11 : 2'b10; axi_adapter #( .CVA6Cfg ( CVA6Cfg ), @@ -527,7 +578,7 @@ axi_adapter #( .axi_resp_i ( dm_axi_m_resp ) ); -if (CVA6Cfg.XLEN==32 ) begin +if (CVA6Cfg.IS_XLEN32) begin logic [31 : 0] dm_master_m_awaddr; logic [31 : 0] dm_master_m_araddr; @@ -720,7 +771,7 @@ axi2mem #( .data_i ( rom_rdata ) ); -if (CVA6Cfg.XLEN==32 ) begin +if (CVA6Cfg.IS_XLEN32) begin bootrom_32 i_bootrom ( .clk_i ( clk ), .req_i ( rom_req ), @@ -744,19 +795,13 @@ end logic clk_200MHz_ref; -AXI_BUS #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_USER_WIDTH ( AxiUserWidth ) -) uart_bus(); cva6_peripherals #( .AxiAddrWidth ( AxiAddrWidth ), .AxiDataWidth ( AxiDataWidth ), .AxiIdWidth ( AxiIdWidthSlaves ), .AxiUserWidth ( AxiUserWidth ), - .InclUART ( 1'b0 ), + .InclUART ( 1'b1 ), .InclGPIO ( 1'b1 ), .InclSPI ( 1'b0 ), .InclEthernet ( 1'b0 ) @@ -765,8 +810,7 @@ cva6_peripherals #( .clk_200MHz_i ( clk_200MHz_ref ), .rst_ni ( ndmreset_n ), .plic ( master[ariane_soc::PLIC] ), - // .uart ( master[ariane_soc::UART] ), - .uart ( uart_bus ), + .uart ( master[ariane_soc::UART] ), .spi ( master[ariane_soc::SPI] ), .gpio ( master[ariane_soc::GPIO] ), .eth_clk_i ( eth_clk ), @@ -785,7 +829,7 @@ cva6_peripherals #( // .eth_mdio, // .eth_mdc, .phy_tx_clk_i ( phy_tx_clk ), - .sd_clk_i ( sd_clk_sys ), + .sd_irq ( sd_irq ), // .spi_clk_o ( spi_clk_o ), // .spi_mosi ( spi_mosi ), // .spi_miso ( spi_miso ), @@ -797,84 +841,6 @@ cva6_peripherals #( -// UART Through JTAG// - -logic uart_amm_ready; -logic uart_amm_read; -logic uart_amm_write; -logic uart_amm_read_n; -logic uart_amm_write_n; -logic uart_amm_chipselect; -logic uart_amm_irq; -logic [0:0] uart_amm_address; -logic [31:0] uart_amm_rdata; -logic [31:0] uart_amm_wdata; - - -assign uart_amm_read_n = ~uart_amm_read; -assign uart_amm_write_n = ~uart_amm_write; - -cva6_intel_jtag_uart_0 uart_i ( - .clk (clk), // input, width = 1, clk.clk - .rst_n (ndmreset_n), // input, width = 1, reset.reset_n - .av_chipselect (uart_amm_chipselect), // input, width = 1, avalon_jtag_slave.chipselect - .av_address (uart_amm_address), // input, width = 1, .address - .av_read_n (uart_amm_read_n), // input, width = 1, .read_n - .av_readdata (uart_amm_rdata), // output, width = 32, .readdata - .av_write_n (uart_amm_write_n), // input, width = 1, .write_n - .av_writedata (uart_amm_wdata), // input, width = 32, .writedata - .av_waitrequest (uart_amm_ready), // output, width = 1, .waitrequest - .av_irq (uart_amm_irq) // output, width = 1, irq.irq -); - -//axi4 to avalon converter -interconnect_altera_mm_interconnect_1920_v5r556a axi_to_avalon_uart ( - .axi_bridge_1_m0_awid (master[ariane_soc::UART].aw_id), // input, width = 8, axi_bridge_1_m0.awid - .axi_bridge_1_m0_awaddr (master[ariane_soc::UART].aw_addr), // input, width = 64, .awaddr - .axi_bridge_1_m0_awlen (master[ariane_soc::UART].aw_len), // input, width = 8, .awlen - .axi_bridge_1_m0_awsize (master[ariane_soc::UART].aw_size), // input, width = 3, .awsize - .axi_bridge_1_m0_awburst (master[ariane_soc::UART].aw_burst), // input, width = 2, .awburst - .axi_bridge_1_m0_awlock (master[ariane_soc::UART].aw_lock), // input, width = 1, .awlock - .axi_bridge_1_m0_awcache (master[ariane_soc::UART].aw_cache), // input, width = 4, .awcache - .axi_bridge_1_m0_awprot (master[ariane_soc::UART].aw_prot), // input, width = 3, .awprot - .axi_bridge_1_m0_awvalid (master[ariane_soc::UART].aw_valid), // input, width = 1, .awvalid - .axi_bridge_1_m0_awready (master[ariane_soc::UART].aw_ready), // output, width = 1, .awready - .axi_bridge_1_m0_wdata (master[ariane_soc::UART].w_data), // input, width = 64, .wdata - .axi_bridge_1_m0_wstrb (master[ariane_soc::UART].w_strb), // input, width = 8, .wstrb - .axi_bridge_1_m0_wlast (master[ariane_soc::UART].w_last), // input, width = 1, .wlast - .axi_bridge_1_m0_wvalid (master[ariane_soc::UART].w_valid), // input, width = 1, .wvalid - .axi_bridge_1_m0_wready (master[ariane_soc::UART].w_ready), // output, width = 1, .wready - .axi_bridge_1_m0_bid (master[ariane_soc::UART].b_id), // output, width = 8, .bid - .axi_bridge_1_m0_bresp (master[ariane_soc::UART].b_resp), // output, width = 2, .bresp - .axi_bridge_1_m0_bvalid (master[ariane_soc::UART].b_valid), // output, width = 1, .bvalid - .axi_bridge_1_m0_bready (master[ariane_soc::UART].b_ready), // input, width = 1, .bready - .axi_bridge_1_m0_arid (master[ariane_soc::UART].ar_id), // input, width = 8, .arid - .axi_bridge_1_m0_araddr (master[ariane_soc::UART].ar_addr), // input, width = 64, .araddr - .axi_bridge_1_m0_arlen (master[ariane_soc::UART].ar_len), // input, width = 8, .arlen - .axi_bridge_1_m0_arsize (master[ariane_soc::UART].ar_size), // input, width = 3, .arsize - .axi_bridge_1_m0_arburst (master[ariane_soc::UART].ar_burst), // input, width = 2, .arburst - .axi_bridge_1_m0_arlock (master[ariane_soc::UART].ar_lock), // input, width = 1, .arlock - .axi_bridge_1_m0_arcache (master[ariane_soc::UART].ar_cache), // input, width = 4, .arcache - .axi_bridge_1_m0_arprot (master[ariane_soc::UART].ar_prot), // input, width = 3, .arprot - .axi_bridge_1_m0_arvalid (master[ariane_soc::UART].ar_valid), // input, width = 1, .arvalid - .axi_bridge_1_m0_arready (master[ariane_soc::UART].ar_ready), // output, width = 1, .arready - .axi_bridge_1_m0_rid (master[ariane_soc::UART].r_id), // output, width = 8, .rid - .axi_bridge_1_m0_rdata (master[ariane_soc::UART].r_data), // output, width = 64, .rdata - .axi_bridge_1_m0_rresp (master[ariane_soc::UART].r_resp), // output, width = 2, .rresp - .axi_bridge_1_m0_rlast (master[ariane_soc::UART].r_last), // output, width = 1, .rlast - .axi_bridge_1_m0_rvalid (master[ariane_soc::UART].r_valid), // output, width = 1, .rvalid - .axi_bridge_1_m0_rready (master[ariane_soc::UART].r_ready), // input, width = 1, .rready - .jtag_uart_0_avalon_jtag_slave_address (uart_amm_address), // output, width = 1, jtag_uart_0_avalon_jtag_slave.address - .jtag_uart_0_avalon_jtag_slave_write (uart_amm_write), // output, width = 1, .write - .jtag_uart_0_avalon_jtag_slave_read (uart_amm_read), // output, width = 1, .read - .jtag_uart_0_avalon_jtag_slave_readdata (uart_amm_rdata), // input, width = 32, .readdata - .jtag_uart_0_avalon_jtag_slave_writedata (uart_amm_wdata), // output, width = 32, .writedata - .jtag_uart_0_avalon_jtag_slave_waitrequest (uart_amm_ready), // input, width = 1, .waitrequest - .jtag_uart_0_avalon_jtag_slave_chipselect (uart_amm_chipselect), // output, width = 1, .chipselect - .axi_bridge_1_clk_reset_reset_bridge_in_reset_reset (~ndmreset_n), // input, width = 1, axi_bridge_1_clk_reset_reset_bridge_in_reset.reset - .axi_bridge_1_m0_translator_clk_reset_reset_bridge_in_reset_reset (~ndmreset_n), // input, width = 1, axi_bridge_1_m0_translator_clk_reset_reset_bridge_in_reset.reset - .emif_fm_0_emif_usr_clk_clk (clk) // input, width = 1, emif_fm_0_emif_usr_clk.clk - ); // --------------------- // Board peripherals @@ -903,13 +869,14 @@ logic [6:0] ddr_sc_amm_burstcount; logic [63:0] ddr_sc_amm_byteenable; logic ddr_sc_amm_readdatavalid; -logic calbus_read, calbus_write, calbus_clk, ddr_pll_locked, ddr_rst_req, ddr_rst_done; -logic [19:0] calbus_addr; -logic [31:0] calbus_wdata; -logic [31:0] calbus_rdata; -logic [4095:0] calbus_seq_param_tbl; +logic calbus_read, calbus_write, calbus_clk, calbus_read1, calbus_write1, calbus_clk1, ddr_pll_locked, ddr_rst_req, ddr_rst_done; +logic [19:0] calbus_addr,calbus_addr1; +logic [31:0] calbus_wdata, calbus_wdata1; +logic [31:0] calbus_rdata, calbus_rdata1; +logic [4095:0] calbus_seq_param_tbl, calbus_seq_param_tbl1; logic cal_success; logic ddr_amm_wait_request; +logic sd_irq; assign ddr_amm_wait_request = ~ddr_amm_ready; @@ -1125,9 +1092,215 @@ emif_cal ddr_calibration ( .calbus_wdata_0 (calbus_wdata), // output, width = 32, .calbus_wdata .calbus_rdata_0 (calbus_rdata), // input, width = 32, .calbus_rdata .calbus_seq_param_tbl_0 (calbus_seq_param_tbl), // input, width = 4096, .calbus_seq_param_tbl - .calbus_clk (calbus_clk) // output, width = 1, emif_calbus_clk.clk -); + + .calbus_read_1 (calbus_read1), // output, width = 1, emif_calbus_1.calbus_read + .calbus_write_1 (calbus_write1), // output, width = 1, .calbus_write + .calbus_address_1 (calbus_addr1), // output, width = 20, .calbus_address + .calbus_wdata_1 (calbus_wdata1), // output, width = 32, .calbus_wdata + .calbus_rdata_1 (calbus_rdata1), // input, width = 32, .calbus_rdata + .calbus_seq_param_tbl_1 (calbus_seq_param_tbl1), // input, width = 4096, .calbus_seq_param_tbl + .calbus_clk (calbus_clk) // output, width = 1, emif_calbus_clk.clk + ); +wire h2f_reset; +wire ninit_done; + +assign system_reset_n = ~h2f_reset & ~ninit_done; + +AXI_BUS #( + .AXI_ADDR_WIDTH ( CVA6Cfg.XLEN ), + .AXI_DATA_WIDTH ( 128 ), + .AXI_ID_WIDTH ( AxiIdWidthSlaves ), + .AXI_USER_WIDTH ( AxiUserWidth ) +) master_to_hps[0:0](); + +axi_dw_adapter #( + .ADDR_WIDTH (CVA6Cfg.XLEN), + .S_DATA_WIDTH (AxiAddrWidth), + .M_DATA_WIDTH (128), + .ID_WIDTH (AxiIdWidthSlaves) +)i_axi_dwidth_converter_hps( + .clk(clk), + .rst(~ndmreset_n), + .s_axi_awid(master[ariane_soc::HPS].aw_id), + .s_axi_awaddr(master[ariane_soc::HPS].aw_addr[31:0]), + .s_axi_awlen(master[ariane_soc::HPS].aw_len), + .s_axi_awsize(master[ariane_soc::HPS].aw_size), + .s_axi_awburst(master[ariane_soc::HPS].aw_burst), + .s_axi_awlock(master[ariane_soc::HPS].aw_lock), + .s_axi_awcache(master[ariane_soc::HPS].aw_cache), + .s_axi_awprot(master[ariane_soc::HPS].aw_prot), + .s_axi_awregion(master[ariane_soc::HPS].aw_region), + .s_axi_awqos(master[ariane_soc::HPS].aw_qos), + .s_axi_awvalid(master[ariane_soc::HPS].aw_valid), + .s_axi_awready(master[ariane_soc::HPS].aw_ready), + .s_axi_wdata(master[ariane_soc::HPS].w_data), + .s_axi_wstrb(master[ariane_soc::HPS].w_strb), + .s_axi_wlast(master[ariane_soc::HPS].w_last), + .s_axi_wvalid(master[ariane_soc::HPS].w_valid), + .s_axi_wready(master[ariane_soc::HPS].w_ready), + .s_axi_bid(master[ariane_soc::HPS].b_id), + .s_axi_bresp(master[ariane_soc::HPS].b_resp), + .s_axi_bvalid(master[ariane_soc::HPS].b_valid), + .s_axi_bready(master[ariane_soc::HPS].b_ready), + .s_axi_arid(master[ariane_soc::HPS].ar_id), + .s_axi_araddr(master[ariane_soc::HPS].ar_addr[31:0]), + .s_axi_arlen(master[ariane_soc::HPS].ar_len), + .s_axi_arsize(master[ariane_soc::HPS].ar_size), + .s_axi_arburst(master[ariane_soc::HPS].ar_burst), + .s_axi_arlock(master[ariane_soc::HPS].ar_lock), + .s_axi_arcache(master[ariane_soc::HPS].ar_cache), + .s_axi_arprot(master[ariane_soc::HPS].ar_prot), + .s_axi_arregion(master[ariane_soc::HPS].ar_region), + .s_axi_arqos(master[ariane_soc::HPS].ar_qos), + .s_axi_arvalid(master[ariane_soc::HPS].ar_valid), + .s_axi_arready(master[ariane_soc::HPS].ar_ready), + .s_axi_rid(master[ariane_soc::HPS].r_id), + .s_axi_rdata(master[ariane_soc::HPS].r_data), + .s_axi_rresp(master[ariane_soc::HPS].r_resp), + .s_axi_rlast(master[ariane_soc::HPS].r_last), + .s_axi_rvalid(master[ariane_soc::HPS].r_valid), + .s_axi_rready(master[ariane_soc::HPS].r_ready), + .m_axi_awaddr(master_to_hps[0].aw_addr), + .m_axi_awlen(master_to_hps[0].aw_len), + .m_axi_awsize(master_to_hps[0].aw_size), + .m_axi_awburst(master_to_hps[0].aw_burst), + .m_axi_awlock(master_to_hps[0].aw_lock), + .m_axi_awcache(master_to_hps[0].aw_cache), + .m_axi_awprot(master_to_hps[0].aw_prot), + .m_axi_awregion(master_to_hps[0].aw_region), + .m_axi_awqos(master_to_hps[0].aw_qos), + .m_axi_awvalid(master_to_hps[0].aw_valid), + .m_axi_awready(master_to_hps[0].aw_ready), + .m_axi_wdata(master_to_hps[0].w_data ), + .m_axi_wstrb(master_to_hps[0].w_strb), + .m_axi_wlast(master_to_hps[0].w_last), + .m_axi_wvalid(master_to_hps[0].w_valid), + .m_axi_wready(master_to_hps[0].w_ready), + .m_axi_bresp(master_to_hps[0].b_resp), + .m_axi_bvalid(master_to_hps[0].b_valid), + .m_axi_bready(master_to_hps[0].b_ready), + .m_axi_araddr(master_to_hps[0].ar_addr), + .m_axi_arlen(master_to_hps[0].ar_len), + .m_axi_arsize(master_to_hps[0].ar_size), + .m_axi_arburst(master_to_hps[0].ar_burst), + .m_axi_arlock(master_to_hps[0].ar_lock), + .m_axi_arcache(master_to_hps[0].ar_cache), + .m_axi_arprot(master_to_hps[0].ar_prot), + .m_axi_arregion(master_to_hps[0].ar_region), + .m_axi_arqos(master_to_hps[0].ar_qos), + .m_axi_arvalid(master_to_hps[0].ar_valid), + .m_axi_arready(master_to_hps[0].ar_ready), + .m_axi_rdata(master_to_hps[0].r_data), + .m_axi_rresp(master_to_hps[0].r_resp), + .m_axi_rlast(master_to_hps[0].r_last), + .m_axi_rvalid(master_to_hps[0].r_valid), + .m_axi_rready(master_to_hps[0].r_ready) + ); + +system hps_minimal ( + .hps_h2f_sdmmc_interrupt_irq(sd_irq), // output, width = 1 + .hps_hps_io_EMAC0_TX_CLK (hps_emac0_TX_CLK), // output, width = 1, hps_hps_io.EMAC0_TX_CLK + .hps_hps_io_EMAC0_TXD0 (hps_emac0_TXD0), // output, width = 1, .EMAC0_TXD0 + .hps_hps_io_EMAC0_TXD1 (hps_emac0_TXD1), // output, width = 1, .EMAC0_TXD1 + .hps_hps_io_EMAC0_TXD2 (hps_emac0_TXD2), // output, width = 1, .EMAC0_TXD2 + .hps_hps_io_EMAC0_TXD3 (hps_emac0_TXD3), // output, width = 1, .EMAC0_TXD3 + .hps_hps_io_EMAC0_RX_CTL (hps_emac0_RX_CTL), // input, width = 1, .EMAC0_RX_CTL + .hps_hps_io_EMAC0_TX_CTL (hps_emac0_TX_CTL), // output, width = 1, .EMAC0_TX_CTL + .hps_hps_io_EMAC0_RX_CLK (hps_emac0_RX_CLK), // input, width = 1, .EMAC0_RX_CLK + .hps_hps_io_EMAC0_RXD0 (hps_emac0_RXD0), // input, width = 1, .EMAC0_RXD0 + .hps_hps_io_EMAC0_RXD1 (hps_emac0_RXD1), // input, width = 1, .EMAC0_RXD1 + .hps_hps_io_EMAC0_RXD2 (hps_emac0_RXD2), // input, width = 1, .EMAC0_RXD2 + .hps_hps_io_EMAC0_RXD3 (hps_emac0_RXD3), // input, width = 1, .EMAC0_RXD3 + .hps_hps_io_EMAC0_MDIO (hps_emac0_MDIO), // inout, width = 1, .EMAC0_MDIO + .hps_hps_io_EMAC0_MDC (hps_emac0_MDC), // output, width = 1, .EMAC0_MDC + .hps_hps_io_SDMMC_CMD (hps_sdmmc_CMD), // inout, width = 1, .SDMMC_CMD + .hps_hps_io_SDMMC_D0 (hps_sdmmc_D0), // inout, width = 1, .SDMMC_D0 + .hps_hps_io_SDMMC_D1 (hps_sdmmc_D1), // inout, width = 1, .SDMMC_D1 + .hps_hps_io_SDMMC_D2 (hps_sdmmc_D2), // inout, width = 1, .SDMMC_D2 + .hps_hps_io_SDMMC_D3 (hps_sdmmc_D3), // inout, width = 1, .SDMMC_D3 + .hps_hps_io_SDMMC_CCLK (hps_sdmmc_CCLK), // output, width = 1, .SDMMC_CCLK + .hps_hps_io_UART0_RX (hps_uart0_RX), // input, width = 1, .UART0_RX + .hps_hps_io_UART0_TX (hps_uart0_TX), // output, width = 1, .UART0_TX + .hps_hps_io_I2C1_SDA (hps_i2c1_SDA), // inout, width = 1, .I2C1_SDA + .hps_hps_io_I2C1_SCL (hps_i2c1_SCL), // inout, width = 1, .I2C1_SCL + .hps_hps_io_gpio1_io0 (hps_gpio1_io0), // inout, width = 1, .gpio1_io0 + .hps_hps_io_jtag_tck (hps_jtag_tck), // input, width = 1, .jtag_tck + .hps_hps_io_jtag_tms (hps_jtag_tms), // input, width = 1, .jtag_tms + .hps_hps_io_jtag_tdo (hps_jtag_tdo), // output, width = 1, .jtag_tdo + .hps_hps_io_jtag_tdi (hps_jtag_tdi), // input, width = 1, .jtag_tdi + .hps_hps_io_hps_osc_clk (hps_ref_clk), // input, width = 1, .hps_osc_clk + .h2f_reset_reset (h2f_reset), // output, width = 1, h2f_reset.reset + + .hps_f2h_axi_clock_clk (clk), // input, width = 1, hps_f2h_axi_clock.clk + .hps_f2h_axi_reset_reset_n(ndmreset_n), // input, width = 1, hps_f2h_axi_reset.reset_n + .hps_emif_pll_ref_clk_clk (emif_hps_pll_ref_clk_p), // input, width = 1, hps_emif_pll_ref_clk.clk + .hps_emif_oct_oct_rzqin (emif_hps_oct_oct_rzqin), // input, width = 1, hps_emif_oct.oct_rzqin + .hps_emif_mem_mem_ck (emif_hps_mem_mem_ck), // output, width = 1, hps_emif_mem.mem_ck + .hps_emif_mem_mem_ck_n (emif_hps_mem_mem_ck_n), // output, width = 1, .mem_ck_n + .hps_emif_mem_mem_a (emif_hps_mem_mem_a), // output, width = 17, .mem_a + .hps_emif_mem_mem_act_n (emif_hps_mem_mem_act_n), // output, width = 1, .mem_act_n + .hps_emif_mem_mem_ba (emif_hps_mem_mem_ba), // output, width = 2, .mem_ba + .hps_emif_mem_mem_bg (emif_hps_mem_mem_bg), // output, width = 2, .mem_bg + .hps_emif_mem_mem_cke (emif_hps_mem_mem_cke), // output, width = 1, .mem_cke + .hps_emif_mem_mem_cs_n (emif_hps_mem_mem_cs_n), // output, width = 1, .mem_cs_n + .hps_emif_mem_mem_odt (emif_hps_mem_mem_odt), // output, width = 1, .mem_odt + .hps_emif_mem_mem_reset_n (emif_hps_mem_mem_reset_n), // output, width = 1, .mem_reset_n + .hps_emif_mem_mem_par (emif_hps_mem_mem_par), // output, width = 1, .mem_par + .hps_emif_mem_mem_alert_n (emif_hps_mem_mem_alert_n), // input, width = 1, .mem_alert_n + .hps_emif_mem_mem_dqs (emif_hps_mem_mem_dqs), // inout, width = 8, .mem_dqs + .hps_emif_mem_mem_dqs_n (emif_hps_mem_mem_dqs_n), // inout, width = 8, .mem_dqs_n + .hps_emif_mem_mem_dq (emif_hps_mem_mem_dq), // inout, width = 64, .mem_dq + .hps_emif_mem_mem_dbi_n (emif_hps_mem_mem_dbi_n), // inout, width = 8, .mem_dbi_n + + .hps_emif_emif_calbus_calbus_read (calbus_read1), // input, width = 1, hps_emif_emif_calbus.calbus_read + .hps_emif_emif_calbus_calbus_write (calbus_write1), // input, width = 1, .calbus_write + .hps_emif_emif_calbus_calbus_address (calbus_address1), // input, width = 20, .calbus_address + .hps_emif_emif_calbus_calbus_wdata (calbus_wdata1), // input, width = 32, .calbus_wdata + .hps_emif_emif_calbus_calbus_rdata (calbus_rdata1), // output, width = 32, .calbus_rdata + .hps_emif_emif_calbus_calbus_seq_param_tbl (calbus_seq_param_tbl1), // output, width = 4096, .calbus_seq_param_tbl + .hps_emif_emif_calbus_clk_clk (calbus_clk), // input, width = 1, hps_emif_emif_calbus_clk.clk + + .ninit_done_ninit_done (ninit_done), // output, width = 1, ninit_done.ninit_done + + .system_intel_cache_coherency_translator_clock_clk (clk), // input, width = 1, system_intel_cache_coherency_translator_clock.clk + .system_intel_cache_coherency_translator_reset_reset (~ndmreset_n), // input, width = 1, system_intel_cache_coherency_translator_reset.reset + .system_intel_cache_coherency_translator_s0_araddr (master_to_hps[0].ar_addr), // input, width = 32, system_intel_cache_coherency_translator_s0.araddr + .system_intel_cache_coherency_translator_s0_arburst (master_to_hps[0].ar_burst), // input, width = 2, .arburst + .system_intel_cache_coherency_translator_s0_arcache (master_to_hps[0].ar_cache), // input, width = 4, .arcache + .system_intel_cache_coherency_translator_s0_arid (master_to_hps[0].ar_id), // input, width = 5, .arid + .system_intel_cache_coherency_translator_s0_arlen (master_to_hps[0].ar_len), // input, width = 8, .arlen + .system_intel_cache_coherency_translator_s0_arlock (master_to_hps[0].ar_lock), // input, width = 1, .arlock + .system_intel_cache_coherency_translator_s0_arprot (master_to_hps[0].ar_prot), // input, width = 3, .arprot + .system_intel_cache_coherency_translator_s0_arready (master_to_hps[0].ar_ready), // output, width = 1, .arready + .system_intel_cache_coherency_translator_s0_arsize (master_to_hps[0].ar_size), // input, width = 3, .arsize + .system_intel_cache_coherency_translator_s0_arvalid (master_to_hps[0].ar_valid), // input, width = 1, .arvalid + .system_intel_cache_coherency_translator_s0_awaddr (master_to_hps[0].aw_addr), // input, width = 32, .awaddr + .system_intel_cache_coherency_translator_s0_awburst (master_to_hps[0].aw_burst), // input, width = 2, .awburst + .system_intel_cache_coherency_translator_s0_awcache (master_to_hps[0].aw_cache), // input, width = 4, .awcache + .system_intel_cache_coherency_translator_s0_awid (master_to_hps[0].aw_id), // input, width = 5, .awid + .system_intel_cache_coherency_translator_s0_awlen (master_to_hps[0].aw_len), // input, width = 8, .awlen + .system_intel_cache_coherency_translator_s0_awlock (master_to_hps[0].aw_lock), // input, width = 1, .awlock + .system_intel_cache_coherency_translator_s0_awprot (master_to_hps[0].aw_prot), // input, width = 3, .awprot + .system_intel_cache_coherency_translator_s0_awready (master_to_hps[0].aw_ready), // output, width = 1, .awready + .system_intel_cache_coherency_translator_s0_awsize (master_to_hps[0].aw_size), // input, width = 3, .awsize + .system_intel_cache_coherency_translator_s0_awvalid (master_to_hps[0].aw_valid), // input, width = 1, .awvalid + .system_intel_cache_coherency_translator_s0_bid (master_to_hps[0].b_id), // output, width = 5, .bid + .system_intel_cache_coherency_translator_s0_bready (master_to_hps[0].b_ready), // input, width = 1, .bready + .system_intel_cache_coherency_translator_s0_bresp (master_to_hps[0].b_resp), // output, width = 2, .bresp + .system_intel_cache_coherency_translator_s0_bvalid (master_to_hps[0].b_valid), // output, width = 1, .bvalid + .system_intel_cache_coherency_translator_s0_rdata (master_to_hps[0].r_data), // output, width = 128, .rdata + .system_intel_cache_coherency_translator_s0_rid (master_to_hps[0].r_id), // output, width = 5, .rid + .system_intel_cache_coherency_translator_s0_rlast (master_to_hps[0].r_last), // output, width = 1, .rlast + .system_intel_cache_coherency_translator_s0_rready (master_to_hps[0].r_ready), // input, width = 1, .rready + .system_intel_cache_coherency_translator_s0_rresp (master_to_hps[0].r_resp), // output, width = 2, .rresp + .system_intel_cache_coherency_translator_s0_rvalid (master_to_hps[0].r_valid), // output, width = 1, .rvalid + .system_intel_cache_coherency_translator_s0_wdata (master_to_hps[0].w_data), // input, width = 128, .wdata + .system_intel_cache_coherency_translator_s0_wlast (master_to_hps[0].w_last), // input, width = 1, .wlast + .system_intel_cache_coherency_translator_s0_wready (master_to_hps[0].w_ready), // output, width = 1, .wready + .system_intel_cache_coherency_translator_s0_wstrb (master_to_hps[0].w_strb), // input, width = 16, .wstrb + .system_intel_cache_coherency_translator_s0_wvalid (master_to_hps[0].w_valid) // input, width = 1, .wvalid + ); // //clocks diff --git a/corev_apu/altera/src/cva6_altera_peripherals.sv b/corev_apu/altera/src/cva6_altera_peripherals.sv index dbab741d68f..1a6e09d0150 100644 --- a/corev_apu/altera/src/cva6_altera_peripherals.sv +++ b/corev_apu/altera/src/cva6_altera_peripherals.sv @@ -57,7 +57,7 @@ module cva6_peripherals #( input logic spi_miso , output logic spi_ss , // SD Card - input logic sd_clk_i , + input logic sd_irq , output logic [7:0] leds_o , input logic [7:0] dip_switches_i ); @@ -68,7 +68,8 @@ module cva6_peripherals #( logic [ariane_soc::NumSources-1:0] irq_sources; // Unused interrupt sources - assign irq_sources[ariane_soc::NumSources-1:7] = '0; + assign irq_sources[ariane_soc::NumSources-1:8] = '0; + assign irq_sources[7] = sd_irq; REG_BUS #( .ADDR_WIDTH ( 32 ), @@ -192,123 +193,85 @@ module cva6_peripherals #( // --------------- // 2. UART // --------------- - logic uart_penable; - logic uart_pwrite; - logic [31:0] uart_paddr; - logic uart_psel; - logic [31:0] uart_pwdata; - logic [31:0] uart_prdata; - logic uart_pready; - logic uart_pslverr; - axi2apb_64_32 #( - .AXI4_ADDRESS_WIDTH ( AxiAddrWidth ), - .AXI4_RDATA_WIDTH ( AxiDataWidth ), - .AXI4_WDATA_WIDTH ( AxiDataWidth ), - .AXI4_ID_WIDTH ( AxiIdWidth ), - .AXI4_USER_WIDTH ( AxiUserWidth ), - .BUFF_DEPTH_SLAVE ( 2 ), - .APB_ADDR_WIDTH ( 32 ) - ) i_axi2apb_64_32_uart ( - .ACLK ( clk_i ), - .ARESETn ( rst_ni ), - .test_en_i ( 1'b0 ), - .AWID_i ( uart.aw_id ), - .AWADDR_i ( uart.aw_addr ), - .AWLEN_i ( uart.aw_len ), - .AWSIZE_i ( uart.aw_size ), - .AWBURST_i ( uart.aw_burst ), - .AWLOCK_i ( uart.aw_lock ), - .AWCACHE_i ( uart.aw_cache ), - .AWPROT_i ( uart.aw_prot ), - .AWREGION_i( uart.aw_region ), - .AWUSER_i ( uart.aw_user ), - .AWQOS_i ( uart.aw_qos ), - .AWVALID_i ( uart.aw_valid ), - .AWREADY_o ( uart.aw_ready ), - .WDATA_i ( uart.w_data ), - .WSTRB_i ( uart.w_strb ), - .WLAST_i ( uart.w_last ), - .WUSER_i ( uart.w_user ), - .WVALID_i ( uart.w_valid ), - .WREADY_o ( uart.w_ready ), - .BID_o ( uart.b_id ), - .BRESP_o ( uart.b_resp ), - .BVALID_o ( uart.b_valid ), - .BUSER_o ( uart.b_user ), - .BREADY_i ( uart.b_ready ), - .ARID_i ( uart.ar_id ), - .ARADDR_i ( uart.ar_addr ), - .ARLEN_i ( uart.ar_len ), - .ARSIZE_i ( uart.ar_size ), - .ARBURST_i ( uart.ar_burst ), - .ARLOCK_i ( uart.ar_lock ), - .ARCACHE_i ( uart.ar_cache ), - .ARPROT_i ( uart.ar_prot ), - .ARREGION_i( uart.ar_region ), - .ARUSER_i ( uart.ar_user ), - .ARQOS_i ( uart.ar_qos ), - .ARVALID_i ( uart.ar_valid ), - .ARREADY_o ( uart.ar_ready ), - .RID_o ( uart.r_id ), - .RDATA_o ( uart.r_data ), - .RRESP_o ( uart.r_resp ), - .RLAST_o ( uart.r_last ), - .RUSER_o ( uart.r_user ), - .RVALID_o ( uart.r_valid ), - .RREADY_i ( uart.r_ready ), - .PENABLE ( uart_penable ), - .PWRITE ( uart_pwrite ), - .PADDR ( uart_paddr ), - .PSEL ( uart_psel ), - .PWDATA ( uart_pwdata ), - .PRDATA ( uart_prdata ), - .PREADY ( uart_pready ), - .PSLVERR ( uart_pslverr ) - ); + // UART Through JTAG// + +logic uart_amm_ready; +logic uart_amm_read; +logic uart_amm_write; +logic uart_amm_read_n; +logic uart_amm_write_n; +logic uart_amm_chipselect; +logic uart_amm_irq; +logic [0:0] uart_amm_address; +logic [31:0] uart_amm_rdata; +logic [31:0] uart_amm_wdata; + + +assign uart_amm_read_n = ~uart_amm_read; +assign uart_amm_write_n = ~uart_amm_write; + +cva6_intel_jtag_uart_0 uart_i ( + .clk (clk_i), // input, width = 1, clk.clk + .rst_n (rst_ni), + .av_chipselect (uart_amm_chipselect), // input, width = 1, avalon_jtag_slave.chipselect + .av_address (uart_amm_address), // input, width = 1, .address + .av_read_n (uart_amm_read_n), // input, width = 1, .read_n + .av_readdata (uart_amm_rdata), // output, width = 32, .readdata + .av_write_n (uart_amm_write_n), // input, width = 1, .write_n + .av_writedata (uart_amm_wdata), // input, width = 32, .writedata + .av_waitrequest (uart_amm_ready), // output, width = 1, .waitrequest + .av_irq (irq_sources[0]) // output, width = 1, irq.irq +); - if (InclUART) begin : gen_uart - apb_uart i_apb_uart ( - .CLK ( clk_i ), - .RSTN ( rst_ni ), - .PSEL ( uart_psel ), - .PENABLE ( uart_penable ), - .PWRITE ( uart_pwrite ), - .PADDR ( uart_paddr[4:2] ), - .PWDATA ( uart_pwdata ), - .PRDATA ( uart_prdata ), - .PREADY ( uart_pready ), - .PSLVERR ( uart_pslverr ), - .INT ( irq_sources[0] ), - .OUT1N ( ), // keep open - .OUT2N ( ), // keep open - .RTSN ( ), // no flow control - .DTRN ( ), // no flow control - .CTSN ( 1'b0 ), - .DSRN ( 1'b0 ), - .DCDN ( 1'b0 ), - .RIN ( 1'b0 ), - .SIN ( rx_i ), - .SOUT ( tx_o ) - ); - end else begin - /* pragma translate_off */ - `ifndef VERILATOR - mock_uart i_mock_uart ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .penable_i ( uart_penable ), - .pwrite_i ( uart_pwrite ), - .paddr_i ( uart_paddr ), - .psel_i ( uart_psel ), - .pwdata_i ( uart_pwdata ), - .prdata_o ( uart_prdata ), - .pready_o ( uart_pready ), - .pslverr_o ( uart_pslverr ) - ); - `endif - /* pragma translate_on */ - end +//axi4 to avalon converter +interconnect_altera_mm_interconnect_1920_v5r556a axi_to_avalon_uart ( + .axi_bridge_1_m0_awid (uart.aw_id), // input, width = 8, axi_bridge_1_m0.awid + .axi_bridge_1_m0_awaddr (uart.aw_addr), // input, width = 64, .awaddr + .axi_bridge_1_m0_awlen (uart.aw_len), // input, width = 8, .awlen + .axi_bridge_1_m0_awsize (uart.aw_size), // input, width = 3, .awsize + .axi_bridge_1_m0_awburst (uart.aw_burst), // input, width = 2, .awburst + .axi_bridge_1_m0_awlock (uart.aw_lock), // input, width = 1, .awlock + .axi_bridge_1_m0_awcache (uart.aw_cache), // input, width = 4, .awcache + .axi_bridge_1_m0_awprot (uart.aw_prot), // input, width = 3, .awprot + .axi_bridge_1_m0_awvalid (uart.aw_valid), // input, width = 1, .awvalid + .axi_bridge_1_m0_awready (uart.aw_ready), // output, width = 1, .awready + .axi_bridge_1_m0_wdata (uart.w_data), // input, width = 64, .wdata + .axi_bridge_1_m0_wstrb (uart.w_strb), // input, width = 8, .wstrb + .axi_bridge_1_m0_wlast (uart.w_last), // input, width = 1, .wlast + .axi_bridge_1_m0_wvalid (uart.w_valid), // input, width = 1, .wvalid + .axi_bridge_1_m0_wready (uart.w_ready), // output, width = 1, .wready + .axi_bridge_1_m0_bid (uart.b_id), // output, width = 8, .bid + .axi_bridge_1_m0_bresp (uart.b_resp), // output, width = 2, .bresp + .axi_bridge_1_m0_bvalid (uart.b_valid), // output, width = 1, .bvalid + .axi_bridge_1_m0_bready (uart.b_ready), // input, width = 1, .bready + .axi_bridge_1_m0_arid (uart.ar_id), // input, width = 8, .arid + .axi_bridge_1_m0_araddr (uart.ar_addr), // input, width = 64, .araddr + .axi_bridge_1_m0_arlen (uart.ar_len), // input, width = 8, .arlen + .axi_bridge_1_m0_arsize (uart.ar_size), // input, width = 3, .arsize + .axi_bridge_1_m0_arburst (uart.ar_burst), // input, width = 2, .arburst + .axi_bridge_1_m0_arlock (uart.ar_lock), // input, width = 1, .arlock + .axi_bridge_1_m0_arcache (uart.ar_cache), // input, width = 4, .arcache + .axi_bridge_1_m0_arprot (uart.ar_prot), // input, width = 3, .arprot + .axi_bridge_1_m0_arvalid (uart.ar_valid), // input, width = 1, .arvalid + .axi_bridge_1_m0_arready (uart.ar_ready), // output, width = 1, .arready + .axi_bridge_1_m0_rid (uart.r_id), // output, width = 8, .rid + .axi_bridge_1_m0_rdata (uart.r_data), // output, width = 64, .rdata + .axi_bridge_1_m0_rresp (uart.r_resp), // output, width = 2, .rresp + .axi_bridge_1_m0_rlast (uart.r_last), // output, width = 1, .rlast + .axi_bridge_1_m0_rvalid (uart.r_valid), // output, width = 1, .rvalid + .axi_bridge_1_m0_rready (uart.r_ready), // input, width = 1, .rready + .jtag_uart_0_avalon_jtag_slave_address (uart_amm_address), // output, width = 1, jtag_uart_0_avalon_jtag_slave.address + .jtag_uart_0_avalon_jtag_slave_write (uart_amm_write), // output, width = 1, .write + .jtag_uart_0_avalon_jtag_slave_read (uart_amm_read), // output, width = 1, .read + .jtag_uart_0_avalon_jtag_slave_readdata (uart_amm_rdata), // input, width = 32, .readdata + .jtag_uart_0_avalon_jtag_slave_writedata (uart_amm_wdata), // output, width = 32, .writedata + .jtag_uart_0_avalon_jtag_slave_waitrequest (uart_amm_ready), // input, width = 1, .waitrequest + .jtag_uart_0_avalon_jtag_slave_chipselect (uart_amm_chipselect), // output, width = 1, .chipselect + .axi_bridge_1_clk_reset_reset_bridge_in_reset_reset (~rst_ni), // input, width = 1, axi_bridge_1_clk_reset_reset_bridge_in_reset.reset + .axi_bridge_1_m0_translator_clk_reset_reset_bridge_in_reset_reset (~rst_ni), // input, width = 1, axi_bridge_1_m0_translator_clk_reset_reset_bridge_in_reset.reset + .emif_fm_0_emif_usr_clk_clk (clk_i) // input, width = 1, emif_fm_0_emif_usr_clk.clk + ); // --------------- // 3. SPI diff --git a/corev_apu/altera/src/dmi_vjtag.sv b/corev_apu/altera/src/dmi_vjtag.sv index 7204ec76b42..e2a57b76c82 100644 --- a/corev_apu/altera/src/dmi_vjtag.sv +++ b/corev_apu/altera/src/dmi_vjtag.sv @@ -42,9 +42,9 @@ module dmi_vjtag #( output logic tdo_oe_o, // Data out output enable input logic[IrLength-1:0] ir_in_i, // Virtual IR in input logic jtag_state_tlr_i, // Test logic reset - input logic virtual_state_cdr_i, // Virtual Captude DR + input logic virtual_state_cdr_i, // Virtual Capture DR input logic virtual_state_sdr_i, // Virtual Shift DR - input logic virtual_state_udr_i // Virutal Update DR + input logic virtual_state_udr_i // Virtual Update DR ); assign dmi_rst_no = rst_ni; @@ -85,7 +85,7 @@ module dmi_vjtag #( assign dmi_req.addr = address_q; assign dmi_req.data = data_q; assign dmi_req.op = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ; - // we'will always be ready to accept the data we requested + // we will always be ready to accept the data we requested assign dmi_resp_ready = 1'b1; logic error_dmi_busy; diff --git a/corev_apu/altera/src/dmi_vjtag_tap.sv b/corev_apu/altera/src/dmi_vjtag_tap.sv index 44e4008481a..8f36b61a119 100644 --- a/corev_apu/altera/src/dmi_vjtag_tap.sv +++ b/corev_apu/altera/src/dmi_vjtag_tap.sv @@ -35,9 +35,9 @@ module dmi_vjtag_tap #( input logic testmode_i, input logic[IrLength-1:0] ir_in_i, // Virtual IR in input logic jtag_state_tlr_i, // Test logic reset - input logic virtual_state_cdr_i, // Virtual Captude DR + input logic virtual_state_cdr_i, // Virtual Capture DR input logic virtual_state_sdr_i, // Virtual Shift DR - input logic virtual_state_udr_i, // Virutal Update DR + input logic virtual_state_udr_i, // Virtual Update DR // we want to access DMI register output logic dmi_access_o, diff --git a/corev_apu/altera/u-boot-spl-dtb.hex b/corev_apu/altera/u-boot-spl-dtb.hex new file mode 100644 index 00000000000..408f9a011f8 --- /dev/null +++ b/corev_apu/altera/u-boot-spl-dtb.hex @@ -0,0 +1,9599 @@ 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+:10575000732D776964746800696E74656C2C6F666C +:10576000667365742D73657474696E677300736511 +:105770007269616C300073706930007374646F75A6 +:10578000742D7061746800752D626F6F742C737066 +:0D5790006C2D626F6F742D6F726465720076 +:04000005FFE0000018 +:00000001FF diff --git a/corev_apu/bootrom/ariane.dts b/corev_apu/bootrom/ariane.dts index 9b5b84f145a..3f79380f34d 100644 --- a/corev_apu/bootrom/ariane.dts +++ b/corev_apu/bootrom/ariane.dts @@ -41,7 +41,7 @@ reg = <0x0 0x2000000 0x0 0xc0000>; reg-names = "control"; }; - // PLIC needs to be disabeld for tandem verification + // PLIC needs to be disabled for tandem verification // PLIC0: interrupt-controller@c000000 { // #address-cells = <0>; // #interrupt-cells = <1>; @@ -54,7 +54,7 @@ // }; // Specifying the interrupt controller in the devicetree is not necessary. // Furthermore, the IRQ 65535 will cause a `hwirq 0xffff is too large` during - // Linux boot (occured with mainline linux 5.14.0). + // Linux boot (occurred with mainline linux 5.14.0). // debug-controller@0 { // compatible = "riscv,debug-013"; // interrupts-extended = <&CPU0_intc 65535>; diff --git a/corev_apu/clint/README.md b/corev_apu/clint/README.md index a62fc203b63..9401a5f57d0 100644 --- a/corev_apu/clint/README.md +++ b/corev_apu/clint/README.md @@ -2,7 +2,7 @@ This repository contains a RISC-V privilege spec 1.11 (WIP) compatible CLINT for the Ariane Core. -The CLINT plugs into an existing AXI Bus with an AXI 4 Lite interface. The IP mirrors transaction IDs and is fully pin-compatible with the full AXI 4 interface. It does not support burst transfers (as specified in the AMBA 4 Bus specifcation) +The CLINT plugs into an existing AXI Bus with an AXI 4 Lite interface. The IP mirrors transaction IDs and is fully pin-compatible with the full AXI 4 interface. It does not support burst transfers (as specified in the AXI 4 Bus specification) | Address | Description | Note | |-------------------|-------------|------------------------------------------------| diff --git a/corev_apu/clint/clint.sv b/corev_apu/clint/clint.sv index 2d4dc0536c5..e01ca523864 100644 --- a/corev_apu/clint/clint.sv +++ b/corev_apu/clint/clint.sv @@ -102,7 +102,7 @@ module clint #( end [MTIMECMP_BASE:MTIMECMP_BASE+8*NR_CORES]: begin - if (CVA6Cfg.XLEN == 32) begin + if (CVA6Cfg.IS_XLEN32) begin if (be[3:0] == 4'hf) mtimecmp_n[$unsigned(address[AddrSelWidth-1+3:3])][31:0] = wdata[31:0]; else @@ -114,7 +114,7 @@ module clint #( end [MTIME_BASE:MTIME_BASE+4]: begin - if (CVA6Cfg.XLEN == 32) begin + if (CVA6Cfg.IS_XLEN32) begin if (address[2:0] == 3'h0) mtime_n[31:0] = wdata[31:0]; else begin @@ -137,14 +137,14 @@ module clint #( if (en && !we) begin case (register_address) inside [MSIP_BASE:MSIP_BASE+4*NR_CORES]: begin - if (CVA6Cfg.XLEN == 32) + if (CVA6Cfg.IS_XLEN32) rdata[31:0] = msip_q[$unsigned(address[AddrSelWidth-1+2:2])]; else rdata = msip_q[$unsigned(address[AddrSelWidth-1+2:2])]; end [MTIMECMP_BASE:MTIMECMP_BASE+8*NR_CORES]: begin - if (CVA6Cfg.XLEN == 32) begin + if (CVA6Cfg.IS_XLEN32) begin if (address[2:0] == 3'h0) rdata[31:0] = mtimecmp_q[$unsigned(address[AddrSelWidth-1+3:3])][31:0]; else begin @@ -158,7 +158,7 @@ module clint #( end [MTIME_BASE:MTIME_BASE+4]: begin - if (CVA6Cfg.XLEN == 32) begin + if (CVA6Cfg.IS_XLEN32) begin if (address[2:0] == 3'h0) rdata[31:0] = mtime_q[31:0]; else begin diff --git a/corev_apu/fpga/Makefile b/corev_apu/fpga/Makefile index 678e2244382..370b981a9d6 100644 --- a/corev_apu/fpga/Makefile +++ b/corev_apu/fpga/Makefile @@ -12,6 +12,7 @@ ips := xlnx_axi_clock_converter.xci \ xlnx_axi_quad_spi.xci \ xlnx_axi_gpio.xci \ xlnx_clk_gen.xci \ + xlnx_dpti_clk.xci \ xlnx_mig_7_ddr3.xci ips := $(addprefix $(work-dir)/, $(ips)) diff --git a/corev_apu/fpga/ariane-multi-hart.cfg b/corev_apu/fpga/ariane-multi-hart.cfg index 3f21b8646c7..5f579d4b3d0 100644 --- a/corev_apu/fpga/ariane-multi-hart.cfg +++ b/corev_apu/fpga/ariane-multi-hart.cfg @@ -1,10 +1,10 @@ -adapter_khz 1000 +adapter speed 1000 -interface ftdi -ftdi_vid_pid 0x0403 0x6010 +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 # Channel 1 is taken by Xilinx JTAG -ftdi_channel 0 +ftdi channel 0 # links: # http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html @@ -16,9 +16,9 @@ ftdi_channel 0 # Bit3 TMS ADBUS3 TMS Out Select Signal Out # Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O # this corresponds to the following in/out layout, with TMS initially set to 1 -ftdi_layout_init 0x0018 0x001b +ftdi layout_init 0x0018 0x001b # we only have to specify nTRST, the others are assigned correctly by default -ftdi_layout_signal nTRST -ndata 0x0010 +ftdi layout_signal nTRST -ndata 0x0010 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 @@ -26,8 +26,8 @@ jtag newtap $_CHIPNAME cpu -irlen 5 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv -gdb_report_data_abort enable -gdb_report_register_access_error enable +gdb report_data_abort enable +gdb report_register_access_error enable riscv set_reset_timeout_sec 120 riscv set_command_timeout_sec 120 diff --git a/corev_apu/fpga/ariane.cfg b/corev_apu/fpga/ariane.cfg index 82d3f5abe4e..a9f87f3fe37 100644 --- a/corev_apu/fpga/ariane.cfg +++ b/corev_apu/fpga/ariane.cfg @@ -1,10 +1,10 @@ -adapter_khz 1000 +adapter speed 1000 -interface ftdi -ftdi_vid_pid 0x0403 0x6010 +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 # Channel 1 is taken by Xilinx JTAG -ftdi_channel 0 +ftdi channel 0 # links: # http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html @@ -16,9 +16,9 @@ ftdi_channel 0 # Bit3 TMS ADBUS3 TMS Out Select Signal Out # Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O # this corresponds to the following in/out layout, with TMS initially set to 1 -ftdi_layout_init 0x0018 0x001b +ftdi layout_init 0x0018 0x001b # we only have to specify nTRST, the others are assigned correctly by default -ftdi_layout_signal nTRST -ndata 0x0010 +ftdi layout_signal nTRST -ndata 0x0010 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 @@ -26,8 +26,8 @@ jtag newtap $_CHIPNAME cpu -irlen 5 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 -gdb_report_data_abort enable -gdb_report_register_access_error enable +gdb report_data_abort enable +gdb report_register_access_error enable riscv set_reset_timeout_sec 120 riscv set_command_timeout_sec 120 diff --git a/corev_apu/fpga/ariane_pmod.cfg b/corev_apu/fpga/ariane_pmod.cfg index 21da859932c..9ed8cdfb647 100644 --- a/corev_apu/fpga/ariane_pmod.cfg +++ b/corev_apu/fpga/ariane_pmod.cfg @@ -1,13 +1,13 @@ -adapter_khz 1000 +adapter speed 1000 -interface ftdi +adapter driver ftdi # ftdi_device_desc "Olimex Ltd. ARM-USB-OCD-H JTAG+RS232" -ftdi_vid_pid 0x15ba 0x002b +ftdi vid_pid 0x15ba 0x002b -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 +ftdi layout_init 0x0808 0x0a1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal LED -data 0x0800 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 @@ -16,8 +16,8 @@ set _TARGETNAME $_CHIPNAME.cpu # select the HART to debug with the coreid switch target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 -gdb_report_data_abort enable -gdb_report_register_access_error enable +gdb report_data_abort enable +gdb report_register_access_error enable riscv set_reset_timeout_sec 120 riscv set_command_timeout_sec 120 diff --git a/corev_apu/fpga/ariane_pmod_tiny.cfg b/corev_apu/fpga/ariane_pmod_tiny.cfg index bc8a500c833..989f4e45977 100644 --- a/corev_apu/fpga/ariane_pmod_tiny.cfg +++ b/corev_apu/fpga/ariane_pmod_tiny.cfg @@ -1,13 +1,13 @@ -adapter_khz 1000 +adapter speed 1000 -interface ftdi -ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" -ftdi_vid_pid 0x15ba 0x002a +adapter driver ftdi +ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi vid_pid 0x15ba 0x002a -ftdi_layout_init 0x0808 0x0a1b -ftdi_layout_signal nSRST -oe 0x0200 -ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 -ftdi_layout_signal LED -data 0x0800 +ftdi layout_init 0x0808 0x0a1b +ftdi layout_signal nSRST -oe 0x0200 +ftdi layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi layout_signal LED -data 0x0800 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 @@ -16,8 +16,8 @@ set _TARGETNAME $_CHIPNAME.cpu # select the HART to debug with the coreid switch target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 -gdb_report_data_abort enable -gdb_report_register_access_error enable +gdb report_data_abort enable +gdb report_register_access_error enable riscv set_reset_timeout_sec 120 riscv set_command_timeout_sec 120 diff --git a/corev_apu/fpga/constraints/ariane.xdc b/corev_apu/fpga/constraints/ariane.xdc index 714bc451cb5..c2b6a138961 100644 --- a/corev_apu/fpga/constraints/ariane.xdc +++ b/corev_apu/fpga/constraints/ariane.xdc @@ -7,7 +7,7 @@ set_input_jitter tck 1.000 set_input_delay -clock tck -clock_fall 5 [get_ports tdi ] set_input_delay -clock tck -clock_fall 5 [get_ports tms ] set_output_delay -clock tck 5 [get_ports tdo ] -set_false_path -from [get_ports trst_n ] +set_false_path -from [get_ports trst_n ] set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000 @@ -15,5 +15,30 @@ set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_s set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000 # set multicycle path on reset, on the FPGA we do not care about the reset anyway -set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 4 -set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 3 -hold +set_multicycle_path -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 4 +set_multicycle_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 3 + +create_clock -period 16.667 -name prog_clko_pin -waveform {0.000 8.333} [get_ports prog_clko] + +set_input_delay -clock [get_clocks prog_clko_pin] -min -add_delay 1.000 [get_ports {prog_d[*]}] +set_input_delay -clock [get_clocks prog_clko_pin] -max -add_delay 7.150 [get_ports {prog_d[*]}] +set_input_delay -clock [get_clocks prog_clko_pin] -min -add_delay 1.000 [get_ports prog_rxen] +set_input_delay -clock [get_clocks prog_clko_pin] -max -add_delay 7.150 [get_ports prog_rxen] +set_input_delay -clock [get_clocks prog_clko_pin] -min -add_delay 1.000 [get_ports prog_txen] +set_input_delay -clock [get_clocks prog_clko_pin] -max -add_delay 7.150 [get_ports prog_txen] +set_output_delay -clock [get_clocks prog_clko_pin] -min -add_delay 0.400 [get_ports {prog_d[*]}] +set_output_delay -clock [get_clocks prog_clko_pin] -max -add_delay 8.600 [get_ports {prog_d[*]}] +set_output_delay -clock [get_clocks prog_clko_pin] -min -add_delay 0.400 [get_ports prog_oen] +set_output_delay -clock [get_clocks prog_clko_pin] -max -add_delay 8.600 [get_ports prog_oen] +set_output_delay -clock [get_clocks prog_clko_pin] -min -add_delay 0.400 [get_ports prog_rdn] +set_output_delay -clock [get_clocks prog_clko_pin] -max -add_delay 8.600 [get_ports prog_rdn] +set_output_delay -clock [get_clocks prog_clko_pin] -min -add_delay 0.400 [get_ports prog_wrn] +set_output_delay -clock [get_clocks prog_clko_pin] -max -add_delay 8.600 [get_ports prog_wrn] + +set_property IOB TRUE [get_ports {prog_d[*]}] +set_property IOB TRUE [get_ports prog_rxen] +set_property IOB TRUE [get_ports prog_txen] + +set_property DONT_TOUCH true [get_cells i_cva6_rvfi] +set_property DONT_TOUCH true [get_cells i_iti] +set_property DONT_TOUCH true [get_cells i_encapsulator] \ No newline at end of file diff --git a/corev_apu/fpga/constraints/genesys-2.xdc b/corev_apu/fpga/constraints/genesys-2.xdc index 52fd7144526..2a99992571f 100644 --- a/corev_apu/fpga/constraints/genesys-2.xdc +++ b/corev_apu/fpga/constraints/genesys-2.xdc @@ -8,6 +8,47 @@ set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { tdi set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { tdo }]; set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { tms }]; +#PMOD Header JA +set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS33} [get_ports prog_clko]; #IO_L13P_T2_MRCC_14 +set_property -dict {PACKAGE_PIN U28 IOSTANDARD LVCMOS33} [get_ports prog_oen] +set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVCMOS33} [get_ports prog_rdn] +set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports prog_rxen] +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports prog_siwun] +set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports prog_spien] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports prog_txen] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports prog_wrn] + +#PMOD Header JB +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS33} [get_ports {prog_d[0]}] +set_property -dict {PACKAGE_PIN V30 IOSTANDARD LVCMOS33} [get_ports {prog_d[1]}] +set_property -dict {PACKAGE_PIN V25 IOSTANDARD LVCMOS33} [get_ports {prog_d[2]}] +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports {prog_d[3]}] +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports {prog_d[4]}] +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports {prog_d[5]}] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports {prog_d[6]}] +set_property -dict {PACKAGE_PIN U23 IOSTANDARD LVCMOS33} [get_ports {prog_d[7]}] + + +#PMOD Header JC +# set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33} [get_ports prog_clko] +# set_property -dict {PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33} [get_ports prog_oen] +# set_property -dict {PACKAGE_PIN AH30 IOSTANDARD LVCMOS33} [get_ports prog_rdn] +# set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS33} [get_ports prog_rxen] +# set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS33} [get_ports prog_siwun] +# set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports prog_spien] +# set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS33} [get_ports prog_txen] +# set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS33} [get_ports prog_wrn] + +#PMOD Header JD +# set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS33} [get_ports {prog_d[0]}] +# set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS33} [get_ports {prog_d[1]}] +# set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports {prog_d[2]}] +# set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {prog_d[3]}] +# set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports {prog_d[4]}] +# set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS33} [get_ports {prog_d[5]}] +# set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports {prog_d[6]}] +# set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {prog_d[7]}] + ## UART set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports tx] set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports rx] diff --git a/corev_apu/fpga/scripts/run.tcl b/corev_apu/fpga/scripts/run.tcl index 9ba9d4e1878..3777b2803bf 100644 --- a/corev_apu/fpga/scripts/run.tcl +++ b/corev_apu/fpga/scripts/run.tcl @@ -37,6 +37,7 @@ read_ip { \ "xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci" \ "xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xci" \ "xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xci" \ + "xilinx/xlnx_dpti_clk/xlnx_dpti_clk.srcs/sources_1/ip/xlnx_dpti_clk/xlnx_dpti_clk.xci" \ } # read_ip xilinx/xlnx_protocol_checker/ip/xlnx_protocol_checker.xci @@ -45,7 +46,9 @@ set_property include_dirs { \ "../../vendor/pulp-platform/common_cells/include" \ "../../vendor/pulp-platform/axi/include" \ "../../core/cache_subsystem/hpdcache/rtl/include" \ + "../../core/cache_subsystem/hpdcache/rtl/src/utils/ecc" \ "../register_interface/include" \ + "../instr_tracing/ITI/include" \ "../../core/include" \ } [current_fileset] diff --git a/corev_apu/fpga/src/agilex7.svh b/corev_apu/fpga/src/agilex7.svh index 467ddaf3fee..391bc087397 100644 --- a/corev_apu/fpga/src/agilex7.svh +++ b/corev_apu/fpga/src/agilex7.svh @@ -8,7 +8,7 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -// Description: Set global FPGA degines +// Description: Set global FPGA defines // Author: Florian Zaruba `define AGILEX7 @@ -17,5 +17,5 @@ `define ARIANE_DATA_WIDTH 64 -// Instantiate protocl checker +// Instantiate protocol checker // `define PROTOCOL_CHECKER diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index 20e77f77c2c..d1ec621e319 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -10,6 +10,9 @@ // Description: Xilinx FPGA top-level // Author: Florian Zaruba +`include "axi/assign.svh" +`include "rvfi_types.svh" +`include "iti_types.svh" module ariane_xilinx ( // WARNING: Do not define input parameters. This causes the FPGA build to fail. @@ -177,11 +180,20 @@ module ariane_xilinx ( output logic spi_ss , output logic spi_clk_o , // common part - // input logic trst_n , + // input logic trst_n , input logic tck , input logic tms , input logic tdi , - output wire tdo , + output wire tdo , + input logic prog_clko , + input logic prog_rxen , + input logic prog_txen , + input logic prog_spien , + output logic prog_rdn , + output logic prog_wrn , + output logic prog_oen , + output logic prog_siwun , + inout logic [7:0] prog_d , input logic rx , output logic tx ); @@ -199,11 +211,17 @@ endfunction // CVA6 Xilinx configuration localparam config_pkg::cva6_cfg_t CVA6Cfg = build_fpga_config(cva6_config_pkg::cva6_cfg); +localparam type rvfi_instr_t = `RVFI_INSTR_T(CVA6Cfg); +//localparam type rvfi_csr_elmt_t = `RVFI_CSR_ELMT_T(CVA6Cfg); +//localparam type rvfi_csr_t = `RVFI_CSR_T(CVA6Cfg, rvfi_csr_elmt_t); +localparam type rvfi_to_iti_t = `RVFI_TO_ITI_T(CVA6Cfg); +localparam type iti_to_encoder_t = `ITI_TO_ENCODER_T(CVA6Cfg); + localparam type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg); localparam type rvfi_probes_csr_t = `RVFI_PROBES_CSR_T(CVA6Cfg); localparam type rvfi_probes_t = struct packed { logic csr; - logic instr; + rvfi_probes_instr_t instr; }; // 24 MByte in 8 byte words @@ -462,7 +480,7 @@ axi2mem #( .data_i ( dm_slave_rdata ) ); -if (CVA6Cfg.XLEN==32 ) begin +if (CVA6Cfg.IS_XLEN32) begin assign master_to_dm[0].aw_user = '0; assign master_to_dm[0].w_user = '0; @@ -616,7 +634,7 @@ end logic [1:0] axi_adapter_size; -assign axi_adapter_size = (CVA6Cfg.XLEN == 64) ? 2'b11 : 2'b10; +assign axi_adapter_size = CVA6Cfg.IS_XLEN64 ? 2'b11 : 2'b10; axi_adapter #( .CVA6Cfg ( CVA6Cfg ), @@ -645,7 +663,7 @@ axi_adapter #( .axi_resp_i ( dm_axi_m_resp ) ); -if (CVA6Cfg.XLEN==32 ) begin +if (CVA6Cfg.IS_XLEN32) begin logic [31 : 0] dm_master_m_awaddr; logic [31 : 0] dm_master_m_araddr; @@ -753,6 +771,11 @@ end // --------------- ariane_axi::req_t axi_ariane_req; ariane_axi::resp_t axi_ariane_resp; +rvfi_probes_t rvfi_probes; + +rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr; +rvfi_to_iti_t rvfi_to_iti; +iti_to_encoder_t iti_to_encoder; ariane #( .CVA6Cfg ( CVA6Cfg ), @@ -767,7 +790,7 @@ ariane #( .irq_i ( irq ), .ipi_i ( ipi ), .time_irq_i ( timer_irq ), - .rvfi_probes_o( /* open */ ), + .rvfi_probes_o( rvfi_probes ), .debug_req_i ( debug_req_irq ), .noc_req_o ( axi_ariane_req ), .noc_resp_i ( axi_ariane_resp ) @@ -776,6 +799,136 @@ ariane #( `AXI_ASSIGN_FROM_REQ(slave[0], axi_ariane_req) `AXI_ASSIGN_TO_RESP(axi_ariane_resp, slave[0]) + cva6_rvfi #( + .CVA6Cfg (CVA6Cfg), + .rvfi_instr_t(rvfi_instr_t), + .rvfi_csr_t(), + .rvfi_probes_instr_t(rvfi_probes_instr_t), + .rvfi_probes_csr_t(rvfi_probes_csr_t), + .rvfi_probes_t(rvfi_probes_t), + .rvfi_to_iti_t(rvfi_to_iti_t) + ) i_cva6_rvfi ( + .clk_i (clk), + .rst_ni (ndmreset_n), + .rvfi_probes_i(rvfi_probes), + .rvfi_instr_o (rvfi_instr), + .rvfi_to_iti_o (rvfi_to_iti), + .rvfi_csr_o () + ); + + + cva6_iti #( + .CVA6Cfg (CVA6Cfg), + .CAUSE_LEN (iti_pkg::CAUSE_LEN), + .ITYPE_LEN (iti_pkg::ITYPE_LEN), + .IRETIRE_LEN (iti_pkg::IRETIRE_LEN), + .block_mode(0), + .rvfi_to_iti_t(rvfi_to_iti_t), + .iti_to_encoder_t(iti_to_encoder_t) + ) i_iti ( + .clk_i (clk), + .rst_ni (ndmreset_n), + // inputs from rvfi + .valid_i(rvfi_to_iti.valid), + .rvfi_to_iti_i(rvfi_to_iti), + // outputs for the encoder module TODO + .valid_o(), + .iti_to_encoder_o(iti_to_encoder) + ); + + logic packet_valid; + te_pkg::it_packet_type_e [0:0] packet_type; + logic [te_pkg::P_LEN-1:0] packet_length; + logic [te_pkg::PAYLOAD_LEN-1:0] packet_payload; + + rv_tracer #( + .N(1), + .ONLY_BRANCHES(1) + )i_encoder( + .clk_i (clk), + .rst_ni (ndmreset_n), + .valid_i (iti_to_encoder.valid), + .itype_i (iti_to_encoder.itype), + .cause_i (iti_to_encoder.cause), + .tval_i (iti_to_encoder.tval), + .priv_i (iti_to_encoder.priv), + .iaddr_i (iti_to_encoder.iaddr), + .iretire_i (iti_to_encoder.iretire), + .ilastsize_i (iti_to_encoder.ilastsize), + .time_i (iti_to_encoder.cycles), + .tvec_i ('0), + .epc_i ('0), + .encapsulator_ready_i('1), + .paddr_i ('0), + .pwrite_i ('0), + .psel_i ('0), + .penable_i ('0), + .pwdata_i ('0), + .packet_valid_o (packet_valid), + .packet_type_o (packet_type), + .packet_length_o (packet_length), + .packet_payload_o (packet_payload), + .stall_o (), + .pready_o (), + .prdata_o () + ); + + logic encap_valid; + encap_pkg::encap_fifo_entry_s encap_fifo_entry_i; + encap_pkg::encap_fifo_entry_s encap_fifo_entry_o; + logic encap_fifo_full; + logic encap_fifo_empty; + logic encap_fifo_pop; + + encapsulator i_encapsulator ( + .clk_i (clk), + .valid_i (packet_valid), + .packet_length_i (packet_length), + .flow_i ('0), + .timestamp_present_i('1), + //.srcid_i(), + .timestamp_i (rvfi_to_iti.cycles), + //.type_i(), + .trace_payload_i (packet_payload), + .valid_o (encap_valid), + .encap_fifo_entry_o (encap_fifo_entry_i) + ); + + fifo_v3 # ( + .DEPTH(16), + .dtype(encap_pkg::encap_fifo_entry_s) + ) i_fifo_encap ( + .clk_i (clk), + .rst_ni (ndmreset_n), + .flush_i ('0), + .testmode_i('0), + .full_o (encap_fifo_full), + .empty_o (encap_fifo_empty), + .usage_o (), + .data_i (encap_fifo_entry_i), + .push_i (encap_valid), + .data_o (encap_fifo_entry_o), + .pop_i (encap_fifo_pop) + ); + + localparam DATA_LEN = 8; + logic valid_slice; + logic [DATA_LEN-1:0] slice; + logic [$clog2(DATA_LEN)-4:0] valid_bytes; + + slicer_DPTI #( + .SLICE_LEN(DATA_LEN), + .NO_TIME ('0) + ) i_slicer ( + .clk_i (clk), + .rst_ni (ndmreset_n), + .valid_i (!encap_fifo_empty), + .encap_fifo_entry_i(encap_fifo_entry_o), + .fifo_full_i (usrFull), // usrFull DPTI + .valid_o (valid_slice), + .slice_o (slice), + .done_o (encap_fifo_pop) + ); // --------------- // CLINT // --------------- @@ -833,7 +986,7 @@ axi2mem #( .data_i ( rom_rdata ) ); -if (CVA6Cfg.XLEN==32 ) begin +if (CVA6Cfg.IS_XLEN32) begin bootrom_32 i_bootrom ( .clk_i ( clk ), .req_i ( rom_req ), @@ -848,7 +1001,67 @@ end else begin .rdata_o ( rom_rdata ) ); end +// --------------- +// DPTI +// --------------- +logic FifoEn ; +logic usrFull ; +logic usrEmpty ; +logic [7:0] w_data; +logic [7:0] r_data; + +logic [11:0] w_count; +logic [11:0] r_count; + +logic prog_rxen_debug; +logic prog_txen_debug; +logic prog_spien_debug; +logic prog_rdn_debug; +logic prog_wrn_debug; +logic prog_oen_debug; +logic prog_siwun_debug; + +assign prog_rxen_debug = prog_rxen; +assign prog_txen_debug = prog_txen; +assign prog_spien_debug = prog_spien; +assign prog_rdn_debug = prog_rdn; +assign prog_wrn_debug = prog_wrn; +assign prog_oen_debug = prog_oen; +assign prog_siwun_debug = prog_siwun; + +//assign w_data = {iti_to_encoder.itype[0],iti_to_encoder.itype[1],iti_to_encoder.valid} ; + +assign FifoEn = !usrFull && !usrEmpty; + dpti_ctrl i_dpti_ctrl ( + .wr_clk (clk), + .wr_en (valid_slice), + .wr_full(usrFull), + .wr_afull(), + .wr_err(), + .wr_count(w_count), + .wr_di(slice), + + .rd_clk(clk), + .rd_en(FifoEn), + .rd_empty(usrEmpty), + .rd_aempty(), + .rd_err (), + .rd_count(r_count), + .rd_do(r_data), + + .rst(rst), + + .prog_clko(prog_clko), + .prog_rxen(prog_rxen), + .prog_txen(prog_txen), + .prog_spien('0), + .prog_rdn(prog_rdn), + .prog_wrn(prog_wrn), + .prog_oen(prog_oen), + .prog_siwun(prog_siwun), + .prog_d(prog_d) +); // --------------- // Peripherals // --------------- diff --git a/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_rd.v b/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_rd.v index 55afcfc5842..dac48d9c209 100644 --- a/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_rd.v +++ b/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_rd.v @@ -135,12 +135,12 @@ parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT; // bus width assertions initial begin if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin - $error("Error: AXI slave interface data width not evenly divisble (instance %m)"); + $error("Error: AXI slave interface data width not evenly divisible (instance %m)"); $finish; end if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin - $error("Error: AXI master interface data width not evenly divisble (instance %m)"); + $error("Error: AXI master interface data width not evenly divisible (instance %m)"); $finish; end diff --git a/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_wr.v b/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_wr.v index 881495c706a..98bc95aa8a3 100644 --- a/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_wr.v +++ b/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_wr.v @@ -147,12 +147,12 @@ parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT; // bus width assertions initial begin if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin - $error("Error: AXI slave interface data width not evenly divisble (instance %m)"); + $error("Error: AXI slave interface data width not evenly divisible (instance %m)"); $finish; end if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin - $error("Error: AXI master interface data width not evenly divisble (instance %m)"); + $error("Error: AXI master interface data width not evenly divisible (instance %m)"); $finish; end diff --git a/corev_apu/fpga/src/bootrom/Makefile b/corev_apu/fpga/src/bootrom/Makefile index 81679948f26..e1fa839ae24 100644 --- a/corev_apu/fpga/src/bootrom/Makefile +++ b/corev_apu/fpga/src/bootrom/Makefile @@ -8,6 +8,13 @@ CLOCK_FREQUENCY ?= 25000000 #25MHz HALF_CLOCK_FREQUENCY ?= 12500000 #12.5MHz UART_BITRATE ?= 57600 HAS_ETHERNET ?= 0 +else ifeq ($(PLATFORM), PLAT_AGILEX) +DRAM_SIZE_64 ?= 0x40000000 #1GB +DRAM_SIZE_32 ?= 0x08000000 #128MB +CLOCK_FREQUENCY ?= 100000000 #100MHz +HALF_CLOCK_FREQUENCY ?= 50000000 #50MHz +UART_BITRATE ?= 115200 +HAS_ETHERNET ?= 1 else DRAM_SIZE_64 ?= 0x40000000 #1GB DRAM_SIZE_32 ?= 0x08000000 #128MB @@ -17,10 +24,12 @@ UART_BITRATE ?= 115200 HAS_ETHERNET ?= 1 endif -CC = $(RISCV)/bin/${CROSSCOMPILE}gcc -OBJCOPY = $(RISCV)/bin/$(CROSSCOMPILE)objcopy +ifeq ($(CC),cc) + CC = $(RISCV)/bin/${CROSSCOMPILE}gcc + OBJCOPY = $(RISCV)/bin/$(CROSSCOMPILE)objcopy +endif SED = sed -PLATFORM_DEFINES = -DCLOCK_FREQUENCY=$(CLOCK_FREQUENCY) -DUART_BITRATE=$(UART_BITRATE) -D$(PLATFORM) +PLATFORM_DEFINES = -DCLOCK_FREQUENCY=$(CLOCK_FREQUENCY) -DUART_BITRATE=$(UART_BITRATE) -D$(PLATFORM) -DXLEN=$(XLEN) ifeq ($(XLEN), 64) CFLAGS = $(PLATFORM_DEFINES) -Os -ggdb -march=rv64im_zicsr -mabi=lp64 -Wall -mcmodel=medany -mexplicit-relocs -ffreestanding @@ -33,7 +42,7 @@ LDFLAGS = -nostdlib -nodefaultlibs -nostartfiles INCLUDES = -I./ -I./src -SRCS_C = src/main.c src/uart.c src/spi.c src/sd.c src/gpt.c +SRCS_C = src/main.c src/uart.c src/spi.c src/sd.c src/gpt.c src/dw_mmc.c src/bouncebuf.c SRCS_ASM = startup.S OBJS_C = $(SRCS_C:.c=.o) OBJS_S = $(SRCS_ASM:.S=.o) @@ -43,7 +52,11 @@ MAIN_BIN = $(MAIN:.elf=.bin) MAIN_IMG = $(MAIN:.elf=.img) MAIN_SV = $(MAIN:.elf=.sv) +ifeq ($(PLATFORM), PLAT_AGILEX) +DTB = cv$(XLEN)a6_agilex.dtb +else DTB = cv$(XLEN)a6.dtb +endif ifeq ($(HAS_ETHERNET), 1) SED_DELETE_OPT = -e "/DELETE_ETH/d" @@ -65,12 +78,12 @@ $(MAIN): $(DTB) $(OBJS_C) $(OBJS_S) linker.lds $(OBJCOPY) -O binary $< $@ %.o: %.c - @$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@ @echo "CC <= $<" + @$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@ %.o: %.S - @$(CC) $(CFLAGS) $(CCASFLAGS) $(INCLUDES) -c $< -o $@ @echo "CC <= $<" + @$(CC) $(CFLAGS) $(CCASFLAGS) $(INCLUDES) -c $< -o $@ %.dts: %.dts.in $(SED) -e "s/DRAM_SIZE_64/$(DRAM_SIZE_64)/g" \ @@ -82,11 +95,11 @@ $(MAIN): $(DTB) $(OBJS_C) $(OBJS_S) linker.lds cat $@ %.dtb: %.dts - dtc -I dts $< -O dtb -o $@ + dtc -I dts $< -O dtb -o cv$(XLEN)a6.dtb %.sv: %.img - ./gen_rom.py $< @echo "PYTHON >= $(MAIN_SV)" + ./gen_rom.py $< clean: $(RM) $(OBJS_C) $(OBJS_S) $(MAIN) $(MAIN_BIN) $(MAIN_IMG) *.dtb *.dts *.sv diff --git a/corev_apu/fpga/src/bootrom/cv32a6.dts.in b/corev_apu/fpga/src/bootrom/cv32a6.dts.in index 314a7b069e5..c607836128f 100644 --- a/corev_apu/fpga/src/bootrom/cv32a6.dts.in +++ b/corev_apu/fpga/src/bootrom/cv32a6.dts.in @@ -64,7 +64,7 @@ }; // Specifying the interrupt controller in the devicetree is not necessary. // Furthermore, the IRQ 65535 will cause a `hwirq 0xffff is too large` during - // Linux boot (occured with mainline linux 5.14.0). + // Linux boot (occurred with mainline linux 5.14.0). // debug-controller@0 { // compatible = "riscv,debug-013"; // interrupts-extended = <&CPU0_intc 65535>; diff --git a/corev_apu/fpga/src/bootrom/cv32a6_agilex.dts.in b/corev_apu/fpga/src/bootrom/cv32a6_agilex.dts.in new file mode 100644 index 00000000000..d905323ff62 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/cv32a6_agilex.dts.in @@ -0,0 +1,101 @@ +// Copyright (c) 2025 PlanV Technologies +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "eth,ariane-bare-dev"; + model = "eth,ariane-bare"; + chosen { + stdout-path = "/soc/uart@10000000:UART_BITRATE"; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = ; + CPU0: cpu@0 { + clock-frequency = ; + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "eth, ariane", "riscv"; + riscv,isa = "rv32ima"; + mmu-type = "riscv,sv32"; + tlb-split; + // HLIC - hart local interrupt controller + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 DRAM_SIZE_32>; + }; + L26: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "eth,ariane-bare-soc", "simple-bus"; + ranges; + clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>; + reg = <0x2000000 0xc0000>; + reg-names = "control"; + }; + PLIC0: interrupt-controller@c000000 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + reg = <0xc000000 0x4000000>; + riscv,max-priority = <7>; + riscv,ndev = <30>; + }; + // Specifying the interrupt controller in the devicetree is not necessary. + // Furthermore, the IRQ 65535 will cause a `hwirq 0xffff is too large` during + // Linux boot (occured with mainline linux 5.14.0). + // debug-controller@0 { + // compatible = "riscv,debug-013"; + // interrupts-extended = <&CPU0_intc 65535>; + // reg = <0x0 0x1000>; + // reg-names = "control"; + // }; + uart@10000000 { + compatible = "ns16550a"; + reg = < 0x10000000 0x1000>; + clock-frequency = ; + current-speed = ; + interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg-shift = <0>; // regs are spaced on 32 bit boundary + reg-io-width = <1>; // only 32-bit access are supported + }; + timer@18000000 { + compatible = "pulp,apb_timer"; + interrupts = <0x00000004 0x00000005 0x00000006 0x00000007>; + reg = <0x18000000 0x00001000>; + interrupt-parent = <&PLIC0>; + reg-names = "control"; + }; + sysmgr: sysmgr@ffd12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0xffd12000 0x500>; + }; + mmc: mmc@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + fifo-depth = <0x400>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; + status = "disabled"; + }; + }; +}; +// delete ethernet device if disabled +/delete-node/ ð // DELETE_ETH diff --git a/corev_apu/fpga/src/bootrom/cv64a6.dts.in b/corev_apu/fpga/src/bootrom/cv64a6.dts.in index eb8134d78d3..6f0095ae27d 100644 --- a/corev_apu/fpga/src/bootrom/cv64a6.dts.in +++ b/corev_apu/fpga/src/bootrom/cv64a6.dts.in @@ -64,7 +64,7 @@ }; // Specifying the interrupt controller in the devicetree is not necessary. // Furthermore, the IRQ 65535 will cause a `hwirq 0xffff is too large` during - // Linux boot (occured with mainline linux 5.14.0). + // Linux boot (occurred with mainline linux 5.14.0). // debug-controller@0 { // compatible = "riscv,debug-013"; // interrupts-extended = <&CPU0_intc 65535>; diff --git a/corev_apu/fpga/src/bootrom/cv64a6_agilex.dts.in b/corev_apu/fpga/src/bootrom/cv64a6_agilex.dts.in new file mode 100644 index 00000000000..4968db46e55 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/cv64a6_agilex.dts.in @@ -0,0 +1,103 @@ +// Copyright (c) 2025 PlanV Technologies +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "eth,ariane-bare-dev"; + model = "eth,ariane-bare"; + chosen { + stdout-path = "/soc/uart@10000000:UART_BITRATE"; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = ; + CPU0: cpu@0 { + clock-frequency = ; + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "eth, ariane", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 DRAM_SIZE_64>; + }; + L26: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "eth,ariane-bare-soc", "simple-bus"; + ranges; + clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>; + reg = <0x0 0x2000000 0x0 0xc0000>; + reg-names = "control"; + }; + PLIC0: interrupt-controller@c000000 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,max-priority = <7>; + riscv,ndev = <30>; + }; + // Specifying the interrupt controller in the devicetree is not necessary. + // Furthermore, the IRQ 65535 will cause a `hwirq 0xffff is too large` during + // Linux boot (occured with mainline linux 5.14.0). + // debug-controller@0 { + // compatible = "riscv,debug-013"; + // interrupts-extended = <&CPU0_intc 65535>; + // reg = <0x0 0x0 0x0 0x1000>; + // reg-names = "control"; + // }; + uart@10000000 { + compatible = "ns16550a"; + reg = <0x0 0x10000000 0x0 0x1000>; + clock-frequency = ; + current-speed = ; + interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg-shift = <0>; // regs are spaced on 32 bit boundary + reg-io-width = <1>; // only 32-bit access are supported + }; + timer@18000000 { + compatible = "pulp,apb_timer"; + interrupts = <0x00000004 0x00000005 0x00000006 0x00000007>; + reg = <0x00000000 0x18000000 0x00000000 0x00001000>; + interrupt-parent = <&PLIC0>; + reg-names = "control"; + }; + sysmgr: sysmgr@ffd12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0xffd12000 0x500>; + }; + mmc: mmc@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + fifo-depth = <0x400>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; + status = "disabled"; + }; + + + }; +}; +// delete ethernet device if disabled +/delete-node/ ð // DELETE_ETH diff --git a/corev_apu/fpga/src/bootrom/src/bootrom_errno.h b/corev_apu/fpga/src/bootrom/src/bootrom_errno.h new file mode 100644 index 00000000000..4c04274a693 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/bootrom_errno.h @@ -0,0 +1,25 @@ +// Copyright (c) 2025 Thales Research and Technology +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +/** + * \file bootrom_errno.h + * \brief Contains error numbers useful for our bootrom. + * \author Julien Mallet +*/ + +#ifndef BOOTROM_ERRNO_H +#define BOOTROM_ERRNO_H + + +#define EIO 5 /* I/O error */ +#define EBUSY 16 /* Device or resource busy */ +#define EINVAL 22 /* Invalid argument */ +#define ECOMM 70 /* Communication error on send */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define ETIMEDOUT 110 /* Connection timed out */ + +#define ENOTSUPP 255 /* Operation is not supported */ + +#ifndef ENOMEM +#define ENOMEM 12 +#endif +#endif \ No newline at end of file diff --git a/corev_apu/fpga/src/bootrom/src/bootrom_io.h b/corev_apu/fpga/src/bootrom/src/bootrom_io.h new file mode 100644 index 00000000000..5c4a0798201 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/bootrom_io.h @@ -0,0 +1,50 @@ +// Copyright (c) 2025 Thales Research and Technology +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +/** + * \file bootrom_io.h + * \brief Contains the functions for reading and writing registers. + * \author Julien Mallet +*/ + +#ifndef BOOTROM_IO_H +#define BOOTROM_IO_H + +// Generic I/O + +#include "bootrom_types.h" +#include + + +static inline u8_t readb(volatile u32_t addr) +{ + return *(volatile u8_t *)(addr); +} + +static inline u16_t readw(volatile u32_t addr) +{ + return *(volatile u16_t *)(addr); +} + +static inline u32_t readl(volatile u32_t addr) +{ + return *(volatile u32_t *)(addr); +} + + +static inline void writeb(u8_t val, volatile u32_t addr) +{ + *(volatile u8_t *)(addr) = val; +} + +static inline void writew(u16_t val, volatile u32_t addr) +{ + *(volatile u16_t *)(addr) = val; +} + +static inline void writel(u32_t val, volatile u32_t addr) +{ + *(volatile u32_t *)(addr) = val; +} + + +#endif \ No newline at end of file diff --git a/corev_apu/fpga/src/bootrom/src/bootrom_time.h b/corev_apu/fpga/src/bootrom/src/bootrom_time.h new file mode 100644 index 00000000000..94f1b2d43d4 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/bootrom_time.h @@ -0,0 +1,24 @@ +// Copyright (c) 2025 Thales Research and Technology +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +/** + * \file bootrom_time.h + * \brief Contains a custom udelay function. It is a software wait with a loop that does not uses any hardware timer or any pre-existing timer. As such, the duration is not accurate at all. udelay(5) will not be a 5 microsecond wait. This solution is however good enough for our bootrom as it keeps the code small and still does a decent wait. + * \author Julien Mallet +*/ + +#ifndef BOOTROM_TIME_H +#define BOOTROM_TIME_H + +#include "bootrom_types.h" + +// #define UDELAY(nr_us) for(volatile unsigned int count=0 ; count<50*nr_us ; count++){} + +void udelay(u32_t nr_us) +{ + volatile u32_t count = 0; + for(count = 0 ; count < 1*nr_us; ++count) + {} +} + + +#endif \ No newline at end of file diff --git a/corev_apu/fpga/src/bootrom/src/bootrom_types.h b/corev_apu/fpga/src/bootrom/src/bootrom_types.h new file mode 100644 index 00000000000..cf62caaedcb --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/bootrom_types.h @@ -0,0 +1,29 @@ +// Copyright (c) 2025 Thales Research and Technology +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +/** + * \file bootrom_types.h + * \brief Contains custom types which show their size. + * \author Julien Mallet + * +*/ + +#ifndef BOOTROM_TYPES_H +#define BOOTROM_TYPES_H + + +typedef __signed__ char s8_t; +typedef unsigned char u8_t; + +typedef __signed__ short s16_t; +typedef unsigned short u16_t; + +typedef __signed__ int s32_t; +typedef unsigned int u32_t; + +typedef __signed__ long long s64_t; +typedef unsigned long long u64_t; + +typedef unsigned long int uptr_t; + + +#endif \ No newline at end of file diff --git a/corev_apu/fpga/src/bootrom/src/bouncebuf.c b/corev_apu/fpga/src/bootrom/src/bouncebuf.c new file mode 100644 index 00000000000..1eda2edc089 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/bouncebuf.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Generic bounce buffer implementation + * + * Copyright (C) 2012 Marek Vasut + */ + +// #include +// #include +// #include +// #include +// #include +#include "bouncebuf.h" +#include "cache.h" +#include "dma-mapping.h" +#include "uart.h" +#include "bootrom_errno.h" +#include + +// void flush_dcache_range(unsigned long start, unsigned long end) +// { +// if (start >= end) +// return; + +// /* +// * ARCv1 -> call __dc_line_op +// * ARCv2 && L1 D$ disabled -> nothing +// * ARCv2 && L1 D$ enabled && IOC enabled -> nothing +// * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op +// */ +// // if (!_config_enabled(CONFIG_ISA_ARCV2,0)|| !ioc_enabled()) +// __dc_line_op(start, end - start, OP_FLUSH); + +// // if (_config_enabled(CONFIG_ISA_ARCV2,0) && !ioc_enabled() && !slc_data_bypass()) +// // __slc_rgn_op(start, end - start, OP_FLUSH); +// } + +static int addr_aligned(struct bounce_buffer *state) +{ + const unsigned long align_mask = ARCH_DMA_MINALIGN - 1; + + /* Check if start is aligned */ + if ((unsigned long)state->user_buffer & align_mask) { + print_uart("Unaligned buffer address "); + print_uart_int(state->user_buffer); + print_uart("align mask"); + print_uart_int(align_mask); + print_uart("(unsigned long)state->user_buffer & align_mask"); + print_uart_int((unsigned long)state->user_buffer & align_mask); + print_uart("\n"); + return 0; + } + + /* Check if length is aligned */ + if (state->len != state->len_aligned) { + print_uart("Unaligned buffer length"); + print_uart_int(state->len); + print_uart("\n"); + return 0; + } + + /* Aligned */ + return 1; +} + +int bounce_buffer_start_extalign(struct bounce_buffer *state, void *data, + u32_t len, unsigned int flags, + u32_t alignment, + int (*addr_is_aligned)(struct bounce_buffer *state)) +{ + state->user_buffer = data; + state->bounce_buffer = data; + state->len = len; + state->len_aligned = roundup(len, alignment); + state->flags = flags; + + // if (!addr_is_aligned(state)) { + // print_uart("call mem align \n"); + // state->bounce_buffer = memalign(alignment, + // state->len_aligned); + // if (!state->bounce_buffer){ + // print_uart("return enomem \n"); + // return -ENOMEM; + // } + + // if (state->flags & GEN_BB_READ){ + // print_uart("memcpy \n"); + // memcpy(state->bounce_buffer, state->user_buffer, + // state->len); + // } + // } + + /* + * Flush data to RAM so DMA reads can pick it up, + * and any CPU writebacks don't race with DMA writes + */ + print_uart("dma map single\n"); + dma_map_single(state->bounce_buffer, + state->len_aligned, + DMA_BIDIRECTIONAL); + print_uart("return 0\n"); + return 0; +} + +int bounce_buffer_start(struct bounce_buffer *state, void *data, + u32_t len, unsigned int flags) +{ + return bounce_buffer_start_extalign(state, data, len, flags, + ARCH_DMA_MINALIGN, + addr_aligned); +} + +int bounce_buffer_stop(struct bounce_buffer *state) +{ + if (state->flags & GEN_BB_WRITE) { + /* Invalidate cache so that CPU can see any newly DMA'd data */ + dma_unmap_single((dma_addr_t)(uintptr_t)state->bounce_buffer, + state->len_aligned, + DMA_BIDIRECTIONAL); + } + + if (state->bounce_buffer == state->user_buffer) + return 0; + + // if (state->flags & GEN_BB_WRITE) + // memcpy(state->user_buffer, state->bounce_buffer, state->len); + + // free(state->bounce_buffer); + + return 0; +} diff --git a/corev_apu/fpga/src/bootrom/src/bouncebuf.h b/corev_apu/fpga/src/bootrom/src/bouncebuf.h new file mode 100644 index 00000000000..6ff99e68091 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/bouncebuf.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Generic bounce buffer implementation + * + * Copyright (C) 2012 Marek Vasut + */ + +#ifndef __INCLUDE_BOUNCEBUF_H__ +#define __INCLUDE_BOUNCEBUF_H__ + +#include "bootrom_types.h" + +/* + * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware. + * The source buffer is copied into the bounce buffer (if unaligned, otherwise + * the source buffer is used directly) upon start() call, then the operation + * requiring the aligned transfer happens, then the bounce buffer is lost upon + * stop() call. + */ +#define GEN_BB_READ (1 << 0) +/* + * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware. + * The source buffer starts in an undefined state upon start() call, then the + * operation requiring the aligned transfer happens, then the bounce buffer is + * copied into the destination buffer (if unaligned, otherwise destination + * buffer is used directly) upon stop() call. + */ +#define GEN_BB_WRITE (1 << 1) +/* + * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware. + * The source buffer is copied into the bounce buffer (if unaligned, otherwise + * the source buffer is used directly) upon start() call, then the operation + * requiring the aligned transfer happens, then the bounce buffer is copied + * into the destination buffer (if unaligned, otherwise destination buffer is + * used directly) upon stop() call. + */ +#define GEN_BB_RW (GEN_BB_READ | GEN_BB_WRITE) +// #define u32_t u32_t + +struct bounce_buffer { + /* Copy of data parameter passed to start() */ + void *user_buffer; + /* + * DMA-aligned buffer. This field is always set to the value that + * should be used for DMA; either equal to .user_buffer, or to a + * freshly allocated aligned buffer. + */ + void *bounce_buffer; + /* Copy of len parameter passed to start() */ + u32_t len; + /* DMA-aligned buffer length */ + u32_t len_aligned; + /* Copy of flags parameter passed to start() */ + unsigned int flags; +}; + +/** + * bounce_buffer_start() -- Start the bounce buffer session + * state: stores state passed between bounce_buffer_{start,stop} + * data: pointer to buffer to be aligned + * len: length of the buffer + * flags: flags describing the transaction, see above. + */ +int bounce_buffer_start(struct bounce_buffer *state, void *data, + u32_t len, unsigned int flags); + +/** + * bounce_buffer_start() -- Start the bounce buffer session with external align check function + * state: stores state passed between bounce_buffer_{start,stop} + * data: pointer to buffer to be aligned + * len: length of the buffer + * flags: flags describing the transaction, see above. + * alignment: alignment of the newly allocated bounce buffer + * addr_is_aligned: function for checking the alignment instead of the default one + */ +int bounce_buffer_start_extalign(struct bounce_buffer *state, void *data, + u32_t len, unsigned int flags, + u32_t alignment, + int (*addr_is_aligned)(struct bounce_buffer *state)); + +/** + * bounce_buffer_stop() -- Finish the bounce buffer session + * state: stores state passed between bounce_buffer_{start,stop} + */ +int bounce_buffer_stop(struct bounce_buffer *state); + +#endif diff --git a/corev_apu/fpga/src/bootrom/src/cache.h b/corev_apu/fpga/src/bootrom/src/cache.h new file mode 100644 index 00000000000..c174fdef347 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/cache.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#ifndef _ASM_RISCV_CACHE_H +#define _ASM_RISCV_CACHE_H + +/* cache */ +void cache_flush(void); + +/* + * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 64 +#endif + +#endif /* _ASM_RISCV_CACHE_H */ diff --git a/corev_apu/fpga/src/bootrom/src/dma-mapping.h b/corev_apu/fpga/src/bootrom/src/dma-mapping.h new file mode 100644 index 00000000000..6c6d9ba17e4 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/dma-mapping.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_DMA_MAPPING_H +#define _LINUX_DMA_MAPPING_H + +// #include +// #include +#include "bootrom_types.h" +#include "memalign.h" +#include "cache.h" +// #include +// #include +#ifndef _LINUX_DMA_DIRECTION_H +#define _LINUX_DMA_DIRECTION_H +/* + * These definitions mirror those in pci.h, so they can be used + * interchangeably with their PCI_ counterparts. + */ +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, + DMA_NONE = 3, +}; +#endif + +#define dma_mapping_error(x, y) 0 + +/** + * Map a buffer to make it available to the DMA device + * + * Linux-like DMA API that is intended to be used from drivers. This hides the + * underlying cache operation from drivers. Call this before starting the DMA + * transfer. In most of architectures in U-Boot, the virtual address matches to + * the physical address (but we have exceptions like sandbox). U-Boot does not + * support iommu at the driver level, so it also matches to the DMA address. + * Hence, this helper currently just performs the cache operation, then returns + * straight-mapped dma_address, which is intended to be set to the register of + * the DMA device. + * + * @vaddr: address of the buffer + * @len: length of the buffer + * @dir: the direction of DMA + */ +typedef u64_t dma_addr_t; + +void enable_caches(void); +void flush_cache(unsigned long addr, unsigned long size); +void flush_dcache_all(void); +void flush_dcache_range(unsigned long start, unsigned long stop); +void invalidate_dcache_range(unsigned long start, unsigned long stop); +void invalidate_dcache_all(void); +void invalidate_icache_all(void); + +static inline dma_addr_t dma_map_single(void *vaddr, size_t len, + enum dma_data_direction dir) +{ + unsigned long addr = (unsigned long)vaddr; + + len = ALIGN(len, ARCH_DMA_MINALIGN); + + // if (dir == DMA_FROM_DEVICE) + // invalidate_dcache_range(addr, addr + len); + // else + // flush_dcache_range(addr, addr + len); + + return addr; +} + +/** + * Unmap a buffer to make it available to CPU + * + * Linux-like DMA API that is intended to be used from drivers. This hides the + * underlying cache operation from drivers. Call this after finishin the DMA + * transfer. + * + * @addr: DMA address + * @len: length of the buffer + * @dir: the direction of DMA + */ +static inline void dma_unmap_single(dma_addr_t addr, size_t len, + enum dma_data_direction dir) +{ + len = ALIGN(len, ARCH_DMA_MINALIGN); + + // if (dir != DMA_TO_DEVICE) + // invalidate_dcache_range(addr, addr + len); +} + +#endif diff --git a/corev_apu/fpga/src/bootrom/src/dw_mmc.c b/corev_apu/fpga/src/bootrom/src/dw_mmc.c new file mode 100644 index 00000000000..baf157575a8 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/dw_mmc.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung + * Rajeshawari Shinde + */ + + + +#include "bootrom_time.h" +#include "uart.h" +#include "dwmmc.h" +#include "cache.h" +#include "bouncebuf.h" +#include "memalign.h" +// #include "wait_bit.h" + +#define PAGE_SIZE 4096 +#define FIFO_MODE 1 + +void write_print(u32_t print,u32_t address, u32_t val){ + writel(val,MMC_BASE_ADDR+address); + if (print){ + print_uart("WRITE L ADDR: "); + print_uart_int(MMC_BASE_ADDR+address); + print_uart(" DATA: "); + print_uart_int(val); + print_uart( "\n"); + } + + if(MMC_BASE_ADDR+address == 0x80000000UL){ + + print_uart("WRITING TO FIRST ADDRESS: "); + print_uart("WRITE L ADDR: "); + print_uart_int(MMC_BASE_ADDR+address); + print_uart(" DATA: "); + print_uart_int(val); + print_uart( "\n"); + } + +} + +u32_t read_print(u32_t print, u32_t address){ + u32_t val = readl(MMC_BASE_ADDR+address); + if (print){ + print_uart("READ L ADDR: "); + print_uart_int(MMC_BASE_ADDR+address); + print_uart("DATA: "); + print_uart_int(val); + print_uart( "\n"); + } + return val; +} +static int dwmci_wait_reset(u32_t value) +{ + unsigned long timeout = 1000; + u32_t ctrl; + + write_print(0, DWMCI_CTRL, value); + + while (timeout--) { + ctrl = read_print(0, DWMCI_CTRL); + if (!(ctrl & DWMCI_RESET_ALL)) + return 1; + } + return 0; +} + +static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, + u32_t desc0, u32_t desc1, u32_t desc2) +{ + struct dwmci_idmac *desc = idmac; + + desc->flags = desc0; + desc->cnt = desc1; + desc->addr = desc2; + desc->next_addr = (unsigned long)desc + sizeof(struct dwmci_idmac); + print_uart("descriptor pointer address: "); + print_uart_int(desc); + print_uart("set descriptor: flags "); + print_uart_int(desc->flags); + print_uart(" cnt "); + print_uart_int(desc->cnt); + print_uart(" addr "); + print_uart_int(desc->addr); + print_uart(" next_addr "); + print_uart_int(desc->next_addr); + print_uart("\n"); +} + +static void dwmci_prepare_data(struct mmc_data *data, + struct dwmci_idmac *cur_idmac, + void *bounce_buffer) +{ + unsigned long ctrl; + unsigned int i = 0, flags, cnt, blk_cnt; + unsigned long data_start, data_end; + + + blk_cnt = data->blocks; + + dwmci_wait_reset(DWMCI_CTRL_FIFO_RESET); + + /* Clear IDMAC interrupt */ + write_print(0, DWMCI_IDSTS, 0xFFFFFFFF); + + data_start = (unsigned long)cur_idmac; + write_print(0, DWMCI_DBADDR, (unsigned long)cur_idmac); + + do { + flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; + flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; + if (blk_cnt <= 8) { + flags |= DWMCI_IDMAC_LD; + cnt = data->blocksize * blk_cnt; + } else + cnt = data->blocksize * 8; + + dwmci_set_idma_desc(cur_idmac, flags, cnt, + (unsigned long)bounce_buffer + (i * PAGE_SIZE)); + + cur_idmac++; + if (blk_cnt <= 8) + break; + blk_cnt -= 8; + i++; + } while(1); + + print_uart("prepare data, skipping flush! \n"); + // data_end = (unsigned long)cur_idmac; + // flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN)); + + ctrl = read_print(1, DWMCI_CTRL); + ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; + write_print(0, DWMCI_CTRL, ctrl); + + ctrl = read_print(1, DWMCI_BMOD); + ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; + write_print(0, DWMCI_BMOD, ctrl); + + write_print(0, DWMCI_BLKSIZ, data->blocksize); + write_print(0, DWMCI_BYTCNT, data->blocksize * data->blocks); +} + +static int dwmci_fifo_ready(u32_t bit, u32_t *len) +{ + u32_t timeout = 20000; + // print_uart(" fifo ready get len: "); + *len = read_print(0, DWMCI_STATUS); + while (--timeout && (*len & bit)) { + udelay(200); + print_uart(" fifo ready get len inside while : "); + *len = read_print(1, DWMCI_STATUS); + } + + if (!timeout) { + print_uart("FIFO underflow timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + + +static int dwmci_data_transfer(struct mmc_data *data) +{ + int ret = 0; + u32_t timeout, mask, size, i, len = 0; + u32_t *buf = NULL; + // unsigned long start = get_timer(0); + // u32_t fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> + // RX_WMARK_SHIFT) + 1) * 2; + + size = data->blocksize * data->blocks; + // if (data->flags == MMC_DATA_READ) + buf = (unsigned int *)data->dest; + // else + // buf = (unsigned int *)data->src; + + timeout = 1000000; + + size /= 4; + read_print(0,DWMCI_STATUS); + for (;;) { + mask = read_print(0, DWMCI_RINTSTS); + int val = read_print(0,DWMCI_STATUS); + // if(val & 0x4) + // print_uart("FIFO empty \n"); + /* Error during data transfer. */ + if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { + print_uart("DATA ERROR!\n"); + ret = -EINVAL; + return ret; + } + + + + if (FIFO_MODE && size!=0) { + // print_uart("FIFO_MODE && size \n"); + len = 0; + if (data->flags == MMC_DATA_READ && + (mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) { + write_print(0, DWMCI_RINTSTS, + mask & (DWMCI_INTMSK_RXDR | + DWMCI_INTMSK_DTO)); + while (size) { + ret = dwmci_fifo_ready( DWMCI_FIFO_EMPTY, + &len); + if (ret < 0) + break; + + len = (len >> DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK; + len = min(size, len); + // print_uart("actually reading! to "); + // print_uart_int(buf); + // print_uart("\n"); + + // print_uart("size "); + // print_uart_int(size); + // print_uart("\n"); + + // print_uart("len "); + // print_uart_int(len); + // print_uart("\n"); + + for (i = 0; i < len; i++) + *buf++ = + read_print(0, DWMCI_DATA); + size = size > len ? (size - len) : 0; + } + } // else if (data->flags == MMC_DATA_WRITE && + // (mask & DWMCI_INTMSK_TXDR)) { + // while (size) { + // ret = dwmci_fifo_ready(host, + // DWMCI_FIFO_FULL, + // &len); + // if (ret < 0) + // break; + + // len = fifo_depth - ((len >> + // DWMCI_FIFO_SHIFT) & + // DWMCI_FIFO_MASK); + // len = min(size, len); + // for (i = 0; i < len; i++) + // write_print(0, DWMCI_DATA, + // *buf++); + // size = size > len ? (size - len) : 0; + // } + // write_print(0, DWMCI_RINTSTS, + // DWMCI_INTMSK_TXDR); + // } + } + + /* Data arrived correctly. */ + if (mask & DWMCI_INTMSK_DTO) { + ret = 0; + break; + } + + /* Check for timeout. */ + if (timeout-- > 0) { + udelay(10); + } + else { + read_print(1,DWMCI_STATUS); + print_uart("Timeout waiting for data!\n"); + ret = -ETIMEDOUT; + break; + } + } + + write_print(0, DWMCI_RINTSTS, mask); + + return ret; +} + +static int dwmci_set_transfer_mode() +{ + unsigned long mode; + + mode = DWMCI_CMD_DATA_EXP; + // if (data->flags & MMC_DATA_WRITE) + // mode |= DWMCI_CMD_RW; + + return mode; +} + + +static int dwmci_send_cmd(struct mmc_cmd *cmd, + struct mmc_data *data) +{ + + struct dwmci_idmac *cur_idmac = (struct dwmci_idmac *) (0xFFE30000); + + // ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, + // data ? DIV_ROUND_UP(data->blocks, 8) : 0); + int ret = 0, flags = 0, i; + unsigned int timeout = 500; + u32_t retry = 100000; + u32_t mask, ctrl,reg; + // unsigned long start = get_timer(0); + struct bounce_buffer bbstate; + + while (read_print(0, DWMCI_STATUS) & DWMCI_BUSY) { + if (timeout-- > 0) + { + udelay(10); + } + else { + read_print(1, DWMCI_STATUS); + print_uart("Timeout on data busy, continue anyway\n"); + break; + } + } + + write_print(0, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); + + if (data) { + if (FIFO_MODE) { + write_print(0, DWMCI_BLKSIZ, data->blocksize); + write_print(0, DWMCI_BYTCNT, + data->blocksize * data->blocks); + dwmci_wait_reset(DWMCI_CTRL_FIFO_RESET); + } else { + // if (data->flags == MMC_DATA_READ) { + ret = bounce_buffer_start(&bbstate, + (void*)data->dest, + data->blocksize * + data->blocks, GEN_BB_WRITE); + // } else { + // ret = bounce_buffer_start(&bbstate, + // (void*)data->src, + // data->blocksize * + // data->blocks, GEN_BB_READ); + // } + + if (ret) + return ret; + + dwmci_prepare_data(data, cur_idmac, + bbstate.bounce_buffer); + } + } + + write_print(0, DWMCI_CMDARG, cmd->cmdarg); + + if (data) + flags = dwmci_set_transfer_mode(); + + if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) + return -EBUSY; + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + flags |= DWMCI_CMD_ABORT_STOP; + else + flags |= DWMCI_CMD_PRV_DAT_WAIT; + + if (cmd->resp_type & MMC_RSP_PRESENT) { + flags |= DWMCI_CMD_RESP_EXP; + if (cmd->resp_type & MMC_RSP_136) + flags |= DWMCI_CMD_RESP_LENGTH; + } + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= DWMCI_CMD_CHECK_CRC; + + flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); + + // print_uart("Sending CMD\n"); + + write_print(0, DWMCI_CMD, flags); + + for (i = 0; i < retry; i++) { + mask = read_print(0, DWMCI_RINTSTS); + if (mask & DWMCI_INTMSK_CDONE) { + if (!data) + write_print(0, DWMCI_RINTSTS, mask); + break; + } + } + + if (i == retry) { + print_uart("Timeout. RINTSTS: "); + print_uart_int(mask); + print_uart("\n"); + + return -ETIMEDOUT; + } + + if (mask & DWMCI_INTMSK_RTO) { + /* + * Timeout here is not necessarily fatal. (e)MMC cards + * will splat here when they receive CMD55 as they do + * not support this command and that is exactly the way + * to tell them apart from SD cards. Thus, this output + * below shall be debug(). eMMC cards also do not favor + * CMD8, please keep that in mind. + */ + print_uart("Response Timeout.\n"); + return -ETIMEDOUT; + } else if (mask & DWMCI_INTMSK_RE) { + print_uart("Response Error.\n"); + return -EIO; + } else if ((cmd->resp_type & MMC_RSP_CRC) && + (mask & DWMCI_INTMSK_RCRC)) { + print_uart("Response CRC Error.\n"); + return -EIO; + } + + + if (cmd->resp_type & MMC_RSP_PRESENT) { + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = read_print(0, DWMCI_RESP3); + cmd->response[1] = read_print(0, DWMCI_RESP2); + cmd->response[2] = read_print(0, DWMCI_RESP1); + cmd->response[3] = read_print(0, DWMCI_RESP0); + } else { + cmd->response[0] = read_print(0, DWMCI_RESP0); + } + } + + if (data) { + ret = dwmci_data_transfer(data); + + /* only dma mode need it */ + if (!FIFO_MODE) { + // if (data->flags == MMC_DATA_READ) + mask = DWMCI_IDINTEN_RI; + // else + // mask = DWMCI_IDINTEN_TI; + + timeout = 1000; + ret = 1; + + while(timeout-- > 0){ + reg = read_print(0,DWMCI_IDSTS); + if ((reg & mask) == mask){ + ret = 0; + break; + } + + udelay(10); + } + // ret = wait_for_bit_le32(MMC_BASE_ADDR + DWMCI_IDSTS, + // mask, true, 1000, false); + if (ret){ + print_uart_int(reg); + print_uart(" DWMCI_IDINTEN mask timeout.\n"); + return ret; + } + /* clear interrupts */ + write_print(0, DWMCI_IDSTS, DWMCI_IDINTEN_MASK); + + ctrl = read_print(1, DWMCI_CTRL); + ctrl &= ~(DWMCI_DMA_EN); + write_print(0, DWMCI_CTRL, ctrl); + bounce_buffer_stop(&bbstate); + } + } + + udelay(100); + + return ret; +} + + +// Set the number of block to read from the SD card. +static u8_t set_block_count(u32_t blkcnt) +{ + u8_t err = 0; + struct mmc_cmd cmd23; + + cmd23.cmdidx = MMC_CMD_SET_BLOCK_COUNT; + cmd23.cmdarg = blkcnt; + cmd23.resp_type = MMC_RSP_R1; + + // mmc_trace_before_send(&cmd23); + err = dwmci_send_cmd(&cmd23, NULL); + // mmc_trace_after_send(&cmd23, err); + + return err; +} + + +// Copies the data blocks from the SD card to dst by sending the read command. The blkcnt argument type is u64_t because lbas are 64 bits integer in the gpt format. But the block size argument of the read command is a u32_t. Since blkcnt is the result of the subtraction between two lbas and given the size of the linux image, we assume blkcnt will NEVER be above the maximum value of a u32_t. We can then safely cast blkcnt from u64_t to u32_t. +u8_t sd_copy_mmc(void *dst, u64_t src_lba, u64_t blkcnt) +{ + u8_t err = 0; + + struct mmc_cmd cmd18; + struct mmc_data data; + + if (blkcnt > 1) + { + err = set_block_count(blkcnt); + if (err) + return err; + cmd18.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; + } + else + cmd18.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; + + /* + We assume the card is high capacity as all SD Card today are. + The check of the SD card high capacity property is done during "Send Operating Condition Command (ACMD41)" in the OCR register. + */ + // if (g_dwc_mshc->high_capacity) + cmd18.cmdarg = src_lba; + // else + // cmd18.cmdarg = src_lba * g_dwc_mshc->read_bl_len; + + cmd18.resp_type = MMC_RSP_R1; + + data.dest = dst; + // The blkcnt argument type is u64_t because lbas are 64 bits integer in the gpt format. But the block size argument of the read command is a u32_t. Since blkcnt is the result of the subtraction between two lbas and given the size of the linux image, we assume blkcnt will NEVER be above the maximum value of a u32_t. We can then safely cast blkcnt from u64_t to u32_t. + data.blocks = (u32_t) blkcnt; + data.blocksize = 0x200; // blocksize is 512 by default + data.flags = MMC_DATA_READ; + + // mmc_trace_before_send(&cmd18); + err = dwmci_send_cmd(&cmd18, &data); + // mmc_trace_after_send(&cmd18, err); + + return err; +} + diff --git a/corev_apu/fpga/src/bootrom/src/dwmmc.h b/corev_apu/fpga/src/bootrom/src/dwmmc.h new file mode 100644 index 00000000000..3d6acab5073 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/dwmmc.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung + */ + +#ifndef __DWMMC_HW_H +#define __DWMMC_HW_H + +// #include +// #include +#include "mmc.h" +#include "bootrom_errno.h" +#include "bootrom_io.h" +#include "cache.h" +// #include +#ifndef min +#define min(a,b) (((a) < (b)) ? (a) : (b)) +#endif +#define BIT(nr) (1UL << (nr)) +#define MMC_BASE_ADDR 0xFF808000 +#define MMC_MEM_SIZE 0x1000 + +#define DWMCI_CTRL 0x000 +#define DWMCI_PWREN 0x004 +#define DWMCI_CLKDIV 0x008 +#define DWMCI_CLKSRC 0x00C +#define DWMCI_CLKENA 0x010 +#define DWMCI_TMOUT 0x014 +#define DWMCI_CTYPE 0x018 +#define DWMCI_BLKSIZ 0x01C +#define DWMCI_BYTCNT 0x020 +#define DWMCI_INTMASK 0x024 +#define DWMCI_CMDARG 0x028 +#define DWMCI_CMD 0x02C +#define DWMCI_RESP0 0x030 +#define DWMCI_RESP1 0x034 +#define DWMCI_RESP2 0x038 +#define DWMCI_RESP3 0x03C +#define DWMCI_MINTSTS 0x040 +#define DWMCI_RINTSTS 0x044 +#define DWMCI_STATUS 0x048 +#define DWMCI_FIFOTH 0x04C +#define DWMCI_CDETECT 0x050 +#define DWMCI_WRTPRT 0x054 +#define DWMCI_GPIO 0x058 +#define DWMCI_TCMCNT 0x05C +#define DWMCI_TBBCNT 0x060 +#define DWMCI_DEBNCE 0x064 +#define DWMCI_USRID 0x068 +#define DWMCI_VERID 0x06C +#define DWMCI_HCON 0x070 +#define DWMCI_UHS_REG 0x074 +#define DWMCI_BMOD 0x080 +#define DWMCI_PLDMND 0x084 +#define DWMCI_DBADDR 0x088 +#define DWMCI_IDSTS 0x08C +#define DWMCI_IDINTEN 0x090 +#define DWMCI_DSCADDR 0x094 +#define DWMCI_BUFADDR 0x098 +#define DWMCI_DATA 0x200 + +/* Interrupt Mask register */ +#define DWMCI_INTMSK_ALL 0xffffffff +#define DWMCI_INTMSK_RE (1 << 1) +#define DWMCI_INTMSK_CDONE (1 << 2) +#define DWMCI_INTMSK_DTO (1 << 3) +#define DWMCI_INTMSK_TXDR (1 << 4) +#define DWMCI_INTMSK_RXDR (1 << 5) +#define DWMCI_INTMSK_RCRC (1 << 6) +#define DWMCI_INTMSK_DCRC (1 << 7) +#define DWMCI_INTMSK_RTO (1 << 8) +#define DWMCI_INTMSK_DRTO (1 << 9) +#define DWMCI_INTMSK_HTO (1 << 10) +#define DWMCI_INTMSK_FRUN (1 << 11) +#define DWMCI_INTMSK_HLE (1 << 12) +#define DWMCI_INTMSK_SBE (1 << 13) +#define DWMCI_INTMSK_ACD (1 << 14) +#define DWMCI_INTMSK_EBE (1 << 15) + +/* Raw interrupt Regsiter */ +#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ + DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) +#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) +/* CTRL register */ +#define DWMCI_CTRL_RESET (1 << 0) +#define DWMCI_CTRL_FIFO_RESET (1 << 1) +#define DWMCI_CTRL_DMA_RESET (1 << 2) +#define DWMCI_DMA_EN (1 << 5) +#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) +#define DWMCI_IDMAC_EN (1 << 25) +#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ + DWMCI_CTRL_DMA_RESET) + +/* CMD register */ +#define DWMCI_CMD_RESP_EXP (1 << 6) +#define DWMCI_CMD_RESP_LENGTH (1 << 7) +#define DWMCI_CMD_CHECK_CRC (1 << 8) +#define DWMCI_CMD_DATA_EXP (1 << 9) +#define DWMCI_CMD_RW (1 << 10) +#define DWMCI_CMD_SEND_STOP (1 << 12) +#define DWMCI_CMD_ABORT_STOP (1 << 14) +#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) +#define DWMCI_CMD_UPD_CLK (1 << 21) +#define DWMCI_CMD_USE_HOLD_REG (1 << 29) +#define DWMCI_CMD_START (1 << 31) + +/* CLKENA register */ +#define DWMCI_CLKEN_ENABLE (1 << 0) +#define DWMCI_CLKEN_LOW_PWR (1 << 16) + +/* Card-type registe */ +#define DWMCI_CTYPE_1BIT 0 +#define DWMCI_CTYPE_4BIT (1 << 0) +#define DWMCI_CTYPE_8BIT (1 << 16) + +/* Status Register */ +#define DWMCI_FIFO_EMPTY (1 << 2) +#define DWMCI_FIFO_FULL (1 << 3) +#define DWMCI_BUSY (1 << 9) +#define DWMCI_FIFO_MASK 0x1fff +#define DWMCI_FIFO_SHIFT 17 + +/* FIFOTH Register */ +#define MSIZE(x) ((x) << 28) +#define RX_WMARK(x) ((x) << 16) +#define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) + +#define DWMCI_IDMAC_OWN (1 << 31) +#define DWMCI_IDMAC_CH (1 << 4) +#define DWMCI_IDMAC_FS (1 << 3) +#define DWMCI_IDMAC_LD (1 << 2) + +/* Bus Mode Register */ +#define DWMCI_BMOD_IDMAC_RESET (1 << 0) +#define DWMCI_BMOD_IDMAC_FB (1 << 1) +#define DWMCI_BMOD_IDMAC_EN (1 << 7) + +/* UHS register */ +#define DWMCI_DDR_MODE (1 << 16) + +/* Internal IDMAC interrupt defines */ +#define DWMCI_IDINTEN_RI BIT(1) +#define DWMCI_IDINTEN_TI BIT(0) + +#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \ + DWMCI_IDINTEN_RI) + +/* quirks */ +#define DWMCI_QUIRK_DISABLE_SMU (1 << 0) + +/** + * struct dwmci_host - Information about a designware MMC host + * + * @name: Device name + * @ioaddr: Base I/O address of controller + * @quirks: Quick flags - see DWMCI_QUIRK_... + * @caps: Capabilities - see MMC_MODE_... + * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL + * @div: Arbitrary clock divider value for use by controller + * @dev_index: Arbitrary device index for use by controller + * @dev_id: Arbitrary device ID for use by controller + * @buswidth: Bus width in bits (8 or 4) + * @fifoth_val: Value for FIFOTH register (or 0 to leave unset) + * @mmc: Pointer to generic MMC structure for this device + * @priv: Private pointer for use by controller + */ +// struct dwmci_host { +// const char *name; +// void *ioaddr; +// unsigned int quirks; +// unsigned int caps; +// unsigned int version; +// unsigned int clock; +// unsigned int bus_hz; +// unsigned int div; +// int dev_index; +// int dev_id; +// int buswidth; +// u32_t fifoth_val; +// struct mmc *mmc; +// void *priv; + +// int (*clksel)(struct dwmci_host *host); +// void (*board_init)(struct dwmci_host *host); + +// /** +// * Get / set a particular MMC clock frequency +// * +// * This is used to request the current clock frequency of the clock +// * that drives the DWMMC peripheral. The caller will then use this +// * information to work out the divider it needs to achieve the +// * required MMC bus clock frequency. If you want to handle the +// * clock external to DWMMC, use @freq to select the frequency and +// * return that value too. Then DWMMC will put itself in bypass mode. +// * +// * @host: DWMMC host +// * @freq: Frequency the host is trying to achieve +// */ +// unsigned int (*get_mmc_clk)(struct dwmci_host *host, int freq); +// #ifndef CONFIG_BLK +// struct mmc_config cfg; +// #endif + +// /* use fifo mode to read and write data */ +// bool fifo_mode; +// }; + +struct dwmci_idmac { + u32_t flags; + u32_t cnt; + u32_t addr; + u32_t next_addr; +} __aligned(ARCH_DMA_MINALIGN); + +// static inline void dwmci_writel(struct dwmci_host *host, int reg, u32_t val) +// { +// writel(val, host->ioaddr + reg); +// } + +// static inline void dwmci_writew(struct dwmci_host *host, int reg, u16_t val) +// { +// writew(val, host->ioaddr + reg); +// } + +// static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8_t val) +// { +// writeb(val, host->ioaddr + reg); +// } +// static inline u32_t dwmci_readl(struct dwmci_host *host, int reg) +// { +// return readl(host->ioaddr + reg); +// } + +// static inline u16_t dwmci_readw(struct dwmci_host *host, int reg) +// { +// return readw(host->ioaddr + reg); +// } + +// static inline u8_t dwmci_readb(struct dwmci_host *host, int reg) +// { +// return readb(host->ioaddr + reg); +// } + +// #ifdef CONFIG_BLK +// /** +// * dwmci_setup_cfg() - Set up the configuration for DWMMC +// * +// * This is used to set up a DWMMC device when you are using CONFIG_BLK. +// * +// * This should be called from your MMC driver's probe() method once you have +// * the information required. +// * +// * Generally your driver will have a platform data structure which holds both +// * the configuration (struct mmc_config) and the MMC device info (struct mmc). +// * For example: +// * +// * struct rockchip_mmc_plat { +// * struct mmc_config cfg; +// * struct mmc mmc; +// * }; +// * +// * ... +// * +// * Inside U_BOOT_DRIVER(): +// * .plat_auto = sizeof(struct rockchip_mmc_plat), +// * +// * To access platform data: +// * struct rockchip_mmc_plat *plat = dev_get_plat(dev); +// * +// * See rockchip_dw_mmc.c for an example. +// * +// * @cfg: Configuration structure to fill in (generally &plat->mmc) +// * @host: DWMMC host +// * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) +// * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) +// */ +// void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, +// u32_t max_clk, u32_t min_clk); + +// /** +// * dwmci_bind() - Set up a new MMC block device +// * +// * This is used to set up a DWMMC block device when you are using CONFIG_BLK. +// * It should be called from your driver's bind() method. +// * +// * See rockchip_dw_mmc.c for an example. +// * +// * @dev: Device to set up +// * @mmc: Pointer to mmc structure (normally &plat->mmc) +// * @cfg: Empty configuration structure (generally &plat->cfg). This is +// * normally all zeroes at this point. The only purpose of passing +// * this in is to set mmc->cfg to it. +// * Return: 0 if OK, -ve if the block device could not be created +// */ +// int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); + +// #else +// /** +// * add_dwmci() - Add a new DWMMC interface +// * +// * This is used when you are not using CONFIG_BLK. Convert your driver over! +// * +// * @host: DWMMC host structure +// * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) +// * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) +// * Return: 0 if OK, -ve on error +// */ +// int add_dwmci(struct dwmci_host *host, u32_t max_clk, u32_t min_clk); +// #endif /* !CONFIG_BLK */ + +// #ifdef CONFIG_DM_MMC +// /* Export the operations to drivers */ +// int dwmci_probe(struct udevice *dev); +// extern const struct dm_mmc_ops dm_dwmci_ops; +// #endif + +#endif /* __DWMMC_HW_H */ diff --git a/corev_apu/fpga/src/bootrom/src/main.c b/corev_apu/fpga/src/bootrom/src/main.c index fe2f744ec86..fa11e446550 100644 --- a/corev_apu/fpga/src/bootrom/src/main.c +++ b/corev_apu/fpga/src/bootrom/src/main.c @@ -7,9 +7,8 @@ #include "sd.h" #include "gpt.h" -// 1 second at 50MHz -#define SECOND_CYCLES (50 * 1000 * 1000) -#define WAIT_SECONDS (5) +#define SECOND_CYCLES CLOCK_FREQUENCY +#define WAIT_SECONDS (10) static inline uintptr_t get_cycle_count() { uintptr_t cycle; @@ -48,6 +47,7 @@ int main() uint8_t uart_res = 0; uintptr_t start; + #ifndef PLAT_AGILEX init_uart(CLOCK_FREQUENCY, UART_BITRATE); //not needed in intel setup as UART IP is already configured via HW #endif @@ -73,11 +73,24 @@ int main() } else { print_uart(" booting!\r\n"); #ifndef PLAT_AGILEX - res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384); // linux boot not yet supported for altera + res = gpt_find_boot_partition((uint8_t *)0x80000000UL, 2 * 16384); + #else + int start_block_fw_payload = 0x32800; //payload at 100MB + print_uart("I am Agilex 7! \r\n"); + + print_uart("Loading fw_payload into memory address 0x80000000 \n"); + for (uint64_t i = 0; i < 15000; i++){ + res = sd_copy_mmc((uint8_t *)0x80000000UL + (i * 0x200), start_block_fw_payload + i, 1); // for now hardcoded, need to develop the code to find the file in the SD card + + if (res) + { + print_uart("TRANSFER ERROR\n"); + return res; + } + } #endif } - #ifndef PLAT_AGILEX // linux boot not yet supported for altera if (res == 0) { // jump to the address @@ -86,7 +99,6 @@ int main() "la a1, _dtb;" "jr s0"); } - #endif while (1) { diff --git a/corev_apu/fpga/src/bootrom/src/memalign.h b/corev_apu/fpga/src/bootrom/src/memalign.h new file mode 100644 index 00000000000..7c4efef6f96 --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/memalign.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Google, Inc + */ + +#ifndef __ALIGNMEM_H +#define __ALIGNMEM_H + +/* + * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It + * is used to align DMA buffers. + */ +#ifndef __ASSEMBLY__ +// #include +#include "cache.h" +#include + +/* + * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the + * stack that meets the minimum architecture alignment requirements for DMA. + * Such a buffer is useful for DMA operations where flushing and invalidating + * the cache before and after a read and/or write operation is required for + * correct operations. + * + * When called the macro creates an array on the stack that is sized such + * that: + * + * 1) The beginning of the array can be advanced enough to be aligned. + * + * 2) The size of the aligned portion of the array is a multiple of the minimum + * architecture alignment required for DMA. + * + * 3) The aligned portion contains enough space for the original number of + * elements requested. + * + * The macro then creates a pointer to the aligned portion of this array and + * assigns to the pointer the address of the first element in the aligned + * portion of the array. + * + * Calling the macro as: + * + * ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024); + * + * Will result in something similar to saying: + * + * uint32_t buffer[1024]; + * + * The following differences exist: + * + * 1) The resulting buffer is guaranteed to be aligned to the value of + * ARCH_DMA_MINALIGN. + * + * 2) The buffer variable created by the macro is a pointer to the specified + * type, and NOT an array of the specified type. This can be very important + * if you want the address of the buffer, which you probably do, to pass it + * to the DMA hardware. The value of &buffer is different in the two cases. + * In the macro case it will be the address of the pointer, not the address + * of the space reserved for the buffer. However, in the second case it + * would be the address of the buffer. So if you are replacing hard coded + * stack buffers with this macro you need to make sure you remove the & from + * the locations where you are taking the address of the buffer. + * + * Note that the size parameter is the number of array elements to allocate, + * not the number of bytes. + * + * This macro can not be used outside of function scope, or for the creation + * of a function scoped static buffer. It can not be used to create a cache + * line aligned global buffer. + */ +#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) +#define ALIGN_DOWN(x, a) ALIGN((x) - ((a) - 1), (a)) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + +#define __round_mask(x, y) ((__typeof__(x))((y)-1)) +#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) +#define round_down(x, y) ((x) & ~__round_mask(x, y)) + +#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f)) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) + +#define DIV_ROUND_DOWN_ULL(ll, d) \ + ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) + +#define DIV_ROUND_UP_ULL(ll, d) DIV_ROUND_DOWN_ULL((ll) + (d) - 1, (d)) + +#define ROUND(a, b) (((a) + (b) - 1) & ~((b) - 1)) + +#if BITS_PER_LONG == 32 +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d) +#else +# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d) +#endif + +/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */ +#define roundup(x, y) ( \ +{ \ + const typeof(y) __y = y; \ + (((x) + (__y - 1)) / __y) * __y; \ +} \ +) +#define rounddown(x, y) ( \ +{ \ + typeof(x) __x = (x); \ + __x - (__x % (y)); \ +} \ +) + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1) +#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad) +#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad) \ + char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align) \ + + (align - 1)]; \ + \ + type *name = (type *)ALIGN((uintptr_t)__##name, align) +#define ALLOC_ALIGN_BUFFER(type, name, size, align) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1) +#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad) \ + ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad) +#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ + ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + +/* + * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's + * purpose is to allow allocating aligned buffers outside of function scope. + * Usage of this macro shall be avoided or used with extreme care! + */ +#define DEFINE_ALIGN_BUFFER(type, name, size, align) \ + static char __##name[ALIGN(size * sizeof(type), align)] \ + __aligned(align); \ + \ + static type *name = (type *)__##name +#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \ + DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + +/** + * malloc_cache_aligned() - allocate a memory region aligned to cache line size + * + * This allocates memory at a cache-line boundary. The amount allocated may + * be larger than requested as it is rounded up to the nearest multiple of the + * cache-line size. This ensured that subsequent cache operations on this + * memory (flush, invalidate) will not affect subsequently allocated regions. + * + * @size: Minimum number of bytes to allocate + * + * Return: pointer to new memory region, or NULL if there is no more memory + * available. + */ +static inline void *malloc_cache_aligned(size_t size) +{ + return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); +} +#endif + +#endif /* __ALIGNMEM_H */ diff --git a/corev_apu/fpga/src/bootrom/src/mmc.h b/corev_apu/fpga/src/bootrom/src/mmc.h new file mode 100644 index 00000000000..6ab17a2306f --- /dev/null +++ b/corev_apu/fpga/src/bootrom/src/mmc.h @@ -0,0 +1,127 @@ +// Copyright (c) 2025 Thales Research and Technology +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +/** + * \file mmc.h + * \brief Contains all the symbols for the mmc commands. + * \author Julien Mallet + * +*/ + +#ifndef MMC_H +#define MMC_H + + +#include "bootrom_types.h" + +/* *************** DATA *************** */ +#define MMC_DATA_READ 1 + + +/* *************** VOLTAGE *************** */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ + + +/* *************** OCR *************** */ +#define OCR_HCS 0x40000000 +#define OCR_BUSY 0x80000000 + + +/* *************** MMC STATUS *************** */ +// #define MMC_STATUS_CURR_STATE (0xf << 9) + + +/* *************** MMC CMD *************** */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_STOP_TRANSMISSION 12 +// #define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_SET_BLOCK_COUNT 23 + + +#define MMC_CMD_APP_CMD 55 + +// SD SPECIFIC +#define SD_CMD_SEND_RELATIVE_ADDR 3 +// #define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_SEND_IF_COND 8 +#define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_SEND_SCR 51 + + +/* *************** MMC RESPONSE *************** */ +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) + + +/* *************** MMC STORAGE *************** */ + +/* Maximum block size for MMC */ +#define MMC_MAX_BLOCK_LEN 512 + + +/* *************** MMC STRUCTURES *************** */ + +struct mmc_cmd +{ + u8_t cmdidx; // Command index + u32_t resp_type; // Response type + u32_t cmdarg; // Command argument + u32_t response[4]; // Response array +}; + + +struct mmc_data +{ + u8_t *dest; + + u32_t flags; + u32_t blocks; + u32_t blocksize; +}; + + +struct sdhci_host_t +{ + u32_t dma_buf_addr; // addr of the buffer used by the dma + u16_t rca; // relative card address + u8_t bus_width; +}; + + +/* *************** FUNCTIONS SIGNATURES *************** */ + + +// MMC CMD +u8_t mmc_go_idle(volatile struct sdhci_host_t *g_dwc_mshc); +u8_t mmc_send_if_cond(volatile struct sdhci_host_t *g_dwc_mshc); +u8_t sd_send_op_cond(volatile struct sdhci_host_t *g_dwc_mshc); +u8_t mmc_send_cid(volatile struct sdhci_host_t *g_dwc_mshc); +u8_t sd_send_rca(volatile struct sdhci_host_t *g_dwc_mshc); +u8_t sd_send_csd(volatile struct sdhci_host_t *g_dwc_mshc); +u8_t sd_select_card(volatile struct sdhci_host_t *g_dwc_mshc); +u8_t sd_send_scr(volatile struct sdhci_host_t *g_dwc_mshc); +// u32_t mmc_send_status(volatile struct sdhci_host_t *g_dwc_mshc); +u8_t mmc_set_blocklen(volatile struct sdhci_host_t *g_dwc_mshc, u32_t len); +u8_t sd_copy(volatile struct sdhci_host_t *g_dwc_mshc, void *dst, u64_t src_lba, u64_t blkcnt); + + +#endif \ No newline at end of file diff --git a/corev_apu/fpga/src/bootrom/src/spi.c b/corev_apu/fpga/src/bootrom/src/spi.c index b79ae6680af..cd4784acf30 100644 --- a/corev_apu/fpga/src/bootrom/src/spi.c +++ b/corev_apu/fpga/src/bootrom/src/spi.c @@ -119,7 +119,7 @@ int spi_write_bytes(uint8_t *bytes, uint32_t len, uint8_t *ret) for (int i = 0; i < len;) { status = read_reg(SPI_STATUS_REG); - if ((status & 0x1) != 0x1) // recieve fifo not empty + if ((status & 0x1) != 0x1) // receive fifo not empty { ret[i++] = read_reg(SPI_RECEIVE_REG); } diff --git a/corev_apu/fpga/src/bootrom/src/uart.c b/corev_apu/fpga/src/bootrom/src/uart.c index 79a4ee8b786..7a22b32f103 100644 --- a/corev_apu/fpga/src/bootrom/src/uart.c +++ b/corev_apu/fpga/src/bootrom/src/uart.c @@ -15,6 +15,11 @@ uint8_t read_reg_u8(uintptr_t addr) return *(volatile uint8_t *)addr; } +uint32_t read_reg_u32(uintptr_t addr) +{ + return *(volatile uint32_t *)addr; +} + int is_transmit_empty() { return read_reg_u8(UART_LINE_STATUS) & 0x20; @@ -22,7 +27,7 @@ int is_transmit_empty() char is_transmit_empty_altera() { - return read_reg_u8(UART_THR+6); + return ((read_reg_u8(UART_THR+7) << 8 ) + read_reg_u8(UART_THR+6)); } int is_receive_empty() @@ -30,7 +35,7 @@ int is_receive_empty() #ifndef PLAT_AGILEX return !(read_reg_u8(UART_LINE_STATUS) & 0x1); #else - return !(read_reg_u8(UART_THR+1) & 0x8); + return (read_reg_u8(UART_THR) == 0); #endif } diff --git a/corev_apu/fpga/src/bootrom/src/uart.h b/corev_apu/fpga/src/bootrom/src/uart.h index 38c7e44a44c..b7cbc47e5ef 100644 --- a/corev_apu/fpga/src/bootrom/src/uart.h +++ b/corev_apu/fpga/src/bootrom/src/uart.h @@ -20,7 +20,7 @@ #define UART_DLAB_LSB UART_BASE + 0 #define UART_DLAB_MSB UART_BASE + 4 -void init_uart(); +void init_uart(uint32_t freq, uint32_t baud); int read_serial(uint8_t *res); diff --git a/corev_apu/fpga/src/genesysii.svh b/corev_apu/fpga/src/genesysii.svh index 0456b92ef0a..650f597b842 100644 --- a/corev_apu/fpga/src/genesysii.svh +++ b/corev_apu/fpga/src/genesysii.svh @@ -8,7 +8,7 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -// Description: Set global FPGA degines +// Description: Set global FPGA defines // Author: Florian Zaruba `define GENESYSII @@ -17,5 +17,5 @@ `define ARIANE_DATA_WIDTH 64 -// Instantiate protocl checker +// Instantiate protocol checker // `define PROTOCOL_CHECKER diff --git a/corev_apu/fpga/src/kc705.svh b/corev_apu/fpga/src/kc705.svh index bd17d0aebdf..6d3749c20de 100644 --- a/corev_apu/fpga/src/kc705.svh +++ b/corev_apu/fpga/src/kc705.svh @@ -8,7 +8,7 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -// Description: Set global FPGA degines +// Description: Set global FPGA defines // Author: Florian Zaruba `define KC705 @@ -17,5 +17,5 @@ `define ARIANE_DATA_WIDTH 64 -// Instantiate protocl checker +// Instantiate protocol checker // `define PROTOCOL_CHECKER diff --git a/corev_apu/fpga/src/nexys_video.svh b/corev_apu/fpga/src/nexys_video.svh index 62231990122..912ef31e4bb 100644 --- a/corev_apu/fpga/src/nexys_video.svh +++ b/corev_apu/fpga/src/nexys_video.svh @@ -2,7 +2,7 @@ `define ARIANE_DATA_WIDTH 64 -// Instantiate protocl checker +// Instantiate protocol checker // `define PROTOCOL_CHECKER // write-back cache diff --git a/corev_apu/fpga/src/vc707.svh b/corev_apu/fpga/src/vc707.svh index ac7b20a9d52..e60568f7db3 100644 --- a/corev_apu/fpga/src/vc707.svh +++ b/corev_apu/fpga/src/vc707.svh @@ -8,12 +8,12 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -// Description: Set global FPGA degines +// Description: Set global FPGA defines // Author: Florian Zaruba `define VC707 `define ARIANE_DATA_WIDTH 64 -// Instantiate protocl checker +// Instantiate protocol checker // `define PROTOCOL_CHECKER diff --git a/corev_apu/fpga/src/vcu118.svh b/corev_apu/fpga/src/vcu118.svh index 47440a844bd..0713c214fcb 100644 --- a/corev_apu/fpga/src/vcu118.svh +++ b/corev_apu/fpga/src/vcu118.svh @@ -8,7 +8,7 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -// Description: Set global FPGA degines +// Description: Set global FPGA defines // Author: Florian Zaruba `define VCU118 diff --git a/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml b/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml index 2b3c0c1e518..a4ec93211b0 100644 --- a/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml +++ b/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml @@ -50,6 +50,17 @@ xlnx_clk_gen: clkout4_requested_out_freq: 50 clkin1_jitter_ps: 50 +xlnx_dpti_clk: + ip: clk_wiz + vendor: xilinx.com + config: + prim_in_freq: 60 + num_out_clks: 2 + clkout2_used: true + clkout1_requested_out_freq: 60 + clkout1_requested_phase: 230 + clkout2_requested_out_freq: 60 + xlnx_ila: ip: ila vendor: xilinx.com diff --git a/corev_apu/fpga/xilinx/xlnx_dpti_clk/Makefile b/corev_apu/fpga/xilinx/xlnx_dpti_clk/Makefile new file mode 100644 index 00000000000..d1acb462e20 --- /dev/null +++ b/corev_apu/fpga/xilinx/xlnx_dpti_clk/Makefile @@ -0,0 +1,2 @@ +PROJECT:=xlnx_dpti_clk +include ../common.mk \ No newline at end of file diff --git a/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl/run.tcl b/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl/run.tcl new file mode 100644 index 00000000000..d836651eabf --- /dev/null +++ b/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl/run.tcl @@ -0,0 +1,26 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +set ipName xlnx_dpti_clk + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName + +set_property -dict [list CONFIG.PRIM_IN_FREQ {60.000} \ + CONFIG.NUM_OUT_CLKS {2} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {60} \ + CONFIG.CLKOUT1_REQUESTED_PHASE {230.000} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {60} \ + CONFIG.USE_RESET {false} \ + ] [get_ips $ipName] + + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 + diff --git a/corev_apu/instr_tracing/DPTI/Digilent.licence b/corev_apu/instr_tracing/DPTI/Digilent.licence new file mode 100644 index 00000000000..124159423de --- /dev/null +++ b/corev_apu/instr_tracing/DPTI/Digilent.licence @@ -0,0 +1,40 @@ +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software including rights to use, copy, redistribute, and/or sublicense the +Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The Software is only to be used with Digilent Inc. hardware directly or with +Digilent Inc. hardware included in an OEM device. + +The Software may be used for the development of custom programs by the +licensee, for use ONLY with Digilent Inc. hardware. This includes, but is not +limited to, all Dynamic Link Libraries (DLLs), Shared Libraries, documentation, +header files, and Applications Programming Interfaces (APIs). + +You agree that you will not modify, adapt, decompile, reverse engineer, +translate, or otherwise attempt to discover the source code for the Software. + +Digilent Inc. maintains all its rights under all applicable laws, including but +not limited to pertinent intellectual property laws. + +The above copyright notice and this permission notice shall be included in all +copies of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + +Copyright (c) 2022 Digilent Inc. + +Contact: +1300 NE Henley Ct. Suite 3 +Pullman, WA 99163 +United States of America + +digilent.com/support + \ No newline at end of file diff --git a/corev_apu/instr_tracing/DPTI/dpti_ctrl.vhd b/corev_apu/instr_tracing/DPTI/dpti_ctrl.vhd new file mode 100755 index 00000000000..7395fdab8f0 --- /dev/null +++ b/corev_apu/instr_tracing/DPTI/dpti_ctrl.vhd @@ -0,0 +1,399 @@ +---------------------------------------------------------------------------------- +-- Company: Digilent Inc. +-- Engineer: +-- +-- Create Date: 16:16:24 10/26/2011 +-- Design Name: +-- Module Name: dpti_ctrl - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: This module implements a synchronous DPTI interface. It includes +-- two local FIFOs that allow the data to be moved from the DPTI clock domain +-- to another clock domain in the FPGA. +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- 5/30/2016(sjb) -- Prepared for public release +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +Library UNIMACRO; +use UNIMACRO.vcomponents.all; + +entity dpti_ctrl is + Port ( + --User Write FIFO signals + wr_clk : in std_logic; + wr_en : in std_logic; + wr_full : out std_logic; + wr_afull : out std_logic; + wr_err : out std_logic; + wr_count : out std_logic_vector(11 downto 0); + wr_di : in std_logic_vector(7 downto 0); + + --User Read FIFO signals + rd_clk : in std_logic; + rd_en : in std_logic; + rd_empty : out std_logic; + rd_aempty : out std_logic; + rd_err : out std_logic; + rd_count : out std_logic_vector(11 downto 0); + rd_do : out std_logic_vector(7 downto 0); + + --misc. signals + rst : in std_logic; --Asynchronously resets the entire component. Must be held high for at least 100ns, or 6 clock cycles of the slowest fifo clock if that is longer + + --DPTI Port signals + prog_clko : in STD_LOGIC; + prog_rxen : in STD_LOGIC; + prog_txen : in STD_LOGIC; + prog_spien : in STD_LOGIC; --called jtagen on some platforms + prog_rdn : out STD_LOGIC; + prog_wrn : out STD_LOGIC; + prog_oen : out STD_LOGIC; + prog_siwun : out STD_LOGIC; + prog_d : inout STD_LOGIC_VECTOR (7 downto 0)); +end dpti_ctrl; + +architecture Behavioral of dpti_ctrl is + + + + + +------------------------------------------------------------------------------- +-- Component Declarations +------------------------------------------------------------------------------- + +component xlnx_dpti_clk is +port + ( + CLK_IN1 : in std_logic; + CLK_OUT1 : out std_logic; + CLK_OUT2 : out std_logic; + LOCKED : out std_logic + ); +end component; + +------------------------------------------------------------------------------- +-- Local Type Declarations +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- Constant Declarations +------------------------------------------------------------------------------- + +-- The following constants define state codes for the Synchronous PTI port +-- state machine. The high order bits of the state number provide a unique +-- state identifier for each state. The low order bits are the state machine +-- outputs for that state. This type of state machine implementation uses no +-- combinational logic to generate the outputs, which should result in glitch +-- free outputs. + + +constant stPtiRdy : std_logic_vector(6 downto 0):= "0" & "00" & "1111"; +constant stPtiInOut0 : std_logic_vector(6 downto 0):= "1" & "00" & "1111"; +constant stPtiInOut1 : std_logic_vector(6 downto 0):= "1" & "00" & "1011"; +constant stPtiInOut2 : std_logic_vector(6 downto 0):= "1" & "01" & "1010"; +constant stPtiInOut3 : std_logic_vector(6 downto 0):= "1" & "10" & "0101"; + +------------------------------------------------------------------------------- +-- Signal Declarations +------------------------------------------------------------------------------- + +signal stPtiCur : std_logic_vector(6 downto 0) := stPtiRdy; +signal stPtiNext : std_logic_vector(6 downto 0); + +signal clkPti : std_logic; +signal clkIOB : std_logic; +signal locked : std_logic; + +--user fifo signals +signal usrWrClk : std_logic; +signal usrWrEn : std_logic; +signal usrFull : std_logic; +signal usrAFull : std_logic; +signal usrWrErr : std_logic; +signal usrRdClk : std_logic; +signal usrRdEn : std_logic; +signal usrEmpty : std_logic; +signal usrAEmpty : std_logic; +signal usrRdErr : std_logic; +signal usrRdCnt : std_logic_vector(11 downto 0); +signal usrDO : std_logic_vector(7 downto 0); +signal usrWrCnt : std_logic_vector(11 downto 0); +signal usrDI : std_logic_vector(7 downto 0); + +-- Internal control signals +signal ctlRd : std_logic; +signal ctlWr : std_logic; +signal ctlOe : std_logic; +signal ctlDir : std_logic; + +signal ctlRxf : std_logic; +signal ctlTxe : std_logic; +signal ctlRst : std_logic; + +signal ctlFull : std_logic; +signal ctlAFull : std_logic; +signal ctlEmpty : std_logic; +signal ctlFwr : std_logic; +signal ctlFrd : std_logic; + +signal dummyWrCnt : std_logic_vector(11 downto 0); +signal dummyRdCnt : std_logic_vector(11 downto 0); + +signal busPtiTris : std_logic; +signal busPtiOut : std_logic_vector(7 downto 0); + +signal busPtiIn : std_logic_vector(7 downto 0); +signal busPtiInReg : std_logic_vector(7 downto 0); +signal busFifoOut : std_logic_vector(7 downto 0); + +------------------------------------------------------------------------------- +-- Module Implementation +------------------------------------------------------------------------------- + +begin + +--This clocking wizard is used to sychronize the clock used throughout this design +--with the prog_clko input. It reduces delays introduced by the global clocking +--network (~4ns in post-route simulation on Artix 200t). It is also used to generate +--a phase shifted clock for latching input data/flags +clkwiz_inst : xlnx_dpti_clk + port map + ( + CLK_IN1 => prog_clko, + CLK_OUT1 => clkIOB, + CLK_OUT2 => clkPti, + LOCKED => locked); + +--This process latches the inputs from the FTDI part at IOB flip-flops. They are latched +--using a phaseshifted clock about ~11ns after the rising edge of the input clock. This +--makes meeting the input delay timing constraints possible. Additional contstraints for +--traveling from the clkIOB domain to clkPti are automatically inferred by the tools +--because they have a known phase relationship (signals will need to settle in <~5ns). +--If the design fails interclock timing analysis with clkIOB, first ensure that IOB flip +--flops are being instantiated for the registers in this process. Then you can try reducing +--the phase shift by a few degrees (too much will cause the inputdelay constraints to fail). Last +--resort is to modify the design so that these flags are all immediately latched to the clkPti +--domain. +--@sjb: I recently came across this code and began questioning if it is necessary. At first thought, it seems +-- that latching the input signals would add to needed setup times vs. just letting them thru +-- asynchronously. It took me awhile, but I believe I understand why this is needed, so I have decided +-- to document my reasoning further for the next time someone comes across this. +-- I believe I inserted these because the FTDI part only holds the data on the bus valid for 1 ns +-- after a prog_clk edge, and I was concerned that the databus/ctrl signals might +-- beat the clock due to delays introduced by the clocking infrastructure. The IOBs treat this situation +-- by ensuring the data/ctrl gets latched internally the moment it is guarenteed to be valid. This seems like +-- the most architecture independent way to treat the problem, because it only requires three things, all of which +-- are very likely to be present in future FPGA architectures/devices: +-- 1) Ability to generate a clock with minimum input delay (~<3ns) +-- 2) IOB flip-flops with minimum setup requirement (~<3ns) +-- 3) Ability to generate a clock with a 230 degree phase shift relative to the generated clock with minimum input delay. +-- Last note, I think the input_delay constraints with the -min option in timing.xdc describe this requirement +-- to the tools. I'm pretty sure removing these flip-flops will cause the design to fail meeting those constraints. + +process(ctlRst, clkIOB) +begin + if (ctlRst = '1') then + busPtiInReg <= (others =>'0'); + ctlRxf <= '0'; + ctlTxe <= '0'; + elsif (rising_edge(clkIOB)) then + busPtiInReg <= busPtiIn; + ctlRxf <= prog_rxen; + ctlTxe <= prog_txen; + end if; +end process; + +------------------------------------------------------------------------------- +-- Map basic status and control signals +------------------------------------------------------------------------------- + +--Asynchronous reset signal +ctlRst <= (prog_spien or rst) or not(locked); + + +--Top level output mapping +prog_siwun <= '1'; +prog_wrn <= ctlWr; +prog_rdn <= ctlRd; +prog_oen <= ctlOe; + +-- Data bus direction and control. +IOBUF_gen : for index in 0 to 7 generate + IOBUF_inst : IOBUF + generic map ( + DRIVE => 16, + SLEW => "FAST") + port map ( + O => busPtiIn(index), -- Buffer output + IO => prog_d(index), -- Buffer inout port (connect directly to top-level port) + I => busPtiOut(index), -- Buffer input + T => busPtiTris -- 3-state enable input, high=input, low=output + ); +end generate; + +busPtiTris <= ctlDir or ctlRst; + +------------------------------------------------------------------------------- +-- PTI State Machine +------------------------------------------------------------------------------- + +-- Map glitch-less control signals from the current state +ctlRd <= stPtiCur(0); --keep in mind: active low +ctlWr <= stPtiCur(1) or ctlEmpty; --keep in mind: active low +ctlOe <= stPtiCur(2); +ctlDir <= stPtiCur(3); + +--Map additional control signals from the current state +ctlFwr <= stPtiCur(4) and not ctlRxf; +ctlFrd <= stPtiCur(5) and ((not ctlTxe) and (not ctlEmpty)); + +-- This process moves the state machine to the next state on each clock. +process (clkPti, ctlRst) +begin + if ctlRst = '1' then + stPtiCur <= stPtiRdy; + elsif clkPti = '1' and clkPti'Event then + stPtiCur <= stPtiNext; + end if; +end process; + +-- This process determines the next state based on the current state and the +-- state machine inputs. +-- TODO: It appears the bandwidth is very limited when the FTDI->FPGA FPGA side FIFO +-- gets almost filled (4080 out of 4096). Almost full seems to take a very long time +-- to deassert, regardless of how fast the user is reading data. This causes the state machine +-- to continuosly receive a single byte at a time (1/3 bandwidth) until the FIFO is full, or until +-- the FIFO has been read by the user past the almost fill point and no data has been available on +-- the DPTI bus for a long time (~50 us). Need to fix this because it will lower bandwidth of designs that involve +-- continuously sending large amounts of data to the FPGA. +process (stPtiCur, stPtiNext, ctlRxf, ctlTxe, ctlFull, ctlAFull, ctlEmpty) +begin + case stPtiCur is + when stPtiRdy => + stPtiNext <= stPtiInOut0; + + when stPtiInOut0 => --Start any pending transactions + if ctlRxf = '0' and ctlFull = '0' then --Receive data from FTDI (gets priority) + stPtiNext <= stPtiInOut1; + elsif ctlTxe = '0' and ctlEmpty = '0' then --send data to FTDI + stPtiNext <= stPtiInOut3; + else --no transaction yet + stPtiNext <= stPtiInOut0; + end if; + + when stPtiInOut1 => --Initiate read transaction (FTDI->FPGA) + stPtiNext <= stPtiInOut2; + + when stPtiInOut2 => --Continue Read transaction + if ctlRxf = '0' and ctlAFull = '0' then + stPtiNext <= stPtiInOut2; + else --if no data available, or FPGA-side FIFO is almost full, stop transaction + stPtiNext <= stPtiInOut0; + end if; + + when stPtiInOut3 => --Start/Continue write transaction (FPGA->FTDI) + if ctlTxe = '0' and ctlEmpty = '0' then --note almost empty is used because the FIFO is first-word fall thru + stPtiNext <= stPtiInOut3; + else --if FTDI FIFO is full, or we are on the last byte being sent, stop transaction + stPtiNext <= stPtiInOut0; + end if; + + when others => + stPtiNext <= stPtiRdy; + end case; +end process; + +------------------------------------------------------------------------------- +-- Input/Output Fifos for data +------------------------------------------------------------------------------- + +--Output Fifo +usr2dpti_fifo : FIFO_DUALCLOCK_MACRO +generic map ( + DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES" + ALMOST_FULL_OFFSET => X"0FF0", -- Sets almost full threshold + ALMOST_EMPTY_OFFSET => X"000F", -- Sets the almost empty threshold + DATA_WIDTH => 8, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb") + FIFO_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb" + FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE +port map ( + ALMOSTEMPTY => open, -- 1-bit output almost empty + ALMOSTFULL => usrAFull, -- 1-bit output almost full + DO => busPtiOut, -- Output data, width defined by DATA_WIDTH parameter + EMPTY => ctlEmpty, -- 1-bit output empty + FULL => usrFull, -- 1-bit output full + RDCOUNT => dummyRdCnt, -- Output read count, width determined by FIFO depth + RDERR => open, -- 1-bit output read error + WRCOUNT => usrWrCnt, -- Output write count, width determined by FIFO depth + WRERR => usrWrErr, -- 1-bit output write error + DI => usrDI, -- Input data, width defined by DATA_WIDTH parameter + RDCLK => clkPti, -- 1-bit input read clock + RDEN => ctlFrd, -- 1-bit input read enable + RST => ctlRst, -- 1-bit input reset + WRCLK => usrWrClk, -- 1-bit input write clock + WREN => usrWrEn -- 1-bit input write enable +); + +usrWrClk <= wr_clk; +usrWrEn <= wr_en; +wr_full <= usrFull; +wr_afull <= usrAFull; +wr_err <= usrWrErr; +wr_count <= usrWrCnt; +usrDI <= wr_di; + +--Input Fifo +dpti2usr_fifo : FIFO_DUALCLOCK_MACRO +generic map ( + DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES" + ALMOST_FULL_OFFSET => X"0FF0", -- Sets almost full threshold + ALMOST_EMPTY_OFFSET => X"000F", -- Sets the almost empty threshold + DATA_WIDTH => 8, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb") + FIFO_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb" + FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE +port map ( + ALMOSTEMPTY => usrAEmpty, -- 1-bit output almost empty + ALMOSTFULL => ctlAFull, -- 1-bit output almost full + DO => usrDO, -- Output data, width defined by DATA_WIDTH parameter + EMPTY => usrEmpty, -- 1-bit output empty + FULL => ctlFull, -- 1-bit output full + RDCOUNT => usrRdCnt, -- Output read count, width determined by FIFO depth + RDERR => usrRdErr, -- 1-bit output read error + WRCOUNT => dummyWrCnt, -- Output write count, width determined by FIFO depth + WRERR => open, -- 1-bit output write error + DI => busPtiInReg, -- Input data, width defined by DATA_WIDTH parameter + RDCLK => usrRdClk, -- 1-bit input read clock + RDEN => usrRdEn, -- 1-bit input read enable + RST => ctlRst, -- 1-bit input reset + WRCLK => clkPti, -- 1-bit input write clock + WREN => ctlFwr -- 1-bit input write enable +); + +usrRdClk <= rd_clk; +usrRdEn <= rd_en; +rd_empty <= usrEmpty; +rd_aempty <= usrAEmpty; +rd_err <= usrRdErr; +rd_count <= usrRdCnt; +rd_do <= usrDO; + +end Behavioral; + diff --git a/corev_apu/instr_tracing/DPTI/slicer_DPTI.sv b/corev_apu/instr_tracing/DPTI/slicer_DPTI.sv new file mode 100644 index 00000000000..7a80687cc3c --- /dev/null +++ b/corev_apu/instr_tracing/DPTI/slicer_DPTI.sv @@ -0,0 +1,66 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 21/05/2025 +module slicer_DPTI #( + parameter SLICE_LEN = 32, + parameter NO_TIME = 0 // 0 : include time ; 1 : exclude time +) ( + input logic clk_i, + input logic rst_ni, + + input logic valid_i, + input encap_pkg::encap_fifo_entry_s encap_fifo_entry_i, + input logic fifo_full_i, + + output logic valid_o, + output logic [SLICE_LEN-1:0] slice_o, + output logic done_o +); + localparam DATA_LEN = encap_pkg::H_LEN + (NO_TIME ? 0 : encap_pkg::T_LEN) + encap_pkg::PAYLOAD_LEN; + localparam NUM_SLICES = DATA_LEN / SLICE_LEN; + localparam COUNT_LEN = $clog2(NUM_SLICES); + + logic [DATA_LEN-1 : 0] data_to_slice_q, data_to_slice_d; + logic [COUNT_LEN-1:0] slice_index_d, slice_index_q; + logic running_q, running_d; + + assign slice_o = data_to_slice_q[DATA_LEN-1:DATA_LEN-SLICE_LEN]; + assign valid_o = running_q && !fifo_full_i; + assign done_o = running_q && (slice_index_q == NUM_SLICES - 1) && !fifo_full_i; + + always_comb begin + data_to_slice_d = data_to_slice_q; + slice_index_d = slice_index_q; + running_d = running_q; + + if (valid_i && !running_q) begin + //new data to slice + data_to_slice_d = NO_TIME ? {encap_fifo_entry_i.header,encap_fifo_entry_i.payload} : + {encap_fifo_entry_i.header,encap_fifo_entry_i.timestamp,encap_fifo_entry_i.payload}; + slice_index_d = 0; + running_d = 1; + end else if (running_q && !fifo_full_i) begin // Stall if fifo is full + //Slicing + data_to_slice_d = data_to_slice_q << SLICE_LEN; + slice_index_d = slice_index_q + 1; + if (slice_index_q == NUM_SLICES - 1) begin + running_d = 0; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + data_to_slice_q <= '0; + slice_index_q <= '0; + running_q <= '0; + end else begin + data_to_slice_q <= data_to_slice_d; + slice_index_q <= slice_index_d; + running_q <= running_d; + end + end + + +endmodule diff --git a/corev_apu/instr_tracing/Decapsuler/Decapsuler.cpp b/corev_apu/instr_tracing/Decapsuler/Decapsuler.cpp new file mode 100644 index 00000000000..fea1d5aba7a --- /dev/null +++ b/corev_apu/instr_tracing/Decapsuler/Decapsuler.cpp @@ -0,0 +1,311 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 17/06/2025 +// Contributors: +// Côme Allart - Thales + +// This code is designed to decapsulate a RAW format into a csv Trace. It is used to convert them in a human readable format for CI diff. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +const size_t NR_PKT = 20; +const size_t PACKET_SIZE = 40; +const size_t BLOCK_SIZE = NR_PKT * PACKET_SIZE; +typedef unsigned char BYTE; +using packet_t = std::array; +typedef std::array sample_t; + +uint64_t extract_bits(const packet_t &packet, std::size_t bit_offset, + std::size_t bit_length) { // FIXME add assertion to prevent desynchro segfault + uint64_t result = 0xdead; // We use 'dead' as an indicator to quickly detect if a desynchro happened during the aquisition (without stoping decapsulation) + if (bit_length <= 64) { + result = 0; + for (std::size_t i = 0; i < bit_length; ++i) { + std::size_t global_bit = bit_offset + i; + std::size_t byte_index = global_bit / 8; + std::size_t bit_index = 7 - (global_bit % 8); + uint64_t bit = (packet[byte_index] >> bit_index) & 0x1; + result = (result << 1) | bit; + } + } + return result; +} + +template struct PrintableOption : public std::optional { + PrintableOption(std::optional &o) : std::optional(o) {} + PrintableOption(T &v) : std::optional(v) {} + PrintableOption(uint64_t v) : std::optional(v) {} + PrintableOption() : std::optional() {} + + friend std::ostream &operator<<(std::ostream &s, const PrintableOption &o) { + if (o.has_value()) + s << unsigned(*o); + else + s << "_"; + + return s; + } +}; + +struct BitExtractor { + const packet_t &packet; + bool is_backward; + size_t i; + + BitExtractor(const packet_t &packet, bool backward) + : packet(packet), is_backward(backward), + i(backward ? PACKET_SIZE * 8 : 0) {} + + uint64_t operator()(size_t bits) { return extract(bits); } + uint64_t to(size_t bit) { return extract_to(bit); } + + uint64_t extract_to(size_t bit) { return extract(i - bit); } + uint64_t extract(size_t bits) { + if (is_backward) + i -= bits; + + uint64_t result = extract_bits(packet, i, bits); + + if (!is_backward) + i += bits; + + return result; + } +}; + +struct Trace { + bool P_Time; // MSB + uint8_t P_ID; // 2 bits after MSB + uint8_t P_Size; // 5bits after P_ID + uint64_t P_Timestamp; // 64 bits after P_Size + PrintableOption format; // 2bits LSB + PrintableOption subformat; // 2bits before LSB if format=3 + PrintableOption address; // start of payload + PrintableOption branch; // F3SF0 (5) F3SF1 (5) else NDF + PrintableOption branches; // F1 (3) + PrintableOption branch_map; // F1 (4 : branches) + PrintableOption branch_count; // NDF + PrintableOption branch_fmt; // NDF + PrintableOption context; // NDF + PrintableOption ecause; //F3SF1 (8) F3SF1T (70) + PrintableOption ienable; //F3SF3 (5) + PrintableOption encoder_mode;//F3SF3 (6) + PrintableOption interrupt; // F3SF1(9) F3SF1T(71) + PrintableOption irreport; // F2 (5) F1(5) + PrintableOption irdepth; //if call/ret F2(6:2^cal) F1(6:2^cal) else NDF + PrintableOption notify; // F2(3) F1(3) + PrintableOption ioptions; //F3SF3 (8:15) + PrintableOption privilege; // F3SF0 (6) F3SF1 (6) F3SF2 (5) + PrintableOption qual_status;// F3SF3(7) + PrintableOption time; //if time F3SF0(8:72) F3SF1(8:72) F3SF2(7:71) //FIXME encoder could have time in last position + PrintableOption thaddr; // F3SF1(40) F3SF1_t(104) + PrintableOption tval; //F3SF1 (41:73) F3SF1_t(105:137) + PrintableOption updiscon;// F2(4) + PrintableOption denable;// NDF here + PrintableOption dloss;// NDF here + PrintableOption doptions;// NDF here + uint8_t size_branch_map; + + Trace(const packet_t &packet, bool time_flag, bool call_flag) { + size_branch_map = 0; + + BitExtractor header_extractor(packet, false); + BitExtractor payload_extractor(packet, true); + + // Header of encapsulated packet : + P_Time = header_extractor(1); + P_ID = header_extractor(2); + P_Size = header_extractor(5); + size_t P_Start = (PACKET_SIZE - P_Size) * 8; + P_Timestamp = header_extractor(64); + + // Extraction of fields contained in the payload : + format = payload_extractor(2); + if (format == 3) { + subformat = payload_extractor(2); + } + + if (format == 3 && subformat.has_value()) { + switch (subformat.value()) { + case 0: { // F3SF0 + branch = payload_extractor(1); + privilege = payload_extractor(2); + if (time_flag) { + time = payload_extractor(64); + } + address = payload_extractor.to(P_Start); + break; + } + case 1: { // F3SF1 + branch = payload_extractor(1); + privilege = payload_extractor(2); + if (time_flag) { + time = payload_extractor(64); + } + ecause = payload_extractor(32); + interrupt = payload_extractor(1); + thaddr = payload_extractor(1); + tval = payload_extractor(32); + address = payload_extractor.to(P_Start); + break; + } + case 2: { // F3SF2 + privilege = payload_extractor(2); + if (time_flag) { + time = payload_extractor(64); + } + break; + } + case 3: { // F3SF3 + ienable = payload_extractor(1); + encoder_mode = payload_extractor(1); + qual_status = payload_extractor(2); + ioptions = payload_extractor(7); + break; + } + } + } + + // F2 + if (format == 2) { + notify = payload_extractor(1); + updiscon = payload_extractor(1); + irreport = payload_extractor(1); + if (call_flag) { // FIXME addapt to call_counter_size + irdepth = payload_extractor(1); // if = 0 else 2^call_counter_size + } + address = payload_extractor.to(P_Start); + } + + // F1 + if (format == 1) { + branches = payload_extractor(5); + if (branches == 0) { + size_branch_map = 31; + } else if (branches == 1) { + size_branch_map = 1; + } else if (branches <= 3) { + size_branch_map = 3; + } else if (branches <= 7) { + size_branch_map = 7; + } else if (branches <= 15) { + size_branch_map = 15; + } else { + size_branch_map = 31; + } + branch_map = payload_extractor(size_branch_map); + + if (branches != 0) { + notify = payload_extractor(1); + updiscon = payload_extractor(1); + irreport = payload_extractor(1); + if (call_flag) { // FIXME addapt to call_counter_size + irdepth = payload_extractor(1); // if = 0 else 2^call_counter_size + } + address = payload_extractor.to(P_Start); + } + } + } + + static std::string csvHeader() { + return std::string( + "format,subformat,address,branch,branches,branch_map,branch_count," + "branch_fmt,context,ecause,ienable,encoder_mode,interrupt,irreport," + "irdepth,notify,ioptions,privilege,qual_status,time,thaddr,tval," + "updiscon,denable,dloss,doptions"); + } + + friend std::ostream &operator<<(std::ostream &s, Trace const &trace) { + trace.put_str(s); + return s; + } + + std::ostream &put_str(std::ostream &s) const { + s << format << "," << subformat << ","; + + s << std::hex << std::nouppercase << address << std::dec << ","; + + s << branch << "," << branches << "," << branch_map << "," << branch_count + << "," << branch_fmt << ","; + + s << context << "," << ecause << "," << ienable << "," << encoder_mode + << "," << interrupt << ","; + + s << irreport << "," << irdepth << "," << notify << "," << ioptions << "," + << privilege << "," << qual_status << ","; + + s << std::hex << std::nouppercase << time << std::dec << ","; + + s << thaddr << "," << tval << "," << updiscon << "," << denable << "," + << dloss << "," << doptions; + + return s; + } + + std::string toCSVLine() { + std::ostringstream oss; + oss << *this; + return oss.str(); + } +}; + + packet_t hexstr_to_packet(const std::string &hexstr){ + unsigned int byte; + packet_t packet; + for (int i=0; i< 40; i++){ + std::sscanf(hexstr.c_str() + 2*i, "%2x",&byte); + packet[i] = (BYTE) byte; + } + return packet; + } + + std::filesystem::path ext_csv(const std::filesystem::path &pi) { + auto po = pi ; + po.replace_extension(".csv"); + return po; + } + +int main(int argc, char* argv[]) { + if (argc <2){ + std::cerr << "Usage: "<< argv[0] <<" Filepath \n"; + return 1; + } + + const bool TIME_FLAG = 1; + const bool CALL_FLAG = 0; + std::filesystem::path nameFile_i = argv[1]; + std::filesystem::path nameFile_o = ext_csv(nameFile_i); + + std::vector all_packets; + std::ifstream file_to_extract(nameFile_i); + std::ofstream csvFile(nameFile_o); + std::string line; + + while(std::getline(file_to_extract,line)){ + packet_t packet; + packet=hexstr_to_packet(line); + all_packets.push_back(packet); + } + + std::cout << "Number packet read :" << all_packets.size() << std::endl; + csvFile << Trace::csvHeader() << "\n"; + for (packet_t &packet : all_packets){ + Trace trace(packet, TIME_FLAG, CALL_FLAG); + csvFile << trace.toCSVLine() << "\n"; + } + + return 0; +} \ No newline at end of file diff --git a/corev_apu/instr_tracing/Decapsuler/Makefile b/corev_apu/instr_tracing/Decapsuler/Makefile new file mode 100644 index 00000000000..5de6887a2a7 --- /dev/null +++ b/corev_apu/instr_tracing/Decapsuler/Makefile @@ -0,0 +1,29 @@ +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales + +# Makefile to build the Decapsuler executable + +CC = $(GCC_11_5_PATH)/g++ +TARGETS = Decapsuler +CFLAGS = -Wall -Wextra -g + +all: $(TARGETS) + +Decapsuler: Decapsuler.cpp + $(CC) --version + $(CC) -o Decapsuler Decapsuler.cpp $(CFLAGS) + +.PHONY: clean + +clean: + rm -f $(TARGETS) + +clean_all: + rm -f $(TARGETS) + rm -rf receiver_data diff --git a/corev_apu/instr_tracing/Decapsuler/affiche_csv.py b/corev_apu/instr_tracing/Decapsuler/affiche_csv.py new file mode 100644 index 00000000000..5d29ce00f26 --- /dev/null +++ b/corev_apu/instr_tracing/Decapsuler/affiche_csv.py @@ -0,0 +1,34 @@ +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales +# Script used to print a csv file in a more readable way +import pandas as pd +import argparse +import os + +pd.set_option('display.max_columns',None) +pd.set_option('display.max_rows',None) +pd.set_option("display.width",220) + +parser = argparse.ArgumentParser(description="Print the CSV file in a more readable format") +parser.add_argument("--file","-f",required=True, help="CSV file path") +args = parser.parse_args() + +csv_path = args.file + +if not os.path.isfile(csv_path): + print(f"Error '{csv_path}' does not exist") + exit(1) + +df = pd.read_csv(csv_path) + +#print(df) + +output_filename = os.path.splitext(os.path.basename(csv_path))[0] + "_output.txt" +with open(output_filename, "w",encoding="utf-8") as f: + f.write(df.to_string(index=False)) \ No newline at end of file diff --git a/corev_apu/instr_tracing/Decapsuler/compare_encoder.sh b/corev_apu/instr_tracing/Decapsuler/compare_encoder.sh new file mode 100755 index 00000000000..823ba3408dc --- /dev/null +++ b/corev_apu/instr_tracing/Decapsuler/compare_encoder.sh @@ -0,0 +1,52 @@ +#!/usr/bin/env bash +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales + +set -euo pipefail + +if [ "$#" -ne 2 ]; then + echo "Usage: $0 " + exit 2 +fi + +dir_work="encoder_log" +rm -rf "$dir_work" +mkdir -p "$dir_work" + +trace_raw_path="$1" +trace_ref_path="$2" + + +base_raw=$(basename "$trace_raw_path") +base_ref=$(basename "$trace_ref_path") + + +for trace in "$trace_raw_path" "$trace_ref_path"; do + if [ ! -f "$trace" ]; then + echo "ERROR file '$trace' does not exist" + exit 1 + fi + base=$(basename "$trace") + cp "$trace" "$dir_work/$base" +done + +trace_raw="$dir_work/$base_raw" +trace_ref="$dir_work/$base_ref" + +./Decapsuler "$trace_raw" + +python3 affiche_csv.py -f "$dir_work/${base_raw%.txt}.csv" +mv "${base_raw%.txt}_output.txt" "$dir_work" +python3 affiche_csv.py -f "$trace_ref" +mv "${base_ref%.te_inst}_output.txt" "$dir_work" + + +python3 diff_color.py "$dir_work/${base_raw%.txt}.csv" "$trace_ref" + + \ No newline at end of file diff --git a/corev_apu/instr_tracing/Decapsuler/debug_encoder_diff.sh b/corev_apu/instr_tracing/Decapsuler/debug_encoder_diff.sh new file mode 100644 index 00000000000..85afb5745bf --- /dev/null +++ b/corev_apu/instr_tracing/Decapsuler/debug_encoder_diff.sh @@ -0,0 +1,23 @@ +#!/bin/bash +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales + +exit_error() { + echo "$1" >&2 + exit ${2:-1} +} + +if [ "$#" -ne 1 ]; then + exit_error "Usage: $0 " 2 +fi + +exe="$1" +base=$(basename "$exe" .o) + +#TODO \ No newline at end of file diff --git a/corev_apu/instr_tracing/Decapsuler/diff_color.py b/corev_apu/instr_tracing/Decapsuler/diff_color.py new file mode 100644 index 00000000000..be107c9974f --- /dev/null +++ b/corev_apu/instr_tracing/Decapsuler/diff_color.py @@ -0,0 +1,104 @@ +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales + + +import csv +import sys +import re + +def gray(s): return f"\033[90m{s}\033[0m" +def red(s): return f"\033[91m{s}\033[0m" +def green(s): return f"\033[92m{s}\033[0m" +def white(s): return f"\033[97m{s}\033[0m" + +ANSI_ESCAPE= re.compile + +def strip(text): + return re.sub(r'\x1b\[[0-9;]*m','',text) + +def read_csv_to_matrix(filepath): + with open(filepath,newline='') as csvfile: + reader = csv.reader(csvfile,delimiter=',') + rows = list(reader) + header = rows[0] + data = rows[1:] + return header,data + + + +def format_value(val_gen, val_ref): + if val_gen is None: + return f"{red('NDF')}{white(' -> ')}{green(val_ref)}" + elif val_gen == val_ref: + return gray(val_gen) + else: + return f"{red(val_gen)}{white(' -> ')}{green(val_ref)}" + +def compare_matrices(header,gen_data,ref_data): + max_rows = max(len(gen_data),len(ref_data)) + num_cols = len(header) + result_matrix = [[None for _ in range (num_cols)] for _ in range(max_rows)] + + for row_idx in range(max_rows): + for col_idx in range(num_cols): + try: + val_ref = ref_data[row_idx][col_idx] + except IndexError: + val_ref="" + try: + val_gen = gen_data[row_idx][col_idx] + except IndexError: + val_gen=None + result_matrix[row_idx][col_idx] = format_value(val_gen,val_ref) + + return result_matrix + +def print_column_by_column(header,matrix,cols_per_block=8): + num_cols = len(header) + num_rows = len(matrix) + + for block_start in range(0,num_cols, cols_per_block): + block_end = min(block_start + cols_per_block,num_cols) + block_indices = range(block_start,block_end) + + col_widths =[] + for i in block_indices: + max_len = max(len(strip(matrix[r][i])) for r in range(num_rows)) + max_len = max(max_len, len(header[i])) + col_widths.append(max_len + 2) + header_line ="" + for i,w in zip(block_indices,col_widths): + header_line += header[i].center(w) + " " + print(header_line) + + for r in range(num_rows): + row_line = "" + for i,w in zip(block_indices,col_widths): + content = matrix[r][i] + pad_len = w - len(strip(content)) + left_pad = pad_len // 2 + right_pad = pad_len - left_pad + row_line += " "*left_pad + content + " "*right_pad + " " + print(row_line) + + print("\n") + +if __name__ == "__main__": + if len(sys.argv) != 3: + print("usage : diff.py ") + sys.exit(1) + + gen_path = sys.argv[1] + ref_path = sys.argv[2] + + gen_header, gen_data = read_csv_to_matrix(gen_path) + ref_header , ref_data = read_csv_to_matrix(ref_path) + + matrix = compare_matrices(ref_header,gen_data,ref_data) + print_column_by_column(ref_header,matrix,cols_per_block=14) diff --git a/corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv b/corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv new file mode 100644 index 00000000000..aaa2e0d115f --- /dev/null +++ b/corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv @@ -0,0 +1,96 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 20/03/2025 +// Contributors: +// Darshak Sheladiya, SYSGO GmbH +// Umberto Laghi, UNIBO + +//Systolic module used to determines the iaddr, ilastsize, iretire for Encoder Module + + +module block_retirement #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type uop_entry_t = logic, + parameter type itt_out_t = logic, + parameter CAUSE_LEN = 5, //Size is ecause_width_p in the E-Trace SPEC + parameter ITYPE_LEN = 3, //Size is itype_width_p in the E-Trace SPEC (3 or 4) + parameter IRETIRE_LEN = 32 //Size is iretire_width_p in the E-Trace SPEC +) ( + input uop_entry_t uop_entry_i, + input logic [ CAUSE_LEN-1:0] cause_i, + input logic [CVA6Cfg.XLEN-1:0] tval_i, + input logic [ IRETIRE_LEN-1:0] counter_i, + input logic [CVA6Cfg.XLEN-1:0] iaddr_i, + input logic was_special_i, + + output itt_out_t itt_out_o, + output logic [ IRETIRE_LEN-1:0] counter_o, + output logic [CVA6Cfg.XLEN-1:0] iaddr_o, + output logic is_special_o +); + + logic special_inst; + logic exception; + logic interrupt; + assign special_inst = !(uop_entry_i.itype inside {iti_pkg::INT, iti_pkg::EXC, iti_pkg::STANDARD}) && uop_entry_i.valid ; + assign exception = (uop_entry_i.itype == iti_pkg::EXC) ? 1'b1 : 1'b0; + assign interrupt = (uop_entry_i.itype == iti_pkg::INT) ? 1'b1 : 1'b0; + + always_comb begin + counter_o = counter_i; + is_special_o = was_special_i; + iaddr_o = iaddr_i; + itt_out_o = '0; + + if (uop_entry_i.valid) begin + + if (was_special_i) begin + counter_o = 0; + iaddr_o = uop_entry_i.pc; + is_special_o = 1'b0; + end + + counter_o = uop_entry_i.compressed ? counter_o + 1 : counter_o + 2; + + if (special_inst) begin + itt_out_o.valid = 1'b1; + itt_out_o.iretire = counter_o; + itt_out_o.itype = uop_entry_i.itype; + itt_out_o.ilastsize = ~uop_entry_i.compressed; + itt_out_o.iaddr = iaddr_o; + itt_out_o.priv = uop_entry_i.priv; + itt_out_o.cycles = uop_entry_i.cycles; + itt_out_o.cause = '0; + itt_out_o.tval = '0; + is_special_o = 1'b1; + end + + if (interrupt) begin + itt_out_o.valid = 1'b1; + itt_out_o.iretire = uop_entry_i.compressed ? 1 : 2; + itt_out_o.itype = uop_entry_i.itype; + itt_out_o.ilastsize = ~uop_entry_i.compressed; + itt_out_o.iaddr = uop_entry_i.pc; + itt_out_o.priv = uop_entry_i.priv; + itt_out_o.cycles = uop_entry_i.cycles; + itt_out_o.cause = cause_i; + itt_out_o.tval = '0; + is_special_o = 1'b1; + end + + if (exception) begin + itt_out_o.valid = 1'b1; + itt_out_o.iretire = uop_entry_i.compressed ? 1 : 2; + itt_out_o.itype = uop_entry_i.itype; + itt_out_o.ilastsize = ~uop_entry_i.compressed; + itt_out_o.iaddr = uop_entry_i.pc; + itt_out_o.priv = uop_entry_i.priv; + itt_out_o.cycles = uop_entry_i.cycles; + itt_out_o.cause = cause_i; + itt_out_o.tval = tval_i; + is_special_o = 1'b1; + end + end + end +endmodule diff --git a/corev_apu/instr_tracing/ITI/cva6_iti/iti.sv b/corev_apu/instr_tracing/ITI/cva6_iti/iti.sv new file mode 100644 index 00000000000..c8f69536ca3 --- /dev/null +++ b/corev_apu/instr_tracing/ITI/cva6_iti/iti.sv @@ -0,0 +1,214 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 20/03/2025 +// Contributors: +// Darshak Sheladiya, SYSGO GmbH +// Umberto Laghi, UNIBO + +// For reference : See Section 4.2 Instruction Trace Interface from Efficient Trace for RISC-V v2.0 (may 5 2022) +// iti stand for Instruction Trace Interface, changing because tip (Trace Ingress Port) and "type" are too similar creating confusion + +module cva6_iti #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter CAUSE_LEN = 5, //Size is ecause_width_p in the E-Trace SPEC + parameter ITYPE_LEN = 3, //Size is itype_width_p in the E-Trace SPEC (3 or 4) + parameter IRETIRE_LEN = 32, //Size is iretire_width_p in the E-Trace SPEC + parameter block_mode = 0, + parameter type rvfi_to_iti_t = logic, + parameter type iti_to_encoder_t = logic +) ( + input logic clk_i, + input logic rst_ni, + + input logic [CVA6Cfg.NrCommitPorts-1:0] valid_i, + input rvfi_to_iti_t rvfi_to_iti_i, + + output logic [CVA6Cfg.NrCommitPorts-1:0] valid_o, + output iti_to_encoder_t iti_to_encoder_o +); + + // pragma translate_off + int f; + initial begin + f = $fopen("iti.traces", "w"); + $fwrite(f, "itype_0,cause,tval,priv,iaddr_0,context,ctype,iretire_0,ilastsize_0\n"); + end + final $fclose(f); + // pragma translate_on + + /* Structure used for each instr*/ + localparam type uop_entry_t = struct packed { + logic valid; + logic [CVA6Cfg.XLEN-1:0] pc; + iti_pkg::itype_t itype; + logic compressed; + riscv::priv_lvl_t priv; + logic [63:0] cycles; + }; + + /* Structure used to output trace_signals if special instr */ + localparam type itt_out_t = struct packed { + logic valid; + logic [IRETIRE_LEN-1:0] iretire; + iti_pkg::itype_t itype; + logic ilastsize; + logic [CVA6Cfg.XLEN-1:0] iaddr; + riscv::priv_lvl_t priv; + logic [CAUSE_LEN-1:0] cause; + logic [CVA6Cfg.XLEN-1:0] tval; + logic [63:0] cycles; + }; + + logic interrupt; + iti_pkg::itype_t [CVA6Cfg.NrCommitPorts-1:0] itype; + + logic [IRETIRE_LEN-1:0] counter_d, counter_q; + logic [CVA6Cfg.XLEN-1:0] addr_d, addr_q; + logic special_d, special_q; + + uop_entry_t [CVA6Cfg.NrCommitPorts-1:0] uop_entry; + itt_out_t [CVA6Cfg.NrCommitPorts-1:0] itt_out; + + logic [CVA6Cfg.NrCommitPorts-1:0][IRETIRE_LEN-1:0] counter_itt; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] addr_itt; + logic [CVA6Cfg.NrCommitPorts-1:0] special_itt; + logic [CVA6Cfg.NrCommitPorts-1:0][CAUSE_LEN-1:0] cause_itt; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] tval_itt; + + logic [CVA6Cfg.NrCommitPorts-1:0][IRETIRE_LEN-1:0] counter; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] addr; + logic [CVA6Cfg.NrCommitPorts-1:0] special; + + + assign interrupt = rvfi_to_iti_i.cause[CVA6Cfg.XLEN-1]; // determined based on the MSB of cause + + for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + itype_detector #( + .ITYPE_LEN(ITYPE_LEN) + ) i_itype_detector ( + .valid_i (valid_i[i]), + .exception_i (rvfi_to_iti_i.ex_valid), + .interrupt_i (interrupt), + .op_i (rvfi_to_iti_i.op[i]), + .branch_taken_i(rvfi_to_iti_i.is_taken[i]), + .itype_o (itype[i]) + ); + + // Adding this to ensure that interrupt/exception happen only in commit port 0 of cva6 + assign cause_itt[i] = i == 0 ? rvfi_to_iti_i.cause[CAUSE_LEN-1:0] : '0; + assign tval_itt[i] = i == 0 ? rvfi_to_iti_i.tval : '0; + + if (block_mode) begin + // Systolic logic (First block_retirement is connected to D Flip-Flop to continue computation if needed) + assign counter_itt[i] = i == 0 ? counter_q : counter[i-1]; + assign addr_itt[i] = i == 0 ? addr_q : addr[i-1]; + assign special_itt[i] = i == 0 ? special_q : special[i-1]; + + block_retirement #( + .CVA6Cfg(CVA6Cfg), + .uop_entry_t(uop_entry_t), + .itt_out_t(itt_out_t), + .CAUSE_LEN(CAUSE_LEN), + .ITYPE_LEN(ITYPE_LEN), + .IRETIRE_LEN(IRETIRE_LEN) + ) i_block_retirement ( + .uop_entry_i(uop_entry[i]), + .cause_i(cause_itt[i]), + .tval_i(tval_itt[i]), + .counter_i(counter_itt[i]), + .iaddr_i(addr_itt[i]), + .was_special_i(special_itt[i]), + .itt_out_o(itt_out[i]), + .counter_o(counter[i]), + .iaddr_o(addr[i]), + .is_special_o(special[i]) + ); + + end else begin + single_retirement #( + .CVA6Cfg(CVA6Cfg), + .uop_entry_t(uop_entry_t), + .itt_out_t(itt_out_t), + .CAUSE_LEN(CAUSE_LEN), + .ITYPE_LEN(ITYPE_LEN), + .IRETIRE_LEN(IRETIRE_LEN) + ) i_single_retirement ( + .uop_entry_i(uop_entry[i]), + .cause_i(cause_itt[i]), + .tval_i(tval_itt[i]), + .itt_out_o(itt_out[i]) + ); + + end + end + + + always_comb begin + iti_to_encoder_o.cause = '0; + iti_to_encoder_o.tval = '0; + iti_to_encoder_o.priv = riscv::PRIV_LVL_U; + iti_to_encoder_o.cycles = '0; + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + uop_entry[i].valid = valid_i[i]; + uop_entry[i].pc = rvfi_to_iti_i.pc[i]; + uop_entry[i].itype = itype[i]; + uop_entry[i].compressed = rvfi_to_iti_i.is_compressed[i]; + uop_entry[i].priv = rvfi_to_iti_i.priv_lvl; + uop_entry[i].cycles = rvfi_to_iti_i.cycles; + + iti_to_encoder_o.valid[i] = 1'b0; + iti_to_encoder_o.iretire[i] = '0; + iti_to_encoder_o.ilastsize[i] = '0; + iti_to_encoder_o.itype[i] = iti_pkg::STANDARD; + iti_to_encoder_o.iaddr[i] = '0; + + valid_o[i] = 1'b0; + + if (itt_out[i].valid) begin + valid_o[i] = itt_out[i].valid; + iti_to_encoder_o.valid[i] = itt_out[i].valid; + iti_to_encoder_o.iretire[i] = itt_out[i].iretire; + iti_to_encoder_o.ilastsize[i] = itt_out[i].ilastsize; + iti_to_encoder_o.itype[i] = itt_out[i].itype; + iti_to_encoder_o.iaddr[i] = itt_out[i].iaddr; + iti_to_encoder_o.priv = itt_out[i].priv; // privilege don't change between 2 instr committed in the same cycle + iti_to_encoder_o.cycles = itt_out[i].cycles; // Same here (same time at same cycle) + end + end + if (itt_out[0].valid) begin // interrupt & exception only in port 0 + iti_to_encoder_o.cause = itt_out[0].cause; + iti_to_encoder_o.tval = itt_out[0].tval; + end + end + if (block_mode) begin + assign counter_d = counter[CVA6Cfg.NrCommitPorts-1]; + assign addr_d = addr[CVA6Cfg.NrCommitPorts-1]; + assign special_d = special[CVA6Cfg.NrCommitPorts-1]; + end + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (block_mode) begin + if (!rst_ni) begin + counter_q <= '0; + addr_q <= '0; + special_q <= 1'b1; + end else begin + counter_q <= counter_d; + addr_q <= addr_d; + special_q <= special_d; + end + end + //pragma translate_off + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + if (itt_out[i].valid) begin + $fwrite(f, "%d,%0d,%0d,%d,%h,0,0,%0d,%0d\n", itt_out[i].itype, itt_out[i].cause, + itt_out[i].tval, itt_out[i].priv, itt_out[i].iaddr, itt_out[i].iretire, + itt_out[i].ilastsize); + end + end + //pragma translate_on + end + + +endmodule diff --git a/corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv b/corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv new file mode 100755 index 00000000000..5c503ab2d5d --- /dev/null +++ b/corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv @@ -0,0 +1,92 @@ +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at + +// https://solderpad.org/licenses/SHL-2.1/ + +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Umberto Laghi +// Contact: umberto.laghi@studio.unibo.it +// Github: @ubolakes +// Contributors: +// Darshak Sheladiya, SYSGO GmbH +// Maxime COLSON, Thales CDI France + +/* ITYPE DETECTOR */ +/* +it produces the type of the instruction +*/ + +module itype_detector #( + parameter ITYPE_LEN = 3 //Size is itype_width_p in the E-Trace SPEC (3 or 4) +) ( + input logic valid_i, + input logic exception_i, + input logic interrupt_i, + input ariane_pkg::fu_op op_i, + input logic branch_taken_i, + output iti_pkg::itype_t itype_o +); + + // internal signals + logic exception; + logic interrupt; + logic eret; + logic nontaken_branch; + logic taken_branch; + logic updiscon; + + // assignments + assign exception = exception_i; + assign interrupt = interrupt_i; // no need to have an inst committed + + + + + assign eret = op_i inside {ariane_pkg::MRET, ariane_pkg::SRET, ariane_pkg::DRET}; + + assign nontaken_branch = ( op_i == ariane_pkg::EQ || + op_i == ariane_pkg::NE || + op_i == ariane_pkg::LTS || + op_i == ariane_pkg::GES || + op_i == ariane_pkg::LTU || + op_i == ariane_pkg::GEU) && + ~branch_taken_i; + + assign taken_branch = ( op_i == ariane_pkg::EQ || + op_i == ariane_pkg::NE || + op_i == ariane_pkg::LTS || + op_i == ariane_pkg::GES || + op_i == ariane_pkg::LTU || + op_i == ariane_pkg::GEU) && + branch_taken_i; + + assign updiscon = op_i == ariane_pkg::JALR; + + // assigning the itype + always_comb begin + // initialization + itype_o = iti_pkg::STANDARD; + + if (exception) begin // exception + itype_o = iti_pkg::EXC; + end else if (interrupt) begin // interrupt + itype_o = iti_pkg::INT; + end else if (valid_i) begin + if (eret) begin // exception or interrupt return + itype_o = iti_pkg::ERET; + end else if (nontaken_branch) begin // nontaken branch + itype_o = iti_pkg::NON_TAKEN_BR; + end else if (taken_branch) begin // taken branch + itype_o = iti_pkg::TAKEN_BR; + end else if (ITYPE_LEN == 3 && updiscon) begin // uninferable discontinuity + itype_o = iti_pkg::UNINF_JMP; + end + end + end + +endmodule diff --git a/corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv b/corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv new file mode 100644 index 00000000000..a9d4a668be9 --- /dev/null +++ b/corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv @@ -0,0 +1,56 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 20/03/2025 + +//Module used to determines the iaddr, ilastsize, iretire in single retirement for Encoder Module + + +module single_retirement #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type uop_entry_t = logic, + parameter type itt_out_t = logic, + parameter CAUSE_LEN = 5, //Size is ecause_width_p in the E-Trace SPEC + parameter ITYPE_LEN = 3, //Size is itype_width_p in the E-Trace SPEC (3 or 4) + parameter IRETIRE_LEN = 32 //Size is iretire_width_p in the E-Trace SPEC +) ( + input uop_entry_t uop_entry_i, + input logic [ CAUSE_LEN-1:0] cause_i, + input logic [CVA6Cfg.XLEN-1:0] tval_i, + output itt_out_t itt_out_o +); + + + logic exception; + logic interrupt; + assign exception = (uop_entry_i.itype == iti_pkg::EXC) ? 1'b1 : 1'b0; + assign interrupt = (uop_entry_i.itype == iti_pkg::INT) ? 1'b1 : 1'b0; + + always_comb begin + itt_out_o = '0; + + if (uop_entry_i.valid) begin + + itt_out_o.valid = 1'b1; + itt_out_o.iretire = 1; + itt_out_o.itype = uop_entry_i.itype; + itt_out_o.ilastsize = ~uop_entry_i.compressed; + itt_out_o.iaddr = uop_entry_i.pc; + itt_out_o.priv = uop_entry_i.priv; + itt_out_o.cycles = uop_entry_i.cycles; + itt_out_o.cause = '0; + itt_out_o.tval = '0; + + if (interrupt) begin + itt_out_o.cause = cause_i; + itt_out_o.tval = '0; + end + + if (exception) begin + itt_out_o.cause = cause_i; + itt_out_o.tval = tval_i; + end + + end + end +endmodule diff --git a/corev_apu/instr_tracing/ITI/include/iti_pkg.sv b/corev_apu/instr_tracing/ITI/include/iti_pkg.sv new file mode 100644 index 00000000000..0099f9e5e10 --- /dev/null +++ b/corev_apu/instr_tracing/ITI/include/iti_pkg.sv @@ -0,0 +1,36 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 20/03/2025 +// Contributors: +// Darshak Sheladiya, SYSGO GmbH +// Umberto Laghi, UNIBO + +// This package is temporary, the idea is to have it directly in the encoder later + +package iti_pkg; + + localparam CAUSE_LEN = 5; //Size is ecause_width_p in the E-Trace SPEC + localparam ITYPE_LEN = 3; //Size is itype_width_p in the E-Trace SPEC (3 or 4) + localparam IRETIRE_LEN = 32; //Size is iretire_width_p in the E-Trace SPEC + + typedef enum logic [ITYPE_LEN-1:0] { + STANDARD = 0, // none of the other named itype codes + EXC = 1, // exception + INT = 2, // interrupt + ERET = 3, // exception or interrupt return + NON_TAKEN_BR = 4, // nontaken branch + TAKEN_BR = 5, // taken branch + UNINF_JMP = 6, // uninferable jump if ITYPE_LEN == 3, otherwise reserved + RES = 7 /*, // reserved + UC = 8, // uninferable call + IC = 9, // inferable call + UIJ = 10, // uninferable jump + IJ = 11, // inferable jump + CRS = 12, // co-routine swap + RET = 13, // return + OUIJ = 14, // other uninferable jump + OIJ = 15*/ // other inferable jump + } itype_t; + +endpackage diff --git a/corev_apu/instr_tracing/ITI/include/iti_types.svh b/corev_apu/instr_tracing/ITI/include/iti_types.svh new file mode 100644 index 00000000000..d8519ee9966 --- /dev/null +++ b/corev_apu/instr_tracing/ITI/include/iti_types.svh @@ -0,0 +1,24 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 20/03/2025 +// Contributors: +// Darshak Sheladiya, SYSGO GmbH +// Umberto Laghi, UNIBO + +`ifndef ITI_TYPES_SVH +`define ITI_TYPES_SVH + +`define ITI_TO_ENCODER_T(Cfg) struct packed { \ + logic [Cfg.NrCommitPorts-1:0] valid; \ + logic [Cfg.NrCommitPorts-1:0][iti_pkg::IRETIRE_LEN-1:0] iretire; \ + logic [Cfg.NrCommitPorts-1:0] ilastsize; \ + iti_pkg::itype_t [Cfg.NrCommitPorts-1:0] itype; \ + logic [iti_pkg::CAUSE_LEN-1:0] cause; \ + logic [Cfg.XLEN-1:0] tval; \ + riscv::priv_lvl_t priv; \ + logic [Cfg.NrCommitPorts-1:0][Cfg.XLEN-1:0] iaddr; \ + logic [63:0] cycles; \ + } + +`endif // ITI_TYPES_SVH diff --git a/corev_apu/instr_tracing/Pictures/Branch_example_dark.svg b/corev_apu/instr_tracing/Pictures/Branch_example_dark.svg new file mode 100644 index 00000000000..eb3a61cea77 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Branch_example_dark.svg @@ -0,0 +1,3 @@ + + +
0000000080001100 <Proc_6>  :
.... ... 
  80001112: c080 {sw s0,0(s1)}
  80001114: 4785 {li a5,1}
  80001116: 02f40463 {beq s0,a5,8000113e }
8000111a:      c81d {beqz s0,80001150 }
> Not Taken ; branches = 1(10)  branche_map = 1(2)
>  Not Taken ; branches = 2(10)  branche_map = 11(2)
 8000111c: 4709 {li a4,2}
 8000111e: 04e40063 {beq s0,a4,8000115e }
> Taken ; branches = 3(10)  branche_map = 011(2)
8000115e: 60e2 {ld ra,24(sp)}
80001160: 6442 {ld s0,16(sp)}
80001162: c09c {sw a5,0(s1)}
80001164: 64a2 {ld s1,8(sp)}
80001166: 6105 {addi sp,sp,32}
80001168: 8082 {ret}
> Uninferable ; packet is sent with : branches = 3(10)  branche_map = 011(2)
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Branch_example_light.svg b/corev_apu/instr_tracing/Pictures/Branch_example_light.svg new file mode 100644 index 00000000000..329d0d46c01 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Branch_example_light.svg @@ -0,0 +1,3 @@ + + +
0000000080001100 <Proc_6>  :
.... ... 
  80001112: c080 {sw s0,0(s1)}
  80001114: 4785 {li a5,1}
  80001116: 02f40463 {beq s0,a5,8000113e }
8000111a:      c81d {beqz s0,80001150 }
> Not Taken ; branches = 1(10)  branche_map = 1(2)
>  Not Taken ; branches = 2(10)  branche_map = 11(2)
 8000111c: 4709 {li a4,2}
 8000111e: 04e40063 {beq s0,a4,8000115e }
> Taken ; branches = 3(10)  branche_map = 011(2)
8000115e: 60e2 {ld ra,24(sp)}
80001160: 6442 {ld s0,16(sp)}
80001162: c09c {sw a5,0(s1)}
80001164: 64a2 {ld s1,8(sp)}
80001166: 6105 {addi sp,sp,32}
80001168: 8082 {ret}
> Uninferable ; packet is sent with : branches = 3(10)  branche_map = 011(2)
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Branch_map_dark.svg b/corev_apu/instr_tracing/Pictures/Branch_map_dark.svg new file mode 100644 index 00000000000..167a10467e0 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Branch_map_dark.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid
empty
Branch
Map
flush
branch_taken
branch_map
branches
full
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Branch_map_light.svg b/corev_apu/instr_tracing/Pictures/Branch_map_light.svg new file mode 100644 index 00000000000..8b440e73cad --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Branch_map_light.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid
empty
Branch
Map
flush
branch_taken
branch_map
branches
full
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/EEPROM.PNG b/corev_apu/instr_tracing/Pictures/EEPROM.PNG new file mode 100644 index 00000000000..5aa90914885 Binary files /dev/null and b/corev_apu/instr_tracing/Pictures/EEPROM.PNG differ diff --git a/corev_apu/instr_tracing/Pictures/Emmiter_dark.svg b/corev_apu/instr_tracing/Pictures/Emmiter_dark.svg new file mode 100644 index 00000000000..06c13f0817d --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Emmiter_dark.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid
packet_valid_o
packet_length_o
Packet
Emmiter
lc_cause
lc_tval
lc_interrupt
tc_cause
tc_tval
tc_interrupt
tc_priv
tc_time
tc_address
branches
branch_map
nc_exc_only
nc_ppccd
tc_ienable
lc_updiscon
packet_payload_o
branch_map_flush
nocontext
notime
qual_status
ioptions
packet_format
packet_subformat
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Emmiter_light.svg b/corev_apu/instr_tracing/Pictures/Emmiter_light.svg new file mode 100644 index 00000000000..987de872161 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Emmiter_light.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid
packet_valid_o
packet_length_o
Packet
Emmiter
lc_cause
lc_tval
lc_interrupt
tc_cause
tc_tval
tc_interrupt
tc_priv
tc_time
tc_address
branches
branch_map
nc_exc_only
nc_ppccd
tc_ienable
lc_updiscon
packet_payload_o
branch_map_flush
nocontext
notime
qual_status
ioptions
packet_format
packet_subformat
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_dark.svg b/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_dark.svg new file mode 100644 index 00000000000..0822cb05b02 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_dark.svg @@ -0,0 +1,3 @@ + + +
Header
Time
Payload
1 Byte
8 Bytes
1    31 Bytes
P_Length
flow
T?
1 bit
2 bits
5 bits
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_light.svg b/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_light.svg new file mode 100644 index 00000000000..fa085eceb7d --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_light.svg @@ -0,0 +1,3 @@ + + +
Header
Time
Payload
1 Byte
8 Bytes
1    31 Bytes
P_Length
flow
T?
1 bit
2 bits
5 bits
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Encoder_dark.svg b/corev_apu/instr_tracing/Pictures/Encoder_dark.svg new file mode 100644 index 00000000000..489d9ddc87c --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Encoder_dark.svg @@ -0,0 +1,3 @@ + + +
Control
Register
Filter
Priority
Resync
Packet
Emmiter
APB
Branch
map
iti_to_encoder 
iretire [N:0][IRET_LEN-1:0];
ilastsize[N:0];
itype [N:0][2:0];
cause [XLEN-1:0];
tval [XLEN-1:0];
priv [1:0];
iaddr [N:0][XLEN-1:0];
cycles [63:0];
valid_i
packet_valid_o
packet_length_o
packet_payload_o
ENCODER
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Encoder_light.svg b/corev_apu/instr_tracing/Pictures/Encoder_light.svg new file mode 100644 index 00000000000..edb997026f9 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Encoder_light.svg @@ -0,0 +1,3 @@ + + +
Control
Register
Filter
Priority
Resync
Packet
Emmiter
APB
Branch
map
iti_to_encoder 
iretire [N:0][IRET_LEN-1:0];
ilastsize[N:0];
itype [N:0][2:0];
cause [XLEN-1:0];
tval [XLEN-1:0];
priv [1:0];
iaddr [N:0][XLEN-1:0];
cycles [63:0];
valid_i
packet_valid_o
packet_length_o
packet_payload_o
ENCODER
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Filter_dark.svg b/corev_apu/instr_tracing/Pictures/Filter_dark.svg new file mode 100644 index 00000000000..db6c3f763e7 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Filter_dark.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid
nc_qualified
Filter
Other 
Events
priv_filter
upper_priv
lower_priv
match_priv
priv_mode
priv_lvl_i
iaddr_filter
upper_iaddr
match_iaddr
iaddr_mode
iaddr_i
lower_iaddr
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Filter_light.svg b/corev_apu/instr_tracing/Pictures/Filter_light.svg new file mode 100644 index 00000000000..2e04cf1a260 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Filter_light.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid
nc_qualified
Filter
Other 
Events
priv_filter
upper_priv
lower_priv
match_priv
priv_mode
priv_lvl_i
iaddr_filter
upper_iaddr
match_iaddr
iaddr_mode
iaddr_i
lower_iaddr
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Gen2_wired.png b/corev_apu/instr_tracing/Pictures/Gen2_wired.png new file mode 100644 index 00000000000..fead93f9fb8 Binary files /dev/null and b/corev_apu/instr_tracing/Pictures/Gen2_wired.png differ diff --git a/corev_apu/instr_tracing/Pictures/ITI_diagram_dark.svg b/corev_apu/instr_tracing/Pictures/ITI_diagram_dark.svg new file mode 100644 index 00000000000..c0d441c0779 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/ITI_diagram_dark.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid_i [N:0]
rvfi_to_iti [N:0] * 
valid_o [N:0]
iti_to_encoder [N:0] * 
ITI
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_dark.svg b/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_dark.svg new file mode 100644 index 00000000000..3c3b1b6e951 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_dark.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid_i [N:0]
rvfi_to_iti 
valid_o [N:0]
iti_to_encoder 
pc [N:0][XLEN-1:0];
op [N:0][7:0];
is_compressed [N:0];
branch_valid [N:0];
is_taken [N:0];
ex_valid ;
tval [XLEN-1:0];
cause [XLEN-1:0];
priv_Ivl [1:0];
cycles [63:0];
iretire[N:0][IRET_LEN-1:0];
ilastsize[N:0];
itype [N:0][2:0];
cause [XLEN-1:0];
tval [XLEN-1:0];
priv [1:0];
iaddr [N:0][XLEN-1:0];
cycles [63:0];
ITI
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_light.svg b/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_light.svg new file mode 100644 index 00000000000..677f5ee1697 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_light.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid_i [N:0]
rvfi_to_iti 
valid_o [N:0]
iti_to_encoder 
pc [N:0][XLEN-1:0];
op [N:0][7:0];
is_compressed [N:0];
branch_valid [N:0];
is_taken [N:0];
ex_valid ;
tval [XLEN-1:0];
cause [XLEN-1:0];
priv_Ivl [1:0];
cycles [63:0];
iretire[N:0][IRET_LEN-1:0];
ilastsize[N:0];
itype [N:0][2:0];
cause [XLEN-1:0];
tval [XLEN-1:0];
priv [1:0];
iaddr [N:0][XLEN-1:0];
cycles [63:0];
ITI
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_dark.svg b/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_dark.svg new file mode 100644 index 00000000000..5e7c938e20e --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_dark.svg @@ -0,0 +1,3 @@ + + +
itype_detector
itype_detector
itype_detector
itype
clk
rst
valid_i [N:0]
rvfi_to_iti [0]
rvfi_to_iti [1]
rvfi_to_iti [N]
valid_o [N:0]
iti_to_encoder [0]
iti_to_encoder [1]
iti_to_encoder [N]
ITI multiple retirement mode (block) 
Block
Retirement
Block
Retirement
Block
Retirement
special
iret
addr
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_light.svg b/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_light.svg new file mode 100644 index 00000000000..a543bf353ff --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_light.svg @@ -0,0 +1,3 @@ + + +
itype_detector
itype_detector
itype_detector
itype
clk
rst
valid_i [N:0]
rvfi_to_iti [0]
rvfi_to_iti [1]
rvfi_to_iti [N]
valid_o [N:0]
iti_to_encoder [0]
iti_to_encoder [1]
iti_to_encoder [N]
ITI multiple retirement mode (block) 
Block
Retirement
Block
Retirement
Block
Retirement
special
iret
addr
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_dark.svg b/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_dark.svg new file mode 100644 index 00000000000..0aca033e7c6 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_dark.svg @@ -0,0 +1,3 @@ + + +
Single 
Retirement
Single 
Retirement
Single 
Retirement
itype_detector
itype_detector
itype_detector
itype
clk
rst
valid_i [N:0]
rvfi_to_iti [0]
rvfi_to_iti [1]
rvfi_to_iti [N]
valid_o [N:0]
iti_to_encoder [0]
iti_to_encoder [1]
iti_to_encoder [N]
ITI single retirement mode 
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_light.svg b/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_light.svg new file mode 100644 index 00000000000..ed16f45d695 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_light.svg @@ -0,0 +1,3 @@ + + +
Single 
Retirement
Single 
Retirement
Single 
Retirement
itype_detector
itype_detector
itype_detector
itype
clk
rst
valid_i [N:0]
rvfi_to_iti [0]
rvfi_to_iti [1]
rvfi_to_iti [N]
valid_o [N:0]
iti_to_encoder [0]
iti_to_encoder [1]
iti_to_encoder [N]
ITI single retirement mode 
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/ITI_diagram_light.svg b/corev_apu/instr_tracing/Pictures/ITI_diagram_light.svg new file mode 100644 index 00000000000..00f0773da34 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/ITI_diagram_light.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid_i [N:0]
rvfi_to_iti [N:0] * 
valid_o [N:0]
iti_to_encoder [N:0] * 
ITI
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/JA_dark.svg b/corev_apu/instr_tracing/Pictures/JA_dark.svg new file mode 100644 index 00000000000..407ef39bf9c --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/JA_dark.svg @@ -0,0 +1,3 @@ + + +
VDD
GND
VDD
GND
rxen
rdn
wrn
txen
oen
clko
spien
siwun
PMOD JA
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/JA_light.svg b/corev_apu/instr_tracing/Pictures/JA_light.svg new file mode 100644 index 00000000000..2242b11d9ab --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/JA_light.svg @@ -0,0 +1,3 @@ + + +
VDD
GND
VDD
GND
rxen
rdn
wrn
txen
oen
clko
spien
siwun
PMOD JA
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/JB_dark.svg b/corev_apu/instr_tracing/Pictures/JB_dark.svg new file mode 100644 index 00000000000..dd322aa9a30 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/JB_dark.svg @@ -0,0 +1,3 @@ + + +
VDD
GND
VDD
GND
d[3]
d[2]
d[7]
d[6]
d[1]
d[0]
d[5]
d[4]
PMOD JB
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/JB_light.svg b/corev_apu/instr_tracing/Pictures/JB_light.svg new file mode 100644 index 00000000000..a58e8ebb938 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/JB_light.svg @@ -0,0 +1,3 @@ + + +
VDD
GND
VDD
GND
d[3]
d[2]
d[7]
d[6]
d[1]
d[0]
d[5]
d[4]
PMOD JB
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Main_tracer_dark.svg b/corev_apu/instr_tracing/Pictures/Main_tracer_dark.svg new file mode 100644 index 00000000000..c5dd8751039 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Main_tracer_dark.svg @@ -0,0 +1,3 @@ + + +
CVA6
RVFI
ITI

TRACER

rvfi_to_iti
iti_to_encoder
ENCODER
TC
0100
1101
DECODER
Encapsulated 
Packets
[Protocol] 
Packets
HARDWARE
SOFTWARE
program binary
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Main_tracer_light.svg b/corev_apu/instr_tracing/Pictures/Main_tracer_light.svg new file mode 100644 index 00000000000..1a4691ae320 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Main_tracer_light.svg @@ -0,0 +1,3 @@ + + +
CVA6
RVFI
ITI

TRACER

rvfi_to_iti
iti_to_encoder
ENCODER
TC
0100
1101
DECODER
Encapsulated 
Packets
[Protocol] 
Packets
HARDWARE
SOFTWARE
program binary
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Priority_dark.svg b/corev_apu/instr_tracing/Pictures/Priority_dark.svg new file mode 100644 index 00000000000..c1d8b7b5879 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Priority_dark.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid_i
valid_o 
packet_format
Priority
lc_exception
lc_updiscon
lc_final_qualified
tc_exception
tc_updiscon
tc_retired
tc_privchange
tc_enc_enabled
tc_enc_disabled
tc_branchmap_empty
tc_branchmap_full
nc_exception
nc_updiscon
nc_retired
nc_privchange
max_resync
tc_first_qualified
tc_qualified
nc_qualified
nc_branchmap_empty
packet_subformat
qual_status
resync_rst
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/Priority_light.svg b/corev_apu/instr_tracing/Pictures/Priority_light.svg new file mode 100644 index 00000000000..d4eae6ec3d8 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/Priority_light.svg @@ -0,0 +1,3 @@ + + +
clk
rst
valid_i
valid_o 
packet_format
Priority
lc_exception
lc_updiscon
lc_final_qualified
tc_exception
tc_updiscon
tc_retired
tc_privchange
tc_enc_enabled
tc_enc_disabled
tc_branchmap_empty
tc_branchmap_full
nc_exception
nc_updiscon
nc_retired
nc_privchange
max_resync
tc_first_qualified
tc_qualified
nc_qualified
nc_branchmap_empty
packet_subformat
qual_status
resync_rst
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/TC_dark.svg b/corev_apu/instr_tracing/Pictures/TC_dark.svg new file mode 100644 index 00000000000..a4e86c2dce6 --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/TC_dark.svg @@ -0,0 +1,3 @@ + + +
SLICER

Transmission Channel

0100
1101
DECODER
Encapsulated 
Packets
DPTI
Frames
HARDWARE
SOFTWARE
RECEIVER
F2232H
USB
Bridge
DPTI
CTRL
ENCAPS
Packet
Slices
Packets
Decapsulated 
Packets
RAW
Packets
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/TC_light.svg b/corev_apu/instr_tracing/Pictures/TC_light.svg new file mode 100644 index 00000000000..6d2bbcaf9bc --- /dev/null +++ b/corev_apu/instr_tracing/Pictures/TC_light.svg @@ -0,0 +1,3 @@ + + +
SLICER

Transmission Channel

0100
1101
DECODER
Encapsulated 
Packets
DPTI
Frames
HARDWARE
SOFTWARE
RECEIVER
F2232H
USB
Bridge
DPTI
CTRL
ENCAPS
Packet
Slices
Packets
Decapsulated 
Packets
RAW
Packets
 \ No newline at end of file diff --git a/corev_apu/instr_tracing/Pictures/decoded_trace.png b/corev_apu/instr_tracing/Pictures/decoded_trace.png new file mode 100644 index 00000000000..3d400c69868 Binary files /dev/null and b/corev_apu/instr_tracing/Pictures/decoded_trace.png differ diff --git a/corev_apu/instr_tracing/Pictures/genesys-2.png b/corev_apu/instr_tracing/Pictures/genesys-2.png new file mode 100644 index 00000000000..8c0db43dba6 Binary files /dev/null and b/corev_apu/instr_tracing/Pictures/genesys-2.png differ diff --git a/corev_apu/instr_tracing/Pictures/genesys2_DPTI.png b/corev_apu/instr_tracing/Pictures/genesys2_DPTI.png new file mode 100644 index 00000000000..81ea39c2c36 Binary files /dev/null and b/corev_apu/instr_tracing/Pictures/genesys2_DPTI.png differ diff --git a/corev_apu/instr_tracing/Pictures/receiver.png b/corev_apu/instr_tracing/Pictures/receiver.png new file mode 100644 index 00000000000..05bfd12d562 Binary files /dev/null and b/corev_apu/instr_tracing/Pictures/receiver.png differ diff --git a/corev_apu/instr_tracing/README.md b/corev_apu/instr_tracing/README.md new file mode 100644 index 00000000000..4e89698f031 --- /dev/null +++ b/corev_apu/instr_tracing/README.md @@ -0,0 +1,721 @@ + + + +# Instruction Tracing + +## Introduction + +Instruction tracing is a crucial feature in modern processor design, particularly when it comes to **certification**, **debugging**, and **formal verification**. It allows engineers to **track the exact sequence of executed instructions**, providing a ground truth that can be compared against expected behavior. + +### Why Instruction Tracing? + +There are several scenarios where instruction tracing is essential: + +* **Certification and Compliance**: In safety-critical systems (e.g., avionics, automotive), it may be necessary to prove that instructions executed **exactly** as specified. +* **Debugging**: When an execution does not behave as expected, a trace can help **reconstruct** the execution flow and understand where and why things went wrong. + +### How Does It Work? + +In this project, we implemented an instruction tracer that uses the **E-TRACE encoding format** (as specified in the [E-Trace specification](https://github.com/riscv-non-isa/riscv-trace-spec)). + + E‑Trace implements a branch‑trace algorithm: it only emits control‑flow "deltas" (branches taken/not‑taken, indirect jumps/calls/returns, interrupts/exceptions) along with PC deltas, assumes sequential instructions implicitly, and can pack multiple retirements into compact packet, achieving a high compression rates while minimizing off‑chip bandwidth and interface complexity. + +There exist other encoding formats such as [N‑Trace](https://github.com/riscv-non-isa/tg-nexus-trace), which is built on the IEEE‑5001 Nexus standard. + +### System Overview + +The tracing system we built is composed of four main elements, illustrated in the block diagram below: + + + + + + + + + +## 1. Instruction Trace Interface (ITI) + +The **Instruction Trace Interface (ITI)** module is implemented in accordance with the [E-Trace specification](https://github.com/riscv-non-isa/riscv-trace-spec) (2025), specifically section 4.2 concerning the Instruction Trace Interface. It sits between the **cva6\_rvfi** (RISC-V Formal Interface) and the **encoder**, and plays a role in collecting and formatting instruction trace data. + +The ITI currently supports **two operating modes**: + +* **Multiple-retirement mode**(`block_mode = 1`): the trace data for several instructions is grouped together and sent to the encoder as a block. +* **Single-retirement mode**(`block_mode = 0`): the trace data are sent to the encoder instructions by instructions. + +At the moment, the ITI only supports the 3-bit itype format (`itype_len = 3`) for classifying instruction types. This is sufficient to distinguish key instruction categories such as branches, uninferable jumps, exceptions, and interrupts. While the E-Trace specification also defines a 4-bit format (`itype_len = 4`) for finer-grained classification, this is not yet implemented in the current design. Support for the 4-bit version could be added later if needed and if compatible with the encoder. + +> For more details about the `itype` field, refer to Table 7 of the [E-Trace specification](https://github.com/riscv-non-isa/riscv-trace-spec), as well as the field description provided just below. + +### Input Interface + + + + + + + +

+The module receives a structured input named **`rvfi_to_iti`**, which encapsulates all the necessary signals to: + +* determine the **instruction type (`itype`)** using fields such as `opcode`, `branch_valid`, etc., +* supply relevant metadata to the encoder like `cycle`, `privilege level`, `pc`, etc. + +Changes were also made to the `cva6_rvfi` module to collect the signals required by the ITI and to properly resynchronize them, since they may originate from different stages of the processor pipeline. This justifies the use of a structured interface to ensure reliable and consistent data transfer to the ITI. + +--- + +### Multiple-Retirement Mode + +In **multiple-retirement mode**, the ITI groups instructions into **blocks**, based on the occurrence of *special* instructions , typically those altering the control flow (e.g., jumps, exceptions, interrupts). + +The ITI outputs the following signals to the encoder in this mode: + +* `iret`: number of half-words for the retired instructions in the current block, +* `iaddr`: address of the first instruction in the block, +* `ilastsize`: size of the last instruction in the block. + +To support this, the ITI adopts a **systolic-like architecture** made up of `block_retirement` submodules. There are `Nr_commit_ports` such submodules, each able to: + +* detect special instructions independently, +* initiate a new block if necessary, +* propagate control and data signals (like `special`, `iaddr`, and incremented `iret`) along a chain. + +This design enables the generation of **multiple blocks in a single cycle** when several special instructions retire simultaneously. + + + + + + + + +--- +### Single-Retirement Mode + +In **single-retirement mode**, the ITI module forwards the trace information **instruction by instruction**, without grouping them into blocks. + +In this configuration: + +* There is no need to track special instructions or segment blocks. +* The encoder receives a simple feed of retired instructions, making this mode well-suited for simpler architectures. + + + + + + + + +--- +### Full System Overview + +The overall role of the ITI module in the trace infrastructure is summarized in the following diagram: + + + + + + +--- +### Continuous Integration for ITI + +The CI (Continuous Integration) test for the ITI is contained in Instr_tracing_test.sh and consist of running a simulation on ariane_testharness with the previous test iti_test.sh and extracting the iti.trace. Then it run the regressionFlow from the [E-Trace specification](https://github.com/riscv-non-isa/riscv-trace-spec) and compare both files. +We cleaned both file to compare what is comparable ,we exclude the start and the end because it's not matching based spike version + + +## 2. Encoder + Encapsulator + +### Collaboration and Reference Design + +For this module, we collaborate with the University of Bologna by integrating their version of the encoder, available +[here](https://github.com/pulp-platform/rv_tracer) + +Their repository is well-documented and serves as a solid foundation. The encoder design is aligned with the **E-Trace specification** and leverages an ITI running in **multiple-retirement mode** to emit **trace packets**. These packets are structured according to the **instruction delta trace algorithm** described in the [E-Trace specification](https://github.com/riscv-non-isa/riscv-trace-spec) (Figure 1), which provides a model for encoding deltas (non-linearities) in the control flow. + +Each data trace outputed by the ITI, whether block-based or instruction-based, is interpreted to identify these deltas and transmit them in the form of trace packets. These packets vary in format and size depending on the instruction type and control flow transitions. + +--- + +### Custom Implementation and Simplification + +While their encoder provides a baseline, it remains under active development. In its current state, its behavior (in terms of number of packets emitted, their contents, or supported options) differs from the Reference Flow. + +As a result, we opted to build a simplified version derived from the original architecture. This internal encoder: + +* Expects **instruction-by-instruction traces** as input, +* Supports only **Nr\_commit\_ports = 1** (single commit port), +* Implements only a **basic subset** of the E-Trace functionality. + +This choice facilitates initial validation and integration, though we remain open to switching back to a mature multiple-retirement encoder once available. + +Below is a high-level architectural diagram of the current encoder setup (here `N=1`): + + + + + + +--- + +### Submodules Description + +The encoder is composed of several key submodules: + +### Submodules Description + +The encoder is composed of several key submodules: + +* **Priority**: + This submodule constitutes the core of the *Instruction Delta Trace Algorithm*. It is responsible for analyzing control flow transitions across instructions and determining the format and/or subformat of trace packets to be emitted. + + + + + + + + The logic is driven by three categories of input signals that represent the state of the instruction stream at different points in time: + - **lc**: *Last Cycle* - information from the previous retired instruction, + - **tc**: *This Cycle* - information from the currently retiring instruction, + - **nc**: *Next Cycle* - information from the next instruction. + + > Some signals are intentionally absent for the sake of understanding + + Using these signals, the `Priority` module identifies the relevant **deltas** (e.g., taken branches, jumps, exceptions) and selects the appropriate **packet format and/or subformat**, which will subsequently guide the `Packet_Emitter`. + +
+ + | Format | Subformat | Description | + | :------: | :-------: | :------------------ | + | 3 | 3 | Support | + | | 2 | Context | + | | 1 | Trap | + | | 0 | Synchronisation | + | 2 | | Address Only | + | 1 | | Branch | + | 0 | | Optional extensions | +
+ + > For more details, refer to [Chapter 7 (Instruction Trace Encoder Output Packet)](https://github.com/riscv-non-isa/riscv-trace-spec) (2025), or consult the corresponding encoder section in the [University of Bologna's implementation](https://github.com/pulp-platform/rv_tracer). + + +* **Packet_Emitter**: + This submodule is responsible for **constructing and filling the trace packet** to be emitted. It plays a central role in materializing the output of the delta trace algorithm into a well-structured packet format compliant with the E-Trace specification. + + + + + + + + Similar to the `Priority` module, it receives multiple input signals that span across different time domains (*lc*,*tc*,*nc*). + + However, the most important **inputs** for this submodule is the **packet format and/or subformat**, which is deteminated by the `Priority` module. This format/subformat dictates the structure and contents of the packet's payload. Also **ppccd** means privilege change, precise context change or context change with discontinuity. + + Based on this, the `Packet_Emitter` output: + - The **payload** which contains all the fields expected for this packet, + - The **packet length** (in bytes), depending on the format/subformat and data, + - A **branch_map_flush** signal that is used to flush the `branch_map` field. This ensures the `branch_map` is ready to accurately track future branches for the next packet. + + > For a complete description of each packet type and its associated payload content, refer to [Chapter 7 (Instruction Trace Encoder Output Packet)](https://github.com/riscv-non-isa/riscv-trace-spec) of the E-Trace specification (2025). + +* **Filter**: + The `Filter` submodule is responsible for **selectively enabling or disabling instruction tracing** (with the qualified signal) based on configurable events defined through **Control Registers**. By filtering out irrelevant or redundant instructions, it can significantly improves trace analysis efficiency and bandwidth usage. + + + + + + + + The filtering mechanism supports a variety of events, including: + + - **Range Address**: Enables tracing **only when the instruction address (`iaddr`) falls within a specified address window**, defined by a `lower_addr` and a `higher_addr` boundary. + - **Stop Event**: Immediately halts instruction tracing when triggered. + - **Selected Privilege Level**: Enables or disables tracing depending on the **current privilege level** (e.g., user, supervisor, machine mode). + - **Other Events**: Filtering can also be triggered by **exceptions**, **interrupts**, or other **context-specific conditions**. + + +* **Branch\_Map**: + The `Branch_Map` submodule acts as a **history buffer** for recently executed branch instructions. It plays a crucial role in the generation of compressed trace packets by allowing the encoder to **reconstruct control-flow paths** through a compact representation. + + + + + + + This module maintains two key outputs: + + - **`branch_map`**: a **bitfield** representing the history of up to 31 conditional branches. For each branch, a **bit is added to the right**: + - `0` if the branch was **taken**, + - `1` if the branch was **not taken**. + + - **`branches`**: an **integer count** of how many branches are currently stored in the map (max: **31**). This counter helps determine the valid width of the `branch_map` field and guides packet formatting/decoding. + + The branch_map is updated as instructions retire. Once the maximum depth is reached or a flush is triggered (e.g., via `branch_map_flush` from the `Packet_Emitter`), the map is cleared to allow tracking of the next sequence. + + Here is an illustrative example, taken from [E-Trace Specification – Chapter 12, Example 4](https://github.com/riscv-non-isa/riscv-trace-spec). + + + + + + + + +--- + +### Encapsulation Module + +This module was developed by the **University of Bologna**, and we reused the `encapsulator.sv` module **as-is**, without any modifications. We chose **not to integrate the other submodules** provided in the original repository, as they are designed for the **ATB (Advanced Trace Bus)** protocol. In our case, we rely on a different trace output interface, named **DPTI (Digilent Parallel Transfer Interface)**, making the use of those ATB-specific modules unnecessary. [Here](https://github.com/pulp-platform/rv_encapsulator) is the repository of the encapsulator from the **University of Bologna**. + +The **encapsulator** is placed directly after the encoder and is responsible for wrapping each trace packet into a **standardized encapsulation format** as defined by the [encapsulation specification](https://github.com/riscv-non-isa/e-trace-encap). + +This format ensures **interoperability**, provides **framing rules**, and facilitates **packet-level synchronization** in the *transmission channel* interface. Each encapsulated packet in this implementation is **fixed at 320 bits (40 bytes)** and includes this field groups: + +- **Header (8 bits)**: + Includes a `length` field (5 bits) specifying the payload size in bytes, a `flow` field (2 bits) which is currently set to `00` (no multi-sink used yet), and an `extend` bit (1 bit) which is set to `1`, indicating the presence of a timestamp (T ? in the figure bellow). + +- **Timestamp (`T * 8` bits)**: + The timestamp is included in our packets and is **fixed at 8 bytes (64 bits)**. Its presence is governed by the `extend` bit in the header. + +- **Payload (1–248 bits)**: + Contains the actual trace packet, emmited by the encoder with `packet_payload_o`. + +An illustration of the encapsulation structure is shown below: + + + + + + +

+ +Once encapsulated, the packets are written into a **FIFO buffer**, where they await transmission through the trace communication channel. + +This design enables modular evolution: improvements or full spec-compliance in the encoder can be adopted later without altering the overall encapsulation and transmission stages. +

+ +> While the [encapsulation specification](https://github.com/riscv-non-isa/e-trace-encap) also defines support for **source IDs** , **null packets** (e.g., `null.idle`, `null.alignment`), and **synchronization sequences**, these features are **not yet implemented** in the current prototype. + +### Continuous Integration for Encoder + Encapsulator + +The CI (Continuous Integration) test for the Encoder and Encapsulator is also contained in Instr_tracing_test.sh and consists in running a simulation on ariane_testharness with the previous test iti_test.sh and extracting the `encoded.trace`, it will convert them in decaspulated csv format with the Decapsuler. Then it runs the regressionFlow from the [E-Trace specification](https://github.com/riscv-non-isa/riscv-trace-spec) and compare both files. +We cleaned both file to compare what is comparable, again we exclude the start and the end because it's not matching based spike version. + + +--- + + +## 3. Transmission Channel (TC) via DPTI + +
+ +

Figure: Digilent Genesys2 development board

+
+ +Picture from [Digilent Reference Manual](digilent.com/reference/programmable-logic/genesys-2/reference-manual) +

+Since most onboard peripherals (UART, SPI, etc.) are already used by the `ariane_xilinx` platform, we use the **FTDI FT2232H**'s DPTI interface exposed on the **USB-JTAG bridge (J17)**: + +
+ +

Figure: USB-JTAG bridge

+
+ +Picture from [Digilent Reference Manual](digilent.com/reference/programmable-logic/genesys-2/reference-manual) + +- **DPTI/DSPI header** on J17 provides: + - A **Digilent Parallel Transfer Interface (DPTI)** channel + - A generic SPI channel (not used here due to limited bandwidth) + +We selected **DPTI** because it is a **mature, out‑of‑the‑box solution** full driver support from Digilent Adept ([Adept Drivers & Utilities](https://digilent.com/reference/software/adept/)). + +--- + +### FT2232H Ports in Genesys 2 + +The FT2232H chip offers two independent channels but in the Top platform `ariane_xilinx` both of them are used : + +| Port | Default Use in `ariane_xilinx`| +|-------|-------------------------------| +| Port A| Bitstream injection | +| Port B| Debug Module interface | + +Because both channels are occupied, we have two deployment options: + +1. **Re-purpose Port B** + - **Disconnect the Debug Module** in `ariane_xilinx.sv`. + - Update `genesys.xdc` to add DPTI pin constraints (e.g., check the [default constraint file](https://github.com/Digilent/digilent-xdc/blob/master/Genesys-2-Master.xdc) section DPTI). + - Inject your program via the on‑chip **bootrom**, modify the Makefile in `corev_apu/fpga/src/bootrom` accordingly. + +2. **Add an FT2232H MiniModule** + - Use a standard [FT2232H Mini Module](https://ftdichip.com/products/ft2232h-mini-module/) connected to two PMOD headers. + - This gives you two **additional** FT2232H channels without touching the existing Port A/B setup. + +
+ +

Figure: FT2232H MiniModule wired to Genesys2 PMODs

+
+

+
+ + + + + + + + + + + +
+

+ +> For more details on the wiring, check these resources: +> - [FT2232H Datasheet](https://ftdichip.com/wp-content/uploads/2024/09/DS_FT2232H.pdf), Table 3.1 +> - [FT2232H Mini Module Datasheet](https://ftdichip.com/wp-content/uploads/2020/07/DS_FT2232H_Mini_Module.pdf), Table 3.1 and Table 3.2 and USB Bus-powered section. + +--- + +### Platform Modifications + + + + + + + + +1. **DPTI Controller** + - Add `dpti_ctrl.vhd` to handle **frame send/receive** over DPTI. This module is provided by Digilent and can be found in the [**Digilent Adept SDK**](https://lp.digilent.com/complete-adept-runtime-download), under `samples/dpti/DptiDemo/logic/dpti_ctrl.vhd`. + - Protocol: **8-bit parallel**, synchronous/asynchronous, running at **60 MHz**, allowing for up to **480 Mbps** throughput. + - The controller requires a clock. It is instantiated in the platform using `xlnx_dpti_clk` located in `cva6/corev_apu/fpga/xilinx/xlnx_dpti_clk`. Alternatively, it can be added to the Vivado project using a Clock Wizard. An example configuration is available in `samples/dpti/DptiDemo/logic/clk_wiz_0.v`. + +2. **Packet Slicer** + - Our trace packets are **320 bits** (40 bytes). + - Insert `slicer_DPTI.sv` to segment each packet into **40 eight‑bit frames** for DPTI transport. + +3. **PMOD Pin Mapping & Constraints** + - PMOD pins used must support external clock (C‑capable). Follow [UG472](https://docs.amd.com/v/u/en-US/ug472_7Series_Clocking) (Vivado) guidelines. + - Example excerpt from `genesys2.xdc`: + ```xdc + ## PMOD Header JA + #set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports prog_clko]; #IO_L13P_T2_MRCC_14 Sch=ja_p[1] + #set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports prog_oen]; #IO_L13N_T2_MRCC_14 Sch=ja_n[1] + #set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports prog_rdn]; #IO_L12P_T1_MRCC_14 Sch=ja_p[2] + #set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports prog_rxen]; #IO_L12N_T1_MRCC_14 Sch=ja_n[2] + #set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports prog_siwun]; #IO_L5P_T0_D06_14 Sch=ja_p[3] + #set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports prog_spien]; #IO_L5N_T0_D07_14 Sch=ja_n[3] // Not needed here + #set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports prog_txen]; #IO_L4P_T0_D04_14 Sch=ja_p[4] + #set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports prog_wrn]; #IO_L4N_T0_D05_14 Sch=ja_n[4] + + ## PMOD Header JB + #set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { prog_d[0] }]; #IO_L17P_T2_A14_D30_14 Sch=jb_p[1] + #set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { prog_d[1] }]; #IO_L17N_T2_A13_D29_14 Sch=jb_n[1] + #set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { prog_d[2] }]; #IO_L18P_T2_A12_D28_14 Sch=jb_p[2] + #set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { prog_d[3] }]; #IO_L18N_T2_A11_D27_14 Sch=jb_n[2] + #set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33 } [get_ports { prog_d[4] }]; #IO_L14P_T2_SRCC_14 Sch=jb_p[3] + #set_property -dict { PACKAGE_PIN U25 IOSTANDARD LVCMOS33 } [get_ports { prog_d[5] }]; #IO_L14N_T2_SRCC_14 Sch=jb_n[3] + #set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { prog_d[6] }]; #IO_L21P_T3_DQS_14 Sch=jb_p[4] + #set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { prog_d[7] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jb_n[4] + ``` + - Ensure **V3V3** pins are tied to **VIO** in the MiniModule. + +4. **FT2232H Configuration** + - Use **FT_Prog** (or equivalent) to set the MiniModule into **USB FIFO mode**. + - ⚠️ Digilent Adept drivers validate a protected EEPROM region not writable via FT_Prog. + - Either use Digilent reprogramming executable + - Or adapt the C++ receiver to be compatible with the FTDI drivers. + +
+ +

Figure: Valid EEPROM for DPTI

+
+ +--- + +### Bitstream Build & Deployment + +Once hardware wiring and constraints are in place with ITI, Encoder, Encapsulator, etc. : +> We used Vivado version: 2018.2 +```bash +make clean +make fpga TARGET=cv32a6_imac_sv32 +``` + +Then upload the generated ariane_xilinx.bit via Vivado Lab or your preferred hardware manager. + +--- +## 4. Software-Side Reception + +The trace reception is handled on a **Linux-based host PC**, which is connected either to the **FTDI MiniModule** or directly to the **Genesys2 board via port J17**. + +To enable communication via **DPTI (Digilent Parallel Trace Interface)**, you must first install the [**Digilent Adept SDK**](https://lp.digilent.com/complete-adept-runtime-download), specifically version `2.4.2`. This provides the required runtime libraries and development headers. The receiver code needs a C++17 version for `std::optional`. + +--- + +### Setup Instructions + +1. **Install Adept SDK** + + * Ensure the Digilent API is installed and correctly configured. + * The official Digilent SDK and documentation provide a guide. + +2. **Configure and Compile the Receiver** + + * The receiver code is located in `Receiver_DPTI.cpp`. + * You must **edit the `Makefile`** to match the paths to the Adept libraries and headers. + + * Refer to the README files in `digilent.adept.sdk_2.4.2/samples` for more informations . + * Then compile the program with: + + ```bash + make clean + make + ``` + +3. **Device Detection and Debugging** + + * The receiver includes debug function, such as `Scan_Device`, which: + + * Lists connected FTDI devices + * Displays their names + +4. **Configure BOARD\_NAME** + + * You must update the `BOARD_NAME` field in `Receiver_DPTI.cpp` to match the actual serial string of your connected device. + * Example: + + ```cpp + char* BOARD_NAME = (char*) "#tpt_0001#ptc_0002#210300075227"; + ``` + * After editing the file, recompile: + + ```bash + make clean + make + ``` + +5. **Running the Receiver** + + * Launch the receiver with: + + ```bash + ./Receiver_DPTI + ``` + * The program proceeds in **two phases**: + + * **Acquisition Phase**: Data is streamed and stored in raw format. Stop the acquisition with `SIGINT` (Ctrl+C). + * **Decapsulation Phase**: The raw binary packets are parsed and converted into human-readable CSV format. + + +
+ +

Figure: Valid execution ./Receiver_DPTI

+
+ +--- + +### Output Files + +Two output files are generated in the `receiver_data/` directory: + +* `YYYYMMDD_hhmm_raw_file.txt` - the raw encapsulated packets +* `YYYYMMDD_hhmm_data.csv` - the decoded content in CSV format + +These CSV files can be supplied to a decoder for further analysis. + +>Currently, no custom decoder is implemented. We use the reference decoder provided in the Reference Flow repository to interpret the trace contents. The University of Bologna released a version of their decoder on 3rd July 2025, but we have not evaluated it yet. + +--- + +## 5. Decoder + +At this stage, we have **not yet implemented** our own decoder. Instead, we rely on the **Reference Flow decoder** provided by the E‑Trace specification. + +#### Running the Reference Flow + +To perform decoding, you first need to run the full reference flow regression so that it can generate the files from the program binary required by its version of Spike(in the `referenceFlow`). In addition, your compiled program must be renamed with a `.riscv` extension so that the flow recognizes it as RISC‑V input and it need to be place in `referenceFlow/tests/test_files`. + +1. **Prepare your binary** + ```bash + cp path/to/your_program.elf referenceFlow/tests/test_files/your_program.riscv + ``` +2. **Execute the full reference flow** +```bash +cd referenceFlow +./scripts/run_regression.sh \ + -t itype3_debug \ + --annotate \ + --debug\ + tests/test_files/your_program.riscv +``` + + * `-t`: Specify the test suite used, here we choose `itype3_debug` to match our encoder and `_debug` to add more information in packets like `full_address mode` + * `--annotate`: This flag is optionnal and using it create annotated version of output files , usefull for understanding/debugging + * `--debug`: This flag is optionnal and using it will print in the terminal more informations about each stage + +### Decoding the Trace +Once the reference flow regression has run successfully (and generated the files needed), you can invoke the decoder step: + +```bash +cd referenceFlow +./scripts/decoder_model.py \ + -u regression_YYYYMMDD_hhmmss/itype3_debug/your_program.decoder.ucf \ + -c regression_YYYYMMDD_hhmmss/itype3_debug/hardware.scf \ + -i TRACE_OUTPUT + +``` + * `-u`: user_config, this file is generated with the first regression, inside there are information about debug flags, object-files, encoder configuration, etc + * `-c`: static_config, this file is also generated but correspond to test suite you choose, inside there are informations about default values (size of fields, encoder options, etc) + * `-i`: This file is the output of the encoder by default :`regression_YYYYMMDD_hhmmss/itype3_debug/your_program.te_inst_raw` but you can use the trace from the receiver, it support CSV format and raw format (needs to be a real binary in this case) + + If everything matches, meaning there are no difference between the captured trace and the reference Trace, you will obtain an output file like this: + +
+ +

Figure: Excerpt from decoded trace

+
+ +

+⚠️ Mismatches can occur if, for example: + +* The platform's address map (CrossBar) doesn't align with your binary's load addresses + +* The encoder fails to emit a packet (e.g., due to a bug in the encoder) + +* There is receiver desynchronization or signal glitches during trace capture + +### Current Limitations & Future Work +When we load the program via the onboard Debug Module, you will notice "trace pollution" : extra instructions corresponding to debug and JTAG activity appear in the trace. One way to mitigate this is to use the Filter submodule in the encoder to suppress unwanted instructions. However: + +**Problem:** We have not yet exposed the APB path needed to drive the Filter's control registers at runtime. + +**Next Steps:** Extend the encoder to include an APB interface for the Filter module, allowing dynamic trace filtering before encapsulation. + + +## 6. Debug Automation & VSCode Setup + +This section presents a set of **automation tools and configurations** developed to streamline the debug process using **Visual Studio Code (VSCode)**. The goal is to make it easy to: + +* **Compile user programs** into a binary format compatible with the **CV32A6** core +* **Launch OpenOCD** using the expected configuration (`ariane.cfg`) +* **Start GDB** in **remote debug mode**, attached to the target via OpenOCD + +--- + +### VSCode Integration + +To integrate these operations directly within the VSCode interface, we make use of two special configuration files: + +* `.vscode/launch.json` - defines how to start a debugging session +* `.vscode/tasks.json` - defines custom build and terminal commands + +With this setup, you can use the built-in **debug pane** of VSCode to: + +* Upload and connect to the board +* Step through code using breakpoints and GDB integration + +These files must be placed inside a `.vscode/` directory at the root of the project. + +--- + +### File Overview + +**launch.json** + +```json +{ + "version": "0.2.0", + "configurations": [ + { + "name": "Debug FPGA via OpenOCD", + "type": "cppdbg", + "targetArchitecture": "x86_64", + "request": "launch", + "program": "${workspaceFolder}/Prog_compiled", + "miDebuggerServerAddress": "localhost:3333", + "useExtendedRemote": true, + "miDebuggerPath": "toolchain/bin/riscv-none-elf-gdb", + "stopAtEntry": true, + "stopAtConnect": true, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "preLaunchTask": "build-and-start-openocd", + "postRemoteConnectCommands": [ + { + "text": "source ${workspaceFolder}/gdb_init.txt" + } + ] + } + ] + } +``` + +**tasks.json** + +```json +{ + "version": "2.0.0", + "tasks": [ + + { + "label": "build-exec", + "type": "shell", + "command": "riscv-none-elf-gcc", + "args": [ + "-g", "-T", "custom_linker.ld", + "-march=rv32imac_zicsr", + "-lgcc", "-fvisibility=hidden", + "-mcmodel=medany", "-mabi=ilp32", + "-nostartfiles", "crt.S", "syscalls.c", "test.c", + "-o", "Prog_compiled" + ], + "problemMatcher": [], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "start openocd", + "type": "shell", + "command": "bash", + "args": [ + "-c", + "nohup gnome-terminal -- bash -c \"openocd -f ariane.cfg; exec bash\"" + ], + "problemMatcher": [] + }, + { + "label": "build-and-start-openocd", + "dependsOn": ["build-exec", "start openocd"] + } + ] + } + + +``` + +These configurations are adaptable to your own build system or directory structure. + +--- + +### Additional Resources + +* [VSCode Debugging Documentation](https://code.visualstudio.com/docs/debugtest/debugging) +* [VSCode Task Configuration](https://code.visualstudio.com/docs/debugtest/tasks) diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile b/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile new file mode 100644 index 00000000000..50517ba22eb --- /dev/null +++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile @@ -0,0 +1,30 @@ +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales + +# Makefile to build the receiver executable +# You need to properly install Digilent Adept and correctly link adept sdk lib +CC = g++ +INC ?= $(HOME)/runtime_adept/digilent.adept.sdk_2.4.2 +LIBDIR = /usr/lib64/digilent/adept +TARGETS = Receiver_DPTI +CFLAGS = -I $(INC) -L $(LIBDIR) -ldpti -ldmgr -Wall -Wextra -g + +all: $(TARGETS) + +Receiver_DPTI: Receiver_DPTI.cpp + $(CC) -o Receiver_DPTI Receiver_DPTI.cpp $(CFLAGS) + +.PHONY: clean + +clean: + rm -f $(TARGETS) + +clean_all: + rm -f $(TARGETS) + rm -rf receiver_data diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp b/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp new file mode 100644 index 00000000000..51290d38d6c --- /dev/null +++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp @@ -0,0 +1,455 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 17/06/2025 +// Contributors: +// Côme Allart - Thales + +// This code is designed to receive encapsulated packets emitted by an instruction encoder (See e-trace-encap). +// It captures them in two formats: raw and decapsulated (.csv). +// These files can then be passed to a decoder (e.g., riscv-trace-spec/referenceFlow/scripts/decoder_model.py). + +// To properly use this receiver, you need a Digilent FPGA board using the DPTI module from the Adept SDK. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dpcdecl.h" +#include "dmgr.h" +#include "dpti.h" + +volatile sig_atomic_t stop = 0; + +void handle_sigint(int) { stop = 1; } + +const size_t NR_PKT = 20; +const size_t PACKET_SIZE = 40; +const size_t BLOCK_SIZE = NR_PKT * PACKET_SIZE; + +typedef BYTE packet_t[PACKET_SIZE]; +typedef std::array sample_t; + +uint64_t extract_bits(const packet_t &packet, std::size_t bit_offset, + std::size_t bit_length) { // FIXME add assertion to prevent desynchro segfault + uint64_t result = 0xdead; // We use 'dead' as an indicator to quickly detect if a desynchro happened during the aquisition (without stoping decapsulation) + if (bit_length <= 64) { + result = 0; + for (std::size_t i = 0; i < bit_length; ++i) { + std::size_t global_bit = bit_offset + i; + std::size_t byte_index = global_bit / 8; + std::size_t bit_index = 7 - (global_bit % 8); + uint64_t bit = (packet[byte_index] >> bit_index) & 0x1; + result = (result << 1) | bit; + } + } + return result; +} + +template struct PrintableOption : public std::optional { + PrintableOption(std::optional &o) : std::optional(o) {} + PrintableOption(T &v) : std::optional(v) {} + PrintableOption(uint64_t v) : std::optional(v) {} + PrintableOption() : std::optional() {} + + friend std::ostream &operator<<(std::ostream &s, const PrintableOption &o) { + if (o.has_value()) + s << unsigned(*o); + else + s << "_"; + + return s; + } +}; + +struct BitExtractor { + const packet_t &packet; + bool is_backward; + size_t i; + + BitExtractor(const packet_t &packet, bool backward) + : packet(packet), is_backward(backward), + i(backward ? PACKET_SIZE * 8 : 0) {} + + uint64_t operator()(size_t bits) { return extract(bits); } + uint64_t to(size_t bit) { return extract_to(bit); } + + uint64_t extract_to(size_t bit) { return extract(i - bit); } + uint64_t extract(size_t bits) { + if (is_backward) + i -= bits; + + uint64_t result = extract_bits(packet, i, bits); + + if (!is_backward) + i += bits; + + return result; + } +}; + +struct Trace { + bool P_Time; // MSB + uint8_t P_ID; // 2 bits after MSB + uint8_t P_Size; // 5bits after P_ID + uint64_t P_Timestamp; // 64 bits after P_Size + PrintableOption format; // 2bits LSB + PrintableOption subformat; // 2bits before LSB if format=3 + PrintableOption address; // start of payload + PrintableOption branch; // F3SF0 (5) F3SF1 (5) else NDF + PrintableOption branches; // F1 (3) + PrintableOption branch_map; // F1 (4 : branches) + PrintableOption branch_count; // NDF + PrintableOption branch_fmt; // NDF + PrintableOption context; // NDF + PrintableOption ecause; //F3SF1 (8) F3SF1T (70) + PrintableOption ienable; //F3SF3 (5) + PrintableOption encoder_mode;//F3SF3 (6) + PrintableOption interrupt; // F3SF1(9) F3SF1T(71) + PrintableOption irreport; // F2 (5) F1(5) + PrintableOption irdepth; //if call/ret F2(6:2^cal) F1(6:2^cal) else NDF + PrintableOption notify; // F2(3) F1(3) + PrintableOption ioptions; //F3SF3 (8:15) + PrintableOption privilege; // F3SF0 (6) F3SF1 (6) F3SF2 (5) + PrintableOption qual_status;// F3SF3(7) + PrintableOption time; //if time F3SF0(8:72) F3SF1(8:72) F3SF2(7:71) //FIXME encoder could have time in last position + PrintableOption thaddr; // F3SF1(40) F3SF1_t(104) + PrintableOption tval; //F3SF1 (41:73) F3SF1_t(105:137) + PrintableOption updiscon;// F2(4) + PrintableOption denable;// NDF here + PrintableOption dloss;// NDF here + PrintableOption doptions;// NDF here + uint8_t size_branch_map; + + Trace(const packet_t &packet, bool time_flag, bool call_flag) { + size_branch_map = 0; + + BitExtractor header_extractor(packet, false); + BitExtractor payload_extractor(packet, true); + + // Header of encapsulated packet : + P_Time = header_extractor(1); + P_ID = header_extractor(2); + P_Size = header_extractor(5); + size_t P_Start = (PACKET_SIZE - P_Size) * 8; + P_Timestamp = header_extractor(64); + + // Extraction of fields contained in the payload : + format = payload_extractor(2); + if (format == 3) { + subformat = payload_extractor(2); + } + + if (format == 3 && subformat.has_value()) { + switch (subformat.value()) { + case 0: { // F3SF0 + branch = payload_extractor(1); + privilege = payload_extractor(2); + if (time_flag) { + time = payload_extractor(64); + } + address = payload_extractor.to(P_Start); + break; + } + case 1: { // F3SF1 + branch = payload_extractor(1); + privilege = payload_extractor(2); + if (time_flag) { + time = payload_extractor(64); + } + ecause = payload_extractor(32); + interrupt = payload_extractor(1); + thaddr = payload_extractor(1); + tval = payload_extractor(32); + address = payload_extractor.to(P_Start); + break; + } + case 2: { // F3SF2 + privilege = payload_extractor(2); + if (time_flag) { + time = payload_extractor(64); + } + break; + } + case 3: { // F3SF3 + ienable = payload_extractor(1); + encoder_mode = payload_extractor(1); + qual_status = payload_extractor(2); + ioptions = payload_extractor(7); + break; + } + } + } + + // F2 + if (format == 2) { + notify = payload_extractor(1); + updiscon = payload_extractor(1); + irreport = payload_extractor(1); + if (call_flag) { // FIXME addapt to call_counter_size + irdepth = payload_extractor(1); // if = 0 else 2^call_counter_size + } + address = payload_extractor.to(P_Start); + } + + // F1 + if (format == 1) { + branches = payload_extractor(5); + if(branches==0) { + size_branch_map = 31; + } else if (branches == 1) { + size_branch_map = 1; + } else if (branches <= 3) { + size_branch_map = 3; + } else if (branches <= 7) { + size_branch_map = 7; + } else if (branches <= 15) { + size_branch_map = 15; + } else { + size_branch_map = 31; + } + + branch_map = payload_extractor(size_branch_map); + + if (branches != 0) { + notify = payload_extractor(1); + updiscon = payload_extractor(1); + irreport = payload_extractor(1); + if (call_flag) { // FIXME addapt to call_counter_size + irdepth = payload_extractor(1); // if = 0 else 2^call_counter_size + } + address = payload_extractor.to(P_Start); + } + } + } + + static std::string csvHeader() { + return std::string( + "format,subformat,address,branch,branches,branch_map,branch_count," + "branch_fmt,context,ecause,ienable,encoder_mode,interrupt,irreport," + "irdepth,notify,ioptions,privilege,qual_status,time,thaddr,tval," + "updiscon,denable,dloss,doptions"); + } + + friend std::ostream &operator<<(std::ostream &s, Trace const &trace) { + trace.put_str(s); + return s; + } + + std::ostream &put_str(std::ostream &s) const { + s << format << "," << subformat << ","; + + s << std::hex << std::nouppercase << address << std::dec << ","; + + s << branch << "," << branches << "," << branch_map << "," << branch_count + << "," << branch_fmt << ","; + + s << context << "," << ecause << "," << ienable << "," << encoder_mode + << "," << interrupt << ","; + + s << irreport << "," << irdepth << "," << notify << "," << ioptions << "," + << privilege << "," << qual_status << ","; + + s << std::hex << std::nouppercase << time << std::dec << ","; + + s << thaddr << "," << tval << "," << updiscon << "," << denable << "," + << dloss << "," << doptions ; + + return s; + } + + std::string toCSVLine() { + std::ostringstream oss; + oss << *this; + return oss.str(); + } +}; + +std::string getTime () { + auto now = std::chrono::system_clock::now(); + std::time_t t = std::chrono::system_clock::to_time_t(now); + std::tm tm = *std::localtime(&t); + std::ostringstream ts; + ts << std::put_time(&tm, "%Y%m%d_%H%M"); + std::string timestamp = ts.str(); + + return timestamp; +} + +void Scan_Device (){ + int indexmax; + DmgrEnumDevices(&indexmax); + std::cout << indexmax < transaction_DPTI(uint32_t peripheral_handle) { + bool Transaction; + int error; + auto sample_ptr = std::make_unique(); + Transaction = DptiIO(peripheral_handle, NULL, 0, (BYTE *) sample_ptr.get(), BLOCK_SIZE, false); + + if (!Transaction) { + error = DmgrGetLastError(); + if (error == ercTransferCancelled) { + throw std::runtime_error("data transfer timed out"); + } else { + throw std::runtime_error("data transfer failed code : " + std::to_string(error)); + } + } + return sample_ptr; +} + +int main() { + // Change this field according to your board / encoder + char *BOARD_NAME = (char*)"#tpt_0001#ptc_0002#210300075227"; + const int32_t PORT = 1; // 0 or 1 + const bool TIME_FLAG = 1; + const bool CALL_FLAG = 0; + + uint32_t peripheral_handle; + peripheral_handle = hifInvalid; + size_t counter = 0; + std::vector> all_data; + //Scan_Device(); + const std::string out_dir = "receiver_data"; + + if (!std::filesystem::exists(out_dir)) { + std::filesystem::create_directory(out_dir); + } + + std::string timestamp= getTime(); + + // File paths + std::string raw_path = out_dir + "/" + timestamp + "_raw_file.txt"; + std::string csv_path = out_dir + "/" + timestamp + "_data.csv"; + + std::ofstream raw_file(raw_path); + std::ofstream csvFile(csv_path); + + + + // Initialisation of the DPTI Channel + try { + peripheral_handle = init_DPTI(BOARD_NAME, PORT); + } catch (const std::exception &e) { + if (peripheral_handle != hifInvalid) { + DptiDisable(peripheral_handle); + DmgrClose(peripheral_handle); + } + std::cerr << "ERROR Init : " << e.what() << std::endl; + return 1; + } + + + // Capture loop + signal(SIGINT, handle_sigint); + std::cout << "\nLoop (Ctrl+C to exit)\n\n"; + auto capture_start = std::chrono::high_resolution_clock::now(); + while (!stop) { + try { + auto sample_ptr = transaction_DPTI(peripheral_handle); + all_data.push_back(std::move(sample_ptr)); + + std::cout << "\rIteration : " << counter << " " << std::flush; + counter += NR_PKT; + } catch (const std::exception &e) { + std::cerr << "ERROR Transaction : " << e.what() << std::endl; + break; + } + } + auto capture_end = std::chrono::high_resolution_clock::now(); + + std::chrono::duration capture_delta_time = + capture_end - capture_start; + double capture_delta_time_sec = capture_delta_time.count(); + double throughput = (counter * PACKET_SIZE * 8) / capture_delta_time_sec; + if (throughput < 1e6) { + std::cout << "\n\nThroughput : " << std::fixed << std::setprecision(2) + << throughput / 1e3 << " Kb/s"; + } else { + std::cout << "\n\nThroughput : " << std::fixed << std::setprecision(2) + << throughput / 1e6 << " Mb/s"; + } + std::cout << "\t\tCapturing took :" << capture_delta_time_sec << "s\n"; + + // Writing output : Raw / Decapsulated csv + auto write_start = std::chrono::high_resolution_clock::now(); + if (csvFile.is_open() && raw_file.is_open()) { + csvFile << Trace::csvHeader() << "\n"; + for (const auto &sample_ptr : all_data) { + for (const packet_t &packet : *sample_ptr) { + Trace trace(packet, TIME_FLAG, CALL_FLAG); + csvFile << trace.toCSVLine() << "\n"; + for (size_t k = 0; k < PACKET_SIZE; ++k) { + raw_file << std::uppercase << std::hex << std::setw(2) + << std::setfill('0') << (unsigned)packet[k]; + } + raw_file << "\n"; + } + } + std::cout + << "\n========================SUCCESS_WRITE========================\n"; + } + auto write_end = std::chrono::high_resolution_clock::now(); + std::chrono::duration write_delta_time = write_end - write_start; + double write_delta_time_sec = write_delta_time.count(); + std::cout << "\nWriting Took : " << write_delta_time_sec << "s\n"; + + auto raw_size = std::filesystem::file_size(raw_path); + auto csv_size = std::filesystem::file_size(csv_path); + std::cout << "\nRaw file size: " << raw_size / 1e6 << " Mbytes\t"; + std::cout << "CSV file size: " << csv_size / 1e6 << " Mbytes\n"; + + DptiDisable(peripheral_handle); + DmgrClose(peripheral_handle); + + std::cout + << "\n========================SUCCESS_CLOSE========================\n\n"; + + return 0; +} \ No newline at end of file diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh b/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh new file mode 100644 index 00000000000..0bbd3ed3163 --- /dev/null +++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh @@ -0,0 +1,34 @@ +#!/usr/bin/env bash +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales +# THis script remove lines above the start packet 3.3 + +if [ $# -ne 1 ]; then + echo "Usage!: $0 file/to/clean.csv" + exit 1 +fi +# This script will clean the csv trace by starting the trace at the first packet after reset +input_file="$1" +output_file="${input_file%.csv}_cleaned.csv" +temp_file=$(mktemp) + +awk 'found || /^3,3,_,_,/ {found=1; print}' "$input_file" > "$temp_file" + +{ + printf "format,subformat,address,branch,branches,branch_map,branch_count," + printf "branch_fmt,context,ecause,ienable,encoder_mode,interrupt,irreport," + printf "irdepth,notify,ioptions,privilege,qual_status,time,thaddr,tval," + printf "updiscon,denable,dloss,doptions\n" + + cat "$temp_file" +} > "$output_file" + +rm "$temp_file" + +echo "File Cleaned : $output_file" \ No newline at end of file diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh b/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh new file mode 100644 index 00000000000..68355bf8834 --- /dev/null +++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh @@ -0,0 +1,39 @@ +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales + +#Script to automate the aquisition process for the receiver + +NR_PKTS=(1 2 10 20 50 100 200) +DURATION=5 + +LOG_FILE="log_$(date +'%Y%m%d_%H%M%S').txt" +echo "Fichier de log : $LOG_FILE" + +echo -e "NR_PKT\tThroughput (Mb/s)" > "$LOG_FILE" + +capture_fct() { + ./Receiver_DPTI & + PID=$! + sleep "$DURATION" + kill -SIGINT "$PID" + sleep 2 +} + +for i in "${NR_PKTS[@]}"; do + echo "=== NR_PKT = $i ===" + sed -i "s/const int NR_PKT = [0-9]\+;/const int NR_PKT = $i;/" Receiver_DPTI.cpp + make > /dev/null || { echo "Compilation échouée à $i"; exit 1; } + + OUTPUT=$(capture_fct | grep -oP 'Throughput\s*:\s*\K[0-9.]+' ) + echo "$i : $OUTPUT" | tee -a "$LOG_FILE" + +done + +python3 script.py "$LOG_FILE" + diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py b/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py new file mode 100644 index 00000000000..2b3f1ef61e0 --- /dev/null +++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py @@ -0,0 +1,59 @@ +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales + +#Script to plot data from run_timeout.sh aquisition with receiver + +import sys +import matplotlib.pyplot as plt + +def parse_log(file_path): + nr_pkts = [] + throughputs = [] + with open(file_path) as f: + for line in f: + line = line.strip() + if not line or ':' not in line or line.startswith('NR_PKT'): + continue + try: + pkt_str, tp_str = line.split(':') + pkt = int(pkt_str.strip()) + tp = float(tp_str.strip()) + nr_pkts.append(pkt) + throughputs.append(tp) + except ValueError: + continue + return nr_pkts, throughputs + +def main(): + if len(sys.argv) != 2: + print(f"Usage: {sys.argv[0]} ") + sys.exit(1) + + log_file = sys.argv[1] + nr_pkts, throughputs = parse_log(log_file) + + if not nr_pkts: + print("Aucune donnée valide trouvée dans le fichier.") + sys.exit(1) + + print("\nNR_PKT\tThroughput (Mb/s)") + for pkt, tp in zip(nr_pkts, throughputs): + print(f"{pkt}\t{tp}") + + plt.figure() + plt.plot(nr_pkts, throughputs, marker='o') + plt.xlabel("Nombre de paquets (NR_PKT)") + plt.ylabel("Throughput (Mb/s)") + plt.title("NR_PKT vs Throughput") + plt.grid(True) + plt.tight_layout() + plt.show() + +if __name__ == "__main__": + main() diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh b/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh new file mode 100644 index 00000000000..3dcaa82005e --- /dev/null +++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh @@ -0,0 +1,27 @@ +#!/usr/bin/env bash +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales +capture_fct() { + ./Receiver_DPTI & + PID=$! + sleep 5 + kill -SIGINT "$PID" + sleep 2 +} + +NR_PKTS=(10 20 50 100 200) + +for i in "${NR_PKTS[@]}"; do + echo "=== $i ===" + + sed -i "s/const int NR_PKT = [0-9]\+;/const int NR_PKT = $i;/" Receiver_DPTI.cpp + make -s + capture_fct >> log2.txt + +done diff --git a/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE b/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE new file mode 100644 index 00000000000..3931d9e54f8 --- /dev/null +++ b/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE @@ -0,0 +1,176 @@ +SOLDERPAD HARDWARE LICENSE version 0.51 + +This license is based closely on the Apache License Version 2.0, but is not +approved or endorsed by the Apache Foundation. A copy of the non-modified +Apache License 2.0 can be found at http://www.apache.org/licenses/LICENSE-2.0. + +As this license is not currently OSI or FSF approved, the Licensor permits any +Work licensed under this License, at the option of the Licensee, to be treated +as licensed under the Apache License Version 2.0 (which is so approved). + +This License is licensed under the terms of this License and in particular +clause 7 below (Disclaimer of Warranties) applies in relation to its use. + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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While redistributing the Work or +Derivative Works thereof, You may choose to offer, and charge a fee for, +acceptance of support, warranty, indemnity, or other liability obligations +and/or rights consistent with this License. However, in accepting such +obligations, You may act only on Your own behalf and on Your sole +responsibility, not on behalf of any other Contributor, and only if You agree +to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_encapsulator-main/README.md b/corev_apu/instr_tracing/rv_encapsulator-main/README.md new file mode 100644 index 00000000000..66687223759 --- /dev/null +++ b/corev_apu/instr_tracing/rv_encapsulator-main/README.md @@ -0,0 +1,2 @@ +The encapsulator is a modified version of https://github.com/pulp-platform/rv_encapsulator +This directory (`rv_encapsulator-main`) is temporary and will soon be replaced by a submodule. \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv b/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv new file mode 100644 index 00000000000..32af59527f2 --- /dev/null +++ b/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv @@ -0,0 +1,50 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +/* +all the type associated params are commented because the type is not required for trace encoders +supporting only instruction tracing +*/ + +package encap_pkg; + + localparam H_LEN = 8; // header length + //localparam SRCID_LEN = 7; // not used because only one source in system + //localparam TYPE_LEN = 8; + localparam PAYLOAD_LEN = 248 /*- TYPE_LEN - (SRCID_LEN % 8)*/; // trace_payload_len + localparam T_LEN = 64; // timestamp length: mcycle length is always 64 + localparam FLOW_LEN = 2; + localparam P_LEN = 5; + localparam MAX_LEN = 264; // max length for payload to slice + + typedef struct packed { + logic extend; + logic [FLOW_LEN-1:0] flow; + logic [P_LEN-1:0] length; + } header_s; + + typedef struct packed { + //logic [TYPE_LEN-1:0] type; // omitted because only instruction trace available + logic [PAYLOAD_LEN-1:0] trace_payload; + } payload_s; + + typedef struct packed { + header_s header; + //logic [SRCID_LEN-1:0] srcid; + logic [T_LEN-1:0] timestamp; + payload_s payload; + } encap_fifo_entry_s; + +endpackage \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv b/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv new file mode 100644 index 00000000000..e93c8ba864f --- /dev/null +++ b/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv @@ -0,0 +1,75 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +/* ENCAPSULATOR */ +/* +this module generates the header and payload necessary based on the protocol used +*/ + +module encapsulator ( + // inputs + input logic clk_i, + input logic valid_i, + input logic [encap_pkg::P_LEN-1:0] packet_length_i, + input logic [encap_pkg::FLOW_LEN-1:0] flow_i, + input logic timestamp_present_i, + //input logic srcid_i, + input logic [encap_pkg::T_LEN-1:0] timestamp_i, + //input logic [encap_pkg::TYPE_LEN-1:0] type_i, + input logic [encap_pkg::PAYLOAD_LEN-1:0] trace_payload_i, + + // outputs + output logic valid_o, + output encap_pkg::encap_fifo_entry_s encap_fifo_entry_o +); + // pragma translate_off + int f; + initial begin + f = $fopen("encaps.traces", "w"); + end + final $fclose(f); + // pragma translate_on + +always_comb begin + // initialization + valid_o = '0; + encap_fifo_entry_o = '0; + + // assignments + if (valid_i) begin + valid_o = '1; + // header + encap_fifo_entry_o.header.length = packet_length_i; + encap_fifo_entry_o.header.flow = flow_i; + encap_fifo_entry_o.header.extend = timestamp_present_i; + // srcID + //encap_fifo_entry_o.srcid = srcid_i; + // timestamp + encap_fifo_entry_o.timestamp = timestamp_i; + // payload + encap_fifo_entry_o.payload.trace_payload = trace_payload_i; + end +end +// pragma translate_off +always_ff @(posedge clk_i) begin + if (valid_o) begin + $fwrite( + f, + "%h\n",encap_fifo_entry_o); + end +end +// pragma translate_on + +endmodule \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_tracer-main/LICENSE b/corev_apu/instr_tracing/rv_tracer-main/LICENSE new file mode 100644 index 00000000000..3931d9e54f8 --- /dev/null +++ b/corev_apu/instr_tracing/rv_tracer-main/LICENSE @@ -0,0 +1,176 @@ +SOLDERPAD HARDWARE LICENSE version 0.51 + +This license is based closely on the Apache License Version 2.0, but is not +approved or endorsed by the Apache Foundation. A copy of the non-modified +Apache License 2.0 can be found at http://www.apache.org/licenses/LICENSE-2.0. + +As this license is not currently OSI or FSF approved, the Licensor permits any +Work licensed under this License, at the option of the Licensee, to be treated +as licensed under the Apache License Version 2.0 (which is so approved). + +This License is licensed under the terms of this License and in particular +clause 7 below (Disclaimer of Warranties) applies in relation to its use. + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +// uncomment to enable 64bits arch support +// `define TE_ARCH64 + +package te_pkg; + localparam PRIV_LEN = 2; // depends on CPU implementation + localparam INST_LEN = 32; + localparam PTYPE_LEN = 4; // is it F + SF? spec not clear + localparam P_LEN = 5; + localparam PAYLOAD_LEN = 248; + localparam TRIGGER_LEN = 4; + localparam CTYPE_LEN = 2; +`ifdef TE_ARCH64 // 64bit arch specific parameters + localparam XLEN = 64; + // APB addresses to access registers + // the value is added to the peripheral address + /* FILTER */ + // cause + localparam CAUSE_UPPER = 8'h5; + localparam CAUSE_LOWER = 8'h6; + localparam CAUSE_MATCH = 8'h7; + // tvec + localparam TVEC_UPPER_L = 8'h8; // least significant bits + localparam TVEC_UPPER_M = 8'h9; // most significant bits + localparam TVEC_LOWER_L = 8'ha; // least significant bits + localparam TVEC_LOWER_M = 8'hb; // most significant bits + localparam TVEC_MATCH_L = 8'hc; // least significant bits + localparam TVEC_MATCH_M = 8'hd; // most significant bits + // tval + localparam TVAL_UPPER_L = 8'he; // least significant bits + localparam TVAL_UPPER_M = 8'hf; // most significant bits + localparam TVAL_LOWER_L = 8'h10; // least significant bits + localparam TVAL_LOWER_M = 8'h11; // most significant bits + localparam TVAL_MATCH_L = 8'h12; // least significant bits + localparam TVAL_MATCH_M = 8'h13; // most significant bits + // iaddr + localparam IADDR_UPPER_L = 8'h16; // least significant bits + localparam IADDR_UPPER_M = 8'h17; // most significant bits + localparam IADDR_LOWER_L = 8'h18; // least significant bits + localparam IADDR_LOWER_M = 8'h19; // most significant bits + localparam IADDR_MATCH_L = 8'h1a; // least significant bits + localparam IADDR_MATCH_M = 8'h1b; // most significant bits +`else // 32bit arch + localparam XLEN = 32; + // APB addresses to access registers + // APB addresses to access registers + // the value is added to the peripheral address + /* FILTER */ + // cause + localparam CAUSE_UPPER = 8'h5; + localparam CAUSE_LOWER = 8'h6; + localparam CAUSE_MATCH = 8'h7; + // tvec + localparam TVEC_UPPER = 8'h8; + localparam TVEC_LOWER = 8'ha; + localparam TVEC_MATCH = 8'hc; + // tval + localparam TVAL_UPPER = 8'he; + localparam TVAL_LOWER = 8'h10; + localparam TVAL_MATCH = 8'h12; + // iaddr + localparam IADDR_UPPER = 8'h16; + localparam IADDR_LOWER = 8'h18; + localparam IADDR_MATCH = 8'h1a; +`endif + /* both archs parameters */ + // localparams for resync counter + localparam CYCLE_MODE = 0; + localparam PACKET_MODE = 1; + // localparams for irreport and irdepth + localparam CALL_COUNTER_SIZE = '0; + localparam RETURN_STACK_SIZE = '0; + // localparams for branch map - defined by spec + localparam BRANCH_MAP_LEN = 31; + localparam BRANCH_COUNT_LEN = 5; + // localparams for filter mode + localparam RANGE_MODE = 1'b0; + localparam EQUAL_MODE = 1'b1; + // localparam for time signal + localparam TIME_LEN = 64; + // localparam for itype + localparam ITYPE_LEN = 3; + // localparam for iretire + localparam IRETIRE_LEN = 32; + + // common APB addresses to access registers + /* FILTER */ + // input and mode + localparam CAUSE_ENABLE_MODE = 8'h0; + localparam TVEC_ENABLE_MODE = 8'h1; + localparam TVAL_ENABLE_MODE = 8'h2; + localparam PRIV_ENABLE_MODE = 8'h3; + localparam IADDR_ENABLE_MODE = 8'h4; + // priv + localparam PRIV_RANGE = 8'h14; + localparam PRIV_MATCH = 8'h15; + /* TRACE MANAGEMENT */ + localparam TRACE_STATE = 8'h1c; + localparam LOSSLESS_TRACE = 8'h1d; + localparam SHALLOW_TRACE = 8'h1e; + /* PACKET EMITTER */ + localparam NO_TIME = 8'h1f; + localparam NO_CONTEXT = 8'h20; + localparam DELTA_ADDRESS = 8'h21; + localparam FULL_ADDRESS = 8'h22; + localparam IMPLICIT_EXCEPTION = 8'h23; + localparam SIJUMP = 8'h24; + localparam IMPLICIT_RETURN = 8'h25; + localparam BRANCH_PREDICTION = 8'h26; + localparam JUMP_TARGET_CACHE = 8'h27; + +// packet types +typedef enum logic[1:0] { + F_OPT_EXT = 2'h0, + F_DIFF_DELTA = 2'h1, + F_ADDR_ONLY = 2'h2, + F_SYNC = 2'h3 +} format_e; + +// subformats available for type 3 packets (F_SYNC) +typedef enum logic[1:0] { + SF_START = 2'h0, + SF_TRAP = 2'h1, + SF_CONTEXT = 2'h2, + SF_SUPPORT = 2'h3 +} f_sync_subformat_e; + +// subformats available for type 0 packets (F_OPT_EXT) +// used a struct for future extensions +typedef enum logic[0:0] { + SF_PBC = 1'h0, // correctly predicted branches + SF_JTC = 1'h1 // jump target cache in spec +} f_opt_ext_subformat_e; + +// qual_status values necessary for format 3 subformat 3 +// packet payload +typedef enum logic[1:0] { + NO_CHANGE = 2'h0, + ENDED_REP = 2'h1, + TRACE_LOST = 2'h2, + ENDED_NTR = 2'h3 +} qual_status_e; + +// struct to determine the ioptions enabled/disabled +// for format 3 subformat 3 packets +typedef struct packed { + logic delta_address_en; + logic full_address_en; + logic implicit_exception_en; + logic sijump_en; + logic implicit_return_en; + logic branch_prediction_en; + logic jump_target_cache_en; +} ioptions_s; + +// enum that expresses the packet format and +// subformat to better readability +typedef enum logic[3:0] { + F0SF0 = 4'h0, + F0SF1 = 4'h1, + F1 = 4'h4, + F2 = 4'h8, + F3SF0 = 4'hC, + F3SF1 = 4'hD, + F3SF2 = 4'hE, + F3SF3 = 4'hF +} it_packet_type_e; // "it" stands for "instruction trace" + +/*TODO: + doptions struct for data tracing + refer to page 36 of the spec */ + +endpackage \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv new file mode 100644 index 00000000000..f28730ac7fb --- /dev/null +++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv @@ -0,0 +1,106 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// `include "common_cells/assertions.svh" + +/// A trailing zero counter / leading zero counter. +/// Set MODE to 0 for trailing zero counter => cnt_o is the number of trailing zeros (from the LSB) +/// Set MODE to 1 for leading zero counter => cnt_o is the number of leading zeros (from the MSB) +/// If the input does not contain a zero, `empty_o` is asserted. Additionally `cnt_o` contains +/// the maximum number of zeros - 1. For example: +/// in_i = 000_0000, empty_o = 1, cnt_o = 6 (mode = 0) +/// in_i = 000_0001, empty_o = 0, cnt_o = 0 (mode = 0) +/// in_i = 000_1000, empty_o = 0, cnt_o = 3 (mode = 0) +/// Furthermore, this unit contains a more efficient implementation for Verilator (simulation only). +/// This speeds up simulation significantly. +module lzc #( + /// The width of the input vector. + parameter int unsigned WIDTH = 2, + /// Mode selection: 0 -> trailing zero, 1 -> leading zero + parameter bit MODE = 1'b0, + /// Dependent parameter. Do **not** change! + /// + /// Width of the output signal with the zero count. + parameter int unsigned CNT_WIDTH = cf_math_pkg::idx_width(WIDTH) +) ( + /// Input vector to be counted. + input logic [WIDTH-1:0] in_i, + /// Count of the leading / trailing zeros. + output logic [CNT_WIDTH-1:0] cnt_o, + /// Counter is empty: Asserted if all bits in in_i are zero. + output logic empty_o +); + + if (WIDTH == 1) begin : gen_degenerate_lzc + + assign cnt_o[0] = !in_i[0]; + assign empty_o = !in_i[0]; + + end else begin : gen_lzc + + localparam int unsigned NumLevels = $clog2(WIDTH); + + // `ifndef COMMON_CELLS_ASSERTS_OFF + // `ASSERT_INIT(width_0, WIDTH > 0, "input must be at least one bit wide") + // `endif + + logic [WIDTH-1:0][NumLevels-1:0] index_lut; + logic [2**NumLevels-1:0] sel_nodes; + logic [2**NumLevels-1:0][NumLevels-1:0] index_nodes; + + logic [WIDTH-1:0] in_tmp; + + // reverse vector if required + always_comb begin : flip_vector + for (int unsigned i = 0; i < WIDTH; i++) begin + in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i]; + end + end + + for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut + assign index_lut[j] = (NumLevels)'(unsigned'(j)); + end + + for (genvar level = 0; unsigned'(level) < NumLevels; level++) begin : g_levels + if (unsigned'(level) == NumLevels - 1) begin : g_last_level + for (genvar k = 0; k < 2 ** level; k++) begin : g_level + // if two successive indices are still in the vector... + if (unsigned'(k) * 2 < WIDTH - 1) begin : g_reduce + assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2] | in_tmp[k * 2 + 1]; + assign index_nodes[2 ** level - 1 + k] = (in_tmp[k * 2] == 1'b1) + ? index_lut[k * 2] : + index_lut[k * 2 + 1]; + end + // if only the first index is still in the vector... + if (unsigned'(k) * 2 == WIDTH - 1) begin : g_base + assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2]; + assign index_nodes[2 ** level - 1 + k] = index_lut[k * 2]; + end + // if index is out of range + if (unsigned'(k) * 2 > WIDTH - 1) begin : g_out_of_range + assign sel_nodes[2 ** level - 1 + k] = 1'b0; + assign index_nodes[2 ** level - 1 + k] = '0; + end + end + end else begin : g_not_last_level + for (genvar l = 0; l < 2 ** level; l++) begin : g_level + assign sel_nodes[2 ** level - 1 + l] = + sel_nodes[2 ** (level + 1) - 1 + l * 2] | sel_nodes[2 ** (level + 1) - 1 + l * 2 + 1]; + assign index_nodes[2 ** level - 1 + l] = (sel_nodes[2 ** (level + 1) - 1 + l * 2] == 1'b1) + ? index_nodes[2 ** (level + 1) - 1 + l * 2] : + index_nodes[2 ** (level + 1) - 1 + l * 2 + 1]; + end + end + end + + assign cnt_o = NumLevels > unsigned'(0) ? index_nodes[0] : {($clog2(WIDTH)) {1'b0}}; + assign empty_o = NumLevels > unsigned'(0) ? ~sel_nodes[0] : ~(|in_i); + + end : gen_lzc + +// `ifndef COMMON_CELLS_ASSERTS_OFF +// `ASSERT_INIT(width_0, WIDTH >= 1, "The WIDTH must at least be one bit wide!") +// `endif + +endmodule : lzc diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv new file mode 100644 index 00000000000..c920c876a26 --- /dev/null +++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv @@ -0,0 +1,911 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +/* TOP LEVEL MODULE */ + +module rv_tracer #( + //parameter IRETIRE_LEN = 32, // set to 1 for single retirement + parameter N = 1, // max number of special inst retired in a cycle, the input port number depends on this value + parameter ONLY_BRANCHES = 0, // special inst are branches or not + parameter APB_ADDR_WIDTH = 32 // address width for APB interface +) +( + input logic clk_i, + input logic rst_ni, + + input logic [N-1:0] valid_i, // used for multiple retirement + + /* data from the CPU */ + // mandatory inputs + input logic [N-1:0][te_pkg::ITYPE_LEN-1:0] itype_i, // termination type of block + input logic [te_pkg::XLEN-1:0] cause_i, + input logic [te_pkg::XLEN-1:0] tval_i, + input logic [te_pkg::PRIV_LEN-1:0] priv_i, + input logic [N-1:0][te_pkg::XLEN-1:0] iaddr_i, // pc of 1st inst in block + input logic [N-1:0][te_pkg::IRETIRE_LEN-1:0] iretire_i, // length of block in halfwords + input logic [N-1:0] ilastsize_i, // length of last inst in 2^ilastsize halfword + // non mandatory inputs + input logic [te_pkg::TIME_LEN-1:0] time_i, + //input logic [:0] context_i, + //input logic [te_pkg::CTYPE_LEN-1:0] ctype_i, // spec says it's 1 or 2 bit wide + //input logic [te_pkg::TRIGGER_LEN-1:0] trigger_i, // must be supported CPU side + + // support inputs + input logic [te_pkg::XLEN-1:0] tvec_i, // tvec_q, contains trap handler address + input logic [te_pkg::XLEN-1:0] epc_i, // epc_q, required for format 3 subformat 1 + input logic encapsulator_ready_i, // non mandatory + + // APB interface inputs + input logic [APB_ADDR_WIDTH-1:0] paddr_i, + input logic pwrite_i, + input logic psel_i, + input logic penable_i, + input logic [31:0] pwdata_i, + + // outputs + // info needed for the encapsulator + output logic [N-1:0] packet_valid_o, + output te_pkg::it_packet_type_e [N-1:0] packet_type_o, + output logic [N-1:0][te_pkg::P_LEN-1:0] packet_length_o, // in bytes + output logic [N-1:0][te_pkg::PAYLOAD_LEN-1:0] packet_payload_o, + // sideband signals + output logic stall_o, + + // APB interface outputs + output logic pready_o, + output logic [31:0] prdata_o +); + + /* signals for management */ + // registers + logic trace_activated; + logic trace_enable; + logic nocontext; + logic notime; + logic encoder_mode; + // filter + logic trigger_trace_on; // hardwired to 0? + logic trigger_trace_off; // hardwired to 0? + //logic qualified; // is it needed or I can use qualified_d? + logic trace_req_deactivate; + // priority + te_pkg::format_e packet_format[N-1:0]; + te_pkg::f_sync_subformat_e packet_f_sync_subformat[N-1:0]; + te_pkg::f_opt_ext_subformat_e packet_f_opt_ext_subformat[N-1:0]; + logic thaddr[N-1:0]; + logic lc_tc_mux[N-1:0]; + te_pkg::qual_status_e qual_status[N-1:0]; + logic nc_branch_map_flush; + logic [te_pkg::BRANCH_MAP_LEN-1:0] branch_map; + logic [te_pkg::BRANCH_COUNT_LEN-1:0] branch_count; + logic resync_rst; + // packet emitter + logic packet_valid[N-1:0]; + // resync counter + logic [N-1:0] packet_emitted; + // not classified + logic nc_branch_map_empty; + logic clk_gated; + logic turn_on_tracer_d, turn_on_tracer_q; + logic lossless_trace; + logic shallow_trace; + + // we have three phases, called last cycle (lc), this cycle (tc) and next + // cycle (nc), based on which we make decision whether we need to emit a + // packet or not. + logic tc_branch_map_empty; + logic [N-1:0] tc_resync; + logic [N-1:0] nc_exc_only; + logic [N-1:0] nc_ppccd_br; + logic [$clog2(te_pkg::XLEN):0] keep_bits[N-1:0]; + logic [te_pkg::XLEN-1:0] addr_to_compress[N-1:0]; + + logic [1:0][N-1:0][te_pkg::IRETIRE_LEN-1:0] iretired_tab; + logic [2:0] exception_tab; + logic [2:0] interrupt_tab; + logic [2:0][te_pkg::XLEN-1:0] cause_tab; + logic [1:0][te_pkg::XLEN-1:0] tvec_tab; + logic [2:0][te_pkg::XLEN-1:0] tval_tab; + logic [1:0][N-1:0][te_pkg::ITYPE_LEN-1:0] itype_tab; + logic [1:0][te_pkg::PRIV_LEN-1:0] priv_tab; + logic [1:0][N-1:0][te_pkg::XLEN-1:0] address_tab; + logic [2:0][te_pkg::XLEN-1:0] epc_tab; + logic [1:0][te_pkg::TIME_LEN-1:0] time_tab; + logic [2:0][N-1:0] updiscon_tab; + logic [2:0][N-1:0] qualified_tab; + + logic [N-1:0][te_pkg::IRETIRE_LEN-1:0] tc_iretired, nc_iretired; + logic lc_exception, tc_exception, nc_exception; + logic lc_interrupt, tc_interrupt, nc_interrupt; + logic [te_pkg::XLEN-1:0] lc_cause, tc_cause, nc_cause; + logic [te_pkg::XLEN-1:0] tc_tvec, nc_tvec; + logic [te_pkg::XLEN-1:0] lc_tval, tc_tval, nc_tval; + logic [N-1:0][te_pkg::ITYPE_LEN-1:0] tc_itype, nc_itype; + logic [te_pkg::PRIV_LEN-1:0] tc_priv, nc_priv; + logic [N-1:0][te_pkg::XLEN-1:0] tc_address, nc_address; + logic [te_pkg::XLEN-1:0] lc_epc, tc_epc, nc_epc; + logic [te_pkg::TIME_LEN-1:0] tc_time, nc_time; + logic [N-1:0] lc_updiscon, tc_updiscon, nc_updiscon; + logic [N-1:0] lc_qualified, tc_qualified, nc_qualified; + + + logic tc_first_qualified; + logic tc_final_qualified; + logic [N-1:0] updiscon; + logic [N-1:0][te_pkg::XLEN-1:0] address; + logic [N-1:0] qualified; + + + logic [N-1:0] valid0_d, valid0_q; + logic privchange_d, privchange_q; + // logic context_change_d, context_change_q; // non mandatory + // logic precise_context_report_d, precise_context_report_q; // requires ctype signal CPU side + // logic context_report_as_disc_d, context_report_as_disc_q; // ibidem + // logic no_context_report_d, no_context_report_q; // ibidem + // logic imprecise_context_report_d, imprecise_context_report_q; // ibidem + logic gt_max_resync_d, gt_max_resync_q; + logic et_max_resync_d, et_max_resync_q; + logic branch_map_full_d, branch_map_full_q; + //logic branch_misprediction_d, branch_misprediction_q; // non mandatory + logic trace_activated_d, trace_activated_q; + logic enc_activated_d, enc_activated_q; + logic enc_deactivated_d, enc_deactivated_q; + //logic packets_lost_d, packets_lost_q; // non mandatory + te_pkg::ioptions_s enc_config_d, enc_config_q; + logic enc_config_change_d, enc_config_change_q; + logic branch_d, branch_q; + logic branch_taken_d, branch_taken_q; + + // branch_map inputs + logic [N-1:0] branch_valid; + logic [N-1:0] branch_taken; + + // te_reg output to filter input + logic cause_filter; + logic [te_pkg::XLEN-1:0] upper_cause; + logic [te_pkg::XLEN-1:0] lower_cause; + logic [te_pkg::XLEN-1:0] match_cause; + logic cause_mode; + logic tvec_filter; + logic [te_pkg::XLEN-1:0] upper_tvec; + logic [te_pkg::XLEN-1:0] lower_tvec; + logic [te_pkg::XLEN-1:0] match_tvec; + logic tvec_mode; + logic tval_filter; + logic [te_pkg::XLEN-1:0] upper_tval; + logic [te_pkg::XLEN-1:0] lower_tval; + logic [te_pkg::XLEN-1:0] match_tval; + logic tval_mode; + logic priv_lvl_filter; + logic [te_pkg::PRIV_LEN-1:0] upper_priv; + logic [te_pkg::PRIV_LEN-1:0] lower_priv; + logic [te_pkg::PRIV_LEN-1:0] match_priv; + logic priv_lvl_mode; + logic iaddr_filter; + logic [te_pkg::XLEN-1:0] upper_iaddr; + logic [te_pkg::XLEN-1:0] lower_iaddr; + logic [te_pkg::XLEN-1:0] match_iaddr; + logic iaddr_mode; + + /* the following commented section has non mandatory signals + for now it's commented + */ + /* combinatorial network to define the following + signals from ctype: + - tc_no_context_report_i -> ctype == 0 + - tc_precise_context_report_i -> ctype == 2 + - tc_context_report_as_disc_i -> ctype == 3 + - tc_imprecise_context_report_i -> ctype == 1 + - nc_precise_context_report_i -> ctype == 2 + - nc_context_report_as_disc_i -> ctype == 3*/ + /* + always_comb begin : ctype_manager + case(ctype_i) + 2'h0: // no report - add signal + tc_no_context_report = '1; + 2'h1: + tc_imprecise_context_report = '1; + 2'h2: + tc_precise_context_report = '1; + 2'h3: + tc_context_report_as_disc = '1; + endcase + end + */ + + /*TODO: create a trigger decoder that produces: + - trigger_trace_on -> 2 + - trigger_trace_off -> 3 + - trigger_notify -> 4 + */ + // maybe it's enough to define values and hardwire them to 0 + + /* ASSIGNMENT */ + /* hardwired assignments */ + assign trigger_trace_on = '0; + assign trigger_trace_off = '0; + + /* FFs inputs */ + assign valid0_d = valid_i; + assign trace_activated_d = trace_activated; + assign enc_activated_d = trace_activated_d && ~trace_activated_q; + assign enc_deactivated_d = ~trace_activated_d && trace_activated_q; + assign enc_config_change_d = enc_config_d != enc_config_q; + + /* next cycle */ + assign nc_branch_map_empty = nc_branch_map_flush || (tc_branch_map_empty /*&& ~branch_q*/); + + // output + assign packet_valid_o = packet_emitted; + // sideband + assign stall_o = ~encapsulator_ready_i && lossless_trace; + + // other + assign branch_taken_d = |branch_taken; + + // first and final qualified + assign tc_first_qualified = trace_activated && |tc_qualified && !lc_qualified && trace_enable; + assign tc_final_qualified = trace_activated && |lc_qualified && !tc_qualified && trace_enable; + + always_ff @( posedge clk_i, negedge rst_ni ) begin + if(~rst_ni) begin + iretired_tab <= '0; + exception_tab <= '0; + interrupt_tab <= '0; + cause_tab <= '0; + tvec_tab <= '0; + tval_tab <= '0; + itype_tab <= '0; + priv_tab <= '0; + address_tab <= '0; + epc_tab <= '0; + time_tab <= '0; + updiscon_tab <= '0; + qualified_tab <= '0; + end else begin + if (|valid_i) begin + iretired_tab <= {iretired_tab[0], iretire_i}; + exception_tab <= {exception_tab[1:0], itype_i[0] == 1}; + interrupt_tab <= {interrupt_tab[1:0], itype_i[0] == 2}; + cause_tab <= {cause_tab[1:0],cause_i}; + tvec_tab <= {tvec_tab[0], tvec_i}; + tval_tab <= {tval_tab [1:0], tval_i}; + itype_tab <= {itype_tab[0], itype_i}; + priv_tab <= {priv_tab[0], priv_i}; + address_tab <= {address_tab[0], address}; + epc_tab <= {epc_tab[1:0], epc_i}; + time_tab <= {time_tab[0], time_i}; + updiscon_tab <= {updiscon_tab[1:0], updiscon}; + qualified_tab <={qualified_tab[1:0], qualified}; + end + end + + end + //lc asignements + assign lc_exception = exception_tab[2]; + assign lc_interrupt = interrupt_tab[2]; + assign lc_cause = cause_tab[2]; + assign lc_tval = tval_tab[2]; + assign lc_epc = epc_tab[2]; + assign lc_updiscon = updiscon_tab[2]; + assign lc_qualified = qualified_tab[2]; + // tc assignements + assign tc_iretired = iretired_tab[1]; + assign tc_exception = exception_tab[1]; + assign tc_interrupt = interrupt_tab[1]; + assign tc_cause= cause_tab[1]; + assign tc_tvec = tvec_tab[1]; + assign tc_tval = tval_tab[1]; + assign tc_itype = itype_tab[1]; + assign tc_priv = priv_tab[1]; + assign tc_address = address_tab[1]; + assign tc_epc = epc_tab[1]; + assign tc_time = time_tab[1]; + assign tc_updiscon = updiscon_tab[1]; + assign tc_qualified = qualified_tab[1]; + + // nc assignements + assign nc_iretired = iretired_tab[0]; + assign nc_exception = exception_tab[0]; + assign nc_interrupt = interrupt_tab[0]; + assign nc_cause= cause_tab[0]; + assign nc_tvec = tvec_tab[0]; + assign nc_tval = tval_tab[0]; + assign nc_itype = itype_tab[0]; + assign nc_priv = priv_tab[0]; + assign nc_address = address_tab[0]; + assign nc_epc = epc_tab[0]; + assign nc_time = time_tab[0]; + assign nc_updiscon = updiscon_tab[0]; + assign nc_qualified = qualified_tab[0]; + + //FIXME need cleaning + // not static assignments + always_comb begin + // init + branch_valid = '0; + branch_taken = '0; + + privchange_d = privchange_q; + // context_change_d = context_change_q; + // precise_context_report_d = precise_context_report_q; // requires ctype signal CPU side + // context_report_as_disc_d = context_report_as_disc_q; //ibidem + // no_context_report_d = no_context_report_q; // ibidem + // imprecise_context_report_d = imprecise_context_report_q; // ibidem + branch_d = branch_q; + + // itype, iretired and address + // it works for all three cases + for (int i = 0; i < N; i++) begin + if (valid_i[i]) begin + address[i] = iaddr_i[i]; + //FIXME we remove block reconstruction address + //address[i] = iaddr_i[i]+2*(iretire_i[i] - 2**ilastsize_i[i]); + end + end + //FIXME weird timing here nc for erveryone ? + // assigning branch map inputs + for (int i = 0; i < N; i++) begin + if (nc_itype[i] == 4 || nc_itype[i] == 5) begin + branch_valid[i] = '1; + end + if (nc_itype[i] == 5) begin + branch_taken[i] = '1; + end + end + + // updiscon + if (N == 1 || (N > 1 && ONLY_BRANCHES)) begin + if (qualified[0]) begin + updiscon[0] = itype_i[0] == 6; + end + end + // wait for this case + if (N > 1 && !ONLY_BRANCHES) begin + for (int i = 0; i < N; i++) begin + if (qualified[i]) begin + updiscon[i] = itype_i[i] == 6; + end + end + end + + // updating registers values + if (|valid_i) begin + privchange_d = (nc_priv != tc_priv) && |valid_i; + // context_change_d; // TODO + //precise_context_report_d; // requires ctype signal CPU side + //context_report_as_disc_d; //ibidem + //no_context_report_d; // ibidem + //imprecise_context_report_d; // ibidem + branch_d = |branch_valid; + end + + if (!turn_on_tracer_q) begin + turn_on_tracer_d = |valid_i && nc_qualified; + end + end + + /* MODULES INSTANTIATION */ + // one instance for all 3 cases + + + /* MAPPED REGISTERS */ + te_reg #( + .APB_ADDR_WIDTH(APB_ADDR_WIDTH) + ) i_te_reg( + .clk_i (clk_i), + .rst_ni (rst_ni), + .trace_req_off_i ('0), + .trace_req_on_i (turn_on_tracer_q), // trigger_trace_on // from trigger unit + .encapsulator_ready_i(encapsulator_ready_i), + .cause_filter_o (cause_filter), + .upper_cause_o (upper_cause), + .lower_cause_o (lower_cause), + .match_cause_o (match_cause), + .cause_mode_o (cause_mode), + .tvec_filter_o (tvec_filter), + .upper_tvec_o (upper_tvec), + .lower_tvec_o (lower_tvec), + .match_tvec_o (match_tvec), + .tvec_mode_o (tvec_mode), + .tval_filter_o (tval_filter), + .upper_tval_o (upper_tval), + .lower_tval_o (lower_tval), + .match_tval_o (match_tval), + .tval_mode_o (tval_mode), + .priv_lvl_filter_o (priv_lvl_filter), + .upper_priv_o (upper_priv), + .lower_priv_o (lower_priv), + .match_priv_o (match_priv), + .priv_lvl_mode_o (priv_lvl_mode), + .iaddr_filter_o (iaddr_filter), + .upper_iaddr_o (upper_iaddr), + .lower_iaddr_o (lower_iaddr), + .match_iaddr_o (match_iaddr), + .iaddr_mode_o (iaddr_mode), + .trace_enable_o (trace_enable), + .trace_activated_o (trace_activated), + .nocontext_o (nocontext), + .notime_o (notime), + .encoder_mode_o (encoder_mode), + .configuration_o (enc_config_d), + .lossless_trace_o (lossless_trace), + .shallow_trace_o (shallow_trace), + .clk_gated_o (clk_gated), + .paddr_i (paddr_i), + .pwrite_i (pwrite_i), + .psel_i (psel_i), + .penable_i (penable_i), + .pwdata_i (pwdata_i), + .pready_o (pready_o), + .prdata_o (prdata_o) + ); + + /* BRANCH MAP */ + te_branch_map #( + .N(N) + ) i_te_branch_map( + .clk_i (clk_gated), + .rst_ni (rst_ni), + .valid_i (branch_valid & nc_qualified & valid0_q), + .branch_taken_i(branch_taken), + .flush_i (nc_branch_map_flush), + //.branch_taken_prediction_i(), // non mandatory + .map_o (branch_map), + .branches_o (branch_count), + //.pbc_o(), // non mandatory - branch prediction mode + //.misprediction_o(), // non mandatory - ibidem + .is_full_o (branch_map_full_d), + .is_empty_o (tc_branch_map_empty) + ); + + /* RESYNC COUNTER */ + te_resync_counter #( + .N(N), + .MODE(te_pkg::CYCLE_MODE), // count cycles + .MAX_VALUE(13'h1FFF) // 8192 + ) i_te_resync_counter( // for testing we keep the def settings + .clk_i (clk_gated), + .rst_ni (rst_ni), + .trace_enabled_i (trace_enable), + .packet_emitted_i(packet_emitted), + .resync_rst_i (resync_rst), + .gt_resync_max_o (gt_max_resync_d), + .et_resync_max_o (et_max_resync_d) + ); + + // N instances for all 3 cases + + /* FILTER */ + generate + if (ONLY_BRANCHES) begin + for (genvar i = 0; i < N; i++) begin + te_filter i_te_filter( + .trace_enable_i (trace_enable || trace_activated), // tracks 1st branch if 1st inst + .cause_filter_i (cause_filter), + .upper_cause_i (upper_cause), + .lower_cause_i (lower_cause), + .match_cause_i (match_cause), + .cause_mode_i (cause_mode), + .cause_i (cause_i), + .tvec_filter_i (tvec_filter), + .upper_tvec_i (upper_tvec), + .lower_tvec_i (lower_tvec), + .match_tvec_i (match_tvec), + .tvec_mode_i (tvec_mode), + .tvec_i (tvec_i), + .tval_filter_i (tval_filter), + .upper_tval_i (upper_tval), + .lower_tval_i (lower_tval), + .match_tval_i (match_tval), + .tval_mode_i (tval_mode), + .tval_i (tval_i), + .priv_lvl_filter_i(priv_lvl_filter), + .upper_priv_i (upper_priv), + .lower_priv_i (lower_priv), + .match_priv_i (match_priv), + .priv_lvl_mode_i (priv_lvl_mode), + .priv_i (priv_i), + .iaddr_filter_i (iaddr_filter), + .upper_iaddr_i (upper_iaddr), + .lower_iaddr_i (lower_iaddr), + .match_iaddr_i (match_iaddr), + .iaddr_mode_i (iaddr_mode), + .iaddr_i (iaddr_i[i]), + .nc_qualified_o (qualified[i]) + ); + end + end + endgenerate + + /* PRIORITY, PACKET EMITTER*/ + // case dependant + generate + // 1 instance for N == 1 || (N > 1 && ONLY_BRANCHES) + if (N == 1 || (N > 1 && ONLY_BRANCHES)) begin + /* PRIORITY */ + te_priority i_te_priority( + .clk_i (clk_gated), + .rst_ni (rst_ni), + .valid_i (valid0_q[0] || (enc_activated_q || enc_deactivated_q)), // necessary to generate F3SF3 packet + .lc_exception_i (lc_exception || lc_interrupt), + .lc_updiscon_i (lc_updiscon), + .tc_qualified_i (tc_qualified[0]), + .tc_exception_i (tc_exception|| tc_interrupt), + .tc_retired_i (tc_iretired[0]), + .tc_first_qualified_i (tc_first_qualified), + .tc_privchange_i (privchange_q), + //.tc_context_change_i(), // non mandatory + //.tc_precise_context_report_i(), // requires ctype signal CPU side + //.tc_context_report_as_disc_i(), // ibidem + //.tc_imprecise_context_report_i(), // ibidem + .tc_gt_max_resync_i (gt_max_resync_q), + .tc_et_max_resync_i (et_max_resync_q), + .tc_branch_map_empty_i (tc_branch_map_empty), + .tc_branch_map_full_i (branch_map_full_d), + //.tc_branch_misprediction_i(), // non mandatory + //.tc_pbc_i(), // non mandatory + .tc_enc_enabled_i (enc_activated_q), + .tc_enc_disabled_i (enc_deactivated_q), + .tc_opmode_change_i (enc_config_change_q), + .tc_final_qualified_i (tc_final_qualified), + .tc_packets_lost_i (~encapsulator_ready_i), // non mandatory + .nc_exception_i (nc_exception || nc_interrupt), + .nc_privchange_i (privchange_d), + //.nc_context_change_i(), + //.nc_precise_context_report_i(), // requires ctype signal CPU side + //.nc_context_report_as_disc_i(), // ibidem + .nc_branch_map_empty_i (nc_branch_map_empty), + .nc_qualified_i (nc_qualified[0]), + .nc_retired_i (nc_iretired[0]), + //.halted_i(), // non mandatory side band signal + //.reset_i(), // ibidem + //.implicit_return_i(), // non mandatory + //.tc_trigger_req_i(), // non mandatory + //.notify_o(), // non mandatory, depends on trigger request + .addr_to_compress_i (addr_to_compress[0]), + .valid_o (packet_valid[0]), + .packet_format_o (packet_format[0]), + .packet_f_sync_subformat_o(packet_f_sync_subformat[0]), + //.packet_f_opt_ext_subformat_o(packet_f_opt_ext_subformat), // non mandatory + .thaddr_o (thaddr[0]), + .lc_tc_mux_o (lc_tc_mux[0]), + .resync_timer_rst_o (resync_rst), + .qual_status_o (qual_status[0]), + .tc_resync_o (tc_resync[0]), + .nc_exc_only_o (nc_exc_only[0]), + .nc_ppccd_br_o (nc_ppccd_br[0]), + .keep_bits_o (keep_bits[0]) + ); + + /* PACKET EMITTER */ + te_packet_emitter i_te_packet_emitter( + .clk_i (clk_gated), + .rst_ni (rst_ni), + .valid_i (packet_valid[0]), + .packet_format_i (packet_format[0]), + .packet_f_sync_subformat_i(packet_f_sync_subformat[0]), + //.packet_f_opt_ext_subformat_i(packet_f_opt_ext_subformat), // non mandatory + .lc_cause_i (lc_cause), + .lc_tval_i (lc_tval), + .lc_interrupt_i (lc_interrupt), + .tc_cause_i (tc_cause), + .tc_tval_i (tc_tval), + .tc_interrupt_i (tc_interrupt), + .tc_resync_i (tc_resync[0]), + .nc_exc_only_i (nc_exc_only[0]), + .nc_ppccd_br_i (nc_ppccd_br[0]), + .nocontext_i (nocontext), + .notime_i (notime), + .tc_branch_i (branch_q), + .tc_branch_taken_i (branch_taken_q), + .tc_priv_i (tc_priv), + .tc_time_i (tc_time), // non mandatory + //.context_i(), // non mandatory + .tc_address_i (tc_address[0]), + .lc_tc_mux_i (lc_tc_mux[0]), + .thaddr_i (thaddr[0]), + .tc_tvec_i (tc_tvec), + .lc_epc_i (lc_epc), + .tc_ienable_i (trace_enable), + .encoder_mode_i (encoder_mode), + .qual_status_i (qual_status[0]), + .ioptions_i (enc_config_q), + //.denable_i(), // stand-by + //.dloss_i(), //stand-by + //.notify_i(), // non mandatory + .lc_updiscon_i (lc_updiscon[0]), + //.irreport_i(), // non mandatory + //.irdepth_i(), // non mandatory + .branches_i (branch_count), + .branch_map_i (branch_map), + .keep_bits_i (keep_bits[0]), + .shallow_trace_i (shallow_trace), + .packet_valid_o (packet_emitted[0]), + .packet_type_o (packet_type_o[0]), + .packet_payload_o (packet_payload_o[0]), + .payload_length_o (packet_length_o[0]), + .branch_map_flush_o (nc_branch_map_flush), + .addr_to_compress_o (addr_to_compress[0]) + ); + + end else if (N > 1 && !ONLY_BRANCHES) begin + // N instances for N > 1 && !ONLY_BRANCHES + for (genvar i = 0; i < N; i++) begin + if (i == 0) begin + /* PRIORITY */ + te_priority i_te_priority( + .clk_i (clk_gated), + .rst_ni (rst_ni), + .valid_i (|valid0_q || (enc_activated_q || enc_deactivated_q)), + .lc_exception_i (lc_exception || lc_interrupt), + .lc_updiscon_i (lc_updiscon[i]), + .tc_qualified_i (tc_qualified[i]), + .tc_exception_i (tc_exception|| tc_interrupt), + .tc_retired_i (tc_iretired[i]), + .tc_first_qualified_i (tc_first_qualified), + .tc_privchange_i (privchange_q), + //.tc_context_change_i(), // non mandatory + //.tc_precise_context_report_i(), // requires ctype signal CPU side + //.tc_context_report_as_disc_i(), // ibidem + //.tc_imprecise_context_report_i(), // ibidem + .tc_gt_max_resync_i (gt_max_resync_q), // connected only to the first port + .tc_et_max_resync_i (et_max_resync_q), // connected only to the first port + .tc_branch_map_empty_i (tc_branch_map_empty), + .tc_branch_map_full_i (branch_map_full_q), // connected only to the first port + //.tc_branch_misprediction_i(), // non mandatory + //.tc_pbc_i(), // non mandatory + .tc_enc_enabled_i (enc_activated_q), + .tc_enc_disabled_i (enc_deactivated_q), + .tc_opmode_change_i (enc_config_change_q), + .tc_final_qualified_i (tc_final_qualified), + .tc_packets_lost_i (~encapsulator_ready_i), // non mandatory + .nc_exception_i (nc_exception || nc_interrupt), + .nc_privchange_i (privchange_d), + //.nc_context_change_i(), + //.nc_precise_context_report_i(), // requires ctype signal CPU side + //.nc_context_report_as_disc_i(), // ibidem + .nc_branch_map_empty_i (nc_branch_map_empty), + .nc_qualified_i (nc_qualified[i]), + .nc_retired_i (nc_iretired[i]), + //.halted_i(), // non mandatory side band signal + //.reset_i(), // ibidem + //.implicit_return_i(), // non mandatory + //.tc_trigger_req_i(), // non mandatory + //.notify_o(), // non mandatory, depends on trigger request + .addr_to_compress_i (addr_to_compress[i]), + .valid_o (packet_valid[i]), + .packet_format_o (packet_format[i]), + .packet_f_sync_subformat_o(packet_f_sync_subformat[i]), + //.packet_f_opt_ext_subformat_o(packet_f_opt_ext_subformat), // non mandatory + .thaddr_o (thaddr[i]), + .lc_tc_mux_o (lc_tc_mux[i]), + .resync_timer_rst_o (resync_rst), + .qual_status_o (qual_status[i]), + .tc_resync_o (tc_resync[i]), + .nc_exc_only_o (nc_exc_only[i]), + .nc_ppccd_br_o (nc_ppccd_br[i]), + .keep_bits_o (keep_bits[i]) + ); + + /* PACKET EMITTER */ + te_packet_emitter i_te_packet_emitter( + .clk_i (clk_gated), + .rst_ni (rst_ni), + .valid_i (packet_valid[i]), + .packet_format_i (packet_format[i]), + .packet_f_sync_subformat_i(packet_f_sync_subformat[i]), + //.packet_f_opt_ext_subformat_i(packet_f_opt_ext_subformat), // non mandatory + .lc_cause_i (lc_cause), + .lc_tval_i (lc_tval), + .lc_interrupt_i (lc_interrupt), + .tc_cause_i (tc_cause), + .tc_tval_i (tc_tval), + .tc_interrupt_i (tc_interrupt), + .tc_resync_i (tc_resync[i]), + .nc_exc_only_i (nc_exc_only[i]), + .nc_ppccd_br_i (nc_ppccd_br[i]), + .nocontext_i (nocontext), + .notime_i (notime), + .tc_branch_i (branch_q), + .tc_branch_taken_i (branch_taken_q), + .tc_priv_i (tc_priv), + .tc_time_i (tc_time), // non mandatory + //.context_i(), // non mandatory + .tc_address_i (tc_address[i]), + .lc_tc_mux_i (lc_tc_mux[i]), + .thaddr_i (thaddr[i]), + .tc_tvec_i (tc_tvec), + .lc_epc_i (lc_epc), + .tc_ienable_i (trace_enable), + .encoder_mode_i (encoder_mode), + .qual_status_i (qual_status[i]), + .ioptions_i (enc_config_q), + //.denable_i(), // stand-by + //.dloss_i(), //stand-by + //.notify_i(), // non mandatory + .lc_updiscon_i (lc_updiscon[i]), + //.irreport_i(), // non mandatory + //.irdepth_i(), // non mandatory + .branches_i (branch_count), + .branch_map_i (branch_map), + .keep_bits_i (keep_bits[i]), + .shallow_trace_i (shallow_trace), + .packet_valid_o (packet_emitted[i]), + .packet_type_o (packet_type_o[i]), + .packet_payload_o (packet_payload_o[i]), + .payload_length_o (packet_length_o[i]), + .branch_map_flush_o (nc_branch_map_flush), + .addr_to_compress_o (addr_to_compress[i]) + ); + end else begin + /* PRIORITY */ + te_priority i_te_priority( + .clk_i (clk_gated), + .rst_ni (rst_ni), + .valid_i (|valid0_q || (enc_activated_q || enc_deactivated_q)), + .lc_exception_i (lc_exception || lc_interrupt), + .lc_updiscon_i (lc_updiscon[i]), + .tc_qualified_i (tc_qualified[i]), + .tc_exception_i (tc_exception || tc_interrupt), + .tc_retired_i (tc_iretired[i]), + .tc_first_qualified_i (tc_first_qualified), + .tc_privchange_i (privchange_q), + //.tc_context_change_i(), // non mandatory + //.tc_precise_context_report_i(), // requires ctype signal CPU side + //.tc_context_report_as_disc_i(), // ibidem + //.tc_imprecise_context_report_i(), // ibidem + .tc_gt_max_resync_i (), // connected only to the first port + .tc_et_max_resync_i (), // connected only to the first port + .tc_branch_map_empty_i (tc_branch_map_empty), + .tc_branch_map_full_i (), // connected only to the first port + //.tc_branch_misprediction_i(), // non mandatory + //.tc_pbc_i(), // non mandatory + .tc_enc_enabled_i (enc_activated_q), + .tc_enc_disabled_i (enc_deactivated_q), + .tc_opmode_change_i (enc_config_change_q), + .tc_final_qualified_i (tc_final_qualified), + .tc_packets_lost_i (~encapsulator_ready_i), // non mandatory + .nc_exception_i (nc_exception || nc_interrupt), + .nc_privchange_i (privchange_d), + //.nc_context_change_i(), + //.nc_precise_context_report_i(), // requires ctype signal CPU side + //.nc_context_report_as_disc_i(), // ibidem + .nc_branch_map_empty_i (nc_branch_map_empty), + .nc_qualified_i (nc_qualified[i]), + .nc_retired_i (nc_iretired[i]), + //.halted_i(), // non mandatory side band signal + //.reset_i(), // ibidem + //.implicit_return_i(), // non mandatory + //.tc_trigger_req_i(), // non mandatory + //.notify_o(), // non mandatory, depends on trigger request + .addr_to_compress_i (addr_to_compress[i]), + .valid_o (packet_valid[i]), + .packet_format_o (packet_format[i]), + .packet_f_sync_subformat_o(packet_f_sync_subformat[i]), + //.packet_f_opt_ext_subformat_o(packet_f_opt_ext_subformat), // non mandatory + .thaddr_o (thaddr[i]), + .lc_tc_mux_o (lc_tc_mux[i]), + .resync_timer_rst_o (), // connected only to the first port + .qual_status_o (qual_status[i]), + .tc_resync_o (tc_resync[i]), + .nc_exc_only_o (nc_exc_only[i]), + .nc_ppccd_br_o (nc_ppccd_br[i]), + .keep_bits_o (keep_bits[i]) + ); + + /* PACKET EMITTER */ + te_packet_emitter i_te_packet_emitter( + .clk_i (clk_gated), + .rst_ni (rst_ni), + .valid_i (packet_valid[i]), + .packet_format_i (packet_format[i]), + .packet_f_sync_subformat_i(packet_f_sync_subformat[i]), + //.packet_f_opt_ext_subformat_i(packet_f_opt_ext_subformat), // non mandatory + .lc_cause_i (lc_cause), + .lc_tval_i (lc_tval), + .lc_interrupt_i (lc_interrupt), + .tc_cause_i (tc_cause), + .tc_tval_i (tc_tval), + .tc_interrupt_i (tc_interrupt), + .tc_resync_i (tc_resync[i]), + .nc_exc_only_i (nc_exc_only[i]), + .nc_ppccd_br_i (nc_ppccd_br[i]), + .nocontext_i (nocontext), + .notime_i (notime), + .tc_branch_i (branch_q), + .tc_branch_taken_i (branch_taken_q), + .tc_priv_i (tc_priv), + .tc_time_i (tc_time), // non mandatory + //.context_i(), // non mandatory + .tc_address_i (tc_address[i]), + .lc_tc_mux_i (lc_tc_mux[i]), + .thaddr_i (thaddr[i]), + .tc_tvec_i (tc_tvec), + .lc_epc_i (lc_epc), + .tc_ienable_i (trace_enable), + .encoder_mode_i (encoder_mode), + .qual_status_i (qual_status[i]), + .ioptions_i (enc_config_q), + //.denable_i(), // stand-by + //.dloss_i(), //stand-by + //.notify_i(), // non mandatory + .lc_updiscon_i (lc_updiscon[i]), + //.irreport_i(), // non mandatory + //.irdepth_i(), // non mandatory + .branches_i (branch_count), + .branch_map_i (branch_map), + .keep_bits_i (keep_bits[i]), + .shallow_trace_i (shallow_trace), + .packet_valid_o (packet_emitted[i]), + .packet_type_o (packet_type_o[i]), + .packet_payload_o (packet_payload_o[i]), + .payload_length_o (packet_length_o[i]), + .branch_map_flush_o (), // connected only to the first port + .addr_to_compress_o (addr_to_compress[i]) + ); + end + end + end + endgenerate + + /* REGISTERS MANAGEMENT */ + always_ff @( posedge clk_i, negedge rst_ni ) begin : registers + if(~rst_ni) begin + valid0_q <= '0; + privchange_q <= '0; + // context_change_q <= '0; + //precise_context_report_q <= '0; // requires ctype signal CPU side + //context_report_as_disc_q <= '0; //ibidem + //no_context_report_q <= '0; // ibidem + //imprecise_context_report_q <= '0; // ibidem + gt_max_resync_q <= '0; + et_max_resync_q <= '0; + branch_map_full_q <= '0; + //branch_misprediction_q <= '0; // non mandatory + trace_activated_q <= '0; + enc_activated_q <= '0; + enc_deactivated_q <= '0; + //packets_lost_q <= '0; // non mandatory + enc_config_q <= te_pkg::DELTA_ADDRESS; // 3'b0 + enc_config_change_q <= '0; + branch_taken_q <= '0; + branch_q <= '0; + turn_on_tracer_q <= '0; + end else begin + privchange_q <= privchange_d; + // context_change_q <= context_change_d; + //precise_context_report_q <= precise_context_report_d; // requires ctype signal CPU side + //context_report_as_disc_q <= context_report_as_disc_d; //ibidem + //no_context_report_q <= no_context_report_d; // ibidem + //imprecise_context_report_q <= imprecise_context_report_d; // ibidem + branch_q <= branch_d; + valid0_q <= valid0_d; + gt_max_resync_q <= gt_max_resync_d; + et_max_resync_q <= et_max_resync_d; + branch_map_full_q <= branch_map_full_d; + //branch_misprediction_q <= branch_misprediction_d; // non mandatory + trace_activated_q <= trace_activated_d; + enc_activated_q <= enc_activated_d; + enc_deactivated_q <= enc_deactivated_d; + //packets_lost_q <= packets_lost_d; // non mandatory + enc_config_q <= enc_config_d; + enc_config_change_q <= enc_config_change_d; + branch_taken_q <= branch_taken_d; + turn_on_tracer_q <= turn_on_tracer_d; + end + end + +endmodule \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv new file mode 100644 index 00000000000..c1e2f0fc8b7 --- /dev/null +++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv @@ -0,0 +1,85 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +/* BRANCH MAP */ +/* +It keeps track of taken and non taken branches. + +Whenever a branch happens it updates the branch map +and the number of branches stored. + +When flush_i signal is asserted, the branch map is +cleaned. +*/ + +module te_branch_map #( + parameter N = 1 // max number of committed branches in one cycle +) +( + input logic clk_i, + input logic rst_ni, + + input logic [N-1:0] valid_i, + input logic [N-1:0] branch_taken_i, + input logic flush_i, + + output logic [te_pkg::BRANCH_MAP_LEN-1:0] map_o, + output logic [te_pkg::BRANCH_COUNT_LEN-1:0] branches_o, + output logic is_full_o, + output logic is_empty_o +); + + + logic [te_pkg::BRANCH_MAP_LEN-1:0] map_d, map_q; + logic [te_pkg::BRANCH_COUNT_LEN-1:0] branch_cnt_d, branch_cnt_q; + + always_comb begin + map_d = map_q; + branch_cnt_d = branch_cnt_q; + + if (flush_i) begin + map_d = '0; + branch_cnt_d = '0; + end + + if (valid_i) begin + if(flush_i) begin + map_d[0] = ~branch_taken_i; + branch_cnt_d = 5'b1; + end else begin + map_d[branch_cnt_q] = ~branch_taken_i ; + branch_cnt_d = branch_cnt_q +1; + end + end + end + + assign map_o = map_d; + assign branches_o = branch_cnt_d; + assign is_full_o = (branch_cnt_d == 31); + assign is_empty_o = (branch_cnt_d == 0); + + + always_ff @(posedge clk_i, negedge rst_ni) begin + if(~rst_ni) begin + map_q <= '0; + branch_cnt_q <= '0; + + end else begin + map_q <= map_d; + branch_cnt_q <= branch_cnt_d; + end + end + +endmodule \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv new file mode 100644 index 00000000000..6d33b7ebc57 --- /dev/null +++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv @@ -0,0 +1,142 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +/* FILTER MODULE */ +/* +it declares instructions qualified or not +*/ + +module te_filter +( + // if trace isn't enabled it doesn't make sense to filter + input logic trace_enable_i, + + /* + The idea is to have all inputs to be filtered in range or match. + To achieve this, the filter requires for each parameter: + - enable + - upper and lower values + - to be matched value + - select between in range or match + - qualified for each mode + + The trace to be qualified according to the filters set it requires + an AND between the qualified of the parameters to filter. + */ + + // parameters to filter + // cause + input logic cause_filter_i, + input logic [te_pkg::XLEN-1:0] upper_cause_i, + input logic [te_pkg::XLEN-1:0] lower_cause_i, + input logic [te_pkg::XLEN-1:0] match_cause_i, + input logic cause_mode_i, + input logic [te_pkg::XLEN-1:0] cause_i, + // tvec + input logic tvec_filter_i, + input logic [te_pkg::XLEN-1:0] upper_tvec_i, + input logic [te_pkg::XLEN-1:0] lower_tvec_i, + input logic [te_pkg::XLEN-1:0] match_tvec_i, + input logic tvec_mode_i, + input logic [te_pkg::XLEN-1:0] tvec_i, + // tval + input logic tval_filter_i, + input logic [te_pkg::XLEN-1:0] upper_tval_i, + input logic [te_pkg::XLEN-1:0] lower_tval_i, + input logic [te_pkg::XLEN-1:0] match_tval_i, + input logic tval_mode_i, + input logic [te_pkg::XLEN-1:0] tval_i, + // priv_lvl + input logic priv_lvl_filter_i, + input logic [te_pkg::PRIV_LEN-1:0] upper_priv_i, + input logic [te_pkg::PRIV_LEN-1:0] lower_priv_i, + input logic [te_pkg::PRIV_LEN-1:0] match_priv_i, + input logic priv_lvl_mode_i, + input logic [te_pkg::PRIV_LEN-1:0] priv_i, + // iaddr (pc) + input logic iaddr_filter_i, + input logic [te_pkg::XLEN-1:0] upper_iaddr_i, + input logic [te_pkg::XLEN-1:0] lower_iaddr_i, + input logic [te_pkg::XLEN-1:0] match_iaddr_i, + input logic iaddr_mode_i, + input logic [te_pkg::XLEN-1:0] iaddr_i, + + output logic nc_qualified_o +); + + // output signals for comparators + // cause + logic cause_in_range; + logic cause_equals; + // tvec + logic tvec_in_range; + logic tvec_equals; + // tval + logic tval_in_range; + logic tval_equals; + // priv_lvl + logic priv_lvl_in_range; + logic priv_lvl_equals; + // iaddr (pc) + logic iaddr_in_range; + logic iaddr_equals; + + // assignments + // cause + assign cause_in_range = cause_mode_i == te_pkg::RANGE_MODE && + cause_i <= upper_cause_i && + cause_i >= lower_cause_i; + assign cause_equals = cause_mode_i == te_pkg::EQUAL_MODE && + cause_i == match_cause_i; + // tvec + assign tvec_in_range = tvec_mode_i == te_pkg::RANGE_MODE && + tvec_i <= upper_tvec_i && + tvec_i >= lower_tvec_i; + assign tvec_equals = tvec_mode_i == te_pkg::EQUAL_MODE && + tvec_i == match_tvec_i; + // tval + assign tval_in_range = tval_mode_i == te_pkg::RANGE_MODE && + tval_i <= upper_tval_i && + tval_i >= lower_tval_i; + assign tval_equals = tval_mode_i == te_pkg::EQUAL_MODE && + tval_i == match_tval_i; + // priv_lvl + assign priv_lvl_in_range = priv_lvl_mode_i == te_pkg::RANGE_MODE && + priv_i <= upper_priv_i && + priv_i >= lower_priv_i; + assign priv_lvl_equals = priv_lvl_mode_i == te_pkg::EQUAL_MODE && + priv_i == match_priv_i; + // iaddr + assign iaddr_in_range = iaddr_mode_i == te_pkg::RANGE_MODE && + iaddr_i <= upper_iaddr_i && + iaddr_i >= lower_iaddr_i; + assign iaddr_equals = iaddr_mode_i == te_pkg::EQUAL_MODE && + iaddr_i == match_iaddr_i; + + // assigning output + // if no filter is enabled -> the instruction is qualified + assign nc_qualified_o = ((cause_filter_i && (cause_in_range || cause_equals)) || + ~cause_filter_i) && // cause + ((tvec_filter_i && (tvec_in_range || tvec_equals)) || + ~tvec_filter_i) && // tvec + ((tval_filter_i && (tval_in_range || tval_equals)) || + ~tval_filter_i) && // tval + ((priv_lvl_filter_i && (priv_lvl_in_range || priv_lvl_equals)) || + ~priv_lvl_filter_i) && // priv_lvl + ((iaddr_filter_i && (iaddr_in_range || iaddr_equals)) || + ~iaddr_filter_i) && // iaddr + trace_enable_i; + +endmodule \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv new file mode 100644 index 00000000000..5dd0d9e7893 --- /dev/null +++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv @@ -0,0 +1,1095 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +/* PACKET EMITTER */ +/* +it produces the packets for the output interface +*/ + +module te_packet_emitter +( + input logic clk_i, + input logic rst_ni, + input logic valid_i, + + // necessary info to assemble packet + input te_pkg::format_e packet_format_i, + input te_pkg::f_sync_subformat_e packet_f_sync_subformat_i, // SF for F3 + //input f_opt_ext_subformat_e packet_f_opt_ext_subformat_i, // non mandatory, SF for F0 + + // lc (last cycle) signals + input logic [te_pkg::XLEN-1:0] lc_cause_i, + input logic [te_pkg::XLEN-1:0] lc_tval_i, + input logic lc_interrupt_i, + + // tc (this cycle) signals + input logic [te_pkg::XLEN-1:0] tc_cause_i, + input logic [te_pkg::XLEN-1:0] tc_tval_i, + input logic tc_interrupt_i, + input logic tc_resync_i, + + input logic nc_exc_only_i, + input logic nc_ppccd_br_i, + + // nc (next cycle) signals + + /* the following signals used to determine + if the packet emitter has to put context + and/or time in the payload*/ + input logic nocontext_i, // both read from registers + input logic notime_i, + // in this implementation both hardwired to 0 + + // format 3 subformat 0 specific signals + input logic tc_branch_i, + input logic tc_branch_taken_i, + input logic [te_pkg::PRIV_LEN-1:0] tc_priv_i, + input logic [te_pkg::TIME_LEN-1:0] tc_time_i, // optional + //input logic [:0] context_i, // optional + input logic [te_pkg::XLEN-1:0] tc_address_i, + + // format 3 subformat 1 specific signals + input logic lc_tc_mux_i, + /* format 3 subformat 1 packets require sometimes lc_cause o tc_cause + To discriminate I use a mux to choose between lc or tc */ + + input logic thaddr_i, + input logic [te_pkg::XLEN-1:0] tc_tvec_i, // trap handler address + input logic [te_pkg::XLEN-1:0] lc_epc_i, + + // format 3 subformat 3 specific signals + input logic tc_ienable_i, // trace encoder enabled + input logic encoder_mode_i, // only branch trace supported (value==0) + input te_pkg::qual_status_e qual_status_i, + input te_pkg::ioptions_s ioptions_i, + // about DATA trace, in stand-by at the moment + //input logic denable_i, // DATA trace enabled, if supported + //input logic dloss_i, // one or more DATA trace packets lost, if supported + //input logic [:0] doptions_i, // it's like ioptions, but for DATA trace + + + // format 2 specific signals + /* notify -> means the packet was requested by the cpu trigger unit*/ + //input logic notify_i, // non mandatory + + // most of the time these 2 values can be compressed + input logic lc_updiscon_i, + + // necessary if implicit_return mode is enabled + //input logic irreport_i, + + //input logic [2**te_pkg::CALL_COUNTER_SIZE-1:0] irdepth_i, // non mandatory, traces nested calls + + // format 1 specific signals + /* this format exists in two modes: + - address, branch map + - NO address, branch maps + + Their generation depends on the value of branches: + - 0: no need for address + - >0: address required + */ + input logic [te_pkg::BRANCH_COUNT_LEN-1:0] branches_i, + input logic [te_pkg::BRANCH_MAP_LEN-1:0] branch_map_i, // can change size to improve efficiency + + // format 0 specific signals + /* This format can have two possible subformats: + - subformat 0: number of correctly predicted branches + - subformat 1: jump target cache index + + Non mandatory, required support by the encoder. + */ + input logic [$clog2(te_pkg::XLEN):0] keep_bits_i, // required for address compression + input logic shallow_trace_i, // used to flush branch map at each packet + + // outputs + output logic packet_valid_o, // asserted when a packet is generated + output te_pkg::it_packet_type_e packet_type_o, + output logic [te_pkg::PAYLOAD_LEN-1:0] packet_payload_o, + output logic [te_pkg::P_LEN-1:0] payload_length_o, // in bytes + output logic branch_map_flush_o, // flushing done after each request + // to send back to priority module in order to compress them + output logic [te_pkg::XLEN-1:0] addr_to_compress_o +); + + // internal signals + logic branch; + logic interrupt; + logic [te_pkg::XLEN-1:0] address; + logic [te_pkg::XLEN-1:0] ecause; + logic [te_pkg::XLEN-1:0] diff_addr; + logic [te_pkg::XLEN-1:0] latest_addr_d, latest_addr_q; // address of the latest packet emitted + logic [te_pkg::XLEN-1:0] tval; + logic [1:0] time_and_context; // if payload requires time/context + logic notify; + logic updiscon; + logic irreport; + logic [2**te_pkg::CALL_COUNTER_SIZE-1:0] irdepth; + logic [4:0] branch_map_off; + logic [3:0] address_off; + logic [8:0] used_bits; // counts the bits used inside each payload + logic flush_d, flush_q; + logic update_latest_addr; + logic resync_d, resync_q; + logic [te_pkg::XLEN-1:0] resync_addr_d, resync_addr_q; + + // assigning values + assign branch = ~(tc_branch_i && tc_branch_taken_i); + assign address = thaddr_i ? tc_tvec_i : lc_epc_i; + assign ecause = lc_tc_mux_i ? tc_cause_i : lc_cause_i; + assign tval = lc_tc_mux_i ? tc_tval_i : lc_tval_i; + assign interrupt = lc_tc_mux_i ? tc_interrupt_i : lc_interrupt_i; + assign time_and_context = {~notime_i, ~nocontext_i}; + assign branch_map_flush_o = flush_q; + assign payload_length_o = (used_bits + 7) >> 3; + + always_comb begin + // init + resync_d = resync_q; + resync_addr_d = resync_addr_q; + + // updates resync signal + if (tc_resync_i) begin + resync_d = '1; + resync_addr_d = tc_address_i; + end + + // synchronous reset of resync signal + if (packet_type_o == te_pkg::F3SF0 && resync_q) begin + resync_d = '0; + end + end + + + // register to store the last address emitted in a packet + always_ff @(posedge clk_i, negedge rst_ni) begin + if(~rst_ni) begin + latest_addr_q <= '0; + flush_q <= '0; + resync_q <= '0; + resync_addr_q <= '0; + end else begin + latest_addr_q <= latest_addr_d; + resync_q <= resync_d; + resync_addr_q <= resync_addr_d; + flush_q <= flush_d; + end + end + + // combinatorial network to compute the offset to compress the branch_map + always_comb begin : branch_map_offset + if(branches_i == 1) begin + branch_map_off = 1; + end else if(branches_i <= 3) begin + branch_map_off = 3; + end else if(branches_i <= 7) begin + branch_map_off = 7; + end else if(branches_i <= 15) begin + branch_map_off = 15; + end else if (branches_i < 31) begin + branch_map_off = 31; + end else begin + branch_map_off = '0; + end + + end + + /* + the address compression works in byte chunks: based on the value of + keep_bits_i, the number of least significant bytes to keep is determined. + + example: + keep_bits_i == 7 -> 1 lsB kept 0111 + keep_bits_i == 10 -> 2 lsB kept 1010 + keep_bits_i == 25 -> 4 lsB kept 11001 + */ + // 33 = 100001 + 7 = 101000 >>3 = 0101 = 5 + + // find the number of least significant bytes to keep in the compressed address + assign address_off = (keep_bits_i + 7)>>3; + + // combinatorial network to output packets + always_comb begin + // init values + packet_payload_o = '0; + packet_valid_o = '0; + flush_d = '0; + used_bits = '0; + packet_type_o = te_pkg::F0SF0; + update_latest_addr = '0; + + if(valid_i) begin + /* branch_map_flush_o + the signal is output in this cycle, but the branch map does + the flush in the next cycle to leave time to the packet + emitter to read values and put them in the payload + */ + // flushes at each packet emitted to get a less precise tracing + flush_d = shallow_trace_i; + + // setting the packet to emit as valid + packet_valid_o = '1; + + /* packet payload creation: + at the beginning it's put in the payload the common part (i.e. the packet format) + then, for each format and subformat it's put the rest of the payload + */ + + // setting the packet format - common for all payloads + packet_payload_o[1:0] = packet_format_i; + + // format bits + used_bits += 2; + + case(packet_format_i) + te_pkg::F_SYNC: begin // format 3 + // setting packet subformat - common for all type 3 payloads + packet_payload_o[3:2] = packet_f_sync_subformat_i; + + used_bits += 2; // subformat bits + + // setting the rest of payload for each type + case(packet_f_sync_subformat_i) + te_pkg::SF_START: begin // subformat 0 + // updating packet type + packet_type_o = te_pkg::F3SF0; + update_latest_addr = '1; + + case(time_and_context) + 2'b00: begin + used_bits += 1 + (address_off * 8) + te_pkg::PRIV_LEN; + + packet_payload_o[4+:1+te_pkg::PRIV_LEN] = { + tc_priv_i, + branch + }; + // address compression + case (address_off) + 1: begin + packet_payload_o[5+te_pkg::PRIV_LEN+:8] = { + addr_to_compress_o[7:0] + }; + end + 2: begin + packet_payload_o[5+te_pkg::PRIV_LEN+:16] = { + addr_to_compress_o[15:0] + }; + end + 3: begin + packet_payload_o[5+te_pkg::PRIV_LEN+:24] = { + addr_to_compress_o[23:0] + }; + end + 4: begin + packet_payload_o[5+te_pkg::PRIV_LEN+:32] = { + addr_to_compress_o[31:0] + }; + end + `ifdef TE_ARCH64 // 64bits case + 5: begin + packet_payload_o[5+te_pkg::PRIV_LEN+:40] = { + addr_to_compress_o[39:0] + }; + end + 6: begin + packet_payload_o[5+te_pkg::PRIV_LEN+:48] = { + addr_to_compress_o[47:0] + }; + end + 7: begin + packet_payload_o[5+te_pkg::PRIV_LEN+:56] = { + addr_to_compress_o[55:0] + }; + end + 8: begin + packet_payload_o[5+te_pkg::PRIV_LEN+:64] = { + addr_to_compress_o + }; + end + `endif + endcase + end + + 2'b10: begin + used_bits += 1 + te_pkg::PRIV_LEN + te_pkg::TIME_LEN + (address_off * 8); + + packet_payload_o[4+:1+te_pkg::PRIV_LEN+te_pkg::TIME_LEN] = { + tc_time_i, + tc_priv_i, + branch + }; + // address compression + // FIXME(MAX): simplify case with: + // for (int unsigned i = 1; i <= 8; i++) begin + // if (i == address_off) begin + // packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:i*8] = { + // addr_to_compress_o[i*8-1:0] + // }; + // end + // end + case (address_off) + 1: begin + packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:8] = { + addr_to_compress_o[7:0] + }; + end + 2: begin + packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:16] = { + addr_to_compress_o[15:0] + }; + end + 3: begin + packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:24] = { + addr_to_compress_o[23:0] + }; + end + 4: begin + packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:32] = { + addr_to_compress_o[31:0] + }; + end + `ifdef TE_ARCH64 // 64bits case + 5: begin + packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:40] = { + addr_to_compress_o[39:0] + }; + end + 6: begin + packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:48] = { + addr_to_compress_o[47:0] + }; + end + 7: begin + packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:56] = { + addr_to_compress_o[55:0] + }; + end + 8: begin + packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:64] = { + addr_to_compress_o + }; + end + `endif + endcase + end + /*TODO: other cases*/ + endcase + end + te_pkg::SF_TRAP: begin // subformat 1 + // updating packet type + packet_type_o = te_pkg::F3SF1; + update_latest_addr = '1; + + case(time_and_context) + 2'b00: begin + used_bits += 1 + te_pkg::PRIV_LEN + te_pkg::XLEN + 2 + (address_off * 8) + te_pkg::XLEN; // last XLEN is for tval + + packet_payload_o[4+:1+te_pkg::PRIV_LEN+te_pkg::XLEN+2] = { + thaddr_i, + interrupt, + ecause, + tc_priv_i, + branch + }; + // address compression //FIXME Why tval is with addr_to_compress ? and not before ??? + case (address_off) + 1: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:8+te_pkg::XLEN] = { + addr_to_compress_o[7:0], + tval + + }; + end + 2: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:16+te_pkg::XLEN] = { + addr_to_compress_o[15:0], + tval + }; + end + 3: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:24+te_pkg::XLEN] = { + addr_to_compress_o[23:0], + tval + }; + end + 4: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:32+te_pkg::XLEN] = { + addr_to_compress_o[31:0], + tval + }; + end + `ifdef TE_ARCH64 // 64bits case + 5: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:40+te_pkg::XLEN] = { + addr_to_compress_o[39:0], + tval + }; + end + 6: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:48+te_pkg::XLEN] = { + addr_to_compress_o[47:0], + tval + }; + end + 7: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:56+te_pkg::XLEN] = { + addr_to_compress_o[55:0], + tval + }; + end + 8: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:64+te_pkg::XLEN] = { + addr_to_compress_o, + tval + }; + end + `endif + endcase + end + + 2'b10: begin + used_bits += 1 + te_pkg::PRIV_LEN + te_pkg::XLEN + 2 + (address_off * 8) + te_pkg::TIME_LEN + te_pkg::XLEN ; // why time_len *2 , time = 64 bits ? + + packet_payload_o[4+:1+te_pkg::PRIV_LEN+te_pkg::XLEN+2+te_pkg::TIME_LEN] = { + thaddr_i, + interrupt, + ecause, + tc_time_i, + tc_priv_i, + branch + }; + // address compression + case (address_off) + 1: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:8+te_pkg::XLEN] = { // FIXME Replace XLEN by TIME_LEN every time ? + addr_to_compress_o[7:0], + tval + + }; + end + 2: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:16+te_pkg::XLEN] = { + addr_to_compress_o[15:0], + tval + }; + end + 3: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:24+te_pkg::XLEN] = { + addr_to_compress_o[23:0], + tval + }; + end + 4: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:32+te_pkg::XLEN] = { + addr_to_compress_o[31:0], + tval + }; + end + `ifdef TE_ARCH64 // 64bits case + 5: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:40+te_pkg::XLEN] = { + addr_to_compress_o[39:0], + tval + }; + end + 6: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:48+te_pkg::XLEN] = { + addr_to_compress_o[47:0], + tval + }; + end + 7: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:56+te_pkg::XLEN] = { + addr_to_compress_o[55:0], + tval + }; + end + 8: begin + packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:64+te_pkg::XLEN] = { + addr_to_compress_o, + tval + }; + end + `endif + endcase + end + /*TODO: other cases*/ + endcase + end + te_pkg::SF_CONTEXT: begin // subformat 2 + // updating packet type + packet_type_o = te_pkg::F3SF2; + + case(time_and_context) + 2'b00: begin + used_bits += te_pkg::PRIV_LEN; + + packet_payload_o[4+:te_pkg::PRIV_LEN] = { + tc_priv_i + }; + end + + 2'b10: begin + used_bits += te_pkg::PRIV_LEN + te_pkg::TIME_LEN; + + packet_payload_o[4+:te_pkg::PRIV_LEN+te_pkg::TIME_LEN] = { + tc_time_i, + tc_priv_i + }; + end + /*TODO: other cases*/ + endcase + end + te_pkg::SF_SUPPORT: begin // subformat 3 + // updating packet type + packet_type_o = te_pkg::F3SF3; + + used_bits += 11; + + packet_payload_o[4+:1+1+2+7] = { + /* info required for data tracing - in the future + doptions_i, + dloss_i, + denable_i, */ + ioptions_i, + qual_status_i, + encoder_mode_i, + tc_ienable_i + }; + end + endcase + end + + te_pkg::F_ADDR_ONLY: begin // format 2 + // updating packet type + packet_type_o = te_pkg::F2; + update_latest_addr = '1; + + // requires trigger unit in CPU + /* + if(notify_i) begin // request from trigger unit + notify = !tc_address_i[XLEN-1]; + updiscon = notify; + irreport = updsicon; + irdepth = irdepth_i; + end else begin*/ + + // case of an updiscon + if(lc_updiscon_i && (nc_exc_only_i || nc_ppccd_br_i)) begin //FIXME spec says lc_updiscon AND nc_execption/interrupt /priv change / resync <= need to add nc_resync + notify = tc_address_i[te_pkg::XLEN-1]; + updiscon = !notify; + irreport = updiscon; + irdepth = {2**te_pkg::CALL_COUNTER_SIZE{updiscon}}; + /* non mandatory + end else if(implicit_mode_i && irreport_i) begin // request for implicit return mode + notify = tc_address_i[XLEN-1]; + updiscon = notify; + irreport = !updiscon; + irdepth = irdepth_i; + */ + end else begin //other cases + notify = tc_address_i[te_pkg::XLEN-1]; + updiscon = notify; + irreport = updiscon; + irdepth = {2**te_pkg::CALL_COUNTER_SIZE{updiscon}}; + end + + // checking if implicit return is supported + if (te_pkg::CALL_COUNTER_SIZE == 0 && + te_pkg::RETURN_STACK_SIZE == 0) begin // not supported + + // payload bits + used_bits += 3 + address_off*8 ; + + // address compression + case (address_off) + 1: begin + packet_payload_o[2+:8+3] = { + addr_to_compress_o[7:0], + irreport, + updiscon, + notify + }; + end + 2: begin + packet_payload_o[2+:16+3] = { + addr_to_compress_o[15:0], + irreport, + updiscon, + notify + }; + end + 3: begin + packet_payload_o[2+:24+3] = { + addr_to_compress_o[23:0], + irreport, + updiscon, + notify + }; + end + 4: begin + packet_payload_o[2+:32+3] = { + addr_to_compress_o[31:0], + irreport, + updiscon, + notify + }; + end + `ifdef TE_ARCH64 // 64bits case + 5: begin + packet_payload_o[2+:40+3] = { + addr_to_compress_o[39:0], + irreport, + updiscon, + notify + }; + end + 6: begin + packet_payload_o[2+:48+3] = { + addr_to_compress_o[47:0], + irreport, + updiscon, + notify + }; + end + 7: begin + packet_payload_o[2+:56+3] = { + addr_to_compress_o[55:0], + irreport, + updiscon, + notify + }; + end + 8: begin + packet_payload_o[2+:64+3] = { + addr_to_compress_o, + irreport, + updiscon, + notify + }; + end + `endif + endcase + + end else begin // supported + // payload bits + used_bits += 3 + 2**te_pkg::CALL_COUNTER_SIZE + address_off*8 ; + + // address compression + case (address_off) + 1: begin + packet_payload_o[2+:8+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[7:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 2: begin + packet_payload_o[2+:16+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[15:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 3: begin + packet_payload_o[2+:24+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[23:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 4: begin + packet_payload_o[2+:32+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[31:0], + irdepth, + irreport, + updiscon, + notify + }; + end + `ifdef TE_ARCH64 // 64bits case + 5: begin + packet_payload_o[2+:40+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[39:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 6: begin + packet_payload_o[2+:48+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[47:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 7: begin + packet_payload_o[2+:56+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[55:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 8: begin + packet_payload_o[2+:64+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o, + irdepth, + irreport, + updiscon, + notify + }; + end + `endif + endcase + end + end + + te_pkg::F_DIFF_DELTA: begin // format 1 + /* There can be two type of payloads for this format: + 1. address, branch map + 2. no address, branch map + + Type 1 payload is used when there has been at least + one branch from last packet. This can be determined + by the number of branches in the branch map. + + Type 2 payload is used when the address is not needed, + for examples if the branch map is full. + */ + // flushing the branch_map + flush_d = '1; + // updating packet type + packet_type_o = te_pkg::F1; + + // requires trigger unit in CPU + /* + if(notify_i) begin // request from trigger unit + notify = !tc_address_i[XLEN-1]; + updiscon = notify; + irreport = updsicon; + irdepth = irdepth_i; + end else begin*/ + + // case of an updiscon + if(lc_updiscon_i && (nc_exc_only_i || nc_ppccd_br_i)) begin //FIXME spec says lc_updiscon AND nc_execption/interrupt /priv change / resync <= need to add nc_resync + notify = tc_address_i[te_pkg::XLEN-1]; + updiscon = !notify; + irreport = updiscon; + irdepth = {2**te_pkg::CALL_COUNTER_SIZE{updiscon}}; + /* non mandatory + end else if(implicit_return_i && irreport_i) begin // request for implicit return mode + notify = tc_address_i[XLEN-1]; + updiscon = notify; + irreport = !updiscon; + irdepth = irdepth_i; + */ + end else begin // other cases + notify = tc_address_i[te_pkg::XLEN-1]; + updiscon = notify; + irreport = updiscon; + irdepth = {2**te_pkg::CALL_COUNTER_SIZE{updiscon}}; + end + + // branches and branch_map bits + used_bits += (branch_map_off==0)? te_pkg::BRANCH_COUNT_LEN + 32 : te_pkg::BRANCH_COUNT_LEN + branch_map_off; + + // adding branch count and branch map + if (branch_map_off == 1) begin + packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+1] = { + branch_map_i[0], + branches_i + }; + end else if (branch_map_off == 3) begin + packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+3] = { + branch_map_i[2:0], + branches_i + }; + end else if (branch_map_off == 7) begin + packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+7] = { + branch_map_i[6:0], + branches_i + }; + end else if (branch_map_off == 15) begin + packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+15] = { + branch_map_i[14:0], + branches_i + }; + end else if (branch_map_off == 31) begin + packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+31] = { + branch_map_i[30:0], + branches_i + }; + end else begin //FIXME if we have discontinuity branches =31 not 0 + packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+31] = { + branch_map_i[30:0], + 5'b00000 + }; + end + + // attaching the rest of the payload + if(branches_i < 31) begin // branch map not full - address + update_latest_addr = '1; + // checking if implicit return is supported + if (te_pkg::CALL_COUNTER_SIZE == 0 && + te_pkg::RETURN_STACK_SIZE == 0) begin // not supported + // rest of the payload bits + used_bits += 3 + address_off*8 ; + + // address compression + case (address_off) + 1: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:8+3] = { + addr_to_compress_o[7:0], + irreport, + updiscon, + notify + }; + end + 2: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:16+3] = { + addr_to_compress_o[15:0], + irreport, + updiscon, + notify + }; + end + 3: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:24+3] = { + addr_to_compress_o[23:0], + irreport, + updiscon, + notify + }; + end + 4: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:32+3] = { + addr_to_compress_o[31:0], + irreport, + updiscon, + notify + }; + end + `ifdef TE_ARCH64 // 64bits case + 5: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:40+3] = { + addr_to_compress_o[39:0], + irreport, + updiscon, + notify + }; + end + 6: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:48+3] = { + addr_to_compress_o[47:0], + irreport, + updiscon, + notify + }; + end + 7: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:56+3] = { + addr_to_compress_o[55:0], + irreport, + updiscon, + notify + }; + end + 8: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:64+3] = { + addr_to_compress_o, + irreport, + updiscon, + notify + }; + end + `endif + endcase + + end else begin // supported -> uses irdepth and irreport + // rest of the payload bits + used_bits += 3 + 2**te_pkg::CALL_COUNTER_SIZE + address_off*8 ; + + // address compression + case (address_off) + 1: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:8+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[7:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 2: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:16+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[15:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 3: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:24+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[23:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 4: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:32+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[31:0], + irdepth, + irreport, + updiscon, + notify + }; + end + `ifdef TE_ARCH64 // 64bits case + 5: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:40+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[39:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 6: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:48+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[47:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 7: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:56+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o[55:0], + irdepth, + irreport, + updiscon, + notify + }; + end + 8: begin + packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:64+3+2**te_pkg::CALL_COUNTER_SIZE] = { + addr_to_compress_o, + irdepth, + irreport, + updiscon, + notify + }; + end + `endif + endcase + end + end + end + + //F_OPT_EXT: begin // format 0 // TODO + // requires trigger unit in CPU + /* + if(notify_i) begin // request from trigger unit + notify = !tc_address_i[XLEN-1]; + updiscon = notify; + irreport = updsicon; + irdepth = irdepth_i; + end else begin + notify = tc_address_i[XLEN-1]; + updiscon = notify; + irreport = updiscon; + irdepth = {2**CALL_COUNTER_SIZE{updiscon}}; + end */ + + /* requires non mandatory support for jtc and branch prediction + case(packet_f_opt_ext_subformat_i) + SF_PBC: begin // subformat 0 + // There can be two type of payloads for this subformat: + // 1. no address, branch count + // 2. address, branch count + + // only for F0SF0 payload w/address + // updating latest address sent in a packet + + packet_payload_o = {F_OPT_EXT, SF_PBC, etc..}; + packet_valid_o = '1; + end + + SF_JTC: begin // subformat 1 + packet_payload_o = {F_OPT_EXT, SF_JTC, etc..}; + packet_valid_o = '1; + end + endcase + */ + //end + endcase + end + end + + always_comb begin : address_to_compress + diff_addr = '0; + addr_to_compress_o = '0; + latest_addr_d = latest_addr_q; + + // determines differential address for F1, F2 + if (packet_valid_o && (packet_format_i == te_pkg::F_DIFF_DELTA || + packet_format_i == te_pkg::F_ADDR_ONLY)) begin + if (ioptions_i.delta_address_en) begin + diff_addr = latest_addr_q - tc_address_i; // mostly >0 exept for jump , remove signed + addr_to_compress_o = diff_addr; + end else if (ioptions_i.full_address_en) begin + addr_to_compress_o = tc_address_i; + end + end + + // determines latest address + if (packet_valid_o && update_latest_addr) begin + if (packet_type_o == te_pkg::F1 || + packet_type_o == te_pkg::F2) begin // F1, F2 + latest_addr_d = tc_address_i; + addr_to_compress_o = tc_address_i; + end + if (packet_type_o == te_pkg::F3SF0) begin // F3SF0 + if (resync_q) begin //FIXME WHY ? + latest_addr_d = tc_address_i; + addr_to_compress_o = tc_address_i; + end else begin + latest_addr_d = tc_address_i; + addr_to_compress_o = tc_address_i; + end + end + if (packet_type_o == te_pkg::F3SF1) begin // F3SF1 + latest_addr_d = address; + addr_to_compress_o = address; + end + end + end + +endmodule diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv new file mode 100644 index 00000000000..9fd6db48af5 --- /dev/null +++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv @@ -0,0 +1,405 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +/*PRIORITY*/ +/* +change this module name to a more appropriate one +for example "packet identifier" or something similar +*/ +/* +it orders packet generation - refer to page 53 of the spec +*/ + +module te_priority ( + + input logic clk_i, + input logic rst_ni, + + input logic valid_i, + + /* signals for the jump target cache mode - non mandatory */ + //input logic jtc_enabled_i, + //input logic address_in_cache_i, // communicates if the address is present in cache + + // lc (last cycle) signals + input logic lc_exception_i, + input logic lc_updiscon_i, // updsicon == uninferable PC discontinuity + + // tc (this cycle) signals + input logic tc_qualified_i, + input logic tc_exception_i, + input logic [te_pkg::IRETIRE_LEN-1:0] tc_retired_i, + input logic tc_first_qualified_i, + input logic tc_privchange_i, + //input logic tc_context_change_i, // non mandatory + //input logic tc_precise_context_report_i, // requires ctype signal CPU side + //input logic tc_context_report_as_disc_i, // ibidem + //input logic tc_imprecise_context_report_i, // ibidem + input logic tc_gt_max_resync_i, // greater than timeout + input logic tc_et_max_resync_i, // one step to timeout + input logic tc_branch_map_empty_i, + input logic tc_branch_map_full_i, + //input logic tc_branch_misprediction_i, // non mandatory + //input logic tc_pbc_i, // correctly predicted branch count, non mandatory + + // format 3 subformat 3 - NOT shown in graph + input logic tc_enc_enabled_i, + input logic tc_enc_disabled_i, + input logic tc_opmode_change_i, + input logic tc_final_qualified_i, + input logic tc_packets_lost_i, // non mandatory + + // nc (next cycle) signals + input logic nc_exception_i, + input logic nc_privchange_i, + //input logic nc_context_change_i, // non mandatory + //input logic nc_precise_context_report_i, // requires ctype signal CPU side + //input logic nc_context_report_as_disc_i, // ibidem + input logic nc_branch_map_empty_i, + input logic nc_qualified_i, + input logic [te_pkg::IRETIRE_LEN-1:0] nc_retired_i, // used w/nc_exception for signal nc_exc_only + + // non mandatory sideband signals + // refer to page 52 of the spec + //input logic halted_i, + //input logic reset_i, + + // inputs for irreport and irdepth, non mandatory + //input logic implicit_return_i, // tells if the mode is enabled + //input logic [:0] call_counter_size_i, // size of nested calls counter, 2^value + //input logic [:0] return_stack_size_i, // size of nested calls stack, 2^value + + // trigger unit request ports, must be supported by the CPU + //input logic tc_trigger_req_i, + //output logic notify_o, + // communicates the packet emitter that format 2 packet was requested by trigger unit + + // input to compress + input logic [te_pkg::XLEN-1:0] addr_to_compress_i, + + // outputs for packet_emitter + output logic valid_o, + output te_pkg::format_e packet_format_o, + output te_pkg::f_sync_subformat_e packet_f_sync_subformat_o, + //output te_pkg::f_opt_ext_subformat_e packet_f_opt_ext_subformat_o, // non mandatory, used for jtc and branch prediction + output logic thaddr_o, // required for f3 sf1 packet payload + output logic lc_tc_mux_o, // operates the MUX to choose between lc or tc cause, tval, interrupt: 0 -> lc, 1 + output logic resync_timer_rst_o, // resets counter + output te_pkg::qual_status_e qual_status_o, + //output logic irreport_o, // non mandatory, required implicit return mode + output logic tc_resync_o, + output logic nc_exc_only_o, + output logic nc_ppccd_br_o, + // output for compression + output logic [$clog2(te_pkg::XLEN):0] keep_bits_o + ); + + + /* internal signals required for packet determination */ + // last cycle + logic lc_ended_ntr_d, lc_ended_ntr_q; + logic lc_ended_rep_d, lc_ended_rep_q; + // this cycle + logic tc_exc_only; // for a precise definition: page 51 of the spec + logic tc_ppccd; // ibidem + logic tc_resync_br; // ibidem + logic tc_er_n; // ibidem + logic tc_rpt_br; // ibidem + //logic tc_cci; // ibidem + logic tc_reported_d, tc_reported_q; // ibidem + logic reported_status; + logic reported_update; // determines when reported_q updates + // reported is updated when the lc_exception was updated or not + logic tc_f3_sf3; + // next cycle + + // signals for compression + logic [$clog2(te_pkg::XLEN)-1:0] addr_zeros, addr_ones; + logic [$clog2(te_pkg::XLEN)-1:0] sign_extendable; + logic empty_zeros; + logic empty_ones; + + // signals to store + logic tc_resync_br_d, tc_resync_br_q; + + // value assignment + assign tc_exc_only = tc_exception_i && tc_retired_i == 0; + assign tc_ppccd = tc_privchange_i /*|| (tc_context_change_i && + (tc_precise_context_report_i || + tc_context_report_as_disc_i))*/; + assign tc_resync_br = tc_et_max_resync_i && ~tc_branch_map_empty_i; + assign tc_er_n = (tc_exception_i && tc_retired_i != 0) /*|| tc_trigger_req_i*/; + assign tc_rpt_br = tc_branch_map_full_i && !nc_branch_map_empty_i/* || tc_branch_misprediction_i*/; + //assign tc_cci = tc_context_change_i && tc_imprecise_context_report_i; + assign nc_exc_only_o = nc_exception_i && nc_retired_i == 0; + assign nc_ppccd_br_o = (nc_privchange_i /*|| (nc_context_change_i && + (nc_precise_context_report_i || nc_context_report_as_disc_i))*/) && + ~nc_branch_map_empty_i; + assign tc_f3_sf3 = tc_enc_enabled_i || tc_enc_disabled_i || tc_opmode_change_i || + tc_final_qualified_i || tc_packets_lost_i; + assign reported_update = ( packet_format_o == te_pkg::F_SYNC && + packet_f_sync_subformat_o == te_pkg::SF_TRAP && + ~thaddr_o) || + ( packet_format_o == te_pkg::F_SYNC && + packet_f_sync_subformat_o == te_pkg::SF_START && + ~tc_exc_only); + assign tc_resync_o = valid_i && tc_resync_br_q; + + always_comb begin + // init + tc_resync_br_d = tc_resync_br_q; + + if (reported_update) begin + tc_reported_d = reported_status; + end + + if (tc_resync_br) begin + tc_resync_br_d = '1; + end + + if (valid_o && + (packet_format_o == te_pkg::F_DIFF_DELTA || + packet_format_o == te_pkg::F_ADDR_ONLY)) begin + tc_resync_br_d = '0; + end + end + + /* + The reset value is 0, the spec doesn't say how to behave. + The 0 value specifies an exception w/out retired instr + in this cycle and an exception in the previous cycle. + */ + always_ff @( posedge clk_i, negedge rst_ni ) begin + if(~rst_ni) begin + tc_reported_q <= '0; + lc_ended_ntr_q <= '0; + lc_ended_rep_q <= '0; + tc_resync_br_q <= '0; + end else begin + tc_reported_q <= tc_reported_d; + tc_resync_br_q <= tc_resync_br_d; + lc_ended_ntr_q <= lc_ended_ntr_d; + lc_ended_rep_q <= lc_ended_rep_d; + end + end + + /*TODO: add condition to determine if F2, F1, F0SF0 are requested by the trigger unit*/ + + /* combinatorial network to determine packet format */ + // refer to flowchart at page 53 of the spec + always_comb begin : select_packet_format + // default init values + valid_o = '0; + packet_format_o = te_pkg::F_OPT_EXT; + packet_f_sync_subformat_o = te_pkg::SF_START; + //packet_f_opt_ext_subformat_o = SF_PBC; + //notify_o = '0; + thaddr_o = '0; + lc_tc_mux_o = '0; + resync_timer_rst_o = '0; + reported_status = '0; + qual_status_o = te_pkg::NO_CHANGE; + lc_ended_ntr_d = '0; + lc_ended_rep_d = '0; + + if(valid_i) begin + // format 3 subformat 3 packet generation + /* this if is not in the flowchart, but it's only described. + To me it made more sense to have it as the first if. */ + if(tc_f3_sf3) begin + packet_format_o = te_pkg::F_SYNC; + packet_f_sync_subformat_o = te_pkg::SF_SUPPORT; + // if-then-else to determine qual_status value for payload + if(lc_ended_ntr_q == '1) begin + qual_status_o = te_pkg::ENDED_NTR; + end else if(lc_ended_rep_q == '1) begin + qual_status_o = te_pkg::ENDED_REP; + end else if(tc_packets_lost_i == '1) begin + qual_status_o = te_pkg::TRACE_LOST; + end + valid_o = '1; + /* TODO: if for halted and reset sideband signals, + if at least one asserted -> considers unqualified*/ + end else if(tc_qualified_i) begin + if(lc_exception_i) begin + if(tc_exc_only) begin + packet_format_o = te_pkg::F_SYNC; + packet_f_sync_subformat_o = te_pkg::SF_TRAP; + resync_timer_rst_o = '1; + lc_tc_mux_o = 0; + reported_status = '1; + thaddr_o = '0; + /* thaddr_d = 0; resync_cnt = 0 + cause = lc_cause_i; tval = lc_tval*/ + valid_o = '1; + end else if(tc_reported_q) begin + packet_format_o = te_pkg::F_SYNC; + packet_f_sync_subformat_o = te_pkg::SF_START; + resync_timer_rst_o = '1; + //reported_d = '0; // not necessary + // resync_cnt = 0 + valid_o = '1; + end else begin // not reported + packet_format_o = te_pkg::F_SYNC; + packet_f_sync_subformat_o = te_pkg::SF_TRAP; + resync_timer_rst_o = '1; + lc_tc_mux_o = '0; + thaddr_o = '1; + /*thaddr_d = 1; resync_cnt = 0 + cause = lc_cause_i; tval = lc_tval */ + valid_o = '1; + end + end else if(tc_first_qualified_i || tc_ppccd || (tc_gt_max_resync_i && !tc_resync_br_q)) begin + packet_format_o = te_pkg::F_SYNC; + packet_f_sync_subformat_o = te_pkg::SF_START; + resync_timer_rst_o = '1; + //resync_cnt = 0 + valid_o = '1; + end else if(lc_updiscon_i) begin + // packet generated due to updiscon + lc_ended_ntr_d = '1; + if(tc_exc_only) begin + packet_format_o = te_pkg::F_SYNC; + packet_f_sync_subformat_o = te_pkg::SF_TRAP; + thaddr_o = '0; + resync_timer_rst_o = '1; + lc_tc_mux_o = '1; + /* thaddr = 0; resync_cnt = 0 + cause = tc_cause_i; tval = tc_tval */ + valid_o = '1; + end else begin + /* choosing between format 0/1/2 */ + /*if(tc_pbc_i >= 31) begin // format 0 subformat 0 + packet_format_o = F_OPT_EXT; + packet_f_opt_ext_subformat_o = SF_JTC; + // value for payload TBD + end else if(jtc_enabled_i && address_in_cache_i) begin // format 0 subformat 1 + packet_format_o = F_OPT_EXT; + packet_f_opt_ext_subformat_o = SF_JTC; + // value for payload TBD + end else*/ if(!tc_branch_map_empty_i) begin + packet_format_o = te_pkg::F_DIFF_DELTA; + end else begin // branch count == 0 + packet_format_o = te_pkg::F_ADDR_ONLY; + end + valid_o = '1; + end + end else if(tc_resync_br_q || tc_er_n) begin + // non mandatory + /* if(tc_er_n && tc_trigger_req_i) begin // requested from trigger unit + notify_o = '1; + end */ + + /* choosing between format 0/1/2 */ + /*if(tc_pbc_i >= 31) begin + packet_format_o = F_OPT_EXT; + packet_f_opt_ext_subformat_o = SF_JTC; + // value for payload TBD + end else if(jtc_enabled_i && address_in_cache_i) begin + packet_format_o = F_OPT_EXT; + packet_f_opt_ext_subformat_o = SF_JTC; + // value for payload TBD + end else*/ if(!tc_branch_map_empty_i) begin + packet_format_o = te_pkg::F_DIFF_DELTA; + end else begin // branch count == 0 + packet_format_o = te_pkg::F_ADDR_ONLY; + end + valid_o = '1; + end else if(nc_exc_only_o || nc_ppccd_br_o || !nc_qualified_i) begin + if(!nc_qualified_i) begin + // the packet is sent because it's the last instr qualified + lc_ended_rep_d = '1; + end + /* choosing between format 0/1/2 */ + /*if(tc_pbc_i >= 31) begin + packet_format_o = F_OPT_EXT; + packet_f_opt_ext_subformat_o = SF_JTC; + // value for payload TBD + end else if(jtc_enabled_i && address_in_cache_i) begin + packet_format_o = F_OPT_EXT; + packet_f_opt_ext_subformat_o = SF_JTC; + // value for payload TBD + end else*/ if(!tc_branch_map_empty_i) begin + packet_format_o = te_pkg::F_DIFF_DELTA; + end else begin // branch count == 0 + packet_format_o = te_pkg::F_ADDR_ONLY; + end + valid_o = '1; + end else if(tc_rpt_br) begin + /* // non mandatory, requires support for jtc and branch prediction + if(tc_pbc_i >= 31) begin + packet_format_o = F_OPT_EXT; + packet_f_opt_ext_subformat_o = SF_PBC; + valid_o = '1; + end else begin*/ + packet_format_o = te_pkg::F_DIFF_DELTA; + valid_o = '1; + //end + end /*else if(tc_cci) begin // non mandatory, requires support for context + packet_format_o = F_SYNC; + packet_f_sync_subformat_o = SF_CONTEXT; + valid_o = '1; + end*/ + end + end + end + + /* compression logic */ + /* short explanation on how it works: + by using the lzc we determine how many bits we can discard starting from the MSB, + this process is done with the normal address (we count 0s) and bitwise not of the + signal (we count 1s). + Then we decide in which way we can compress more and output the keep_bits signal. + + On the encoder side, it's possible to reconstruct the address: because we don't + remove all 0s (or 1s) from the MSB, but we keep one. This way it's possible to + sign extend the compressed address and get back the original address. + + Example 1: + address to compress: 0000001100010 + bits kept: -----01100010 + + Example 2: + address to compress: 1111011110110 + bits kept: ---1011110110 + + */ + // choosing between removing 1s or 0s + assign sign_extendable = addr_zeros > addr_ones ? addr_zeros : addr_ones; + // outputting the least sign bits we want to keep + // empty signals are used to cover 32'b0 and 32'b1 corner cases + assign keep_bits_o = (empty_zeros || empty_ones) ? 1 : te_pkg::XLEN - sign_extendable + 1; + + // leading zero counters + // from common_cells + lzc #( + .WIDTH(te_pkg::XLEN), + .MODE(1) + )i_lzc_zeros( + .in_i (addr_to_compress_i), + .cnt_o (addr_zeros), + .empty_o(empty_zeros) + ); + + lzc #( + .WIDTH(te_pkg::XLEN), + .MODE(1) + )i_lzc_ones( + .in_i (~addr_to_compress_i), + .cnt_o (addr_ones), + .empty_o(empty_ones) + ); + +endmodule \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv new file mode 100644 index 00000000000..0b7a086a514 --- /dev/null +++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv @@ -0,0 +1,792 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +/*REG*/ +/* +it stores values for the encoder in memory mapped registers +*/ + +// uncomment to enable 64bits arch support +//`define TE_ARCH64 + +module te_reg #( + parameter APB_ADDR_WIDTH = 32 // it is the max allowed, maybe change to a smaller value +) +( + input logic clk_i, + input logic rst_ni, + + // tracing management + input logic trace_req_off_i, // from filter + input logic trace_req_on_i, // directly from trigger unit + input logic encapsulator_ready_i, + + // filter settings + output logic cause_filter_o, + output logic [te_pkg::XLEN-1:0] upper_cause_o, + output logic [te_pkg::XLEN-1:0] lower_cause_o, + output logic [te_pkg::XLEN-1:0] match_cause_o, + output logic cause_mode_o, + output logic tvec_filter_o, + output logic [te_pkg::XLEN-1:0] upper_tvec_o, + output logic [te_pkg::XLEN-1:0] lower_tvec_o, + output logic [te_pkg::XLEN-1:0] match_tvec_o, + output logic tvec_mode_o, + output logic tval_filter_o, + output logic [te_pkg::XLEN-1:0] upper_tval_o, + output logic [te_pkg::XLEN-1:0] lower_tval_o, + output logic [te_pkg::XLEN-1:0] match_tval_o, + output logic tval_mode_o, + output logic priv_lvl_filter_o, + output logic [te_pkg::PRIV_LEN-1:0] upper_priv_o, + output logic [te_pkg::PRIV_LEN-1:0] lower_priv_o, + output logic [te_pkg::PRIV_LEN-1:0] match_priv_o, + output logic priv_lvl_mode_o, + output logic iaddr_filter_o, + output logic [te_pkg::XLEN-1:0] upper_iaddr_o, + output logic [te_pkg::XLEN-1:0] lower_iaddr_o, + output logic [te_pkg::XLEN-1:0] match_iaddr_o, + output logic iaddr_mode_o, + + output logic trace_enable_o, // turned off by filter + output logic trace_activated_o, // managed by user + // packet_emitter settings and control + output logic nocontext_o, + output logic notime_o, + output logic encoder_mode_o, // hardwired to 0 - can only be 0 according to spec + output te_pkg::ioptions_s configuration_o, + output logic lossless_trace_o, + output logic shallow_trace_o, + + output logic clk_gated_o, + + // APB I/O interface + input logic [APB_ADDR_WIDTH-1:0] paddr_i, + input logic pwrite_i, + input logic psel_i, + input logic penable_i, + input logic [31:0] pwdata_i, + output logic pready_o, + output logic [31:0] prdata_o +); + + // FFs I/Os + logic trace_enable_d, trace_enable_q; + // trace enabling + logic trace_req_off, trace_req_on; + logic turn_on, turn_off; + logic clk_gated; + logic test_enabled; + + // registers I/O + logic cause_filter_d, cause_filter_q; + logic [te_pkg::XLEN-1:0] upper_cause_d, upper_cause_q; + logic [te_pkg::XLEN-1:0] lower_cause_d, lower_cause_q; + logic [te_pkg::XLEN-1:0] match_cause_d, match_cause_q; + logic cause_mode_d, cause_mode_q; + logic tvec_filter_d, tvec_filter_q; + logic [te_pkg::XLEN-1:0] upper_tvec_d, upper_tvec_q; + logic [te_pkg::XLEN-1:0] lower_tvec_d, lower_tvec_q; + logic [te_pkg::XLEN-1:0] match_tvec_d, match_tvec_q; + logic tvec_mode_d, tvec_mode_q; + logic tval_filter_d, tval_filter_q; + logic [te_pkg::XLEN-1:0] upper_tval_d, upper_tval_q; + logic [te_pkg::XLEN-1:0] lower_tval_d, lower_tval_q; + logic [te_pkg::XLEN-1:0] match_tval_d, match_tval_q; + logic tval_mode_d, tval_mode_q; + logic priv_lvl_filter_d, priv_lvl_filter_q; + logic [te_pkg::PRIV_LEN-1:0] upper_priv_d, upper_priv_q; + logic [te_pkg::PRIV_LEN-1:0] lower_priv_d, lower_priv_q; + logic [te_pkg::PRIV_LEN-1:0] match_priv_d, match_priv_q; + logic priv_lvl_mode_d, priv_lvl_mode_q; + logic iaddr_filter_d, iaddr_filter_q; + logic [te_pkg::XLEN-1:0] upper_iaddr_d, upper_iaddr_q; + logic [te_pkg::XLEN-1:0] lower_iaddr_d, lower_iaddr_q; + logic [te_pkg::XLEN-1:0] match_iaddr_d, match_iaddr_q; + logic iaddr_mode_d, iaddr_mode_q; + logic trace_activated_d, trace_activated_q; + logic nocontext_d, nocontext_q; + logic notime_d, notime_q; + te_pkg::ioptions_s configuration_d, configuration_q; + logic lossless_trace_d, lossless_trace_q; + logic shallow_trace_d, shallow_trace_q; + + // APB transaction + logic read_access; + logic write_access; + logic setup_d, setup_q; + + // assignments + // filter + assign cause_filter_o = cause_filter_q; + assign upper_cause_o = upper_cause_q; + assign lower_cause_o = lower_cause_q; + assign match_cause_o = match_cause_q; + assign cause_mode_o = cause_mode_q; + assign tvec_filter_o = tvec_filter_q; + assign upper_tvec_o = upper_tvec_q; + assign lower_tvec_o = lower_tvec_q; + assign match_tvec_o = match_tvec_q; + assign tvec_mode_o = tvec_mode_q; + assign tval_filter_o = tval_filter_q; + assign upper_tval_o = upper_tval_q; + assign lower_tval_o = lower_tval_q; + assign match_tval_o = match_tval_q; + assign tval_mode_o = tval_mode_q; + assign priv_lvl_filter_o = priv_lvl_filter_q; + assign upper_priv_o = upper_priv_q; + assign lower_priv_o = lower_priv_q; + assign match_priv_o = match_priv_q; + assign priv_lvl_mode_o = priv_lvl_mode_q; + assign iaddr_filter_o = iaddr_filter_q; + assign upper_iaddr_o = upper_iaddr_q; + assign lower_iaddr_o = lower_iaddr_q; + assign match_iaddr_o = match_iaddr_q; + assign iaddr_mode_o = iaddr_mode_q; + // packet emitter + assign configuration_o = configuration_q; + assign lossless_trace_o = lossless_trace_q; // if == 1 stalls the core when the encapsulator buffer is full + assign shallow_trace_o = shallow_trace_q; // if == 1 flushes the branch map at each packet emitted + assign nocontext_o = nocontext_q; + assign notime_o = notime_q; + assign encoder_mode_o = '0; // hardwired + assign trace_activated_o = trace_activated_q; + + // tracing is switched on only when it's not enabled anc a request of turning on is received + assign turn_on = (trace_enable_q == 0) && (trace_req_on /*|| encapsulator_ready_i*/); // encapsulator signal is temporarely disabled + // tracing is switched off only when it's not enabled anc a request of turning off is received + assign turn_off = (trace_enable_q == 1) && (trace_req_off /*|| ~encapsulator_ready_i*/); + // the toggle of trace_enable value happens only when turn off or turn off is asserted + assign trace_enable_d = (turn_off || turn_on) ? ~trace_enable_q : trace_enable_q; + assign trace_enable_o = trace_enable_d; + + assign clk_gated_o = clk_gated; + assign test_enabled = '0; + + assign setup_d = psel_i && ~penable_i; + assign pready_o = setup_q && psel_i && penable_i; + assign read_access = pready_o && !pwrite_i; + assign write_access = pready_o && pwrite_i; + + /* APB read and write */ + always_comb begin + // initialization + // set _d as _q, because we don't to erase them all + cause_filter_d = cause_filter_q; + cause_mode_d = cause_mode_q; + tvec_filter_d = tvec_filter_q; + tvec_mode_d = tvec_mode_q; + tval_filter_d = tval_filter_q; + tval_mode_d = tval_mode_q; + priv_lvl_filter_d = priv_lvl_filter_q; + priv_lvl_mode_d = priv_lvl_mode_q; + iaddr_filter_d = iaddr_filter_q; + iaddr_mode_d = iaddr_mode_q; + lower_priv_d = lower_priv_q; + upper_priv_d = upper_priv_q; + match_priv_d = match_priv_q; + trace_activated_d = trace_activated_q; + lossless_trace_d = lossless_trace_q; + shallow_trace_d = shallow_trace_q; + notime_d = notime_q; + nocontext_d = nocontext_q; + configuration_d = configuration_q; + upper_cause_d = upper_cause_q; + lower_cause_d = lower_cause_q; + match_cause_d = match_cause_q; + upper_tvec_d = upper_tvec_q; + lower_tvec_d = lower_tvec_q; + match_tvec_d = match_tvec_q; + upper_tval_d = upper_tval_q; + lower_tval_d = lower_tval_q; + match_tval_d = match_tval_q; + upper_iaddr_d = upper_iaddr_q; + lower_iaddr_d = lower_iaddr_q; + match_iaddr_d = match_iaddr_q; + prdata_o = '0; // clean output + + if (read_access) begin + case (paddr_i[7:0]) + // XLEN agnostic (or always <= than 32) + // FILTER + // enable and mode + te_pkg::CAUSE_ENABLE_MODE: begin + prdata_o[0] = cause_filter_q; + prdata_o[1] = cause_mode_q; + end + + te_pkg::TVEC_ENABLE_MODE: begin + prdata_o[0] = tvec_filter_q; + prdata_o[1] = tvec_mode_q; + end + + te_pkg::TVAL_ENABLE_MODE: begin + prdata_o[0] = tval_filter_q; + prdata_o[1] = tval_mode_q; + end + + te_pkg::PRIV_ENABLE_MODE: begin + prdata_o[0] = priv_lvl_filter_q; + prdata_o[1] = priv_lvl_mode_q; + end + + te_pkg::IADDR_ENABLE_MODE: begin + prdata_o[0] = iaddr_filter_q; + prdata_o[1] = iaddr_mode_q; + end + + // priv + te_pkg::PRIV_RANGE: begin + prdata_o[te_pkg::PRIV_LEN-1:0] = lower_priv_q; + prdata_o[te_pkg::PRIV_LEN*2-1:te_pkg::PRIV_LEN] = upper_priv_q; + end + + te_pkg::PRIV_MATCH: begin + prdata_o[te_pkg::PRIV_LEN-1:0] = match_priv_q; + end + + // TRACE MANAGEMENT + te_pkg::TRACE_STATE: begin + prdata_o[0] = trace_activated_q; + end + + te_pkg::LOSSLESS_TRACE: begin + prdata_o[0] = lossless_trace_q; + end + + te_pkg::SHALLOW_TRACE: begin + prdata_o[0] = shallow_trace_q; + end + + // PACKET EMITTER + te_pkg::NO_TIME: begin + prdata_o[0] = notime_q; + end + + te_pkg::NO_CONTEXT: begin + prdata_o[0] = nocontext_q; + end + + te_pkg::DELTA_ADDRESS: begin + prdata_o[0] = configuration_q.delta_address_en; + end + te_pkg::FULL_ADDRESS: begin + prdata_o[0] = configuration_q.full_address_en; + end + te_pkg::IMPLICIT_EXCEPTION: begin + prdata_o[0] = configuration_q.implicit_exception_en; + end + te_pkg::SIJUMP: begin + prdata_o[0] = configuration_q.sijump_en; + end + te_pkg::IMPLICIT_RETURN: begin + prdata_o[0] = configuration_q.implicit_return_en; + end + te_pkg::BRANCH_PREDICTION: begin + prdata_o[0] = configuration_q.branch_prediction_en; + end + te_pkg::JUMP_TARGET_CACHE: begin + prdata_o[0] = configuration_q.jump_target_cache_en; + end + + `ifdef TE_ARCH64 // 64bits case + // FILTER + // cause + te_pkg::CAUSE_UPPER: begin + prdata_o[te_pkg::XLEN-1:0] = upper_cause_q; + end + + te_pkg::CAUSE_LOWER: begin + prdata_o[te_pkg::XLEN-1:0] = lower_cause_q; + end + + te_pkg::CAUSE_MATCH: begin + prdata_o[te_pkg::XLEN-1:0] = match_cause_q; + end + + // tvec + te_pkg::TVEC_UPPER_L: begin // least significant bits + prdata_o = upper_tvec_q[31:0]; + end + + te_pkg::TVEC_UPPER_M: begin // most significant bits + prdata_o = upper_tvec_q[63:32]; + end + + te_pkg::TVEC_LOWER_L: begin // least significant bits + prdata_o = lower_tvec_q[31:0]; + end + + te_pkg::TVEC_LOWER_M: begin // most significant bits + prdata_o = lower_tvec_q[63:32]; + end + + te_pkg::TVEC_MATCH_L: begin // least significant bits + prdata_o = match_tvec_q[31:0]; + end + + te_pkg::TVEC_MATCH_M: begin // most significant bits + prdata_o = match_tvec_q[63:32]; + end + + // tval + te_pkg::TVAL_UPPER_L: begin // least significant bits + prdata_o = upper_tval_q[31:0]; + end + + te_pkg::TVAL_UPPER_M: begin // most significant bits + prdata_o = upper_tval_q[63:32]; + end + + te_pkg::TVAL_LOWER_L: begin // least significant bits + prdata_o = lower_tval_q[31:0]; + end + + te_pkg::TVAL_LOWER_M: begin // most significant bits + prdata_o = lower_tval_q[63:32]; + end + + te_pkg::TVAL_MATCH_L: begin // least significant bits + prdata_o = match_tval_q[31:0]; + end + + te_pkg::TVAL_MATCH_M: begin // most significant bits + prdata_o = match_tval_q[63:32]; + end + + // iaddr + te_pkg::IADDR_UPPER_L: begin // least significant bits + prdata_o = upper_iaddr_q[31:0]; + end + + te_pkg::IADDR_UPPER_M: begin // most significant bits + prdata_o = upper_iaddr_q[63:32]; + end + + te_pkg::IADDR_LOWER_L: begin // least significant bits + prdata_o = lower_iaddr_q[31:0]; + end + + te_pkg::IADDR_LOWER_M: begin // most significant bits + prdata_o = lower_iaddr_q[63:32]; + end + + te_pkg::IADDR_MATCH_L: begin // least significant bits + prdata_o = match_iaddr_q[31:0]; + end + + te_pkg::IADDR_MATCH_M: begin // most significant bits + prdata_o = match_iaddr_q[63:32]; + end + + `else // 32bits case + // FILTER + // cause + te_pkg::CAUSE_UPPER: begin + prdata_o[te_pkg::XLEN-1:0] = upper_cause_q; + end + + te_pkg::CAUSE_LOWER: begin + prdata_o[te_pkg::XLEN-1:0] = lower_cause_q; + end + + te_pkg::CAUSE_MATCH: begin + prdata_o[te_pkg::XLEN-1:0] = match_cause_d; + end + + // tvec + te_pkg::TVEC_UPPER: begin + prdata_o = upper_tvec_q; + end + + te_pkg::TVEC_LOWER: begin + prdata_o = lower_tvec_q; + end + + te_pkg::TVEC_MATCH: begin + prdata_o = match_tvec_q; + end + + // tval + te_pkg::TVAL_UPPER: begin + prdata_o = upper_tval_q; + end + + te_pkg::TVAL_LOWER: begin + prdata_o = lower_tval_q; + end + + te_pkg::TVAL_MATCH: begin + prdata_o = match_tval_q; + end + + // iaddr + te_pkg::IADDR_UPPER: begin + prdata_o = upper_iaddr_q; + end + + te_pkg::IADDR_LOWER: begin + prdata_o = lower_iaddr_q; + end + + te_pkg::IADDR_MATCH: begin + prdata_o = match_iaddr_q; + end + `endif + endcase + end else if (write_access) begin + + + case (paddr_i[7:0]) + // common cases + te_pkg::CAUSE_ENABLE_MODE: begin + cause_filter_d = pwdata_i[0]; + cause_mode_d = pwdata_i[1]; + end + + te_pkg::TVEC_ENABLE_MODE: begin + tvec_filter_d = pwdata_i[0]; + tvec_mode_d = pwdata_i[1]; + end + + te_pkg::TVAL_ENABLE_MODE: begin + tval_filter_d = pwdata_i[0]; + tval_mode_d = pwdata_i[1]; + end + + te_pkg::PRIV_ENABLE_MODE: begin + priv_lvl_filter_d = pwdata_i[0]; + priv_lvl_mode_d = pwdata_i[1]; + end + + te_pkg::IADDR_ENABLE_MODE: begin + iaddr_filter_d = pwdata_i[0]; + iaddr_mode_d = pwdata_i[1]; + end + + // priv + te_pkg::PRIV_RANGE: begin + lower_priv_d = pwdata_i[te_pkg::PRIV_LEN-1:0]; + upper_priv_d = pwdata_i[te_pkg::PRIV_LEN*2-1:te_pkg::PRIV_LEN]; + end + + te_pkg::PRIV_MATCH: begin + match_priv_d = pwdata_i[te_pkg::PRIV_LEN-1:0]; + end + + // TRACE MANAGEMENT + te_pkg::TRACE_STATE: begin + trace_activated_d = pwdata_i[0]; + end + + te_pkg::LOSSLESS_TRACE: begin + lossless_trace_d = pwdata_i[0]; + end + + te_pkg::SHALLOW_TRACE: begin + shallow_trace_d = pwdata_i[0]; + end + + // PACKET EMITTER + te_pkg::NO_TIME: begin + notime_d = pwdata_i[0]; + end + + te_pkg::NO_CONTEXT: begin + nocontext_d = pwdata_i[0]; + end + + te_pkg::DELTA_ADDRESS: begin + configuration_d.delta_address_en = pwdata_i[0]; + end + + te_pkg::FULL_ADDRESS: begin + configuration_d.full_address_en = pwdata_i[0]; + end + + te_pkg::IMPLICIT_EXCEPTION: begin + configuration_d.implicit_exception_en = pwdata_i[0]; + end + + te_pkg::SIJUMP: begin + configuration_d.sijump_en = pwdata_i[0]; + end + + te_pkg::IMPLICIT_RETURN: begin + configuration_d.implicit_return_en = pwdata_i[0]; + end + + te_pkg::BRANCH_PREDICTION: begin + configuration_d.branch_prediction_en = pwdata_i[0]; + end + + te_pkg::JUMP_TARGET_CACHE: begin + configuration_d.jump_target_cache_en = pwdata_i[0]; + end + + `ifdef TE_ARCH64 + // cause + te_pkg::CAUSE_UPPER: begin + upper_cause_d = pwdata_i[te_pkg::XLEN-1:0]; + end + + te_pkg::CAUSE_LOWER: begin + lower_cause_d = pwdata_i[te_pkg::XLEN-1:0]; + end + + te_pkg::CAUSE_MATCH: begin + match_cause_d = pwdata_i[te_pkg::XLEN-1:0]; + end + + // tvec + te_pkg::TVEC_UPPER_L: begin // least significant bits + upper_tvec_d[31:0] = pwdata_i; + end + + te_pkg::TVEC_UPPER_M: begin // most significant bits + upper_tvec_d[63:32] = pwdata_i; + end + + te_pkg::TVEC_LOWER_L: begin // least significant bits + lower_tvec_d[31:0] = pwdata_i; + end + + te_pkg::TVEC_LOWER_M: begin // most significant bits + lower_tvec_d[63:32] = pwdata_i; + end + + te_pkg::TVEC_MATCH_L: begin // least significant bits + match_tvec_d[31:0] = pwdata_i; + end + + te_pkg::TVEC_MATCH_M: begin // most significant bits + match_tvec_d[63:32] = pwdata_i; + end + + // tval + te_pkg::TVAL_UPPER_L: begin // least significant bits + upper_tval_d[31:0] = pwdata_i; + end + + te_pkg::TVAL_UPPER_M: begin // most significant bits + upper_tval_d[63:32] = pwdata_i; + end + + te_pkg::TVAL_LOWER_L: begin // least significant bits + lower_tval_d[31:0] = pwdata_i; + end + + te_pkg::TVAL_LOWER_M: begin // most significant bits + lower_tval_d[63:32] = pwdata_i; + end + + te_pkg::TVAL_MATCH_L: begin // least significant bits + match_tval_d[31:0] = pwdata_i; + end + + te_pkg::TVAL_MATCH_M: begin // most significant bits + match_tval_d[63:32] = pwdata_i; + end + + // iaddr + te_pkg::IADDR_UPPER_L: begin // least significant bits + upper_iaddr_d[31:0] = pwdata_i; + end + + te_pkg::IADDR_UPPER_M: begin // most significant bits + upper_iaddr_d[63:32] = pwdata_i; + end + + te_pkg::IADDR_LOWER_L: begin // least significant bits + lower_iaddr_d[31:0] = pwdata_i; + end + + te_pkg::IADDR_LOWER_M: begin // most significant bits + lower_iaddr_d[63:32] = pwdata_i; + end + + te_pkg::IADDR_MATCH_L: begin // least significant bits + match_iaddr_d[31:0] = pwdata_i; + end + + te_pkg::IADDR_MATCH_M: begin // most significant bits + match_iaddr_d[63:32] = pwdata_i; + end + `else // 32 bits case + // cause + te_pkg::CAUSE_UPPER: begin + upper_cause_d = pwdata_i[te_pkg::XLEN-1:0]; + end + + te_pkg::CAUSE_LOWER: begin + lower_cause_d = pwdata_i[te_pkg::XLEN-1:0]; + end + + te_pkg::CAUSE_MATCH: begin + match_cause_d = pwdata_i[te_pkg::XLEN-1:0]; + end + + // tvec + te_pkg::TVEC_UPPER: begin + upper_tvec_d = pwdata_i; + end + + te_pkg::TVEC_LOWER: begin + lower_tvec_d = pwdata_i; + end + + te_pkg::TVEC_MATCH: begin + match_tvec_d = pwdata_i; + end + + // tval + te_pkg::TVAL_UPPER: begin + upper_tval_d = pwdata_i; + end + + te_pkg::TVAL_LOWER: begin + lower_tval_d = pwdata_i; + end + + te_pkg::TVAL_MATCH: begin + match_tval_d = pwdata_i; + end + + // iaddr + te_pkg::IADDR_UPPER: begin + upper_iaddr_d = pwdata_i; + end + + te_pkg::IADDR_LOWER: begin + lower_iaddr_d = pwdata_i; + end + + te_pkg::IADDR_MATCH: begin + match_iaddr_d = pwdata_i; + end + `endif + endcase + end + end + + // clock gating module + pulp_clock_gating i_clock_gating( + .clk_i (clk_i), + .en_i (trace_activated_o), + .test_en_i(test_enabled), + .clk_o (clk_gated) + ); + + // edge detector for trace_req_on_i + // turns on and off the tracing + edge_detect i_edge_detect_on( + .clk_i(clk_gated), + .rst_ni(rst_ni), + .d_i(trace_req_on_i), + .re_o(trace_req_on), + .fe_o() + ); + + // edge detector for trace_req_off_i + // turns on and off the tracing + edge_detect i_edge_detect_off( + .clk_i(clk_gated), + .rst_ni(rst_ni), + .d_i(trace_req_off_i), + .re_o(trace_req_off), + .fe_o() + ); + + always_ff @(posedge clk_i, negedge rst_ni) begin + if(~rst_ni) begin + trace_enable_q <= '1; + // storing config parameters + cause_filter_q <= '0; + upper_cause_q <= '0; + lower_cause_q <= '0; + match_cause_q <= '0; + cause_mode_q <= '0; + tvec_filter_q <= '0; + upper_tvec_q <= '0; + lower_tvec_q <= '0; + match_tvec_q <= '0; + tvec_mode_q <= '0; + tval_filter_q <= '0; + upper_tval_q <= '0; + lower_tval_q <= '0; + match_tval_q <= '0; + tval_mode_q <= '0; + priv_lvl_filter_q <= '0; + upper_priv_q <= '0; + lower_priv_q <= '0; + match_priv_q <= '0; + priv_lvl_mode_q <= '0; + iaddr_filter_q <= '0; + upper_iaddr_q <= '0; + lower_iaddr_q <= '0; + match_iaddr_q <= '0; + iaddr_mode_q <= '0; + configuration_q.delta_address_en <= '0; // delta address only one mandatory //FIXME changing this for debug + configuration_q.full_address_en <= '1; + configuration_q.implicit_exception_en <= '0; + configuration_q.sijump_en <= '0; + configuration_q.implicit_return_en <= '0; + configuration_q.branch_prediction_en <= '0; + configuration_q.jump_target_cache_en <= '0; + lossless_trace_q <= '0; + shallow_trace_q <= '0; + nocontext_q <= '1; + notime_q <= '0; + trace_activated_q <= '1; + setup_q <= '0; + end else begin + trace_enable_q <= trace_enable_d; + // storing config parameters + cause_filter_q <= cause_filter_d; + upper_cause_q <= upper_cause_d; + lower_cause_q <= lower_cause_d; + match_cause_q <= match_cause_d; + cause_mode_q <= cause_mode_d; + tvec_filter_q <= tvec_filter_d; + upper_tvec_q <= upper_tvec_d; + lower_tvec_q <= lower_tvec_d; + match_tvec_q <= match_tvec_d; + tvec_mode_q <= tvec_mode_d; + tval_filter_q <= tval_filter_d; + upper_tval_q <= upper_tval_d; + lower_tval_q <= lower_tval_d; + match_tval_q <= match_tval_d; + tval_mode_q <= tval_mode_d; + priv_lvl_filter_q <= priv_lvl_filter_d; + upper_priv_q <= upper_priv_d; + lower_priv_q <= lower_priv_d; + match_priv_q <= match_priv_d; + priv_lvl_mode_q <= priv_lvl_mode_d; + iaddr_filter_q <= iaddr_filter_d; + upper_iaddr_q <= upper_iaddr_d; + lower_iaddr_q <= lower_iaddr_d; + match_iaddr_q <= match_iaddr_d; + iaddr_mode_q <= iaddr_mode_d; + configuration_q <= configuration_d; + lossless_trace_q <= lossless_trace_d; + shallow_trace_q <= shallow_trace_d; + nocontext_q <= nocontext_d; + notime_q <= notime_d; + trace_activated_q <= trace_activated_d; + setup_q <= setup_d; + end + end + +endmodule \ No newline at end of file diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv new file mode 100644 index 00000000000..d8c6f9a8aa3 --- /dev/null +++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv @@ -0,0 +1,106 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Umberto Laghi +// Contact: umberto.laghi2@unibo.it +// Github: @ubolakes + +/* RESYNC COUNTER */ +/* +It keeps track of the emitted packets or cycles elapsed, +operational mode and threshold are set by the user. + +It produces a signal when the counter reaches the specified +threshold and it remains to 1 until it receives a reset signal. + +In packed mode: the packets that exceeds the defined threshold +are discarded, because they belong to a pre-resync period. +Packets received while the counter is requesting a resync are +ignored. +*/ + +module te_resync_counter #( + parameter N = 1, + parameter MODE = te_pkg::CYCLE_MODE, // counts cycles as default + parameter MAX_VALUE = 16'hFFFF // default max value, can be personalized + ) + ( + input logic clk_i, + input logic rst_ni, + + input logic trace_enabled_i, // it comes from filter + input logic [N-1:0] packet_emitted_i, + input logic resync_rst_i, + + output logic gt_resync_max_o, // greater than the max value, in reality MAX_VALUE + output logic et_resync_max_o // equals to the max value, in reality MAX_VALUE-1 + ); + + /* + The packets that exceeds the defined threshold are discarded, + because they belong to a pre-resync period. + Packets received while the counter is requesting a resync are + ignored. + */ + + // signals declaration + logic [$clog2(MAX_VALUE):0] counter_d, counter_q; + logic [$clog2(N):0] n_packets; + logic overflow; + + // assignments + // both for packet and cycle mode + assign et_resync_max_o = counter_d == MAX_VALUE; + assign gt_resync_max_o = counter_d > MAX_VALUE && ~resync_rst_i; + + always_comb begin + // init + counter_d = counter_q; + n_packets = '0; + + // packet mode + if (MODE == te_pkg::PACKET_MODE && trace_enabled_i) begin + // counting the packets received + for (int i = 0; i < N; i++) begin + if (packet_emitted_i[i]) begin + n_packets += 1; + end + end + + // summing the packets counted + for (int i = 0; i < n_packets; i++) begin + if (counter_d <= MAX_VALUE) begin + counter_d += 1; + end + end + end + + // cycle mode + if (MODE == te_pkg::CYCLE_MODE && trace_enabled_i && counter_d <= MAX_VALUE) begin + counter_d += 1; + end + + // synchronous reset + if (resync_rst_i) begin + counter_d = '0; + end + end + + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + counter_q <= '0; + end else begin + counter_q <= counter_d; + end + end + +endmodule \ No newline at end of file diff --git a/corev_apu/openpiton/ariane_verilog_wrap.sv b/corev_apu/openpiton/ariane_verilog_wrap.sv index 5b8e5744217..8e7cceb4968 100644 --- a/corev_apu/openpiton/ariane_verilog_wrap.sv +++ b/corev_apu/openpiton/ariane_verilog_wrap.sv @@ -12,17 +12,69 @@ // Date: 19.03.2017 // Description: Ariane Top-level wrapper to break out SV structs to logic vectors. - module ariane_verilog_wrap import ariane_pkg::*; + import config_pkg::*; + import l15_pkg::*; #( parameter int unsigned RASDepth = 2, parameter int unsigned BTBEntries = 32, parameter int unsigned BHTEntries = 128, + parameter int unsigned NrCommitPorts = 2, + parameter int unsigned NrLoadBufEntries = 2, + parameter int unsigned NrRgprPorts = 0, + parameter int unsigned NrWbPorts = 0, + parameter int unsigned MaxOutstandingStores = 7, + parameter logic [63:0] HaltAddress = 64'h800, + parameter logic [63:0] ExceptionAddress = 64'h808, + parameter bit EnableAccelerator = 0, + parameter bit SupervisorModeEn = 1, + parameter bit TvalEn = 1, + parameter bit DebugEn = 1, + parameter bit NonIdemPotenceEn = 0, + parameter int unsigned XLEN = 64, + parameter int unsigned VLEN = 64, + parameter bit FpgaEn = 0, + parameter bit FpgaAlteraEn = 0, + // RISCV extensions + parameter bit FpuEn = 1, + parameter bit F16En = 0, + parameter bit F16AltEn = 0, + parameter bit F8En = 0, + parameter bit FVecEn = 0, + parameter bit CvxifEn = 0, + parameter bit CExtEn = 1, + parameter bit ZcbExtEn = 0, + parameter bit AExtEn = 1, + parameter bit BExtEn = 0, + parameter bit VExtEn = 0, + parameter bit ZcmpExtEn = 0, + parameter bit FExtEn = 0, + parameter bit DExtEn = 0, + parameter bit RVUEn = 1, + parameter bit RVZicntrEn = 0, + parameter bit RVZiCondEn = 0, + parameter bit RVZihpmEn = 0, + parameter bit HExtEn = 0, + parameter bit RVFEn = 1, + parameter bit RVDEn = 1, + // extended + parameter bit FpPresent = 0, + parameter int unsigned FLen = 0, + parameter bit NSXEn = 0, // non standard extensions present + parameter bit RVFVecEn = 0, + parameter bit XF16VecEn = 0, + parameter bit XF16ALTVecEn = 0, + parameter bit XF8VecEn = 0, + parameter bit PerfCounterEn = 0, // debug module base address parameter logic [63:0] DmBaseAddress = 64'h0, - // swap endianess in l15 adapter + // swap endianness in l15 adapter parameter bit SwapEndianess = 1, + // AXI Configuration + parameter int unsigned AxiIdWidth = 4, + parameter int unsigned AxiUserWidth = 64, + parameter int unsigned AxiBurstWriteEn = 0, // PMA configuration // idempotent region parameter int unsigned NrNonIdempotentRules = 1, @@ -37,14 +89,18 @@ module ariane_verilog_wrap parameter logic [NrMaxRules*64-1:0] CachedRegionAddrBase = '0, parameter logic [NrMaxRules*64-1:0] CachedRegionLength = '0, // PMP - parameter int unsigned NrPMPEntries = 8 + parameter int unsigned NrPMPEntries = 8, + // HPDC Write coalescing + parameter bit WriteCoalescingEn = 0, + parameter int unsigned WriteCoalescingTh = 0, + parameter bit UseHPDcache = 0 // 1: HPDC, 0: WTcache ) ( input clk_i, input reset_l, // this is an openpiton-specific name, do not change (hier. paths in TB use this) output spc_grst_l, // this is an openpiton-specific name, do not change (hier. paths in TB use this) // Core ID, Cluster ID and boot address are considered more or less static - input [riscv::VLEN-1:0] boot_addr_i, // reset boot address - input [riscv::XLEN-1:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR) + input [VLEN-1:0] boot_addr_i, // reset boot address + input [XLEN-1:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR) // Interrupt inputs input [1:0] irq_i, // level sensitive IR lines, mip & sip (async) input ipi_i, // inter-processor interrupts (async) @@ -53,14 +109,115 @@ module ariane_verilog_wrap input debug_req_i, // debug request (async) // L15 (memory side) - output [$size(wt_cache_pkg::l15_req_t)-1:0] l15_req_o, - input [$size(wt_cache_pkg::l15_rtrn_t)-1:0] l15_rtrn_i + output [$size(l15_pkg::l15_req_t)-1:0] l15_req_o, + input [$size(l15_pkg::l15_rtrn_t)-1:0] l15_rtrn_i ); + localparam cva6_user_cfg_t cva6_user_cfg = '{ + XLEN: XLEN, + VLEN: VLEN, + RVA: AExtEn, + RVB: BExtEn, + ZKN: 1'b0, // Scalar Cryptography extension disabled + RVV: VExtEn, + RVC: CExtEn, + RVH: HExtEn, + RVZCB: ZcbExtEn, + RVZCMP: ZcmpExtEn, + RVZCMT: 1'b0, // Zcmt extension disabled + RVZiCond: RVZiCondEn, + RVZicntr: RVZicntrEn, + RVZihpm: RVZihpmEn, + RVZiCbom: 1'b0, // OpenPiton doesn't support CMOs at this time + RVF: RVFEn, + RVD: RVDEn, + XF16: F16En, + XF16ALT: F16AltEn, + XF8: F8En, + XFVec: FVecEn, + PerfCounterEn: PerfCounterEn, + MmuPresent: 1'b1, + RVS: SupervisorModeEn, + RVU: RVUEn, + SoftwareInterruptEn: 1'b1, // Software interrupts enabled + DebugEn: DebugEn, + DmBaseAddress: DmBaseAddress, + HaltAddress: HaltAddress, + ExceptionAddress: ExceptionAddress, + TvalEn: TvalEn, + DirectVecOnly: 1'b0, + NrPMPEntries: NrPMPEntries, + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, + PMPNapotEn: 1'b1, // PMP NAPOT mode enabled + NrNonIdempotentRules: NrNonIdempotentRules, + NonIdempotentAddrBase: NonIdempotentAddrBase, + NonIdempotentLength: NonIdempotentLength, + NrExecuteRegionRules: NrExecuteRegionRules, + ExecuteRegionAddrBase: ExecuteRegionAddrBase, + ExecuteRegionLength: ExecuteRegionLength, + NrCachedRegionRules: NrCachedRegionRules, + CachedRegionAddrBase: CachedRegionAddrBase, + CachedRegionLength: CachedRegionLength, + CvxifEn: CvxifEn, + CoproType: config_pkg::COPRO_NONE, // No coprocessor + NOCType: SwapEndianess ? NOC_TYPE_L15_BIG_ENDIAN : NOC_TYPE_L15_LITTLE_ENDIAN, + AxiAddrWidth: 40, + AxiDataWidth: 128, // Used to calculate the mem data width of hpdc + AxiIdWidth: 6, + AxiUserWidth: AxiUserWidth, + AxiBurstWriteEn: AxiBurstWriteEn, + MemTidWidth: 6, + IcacheByteSize: 16384, + IcacheSetAssoc: 4, + IcacheLineWidth: 256, + DCacheType: UseHPDcache ? config_pkg::HPDCACHE_WT : config_pkg::WT, + DcacheIdWidth: 1, + DcacheByteSize: 8192, + DcacheSetAssoc: 4, + DcacheLineWidth: 128, + DcacheFlushOnFence: 1'b0, // Don't flush D$ on fence + DcacheFlushOnFenceI: 1'b0, + DcacheInvalidateOnFlush: 1'b0, // Don't invalidate on flush + DataUserEn: 1'b0, + WtDcacheWbufDepth: 8, + FetchUserEn: 0, + FetchUserWidth: 64, + FpgaEn: FpgaEn, + FpgaAlteraEn: FpgaAlteraEn, + TechnoCut: 1'b0, + SuperscalarEn: 1'b0, + ALUBypass: 1'b0, // ALU bypass disabled + NrCommitPorts: NrCommitPorts, + NrLoadPipeRegs: 2, + NrStorePipeRegs: 0, + NrScoreboardEntries: 8, + NrLoadBufEntries: NrLoadBufEntries, + MaxOutstandingStores: MaxOutstandingStores, + RASDepth: RASDepth, + BTBEntries: BTBEntries, + BPType: config_pkg::BHT, // Bimodal predictor + BHTEntries: BHTEntries, + BHTHist: 2, // 2-bit history for BHT + InstrTlbEntries: 16, + DataTlbEntries: 16, + UseSharedTlb: 0, + SvnapotEn: 0, + SharedTlbDepth: 64, + SDTRIG: 0, + Mcontrol6: 0, + Icount: 0, + Etrigger: 0, + Itrigger: 0 + }; + + localparam cva6_cfg_t cva6_cfg = build_config_pkg::build_config(cva6_user_cfg); + // assign bitvector to packed struct and vice versa // L15 (memory side) - wt_cache_pkg::l15_req_t l15_req; - wt_cache_pkg::l15_rtrn_t l15_rtrn; + l15_req_t l15_req; + l15_rtrn_t l15_rtrn; assign l15_req_o = l15_req; assign l15_rtrn = l15_rtrn_i; @@ -156,33 +313,10 @@ module ariane_verilog_wrap // ariane instance ///////////////////////////// - localparam ariane_pkg::ariane_cfg_t ArianeOpenPitonCfg = '{ - RASDepth: RASDepth, - BTBEntries: BTBEntries, - BHTEntries: BHTEntries, - // idempotent region - NrNonIdempotentRules: NrNonIdempotentRules, - NonIdempotentAddrBase: NonIdempotentAddrBase, - NonIdempotentLength: NonIdempotentLength, - NrExecuteRegionRules: NrExecuteRegionRules, - ExecuteRegionAddrBase: ExecuteRegionAddrBase, - ExecuteRegionLength: ExecuteRegionLength, - // cached region - NrCachedRegionRules: NrCachedRegionRules, - CachedRegionAddrBase: CachedRegionAddrBase, - CachedRegionLength: CachedRegionLength, - // cache config - AxiCompliant: 1'b0, - SwapEndianess: SwapEndianess, - // debug - DmBaseAddress: DmBaseAddress, - NrPMPEntries: NrPMPEntries - }; - ariane #( - .ArianeCfg ( ArianeOpenPitonCfg ), - .noc_req_t ( wt_cache_pkg::l15_req_t ), - .noc_resp_t ( wt_cache_pkg::l15_rtrn_t ) + .CVA6Cfg ( cva6_cfg ), + .noc_req_t ( l15_req_t ), + .noc_resp_t ( l15_rtrn_t ) ) ariane ( .clk_i ( clk_i ), .rst_ni ( spc_grst_l ), diff --git a/corev_apu/openpiton/bootrom/linux/src/spi.c b/corev_apu/openpiton/bootrom/linux/src/spi.c index c574f59cf65..fa5b53f4163 100644 --- a/corev_apu/openpiton/bootrom/linux/src/spi.c +++ b/corev_apu/openpiton/bootrom/linux/src/spi.c @@ -115,7 +115,7 @@ int spi_write_bytes(uint8_t *bytes, uint32_t len, uint8_t *ret) for (int i = 0; i < len;) { status = read_reg(SPI_STATUS_REG); - if ((status & 0x1) != 0x1) // recieve fifo not empty + if ((status & 0x1) != 0x1) // receive fifo not empty { ret[i++] = read_reg(SPI_RECEIVE_REG); } diff --git a/corev_apu/src/ariane.sv b/corev_apu/src/ariane.sv index 866c6d63693..272b7f35160 100644 --- a/corev_apu/src/ariane.sv +++ b/corev_apu/src/ariane.sv @@ -12,16 +12,18 @@ // Date: 19.03.2017 // Description: Ariane Top-level module +`include "rvfi_types.svh" `include "cvxif_types.svh" module ariane import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type rvfi_probes_instr_t = logic, - parameter type rvfi_probes_csr_t = logic, + parameter type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg), + parameter type rvfi_probes_csr_t = `RVFI_PROBES_CSR_T(CVA6Cfg), parameter type rvfi_probes_t = struct packed { logic csr; - logic instr; + rvfi_probes_instr_t instr; }, + // CVXIF Types localparam type readregflags_t = `READREGFLAGS_T(CVA6Cfg), localparam type writeregflags_t = `WRITEREGFLAGS_T(CVA6Cfg), @@ -29,12 +31,12 @@ module ariane import ariane_pkg::*; #( localparam type hartid_t = `HARTID_T(CVA6Cfg), localparam type x_compressed_req_t = `X_COMPRESSED_REQ_T(CVA6Cfg, hartid_t), localparam type x_compressed_resp_t = `X_COMPRESSED_RESP_T(CVA6Cfg), - localparam type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartit_t, id_t), + localparam type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartid_t, id_t), localparam type x_issue_resp_t = `X_ISSUE_RESP_T(CVA6Cfg, writeregflags_t, readregflags_t), localparam type x_register_t = `X_REGISTER_T(CVA6Cfg, hartid_t, id_t, readregflags_t), localparam type x_commit_t = `X_COMMIT_T(CVA6Cfg, hartid_t, id_t), localparam type x_result_t = `X_RESULT_T(CVA6Cfg, hartid_t, id_t, writeregflags_t), - localparam type cvxif_req_t = `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t), + localparam type cvxif_req_t = `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_t, x_commit_t), localparam type cvxif_resp_t = `CVXIF_RESP_T(CVA6Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t), // AXI Types parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth, @@ -108,38 +110,36 @@ module ariane import ariane_pkg::*; #( .noc_resp_i ( noc_resp_i ) ); - if (CVA6Cfg.CvxifEn) begin : gen_example_coprocessor - cvxif_example_coprocessor #( - .NrRgprPorts (CVA6Cfg.NrRgprPorts), - .XLEN (CVA6Cfg.XLEN), - .readregflags_t (readregflags_t), - .writeregflags_t (writeregflags_t), - .id_t (id_t), - .hartid_t (hartid_t), - .x_compressed_req_t (x_compressed_req_t), - .x_compressed_resp_t (x_compressed_resp_t), - .x_issue_req_t (x_issue_req_t), - .x_issue_resp_t (x_issue_resp_t), - .x_register_t (x_register_t), - .x_commit_t (x_commit_t), - .x_result_t (x_result_t), - .cvxif_req_t (cvxif_req_t), - .cvxif_resp_t (cvxif_resp_t) - ) i_cvxif_coprocessor ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .cvxif_req_i ( cvxif_req ), - .cvxif_resp_o ( cvxif_resp ) - ); - end else begin - always_comb begin - cvxif_resp = '0; - cvxif_resp.compressed_ready = 1'b1; - cvxif_resp.issue_ready = 1'b1; - cvxif_resp.register_ready = 1'b1; + if (CVA6Cfg.CvxifEn) begin: gen_cvxif + if (CVA6Cfg.CoproType == config_pkg::COPRO_EXAMPLE) begin: gen_COPRO_EXAMPLE + cvxif_example_coprocessor #( + .NrRgprPorts (CVA6Cfg.NrRgprPorts), + .XLEN (CVA6Cfg.XLEN), + .readregflags_t (readregflags_t), + .writeregflags_t (writeregflags_t), + .id_t (id_t), + .hartid_t (hartid_t), + .x_compressed_req_t (x_compressed_req_t), + .x_compressed_resp_t (x_compressed_resp_t), + .x_issue_req_t (x_issue_req_t), + .x_issue_resp_t (x_issue_resp_t), + .x_register_t (x_register_t), + .x_commit_t (x_commit_t), + .x_result_t (x_result_t), + .cvxif_req_t (cvxif_req_t), + .cvxif_resp_t (cvxif_resp_t) + ) i_cvxif_coprocessor ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .cvxif_req_i ( cvxif_req ), + .cvxif_resp_o ( cvxif_resp ) + ); + end else begin: gen_COPRO_NONE + assign cvxif_resp = '{compressed_ready: 1'b1, issue_ready: 1'b1, register_ready: 1'b1, default: '0}; end + end else begin: gen_no_cvxif + assign cvxif_resp = '0; end - endmodule // ariane diff --git a/corev_apu/src/axi_riscv_atomics b/corev_apu/src/axi_riscv_atomics deleted file mode 160000 index 550881f12e2..00000000000 --- a/corev_apu/src/axi_riscv_atomics +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 550881f12e22dfae405612fc1df6368f4c003e68 diff --git a/corev_apu/tb/ariane_gate_tb.sv b/corev_apu/tb/ariane_gate_tb.sv index 958a56fc143..d0774432962 100644 --- a/corev_apu/tb/ariane_gate_tb.sv +++ b/corev_apu/tb/ariane_gate_tb.sv @@ -24,10 +24,13 @@ import uvm_pkg::*; `timescale 1ns/1ns +`ifndef READ_ELF_T +`define READ_ELF_T import "DPI-C" function void read_elf(input string filename); import "DPI-C" function byte get_section(output longint address, output longint len); import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]); import "DPI-C" function string getenv(input string env_name); +`endif module ariane_gate_tb; diff --git a/corev_apu/tb/ariane_soc_pkg.sv b/corev_apu/tb/ariane_soc_pkg.sv index d20b6a6b8bd..7785485310e 100644 --- a/corev_apu/tb/ariane_soc_pkg.sv +++ b/corev_apu/tb/ariane_soc_pkg.sv @@ -29,12 +29,12 @@ package ariane_soc; PLIC = 6, CLINT = 7, ROM = 8, - Debug = 9 + Debug = 9, + HPS = 10 } axi_slaves_t; localparam NB_PERIPHERALS = Debug + 1; - localparam logic[63:0] DebugLength = 64'h1000; localparam logic[63:0] ROMLength = 64'h10000; localparam logic[63:0] CLINTLength = 64'hC0000; @@ -44,6 +44,7 @@ package ariane_soc; localparam logic[63:0] SPILength = 64'h800000; localparam logic[63:0] EthernetLength = 64'h10000; localparam logic[63:0] GPIOLength = 64'h1000; + localparam logic[63:0] HPSLength = 64'h800000; `ifdef NEXYS_VIDEO localparam logic[63:0] DRAMLength = 64'h20000000; // 512MByte of DDR on Nexys video board `else @@ -63,7 +64,8 @@ package ariane_soc; SPIBase = 64'h2000_0000, EthernetBase = 64'h3000_0000, GPIOBase = 64'h4000_0000, - DRAMBase = 64'h8000_0000 + DRAMBase = 64'h8000_0000, + HPSBase = 64'hFF80_0000 } soc_bus_start_t; localparam NrRegion = 1; diff --git a/corev_apu/tb/ariane_tb.cpp b/corev_apu/tb/ariane_tb.cpp index 8de0c5b20fb..3653eaa5164 100644 --- a/corev_apu/tb/ariane_tb.cpp +++ b/corev_apu/tb/ariane_tb.cpp @@ -120,7 +120,7 @@ class preload_aware_dtm_t : public dtm_t { preload_aware_dtm_t(int argc, char **argv) : dtm_t(argc, argv) {} bool is_address_preloaded(addr_t taddr, size_t len) override { return true; } // We do not want to reset the hart here as the reset function in `dtm_t` seems to disregard - // the privilege level and in general does not perform propper reset (despite the name). + // the privilege level and in general does not perform proper reset (despite the name). // As all our binaries in preloading will always start at the base of DRAM this should not // be such a big problem. void reset() {} @@ -351,7 +351,7 @@ int main(int argc, char **argv) { try { read_section_void(addr, (void *) MEM_USER , mem_size); } catch (...){ - std::cerr << "No user memory instanciated ...\n"; + std::cerr << "No user memory instantiated ...\n"; } } diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv index 1df11e75782..6e1d7a283cd 100644 --- a/corev_apu/tb/ariane_testharness.sv +++ b/corev_apu/tb/ariane_testharness.sv @@ -15,6 +15,7 @@ `include "axi/assign.svh" `include "rvfi_types.svh" +`include "iti_types.svh" `ifdef VERILATOR `include "custom_uvm_macros.svh" @@ -46,6 +47,8 @@ module ariane_testharness #( localparam type rvfi_instr_t = `RVFI_INSTR_T(CVA6Cfg); localparam type rvfi_csr_elmt_t = `RVFI_CSR_ELMT_T(CVA6Cfg); localparam type rvfi_csr_t = `RVFI_CSR_T(CVA6Cfg, rvfi_csr_elmt_t); + localparam type rvfi_to_iti_t = `RVFI_TO_ITI_T(CVA6Cfg); + localparam type iti_to_encoder_t = `ITI_TO_ENCODER_T(CVA6Cfg); // RVFI PROBES localparam type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg); @@ -130,7 +133,7 @@ module ariane_testharness #( initial begin if (!$value$plusargs("jtag_rbb_enable=%b", jtag_enable)) jtag_enable = 'h0; if ($test$plusargs("debug_disable")) debug_enable = 'h0; else debug_enable = 'h1; - if (CVA6Cfg.XLEN != 32 & CVA6Cfg.XLEN != 64) $error("CVA6Cfg.XLEN different from 32 and 64"); + if (!CVA6Cfg.IS_XLEN32 & !CVA6Cfg.IS_XLEN64) $error("CVA6Cfg.XLEN different from 32 and 64"); end // debug if MUX @@ -625,6 +628,8 @@ module ariane_testharness #( rvfi_probes_t rvfi_probes; rvfi_csr_t rvfi_csr; rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr; + rvfi_to_iti_t rvfi_to_iti; + iti_to_encoder_t iti_to_encoder; ariane #( .CVA6Cfg ( CVA6Cfg ), @@ -672,7 +677,117 @@ module ariane_testharness #( end end + cva6_iti #( + .CVA6Cfg (CVA6Cfg), + .CAUSE_LEN (iti_pkg::CAUSE_LEN), + .ITYPE_LEN (iti_pkg::ITYPE_LEN), + .IRETIRE_LEN (iti_pkg::IRETIRE_LEN), + .block_mode(0), + .rvfi_to_iti_t(rvfi_to_iti_t), + .iti_to_encoder_t(iti_to_encoder_t) + ) i_cva6_iti ( + .clk_i (clk_i), + .rst_ni (ndmreset_n), + // inputs from rvfi + .valid_i(rvfi_to_iti.valid), + .rvfi_to_iti_i(rvfi_to_iti), + .valid_o(), + .iti_to_encoder_o(iti_to_encoder) + ); + + logic packet_valid; + te_pkg::it_packet_type_e [0:0] packet_type; + logic [te_pkg::P_LEN-1:0] packet_length; + logic [te_pkg::PAYLOAD_LEN-1:0] packet_payload; + + rv_tracer #( + .N(1), + .ONLY_BRANCHES(1) + ) i_encoder( + .clk_i (clk_i), + .rst_ni (rst_ni), + .valid_i (iti_to_encoder.valid), + .itype_i (iti_to_encoder.itype), + .cause_i (iti_to_encoder.cause), + .tval_i (iti_to_encoder.tval), + .priv_i (iti_to_encoder.priv), + .iaddr_i (iti_to_encoder.iaddr), + .iretire_i (iti_to_encoder.iretire), + .ilastsize_i (iti_to_encoder.ilastsize), + .time_i (iti_to_encoder.cycles), + .tvec_i ('0), + .epc_i ('0), + .encapsulator_ready_i('1), + .paddr_i ('0), + .pwrite_i ('0), + .psel_i ('0), + .penable_i ('0), + .pwdata_i ('0), + .packet_valid_o (packet_valid), + .packet_type_o (packet_type), + .packet_length_o (packet_length), + .packet_payload_o (packet_payload), + .stall_o (), + .pready_o (), + .prdata_o () + ); + logic encap_valid; + encap_pkg::encap_fifo_entry_s encap_fifo_entry_i; + encap_pkg::encap_fifo_entry_s encap_fifo_entry_o; + logic encap_fifo_full; + logic encap_fifo_empty; + logic encap_fifo_pop; + + encapsulator i_encapsulator ( + .clk_i (clk_i), + .valid_i (packet_valid), + .packet_length_i (packet_length), + .flow_i ('0), + .timestamp_present_i('1), + //.srcid_i(), + .timestamp_i (rvfi_to_iti.cycles), + //.type_i(), + .trace_payload_i (packet_payload), + .valid_o (encap_valid), + .encap_fifo_entry_o (encap_fifo_entry_i) + ); + + fifo_v3 # ( + .DEPTH(16), + .dtype(encap_pkg::encap_fifo_entry_s) + ) i_fifo_encap ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .flush_i ('0), + .testmode_i('0), + .full_o (encap_fifo_full), + .empty_o (encap_fifo_empty), + .usage_o (), + .data_i (encap_fifo_entry_i), + .push_i (encap_valid), + .data_o (encap_fifo_entry_o), + .pop_i (encap_fifo_pop) + ); + localparam DATA_LEN = 8; + + logic slicer_valid; + logic [DATA_LEN-1:0] slice; + logic [$clog2(DATA_LEN)-4:0] valid_bytes; + + slicer_DPTI #( + .SLICE_LEN(DATA_LEN), + .NO_TIME ('0) + ) i_slicer ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .valid_i (!encap_fifo_empty), + .encap_fifo_entry_i(encap_fifo_entry_o), + .fifo_full_i ('0), // usrFull DPTI in ariane_xilinx + .valid_o (slicer_valid), + .slice_o (slice), + .done_o (encap_fifo_pop) + ); cva6_rvfi #( .CVA6Cfg (CVA6Cfg), @@ -680,13 +795,15 @@ module ariane_testharness #( .rvfi_csr_t(rvfi_csr_t), .rvfi_probes_instr_t(rvfi_probes_instr_t), .rvfi_probes_csr_t(rvfi_probes_csr_t), - .rvfi_probes_t(rvfi_probes_t) + .rvfi_probes_t(rvfi_probes_t), + .rvfi_to_iti_t(rvfi_to_iti_t) ) i_cva6_rvfi ( - .clk_i (clk_i), - .rst_ni (rst_ni), + .clk_i (clk_i), + .rst_ni (rst_ni), .rvfi_probes_i(rvfi_probes), - .rvfi_instr_o(rvfi_instr), - .rvfi_csr_o(rvfi_csr) + .rvfi_instr_o (rvfi_instr), + .rvfi_to_iti_o (rvfi_to_iti), + .rvfi_csr_o (rvfi_csr) ); rvfi_tracer #( diff --git a/corev_apu/tb/common/mock_uart.sv b/corev_apu/tb/common/mock_uart.sv index 0124ea714ef..839b41f0e15 100644 --- a/corev_apu/tb/common/mock_uart.sv +++ b/corev_apu/tb/common/mock_uart.sv @@ -10,7 +10,7 @@ // // Author: Florian Zaruba, ETH Zurich // Date: 28/09/2018 -// Description: Mock replacement for UART in testbench (not synthesiesable!) +// Description: Mock replacement for UART in testbench (not synthesizable!) module mock_uart ( input logic clk_i, diff --git a/corev_apu/tb/common/tb_amoport.sv b/corev_apu/tb/common/tb_amoport.sv index 18a59636ffe..604f211fc9f 100644 --- a/corev_apu/tb/common/tb_amoport.sv +++ b/corev_apu/tb/common/tb_amoport.sv @@ -88,7 +88,7 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #( else size = 'h2; - // For LRs/SCs, choose from only 4 adresses, + // For LRs/SCs, choose from only 4 addresses, // so that valid LR/SC combinations become more likely. // Note: AMOs to address 0 are not supported in axi_riscv_atomics module // so we start at 8 (for alignment purposes) @@ -97,7 +97,7 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #( else void'(randomize(paddr) with {paddr >= 8; paddr < (MemWords<<$clog2(CVA6Cfg.XLEN/8));}); - // Align adress + // Align address if (size == 2) paddr[1:0] = '0; else diff --git a/corev_apu/tb/common/tb_dcache_pkg.sv b/corev_apu/tb/common/tb_dcache_pkg.sv index 7584d81a868..0597824453b 100644 --- a/corev_apu/tb/common/tb_dcache_pkg.sv +++ b/corev_apu/tb/common/tb_dcache_pkg.sv @@ -31,7 +31,7 @@ package tb_pkg; time CLK_LO = 5ns; // set clock low time time CLK_PERIOD = CLK_HI+CLK_LO; time APPL_DEL = 2ns; // set stimuli application delay - time ACQ_DEL = 8ns; // set response aquisition delay + time ACQ_DEL = 8ns; // set response acquisition delay parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation... diff --git a/corev_apu/tb/common/tb_writeport.sv b/corev_apu/tb/common/tb_writeport.sv index 46cb3628759..82cc10bbee1 100644 --- a/corev_apu/tb/common/tb_writeport.sv +++ b/corev_apu/tb/common/tb_writeport.sv @@ -152,7 +152,7 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( dut_req_port_o.data_wdata = 'x; endtask : genSeqWrite - // Repeadedly write to the same address + // Repeatedly write to the same address task automatic genConstWrite(); automatic logic [CVA6Cfg.XLEN-1:0] val; paddr = CachedAddrBeg; diff --git a/corev_apu/tb/dpi/elfloader.cc b/corev_apu/tb/dpi/elfloader.cc index f137015a5e0..8cdf6a4cbc8 100644 --- a/corev_apu/tb/dpi/elfloader.cc +++ b/corev_apu/tb/dpi/elfloader.cc @@ -50,7 +50,7 @@ extern "C" char get_section (long long* address, long long* len) { } extern "C" void read_section (long long address, const svOpenArrayHandle buffer) { - // get actual poitner + // get actual pointer void* buf = svGetArrayPtr(buffer); // check that the address points to a section assert(mems.count(address) > 0); diff --git a/corev_apu/tb/rvfi_tracer.sv b/corev_apu/tb/rvfi_tracer.sv index 13d7183fa6c..1fdd099f25b 100644 --- a/corev_apu/tb/rvfi_tracer.sv +++ b/corev_apu/tb/rvfi_tracer.sv @@ -69,6 +69,39 @@ module rvfi_tracer #( logic[31:0] end_of_test_q; logic[31:0] end_of_test_d; + function automatic logic fp_instr_writes_gpr(logic [31:0] insn); + logic [6:0] opcode; + logic [4:0] funct5; + logic [2:0] rm; + + opcode = insn[6:0]; + funct5 = insn[31:27]; + rm = insn[14:12]; + + if (opcode != riscv::OpcodeOpFp) begin + return 1'b0; + end + + if (funct5 == 5'b11000) begin + return 1'b1; + end + + if (funct5 == 5'b10100) begin + return 1'b1; + end + + if (funct5 == 5'b11100) begin + if ((rm == 3'b000) || (rm == 3'b001)) begin + return 1'b1; + end + if (CVA6Cfg.XF16ALT && ((rm == 3'b100) || (rm == 3'b101))) begin + return 1'b1; + end + end + + return 1'b0; + endfunction + assign end_of_test_o = end_of_test_d; always_ff @(posedge clk_i) begin @@ -77,6 +110,7 @@ module rvfi_tracer #( pc64 = {{CVA6Cfg.XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata}; // print the instruction information if the instruction is valid or a trap is taken if (rvfi_i[i].valid) begin + logic dest_is_fp; // Instruction information if (rvfi_i[i].intr[2]) begin $fwrite(f, "core INTERRUPT 0: 0x%h (0x%h) DASM(%h)\n", @@ -96,6 +130,7 @@ module rvfi_tracer #( end // Decode instruction to know if destination register is FP register. // Handle both uncompressed and compressed instructions. + dest_is_fp = 1'b0; if ( rvfi_i[i].insn[6:0] == 7'b1001111 || rvfi_i[i].insn[6:0] == 7'b1001011 || rvfi_i[i].insn[6:0] == 7'b1000111 || @@ -104,23 +139,31 @@ module rvfi_tracer #( (rvfi_i[i].insn[6:0] == 7'b1010011 && rvfi_i[i].insn[31:26] != 6'b111000 && rvfi_i[i].insn[31:26] != 6'b101000 && rvfi_i[i].insn[31:26] != 6'b110000) || - (rvfi_i[i].insn[0] == 1'b0 && ((rvfi_i[i].insn[15:13] == 3'b001 && CVA6Cfg.XLEN == 64) || - (rvfi_i[i].insn[15:13] == 3'b011 && CVA6Cfg.XLEN == 32) ))) begin + (rvfi_i[i].insn[0] == 1'b0 && ((rvfi_i[i].insn[15:13] == 3'b001 && CVA6Cfg.IS_XLEN64) || + (rvfi_i[i].insn[15:13] == 3'b011 && CVA6Cfg.IS_XLEN32) ))) begin + if (fp_instr_writes_gpr(rvfi_i[i].insn)) begin + dest_is_fp = 1'b0; + end else begin + dest_is_fp = 1'b1; + end + end + + if (dest_is_fp) begin $fwrite(f, " f%d 0x%h", rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata); end else if (rvfi_i[i].rd_addr != 0) begin $fwrite(f, " x%d 0x%h", rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata); if (rvfi_i[i].mem_rmask != 0) begin $fwrite(f, " mem 0x%h", rvfi_i[i].mem_addr); end - end else begin - if (rvfi_i[i].mem_wmask != 0) begin - $fwrite(f, " mem 0x%h 0x%h", rvfi_i[i].mem_addr, rvfi_i[i].mem_wdata); - if (TOHOST_ADDR != '0 && - rvfi_i[i].mem_paddr == TOHOST_ADDR && - rvfi_i[i].mem_wdata[0] == 1'b1) begin - end_of_test_q <= rvfi_i[i].mem_wdata[31:0]; - $display("*** [rvfi_tracer] INFO: Simulation terminated after %d cycles!\n", cycles); - end + end + // Handle memory writes (including for AMO instructions which have both rd and mem_wmask) + if (rvfi_i[i].mem_wmask != 0) begin + $fwrite(f, " mem 0x%h 0x%h", rvfi_i[i].mem_addr, rvfi_i[i].mem_wdata); + if (TOHOST_ADDR != '0 && + rvfi_i[i].mem_paddr == TOHOST_ADDR && + rvfi_i[i].mem_wdata[0] == 1'b1) begin + end_of_test_q <= rvfi_i[i].mem_wdata[31:0]; + $display("*** [rvfi_tracer] INFO: Simulation terminated after %d cycles!\n", cycles); end end $fwrite(f, "\n"); @@ -136,6 +179,11 @@ module rvfi_tracer #( 32'h6: cause = "ST_ADDR_MISALIGNED"; 32'h7: cause = "ST_ACCESS_FAULT"; 32'hb: cause = "ENV_CALL_MMODE"; + 32'h8: cause = "ENV_CALL_UMODE"; + 32'h9: cause = "ENV_CALL_SMODE"; + 32'hc: cause = "INSTR_PAGE_FAULT"; + 32'hd: cause = "LOAD_PAGE_FAULT"; + 32'hf: cause = "STORE_PAGE_FAULT"; endcase; if (rvfi_i[i].insn[1:0] != 2'b11) begin $fwrite(f, "%s exception @ 0x%h (0x%h)\n", cause, pc64, rvfi_i[i].insn[15:0]); @@ -159,12 +207,13 @@ module rvfi_tracer #( // Trace any custom signals // Define signals to be traced by adding them into debug and name arrays - string name[0:10]; - logic[63:0] debug[0:10], debug_previous[0:10]; + localparam int unsigned DEBUG_SIZE = 11; + string name [0:DEBUG_SIZE-1]; + logic [63:0] debug [0:DEBUG_SIZE-1], debug_previous [0:DEBUG_SIZE-1]; always_ff @(posedge clk_i) begin if (cycles > DEBUG_START && cycles < DEBUG_STOP) - for (int index = 0; index < 100; index++) + for (int index = 0; index < DEBUG_SIZE; index++) if (debug_previous[index] != debug[index]) $fwrite(f, "%d %s %x\n", cycles, name[index], debug[index]); debug_previous <= debug; diff --git a/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv b/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv index 994190e314a..300c8d1f8ea 100644 --- a/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv +++ b/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv @@ -151,7 +151,7 @@ module mem_emul import ariane_pkg::*; import wt_cache_pkg::*; #( infifo_data.rtype = ICACHE_INV_REQ; // since we do not keep a mirror tag table here, - // we allways invalidate all ways of the aliased index. + // we always invalidate all ways of the aliased index. // this is not entirely correct and will produce // too many invalidations infifo_data.inv.idx = rand_addr_q[CVA6Cfg.ICACHE_INDEX_WIDTH-1:0]; diff --git a/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv b/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv index ae461862ab8..488d4713a97 100644 --- a/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv +++ b/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv @@ -30,7 +30,7 @@ package tb_pkg; time CLK_HI = 5ns; // set clock high time time CLK_LO = 5ns; // set clock low time time APPL_DEL = 2ns; // set stimuli application delay - time ACQ_DEL = 8ns; // set response aquisition delay + time ACQ_DEL = 8ns; // set response acquisition delay parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation... diff --git a/corev_apu/tb/tb_serdiv/hdl/tb.sv b/corev_apu/tb/tb_serdiv/hdl/tb.sv index a01a1bfe3bc..75903539461 100644 --- a/corev_apu/tb/tb_serdiv/hdl/tb.sv +++ b/corev_apu/tb/tb_serdiv/hdl/tb.sv @@ -188,7 +188,7 @@ module tb; $display("TB> response acquisition started"); /////////////////////////////////////////////// - // acquisiton and verification + // acquisition and verification /////////////////////////////////////////////// repeat(4) begin diff --git a/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv b/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv index 9767d472e27..15ff02e8196 100644 --- a/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv +++ b/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv @@ -33,7 +33,7 @@ package tb_pkg; time CLK_LO = 5ns; // set clock low time time CLK_PERIOD = CLK_HI+CLK_LO; time APPL_DEL = 2ns; // set stimuli application delay - time ACQ_DEL = 8ns; // set response aquisition delay + time ACQ_DEL = 8ns; // set response acquisition delay parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation... diff --git a/corev_apu/tb/tb_wb_dcache/hdl/tb.sv b/corev_apu/tb/tb_wb_dcache/hdl/tb.sv index 37e992c220f..9cba78c7db5 100644 --- a/corev_apu/tb/tb_wb_dcache/hdl/tb.sv +++ b/corev_apu/tb/tb_wb_dcache/hdl/tb.sv @@ -318,7 +318,7 @@ module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #( amo_op_a_u = $unsigned(amo_shadow[31:0]); amo_op_b_u = $unsigned(amo_req_i.operand_b[31:0]); - // The result that is expected to be returned by AMO and evantually to be stored in rd. + // The result that is expected to be returned by AMO and eventually to be stored in rd. // For most AMOs, this is the previous memory content. // RISC-V spec requires: "For RV64, 32-bit AMOs always sign-extend the value placed in rd." amo_exp_result = amo_op_a; diff --git a/corev_apu/tb/tb_wb_dcache/tb.list b/corev_apu/tb/tb_wb_dcache/tb.list index d08c0adaef7..8e67d1e4c58 100644 --- a/corev_apu/tb/tb_wb_dcache/tb.list +++ b/corev_apu/tb/tb_wb_dcache/tb.list @@ -39,12 +39,12 @@ hdl/cv64a6_config_pkg.sv ../../../vendor/pulp-platform/common_cells/src/stream_demux.sv ../../../core/cache_subsystem/axi_adapter.sv ../../../common/local/util/sram.sv -../../src/axi_riscv_atomics/src/axi_res_tbl.sv -../../src/axi_riscv_atomics/src/axi_riscv_amos.sv -../../src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv -../../src/axi_riscv_atomics/src/axi_riscv_lrsc.sv -../../src/axi_riscv_atomics/src/axi_riscv_atomics.sv -../../src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_res_tbl.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos_alu.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv ../common/tb_dcache_pkg.sv ../common/tb_readport.sv diff --git a/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv b/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv index f3279f3439f..f47b77fa4e8 100644 --- a/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv +++ b/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv @@ -279,7 +279,7 @@ module tb import ariane_pkg::*; import wt_cache_pkg::*; import tb_pkg::*; #()(); amo_op_a_u = $unsigned(amo_shadow[31:0]); amo_op_b_u = $unsigned(amo_req_i.operand_b[31:0]); - // The result that is expected to be returned by AMO and evantually to be stored in rd. + // The result that is expected to be returned by AMO and eventually to be stored in rd. // For most AMOs, this is the previous memory content. // RISC-V spec requires: "For RV64, 32-bit AMOs always sign-extend the value placed in rd." amo_exp_result = amo_op_a; diff --git a/corev_apu/tb/tb_wt_axi_dcache/tb.list b/corev_apu/tb/tb_wt_axi_dcache/tb.list index 50a6df5c25d..5d951111f06 100644 --- a/corev_apu/tb/tb_wt_axi_dcache/tb.list +++ b/corev_apu/tb/tb_wt_axi_dcache/tb.list @@ -40,12 +40,12 @@ ../../src/tech_cells_generic/src/rtl/tc_sram.sv ../../../common/local/util/tc_sram_wrapper.sv ../../../common/local/util/sram.sv -../../src/axi_riscv_atomics/src/axi_res_tbl.sv -../../src/axi_riscv_atomics/src/axi_riscv_amos.sv -../../src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv -../../src/axi_riscv_atomics/src/axi_riscv_lrsc.sv -../../src/axi_riscv_atomics/src/axi_riscv_atomics.sv -../../src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_res_tbl.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos_alu.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics.sv +../../../vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv ../common/tb_dcache_pkg.sv ../common/tb_readport.sv diff --git a/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv b/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv index f7094bcc7c5..92f4c7cc608 100644 --- a/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv +++ b/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv @@ -159,7 +159,7 @@ module tb_mem import tb_pkg::*; import ariane_pkg::*; import wt_cache_pkg::*;#( rand_addr_q <= lval<<3; // with the current TB setup, we cannot invalidate a memory location if a write response to the same address is - // in flight, since this could lead to an incosistent state between the real memory and the shadow memory view. + // in flight, since this could lead to an inconsistent state between the real memory and the shadow memory view. // the workaround is not to overwrite shadow memory regions that are still pending in the write buffer // this can be improved. for(int k=0; k<8; k++) begin @@ -205,7 +205,7 @@ module tb_mem import tb_pkg::*; import ariane_pkg::*; import wt_cache_pkg::*;#( infifo_data.rtype = DCACHE_INV_REQ; // since we do not keep a mirror tag table here, - // we allways invalidate all ways of the aliased index. + // we always invalidate all ways of the aliased index. // this is not entirely correct and will produce // too many invalidations infifo_data.inv.idx = rand_addr_q[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0]; diff --git a/docs/01_cva6_user/AXI_Interface.rst b/docs/01_cva6_user/AXI_Interface.rst index 09c8f51a30f..b7a9fa5f5cd 100644 --- a/docs/01_cva6_user/AXI_Interface.rst +++ b/docs/01_cva6_user/AXI_Interface.rst @@ -15,7 +15,7 @@ Introduction ------------ In this chapter, we describe in detail the restriction that apply to the supported features. -In order to understand how the AXI memory interface behaves in CVA6, it is necessary to read the AMBA AXI and ACE Protocol Specification (https://developer.arm.com/documentation/ihi0022/hc) and this chapter. +In order to understand how the AXI memory interface behaves in CVA6, it is necessary to read the AXI and ACE Protocol Specification (https://developer.arm.com/documentation/ihi0022/hc) and this chapter. *Applicability of this chapter to configurations:* @@ -30,7 +30,7 @@ In order to understand how the AXI memory interface behaves in CVA6, it is neces About the AXI4 protocol ~~~~~~~~~~~~~~~~~~~~~~~ -The AMBA AXI protocol supports high-performance, high-frequency system designs for communication between Manager and Subordinate components. +The AXI protocol supports high-performance, high-frequency system designs for communication between Manager and Subordinate components. The AXI protocol features are: @@ -59,7 +59,7 @@ AXI4 and CVA6 The AXI bus protocol is used with the CVA6 processor as a memory interface. Since the processor is the one that initiates the connection with the memory, it will have a manager interface to send requests to the subordinate, which will be the memory. -Features supported by CVA6 are the ones in the AMBA AXI4 specification and the Atomic Operation feature from AXI5. With restriction that apply to some features. +Features supported by CVA6 are the ones in the AXI4 specification and the Atomic Operation feature from AXI5. With restriction that apply to some features. This doesn’t mean that all the full set of signals available on an AXI interface are supported by the CVA6. Nevertheless, all required AXI signals are implemented. @@ -510,7 +510,7 @@ for each 8 bits of the write data bus, therefore ``WSTRB[n]`` corresponds to ``W *The size of transactions performed by cva6 is equal to the number of data byte lanes containing valid information.* *This means 1, 2, 4, ... or (AXI_DATA_WIDTH/8) byte lanes containing valid information.* -*CVA6 doesn't perform unaligned memory acces, therefore the WSTRB take only combination of aligned access* +*CVA6 doesn't perform unaligned memory access, therefore the WSTRB take only combination of aligned access* *If(RV32) WSTRB < 255 (Since AWSIZE lower than 3, so the data bus cannot have more than 4 valid byte lanes)* @@ -596,7 +596,7 @@ If the CVA6 requires ordering between transactions that have no ordering guarant Memory locations and Peripheral regions (Section A6.2) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The address map in AMBA is made up of Memory locations and Peripheral regions. But the AXI is associated to the memory interface of CVA6. +The address maps in some bus specifications can differentiate Memory locations and Peripheral regions. But the AXI is associated to the memory interface of CVA6. A Memory location has all of the following properties: @@ -640,7 +640,7 @@ An interface that exhibits Ordered Write Observation gives guarantees for write Atomic transactions (Section E1.1) ----------------------------------- -AMBA 5 introduces Atomic transactions, which perform more than just a single access and have an operation that is associated with the transaction. Atomic transactions enable sending the operation to the data, permitting the operation to be performed closer to where the data is located. Atomic transactions are suited to situations where the data is located a significant distance from the agent that must perform the operation. +AXI 5 introduces Atomic transactions, which perform more than just a single access and have an operation that is associated with the transaction. Atomic transactions enable sending the operation to the data, permitting the operation to be performed closer to where the data is located. Atomic transactions are suited to situations where the data is located a significant distance from the agent that must perform the operation. *If(RVA) AWATOP = 0 (If AMO instructions are not supported, CVA6 cannot perform Atomic transaction)* diff --git a/docs/01_cva6_user/CSR_Performance_Counters.rst b/docs/01_cva6_user/CSR_Performance_Counters.rst index 46455c74e22..1b55bc9a43f 100644 --- a/docs/01_cva6_user/CSR_Performance_Counters.rst +++ b/docs/01_cva6_user/CSR_Performance_Counters.rst @@ -97,7 +97,7 @@ Each of the six generic performance counters is able to monitor events from one Controlling the counters from software --------------------------------------- -All performance counters are enabled after reset. The ``mcountinhibit`` CSR at address ``0x320`` controls which of the performance counters increment as described in the RISC-V Privileged Specification, version 1.11 (see Machine Counter-Inhibit CSR, Section 3.1.12). For instance, bit 0 is set to 0 for ``mcycle(h)`` to increment as usual, bit 2 for ``minstrert(h)`` and bit X for event counter mhpmcounterX(h). +All performance counters are enabled after reset. The ``mcountinhibit`` CSR at address ``0x320`` controls which of the performance counters increment as described in the RISC-V Privileged Specification, version 1.11 (see Machine Counter-Inhibit CSR, Section 3.1.12). For instance, bit 0 is set to 0 for ``mcycle(h)`` to increment as usual, bit 2 for ``minstret(h)`` and bit X for event counter mhpmcounterX(h). The lower 32 bits of all counters can be accessed through the base register, whereas the upper 32 bits are accessed through the h-register. diff --git a/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst b/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst index f7f3805ff4b..374ed8156bb 100644 --- a/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst +++ b/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst @@ -24,7 +24,7 @@ access a CSR with a higher privilege level than the core is currently running in will throw an illegal instruction exception. This is largely a moot point for the CV32E40P as it only supports machine and debug modes. The remaining letters indicate the read and/or write behavior of the CSR when accessed by -the indicated or higher privilge level: +the indicated or higher privilege level: * **RW**: CSR is **read-write**. That is, CSR instructions (e.g. csrrw) may write any value and that value will be returned on a subsequent read (unless @@ -86,7 +86,7 @@ Register Summary "``pmpcfg2``", "0x3A2", "32", "RW", "0x00000000", "Physical Memory Protection Config 2" "``pmpcfg3``", "0x3A3", "32", "RW", "0x00000000", "Physical Memory Protection Config 3" "``pmpaddr[16]``", "0x3B0 [+ i*0x1]", "32", "RW", "0x00000000", "Physical Memory Protection Address" - "``icache``", "0x700", "32", "RW", "0x00000001", "Instuction Cache" + "``icache``", "0x700", "32", "RW", "0x00000001", "Instruction Cache" "``dcache``", "0x701", "32", "RW", "0x00000001", "Data Cache" "``tselect``", "0x7A0", "32", "RW", "0x00000000", "Trigger Select" "``tdata1``", "0x7A1", "32", "RW", "0x00000000", "Trigger Data 1" @@ -596,7 +596,7 @@ Supervisor Interrupt Pending (``sip``) :Supervisor-level Software Interrupt Pending (``SSIP``): SSIP is the interrupt-pending bit for supervisor-level software interrupts. -:``USIP``: A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit +:``USIP``: A user-level software interrupt is triggered on the current hart by writing 1 to its user software interrupt-pending (USIP) bit Supervisor Address Translation and Protection (``satp``) @@ -878,7 +878,7 @@ Machine Interrupt Enable (``mie``) :S-mode Software Interrupt Enable (``SSIE``): Enables supervisor mode software interrupts. -:``USIE``: enable U-mode software interrrupts +:``USIE``: enable U-mode software interrupts Machine Trap Vector (``mtvec``) @@ -1255,7 +1255,7 @@ Physical Memory Protection Address (``pmpaddr[16]``) :Address (``address``): Encodes bits 33-2 of a 34-bit physical address. -Instuction Cache (``icache``) +Instruction Cache (``icache``) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :Address Offset: 0x700 @@ -1432,7 +1432,7 @@ Debug Control and Status (``dcsr``) :Width (bits): 32 :Access Type: RW :Reset Value: 0x00000000 -:Description: Debug ontrol and status register. +:Description: Debug control and status register. .. csv-table:: :widths: auto @@ -1465,7 +1465,7 @@ Debug Control and Status (``dcsr``) "0b0000", "no_ext_debug", "There is no external debug support." "0b0100", "ext_debug_spec", "External debug support exists as it is described in the riscv-debug-release document." "0b1111", "ext_debug_no_spec", "There is external debug support, but it does not conform to any available version of the riscv-debug-release spec." -:Environment Breakpoint M-mode (``ebreakm``): Shows the behvior of the ``ebreak`` instruction in machine mode. +:Environment Breakpoint M-mode (``ebreakm``): Shows the behavior of the ``ebreak`` instruction in machine mode. .. csv-table:: The following table shows the bitfield encoding :widths: auto @@ -1474,7 +1474,7 @@ Debug Control and Status (``dcsr``) "0", "break_as_spec", "``ebreak`` instructions in M-mode behave as described in the Privileged Spec." "1", "break_to_debug", "``ebreak`` instructions in M-mode enter Debug Mode." -:Environment Breakpoint S-mode (``ebreaks``): Shows the behvior of the ``ebreak`` instruction in supervisor mode. +:Environment Breakpoint S-mode (``ebreaks``): Shows the behavior of the ``ebreak`` instruction in supervisor mode. .. csv-table:: The following table shows the bitfield encoding :widths: auto @@ -2303,7 +2303,7 @@ Machine Vendor ID (``mvendorid``) :Width (bits): 32 :Access Type: RO :Reset Value: 0x00000000 -:Description: This register provids the JEDEC manufacturer ID of the provider of the core. +:Description: This register provides the JEDEC manufacturer ID of the provider of the core. .. csv-table:: :widths: auto @@ -2315,7 +2315,7 @@ Machine Vendor ID (``mvendorid``) :Bank (``bank``): Contain encoding for number of one-byte continuation codes discarding the parity bit. -:Offset (``offset``): Contain encording for the final byte discarding the parity bit. +:Offset (``offset``): Contain encoding for the final byte discarding the parity bit. Machine Architecture ID (``marchid``) diff --git a/docs/01_cva6_user/CVX_Interface_Coprocessor.rst b/docs/01_cva6_user/CVX_Interface_Coprocessor.rst index ede928b0395..60c4e14efc2 100644 --- a/docs/01_cva6_user/CVX_Interface_Coprocessor.rst +++ b/docs/01_cva6_user/CVX_Interface_Coprocessor.rst @@ -1,203 +1,203 @@ -.. - Copyright (c) 2023 OpenHW Group - Copyright (c) 2023 Thales - - SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - -.. Level 1 - ======= - - Level 2 - ------- - - Level 3 - ~~~~~~~ - - Level 4 - ^^^^^^^ - -.. _cva6_cvx_interface_coprocessor: - -CV-X-IF Interface and Coprocessor -================================= - -The CV-X-IF interface of CVA6 allows to extend its supported instruction set -with external coprocessors. - -*Applicability of this chapter to configurations:* - -.. csv-table:: - :widths: auto - :align: left - :header: "Configuration", "Implementation" - - "CV32A60AX", "CV-X-IF included" - "CV32A60X", "CV-X-IF included" - "CV64A6_MMU", "CV-X-IF included" - - -CV-X-IF interface specification -------------------------------- - -Description -~~~~~~~~~~~ -This design specification presents global functionalities of -Core-V-eXtension-Interface (XIF, CVXIF, CV-X-IF, X-interface) in the CVA6 core. - -.. code-block:: text - - The CORE-V X-Interface is a RISC-V eXtension interface that provides a - generalized framework suitable to implement custom coprocessors and ISA - extensions for existing RISC-V processors. - - --core-v-xif Readme, https://github.com/openhwgroup/core-v-xif - -The specification of the CV-X-IF bus protocol can be found at [CV-X-IF]. - -CV-X-IF aims to: - -* Create interfaces to connect a coprocessor to the CVA6 to execute instructions. -* Offload CVA6 illegal instrutions to the coprocessor to be executed. -* Get the results of offloaded instructions from the coprocessor so they are written back into the CVA6 register file. -* Add standard RISC-V instructions unsupported by CVA6 or custom instructions and implement them in a coprocessor. -* Kill offloaded instructions to allow speculative execution in the coprocessor. (Unsupported in CVA6 yet) -* Connect the coprocessor to memory via the CVA6 Load and Store Unit. (Unsupported in CVA6 yet) - -The coprocessor operates like another functional unit so it is connected to -the CVA6 in the execute stage. - -Only the 3 mandatory interfaces from the CV-X-IF specification (issue, commit and result -) have been implemented. -Compressed interface, Memory Interface and Memory result interface are not yet -implemented in the CVA6. - -Supported Parameters -~~~~~~~~~~~~~~~~~~~~ -The following table presents CVXIF parameters supported by CVA6. - -=============== =========================== =============================================== -Signal Value Description -=============== =========================== =============================================== -**X_NUM_RS** int: 2 or 3 (configurable) | Number of register file read ports that can - | be used by the eXtension interface -**X_ID_WIDTH** int: 3 | Identification width for the eXtension - | interface -**X_MEM_WIDTH** n/a (feature not supported) | Memory access width for loads/stores via the - | eXtension interface -**X_RFR_WIDTH** int: ``XLEN`` (32 or 64) | Register file read access width for the - | eXtension interface -**X_RFW_WIDTH** int: ``XLEN`` (32 or 64) | Register file write access width for the - | eXtension interface -**X_MISA** logic[31:0]: 0x0000_0000 | MISA extensions implemented on the eXtension - | interface -=============== =========================== =============================================== - -CV-X-IF Enabling -~~~~~~~~~~~~~~~~ -CV-X-IF can be enabled or disabled via the ``CVA6ConfigCvxifEn`` parameter in the SystemVerilog source code. - -Illegal instruction decoding -~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The CVA6 decoder module detects illegal instructions for the CVA6, prepares exception field -with relevant information (exception code "ILLEGAL INSTRUCTION", instruction value). - -The exception valid flag is raised in CVA6 decoder when CV-X-IF is disabled. Otherwise -it is not raised at this stage because the decision belongs to the coprocessor -after the offload process. - -RS3 support -~~~~~~~~~~~ -The number of source registers used by the CV-X-IF coprocessor is configurable with 2 or -3 source registers. - -If CV-X-IF is enabled and configured with 3 source registers, -a third read port is added to the CVA6 general purpose register file. - -Description of interface connections between CVA6 and Coprocessor -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -In CVA6 execute stage, there is a new functional unit dedicated to drive the CV-X-IF interfaces. -Here is *how* and *to what* CV-X-IF interfaces are connected to the CVA6. - -* Issue interface - - Request - + | Operands are connected to ``issue_req.rs`` signals - + | Scoreboard transaction id is connected to ``issue_req.id`` signal. - | Therefore scoreboard ids and offloaded instruction ids are linked - | together (equal in this implementation). It allows the CVA6 to do out - | of order execution with the coprocessor in the same way as other - | functional units. - + | Undecoded instruction is connected to ``issue_req.instruction`` - + | Valid signal for CVXIF functional unit is connected to - | ``issue_req.valid`` - + | All ``issue_req.rs_valid`` signals are set to 1. The validity of source - | registers is assured by the validity of valid signal sent from issue stage. - - Response - + | If ``issue_resp.accept`` is set during a transaction (i.e. issue valid - | and ready are set), the offloaded instruction is accepted by the coprocessor - | and a result transaction will happen. - + | If ``issue_resp.accept`` is not set during a transaction, the offloaded - | instruction is illegal and an illegal instruction exception will be - | raised as soon as no result transaction are written on the writeback bus. - -* Commit interface - - | Valid signal of commit interface is connected to the valid signal of - | issue interface. - - | Id signal of commit interface is connected to issue interface id signal - | (i.e. scoreboard id). - - | Killing of offload instruction is never set. (Unsupported feature) - - | Therefore all accepted offloaded instructions are commited to their - | execution and no killing of instruction is possible in this implementation. - -* Result interface - - Request - + | Ready signal of result interface is always set as CVA6 is always ready - | to take a result from coprocessor for an accepted offloaded instruction. - - Response - + | Result response is directly connected to writeback bus of the CV-X-IF - | functionnal unit. - + | Valid signal of result interface is connected to valid signal of - | writeback bus. - + | Id signal of result interface is connected to scoreboard id of - | writeback bus. - + | Write enable signal of result interface is connected to a dedicated CV-X-IF WE - | signal in CVA6 which signals scoreboard if a writeback should happen - | or not to the CVA6 register file. - + | ``exccode`` and ``exc`` signal of result interface are connected to exception - | signals of writeback bus. Exception from coprocessor does not write - | the ``tval`` field in exception signal of writeback bus. - + | Three registers are added to hold illegal instruction information in - | case a result transaction and a non-accepted issue transaction happen - | in the same cycle. Result transactions will be written to the writeback - | bus in this case having priority over the non-accepted instruction due - | to being linked to an older offloaded instruction. Once the writeback - | bus is free, an illegal instruction exception will be raised thanks to - | information held in these three registers. - -Coprocessor recommendations for use with CVA6's CV-X-IF -------------------------------------------------------- - -CVA6 supports all coprocessors supporting the CV-X-IF specification with the exception of : - -* Coprocessor requiring the Memory interface and Memory result interface (not implemented in CVA6 yet). - - All memory transaction should happen via the Issue interface, i.e. Load into CVA6 register file - then initialize an issue transaction. -* Coprocessor requiring the Compressed interface (not implemented in CVA6 yet). - - RISC-V Compressed extension (RVC) is already implemented in CVA6. User Space for custom compressed instruction - is not big enough to have RVC and a custom compressed extension. -* Stateful coprocessors. - - CVA6 will commit on the Commit interface all its issue transactions. Speculation - informations are only kept in the CVA6 and speculation process is only done in CVA6. - The coprocessor shall be stateless otherwise it will not be able to revert its state if CVA6 kills an - in-flight instruction (in case of mispredict or flush). - -How to use CVA6 without CV-X-IF interface ------------------------------------------ -Select a configuration with ``CVA6ConfigCvxifEn`` parameter disabled or change it for your configuration. - -Never let the CV-X-IF interface unconnected with the ``CVA6ConfigCvxifEn`` parameter enabled. - -How to design a coprocessor for the CV-X-IF interface ------------------------------------------------------ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 Thales + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_cvx_interface_coprocessor: + +CV-X-IF Interface and Coprocessor +================================= + +The CV-X-IF interface of CVA6 allows to extend its supported instruction set +with external coprocessors. + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "CV-X-IF included" + "CV32A60X", "CV-X-IF included" + "CV64A6_MMU", "CV-X-IF included" + + +CV-X-IF interface specification +------------------------------- + +Description +~~~~~~~~~~~ +This design specification presents global functionalities of +Core-V-eXtension-Interface (XIF, CVXIF, CV-X-IF, X-interface) in the CVA6 core. + +.. code-block:: text + + The CORE-V X-Interface is a RISC-V eXtension interface that provides a + generalized framework suitable to implement custom coprocessors and ISA + extensions for existing RISC-V processors. + + --core-v-xif Readme, https://github.com/openhwgroup/core-v-xif + +The specification of the CV-X-IF bus protocol can be found at [CV-X-IF]. + +CV-X-IF aims to: + +* Create interfaces to connect a coprocessor to the CVA6 to execute instructions. +* Offload CVA6 illegal instructions to the coprocessor to be executed. +* Get the results of offloaded instructions from the coprocessor so they are written back into the CVA6 register file. +* Add standard RISC-V instructions unsupported by CVA6 or custom instructions and implement them in a coprocessor. +* Kill offloaded instructions to allow speculative execution in the coprocessor. (Unsupported in CVA6 yet) +* Connect the coprocessor to memory via the CVA6 Load and Store Unit. (Unsupported in CVA6 yet) + +The coprocessor operates like another functional unit so it is connected to +the CVA6 in the execute stage. + +Only the 3 mandatory interfaces from the CV-X-IF specification (issue, commit and result +) have been implemented. +Compressed interface, Memory Interface and Memory result interface are not yet +implemented in the CVA6. + +Supported Parameters +~~~~~~~~~~~~~~~~~~~~ +The following table presents CVXIF parameters supported by CVA6. + +=============== =========================== =============================================== +Signal Value Description +=============== =========================== =============================================== +**X_NUM_RS** int: 2 or 3 (configurable) | Number of register file read ports that can + | be used by the eXtension interface +**X_ID_WIDTH** int: 3 | Identification width for the eXtension + | interface +**X_MEM_WIDTH** n/a (feature not supported) | Memory access width for loads/stores via the + | eXtension interface +**X_RFR_WIDTH** int: ``XLEN`` (32 or 64) | Register file read access width for the + | eXtension interface +**X_RFW_WIDTH** int: ``XLEN`` (32 or 64) | Register file write access width for the + | eXtension interface +**X_MISA** logic[31:0]: 0x0000_0000 | MISA extensions implemented on the eXtension + | interface +=============== =========================== =============================================== + +CV-X-IF Enabling +~~~~~~~~~~~~~~~~ +CV-X-IF can be enabled or disabled via the ``CVA6ConfigCvxifEn`` parameter in the SystemVerilog source code. + +Illegal instruction decoding +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The CVA6 decoder module detects illegal instructions for the CVA6, prepares exception field +with relevant information (exception code "ILLEGAL INSTRUCTION", instruction value). + +The exception valid flag is raised in CVA6 decoder when CV-X-IF is disabled. Otherwise +it is not raised at this stage because the decision belongs to the coprocessor +after the offload process. + +RS3 support +~~~~~~~~~~~ +The number of source registers used by the CV-X-IF coprocessor is configurable with 2 or +3 source registers. + +If CV-X-IF is enabled and configured with 3 source registers, +a third read port is added to the CVA6 general purpose register file. + +Description of interface connections between CVA6 and Coprocessor +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +In CVA6 execute stage, there is a new functional unit dedicated to drive the CV-X-IF interfaces. +Here is *how* and *to what* CV-X-IF interfaces are connected to the CVA6. + +* Issue interface + - Request + + | Operands are connected to ``issue_req.rs`` signals + + | Scoreboard transaction id is connected to ``issue_req.id`` signal. + | Therefore scoreboard ids and offloaded instruction ids are linked + | together (equal in this implementation). It allows the CVA6 to do out + | of order execution with the coprocessor in the same way as other + | functional units. + + | Undecoded instruction is connected to ``issue_req.instruction`` + + | Valid signal for CVXIF functional unit is connected to + | ``issue_req.valid`` + + | All ``issue_req.rs_valid`` signals are set to 1. The validity of source + | registers is assured by the validity of valid signal sent from issue stage. + - Response + + | If ``issue_resp.accept`` is set during a transaction (i.e. issue valid + | and ready are set), the offloaded instruction is accepted by the coprocessor + | and a result transaction will happen. + + | If ``issue_resp.accept`` is not set during a transaction, the offloaded + | instruction is illegal and an illegal instruction exception will be + | raised as soon as no result transaction are written on the writeback bus. + +* Commit interface + - | Valid signal of commit interface is connected to the valid signal of + | issue interface. + - | Id signal of commit interface is connected to issue interface id signal + | (i.e. scoreboard id). + - | Killing of offload instruction is never set. (Unsupported feature) + - | Therefore all accepted offloaded instructions are commited to their + | execution and no killing of instruction is possible in this implementation. + +* Result interface + - Request + + | Ready signal of result interface is always set as CVA6 is always ready + | to take a result from coprocessor for an accepted offloaded instruction. + - Response + + | Result response is directly connected to writeback bus of the CV-X-IF + | functional unit. + + | Valid signal of result interface is connected to valid signal of + | writeback bus. + + | Id signal of result interface is connected to scoreboard id of + | writeback bus. + + | Write enable signal of result interface is connected to a dedicated CV-X-IF WE + | signal in CVA6 which signals scoreboard if a writeback should happen + | or not to the CVA6 register file. + + | ``exccode`` and ``exc`` signal of result interface are connected to exception + | signals of writeback bus. Exception from coprocessor does not write + | the ``tval`` field in exception signal of writeback bus. + + | Three registers are added to hold illegal instruction information in + | case a result transaction and a non-accepted issue transaction happen + | in the same cycle. Result transactions will be written to the writeback + | bus in this case having priority over the non-accepted instruction due + | to being linked to an older offloaded instruction. Once the writeback + | bus is free, an illegal instruction exception will be raised thanks to + | information held in these three registers. + +Coprocessor recommendations for use with CVA6's CV-X-IF +------------------------------------------------------- + +CVA6 supports all coprocessors supporting the CV-X-IF specification with the exception of : + +* Coprocessor requiring the Memory interface and Memory result interface (not implemented in CVA6 yet). + - All memory transaction should happen via the Issue interface, i.e. Load into CVA6 register file + then initialize an issue transaction. +* Coprocessor requiring the Compressed interface (not implemented in CVA6 yet). + - RISC-V Compressed extension (RVC) is already implemented in CVA6. User Space for custom compressed instruction + is not big enough to have RVC and a custom compressed extension. +* Stateful coprocessors. + - CVA6 will commit on the Commit interface all its issue transactions. Speculation + information is only kept in the CVA6 and speculation process is only done in CVA6. + The coprocessor shall be stateless otherwise it will not be able to revert its state if CVA6 kills an + in-flight instruction (in case of mispredict or flush). + +How to use CVA6 without CV-X-IF interface +----------------------------------------- +Select a configuration with ``CVA6ConfigCvxifEn`` parameter disabled or change it for your configuration. + +Never let the CV-X-IF interface unconnected with the ``CVA6ConfigCvxifEn`` parameter enabled. + +How to design a coprocessor for the CV-X-IF interface +----------------------------------------------------- We can add a custom coprocessor that implements custom instructions by modifying the example coprocessor in this repository. This section is structured as a tutorial to implement two instructions that manipulate binary-coded decimal numbers. @@ -420,7 +420,7 @@ For example, 123 in decimal = 0x7B in hexadecimal = 0x123 in binary-coded decima gtkwave verif/sim/out_*/veri-testharness_sim/cvxif_bcd.cv64a6_imafdc_sv39.vcd The signals in TOP.ariane_testharness.i_ariane.cvxif_req/resp should be useful. - -How to program a CV-X-IF coprocessor + +How to program a CV-X-IF coprocessor ------------------------------------ *The team is looking for a contributor to write this section.* diff --git a/docs/01_cva6_user/Introduction.rst b/docs/01_cva6_user/Introduction.rst index 2e39faea644..3bde759061a 100644 --- a/docs/01_cva6_user/Introduction.rst +++ b/docs/01_cva6_user/Introduction.rst @@ -40,7 +40,7 @@ The current limitation of documentation on CVA6 is well understood. Rather than regretting this, the reader is encouraged to contribute to it to make CVA6 an even better core. To contribute to the project, refer to the Contributing_ guidelines and get in touch with the team. -.. _Contributing: https://github.com/jquevremont/cva6/blob/master/CONTRIBUTING.md +.. _Contributing: https://github.com/openhwgroup/cva6/blob/master/CONTRIBUTING.md Target Audience --------------- @@ -49,7 +49,7 @@ The CVA6 user manual targets: * SW programmers * HW designers who integrate CVA6 into a SoC/ASIC/FPGA * Architects who design a coprocessor for the CV-X-IF interface and who need to create SW to use it -* HW designers who synthetize/place&route/verify a design that embeds CVA6 +* HW designers who synthesize/place&route/verify a design that embeds CVA6 * Verification engineers involved in the OpenHW Group’s CVA6 project who use this manual as a reference. The user guide does not target people who dig into CVA6 design. No internal mechanisms are described here, diff --git a/docs/01_cva6_user/Programmer_View.rst b/docs/01_cva6_user/Programmer_View.rst index cd67c3c7511..14ef0b4f27c 100644 --- a/docs/01_cva6_user/Programmer_View.rst +++ b/docs/01_cva6_user/Programmer_View.rst @@ -39,19 +39,21 @@ Some of them are optional and are enabled through parameters in the SystemVerilo :align: left :header: "Extension", "Optional", "RV32 (in CV32A6)", "RV64 (in CV64A6)", "Note" - "I- Base Integer Instruction Set", "No", "✔", "✔", "Note 1" - "A - Atomic Instructions", "Yes", "✔", "✔", "Note 1" - "Zb* - Bit-Manipulation", "Yes", "✔", "✔", "Note 1" - "C - Compressed Instructions ", "Yes", "✔", "✔", "Note 1" - "Zcb - Code Size Reduction", "Yes", "✔", "✔", "Note 1" - "Zcmp - Code Size Reduction", "Yes", "✔", "✔", "Note 1" - "D - Double precision floating-point", "Yes", "", "✔", "Note 1" - "F - Single precision floating-point", "Yes", "✔", "✔", "Note 1" - "M - Integer Multiply/Divide", "No", "✔", "✔", "Note 1" - "Zicount - Performance Counters", "Yes", "✔", "✔", "Note 2" - "Zicsr - Control and Status Register Instructions", "No", "✔", "✔", "Note 2" - "Zifencei - Instruction-Fetch Fence", "No", "✔", "✔", "Note 2" - "Zicond - Integer Conditional Operations(Ratification pending)", "Yes", "✔", "✔", "Note 2" + "I- Base Integer Instruction Set", "No", "✔", "✔", "Note 1" + "A - Atomic Instructions", "Yes", "✔", "✔", "Note 1" + "Zb* - Bit-Manipulation", "Yes", "✔", "✔", "Note 1" + "C - Compressed Instructions ", "Yes", "✔", "✔", "Note 1" + "Zcb - Code Size Reduction", "Yes", "✔", "✔", "Note 1" + "Zcmp - Code Size Reduction", "Yes", "✔", "✔", "Note 1" + "Zcmt - Code Size Reduction", "Yes", "✔", "✔", "Note 2" + "Zkn - NIST Algorithm Suite (comprised of Zbkb, Zbkc, Zbkx, Zkne, Zknd and Zknh)", "Yes", "✔", "✔", "Note 1" + "D - Double precision floating-point", "Yes", "", "✔", "Note 1" + "F - Single precision floating-point", "Yes", "✔", "✔", "Note 1" + "M - Integer Multiply/Divide", "No", "✔", "✔", "Note 1" + "Zicount - Performance Counters", "Yes", "✔", "✔", "Note 2" + "Zicsr - Control and Status Register Instructions", "No", "✔", "✔", "Note 2" + "Zifencei - Instruction-Fetch Fence", "No", "✔", "✔", "Note 2" + "Zicond - Integer Conditional Operations(Ratification pending)", "Yes", "✔", "✔", "Note 2" Notes: @@ -76,6 +78,8 @@ These extensions are available in CV32A60AX: "RV32C - Compressed Instructions ", "✔" "RV32Zcb - Code Size Reduction", "✔" "RVZcmp - Code Size Reduction", "" + "RVZcmt - Code Size Reduction", "" + "Zkn - NIST Algorithm Suite", "" "RV32D - Double precision floating-point", "" "RV32F - Single precision floating-point", "" "RV32M - Integer Multiply/Divide", "✔" @@ -100,6 +104,8 @@ These extensions are available in CV32A60X: "RV32C - Compressed Instructions ", "✔" "RV32Zcb - Code Size Reduction", "✔" "RVZcmp - Code Size Reduction", "✔" + "RVZcmt - Code Size Reduction", "" + "Zkn - NIST Algorithm Suite", "" "RV32D - Double precision floating-point", "" "RV32F - Single precision floating-point", "" "RV32M - Integer Multiply/Divide", "✔" @@ -124,6 +130,8 @@ These extensions are available in CV64A6_MMU: "RV32C - Compressed Instructions ", "✔" "RV32Zcb - Code Size Reduction", "✔" "RVZcmp - Code Size Reduction", "✔" + "RVZcmt - Code Size Reduction", "" + "Zkn - NIST Algorithm Suite", "" "RV32D - Double precision floating-point", "" "RV32F - Single precision floating-point", "" "RV32M - Integer Multiply/Divide", "✔" @@ -203,7 +211,7 @@ CVA6 family CV32A6 supports the RISC-V **Sv32** virtual memory when the ``MMUEn`` parameter is set to 1 (and ``Xlen`` is set to 32). -CV64A6 supports the RISC-V **Sv39** virtual memory when the ``MMUEn`` parameter is set to 1 (and ``Xlen`` is set to 64). +CV64A6 supports the RISC-V **Sv39** virtual memory when the ``MMUEn`` parameter is set to 1 (and ``Xlen`` is set to 64). Additionally, the **Svnapot** extension can be enabled with Sv39 when ``SvnapotEn`` parameter is set to 1. Within CV64A6, the hypervisor extension is available and supports **Sv39x4** virtual memory when the ``CVA6ConfigHExtEn`` parameter is set to 1 (and ``Xlen`` is set to 64). diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32A.rst b/docs/01_cva6_user/RISCV_Instructions_RV32A.rst index 76b8bc434c1..c5cc06156ab 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32A.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32A.rst @@ -134,7 +134,7 @@ Atomic Memory Operations **Format**: amomin.d rd, rs2, (rs1) - **Description**: AMOMIN.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the minimum between the loaded value and the original value in rs2, then stores the result back to the address in rs1. + **Description**: AMOMIN.W atomically loads a data value from the address in rs1, places the value into register rd, then chooses the minimum between the loaded value and the original value in rs2, then stores the result back to the address in rs1. **Pseudocode**: x[rd] = AMO32(M[x[rs1]] MIN x[rs2]) diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst index 6981ce82bc0..a58cc862c45 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst @@ -205,7 +205,7 @@ RV64 specific instructions -Integer minumum/maximum +Integer minimum/maximum -------------------------- The integer minimum/maximum instructions are arithmetic R-type instructions that return the smaller/larger of two operands. diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbkc.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbkc.rst new file mode 100644 index 00000000000..abaf205afc2 --- /dev/null +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbkc.rst @@ -0,0 +1,87 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + Copyright (c) 2025 Thales + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zbkc: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV32A60X", "Implemented extension" + "CV64A6_MMU", "Implemented extension" + + +================================================== +RVZbkc: Carry-less multiplication for Cryptography +================================================== +This extension is a subset of the Zbc extension. + +Carry-less multiplication is the multiplication in the polynomial ring over GF(2). + +clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product. + +The following instructions (and pseudoinstructions) comprise the Zbkc extension: + ++-----------+-----------+-----------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+=======================+ +| ✔ | ✔ | clmul rd, rs1, rs2 | ++-----------+-----------+-----------------------+ +| ✔ | ✔ | clmulh rd, rs1, rs2 | ++-----------+-----------+-----------------------+ + +RV32 and RV64 Instructions +-------------------------- + +- **CLMUL**: Carry-less multiply (low-part) + + **Format**: clmul rd, rs1, rs2 + + **Description**: clmul produces the lower half of the 2.XLEN carry-less product. + + **Pseudocode**: foreach (i from 1 to xlen by 1) { output = if ((rs2 >> i) & 1) then output ^ (rs1 << i); else output; } + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **CLMULH**: Carry-less multiply (high-part) + + **Format**: clmulh rd, rs1, rs2 + + **Description**: clmulh produces the upper half of the 2.XLEN carry-less product. + + **Pseudocode**: foreach (i from 1 to xlen by 1) { output = if ((rs2_val >> i) & 1) then output ^ (rs1_val >> (xlen - i)) else output } + + **Invalid values**: NONE + + **Exception raised**: NONE + + + + + + + + + diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbkx.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbkx.rst new file mode 100644 index 00000000000..1b6395f54d5 --- /dev/null +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbkx.rst @@ -0,0 +1,93 @@ +.. Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); +.. you may not use this file except in compliance with the License. +.. SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +.. You may obtain a copy of the License at https://solderpad.org/licenses/ + +.. Author: Munail Waqar, 10xEngineers +.. Date: 03.05.2025 +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zbkx: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV64A6_MMU", "Implemented extension" + +============================= +RVZbkx: Crossbar permutation instructions +============================= + +The following instructions comprise the Zbkx extension: + +Xperm instructions +-------------------- +The xperm instructions perform permutation operations on a register. They use indices extracted from rs2 to select data chunks (bytes for xperm8 or nibbles for xperm4) from rs1. The selected data is then placed into the destination register (rd) at positions corresponding to the extracted indices in rs2. If an index in rs2 is out of range, the corresponding chunk in rd is set to 0. + ++-----------+-----------+-----------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+=======================+ +| ✔ | ✔ | xperm8 rd, rs1, rs2 | ++-----------+-----------+-----------------------+ +| ✔ | ✔ | xperm4 rd, rs1, rs2 | ++-----------+-----------+-----------------------+ + + +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + + +- **XPERM8**: Crossbar permutation (bytes) + + **Format**: xperm8 rd, rs1, rs2 + + **Description**: The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8 8-bit elements. The rs2 register contains a vector of XLEN/8 8-bit indexes. The result is each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds. + + **Pseudocode**: foreach (i from 0 to xlen by 8) { + if (rs2[i*8+:8]<(xlen/8)) + X(rd)[i*8+:8] = rs1[rs2[i*8+:8]*8+:8]; + else + X(rd)[i*8+:8] = 8'b0; + } + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **XPERM4**: Crossbar permutation (nibbles) + + **Format**: xperm4 rd, rs1, rs2 + + **Description**: The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4 4-bit elements. The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds. + + **Pseudocode**: foreach (i from 0 to xlen by 4) { + if (rs2[i*4+:4]<(xlen/4)) + X(rd)[i*4+:4] = rs1[rs2[i*4+:4]*4+:4]; + else + X(rd)[i*4+:4] = 4'b0; + } + + **Invalid values**: NONE + + **Exception raised**: NONE diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZknd.rst b/docs/01_cva6_user/RISCV_Instructions_RVZknd.rst new file mode 100644 index 00000000000..fc17673b67f --- /dev/null +++ b/docs/01_cva6_user/RISCV_Instructions_RVZknd.rst @@ -0,0 +1,161 @@ +.. Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); +.. you may not use this file except in compliance with the License. +.. SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +.. You may obtain a copy of the License at https://solderpad.org/licenses/ + +.. Author: Munail Waqar, 10xEngineers +.. Date: 03.05.2025 +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zkne: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV64A6_MMU", "Implemented extension" + +============================= +RVZknd: NIST Suite: AES Decryption +============================= + +The following instructions comprise the Zknd extension: + +Decryption instructions +-------------------- +The Decryption instructions (Zknd) provide support and acceleration for AES decryption and key expansion. + ++-----------+-----------+----------------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+============================+ +| ✔ | | aes32dsi rd, rs1, rs2, bs | ++-----------+-----------+----------------------------+ +| ✔ | | aes32dsmi rd, rs1, rs2, bs | ++-----------+-----------+----------------------------+ +| | ✔ | aes64ds rd, rs1, rs2 | ++-----------+-----------+----------------------------+ +| | ✔ | aes64dsm rd, rs1, rs2 | ++-----------+-----------+----------------------------+ + +RV32 specific instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + + +- **AES32DSI**: AES final round decryption instruction for RV32 + + **Format**: aes32dsi rd, rs1, rs2, bs + + **Description**: This instruction sources a single byte from rs2 according to bs. To this it applies the inverse AES SBox operation, and XOR the result with rs1. + + **Pseudocode**: X(rd) = X(rs1)[31..0] ^ rol32((0x000000 @ aes_sbox_inv((X(rs2)[31..0] >> bs*8)[7..0])), unsigned(bs*8)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AES32DSMI**: AES middle round decryption instruction for RV32. + + **Format**: aes32dsmi rd, rs1, rs2, bs + + **Description**: This instruction sources a single byte from rs2 according to bs. To this it applies the inverse AES SBox operation, and a partial inverse MixColumn, before XORing the result with rs1. + + **Pseudocode**: X(rd) = X(rs1)[31..0] ^ rol32(aes_mixcolumn_byte_inv(aes_sbox_inv((X(rs2)[31..0] >> bs*8)[7..0])), unsigned(bs*8)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +RV64 specific instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **AES64DS**: AES final round decryption instruction for RV64. + + **Format**: aes64ds rd, rs1, rs2 + + **Description**: Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the Inverse ShiftRows and SubBytes steps. + + **Pseudocode**: X(rd) = aes_apply_inv_sbox_to_each_byte(aes_rv64_shiftrows_inv(X(rs2)[63..0], X(rs1)[63..0])); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AES64DSM**: AES middle round decryption instruction for RV64. + + **Format**: aes64dsm rd, rs1, rs2 + + **Description**: Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps. + + **Pseudocode**: X(rd) = aes_mixcolumn_inv(aes_apply_inv_sbox_to_each_byte(aes_rv64_shiftrows_inv(X(rs2)[63..0], X(rs1)[63..0]))[63..32]) + @ + aes_mixcolumn_inv(aes_apply_inv_sbox_to_each_byte(aes_rv64_shiftrows_inv(X(rs2)[63..0], X(rs1)[63..0]))[31..0]); + + **Invalid values**: NONE + + **Exception raised**: NONE + + +Key Schedule instructions +-------------------------------- + ++-----------+-----------+-----------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+=======================+ +| | ✔ | aes64ks1i rd, rs | ++-----------+-----------+-----------------------+ +| | ✔ | aes64ks2 rd, rs | ++-----------+-----------+-----------------------+ + +RV64 specific Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **AES64KS1I**: This instruction implements part of the KeySchedule operation for the AES Block cipher involving the SBox operation. + + **Format**: aes64ks1i rd, rs1, rnum + + **Description**: This instruction implements the rotation, SubBytes and Round Constant addition steps of the AES block cipher Key Schedule. Note that rnum must be in the range 0x0..0xA. + + **Pseudocode**: if(unsigned(rnum) > A) { + X(rd) = 64'b0; + } else { + tmp = if (rnum ==0xA) + X(rs1)[63..32] + else + ror32(X(rs1)[63..32], 8) + X(rd) = (aes_subword_fwd(tmp) ^ aes_decode_rcon(rnum)) @ (aes_subword_fwd(tmp) ^ aes_decode_rcon(rnum)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AES64KS2**: This instruction implements part of the KeySchedule operation for the AES Block cipher. + + **Format**: aes64ks2 rd, rs1, rs2 + + **Description**: This instruction implements the additional XORing of key words as part of the AES block cipher Key Schedule. + + **Pseudocode**: X(rd) = (X(rs1)[63..32] ^ X(rs2)[31..0] ^ X(rs2)[63..32]) @ (X(rs1)[63..32] ^ X(rs2)[31..0]); + + **Invalid values**: NONE + + **Exception raised**: NONE diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZkne.rst b/docs/01_cva6_user/RISCV_Instructions_RVZkne.rst new file mode 100644 index 00000000000..4884a274859 --- /dev/null +++ b/docs/01_cva6_user/RISCV_Instructions_RVZkne.rst @@ -0,0 +1,161 @@ +.. Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); +.. you may not use this file except in compliance with the License. +.. SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +.. You may obtain a copy of the License at https://solderpad.org/licenses/ + +.. Author: Munail Waqar, 10xEngineers +.. Date: 03.05.2025 +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zkne: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV64A6_MMU", "Implemented extension" + +============================= +RVZkne: NIST Suite: AES Encryption +============================= + +The following instructions comprise the Zkne extension: + +Encryption instructions +-------------------- +The Encryption instructions (Zkne) provide support and acceleration for AES encryption and key expansion. + ++-----------+-----------+----------------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+============================+ +| ✔ | | aes32esi rd, rs1, rs2, bs | ++-----------+-----------+----------------------------+ +| ✔ | | aes32esmi rd, rs1, rs2, bs | ++-----------+-----------+----------------------------+ +| | ✔ | aes64es rd, rs1, rs2 | ++-----------+-----------+----------------------------+ +| | ✔ | aes64esm rd, rs1, rs2 | ++-----------+-----------+----------------------------+ + +RV32 specific instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + + +- **AES32ESI**: AES final round encryption instruction for RV32 + + **Format**: aes32esi rd, rs1, rs2, bs + + **Description**: This instruction sources a single byte from rs2 according to bs. To this it applies the forward AES SBox operation, before XORing the result with rs1. + + **Pseudocode**: X(rd) = X(rs1)[31..0] ^ rol32((0x000000 @ aes_sbox_fwd((X(rs2)[31..0] >> bs*8)[7..0])), unsigned(bs*8)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AES32ESMI**: AES middle round encryption instruction for RV32. + + **Format**: aes32esmi rd, rs1, rs2, bs + + **Description**: This instruction sources a single byte from rs2 according to bs. To this it applies the forward AES SBox operation, and a partial forward MixColumn, before XORing the result with rs1. + + **Pseudocode**: X(rd) = X(rs1)[31..0] ^ rol32(aes_mixcolumn_byte_fwd(aes_sbox_fwd((X(rs2)[31..0] >> bs*8)[7..0])), unsigned(bs*8)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +RV64 specific instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **AES64ES**: AES final round encryption instruction for RV64. + + **Format**: aes64es rd, rs1, rs2 + + **Description**: Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the ShiftRows and SubBytes steps. + + **Pseudocode**: X(rd) = aes_apply_fwd_sbox_to_each_byte(aes_rv64_shiftrows_fwd(X(rs2)[63..0], X(rs1)[63..0])); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AES64ESM**: AES middle round encryption instruction for RV64. + + **Format**: aes64esm rd, rs1, rs2 + + **Description**: Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the ShiftRows, SubBytes and MixColumns steps. + + **Pseudocode**: X(rd) = aes_mixcolumn_fwd(aes_apply_fwd_sbox_to_each_byte(aes_rv64_shiftrows_fwd(X(rs2)[63..0], X(rs1)[63..0]))[63..32]) + @ + aes_mixcolumn_fwd(aes_apply_fwd_sbox_to_each_byte(aes_rv64_shiftrows_fwd(X(rs2)[63..0], X(rs1)[63..0]))[31..0]); + + **Invalid values**: NONE + + **Exception raised**: NONE + + +Key Schedule instructions +-------------------------------- + ++-----------+-----------+-----------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+=======================+ +| | ✔ | aes64ks1i rd, rs | ++-----------+-----------+-----------------------+ +| | ✔ | aes64ks2 rd, rs | ++-----------+-----------+-----------------------+ + +RV64 specific Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **AES64KS1I**: This instruction implements part of the KeySchedule operation for the AES Block cipher involving the SBox operation. + + **Format**: aes64ks1i rd, rs1, rnum + + **Description**: This instruction implements the rotation, SubBytes and Round Constant addition steps of the AES block cipher Key Schedule. Note that rnum must be in the range 0x0..0xA. + + **Pseudocode**: if(unsigned(rnum) > A) { + X(rd) = 64'b0; + } else { + tmp = if (rnum ==0xA) + X(rs1)[63..32] + else + ror32(X(rs1)[63..32], 8) + X(rd) = (aes_subword_fwd(tmp) ^ aes_decode_rcon(rnum)) @ (aes_subword_fwd(tmp) ^ aes_decode_rcon(rnum)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **AES64KS2**: This instruction implements part of the KeySchedule operation for the AES Block cipher. + + **Format**: aes64ks2 rd, rs1, rs2 + + **Description**: This instruction implements the additional XORing of key words as part of the AES block cipher Key Schedule. + + **Pseudocode**: X(rd) = (X(rs1)[63..32] ^ X(rs2)[31..0] ^ X(rs2)[63..32]) @ (X(rs1)[63..32] ^ X(rs2)[31..0]); + + **Invalid values**: NONE + + **Exception raised**: NONE diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZknh.rst b/docs/01_cva6_user/RISCV_Instructions_RVZknh.rst new file mode 100644 index 00000000000..51dd0a9b903 --- /dev/null +++ b/docs/01_cva6_user/RISCV_Instructions_RVZknh.rst @@ -0,0 +1,263 @@ +.. Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License"); +.. you may not use this file except in compliance with the License. +.. SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +.. You may obtain a copy of the License at https://solderpad.org/licenses/ + +.. Author: Munail Waqar, 10xEngineers +.. Date: 03.05.2025 +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zknh: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV64A6_MMU", "Implemented extension" + +============================= +RVZknh: NIST Suite: Hash Function Instructions +============================= + +The following instructions comprise the Zknh extension: + +Hash Function instructions +-------------------- +The Hash Function instructions (Zknh) provide acceleration for the SHA2 family of cryptographic hash functions. + ++-----------+-----------+----------------------------+ +| RV32 | RV64 | Mnemonic | ++===========+===========+============================+ +| ✔ | ✔ | sha256sig0 rd, rs1 | ++-----------+-----------+----------------------------+ +| ✔ | ✔ | sha256sig1 rd, rs1 | ++-----------+-----------+----------------------------+ +| ✔ | ✔ | sha256sum0 rd, rs1 | ++-----------+-----------+----------------------------+ +| ✔ | ✔ | sha256sum1 rd, rs1 | ++-----------+-----------+----------------------------+ +| ✔ | | sha512sig0h rd, rs1, rs2 | ++-----------+-----------+----------------------------+ +| ✔ | | sha512sig0l rd, rs1, rs2 | ++-----------+-----------+----------------------------+ +| ✔ | | sha512sig1h rd, rs1, rs2 | ++-----------+-----------+----------------------------+ +| ✔ | | sha512sig1l rd, rs1, rs2 | ++-----------+-----------+----------------------------+ +| ✔ | | sha512sum0r rd, rs1, rs2 | ++-----------+-----------+----------------------------+ +| ✔ | | sha512sum1r rd, rs1, rs2 | ++-----------+-----------+----------------------------+ +| | ✔ | sha512sig0 rd, rs1 | ++-----------+-----------+----------------------------+ +| | ✔ | sha512sig1 rd, rs1 | ++-----------+-----------+----------------------------+ +| | ✔ | sha512sum0 rd, rs1 | ++-----------+-----------+----------------------------+ +| | ✔ | sha512sum1 rd, rs1 | ++-----------+-----------+----------------------------+ + + +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **SHA256SIG0**: SHA2-256 Sigma0 instruction + + **Format**: sha256sig0 rd, rs1 + + **Description**: Implements the Sigma0 transformation function as used in the SHA2-256 hash function. For RV32, the entire XLEN source register is operated on. For RV64, the low 32 bits of the source register are operated on, and the result sign extended to XLEN bits. + + **Pseudocode**: X(rd) = EXTS(ror32(X(rs1)[31..0], 7) ^ ror32(X(rs1)[31..0], 18) ^ (X(rs1)[31..0] >> 3)); + + **Invalid values**: NONE + + **Exception raised**: NONE + + +- **SHA256SIG1**: SHA2-256 Sigma1 instruction + + **Format**: sha256sig1 rd, rs1 + + **Description**: Implements the Sigma1 transformation function as used in the SHA2-256 hash function. For RV32, the entire XLEN source register is operated on. For RV64, the low 32 bits of the source register are operated on, and the result sign extended to XLEN bits. + + **Pseudocode**: X(rd) = EXTS(ror32(X(rs1)[31..0], 17) ^ ror32(X(rs1)[31..0], 19) ^ (X(rs1)[31..0] >> 10)); + + **Invalid values**: NONE + + **Exception raised**: NONE + + +- **SHA256SUM0**: SHA2-256 Sum0 instruction + + **Format**: sha256sum0 rd, rs1 + + **Description**: Implements the Sum0 transformation function as used in the SHA2-256 hash function. For RV32, the entire XLEN source register is operated on. For RV64, the low 32 bits of the source register are operated on, and the result sign extended to XLEN bits. + + **Pseudocode**: X(rd) = EXTS(ror32(X(rs1)[31..0], 2) ^ ror32(X(rs1)[31..0], 13) ^ ror32(X(rs1)[31..0] >> 22)); + + **Invalid values**: NONE + + **Exception raised**: NONE + + +- **SHA256SUM1**: SHA2-256 Sum1 instruction + + **Format**: sha256sum1 rd, rs1 + + **Description**: Implements the Sum1 transformation function as used in the SHA2-256 hash function. For RV32, the entire XLEN source register is operated on. For RV64, the low 32 bits of the source register are operated on, and the result sign extended to XLEN bits. + + **Pseudocode**: X(rd) = EXTS(ror32(X(rs1)[31..0], 6) ^ ror32(X(rs1)[31..0], 11) ^ ror32(X(rs1)[31..0] >> 25)); + + **Invalid values**: NONE + + **Exception raised**: NONE + + + +RV32 specific instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **SHA512SIG0H**: SHA2-512 Sigma0 high (RV32) + + **Format**: sha512sig0h rd, rs1, rs2 + + **Description**: Implements the high half of the Sigma0 transformation, as used in the SHA2-512 hash function. Used to compute the Sigma0 transform of the SHA2-512 hash function in conjunction with the sha512sig0l instruction. The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers. + + **Pseudocode**: X(rd) = EXTS((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^ (X(rs2) << 31) ^ (X(rs2) << 24)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SHA512SIG0L**: SHA2-512 Sigma0 low (RV32) + + **Format**: sha512sig0l rd, rs1, rs2 + + **Description**: Implements the low half of the Sigma0 transformation, as used in the SHA2-512 hash function. Used to compute the Sigma0 transform of the SHA2-512 hash function in conjunction with the sha512sig0h instruction. The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers. + + **Pseudocode**: X(rd) = EXTS((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^ (X(rs2) << 31) ^ (X(rs2) << 25) ^ (X(rs2) << 24)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SHA512SIG1H**: SHA2-512 Sigma1 high (RV32) + + **Format**: sha512sig1h rd, rs1, rs2 + + **Description**: Implements the high half of the Sigma1 transformation, as used in the SHA2-512 hash function. Used to compute the Sigma1 transform of the SHA2-512 hash function in conjunction with the sha512sig1l instruction. The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers. + + **Pseudocode**: X(rd) = EXTS((X(rs1) << 3) ^ (X(rs1) >> 6) ^ (X(rs1) >> 19) ^ (X(rs2) >> 29) ^ (X(rs2) << 13)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SHA512SIG1L**: SHA2-512 Sigma1 low (RV32) + + **Format**: sha512sig1l rd, rs1, rs2 + + **Description**: Implements the low half of the Sigma1 transformation, as used in the SHA2-512 hash function. Used to compute the Sigma1 transform of the SHA2-512 hash function in conjunction with the sha512sig0h instruction. The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers. + + **Pseudocode**: X(rd) = EXTS((X(rs1) << 3) ^ (X(rs1) >> 6) ^ (X(rs1) >> 19) ^ (X(rs2) >> 29) ^ (X(rs2) << 26) ^ (X(rs2) << 13)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SHA512SUM0R**: SHA2-512 Sum0 (RV32) + + **Format**: sha512sum0r rd, rs1, rs2 + + **Description**: Implements the Sum0 transformation, as used in the SHA2-512 hash function. The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers. + + **Pseudocode**: X(rd) = EXTS((X(rs1) << 25) ^ (X(rs1) << 30) ^ (X(rs1) >> 28) ^ (X(rs2) >> 7) ^ (X(rs2) >> 2) ^ (X(rs2) << 4)); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SHA512SUM1R**: SHA2-512 Sum1 (RV32) + + **Format**: sha512sum1r rd, rs1, rs2 + + **Description**: Implements the Sum1 transformation, as used in the SHA2-512 hash function. The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers. + + **Pseudocode**: X(rd) = EXTS((X(rs1) << 23) ^ (X(rs1) >> 14) ^ (X(rs1) >> 18) ^ (X(rs2) >> 9) ^ (X(rs2) << 18) ^ (X(rs2) << 14)); + + **Invalid values**: NONE + + **Exception raised**: NONE + + + +RV64 specific Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **SHA512SIG0**: SHA2-512 Sigma0 instruction (RV64) + + **Format**: sha512sig0 rd, rs1 + + **Description**: Implements the Sigma0 transformation function as used in the SHA2-512 hash function. + + **Pseudocode**: X(rd) = ror64(X(rs1), 1) ^ ror64(X(rs1), 8) ^ (X(rs1) >> 7); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SHA512SIG1**: SHA2-512 Sigma1 instruction (RV64) + + **Format**: sha512sig1 rd, rs1 + + **Description**: Implements the Sigma1 transformation function as used in the SHA2-512 hash function. + + **Pseudocode**: X(rd) = ror64(X(rs1), 19) ^ ror64(X(rs1), 61) ^ (X(rs1) >> 6); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SHA512SUM0**: SHA2-512 Sum0 instruction (RV64) + + **Format**: sha512sum0 rd, rs1 + + **Description**: Implements the Sum0 transformation function as used in the SHA2-512 hash function. + + **Pseudocode**: X(rd) = ror64(X(rs1), 28) ^ ror64(X(rs1), 34) ^ ror64(X(rs1) ,39); + + **Invalid values**: NONE + + **Exception raised**: NONE + +- **SHA512SUM1**: SHA2-512 Sum1 instruction (RV64) + + **Format**: sha512sum1 rd, rs1 + + **Description**: Implements the Sum1 transformation function as used in the SHA2-512 hash function. + + **Pseudocode**: X(rd) = ror64(X(rs1), 14) ^ ror64(X(rs1), 18) ^ ror64(X(rs1) ,41); + + **Invalid values**: NONE + + **Exception raised**: NONE diff --git a/docs/01_cva6_user/Traps_Interrupts_Exceptions.rst b/docs/01_cva6_user/Traps_Interrupts_Exceptions.rst index bb0c8f266c9..14793223fc6 100644 --- a/docs/01_cva6_user/Traps_Interrupts_Exceptions.rst +++ b/docs/01_cva6_user/Traps_Interrupts_Exceptions.rst @@ -9,7 +9,7 @@ Traps, Interrupts, Exceptions ============================= Traps are composed of interrupts and exceptions. Interrupts are asynchronous events whereas exceptions are synchronous ones. -On one hand, interrupts are occuring independently of the instructions +On one hand, interrupts are occurring independently of the instructions (mainly raised by peripherals or debug module). On the other hand, an instruction may raise exceptions synchronously. diff --git a/docs/01_cva6_user/Trigger_Module.rst b/docs/01_cva6_user/Trigger_Module.rst new file mode 100644 index 00000000000..23fd1a2c034 --- /dev/null +++ b/docs/01_cva6_user/Trigger_Module.rst @@ -0,0 +1,333 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 Thales DIS SAS + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + Original Author : Munail Waqar - 10X Engineers + Contributors : Mounsaf YOUSFI - Thales DIS + + +Trigger Module (Sdtrig Extension) +================================= +The module provides powerful hardware breakpoints and watchpoints in the core. +Upon trigger match, the core supports two actions i.e. breakpoint excpetion generation and entry into debug mode. +The number of triggers is parameterized and the module itself is configurable under the SDTRIG bit. + +Configuration CSRs +~~~~~~~~~~~~~~~~~~ +* ``tselect`` : The currently selected trigger. +* ``tinfo`` : Shows the currently supported triggers. +* ``tdata1`` : Specifies trigger data like trigger type, configuration, privilege mode, status. +* ``tdata2`` : The value to be matched. +* ``tdata3`` : Specifies context data. +* ``scontext`` : Specifies supervisor mode context data. + + +Modified CSRs (Breakpoint action) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +* ``mstatus``: several fields are updated like previous privilege mode (``MPP``), previous interrupt enabled (``MPIE``) +* ``mepc`` : updated with the address of the instruction raising the exception. +* ``mcause`` : updated with a breakpoint code (0x00000003) indicating the event causing the trap. + +Modified CSRs (Debug action) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +* ``dpc`` : updated with the address of the instruction causing the debug request. +* ``dcsr`` : some fields are updated like debug entry cause (``CAUSE``) + +Priorities + +All triggers are subject to priority handling. The priority is such : ``Mcontrol6 load data timing:AFTER`` <=> ``Icount`` <=> ``Etrigger`` <=> ``Itrigger`` > ``Mcontrol6 execute address timing:BEFORE`` > ``Mcontrol6 execute data timing:BEFORE`` > ``Mcontrol6 load address timing:BEFORE`` <=> ``Mcontrol6 store address/data timing:BEFORE``. + +Priorities are handled as such : if multiple triggers request fire at the same time, only the highest priority ones are taken. If multiple triggers request fire in the same priority, all actions within this priority are taken at the same time. + +This order and behaviour fits the RISC-V debug specification chapter 5 (Sdtrig), paragraph 5.3 (Priority). + +Precision + +All triggers are precise which means ``mepc`` will always correspond to the matching instruction, except ``mcontrol6 load data`` trigger type, which updates ``mepc`` with the immediately-next instruction for physics related reasons(impossible to match on a load result if result is not obtained yet, which implies the execution of the whole instruction hence breaking on the next instruction to commit the result of the load instead of losing the data). + +Icount +------ +The ``icount`` trigger is used to delay a breakpoint or debug entry by a programmable number of instructions. It acts like a countdown timer based on instruction commits and gives deterministic trigger behavior useful for testing or stepping into debug mode after a specific number of instructions. + +Prerequisites +~~~~~~~~~~~~~ +- ``SDTRIG`` and ``Icount`` configuration bits must be enabled. +- Trigger type must be ``4'd3`` in ``tdata1``. + +Trigger Match Logic +~~~~~~~~~~~~~~~~~~~ +- The ``count`` field in ``tdata1`` is initialized with the number of instructions to wait. +- The counter decrements on every instruction commit. +- Countdown continues only outside trap handlers to avoid miscounts during exceptions. + +- Matching occurs when: + - ``count == 0`` + - Current privilege level matches the trigger config (``m/s/u``) + +- On match: + - ``pending`` is set + - The specified ``action`` is triggered: + - ``0`` → raise a breakpoint exception + - ``1`` → enter debug mode + +- Once in debug mode: + - ``pending`` is cleared + - ``hit`` is set and remains latched + +Key Fields (in ``tdata1``) +~~~~~~~~~~~~~~~~~~~~~~~~~~ +- ``count``: Current countdown value. +- ``action``: Determines what to do on match: + + - ``0``: Raise a breakpoint exception + - ``1``: Enter debug mode + +- ``m``, ``s``, ``u``: Privilege mode flags — trigger only fires in selected modes. +- ``pending``: Indicates the trigger condition has been met and is awaiting action. +- ``hit``: Latched once the action (break/debug) occurs. + +Action Taken on Match +~~~~~~~~~~~~~~~~~~~~~ +- Breakpoint (``fire_req_Icount.action == 0``): + - Sets ``fire_req_Icount.valid = 1``, which results in a trap request that, if taken, results in: + - Trap entry + - Updates to ``mstatus``, ``mepc``, ``mcause`` + +- Debug Entry (``fire_req_Icount.action == 1``): + - Sets ``debug_from_trigger_d = 1``, resulting in: + - Trap into debug mode + - Updates ``dpc``, ``dcsr`` + +Pseudocode +~~~~~~~~~~ +.. code-block:: text + + If icount trigger is enabled and type is 0x3: + On instruction execute: + If in trap handler: + Hold countdown + Else if not in trap and count > 0: + Decrement count + If count == 0 and privilege matches and not pending: + Set pending + If action == 0: raise breakpoint + If action == 1: enter debug mode + If breakpoint or debug action occurred: + Set hit + Clear pending (for debug) + + +Mcontrol6 +--------- +The ``mcontrol6`` trigger detects specific memory accesses (load/store), instruction fetches or execution of specific instructions. It matches on instruction address, instruction, load/store data and load/store addresses. It is the most general and powerful of the trigger types allowing address/data breakpoints, watchpoints, and instruction level filters. + +Prerequisites +~~~~~~~~~~~~~~~ +- ``SDTRIG`` and ``Mcontrol6`` configuration bits must be enabled. +- Trigger type must be ``4'd6`` in ``tdata1``. + +Trigger Match Logic +~~~~~~~~~~~~~~~~~~~ +A match occurs if: + +1. Privilege Mode Match: + - One of the flags ``m``, ``s``, ``u`` in ``tdata1`` must match current mode. + +2. Condition Match: + - Based on operation type and mode: + - Instruction Execute: + - Match against PC (`fetch_sdtrig_pc_i`) or instruction (`fetch_sdtrig_instr_i`). + - Store Operation: + - Match against store data (`sdtrig_lsu_inputs_data_i`) or address (`sdtrig_lsu_inputs_vaddr_i`). + - Load Operation: + - Match against load result (`sdtrig_load_data_i`) or load address (`sdtrig_lsu_inputs_vaddr_i`). + +3. Selection Mode: + - If ``select == 1`` → compare data/instruction value. + - If ``select == 0`` → compare address. + +4. Match Type (`match` field): + - ``0`` → exact match (``==``) + - ``1`` → NAPOT (Naturally Aligned Power-of-Two) range match + - ``8`` → not equal (``!=``) + +5. Action (only one supported here): + - ``0`` → breakpoint exception generation + - ``1`` → enter debug mode + +6. Trigger chains + +``Mcontrol6`` type trigger supports trigger chaining. A trigger chain is necessarily a located on a contiguous sequence of ``tselect`` indexes (e.g. first trigger on index 2, last trigger on index 4, index 3 is part of the chain too). First chain' trigger has ``chain == 1``, last has ``chain == 0``. + +Every trigger must match and the only action taken is last trigger's action. + +Since priorities are taken into account, multiple trigger timings exist within ``mcontrol6`` type trigger and the CVA6 is a pipeline, it is necessary for the trigger chain to fire that the earliest events in terms of pipeline stages must be located on the lowest indexes, e.g. for a trigger chain on a load data instruction the order must be : execute address (pc check) > load address > load data because these events happen in that order in the pipeline. + +On match: +- The configured ``action`` is executed. +- In debug mode, internal state is reset: + - ``hit0`` is cleared + - ``hit1`` is latched + +Key Fields +~~~~~~~~~~ +- ``tdata1``: + - ``execute`` / ``load`` / ``store``: Operation type + - ``select``: Controls address vs. value comparison + - ``match``: Match type (exact, NAPOT, not-equal) + - ``action``: Trigger response (`1` → debug) + - ``m``, ``s``, ``u``: Privilege filters + - ``hit0``, ``hit1``: Used to track match state + +- ``tdata2``: Match value — can be an address, instruction or data value + +Pseudocode +~~~~~~~~~~ +.. code-block:: text + + If mcontrol6 is enabled and type is 0x6: + If privilege level matches tdata1: + Determine comparison target: + If execute: + If select == 0 → compare PC + If select == 1 → compare instruction + If store: + If select == 0 → compare store address + If select == 1 → compare store data + If load: + If select == 0 → compare load address + If select == 1 → compare load result + Use match field (==, NAPOT, !=) to evaluate + If match: + If action == 0 → generate breakpoint exception + If action == 1 → enter debug mode + In debug mode: + Clear hit0, set hit1, reset trigger state + +Etrigger +-------- +The ``etrigger`` trigger monitors **exception causes** and fires a trigger action when a matching exception occurs depending on privilege mode. It is highly useful for detecting specific trap causes such as illegal instructions, page faults, breakpoints etc. + +Prerequisites +~~~~~~~~~~~~~ +- ``SDTRIG`` and ``Etrigger`` configuration bits must be enabled. +- Trigger type must be ``4'd5`` in ``tdata1``. + +Trigger Match Logic +~~~~~~~~~~~~~~~~~~~ +- The trigger matches and activates when both conditions are met: + + - The trigger checks if the current exception cause (`ex_i.cause`) is set in the exception mask stored in ``tdata2``. + - The current privilege mode (`m`, `s`, `u`) matches what is enabled in ``tdata1``. + +- On a match: + - The normal exception is suppressed. + - The ``hit`` bit in ``tdata1`` is latched. + - The specified ``action`` is triggered: + - ``0`` → raise a breakpoint exception + - ``1`` → enter debug mode + +- While in debug mode, ``hit`` and internal state are cleared. + +Key Fields +~~~~~~~~~~ +- ``tdata1``: + - ``action``: Determines the response: + - ``0``: Raise a breakpoint exception + - ``1``: Enter debug mode + - ``m``, ``s``, ``u``: Privilege level flags. + - ``hit``: Latched on trigger match. + +- ``tdata2``: Bitmask for exception causes where each bit corresponds to a cause number. For example: + - Bit 2 → Illegal instruction + - Bit 3 → Breakpoint + - Bit 11 → Environment call from M-mode + +Action Taken on Match +~~~~~~~~~~~~~~~~~~~~~ +- Breakpoint (``action == 0``): + - Raises exception + - Updates ``mstatus``, ``mepc``, ``mcause`` + +- Debug Entry (``action == 1``): + - Requests debug mode entry + - Updates ``dpc``, ``dcsr`` + +Pseudocode +~~~~~~~~~~ +.. code-block:: text + + If etrigger is enabled and type is 0x5: + If current priv level matches trigger (m/s/u): + If tdata2[exception_cause] is set: + Mark hit + If action == 0: raise breakpoint + If action == 1: enter debug mode + In debug mode: + Clear hit and trigger state + + + +Itrigger +-------- +The ``itrigger`` trigger monitors **interrupt causes** and fires a trigger action when a matching interrupt occurs at the configured privilege level. This allows catching specific hardware or software interrupt events and take debugging or trapping action immediately. + +Prerequisites +~~~~~~~~~~~~~ +- ``SDTRIG`` and ``Itrigger`` configuration bits must be enabled. +- Trigger type must be ``4'd4`` in ``tdata1``. + +Trigger Match Logic +~~~~~~~~~~~~~~~~~~~ +- The trigger matches when both of the following are true: + + - The current exception (`ex_i.cause`) is a valid interrupt (i.e., MSB of the cause is set). + - The lower 5 bits of `ex_i.cause` index into a set bit in the interrupt mask (`tdata2`). + - Privilege mode matches enabled flags in ``tdata1`` (``m``, ``s``, ``u``). + +- On a match: + - The normal exception is suppressed. + - The ``hit`` bit is latched. + - The configured ``action`` is taken: + - ``0`` → raise a breakpoint exception + - ``1`` → enter debug mode + +- When in debug mode: + - The ``hit`` bit and trigger state are cleared + +Key Fields +~~~~~~~~~~ +- ``tdata1``: + - ``action``: Determines what to do when the interrupt matches: + - ``0``: Breakpoint + - ``1``: Debug mode + - ``m``, ``s``, ``u``: Privilege level match + - ``hit``: Set on match + +- ``tdata2``: Interrupt cause bitmask + +Action Taken on Match +~~~~~~~~~~~~~~~~~~~~~ +- Breakpoint (``action == 0``): + - Raises exception + - Updates ``mstatus``, ``mepc``, ``mcause`` + +- Debug Entry (``action == 1``): + - Requests debug mode entry + - Updates ``dpc``, ``dcsr`` + +Pseudocode +~~~~~~~~~~~~ +.. code-block:: text + + If itrigger is enabled and type is 0x4: + If ex_i.cause[XLEN-1] == 1 (interrupt): + If tdata2[ex_i.cause[4:0]] is set: + If current priv level matches tdata1 (m/s/u): + Mark hit + If action == 0: raise breakpoint + If action == 1: enter debug mode + In debug mode: + Clear hit and internal match state + diff --git a/docs/01_cva6_user/index.rst b/docs/01_cva6_user/index.rst index 6ca5b007270..f086acf8aa0 100644 --- a/docs/01_cva6_user/index.rst +++ b/docs/01_cva6_user/index.rst @@ -42,6 +42,12 @@ CVA6 User Manual RVZbb RVZbc RVZbs + RVZbkb + RVZbkc + RVZbkx + RVZkne + RVZknd + RVZknh RVZicsr RVZifencei RVZicond @@ -62,3 +68,4 @@ CVA6 User Manual + diff --git a/docs/01_cva6_user/user_cfg_doc.rst b/docs/01_cva6_user/user_cfg_doc.rst index d0e52b1a1bd..cec1dbb2328 100644 --- a/docs/01_cva6_user/user_cfg_doc.rst +++ b/docs/01_cva6_user/user_cfg_doc.rst @@ -262,7 +262,7 @@ * - ``TechnoCut`` - ``bit`` - - Is Techno Cut instanciated + - Is Techno Cut instantiated * - ``SuperscalarEn`` - ``bit`` diff --git a/docs/02_cva6_requirements/cva6_requirements_specification.rst b/docs/02_cva6_requirements/cva6_requirements_specification.rst index da5605efbb0..57bf1d9e7e2 100644 --- a/docs/02_cva6_requirements/cva6_requirements_specification.rst +++ b/docs/02_cva6_requirements/cva6_requirements_specification.rst @@ -1,9 +1,9 @@ =============================== CVA6 Requirement Specification =============================== -Editor: **Jerome Quevremont** +Editor: **Jérôme Quévremont** -Revision 1.0.1 +.. Revision 1.0.1 .. _license: @@ -35,20 +35,19 @@ configured as a 32- or 64-bit core (RV32 or RV64). It includes L1 caches, optional MMU, optional PMP and optional FPU. It is an industrial evolution of ARIANE created by ETH Zürich and the -University of Bologna. It is written in SystemVerilog and maintained by -the OpenHW Group. +University of Bologna. It is written in SystemVerilog and maintained at +the OpenHW Foundation, part of Eclipse Foundation. This specification is organized as requirements that apply to the “Scope of the IP”. -The requirement list is to be approved by the OpenHW Group Technical -Work Group (TWG), as well as its change requests. +The requirement list is maintained by the project committers. -The specification will be complemented by a user’s guide. +The specification is complemented by a user’s guide. -Revision 1.0.0 refers to the product of the first CVA6 project led at -OpenHW Group. It is a placeholder in case of future evolutions after -project freeze (PF gate). +.. Revision 1.0.0 refers to the product of the first CVA6 project led at +.. OpenHW Group. It is a placeholder in case of future evolutions after +.. project freeze (PF gate). A list of abbreviations is available at the end of this document. @@ -79,7 +78,7 @@ As displayed in the picture above, the IP comprises: - The CVA6 core; -- L1 write-through cache; +- L1 caches; - Optional FPU; @@ -117,7 +116,7 @@ support…​”, “…​should reduce latency…​”). These are not in the scope of this specification: - SW layers, such as compiler and OSes (that can however be part of the - OpenHW Group CVA6 project); + OpenHW Foundation CVA6 project); - SW emulation of RISC-V optional extensions ( feasible but the scope of the IP is the core hardware); @@ -136,19 +135,22 @@ Initial Release The CVA6 is highly configurable via SystemVerilog parameters. It is not practical to fully document and verify all possible combinations of parameters, so a set of "viable IP configurations" has been defined. -The full list of parameters for this configuration will be detailed in the users’ guide. + +The full list of parameters for these configuration are detailed in the users’ guide. Below are the configuration of the first releases of the CVA6. -+--------------------+---------+---------+------+-------+---------+---------+---------+---------+ -| Release ID | Target | ISA | XLEN | FPU | CV-X-IF | MMU | L1 D$ | L1 I$ | -+====================+=========+=========+======+=======+=========+=========+=========+=========+ -| ``CV32A60X`` | ASIC | IMC | 32 | No | Yes | None | 2 kB | 2 kB | -+--------------------+---------+---------+------+-------+---------+---------+---------+---------+ -| ``CV32A60AX`` | ASIC | IMC | 32 | No | Yes | Sv32 | 16kB | 16 kB | -+--------------------+---------+---------+------+-------+---------+---------+---------+---------+ ++--------------------+---------+-----------------+------+-------+---------+---------+---------+---------+ +| Release ID | Target | ISA (main ext.) | XLEN | FPU | CV-X-IF | MMU | L1 D$ | L1 I$ | ++====================+=========+=================+======+=======+=========+=========+=========+=========+ +| ``CV32A60X`` | ASIC | IMC | 32 | No | Yes | None | None | None | ++--------------------+---------+-----------------+------+-------+---------+---------+---------+---------+ +| ``CV32A60AX`` | ASIC | IMC | 32 | No | Yes | Sv32 | 16kB | 16 kB | ++--------------------+---------+-----------------+------+-------+---------+---------+---------+---------+ +| ``CV64A60AX`` | ASIC | IMACFDB | 64 | Yes | Yes | Sv39 | 32kB | 32 kB | ++--------------------+---------+-----------------+------+-------+---------+---------+---------+---------+ -CV32A60X could evolve to CV32A65X if the team decides to integrate the dual-issue optional architectural feature. +.. note:: CV32A60X is the first fully verified (TRL-5) configuration of CVA6. .. Possible Future Releases .. ------------------------ @@ -157,7 +159,7 @@ CV32A60X could evolve to CV32A65X if the team decides to integrate the dual-issu .. The full list of parameters for these configurations will be detailed in the users’ guide if and when these configurations are fully verified. .. .. +--------------------+---------+--------+------+-------+---------+---------+---------+---------+ -.. | Configuation ID | Target | ISA | XLEN | FPU | CV-X-IF | MMU | L1 D$ | L1 I$ | +.. | Configuration ID | Target | ISA | XLEN | FPU | CV-X-IF | MMU | L1 D$ | L1 I$ | .. +====================+=========+========+======+=======+=========+=========+=========+=========+ .. | cv32a6_imacf_sv32 | FPGA | IMACF | 32 | Yes | TBD | Sv32 | 32 kB | 16 kB | .. +--------------------+---------+--------+------+-------+---------+---------+---------+---------+ @@ -245,7 +247,7 @@ General requirement +-----------------------------------+-----------------------------------+ As the RISC-V specification leaves space for variations, this -specification specificies some of these variations. +specification specifies some of these variations. .. _risc_v_standard_instructions: @@ -311,8 +313,8 @@ independent requirements. +-----------------------------------+-----------------------------------+ | ISA-130 | CVA6 should support as an | | | **option** the **Zicond** | -| | extension(ratification pending) | -| | version 1.0. | +| | extension (integer conditional | +| | operations) version 1.0. | +-----------------------------------+-----------------------------------+ | ISA-140 | CVA6 should support as an | | | **option** the **Zcb** | @@ -322,9 +324,20 @@ independent requirements. | | **option** the **Zcmp** | | | extension version 1.0. | +-----------------------------------+-----------------------------------+ +| ISA-160 | CVA6 should support as an | +| | **option** the **Zcmt** | +| | extension version 1.0. | ++-----------------------------------+-----------------------------------+ +| ISA-170 | CVA6 should support as an | +| | **option** the **Zkn** extension | +| | (NIST algorithm suite). The | +| | **Zkn** extension comprises the | +| | **Zbkb**, **Zbkc**, **Zbkx**, | +| | **Zkne**, **Zknd** and **Zknh** | +| | extensions. | ++-----------------------------------+-----------------------------------+ - -Note to ISA-60 and ISA-70: CV64A6 cannot support the D extension with +Note to ISA-60 and ISA-70: CV64A6 cannot support the D extension without the F extension. .. _privileges_and_virtual_memory: @@ -359,6 +372,11 @@ The MMU includes a TLB and a hardware PTW. | | **option** the **H** extension | | | (hypervisor) version 1.0. | +-----------------------------------+-----------------------------------+ +| PVL‑70 | CVA6 shall support as an | +| | **option** the **Svnapot** | +| | (NAPOT Translation Contiguity) | +| | extension version 1.0. | ++-----------------------------------+-----------------------------------+ .. _csr: @@ -366,7 +384,7 @@ CSR --- There are no requirements related to CSR as they derive from other -requirements, such as PVL-10, PVL-60… Details of CSRs will be available +requirements, such as PVL-10, PVL-60… Details of CSRs are available in the user’s manual. .. _performance_counters: @@ -450,7 +468,7 @@ applications. | | counterparts in CV32A6). | +-----------------------------------+-----------------------------------+ -The user’s manual will detail the list of counters, events and related +The user’s manual details the list of counters, events and related controls. .. _cache_requirements: @@ -487,11 +505,8 @@ where a high level of timing predictability is needed. | | cycles. The upper-bound is fixed | | | but not specified here. | +-----------------------------------+-----------------------------------+ -| L1W‑20 | L1WTD shall not change the order | -| | of write accesses to the external | -| | memory with respect to the order | -| | of write accesses (stores) | -| | received from the CVA6 core. | +| L1W‑20 | L1WTD shall support RISC-V | +| | Weak Memory Ordering (RVWMO). | +-----------------------------------+-----------------------------------+ | L1W‑30 | L1WTD should offer the | | | following size/ways | @@ -545,6 +560,12 @@ size/ways configurations may be implemented in the design. The design will support one replacement policy allowed by L1W-80. +These L1WTD requirements apply to the legacy WT cache from PULP. + +They also apply to the HPDCache that is superseding the legacy PULP caches. +Note that the HPDCache has more features, such as write-back options, that +are beyond the scope of this specification. + .. _l1_instruction_cache: L1 Instruction cache @@ -603,6 +624,9 @@ size/ways configurations may be implemented in the design. The design will support one replacement policy allowed by L1I-50. +These requirements apply to the HPICache, a modified version of HPDCache, that +will likely supersede the legacy PULP cache. + .. _fence_t_custom_instruction: FENCE.T custom instruction @@ -650,8 +674,16 @@ integrated in the continuous integration flow. | PPA‑10 | CVA6 should be resource-optimized | | | on FPGA and ASIC targets. | +-----------------------------------+-----------------------------------+ -| PPA‑20 | CVA6 should deliver more than 2.1 | -| | CoreMark/MHz. | +| PPA‑20 | CVA6 should target 3.0 | +| | CoreMark/MHz , assuming a | +| | sufficiently fast memory | +| | hierarchy. | ++-----------------------------------+-----------------------------------+ +| PPA‑25 | CVA6 should target as an | +| | **option** 4.5 | +| | CoreMark/MHz, assuming a | +| | sufficiently fast memory | +| | hierarchy. | +-----------------------------------+-----------------------------------+ | PPA‑30 | CV32A6 should run at more than | | | 150 MHz in the cv32a6_imac_sv32 | @@ -675,6 +707,8 @@ integrated in the continuous integration flow. | | performance per MHz. | +-----------------------------------+-----------------------------------+ +PPA-25 comes with the optional dual-issue feature. + .. _interface_requirements: Interface requirements @@ -785,11 +819,21 @@ integration in FPGA and ASIC design flows: | RUL‑40 | CVA6 should not include | | | technology-dependent blocks. | +-----------------------------------+-----------------------------------+ +| RUL-50 | CVA6 should support as an | +| | **option** protection of SRAM | +| | against single-event upsets (SEU).| ++-----------------------------------+-----------------------------------+ If technology-dependent blocks are used, e.g. to improve PPA on certain targets, the equivalent technology-independent block should be available. Parameters can be used to select between the implementations. +Also refer to https://github.com/openhwgroup/cva6/blob/master/CONTRIBUTING.md +for contribution guidelines. + +.. attention:: + RUL-10 is not supported by CVA6 as of now. + .. _list_of_abbreviations: List of abbreviations @@ -815,6 +859,7 @@ List of abbreviations | LFSR: Linear Feedback Shift Register | LRU: Least Recently Used | MMU: Memory Management Unit +| NAPOT: Naturally aligned power-of-two | OS: Operating System | PF: Project Freeze | PPA: Power Performance Area @@ -823,7 +868,6 @@ List of abbreviations | RW: Read Write | SW: Software | TLB: Translation Lookaside Buffer -| TWG: Technical Work Group | WB: Write-Back | WT: Write-Through diff --git a/docs/03_cva6_design/MMU.rst b/docs/03_cva6_design/MMU.rst index 7e67fea64c3..5f5024fe9bf 100644 --- a/docs/03_cva6_design/MMU.rst +++ b/docs/03_cva6_design/MMU.rst @@ -255,7 +255,7 @@ The MMU block can be parameterized to support sv32, sv39 and sv39x4 virtual memo - in - CSR RegFile - logic - - Enables virtual memory translation for instrucionts + - Enables virtual memory translation for instructions * - ``en_ld_st_translation_i`` - in @@ -1159,7 +1159,7 @@ Figure shows every possible path that traverses to find out the PLRU entry. If t .. raw:: html -

Table 9: Entry Selection for Reaplacement

+

Table 9: Entry Selection for Replacement

+-------------------+---------------+----------------------+ | **Path Traverse** | **PLRU Bits** | **Entry to replace** | @@ -1887,7 +1887,7 @@ Page Table Walker is implemented as a finite state machine. It listens to shared * **IDLE:** The initial state where the PTW is awaiting a trigger, often a Shared TLB miss, to initiate a memory access request. In the case of the Hypervisor extension, the stage to which the translation belongs is determined by the enable_translation_XX and en_ld_st_translation_XX signals. There are 3 possible stages: (i) S-Stage - the PTW current state is translating a guest-virtual address into a guest-physical address; (ii) G-Stage Intermed - the PTW current state is translating memory access made from the VS-Stage during the walk to host-physical address; and (iii) G-Stage Final - the PTW current state is translating the final output address from VS-Stage into a host-physical address. When Hypervisor is not enabled PTW is always in S_STAGE. * **WAIT_GRANT:** Request memory access and wait for data grant -* **PTE_LOOKUP:** Once granted access, the PTW examines the valid Page Table Entry (PTE), checking attributes to determine the appropriate course of action. Depending on the STAGE determined in the previous state, pptr and other atributes are updated accordingly. +* **PTE_LOOKUP:** Once granted access, the PTW examines the valid Page Table Entry (PTE), checking attributes to determine the appropriate course of action. Depending on the STAGE determined in the previous state, pptr and other attributes are updated accordingly. * **PROPAGATE_ERROR:** If the PTE is invalid, this state handles the propagation of an error, often leading to a page-fault exception due to non-compliance with access conditions. * **PROPAGATE_ACCESS_ERROR:** Propagate access fault if access is not allowed from a PMP perspective * **WAIT_RVALID:** After processing a PTE, the PTW waits for a valid data signal, indicating that relevant data is ready for further processing. diff --git a/docs/03_cva6_design/_static/bht2lvl.png b/docs/03_cva6_design/_static/bht2lvl.png new file mode 100644 index 00000000000..60f53c6cb40 Binary files /dev/null and b/docs/03_cva6_design/_static/bht2lvl.png differ diff --git a/docs/03_cva6_design/_static/ld_pipeline_diagram.svg b/docs/03_cva6_design/_static/ld_pipeline_diagram.svg index f559adbe923..6ff74956961 100644 --- a/docs/03_cva6_design/_static/ld_pipeline_diagram.svg +++ b/docs/03_cva6_design/_static/ld_pipeline_diagram.svg @@ -142,7 +142,7 @@ Two cycle memory access. The cache is physically indexed and virtually tagged. Multicycle memory access. Address translation -is perforemd in the same cycle. +is performed in the same cycle. Same as option one but the addressing of the cache needs to be delayed until the whole address has successfully been translated. diff --git a/docs/03_cva6_design/commit_stage.rst b/docs/03_cva6_design/commit_stage.rst index 878d7e43cfe..71430f4f919 100644 --- a/docs/03_cva6_design/commit_stage.rst +++ b/docs/03_cva6_design/commit_stage.rst @@ -22,7 +22,7 @@ In addition to retiring instructions the commit stage also manages the various exception sources. In particular at time of commit exceptions can arise from three different sources. First an exception has occurred in any of the previous four pipeline stages (only four as PC Gen can't -throw an exception). Second an exception happend during commit. The only +throw an exception). Second an exception happened during commit. The only source where during commit an exception can happen is from the CS register file and from an interrupt. diff --git a/docs/03_cva6_design/ex_stage.md b/docs/03_cva6_design/ex_stage.md index c3a083eb587..7e9b706413b 100644 --- a/docs/03_cva6_design/ex_stage.md +++ b/docs/03_cva6_design/ex_stage.md @@ -38,7 +38,7 @@ issued to a functional unit and monitor the branch prediction information. If a branch was accidentally predicted on a non-branch instruction it also takes corrective action and re-sets the PC to the correct address (depending on whether the instruction was compressed or -not it add PC `+ 2` or PC `+ 4`). +not it adds PC `+ 2` or PC `+ 4`). As briefly mentioned in the section about instruction re-aligning the branch unit places the PC from an unaligned 32-bit instruction on the @@ -121,9 +121,9 @@ is described in more detail in the upcoming paragraphs: ##### LSU Bypass {#par:lsu_bypass} -The LSU bypass module is a auxiliary module which manages the LSU status +The LSU bypass module is an auxiliary module which manages the LSU status information (full flag etc.) which it presents to the issue stage. This -is necessary for a the following reason: The design of the LSU is critical in +is necessary for the following reason: The design of the LSU is critical in most aspects as it directly interfaces the relatively slow SRAMs. It additionally needs to do some costly operation in sequence. The most costly (in terms of timing) being address generation, address translation and checking @@ -194,7 +194,7 @@ signal of the commit queue goes to the commit stage. Commit stage will stall if it the commit queue can't accept any new data items. On every committed store the commit stage also asserts the `lsu_commit` signal which will put the particular entry from the speculative queue into the -non-sepculative (commit) queue. +non-speculative (commit) queue. As soon as a store is in the commit queue the queue will automatically try to commit the oldest store in the queue to memory as soon as the @@ -290,7 +290,7 @@ access to the (translated) physical address. However, PMPs must be checked during the page table walk as well. During a page walk, all memory access must pass the PMP rules. -The amount of entries is parametrizable under the +The amount of entries is parameterizable under the `CVA6Cfg.NrPMPEntries` parameter. However, the core only supports granularity 8 (G=8). This simplifies the implementation since we do not have to worry about any unaligned accesses. There are a total of @@ -317,10 +317,10 @@ division is a simple serial divider which needs 64 cycles in the worst case. #### CSR Buffer -The CSR buffer a functional unit which its only purpose is to store the +The CSR buffer is a functional unit which only purpose is to store the address of the CSR register the instruction is going to read/write. There are two reasons why we need to do this. The first reason is that -an CSR instruction alters the architectural state, hence this +a CSR instruction alters the architectural state, hence this instruction has to be buffered and can only be executed as soon as the commit stage decides to commit the instruction. The second reason is the way the scoreboard entry is structured: It has only one result diff --git a/docs/03_cva6_design/id_stage.md b/docs/03_cva6_design/id_stage.md index 81ef701e900..3e9fcf286a5 100644 --- a/docs/03_cva6_design/id_stage.md +++ b/docs/03_cva6_design/id_stage.md @@ -79,7 +79,7 @@ It gets incrementally processed further down the pipeline. The scoreboard entry controls operand selection, dispatch and the execution. Furthermore it contains an exception entry which strongly ties the particular instruction to its potential exception. As the first time an -exception could have occoured was already in the IF stage the decoder +exception could have occurred was already in the IF stage the decoder also makes sure that this exception finds its way into the scoreboard entry. A potential illegal instruction exception can occur during decoding. If this is the case and no previous exception has happened the diff --git a/docs/04_cv32a65x/tristan/README.md b/docs/04_cv32a65x/tristan/README.md index 9b7111edc71..b285d5e040e 100644 --- a/docs/04_cv32a65x/tristan/README.md +++ b/docs/04_cv32a65x/tristan/README.md @@ -1,6 +1,6 @@ This directory contains documents written for Tristan project. -- [Verification Specifications](./verif-spec/verification_specifications.adoc) -This document describes the CVA6 verification strategy and implementation. -- [Tandem-Based Verification](./tandem-verification/tandem.adoc) -This document describes the CVA6 tandem (lockstep) verification infrastructure and contains associated User and Reference Manuals. +- [Verification Specifications](./verification/README.adoc) +This is the top-level verification document that describes the CVA6 verification strategy and implementation. +- [Tandem-Based Verification](./verification/tandem/README.adoc) +The collection of documents under `verification/tandem` describes in detail the CVA6 tandem (lockstep) verification infrastructure and contains associated User and Reference Manuals. diff --git a/docs/04_cv32a65x/tristan/tandem-verification/tandem.adoc b/docs/04_cv32a65x/tristan/tandem-verification/tandem.adoc deleted file mode 100644 index 46a139f5d23..00000000000 --- a/docs/04_cv32a65x/tristan/tandem-verification/tandem.adoc +++ /dev/null @@ -1,321 +0,0 @@ -= Tandem-based verification -:toc: - -This document describes the OpenHW Group functional verification environment based on lockstep ("tandem") simulation of a RISC-V reference model and an RTL implementation of a RISC-V core. - -It is divided into two parts: - -* a User Manual which discusses the principle, the architecture and the usage of the environment, and outlines future work; -* a Reference Manual which provides a reference of configuration parameters and programming interfaces to support hardware designers, software developers, and verification engineers. - -== User Manual - -=== Scope of verification - -The verification is performed on the CVA6 core, with the exclusion of interrupt controllers, platform-related mechanisms (real-time timer), peripherals etc. - -The behaviors that are verified are: - -* instruction completion -* general-purpose register value changes -* CSR value changes -* memory operations (as seen by the CVA6 core) -* raising of exceptions -* raising of interrupts -* trap entry and return - -=== Basic Architecture and Design Choices - -Tandem-based functional verification of an RTL design consists in a lockstep comparison of the behavior of an RTL implementation against the behavior of a reference model (usually an Instruction Set Simulator, or ISS), both executing the same programs from the same initial state. In opposition to post-execution trace comparison, the tandem approach enables immediate detection of differences in observable behavior of the RTL implementation and the reference model, thus greatly simplifying the investigation of the root causes of any discrepancies. - -The OpenHW Group tandem verification environment relies on the use of RVFI (RISC-V Formal Interface, https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md). RVFI provides a well-defined abstraction of design state at each instruction commit or exception occurrence. - -RVFI events are collected from both RTL and reference model side, and the RVFI states of both simulations are compared after every step. - -The reference model is a slave to the RTL model; it performs an execution step only when the RTL model has completed the current step. This enables partial verification of behaviors involving values that depend on micro-architecture features, e.g., clock cycle counts. The RTL provides the actual values of such registers to the reference model; these values are trusted by the reference model and hence, the reads of CSR registers yield the same results in the reference model as they do in the RTL simulation. - -The RTL simulation environment provides the testbench and the required abstractions of platform-level resources and behaviors. To match the features of the RTL environment, the reference model needs to include a basic platform abstraction that at the very minimum contains a memory model. For this reason Spike is a prime choice as it contains a superset of the minimum platform needed, cf. xref:fig-spike-platform[xrefstyle=short]. - -.High-level view of the platform supported by Spike -[#fig-spike-platform] -image::figures/Spike-simulation-scope.svg[High-level view of Spike platform,1024] - -In order to ease the integration with RTL simulators, the tandem infrastructure does not depend on the availability of a fully-featured UVM implementation. Instead, it uses a limited subset of UVM to provide a uniform SystemVerilog interface across all supported RTL simulators, whether commercial or open-source. - -==== Operation - -The principle of operation of CVA6 tandem verification is shown in xref:fig-overall-tandem-flow[xrefstyle=short]. The execution of the tandem simulation is controlled by the main RTL simulation loop that is managed either by the "run" phase of the UVM testbench, or explicitly in a test harness. The RTL simulation runs through successive clock cycles until the RVFI state of the RTL model is marked as valid, indicating an instruction commit or an exception in the current RTL clock cycle. - -.Overall tandem verification flow -[#fig-overall-tandem-flow] -image::figures/overall-tandem-architecture.svg[Tandem verification flow,1024] - -In the CVA6 RTL implementation multiple commits or exceptions can occur in a single cycle. If multiple simultaneous events are reported by RVFI, the corresponding entries in the RFVI interface are always ordered in the sequential execution order. For each commit or exception reported by the RVFI interface of the RTL model, the tandem control loop performs a single step of the reference model and compares the RVFI state between the current RTL-side RVFI entry and the reference model RVFI output. Per-commit entries in the RFVI interface are ordered in the sequential execution order, - -Interrupt and debug events detected by the RTL model are injected into the reference model at the beginning of each step. Likewise, the most recent *previously* committed values of microarchitecture-dependent CSRs such as clock cycle counters (`cycle`/`cycleh`, `mcycle`/`mcycleh`) are injected before the reference model step since the RTL values of these registers already correspond to RTL state *after* the corresponding RTL event. - -//.Stages of a single reference model step -//[#fig-refmodel-step] -//image::figures/refmodel-step-stages.svg[Stages of a reference model step,800,opts=inline] - -If a discrepancy in RFVI state is detected, an appropriate human-readable error output is written into the log file and the error count of the simulation is incremented. The tandem simulation stops once a preset number of errors is encountered. By controlling the error count limit is it possible to accommodate transient differences between the RTL and reference model states. A typical example of transient difference occurs when two instructions are committed in a single cycle by a superscalar RTL implementation, causing the counter of retired instructions `minstret` to be atomically incremented by two whereas the reference model will always commit instruction one by one, thus incrementing `minstret` by one each time. - -At the end of a tandem simulation a Yaml report file is produced. It contains information about the test setup (architecture, ISA, test name, etc.) and the list of mismatches found if any. - -For the purpose of CVA6 core verification the core-level interrupt controller (CLIC) is **not** modeled; instead, interrupt management is performed by the testbench. The RTL core model receives interrupt notifications from the testbench through the available interrupt input ports. When the RTL model of the core detects an interrupt, the information about the interrupt is passed to the reference model by reconstructing the value of the `mip` (Machine Interrupt Pending) CSR from the value of the `mcause` register to ensure that the interrupt taken is the same as the one already taken by the RTL simulation. The actual RTL value of the `mip` register may contain additional bits which are set; it will be injected into the reference model state at the end of the reference model step. - -==== Implementation - -The RTL testbenches use DPI functions to control Spike stepping, inject CSR values and query Spike's RVFI interface. - -The selection of single/tandem operation mode is achieved using the SystemVerilog macro `SPIKE_TANDEM`. If defined to a non-zero ("true") value, it enables the tandem configuration in the RTL simulation by instantiating and connecting the Spike wrapper, and activates the stepping and RVFI compare functions. - -The selection of file locations for the Yaml configuration and the Yaml report file locations is performed using dedicated "plusarg" command-line options added to the testbenches: - -* `+config_file=` sets the name of the Yaml configuration file to `` -* `+report_file=` sets the name of the Yaml tandem report file to ``. - -Option `+config_file` should only be used when an appropriate configuration file exists, and should be omitted otherwise. - -SystemVerilog code of the tandem infrastructure is maintained in OpenHW Group repositiory `core-v-verif` (https://github.com/openhwgroup/core-v-verif) which also contains the UVM components and agents that leverage the pure SystemVerilog layer. - -A pure SystemVerilog tandem testbench for CVA6 is available in the OpenHW Group CVA6 repository (https://github.com/openhwgroup/cva6/). - -To limit the impact on the Spike original code base, Spike modifications rely on "shim" (adapter) classes that add extra functionality in two ways: - -* by adding a new base class below the original base class (used for CSRs) -* by specializing a class to provide additional interfaces (Processor and Simulation) - -Spike execution model was modified to run a single-instruction step function instead of the performance-optimized "instruction batch" mode that executes hundreds to thousands of instructions without yielding control to the environment of the simulated design. - -In order to provide fine-grained control over the configuration of the simulated design, Spike was extended with a parameter mechanism with the following characteristics: - -* multiple ways of controlling Spike simulator behavior: -** configuration files (Yaml) -** DPI API -** C++ API -** additional command-line options -* ability to set platform-related values (memory map, boot addresses) -* ability to set implementation-defined values (number of PMP regions in total, vendor ID, architecture ID, implementation ID, ...) -* extended CSR control: -** availability or not of any CSR -** CSR initialization masks and values -** CSR write-enable masks with bit granularity -* ability to inject CSR values from the RTL model for architecture-dependent CSRs (`cycles`/`cyclesh`, `mcycles`/`mcyclesh`, `mip` etc.) - -Spike modifications are maintained in a forked Spike tree integrated into the OpenHW `core-v-verif` repository (https://github.com/openhwgroup/core-v-verif/). - -=== Fundamental limitations of the tandem verification approach - -* By definition, a reference model based on an instruction set simulator has only the notion of instruction commits and is not capable of representing the behaviors between commits (transient signals, micro-architectural artefacts such as stalls etc.) -+ -Such behaviors must be verified by other means. - -* Simultaneous occurrence of the same error in both reference model and RTL implementation will not be detected since the two behaviors will match. -+ -This stresses the importance of validation of the reference model against the specification. - -* Since the reference model for tandem verification does not include an interrupt controller, the presence of pending interrupts must be notified to the `mip` register by other means. -+ -In the OpenHW Group solution, the presence of the interrupt is detected by the RTL model and the information about the actual interrupt raised as the result of interrupt arbitration is passed to the reference model in the `mcause` register. The value in `mcause` is then used to trigger the corresponding event in the reference model. - -* Transient discrepancies can be caused by differences between purely sequential and concurrent model execution. -+ -Spike executes instructions in sequence whereas a superscalar architecture may commit multiple instructions in a single cycle; this means that some CSR updates may differ between Spike and RTL, typically MINSTRET may advance by 2 or more in the RTL model, yet Spike will increment it by 1 at every instruction committed. - -=== QuickStart Guide - -==== Build instructions - -The standard build procedure of Spike supplied with the CVA6 project (https://github.com/openhwgroup/cva6/) builds a Spike binary with all necessary modifications required for DPI interfacing to the RTL testbench. - -Building Spike with tandem extensions requires the availability of `CMake` in version 3.16 or higher. The `yaml-cpp` source package (https://github.com/jbeder/yaml-cpp) that is used to parse and manipulate Yaml configurations is a submodule of Spike and will be downloaded when performing a recursive clone or update of the CVA6 repository. - -If a rebuild is required in an existing setup, it is necessary to either select a different installation directory for Spike or to remove the current installation directory of Spike. It is also necessary to remove Spike build directories `verif/core-v-verif/vendor/riscv/riscv-isa-sim/build` (Spike proper) and `verif/core-v-verif/vendor/riscv/riscv-isa-sim/yaml-cpp/build` (`yaml-cpp` library). - -==== Understanding the Spike configuration file - -Spike configuration files represent a Spike parameter tree in the form of nested Yaml dictionaries under a common root node `spike_param_tree`: - -[,yaml] ----- - spike_param_tree: - bootrom_enable: true - bootrom_base: 0x10000 - bootrom_size: 0x1000 - dram_enable: true - dram_base: 0x80000000 - dram_size: 0x40000000 - core_configs: - - - isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs - priv: M - extensions: cv32a60x,cvxif - boot_addr: 0x80000000 - marchid_override_mask: 0xFFFFFFFF - marchid_override_value: 0x3 - misa_write_mask: 0x0 ----- - -The first-level entries define platform properties (`bootrom_*` and `dram_*`) and the default settings for all cores of the system (`core_configs`). - -The configuration fragment above instructs the reference model that: - -* the platform contains a boot ROM of size 4 KiB starting at address 0x10000 (0+64 KiB); -* the platform contains a DRAM memory of 1 GiB starting at the address 0x80000000 (0+2 GiB) -* all cores: -** implement an RV32IMC ISA with extensions `Zicsr`, `Zcb`, `Zba`, `Zbb`, `Zbc` and `Zbs`; -** support only the Machine privilege level; -** implement additional features modeled in Spike custom extensions `cv32a60x` (additional CSRs specific to `CV32A6*X` family of cores) and `cvxif` (the CV-X-IF interface); -** boot from address `0x80000000` (the start address of the DRAM memory); -** force the reset value of register `marchid` to value `0x3` (corresponding to the CVA6 architecture); -** discard writes into `misa` CSR register by marking all its bits as non-mutable. - -==== Running simulations in tandem mode - -Currently, tandem simulations are supported out-of-the-box only for CVA6 target `cv32a65x` using RTL simulator configurations `vcs-uvm` (recommended), `vcs-testharness`, `questa-uvm` and `questa-testharness`. Tandem simulations of target `cv32a65x` with Verilator using the `veri-testharness` configuration require Verilator v5.016 or higher. - -Tandem verification is enabled by setting environment variable `SPIKE_TANDEM` to a non-empty value prior to invoking any of the test scripts located in the `verif/regress` directory of the CVA6 source tree. - -**Example:** -[,sh] ----- -export SPIKE_TANDEM=1 ; bash verif/regress/dv-csr-embedded-tests.sh ----- - -The output of tandem simulation is sent to the log file of the RTL simulator, by default `verif/sim/out_/_sim/..log.iss`. - -A machine-processable Yaml report file summarizing the mismatches detected during the simulation is stored in a separate report file, by default `verif/sim/out_/_sim/..log.yaml`. It contains the configuration of the simulated design, the number of mismatches that were found (if any) and a list of entries describing the successive mismatches. - -=== How to analyze tandem verification results - -To simplify failure analysis, the RVFI state comparator reports mismatches between commit states of the reference model and the RTL model at all verbosity levels. However, it produces no output if the commit states are identical and the verbosioty level is `UVM_LOW`. By controlling output verbosity, the simulation log can be reduced to the sole list of state discrepancies, or it can contain a complete log of commits and exceptions to provide additional context at failure locations. - -A scoreboard discrepancy is represented by a line describing the nature of the error, followed by two lines that provide a summary view of the RVFI state of the reference model and the RTL core. - -**Example:** -[,text] ----- -CSR 304 Mismatch [REF]: 0x0 [CORE]: 0x8 -UVM_INFO @ 45992.000 ns : uvmc_rvfi_scoreboard_utils.sv(206) reporter [spike_tandem] 45992.000 ns | RVFI | 0 | 0 | 800036ac | 30419073 | M | x3 | 00000008 | x0 | 0000000000000000 | csrrw zero, mie, gp -UVM_ERROR @ 45992.000 ns : uvmc_rvfi_scoreboard_utils.sv(211) reporter [spike_tandem] 45992.000 ns | RVFI | 0 | 0 | 800036ac | 30419073 | M | x3 | 00000008 | x0 | 0000000000000000 | csrrw zero, mie, gp <- CORE ----- - -The first line indicates that for current instruction commit the content of the CSR with hexadecimal address `304`, i.e., `mie` ("Machine Interrupt Enable") differs between the reference model (value `0x0`) and the RTL core model (value `0x8`). The next two lines provide details about the current instruction in both models: - -* the current time stamp: `45992.000 ns`, -* the value of PC: `0x800036ac`, -* the encoding of the instruction: hex `30419073`, -* the current privilege mode: `M` (Machine), -* the values of general-purpose register operands of the instruction: `x3` (`gp` in RISC-V ABI) equals `0x00000008`, `x0` equals `0x00000000`. - -Since the values stored into the `mie` CSR differ whereas the instruction executed is the same including the values of its input operands, the discrepancy can only come from the write behavior of the `mie` CSR. In this specific case, bit 3 of the `mie` register is specified as "read-only zero" in the reference model, yet the RTL implementation accepts writes into this specific bit of `mie`. - -The following is the corresponding fragment from the Yaml report, including the configuration and status summary of the simulation run: - -[,yaml] ----- -csrs_match_count: 461 -exit_cause: MISMATCH -exit_code: 0 -instr_count: 3280 -isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei -mismatch_description: 'CSR 304 Mismatch [REF]: 0x880 [CORE]: 0x888 ' -mismatches: -- 0: null - core: - insn: 0000000030419073 - insn_disasm: csrrw zero, mie, gp - mode: 3 - pc_rdata: 00000000800036ac - pc_wdata: 0 - rd1_addr: 0 - rd1_rdata: 0 - rs1_addr: 3 - rs1_rdata: 0000000000000008 - trap: 0 - reference_model: - insn: 0000000030419073 - insn_disasm: csrrw zero, mie, gp - mode: 3 - pc_rdata: 00000000800036ac - pc_wdata: 0 - rd1_addr: 0 - rd1_rdata: 0 - rs1_addr: 3 - rs1_rdata: 0000000000000008 - trap: 0 -[...] -mismatches_count: 5 -simulator: vcs-uvm -target: cv32a65x -test: csr_test -testlist: csr_embedded ----- - -=== Example uses of Yaml reference model parameters - -==== Enable (make "accessible") or disable (make "inaccessible") a CSR - -A Boolean parameter consisting of CSR name and suffix `_accessible`, placed in generic or per-core configuration, indicates whether the given register should be accessible or not. - -**Example**: - -[,yaml] ----- -spike_param_tree: - ... - core_configs: - - - ... - tinfo_accessible: False ----- - -makes the `tinfo` CSR inaccessible in the reference model for all cores, meaning that any attempt to access (read or write) the `tinfo` register when executing an instruction in the reference model will trigger an illegal instruction exception. - -==== Force specific bits in a CSR to a constant value - -The reference model parameters provide two levels of control over the content of CSRs: - -* override the reset value of selected bits of any CSR; -* define which bits of a CSR cannot be modified. - -Assuming that bit 5 of a certain CSR `` should always be set irrespective of the default setting in the reference model, it is necessary to indicate that: - -* the reset value of that bit should be 1; -* writes to that bit should be ignored. - -The parameters needed to express this property are: - -* `_override_mask` which defines which bits of `` should be forced to a specific value at reset, -* `_override_value` which indicates the reset value of the forced bits of ``, -* `_write_mask` which indicates which bits of `` are writable (mask bit is set) and which are not (mask bit is cleared). - -Assuming that the XLEN is 32 and only bit 5 of `` should be fixed, the Yaml settings to use are: - -[,yaml] ----- -spike_param_tree: - ... - core_configs: - - - ... - _override_mask: 0x00000020 - _override_value: 0x00000020 - _write_mask: 0xffffffdf ----- - -=== Integration with the RISC-V Open Source ecosystem - -* The entire tandem verification infrastructure is available as Open Source under SHL 2.0+ (an Apache-type license) in OpenHW Group repositories `cva6` (https://github.com/openhwgroup/cva6/) and `core-v-verif` (https://github.com/openhwgroup/cva6/). - -* The OpenHW Group tandem verification infrastructure relies on Spike (https://github.com/riscv-software-src/riscv-isa-sim/) as reference model. -+ -The tandem verification approach is a general template and is not bound to a single ISS or RTL simulator. However, it requires that the ISS provides a basic platform capable of running software matching the capabilities of the RTL testbench, including a model of memory and buses. -Because of this constraint the current tandem framework relies on Spike which is fully Open Source and provides all necessary components. - -* Verilator-based tandem verification -+ -Starting with version 5.016, Verilator supports tandem simulations. Earlier versions did not provide sufficient support for structured types in the DPI interface. - -include::reference.adoc[] diff --git a/docs/04_cv32a65x/tristan/verification/README.adoc b/docs/04_cv32a65x/tristan/verification/README.adoc new file mode 100644 index 00000000000..030fbf2a82c --- /dev/null +++ b/docs/04_cv32a65x/tristan/verification/README.adoc @@ -0,0 +1,99 @@ += CV32A6 Verification: Strategy, Environment and the Actual Verification Process +:toc: + +== Introduction +=== General Information + +This document describes the CV32A6 verification strategy, the verification environment and the actual verification process that led to the CV32A60X cores reaching TRL5. + +The development of the environment and the actual verification process of the CV32A6 cores was supported by the TRISTAN project. + +[#_Verification_Strategy] +== Verification Strategy + +To verify the CVA6 core, the starting point are the specification documents as +tailored RISC-V International ISA Manuals, OpenHW Foundation specifications (for CV-X-IF and OBI) and CVA6 CSR specifications. See the link:../../../design/design-manual/source/intro.adoc[design documentation] for all the references. + +As CVA6 as many parameters, currently only one configuration is fully verified according the described strategy. It is the so called CV32A60X core. + +From them, link:../../../../verif/docs/VerifPlans/source/index.rst[DV plans] +are written with the help of VP tool. +For each applicable feature in the specifications, several informations are provided in these plans: +e.g. which kind of tests to use, which criteria for passing, which coverage method, unique tag for traceability, link to coverage model. + +Based on these DV plans, on one hand, functional coverage items are implemented in the UVM test bench +and on the second hand, tests are generated. Afterwards, the tests are executed on the test bench. +To ensure the compliance of the RTL, the tests are simultaneously run on Spike, used as reference model. +According to produced test results, functional and code coverage is computed. +If some items (cover group for functional coverage, line and condition for code coverage) are not covered, it means that generated tests are not sufficient or the RTL itself contains useless code. + +image:./media/verif-strategy.png[./media/verif-strategy,width=723,height=295] + +To fill the holes, tests are added (either by better generation or by writing dedicated tests by hand) +and/or RTL code is adapted. +At the end, the few remaining gaps are fully explained (see GitHub tasks +link:https://github.com/openhwgroup/cva6/issues/2870[2870] and +link:https://github.com/openhwgroup/cva6/issues/2908[2908]). + +The coverage results and the checklist regarding the CV32A60X configuration are available on +link:https://github.com/openhwgroup/programs/tree/master/Project-Descriptions-and-Plans/CV32A60X[OpenHW project level documentation GitHub repository]. + +=== Objectives + +In order to ensure that the implementation of the design conforms to the specification and that all parts of the implementation have been exercised during the verification process, the verification of a design involves three key aspects: + +* the generation of stimuli (through statically defined and/or generated tests), +* the checking of behaviors and properties when the design processes the stimuli, +* the coverage analysis of the RTL code of the implementation. + +The checking of behaviors and properties is usually performed by combining several methods: + +* logical properties defined in the specification are typically represented using assertions that must hold true at all times; +* behaviors (especially complex ones) are checked by comparing the state of the design at the end of a test scenario against a reference state encoded in the test, typically one or more expected register values; +* when a reference model is available, the behaviors of the design can be tested against the behaviors of the reference model. + +The comparison of behaviors of the implementation against a reference model can take two forms: + +* post-mortem trace comparison, whereby simulation traces of the implementation and the reference model are compared once both simulations have completed; +* lock-step or "tandem" simulation, whereby both implementation and reference model simulations advance one step at a time and a state comparison between the implementation and the reference model is performed at a common granularity (typically upon instruction completion and trap entry). + +For the verification of the CV32A60X core, the decision was made to rely as much as possible on tandem simulations, complemented with assertions when micro-architectural properties needed to be verified. +This choice was motivated by several factors: + +* a reference model was already available in the form the Spike instruction set simulator; +* tandem simulations provide quasi-immediate feedback in case of divergence between the behavior of the implementation and that of the referece model; +* the team at Thales has an in-depth knowldege of the RTL implementation, the Spike simulator and the UVM framework developed inside OpenHW Foundation. + +=== Approach + +The verification solution retained for CV32A60X and CV32A65X is to combine the UVM framework and Spike into a tandem simulation environment in which the RTL simulator acts as a master and Spike is the slave (see xref:fig-overall-tandem-flow[xrefstyle=short]): + +* The UVM-based RTL simulation advances until an instruction is committed or a trap in entered; +* If a trap was entered, this fact is notified to the reference model; +* The reference model performs the simulation of one instruction; +* If any CSR registers have been modified by hardware without a corresponding software action, their values are injected into reference model state in place of the values reported by the reference model; +* The hart state reported by the reference model after the single instruction is compared against the state of the RTL model; +* If a difference is found, it is reported to the user; +* If a predefined (and adjustable) number of differences is found, the tandem simulation is aborted. + +The structure and operation of the tandem simulation environment is discussed futher in a xref:tandem/README.adoc[dedicated document] which also provides access to reference documentation for Spike and UVM tandem users and developers. + +.Overall tandem verification flow +[#fig-overall-tandem-flow] +image::tandem/figures/overall-tandem-architecture.svg[Tandem verification flow,800] + +The UVM verification environment used in the verification the CV32A60X and CV32A65X cores is further presented in a xref:verification_environment.adoc[separate CV32A6 UVM environment manual] which describes the architecture of the environment, its elements and their interactions. + +The verification process deployed to verify the CV32A60X and CV32A65X cores to TRL5 is described in the xref:verification_process.adoc[CV32A6 verification process document] that discusses the planning, the execution and the outcomes of the verification process using the CV32A6 UVM environment. + +http://www.tristan-project.eu[_www.tristan-project.eu_] + +_info@tristan-project.eu_ + + +[width="100%",cols="28%,72%",options="header",] + +|=== + +|image:./media/image7.png[Graphical user interface, application Description automatically generated,width=173,height=80] |_TRISTAN has received funding from the Key Digital Technologies Joint Undertaking (KDT JU) under grant agreement nr. 101095947. The KDT JU receives support from the European Union’s Horizon Europe’s research and innovation programme and Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Israel, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey. +|=== diff --git a/docs/04_cv32a65x/tristan/verif-spec/media/axiagentmerge.png b/docs/04_cv32a65x/tristan/verification/media/axiagentmerge.png similarity index 100% rename from docs/04_cv32a65x/tristan/verif-spec/media/axiagentmerge.png rename to docs/04_cv32a65x/tristan/verification/media/axiagentmerge.png diff --git a/docs/04_cv32a65x/tristan/verif-spec/media/frontendsb.png b/docs/04_cv32a65x/tristan/verification/media/frontendsb.png similarity index 100% rename from docs/04_cv32a65x/tristan/verif-spec/media/frontendsb.png rename to docs/04_cv32a65x/tristan/verification/media/frontendsb.png diff --git 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b/docs/04_cv32a65x/tristan/verification/media/verif-strategy.png differ diff --git a/docs/04_cv32a65x/tristan/verification/tandem/README.adoc b/docs/04_cv32a65x/tristan/verification/tandem/README.adoc new file mode 100644 index 00000000000..8f4ce9c12b4 --- /dev/null +++ b/docs/04_cv32a65x/tristan/verification/tandem/README.adoc @@ -0,0 +1,126 @@ += CVA6 Tandem Verification +:toc: + +== Quick links + +User manual and technical reference documentation of the tandem simulation framework used in the TRISTAN project can be directly accessed through these links: + +* xref:./tandem-user-guide.adoc[Tandem User Guide] + provides a progressive introduction to tandem simulation using UVM and Spike as deployed for the CV32A60X and CV32A65X cores. +* xref:./uvm-tandem-refman.adoc[UVM Tandem Reference Manual] + describes in detail the UVM-side tandem support. +* xref:./spike-tandem-refman.adoc[Spike Tandem Reference Manual] + contains the programming manual of the Spike part of tandem verification infrastructure. +* xref:./tandem-modifications-for-trl5.adoc[Tandem Modifications for TRL5 Verification of CV32A60X core] + discusses the modifications of Spike and the tandem infrastructure that were necessary to support TRL5 verification of the CV32A60X core. + += Introduction to Tandem Verification + +Tandem-based functional verification of an RTL design consists in a lockstep comparison of the behavior of an RTL implementation against the behavior of a reference model (usually an Instruction Set Simulator, or ISS), both executing the same programs from the same initial state. In opposition to post-execution trace comparison, the tandem approach enables immediate detection of differences in observable behavior of the RTL implementation and the reference model, thus greatly simplifying the investigation of the root causes of any discrepancies. + +The verification is performed on the CVA6 core, with the exclusion of interrupt controllers, platform-related mechanisms (e.g. real-time timer), peripherals etc. + +The behaviors that are verified are: + +* instruction completion +* general-purpose register value changes +* CSR value changes +* memory operations (as seen by the CVA6 core) +* raising of exceptions +* raising of interrupts +* trap entry and return + +== Basic Architecture and Design Choices + +.Overall tandem verification flow +[#fig-overall-tandem-flow] +image::figures/overall-tandem-architecture.svg[Tandem verification flow,1024] + +The tandem simulation environment (see xref:fig-overall-tandem-flow[xrefstyle=short]) consists of: + +* an RTL simulator that models the design and provides a testbench capable of loading programs and reporting changes in design state via a well-defined interface; +* a reference model provided by the Spike ISS that exposes its state on an interface identifcal to that of the RTL simulator; +* a comparison agent that checks if the the state of the RTL simulation and the state of the reference are equivalent. + +To represent simulation state, the OpenHW Group tandem verification environment relies on the use of the RISC-V Formal Interface, or RVFI (https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md). RVFI provides a well-defined abstraction of design state at each instruction commit or exception occurrence. + +RVFI events are collected from both RTL and reference model side, and the RVFI states of both simulations are compared after every step. In the CVA6 RTL implementation, multiple commits or exceptions can occur in a single cycle. If multiple simultaneous events are reported by RVFI, the corresponding entries in the RVFI interface are always ordered in the sequential execution order. For each commit or exception reported by the RVFI interface of the RTL model, the tandem control loop performs a single step of the reference model and compares the RVFI state reported by the RTL simulator and the reference model. + +Since the CVA6 is only a processor core, the simulation of actual program execution requires a minimal platform that will at least contain the memory to store the program and its data and provide a means of loading programs into that memory. The RTL simulation environment provides the required abstractions of platform-level resources and behaviors as part of the testbench. The reference model provides its own platform abstraction which needs to be aligned with the constraints and choices of the RTL platform. For this reason Spike is a prime choice as it contains a superset of the minimum platform needed and its properties can be controlled by means of Spike configuration parameters. + +In order to ease the integration with RTL simulators, the Spike part of tandem infrastructure does not depend on the availability of a fully-featured UVM implementation. Instead, it uses a limited subset of UVM to provide a uniform SystemVerilog interface across all supported RTL simulators, whether commercial or open-source. + +=== Operation + +The principle of operation of CVA6 tandem verification is shown in xref:fig-overall-tandem-flow[xrefstyle=short]. The execution of the tandem simulation is controlled by the main RTL simulation loop that is managed either by the "run" phase of the UVM testbench, or explicitly in a test harness. The RTL simulation runs through successive clock cycles until the RVFI state of the RTL model is marked as valid, indicating an instruction commit or an exception in the current RTL clock cycle. + +Interrupt and debug events detected by the RTL model are injected into the reference model at the beginning of each step. Likewise, the most recent *previously* committed values of microarchitecture-dependent CSRs such as clock cycle counters (`cycle`/`cycleh`, `mcycle`/`mcycleh`) are injected before the reference model step since the RTL values of these registers already correspond to RTL state *after* the corresponding RTL event. + +//.Stages of a single reference model step +//[#fig-refmodel-step] +//image::figures/refmodel-step-stages.svg[Stages of a reference model step,800,opts=inline] + +If a discrepancy in RFVI state is detected, an appropriate human-readable error output is written into the log file and the error count of the simulation is incremented. The tandem simulation stops once a preset number of errors is encountered. By controlling the error count limit is it possible to accommodate transient differences between the RTL and reference model states. A typical example of transient difference occurs when two instructions are committed in a single cycle by a superscalar RTL implementation, causing the counter of retired instructions `minstret` to be atomically incremented by two whereas the reference model will always commit instruction one by one, thus incrementing `minstret` by one each time. + +At the end of a tandem simulation a Yaml report file is produced. It contains information about the test setup (architecture, ISA, test name, etc.) and the list of mismatches found if any. + +For the purpose of CVA6 core verification the core-level interrupt controller (CLIC) is **not** modeled; instead, interrupt management is performed by the testbench. The RTL core model receives interrupt notifications from the testbench through the available interrupt input ports. When the RTL model of the core detects an interrupt, the information about the interrupt is passed to the reference model by reconstructing the value of the `mip` (Machine Interrupt Pending) CSR from the value of the `mcause` register to ensure that the interrupt taken is the same as the one already taken by the RTL simulation. The actual RTL value of the `mip` register may contain additional bits which are set; it will be injected into the reference model state at the end of the reference model step. + +=== Implementation + +The RTL testbenches use DPI functions to control Spike stepping, inject CSR values and query Spike's RVFI interface. + +The selection of single/tandem operation mode is achieved using the SystemVerilog macro `SPIKE_TANDEM`. If defined to a non-zero ("true") value, it enables the tandem configuration in the RTL simulation by instantiating and connecting the Spike wrapper, and activates the stepping and RVFI compare functions. + +The selection of file locations for the Yaml configuration and the Yaml report file locations is performed using dedicated "plusarg" command-line options added to the testbenches: + +* `+config_file=` sets the name of the Yaml configuration file to `` +* `+report_file=` sets the name of the Yaml tandem report file to ``. + +Option `+config_file` should only be used when an appropriate configuration file exists, and should be omitted otherwise. + +SystemVerilog code of the tandem infrastructure is maintained in OpenHW Group repositiory `core-v-verif` (https://github.com/openhwgroup/core-v-verif) which also contains the UVM components and agents that leverage the pure SystemVerilog layer. + +A pure SystemVerilog tandem testbench for CVA6 is available in the OpenHW Group CVA6 repository (https://github.com/openhwgroup/cva6/). + +To limit the impact on the Spike original code base, Spike modifications rely on "shim" (adapter) classes that add extra functionality in two ways: + +* by adding a new base class below the original base class (used for CSRs) +* by specializing a class to provide additional interfaces (Processor and Simulation) + +Spike execution model was modified to run a single-instruction step function instead of the performance-optimized "instruction batch" mode that executes hundreds to thousands of instructions without yielding control to the environment of the simulated design. + +In order to provide fine-grained control over the configuration of the simulated design, Spike was extended with a parameter mechanism with the following characteristics: + +* multiple ways of controlling Spike simulator behavior: +** configuration files (Yaml) +** DPI API +** C++ API +** additional command-line options +* ability to set platform-related values (memory map, boot addresses) +* ability to set implementation-defined values (number of PMP regions in total, vendor ID, architecture ID, implementation ID, ...) +* extended CSR control: +** availability or not of any CSR +** CSR initialization masks and values +** CSR write-enable masks with bit granularity +* ability to inject CSR values from the RTL model for architecture-dependent CSRs (`cycles`/`cyclesh`, `mcycles`/`mcyclesh`, `mip` etc.) + +Spike modifications are maintained in a forked Spike tree integrated into the OpenHW `core-v-verif` repository (https://github.com/openhwgroup/core-v-verif/). + +== Fundamental limitations of the tandem verification approach + +* By definition, a reference model based on an instruction set simulator has only the notion of instruction commits and is not capable of representing the behaviors between commits (transient signals, micro-architectural artefacts such as stalls etc.) ++ +Such behaviors must be verified by other means. + +* Simultaneous occurrence of the same error in both reference model and RTL implementation will not be detected since the two behaviors will match. ++ +This stresses the importance of validation of the reference model against the specification. + +* Since the reference model for tandem verification does not include an interrupt controller, the presence of pending interrupts must be notified to the `mip` register by other means. ++ +In the OpenHW Group solution, the presence of the interrupt is detected by the RTL model and the information about the actual interrupt raised as the result of interrupt arbitration is passed to the reference model in the `mcause` register. The value in `mcause` is then used to trigger the corresponding event in the reference model. + +* Transient discrepancies can be caused by differences between purely sequential and concurrent model execution. ++ +Spike executes instructions in sequence whereas a superscalar architecture may commit multiple instructions in a single cycle; this means that some CSR updates may differ between Spike and RTL, typically MINSTRET may advance by 2 or more in the RTL model, yet Spike will increment it by 1 at every instruction committed. diff --git a/docs/04_cv32a65x/tristan/tandem-verification/figures/Spike-simulation-scope.svg b/docs/04_cv32a65x/tristan/verification/tandem/figures/Spike-simulation-scope.svg similarity index 100% rename from docs/04_cv32a65x/tristan/tandem-verification/figures/Spike-simulation-scope.svg rename to docs/04_cv32a65x/tristan/verification/tandem/figures/Spike-simulation-scope.svg diff --git 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + INTn + + + + step + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + i1 + i2 + i3 + H1 + H2 + + + + + + + + + + + + + + + + + + + committed before INTn taken + + + + + + hold and inject MIP/MIE state associated with INTn + + + + r + + + + e + + + + c + + + + f + + + + g + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + int active + + + + + + INT agent + + + + + + mip + + + + + + mie + + + + + + RTL + + + + + + mip + + + + + + mie + + + + + + Spike + + + + + + diff --git a/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-svg.png b/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-svg.png new file mode 100644 index 00000000000..e2866fe31f8 Binary files /dev/null and b/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-svg.png differ diff --git a/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario.wave b/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario.wave new file mode 100644 index 00000000000..2cb93539f83 --- /dev/null +++ b/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario.wave @@ -0,0 +1,52 @@ +// Copyright 2024 Thales DIS France SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Zbigniew CHAMSKI - Thales + +{signal: [ + { name: 'clk', wave: 'p.PlPlp.Plp|PlPlp'}, + ['INT agent', + ['int active', + {name: 'int #0', wave: '0..........|.....'}, + {name: 'int #n', wave: '01.x.......|.....'}, + ] + ], + {}, + ['RTL', + ['mip', + {name: 'bit[0]', wave: 'x..........|.....'}, + {name: 'bit[n]', wave: '0.1........|.....', + node: '..rC.............'}, + ], + ['mie', + {name: 'bit[0]', wave: '0..........|.....'}, + {name: 'bit[n]', wave: '01..0......|.....', + node: '.e..c............'}, + ], + {name: 'commit0', wave: 'x.72723.723|4242x', data: 'i1 RM i2 RM uarch i3 RM uarch H1 RM H2 RM', + node: '..XCf.....g..J...'}, + ], + { node: '...EF.....GZ.....'}, + ['Spike', + ['mip', + {name: 'bit[0]', wave: 'x..........|.....'}, + {name: 'bit[n]', wave: '0..1.0.....|.....'}, + ], + ['mie', + {name: 'bit[0]', wave: '0..........|.....'}, + {name: 'bit[n]', wave: '0..1.0.....|.....', + node: '.................'}, + ], + {name: 'mcause', wave: 'x..........|.4x..', data: 'INTn'}, + {name: 'step', wave: 'x..7x7x..7x|.4x4x', data: 'i1 i2 i3 H1 H2',}, + {node: '...RS........H...'} + ], + {}, +], + edge: + ['r|X', 'C|R', 'f|F', 'g|G', 'F<->G committed before INTn taken', 'J|H', 'R->H hold and inject MIP/MIE state associated with INTn'], +} diff --git a/docs/04_cv32a65x/tristan/tandem-verification/figures/overall-tandem-architecture.svg b/docs/04_cv32a65x/tristan/verification/tandem/figures/overall-tandem-architecture.svg similarity index 100% rename from docs/04_cv32a65x/tristan/tandem-verification/figures/overall-tandem-architecture.svg rename to docs/04_cv32a65x/tristan/verification/tandem/figures/overall-tandem-architecture.svg diff --git a/docs/04_cv32a65x/tristan/tandem-verification/figures/refmodel-step-stages.svg b/docs/04_cv32a65x/tristan/verification/tandem/figures/refmodel-step-stages.svg similarity index 100% rename from docs/04_cv32a65x/tristan/tandem-verification/figures/refmodel-step-stages.svg rename to docs/04_cv32a65x/tristan/verification/tandem/figures/refmodel-step-stages.svg diff --git a/docs/04_cv32a65x/tristan/tandem-verification/reference.adoc b/docs/04_cv32a65x/tristan/verification/tandem/spike-tandem-refman.adoc similarity index 90% rename from docs/04_cv32a65x/tristan/tandem-verification/reference.adoc rename to docs/04_cv32a65x/tristan/verification/tandem/spike-tandem-refman.adoc index 35109f87723..8ab841b3b66 100644 --- a/docs/04_cv32a65x/tristan/tandem-verification/reference.adoc +++ b/docs/04_cv32a65x/tristan/verification/tandem/spike-tandem-refman.adoc @@ -1,8 +1,10 @@ -== Programming Reference Manual += Tandem Programming Reference Manual: Spike Interface +:toc: -=== Configuration parameter names and scopes -Parameters are referenced by their hierarchical names of the form `PREFIX/PARAM_NAME` that enable a tree-like hierachical structure. Supported values of `PREFIX` are: +== Spike configuration parameter names and scopes + +Parameters are referenced by their hierarchical names of the form `PREFIX/PARAM_NAME` that enable a tree-like hierarchical structure. Supported values of `PREFIX` are: * `/top`: parameter values apply to the complete platform (which may consist of several cores.) * `/top/cores`: parameter values apply to all harts, and can be overridden on a core-by-core basis using core-specific values. @@ -18,9 +20,9 @@ Parameter names are not constrained by the C/C++/SystemVerilog identifier syntax Some parameters are only meaningful in specific scopes: either platform (`/top/`), or core (`/top/cores/` or `/top/core//`). -=== Parameter index +== Parameter index -==== Platform-level parameters +=== Platform-level parameters [cols="1,1,1,5"] |=== @@ -87,7 +89,7 @@ Some parameters are only meaningful in specific scopes: either platform (`/top/` |Number of cores (harts) in the platform. |=== -==== Per-CSR parameters +=== Per-CSR parameters All CSRs of cores in the platform can be controlled wrt. their presence ("availability") using a per-CSR parameter. For each CSR that is available, per-CSR parameters control the initial value, the writable bits and the overall writability of the register. @@ -133,16 +135,21 @@ Depending on the prefix used (`/top/cores/` or `/top/core/`) the core-le |=== |Name |Type |Default |Description -|`boot_addr` -|uint64_t -|`0x10000` -|Boot address for core(s). +|`allow_unmapped_mem_access` +|bool +|`False` +|If `True`, do not raise exceptions upon accessing unmapped memory locations; instead, return zeroes on load and fetch accesses, and do nothing on store accesses. -|`csr_counters_injection` +r|`csr_counters_injection` |bool |`False` |If `True`, inject values of microarchitecture-dependent counter CSRs from RTL into the reference model. Affected CSRs are `cycle`, `cycleh`, `mcycle`, `mcycleh` and `mip`. +|`cvxif_x_num_rs` +|uint64_t +|`3` +|Maximum count of source registers that can be accessed by R4-type instructions of the CV-X-IF interface on this core. + |`debug_exception_handler_addr` |uint64_t |`0x1a140000` @@ -219,7 +226,7 @@ Extensions currently supported: + |`non_standard_interrupts` |bool |`False` -|Support non-standard interrupt notification scheme in which arbitraty patterns can be written into the lower 16 bits of `mie` and `mip` CSRs. +|Support non-standard interrupt notification scheme in which arbitrary patterns can be written into the lower 16 bits of `mie` and `mip` CSRs. |`override_custom_extensions` |bool @@ -268,14 +275,14 @@ Extensions currently supported: + |=== -=== DPI Programming Interface +== DPI Programming Interface The DPI interface is implemented in file `vendor/riscv/riscv-isa-sim/riscv/riscv_dpi.cc` in `core-v-verif` repository (https://github.com/openhwgroup/core-v-verif/). The shared library providing the implementation of the DPI functions to RTL simulators is named `libriscv.so`. It is built during Spike build and is installed in the `lib` subdirectory of Spike installation directory, typically `/tools/spike/lib`. -==== Create a new instance of Spike extended with DPI interfaces suitable for tandem operation +=== Create a new instance of Spike extended with DPI interfaces suitable for tandem operation [,verilog] ---- @@ -334,7 +341,7 @@ Return value: NONE. Before stepping, the entry state of the reference model will be adjusted according to the state of the RTL model. After the step completes, the return state will represent the result of stepping the reference model for one commit (or exception) from the *updated* input state. -==== Set Boolean parameter `` to `` +=== Set Boolean parameter `` to `` [,verilog] ---- @@ -354,7 +361,7 @@ Input args: Return value: NONE. -==== Set uint64_t parameter `` to `` +=== Set uint64_t parameter `` to `` [,verilog] ---- @@ -374,7 +381,7 @@ Input args: Return value: NONE. -==== Set string parameter `` to `` +=== Set string parameter `` to `` [,verilog] ---- @@ -394,7 +401,7 @@ Input args: Return value: NONE. -==== Return the value of Boolean parameter `` +=== Return the value of Boolean parameter `` [,verilog] ---- @@ -413,7 +420,7 @@ Input args: Return value: Current value of Boolean parameter ``. -==== Return the value of uint64_t parameter `` +=== Return the value of uint64_t parameter `` [,verilog] ---- @@ -432,7 +439,7 @@ Input args: Return value: Current value of uint64_t parameter `` -==== Return the value of string parameter `` +=== Return the value of string parameter `` [,verilog] ---- @@ -451,7 +458,7 @@ Input args: Return value: Current value of string parameter ``. -==== Set a collection of parameters from a Yaml configuration file +=== Set a collection of parameters from a Yaml configuration file [,verilog] ---- @@ -465,7 +472,7 @@ extern "C" void spike_set_params_from_file(const char *paramFilePath); Sets parameters of the current Spike instance according to the content of file named ``. -==== Get current value of a Spike CSR of a specific core +=== Get current value of a Spike CSR of a specific core [,verilog] ---- @@ -485,7 +492,7 @@ Input args: Return value: NONE (CSR value is passed in an in-out arg). -==== Set value of a Spike CSR for a specific core +=== Set value of a Spike CSR for a specific core [,verilog] ---- @@ -508,14 +515,14 @@ Return value: NONE. //=== C++ Programming Interface -=== Command-line interface +== Command-line interface Command-line options added to Spike serve a dual purpose: * run Spike in standalone mode using the same configurations as in tandem mode; * (development aid) test the effect of individual parameters without editing configuration files. -==== Load Spike parameters from a configuration file +=== Load Spike parameters from a configuration file [,sh] ---- @@ -526,7 +533,7 @@ Load the parameter tree from Yaml file named ``. The file is expected to contain a valid parameter tree. Parameters which are not recognized will be silently ignored. -==== Set a single Spike parameter +=== Set a single Spike parameter [,sh] ---- diff --git a/docs/04_cv32a65x/tristan/verification/tandem/tandem-modifications-for-trl5.adoc b/docs/04_cv32a65x/tristan/verification/tandem/tandem-modifications-for-trl5.adoc new file mode 100644 index 00000000000..6b29951778e --- /dev/null +++ b/docs/04_cv32a65x/tristan/verification/tandem/tandem-modifications-for-trl5.adoc @@ -0,0 +1,192 @@ += Case Study: Tandem Modifications for TRL5 Verification of CV32A60X +:toc: + +== Introduction + +The CV32A60X core was verified at TRL5 level through tandem co-simulation of the RTL implementation and a Spike reference model in a UVM environment. +Spike operation was primarily controlled by parameters supplied through a core-specific Yaml file. However, during the verification process it appeared that several implementation-dependent choices hardcoded in Spike were in conflict with the choices specified for the CV32A60X core for the corresponding features. +Addressing these differences required additional Spike modifications and the introduction of new parameters not present in the initial version of the tandem infrastructure. Similarly, Spike was not aware of custom ISA extensions such as the CV-X-IF verification instructions. + +The following sections discuss the modifications that were necessary and the way they are addressed in the CVA6 tandem verification infrastructure in order to support TRL5 verificatiom of the CV32A60X and CV32A65X cores. + +== Precise handling of interrupts + +The handling of interrupts in tandem simulation needs to address the fact tha in the RTL implementation, interrupt detection and processing are decoupled because of micro-architectural behavior properties: + +* the occurrence of non-masked interrupts is detected in the "instruction decode" stage of the instruction pipeline; +* the instructions already decoded and the instruction being decoded when the interrupt is detected are executed to completion. + +This is illustrated in xref:fig-tandem-interrupt-scenario[xrefstyle=short]: + +.Interrupt processing scenario in tandem environment +[#fig-tandem-interrupt-scenario] +image::figures/interrupt-tandem-scenario-svg.png[Tandem interrupt scenario,1024] + +where: + +* clock (`clk`) rising edges marked with an upward arrow indicate cycles in which instructions are committed; rising clock edges without an upward arrow correspond to additional RTL clock cycles required by microarchitectural constraints; +* `i1`, `i2`, `i3` are normal instruction flow instructions; the interrupt arrives while decoding instruction `i3`; +* `H1` and `H2` are the first two instructions of the interrupt handler; +* `uarch` stands for RTL cycles in which no commits occur (cf. rising clock edges without an upward arrow marker); +* `RM` stands for **Reference Model** and designates intervals in the RTL-driven tandem simulation when the reference model (Spike) simulation is active rather than the RTL one. + +In the scenario presented in the figure, the arrival of an external interrupt is represented by interrupt line `int #n` being raised by the UVM interrupt agent. +Since the corresponding interrupt enable bit `mie[n]` was already high (marker `e` on RTL `mie[n]` waveform), the raising of the `mip[n]` triggers the `INT#n` interrupt in the core (marker `r` on the RTL `mip[n]` waveform). +The interrupt is memorized in the cycle in which instruction `i1` is ready to be committed. The fact that the `mie[n]` interrupt enable bit corresponding to `int #n` is cleared after committing instruction `i1` has no impact on the already latched interrupt: its presence will be propagated through the instruction pipeline. +However, the corresponding handler will only be entered by the RTL implementation when all three instructions that have already been decoded (`i1`, `i2`, `i3`) will have completed. + +On the other hand, without special provisions the Reference Model (Spike) would observe the arrival of the interrupt when committing instruction `i1`, and would enter the interrupt handler before committing instruction `i2` which does not match the hardware behavior. + +A simple interrupt delaying mechanism consisting in propagating the value of the `mcause` CSR to Spike to indicate that an associated interrupt was taken is **not** reliable either: since the corresponding interrupt enable flag is cleared before the `mcause` notification, Spike will complain that a **disabled** interrupt was taken. + +In order to address this issue correctly, it is necessary to notify the Reference Model of the arrival of a taken interrupt upon committing the instruction that was being decoded when the interrupt arrived, and to provide the memorized `mip` and `mie` context matching the detection of the interrupt. +This mechanism was added to Spike in the CSR injection stage. The information about the *commit* of an instruction associated with an interrupt at decode time is obtained from the RVFI data structures, and the CSR conditions corresponding to the arrival of a non-masked interrupt are maintained inside the Spike tandem interface. + +== Support of instructions with multiple destination registers + +* describe all additions using a diagram to guide the reader: + +** RVFI additions + conventions +** instruction monitor +** new types +** communication channels +** Spike-side UVM interface +** UVM scoreboard and its conventions (no compare of x0, debugging support for reg comparison) + +== Implicit activation of ISA extensions by Spike + +The specification of CV32A60X ISA does not support the `Zifencei` extension. However, Spike activated this extension implicitly at all times. + +**Remedy: ** + +. Modify extension activation policy in the ISA handler class `isa_parser_t` to comply with the content of the ISA string wrt. the presence of extension `Zifencei`. This extension is now activated for a core only if extension name `zifencei` occurs in the ISA string of that core. +. Ensure that the Yaml parameter file of the CV32A60X target does not specify the `zifencei` extension in any ISA strings. + +== Addition of a new ISA extension + +Spike was not aware of the CV-X-IF verification instructions which are custom additions specific to OpenHW Foundation cores. + +**Remedy: ** + +. Add a new custom extension `xcvxif` to the set of supported ISA extensions in the ISA handler class `isa_parser_t` (files `riscv/isa_parser.h`, `disasm/isa_parser.cc`). +. Add suitable mask and match patterns for the CV-X-IF verification instructions to the list of known encodings in file `riscv/encoding.h`. +. Place the definitions of the instructions in a custom Spike extension `cvxif` which is automatically loaded when `xcvxif` ISA extension name is present in an ISA string. + +== Configuration of extensions using parameter files + +The CV-X-IF interface has two modes of operation for instructions with three input operands (so-called *R4-type* instructions): these instructions can use all three input operands or only the first two of them. The mode is controlled by a statically set configuration parameter. The CV32A60X core only uses the first two source registers. + +**Remedy: ** + +. Add a new core-specific parameter `cvxif_x_num_rs` to Spike. +. Let the `cvxif` custom extension store the value of the parameter as part of its internal state and use it to control the execution of R4-type CV-X-IF instructions. +. Pass the value of the parameter to the extension by means of the standard `reset()` method of the `extension_t` class called when resetting the `Processor` class object used to represent a core. +. Modify the Yaml parameter file of the CV32A60X simulation target to set the `cvxif_x_num_rs` parameter to value 2. + +== Behavior of accesses to unmapped memory addresses + +The CV32A60X core is intended for embedded applications and has no memory protection unit. The memory protection is delegated to platform level and the core treats read and fetch accesses to unmapped locations as returning zeroes, and silently ignores writes to unmapped locations. On the other hand Spike implicitly integrates a PMP unit and raises exceptions under these conditions. + +**Remedy: ** + +. Add a new core-specific parameter `allow_unmapped_mem_access` to Spike. +. Modify Spike low-level physical read, fetch and store routines in class `mmu_t` to change behaviour according to the value of the `allow_unmapped_mem_access` parameter. +. Modify the Yaml parameter file of the CV32A60X simulation target to set the `allow_unmapped_mem_access` parameter to `True`. + +== Parameter-only adjustments of Spike behaviour + +The remaining behaviour differences between Spike defaults and the CV32A60X specification could be addressed by already existing parameters: + +* CV32A60X has no writable PMP regions: set the number of writable PMP registers to zero + +[,yaml] +---- + pmpregions_writable: 0 +---- + +* The `misa` register in CV32A60X has the `X` bit cleared even when the `xcvxif` extension is enabled: override the value of bit 23 in `misa` as determined by Spike and replace it with value 0: + +[,yaml] +---- + misa_override_mask: 0x00800000 + misa_override_value: 0x00000000 +---- + + +* The `mtvec` register in CV32A60X is writable, but the `MODE` field of `mtvec` has always value 0 corresponding to *direct mode*: enable writing arbitrary values into bits 31:2 of `mtvec` register but force bits 1:0 to zero + +[,yaml] +---- + mtvec_write_mask: 0xFFFFFFFC + mtvec_override_mask: 0x00000003 + mtvec_override_value: 0x00000000 +---- + +== Appendix: The final Yaml parameter file used for CV32A60X TRL5 verification + +This is a verbatim copy of file config/gen_from_riscv_config/cv32a60x/spike/spike.yaml@b1f80bd7cff3a94e5191aad96dc3a22f87d0a517 (branch `cv32a60x`, tag `cv32a60x-v6.0.0`): + +[,yaml] +---- +spike_param_tree: + bootrom: true + bootrom_base: 65536 + bootrom_size: 4096 + dram: true + dram_base: 2147483648 + dram_size: 1073741824 + generic_core_config: false + max_steps: 200000 + max_steps_enabled: false + isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif + priv: M + core_configs: + - + isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif + extensions: cv32a60x + boot_addr: 2147483648 + marchid_override_mask: 0xFFFFFFFF + marchid_override_value: 0x3 + misa_write_mask: 0x0 + misa_override_mask: 0x00800000 + misa_override_value: 0x00000000 + pmp_granularity: 8 + pmpaddr0: 0 + pmpcfg0: 0 + pmpregions_max: 64 + pmpregions_writable: 0 + priv: M + status_fs_field_we: false + status_fs_field_we_enable: false + status_vs_field_we: false + status_vs_field_we_enable: false + mstatus_write_mask: 136 + mstatus_override_mask: 6144 + mie_write_mask: 0x00000880 + mie_override_mask: 0xfffff77f + mie_override_value: 0x00000000 + mip_write_mask: 0x00000000 + mip_override_mask: 0xfffff77f + mip_override_value: 0x00000000 + mtval_write_mask: 0 + tinfo_accessible: 0 + mscontext_accessible: 0 + mcontext_accessible: 0 + tdata1_accessible: 0 + tdata2_accessible: 0 + tdata3_accessible: 0 + tselect_accessible: 0 + mtvec_write_mask: 0xFFFFFFFC + mtvec_override_mask: 0x00000003 + mtvec_override_value: 0x00000000 + mhartid: 0 + mvendorid_override_mask : 0xFFFFFFFF + mvendorid_override_value: 1538 + csr_counters_injection: true + interrupts_injection: true + unified_traps: true + mcycleh_implemented: false + mhpmevent31_implemented: false + cvxif_x_num_rs: 2 + allow_unmapped_mem_access: true +---- diff --git a/docs/04_cv32a65x/tristan/verification/tandem/tandem-user-guide.adoc b/docs/04_cv32a65x/tristan/verification/tandem/tandem-user-guide.adoc new file mode 100644 index 00000000000..362cc81cfa6 --- /dev/null +++ b/docs/04_cv32a65x/tristan/verification/tandem/tandem-user-guide.adoc @@ -0,0 +1,197 @@ += Tandem-based Verification User Manual +:toc: + +== QuickStart Guide + +=== Build instructions + +The standard build procedure of Spike supplied with the CVA6 project (https://github.com/openhwgroup/cva6/) builds a Spike binary with all necessary modifications required for DPI interfacing to the RTL testbench. + +Building Spike with tandem extensions requires the availability of `CMake` in version 3.16 or higher. The `yaml-cpp` source package (https://github.com/jbeder/yaml-cpp) that is used to parse and manipulate Yaml configurations is a submodule of Spike and will be downloaded when performing a recursive clone or update of the CVA6 repository. + +If a rebuild is required in an existing setup, it is necessary to either select a different installation directory for Spike or to remove the current installation directory of Spike. It is also necessary to remove Spike build directories `verif/core-v-verif/vendor/riscv/riscv-isa-sim/build` (Spike proper) and `verif/core-v-verif/vendor/riscv/riscv-isa-sim/yaml-cpp/build` (`yaml-cpp` library). + +=== Understanding the Spike configuration file + +Spike configuration files represent a Spike parameter tree in the form of nested Yaml dictionaries under a common root node `spike_param_tree`: + +[,yaml] +---- + spike_param_tree: + bootrom_enable: true + bootrom_base: 0x10000 + bootrom_size: 0x1000 + dram_enable: true + dram_base: 0x80000000 + dram_size: 0x40000000 + core_configs: + - + isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs + priv: M + extensions: cv32a60x,cvxif + boot_addr: 0x80000000 + marchid_override_mask: 0xFFFFFFFF + marchid_override_value: 0x3 + misa_write_mask: 0x0 +---- + +The first-level entries define platform properties (`bootrom_*` and `dram_*`) and the default settings for all cores of the system (`core_configs`). + +The configuration fragment above instructs the reference model that: + +* the platform contains a boot ROM of size 4 KiB starting at address 0x10000 (0+64 KiB); +* the platform contains a DRAM memory of 1 GiB starting at the address 0x80000000 (0+2 GiB) +* all cores: +** implement an RV32IMC ISA with extensions `Zicsr`, `Zcb`, `Zba`, `Zbb`, `Zbc` and `Zbs`; +** support only the Machine privilege level; +** implement additional features modeled in Spike custom extensions `cv32a60x` (additional CSRs specific to `CV32A6*X` family of cores) and `cvxif` (the CV-X-IF interface); +** boot from address `0x80000000` (the start address of the DRAM memory); +** force the reset value of register `marchid` to value `0x3` (corresponding to the CVA6 architecture); +** discard writes into `misa` CSR register by marking all its bits as non-mutable. + +=== Running simulations in tandem mode + +Currently, tandem simulations are supported out-of-the-box only for CVA6 target `cv32a65x` using RTL simulator configurations `vcs-uvm` (recommended), `vcs-testharness`, `questa-uvm` and `questa-testharness`. Tandem simulations of target `cv32a65x` with Verilator using the `veri-testharness` configuration require Verilator v5.016 or higher. + +Tandem verification is enabled by setting environment variable `SPIKE_TANDEM` to a non-empty value prior to invoking any of the test scripts located in the `verif/regress` directory of the CVA6 source tree. + +**Example:** +[,sh] +---- +export SPIKE_TANDEM=1 ; bash verif/regress/dv-csr-embedded-tests.sh +---- + +The output of tandem simulation is sent to the log file of the RTL simulator, by default `verif/sim/out_/_sim/..log.iss`. + +A machine-processable Yaml report file summarizing the mismatches detected during the simulation is stored in a separate report file, by default `verif/sim/out_/_sim/..log.yaml`. It contains the configuration of the simulated design, the number of mismatches that were found (if any) and a list of entries describing the successive mismatches. + +== How to analyze tandem verification results + +To simplify failure analysis, the RVFI state comparator reports mismatches between commit states of the reference model and the RTL model at all verbosity levels. However, it produces no output if the commit states are identical and the verbosity level is `UVM_LOW`. By controlling output verbosity, the simulation log can be reduced to the sole list of state discrepancies, or it can contain a complete log of commits and exceptions to provide additional context at failure locations. + +A scoreboard discrepancy is represented by a line describing the nature of the error, followed by two lines that provide a summary view of the RVFI state of the reference model and the RTL core. + +**Example:** +[,text] +---- +CSR 304 Mismatch [REF]: 0x0 [CORE]: 0x8 +UVM_INFO @ 45992.000 ns : uvmc_rvfi_scoreboard_utils.sv(206) reporter [spike_tandem] 45992.000 ns | RVFI | 0 | 0 | 800036ac | 30419073 | M | x3 | 00000008 | x0 | 0000000000000000 | csrrw zero, mie, gp +UVM_ERROR @ 45992.000 ns : uvmc_rvfi_scoreboard_utils.sv(211) reporter [spike_tandem] 45992.000 ns | RVFI | 0 | 0 | 800036ac | 30419073 | M | x3 | 00000008 | x0 | 0000000000000000 | csrrw zero, mie, gp <- CORE +---- + +The first line indicates that for current instruction commit the content of the CSR with hexadecimal address `304`, i.e., `mie` ("Machine Interrupt Enable") differs between the reference model (value `0x0`) and the RTL core model (value `0x8`). The next two lines provide details about the current instruction in both models: + +* the current time stamp: `45992.000 ns`, +* the value of PC: `0x800036ac`, +* the encoding of the instruction: hex `30419073`, +* the current privilege mode: `M` (Machine), +* the values of general-purpose register operands of the instruction: `x3` (`gp` in RISC-V ABI) equals `0x00000008`, `x0` equals `0x00000000`. + +Since the values stored into the `mie` CSR differ whereas the instruction executed is the same including the values of its input operands, the discrepancy can only come from the write behavior of the `mie` CSR. In this specific case, bit 3 of the `mie` register is specified as "read-only zero" in the reference model, yet the RTL implementation accepts writes into this specific bit of `mie`. + +The following is the corresponding fragment from the Yaml report, including the configuration and status summary of the simulation run: + +[,yaml] +---- +csrs_match_count: 461 +exit_cause: MISMATCH +exit_code: 0 +instr_count: 3280 +isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei +mismatch_description: 'CSR 304 Mismatch [REF]: 0x880 [CORE]: 0x888 ' +mismatches: +- 0: null + core: + insn: 0000000030419073 + insn_disasm: csrrw zero, mie, gp + mode: 3 + pc_rdata: 00000000800036ac + pc_wdata: 0 + rd1_addr: 0 + rd1_rdata: 0 + rs1_addr: 3 + rs1_rdata: 0000000000000008 + trap: 0 + reference_model: + insn: 0000000030419073 + insn_disasm: csrrw zero, mie, gp + mode: 3 + pc_rdata: 00000000800036ac + pc_wdata: 0 + rd1_addr: 0 + rd1_rdata: 0 + rs1_addr: 3 + rs1_rdata: 0000000000000008 + trap: 0 +[...] +mismatches_count: 5 +simulator: vcs-uvm +target: cv32a65x +test: csr_test +testlist: csr_embedded +---- + +== Example uses of Yaml reference model parameters + +=== Enable (make "accessible") or disable (make "inaccessible") a CSR + +A Boolean parameter consisting of CSR name and suffix `_accessible`, placed in generic or per-core configuration, indicates whether the given register should be accessible or not. + +**Example**: + +[,yaml] +---- +spike_param_tree: + ... + core_configs: + - + ... + tinfo_accessible: False +---- + +makes the `tinfo` CSR inaccessible in the reference model for all cores, meaning that any attempt to access (read or write) the `tinfo` register when executing an instruction in the reference model will trigger an illegal instruction exception. + +=== Force specific bits in a CSR to a constant value + +The reference model parameters provide two levels of control over the content of CSRs: + +* override the reset value of selected bits of any CSR; +* define which bits of a CSR cannot be modified. + +Assuming that bit 5 of a certain CSR `` should always be set irrespective of the default setting in the reference model, it is necessary to indicate that: + +* the reset value of that bit should be 1; +* writes to that bit should be ignored. + +The parameters needed to express this property are: + +* `_override_mask` which defines which bits of `` should be forced to a specific value at reset, +* `_override_value` which indicates the reset value of the forced bits of ``, +* `_write_mask` which indicates which bits of `` are writable (mask bit is set) and which are not (mask bit is cleared). + +Assuming that the XLEN is 32 and only bit 5 of `` should be fixed, the Yaml settings to use are: + +[,yaml] +---- +spike_param_tree: + ... + core_configs: + - + ... + _override_mask: 0x00000020 + _override_value: 0x00000020 + _write_mask: 0xffffffdf +---- + +== Integration with the RISC-V Open Source ecosystem + +* The entire tandem verification infrastructure is available as Open Source under SHL 2.0+ (an Apache-type license) in OpenHW Group repositories `cva6` (https://github.com/openhwgroup/cva6/) and `core-v-verif` (https://github.com/openhwgroup/cva6/). + +* The OpenHW Group tandem verification infrastructure relies on Spike (https://github.com/riscv-software-src/riscv-isa-sim/) as reference model. ++ +The tandem verification approach is a general template and is not bound to a single ISS or RTL simulator. However, it requires that the ISS provides a basic platform capable of running software matching the capabilities of the RTL testbench, including a model of memory and buses. +Because of this constraint the current tandem framework relies on Spike which is fully Open Source and provides all necessary components. + +* Verilator-based tandem verification ++ +Starting with version 5.016, Verilator supports tandem simulations. Earlier versions did not provide sufficient support for structured types in the DPI interface. diff --git a/docs/04_cv32a65x/tristan/verification/tandem/uvm-tandem-refman.adoc b/docs/04_cv32a65x/tristan/verification/tandem/uvm-tandem-refman.adoc new file mode 100644 index 00000000000..9ddf0265e51 --- /dev/null +++ b/docs/04_cv32a65x/tristan/verification/tandem/uvm-tandem-refman.adoc @@ -0,0 +1,8 @@ += [PLACEHOLDER] UVM Tandem Support: the Reference Manual +:toc: + +== Architectue of UVM Tandem Support + +== UVM Programmer's View + +== Adapting tandem support to new targets diff --git a/docs/04_cv32a65x/tristan/verif-spec/verification_specifications.adoc b/docs/04_cv32a65x/tristan/verification/verification_environment.adoc similarity index 76% rename from docs/04_cv32a65x/tristan/verif-spec/verification_specifications.adoc rename to docs/04_cv32a65x/tristan/verification/verification_environment.adoc index b7b59b27e14..c5bafee2004 100644 --- a/docs/04_cv32a65x/tristan/verif-spec/verification_specifications.adoc +++ b/docs/04_cv32a65x/tristan/verification/verification_environment.adoc @@ -1,93 +1,10 @@ -[.text-center] -*TRISTAN* += CV32A6 Verification Environment: Structure and Organization +:toc: -[.text-center] -*Together for RISc-V Technology and ApplicatioNs* - -[.text-center] -image:./media/image1.png[./media/image1,width=273,height=273] - -[.text-center] -*Verification Specifications* - -*Project Website* www.tristan-project.eu - -*JU Grant Agreement Number* 101095947 - -[width="100%",cols="40%,60%",options="header",] - -|=== - -|image:./media/image2.png[./media/image2,width=172,height=81] |TRISTAN - -has received funding from the Key Digital Technologies Joint Undertaking -(KDT JU) under grant agreement nr. 101095947. The KDT JU receives support from the European Union’s Horizon Europe’s research and innovation programme and Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Israel, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey - -|=== - -== Table of Contents - -. link:#_Introduction[Introduction] - -.. General Information - -.. Acronyms and Definitions - -. link:#_Verification_Strategy[Verification Strategy] - -.. Methodology - -.. Database Structure - -.. Tools - -.. Planned releases - -. link:#_Testbench[Testbench] - -.. Testbench Architecture - -.. Testbench Block-Diagram - -.. Testbench Components - -... Agents - -... UVCs - -... Checkers - -... Assertions - -... UVM Scoreboard - -... Coverage Model - -... Write or Generate Tests - -. link:#_Verification_Plan[Verification Plan] - -.. - -.. - -. link:#_Verification_Reports[Verification Reports] - -.. Regression Results - -.. Functional coverage - -.. Code coverage - -.. SpyGlass integration - -.. RTL issues detected - -[#_Introduction] == Introduction === General Information -This document describes the CVA6 verification strategy and implementation. +This document describes the structure and organization of the CV32A6 verification environment which was developed with partial support of the TRISTAN project. === Acronyms and Definitions @@ -105,10 +22,10 @@ This document describes the CVA6 verification strategy and implementation. |SV | SystemVerilog |VIF | Virtual InterFace |AXI | Advanced eXtensible Interface +|ISS | Instruction Set Simulator +|RM | Reference Model |=== -[#_Verification_Strategy] -== Verification Strategy === Methodology This project is not a single verification environment that can support any-and-all CORE-V cores. Rather, it supports the verification of multiple cores by enabling the rapid creation of core-specific verification environments. There is no attempt to define a one-size-fits-all environment as these inevitably lead to either bloated code, needless complexity, or both. Instead, the idea is to create a toolkit allowing the rapid development of core-specific environments using a set of high-level reusable components and a standard UVM framework. @@ -119,7 +36,7 @@ The core-v-verif project exploits this idea to maximize re-use across multiple c Depending on the details of the top-level interfaces of individual cores, the lowest layers of this environment may not be re-usable at all. -=== Database Structure +=== UVM Database Structure The verification environment, built from the resources provided by core-v-verif project can be conceptually divided into four levels: Testbench Layer, Translation Layer, Abstraction Layer and Test Layer. Each of these will be discussed in turn. @@ -404,7 +321,7 @@ This class has the expected functionality following UVM standards. It receives t *_[.underline]#Axi Agent#_* -This agent is an AXI4 (Advanced eXtensible Interface) SV UVM1.1 SLAVE. Aligned to AXI4 AMBA spec https://developer.arm.com/documentation/ihi0022/hc +This agent is an AXI4 (Advanced eXtensible Interface) SV UVM1.1 SLAVE. Aligned to AXI4 spec https://developer.arm.com/documentation/ihi0022/hc [.underline]#Agent Architecture:# @@ -479,7 +396,7 @@ This collaboration is also important for the open-source community, as it enable It is described in a previous section of this document. ===== Agent developed by CEA -The AXI superset agent is a highly configurable AXI agent. It is based on the AMBA AXI and ACE Protocol Specification from ARM(https://developer.arm.com/documentation/ihi0022/g/). It provides the functionality of AXI master and AXI slave. In the master mode, it provides the sequences/APIs to drive READ/WRITE/ATOP transactions. In the slave mode, the agent uses an external memory to perform response. +The AXI superset agent is a highly configurable AXI agent. It is based on the AXI and ACE Protocol Specification from ARM(https://developer.arm.com/documentation/ihi0022/g/). It provides the functionality of AXI master and AXI slave. In the master mode, it provides the sequences/APIs to drive READ/WRITE/ATOP transactions. In the slave mode, the agent uses an external memory to perform response. ===== Enhancement The idea was to merge the master part of the CEA agent with the Thales slave agent and create one agent supporting both slave and master functionality, incorporating all AXI4 features and the potential to support additional functionality from AXI5. The agent must also support external memory in slave mode. @@ -677,131 +594,7 @@ Our verification environment has functional coverage also, define with several c * *_AXI_*: provide functional coverage relate to AXI protocol. -To know all the functional coverage related to the CVA6 only is define in the environment, like CVXIF custom instruction, and soma AXI features. - -==== Write or Generate Tests -Testing is a crucial part of the verification process. Different types of tests are employed: - -* Generate assembly tests using CVA6-DV: Uses the RISCV-DV framework to generate assembly-level test programs for the CVA6 core. RISCV-DV is a flexible and extensible tool used for generating RISC-V architecture assembly programs to stress-test the core. The extensions to RISCV-DV are available at (https://github.com/openhwgroup/cva6/tree/master/verif/env/corev-dv). -* Write directed assembly tests: These are manually written test cases designed to target specific behaviors or edge cases that are not covered by automated test generation. - - - -[#_Verification_Plan] -== Verification Plan - -The DVPlans are available at (https://github.com/openhwgroup/cva6/tree/master/verif/docs/VerifPlans). - -=== - -* ISA DVPlan: Focuses on verifying the Instruction Set Architecture (ISA) to ensure the core executes instructions correctly. -* CV-XIF DVPlan: This covers the verification of the Core-View External Interface (CV-XIF), likely to be an interface protocol used for communication between the core and external components. It mentions that this plan is for the first version and will require updates as the protocol evolves. -* AXI DVPlan: Deals with the verification of the AXI (Advanced eXtensible Interface). -* Traps DVPlan: Verifies the behavior of the core when exceptions, interrupts, or traps occur. -* CSRs DVPlan: Focuses on verifying the control and status registers (CSRs), which are key for managing the operation of the core. - -=== - -* Frontend DVPlan: Verifies the frontend part of the core, which involves instruction fetching, next pc generation, pre-decoding instruction and RET/Branch prediction. - -[#_Verification_Reports] -== Verification Reports - -=== Regression Results - -* 2000+ tests running on the server: specifically, 2112 tests are executed as part of the regression process, which runs the entire suite of tests repeatedly to ensure that changes or updates do not introduce new bugs. All tests passed, which indicates a stable design at this stage. - -[cols="1,1,1,1,1"] -|=== -| -|ISA -|Traps -|CSRs -|Data hazard - -|Generated tests -|900 -|449 -|450 -|300 - -|Directed tests -|6 -|2 -|5 -|0 -|=== - -* Scripts handling failed tests: A script is used to automatically remove failing tests from the coverage database. This ensures that the coverage report is based solely on tests that pass, meaning the coverage metrics are representative of correctly functioning parts of the design. - - -=== Functional coverage - -* Create HVP in the CVA6 env to track functional coverage: HVP refers to "Hierarchical Verification Plan," which helps monitor and track the functional coverage of the tests. The goal is to ensure that all functional aspects of the core are exercised during the verification. Functional coverage measures how much of the design’s intended functionality has been exercised. -The functional coverage is split in several parts: - - * Programmer view level: it corresponds to CVA6 from the perspective of the programmer (architectural view): ISA, CSRs, and traps. - * Design level: it corresponds to the different parts of the CVA6 pipeline (micro-architectural view). - -image:./media/hvp.png[./media/hvp,width=624,height=190] - -* 98.09% functional coverage for programmer view level: Achieving 98.09% coverage is an excellent result, indicating that most of the ISA (Instruction Set Architecture), CSRs (Control and Status Registers), and traps (interrupt and exception handling) have been tested thoroughly. - -image:./media/funccovresults.png[./media/funccovresults,width=426,height=93] - -* Justificative report for coverage holes: This refers to generating a report explaining any missing coverage (the 1.91% not covered). This might happen due to untested corner cases or unsupported configurations. - -* Regarding the design level, the 6.65% coverage result is poor as only the frontend stage of the CVA6 pipeline is currently addressed. - - -=== Code coverage - -* The coverage of line and condition was low, primarily due to unsupported features in the CV32A65X configuration. -* The solution was to parameterize the RTL to make it configurable, remove dead code from the coverage report, and eliminate dead gates from the netlist. -* To achieve this, we used the VCS switch “-cm_seqnoconst -diag noconst” to automatically exclude constant variables and inaccessible code from the coverage analysis. -* An example of the implementation is provided below: - -image:./media/rtlparam.png[./media/rtlparam,width=624,height=161] - -* The gain of parameterization for only MMU and FPU: - -image:./media/rtlparamgates.png[./media/rtlparamgates,width=975,height=92] - -* We encountered the same problem with toggle coverage, and the score was very low compared to that of line and condition coverage. -* We can’t use the same options applied for line and condition coverage because we can’t parameterize the interface signals. Additionally, the VCS simulator only tracks constant signals if they are directly assigned to a constant value. -* For example, if the aw_user signal from the AXI interface is directly assigned to '0', the simulator will exclude the signal from toggle coverage. However, if aw_user is assigned to another signal, even if that signal is constant, the simulator will take no action. -* To address this, the solution is to generate an exclusion file based on the results of a Python script that detects unsupported signals according to your configuration. (More details about the script) -* Low toggle coverage initially (50%): Toggle coverage refers to how often signals switch between states during simulation. Initially, only 50% of the signals in the design were toggling, which suggests that a significant portion of the design was not being exercised. - -image:./media/toggleresults.png[./media/toggleresults,width=241,height=70] - -* Issue with unsupported signals for configuration: The problem was that some signals were unsupported in the current design configuration. A Python script was used to identify these unsupported signals, and an exclusion file was generated to exclude these signals from code coverage, ensuring accurate reporting. - -==== What is missing in code coverage - -* CV-XIF tests: An update of the Core-View External Interface (CV-X-IF) protocol (version 1.0) is available, and the verification tests hadn’t been updated to reflect these changes. This gap in testing impacts code coverage, as some parts of the design using this protocol may remain untested. -The verification work of CV-X-IF v1.0 will be done in the ISOLDE project. -* Dead code: There is still some "dead code" in the design, code that is never executed. This could indicate unnecessary or outdated features that need to be either removed or refactored. - -=== SpyGlass integration - -SpyGlass is a static analysis tool used to find potential issues in RTL code, such as linting errors, coding style violations, and design rule checks. The verification effort involved: - -* Adding SpyGlass support from scratch: This included setting up scripts, Makefiles, and other infrastructure to integrate SpyGlass into the CVA6 verification environment. -* Integrating SpyGlass into regression tests: SpyGlass was included in the regression process so that any RTL changes would automatically be checked for issues. -* Reporting results in a dashboard: The results of the SpyGlass runs were compared with previous runs, and reports were generated to track progress, likely in a dashboard for easy visualization of errors and trends. - -=== RTL issues detected - -RTL (Register Transfer Level) bugs have been detected in various areas of the CVA6 design thanks to verification: - -* ISA bugs: Bugs in the instruction set implementation. -* Traps: Bugs in how the core handles exceptions and interrupts. -* CSRs: Bugs related to control and status registers. -* CV-X-IF: Bugs related to the CV-X-IF protocol. -* AXI: Bugs related to the AXI protocol. - -All issues are described in CVA6 GitHub repository (https://github.com/openhwgroup/cva6/issues?q=label%3AType%3ABug). +To know all the functional coverage related to the CVA6 only is define in the environment, like CVXIF custom instruction, and some AXI features. http://www.tristan-project.eu[_www.tristan-project.eu_] diff --git a/docs/04_cv32a65x/tristan/verification/verification_process.adoc b/docs/04_cv32a65x/tristan/verification/verification_process.adoc new file mode 100644 index 00000000000..96fe10024f6 --- /dev/null +++ b/docs/04_cv32a65x/tristan/verification/verification_process.adoc @@ -0,0 +1,163 @@ += CV32A6 Verification Process: Planning, Execution and Outcomes +:toc: + +== Introduction +=== General Information + +This document describes the CV32A6 verification process, focussing on the creation of verification plans, the use of the environment to verify the CV32A60X and CV32A65X designs to TRL5, and reports on the outcomes of the process. This process was defined and deployed with partial support from the TRISTAN project. + +=== Acronyms and Definitions + +[width="100%",cols="24%,76%",options="header",] + +|=== +|Acronym |Description +|TB |Testbench +|UVC |Universal verification component +|IF |SystemVerilog Interface +|CVXIF |CORE-V eXtension Interface +|UVM | Universal Verification Methodology +|RVFI | RISC-V Formal Interface +|DUT | Device Under Test +|SV | SystemVerilog +|VIF | Virtual InterFace +|AXI | Advanced eXtensible Interface +|ISS | Instruction Set Simulator +|RM | Reference Model +|=== + +==== Write or Generate Tests +Testing is a crucial part of the verification process. Different types of tests are employed: + +* Generate assembly tests using CVA6-DV: Uses the RISCV-DV framework to generate assembly-level test programs for the CVA6 core. RISCV-DV is a flexible and extensible tool used for generating RISC-V architecture assembly programs to stress-test the core. The extensions to RISCV-DV are available at (https://github.com/openhwgroup/cva6/tree/master/verif/env/corev-dv). +* Write directed assembly tests: These are manually written test cases designed to target specific behaviors or edge cases that are not covered by automated test generation. + + + +[#_Verification_Plan] +== Verification Plan + +The DVPlans are available at (https://github.com/openhwgroup/cva6/tree/master/verif/docs/VerifPlans). + +=== + +* ISA DVPlan: Focuses on verifying the Instruction Set Architecture (ISA) to ensure the core executes instructions correctly. +* CV-XIF DVPlan: This covers the verification of the Core-View External Interface (CV-XIF), likely to be an interface protocol used for communication between the core and external components. It mentions that this plan is for the first version and will require updates as the protocol evolves. +* AXI DVPlan: Deals with the verification of the AXI (Advanced eXtensible Interface). +* Traps DVPlan: Verifies the behavior of the core when exceptions, interrupts, or traps occur. +* CSRs DVPlan: Focuses on verifying the control and status registers (CSRs), which are key for managing the operation of the core. + +=== + +* Frontend DVPlan: Verifies the frontend part of the core, which involves instruction fetching, next pc generation, pre-decoding instruction and RET/Branch prediction. + +[#_Verification_Reports] +== Verification Reports + +=== Regression Results + +* 2000+ tests running on the server: specifically, 2112 tests are executed as part of the regression process, which runs the entire suite of tests repeatedly to ensure that changes or updates do not introduce new bugs. All tests passed, which indicates a stable design at this stage. + +[cols="1,1,1,1,1"] +|=== +| +|ISA +|Traps +|CSRs +|Data hazard + +|Generated tests +|900 +|449 +|450 +|300 + +|Directed tests +|6 +|2 +|5 +|0 +|=== + +* Scripts handling failed tests: A script is used to automatically remove failing tests from the coverage database. This ensures that the coverage report is based solely on tests that pass, meaning the coverage metrics are representative of correctly functioning parts of the design. + + +=== Functional coverage + +* Create HVP in the CVA6 env to track functional coverage: HVP refers to "Hierarchical Verification Plan," which helps monitor and track the functional coverage of the tests. The goal is to ensure that all functional aspects of the core are exercised during the verification. Functional coverage measures how much of the design’s intended functionality has been exercised. +The functional coverage is split in several parts: + + * Programmer view level: it corresponds to CVA6 from the perspective of the programmer (architectural view): ISA, CSRs, and traps. + * Design level: it corresponds to the different parts of the CVA6 pipeline (micro-architectural view). + +image:./media/hvp.png[./media/hvp,width=624,height=190] + +* 98.09% functional coverage for programmer view level: Achieving 98.09% coverage is an excellent result, indicating that most of the ISA (Instruction Set Architecture), CSRs (Control and Status Registers), and traps (interrupt and exception handling) have been tested thoroughly. + +image:./media/funccovresults.png[./media/funccovresults,width=426,height=93] + +* Justificative report for coverage holes: This refers to generating a report explaining any missing coverage (the 1.91% not covered). This might happen due to untested corner cases or unsupported configurations. + +* Regarding the design level, the 6.65% coverage result is poor as only the frontend stage of the CVA6 pipeline is currently addressed. + + +=== Code coverage + +* The coverage of line and condition was low, primarily due to unsupported features in the CV32A65X configuration. +* The solution was to parameterize the RTL to make it configurable, remove dead code from the coverage report, and eliminate dead gates from the netlist. +* To achieve this, we used the VCS switch “-cm_seqnoconst -diag noconst” to automatically exclude constant variables and inaccessible code from the coverage analysis. +* An example of the implementation is provided below: + +image:./media/rtlparam.png[./media/rtlparam,width=624,height=161] + +* The gain of parameterization for only MMU and FPU: + +image:./media/rtlparamgates.png[./media/rtlparamgates,width=975,height=92] + +* We encountered the same problem with toggle coverage, and the score was very low compared to that of line and condition coverage. +* We can’t use the same options applied for line and condition coverage because we can’t parameterize the interface signals. Additionally, the VCS simulator only tracks constant signals if they are directly assigned to a constant value. +* For example, if the aw_user signal from the AXI interface is directly assigned to '0', the simulator will exclude the signal from toggle coverage. However, if aw_user is assigned to another signal, even if that signal is constant, the simulator will take no action. +* To address this, the solution is to generate an exclusion file based on the results of a Python script that detects unsupported signals according to your configuration. (More details about the script) +* Low toggle coverage initially (50%): Toggle coverage refers to how often signals switch between states during simulation. Initially, only 50% of the signals in the design were toggling, which suggests that a significant portion of the design was not being exercised. + +image:./media/toggleresults.png[./media/toggleresults,width=241,height=70] + +* Issue with unsupported signals for configuration: The problem was that some signals were unsupported in the current design configuration. A Python script was used to identify these unsupported signals, and an exclusion file was generated to exclude these signals from code coverage, ensuring accurate reporting. + +==== What is missing in code coverage + +* CV-XIF tests: An update of the Core-View External Interface (CV-X-IF) protocol (version 1.0) is available, and the verification tests hadn’t been updated to reflect these changes. This gap in testing impacts code coverage, as some parts of the design using this protocol may remain untested. +The verification work of CV-X-IF v1.0 will be done in the ISOLDE project. +* Dead code: There is still some "dead code" in the design, code that is never executed. This could indicate unnecessary or outdated features that need to be either removed or refactored. + +=== SpyGlass integration + +SpyGlass is a static analysis tool used to find potential issues in RTL code, such as linting errors, coding style violations, and design rule checks. The verification effort involved: + +* Adding SpyGlass support from scratch: This included setting up scripts, Makefiles, and other infrastructure to integrate SpyGlass into the CVA6 verification environment. +* Integrating SpyGlass into regression tests: SpyGlass was included in the regression process so that any RTL changes would automatically be checked for issues. +* Reporting results in a dashboard: The results of the SpyGlass runs were compared with previous runs, and reports were generated to track progress, likely in a dashboard for easy visualization of errors and trends. + +=== RTL issues detected + +RTL (Register Transfer Level) bugs have been detected in various areas of the CVA6 design thanks to verification: + +* ISA bugs: Bugs in the instruction set implementation. +* Traps: Bugs in how the core handles exceptions and interrupts. +* CSRs: Bugs related to control and status registers. +* CV-X-IF: Bugs related to the CV-X-IF protocol. +* AXI: Bugs related to the AXI protocol. + +All issues are described in CVA6 GitHub repository (https://github.com/openhwgroup/cva6/issues?q=label%3AType%3ABug). + +http://www.tristan-project.eu[_www.tristan-project.eu_] + +_info@tristan-project.eu_ + + +[width="100%",cols="28%,72%",options="header",] + +|=== + +|image:./media/image7.png[Graphical user interface, application Description automatically generated,width=173,height=80] |_TRISTAN has received funding from the Key Digital Technologies Joint Undertaking (KDT JU) under grant agreement nr. 101095947. The KDT JU receives support from the European Union’s Horizon Europe’s research and innovation programme and Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Israel, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia, Turkey. +|=== diff --git a/docs/05_cva6_apu/cva6_testharness.md b/docs/05_cva6_apu/cva6_testharness.md index 958838df029..338d6add74f 100644 --- a/docs/05_cva6_apu/cva6_testharness.md +++ b/docs/05_cva6_apu/cva6_testharness.md @@ -128,7 +128,7 @@ Only the signals related to the test_harness have been shown in the above diagra ## PLIC -PLIC is a slave in this SoC. The hiearchy through which the request is propagated to the plic_top module is as follows: +PLIC is a slave in this SoC. The hierarchy through which the request is propagated to the plic_top module is as follows: ![plic_hierarchy](_static/plic.png ) diff --git a/docs/07_cv32a60x/index.rst b/docs/07_cv32a60x/index.rst new file mode 100644 index 00000000000..0d0669c016c --- /dev/null +++ b/docs/07_cv32a60x/index.rst @@ -0,0 +1,17 @@ +CV32A60X documentation +====================== + +.. toctree:: + :maxdepth: 1 + +.. + riscv/unpriv.rst + riscv/priv.rst + +Below are links to RISC-V ISA documents tailored for the CV32A60X and to CV32A60X-specific design documentation. +Only those CSRs and Instructions that are supported by the CV32A60X are documented here. + +| `Unprivileged RISC-V ISA `_ +| `Privileged RISC-V ISA `_ +| `Design Documentation for CV32A60X `_ + diff --git a/docs/07_cv32a60x/riscv/Makefile b/docs/07_cv32a60x/riscv/Makefile new file mode 100644 index 00000000000..85540807ba4 --- /dev/null +++ b/docs/07_cv32a60x/riscv/Makefile @@ -0,0 +1,10 @@ +# Copyright 2025 Thales DIS France SAS +# Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: André Sintzoff - Thales DIS + +CONFIG := cv32a60x +include ../../riscv-isa/build.mk diff --git a/docs/07_cv32a60x/riscv/priv.rst b/docs/07_cv32a60x/riscv/priv.rst new file mode 100644 index 00000000000..b6e0a8d8cd1 --- /dev/null +++ b/docs/07_cv32a60x/riscv/priv.rst @@ -0,0 +1,14 @@ +.. + Copyright (c) 2025 Thales DIS France SAS + Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: André Sintzoff - Thales DIS + +Privileged RISC-V ISA +===================== + +.. raw:: html + :file: priv-isa-cv32a60x.html diff --git a/docs/07_cv32a60x/riscv/unpriv.rst b/docs/07_cv32a60x/riscv/unpriv.rst new file mode 100644 index 00000000000..ed4ce544780 --- /dev/null +++ b/docs/07_cv32a60x/riscv/unpriv.rst @@ -0,0 +1,14 @@ +.. + Copyright (c) 2025 Thales DIS France SAS + Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: André Sintzoff - Thales DIS + +Unprivileged RISC-V ISA +======================= + +.. raw:: html + :file: unpriv-isa-cv32a60x.html diff --git a/docs/Makefile b/docs/Makefile index 0e7527e7055..567c13ceb64 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -6,6 +6,8 @@ prepare: make -C 06_cv64a6_mmu/riscv priv-html unpriv-html + make -C 07_cv32a60x/riscv priv-html unpriv-html + sphinx: sphinx-build . _build diff --git a/docs/common/config_define.adoc b/docs/common/config_define.adoc index 3d7952b36db..6003998f7f2 100644 --- a/docs/common/config_define.adoc +++ b/docs/common/config_define.adoc @@ -1,12 +1,21 @@ +ifeval::["{ohg-config}"=="CV32A60X"] +:archi-CVA6: +:archi-CV32A60X: +// specify that it is a custom architecture +:archi-not-default: +endif::[] + ifeval::["{ohg-config}"=="CV32A65X"] :archi-CVA6: +:archi-CV32A65X: // specify that it is a custom architecture :archi-not-default: endif::[] ifeval::["{ohg-config}"=="CV64A6_MMU"] :archi-CVA6: +:archi-CV64A6_MMU: // specify that it is a custom architecture :archi-not-default: endif::[] diff --git a/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md b/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md index 87fd36c732e..8b1f08755b5 100644 --- a/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md +++ b/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md @@ -171,7 +171,7 @@ The ``sip`` register contains information on pending interrupts. | 4 | UTIP | | read-write,WARL | A user\-level timer interrupt is pending if the UTIP bit in the sip register is set\.``Legal Values:``0\.| | 3:2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 1 | SSIP | Supervisor-level software interrupt pending | read-only,WARL | SSIP is the interrupt\-pending bit for supervisor\-level software interrupts\.| -| 0 | USIP | | read-write,WARL | A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit\.``Legal Values:``0\.| +| 0 | USIP | | read-write,WARL | A user\-level software interrupt is triggered on the current hart by writing 1 to its user software interrupt\-pending \(USIP\) bit\.``Legal Values:``0\.| ## Supervisor Address Translation and Protection Register ### *AddressOffset*: 'h180 @@ -259,7 +259,7 @@ This register contains machine interrupt enable bits. | 3 | MSIE | M-mode software interrupt enable | read-write | Enables machine mode software interrupts\.| | 2 | Reserved_2 | Reserved | read-write,WARL | Reserved\.``Legal Values:``0\.| | 1 | SSIE | S-mode software interrupt enable | read-write,WARL | Enables supervisor mode software interrupts\.| -| 0 | USIE | | read-write,WARL | enable U\-mode software interrrupts\.``Legal Values:``0\.| +| 0 | USIE | | read-write,WARL | enable U\-mode software interrupts\.``Legal Values:``0\.| ## Machine Trap Vector Register ### *AddressOffset*: 'h305 @@ -426,7 +426,7 @@ Address register for Physical Memory Protection. | --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- | | 31:0 | address | Address | read-write,WARL | Address register for Physical Memory Protection\.| -## Instuction Cache Register +## Instruction Cache Register ### *AddressOffset*: 'h7C0 ### *Description*: Custom Register to enable/disable for Icache [bit 0] @@ -487,13 +487,13 @@ Shows trigger information. ## Debug Control and Status Register ### *AddressOffset*: 'h7B0 ### *Description*: -Debug ontrol and status register. +Debug control and status register. | BIT | NAME | displayName | RIGHT | Description | | --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- | | 31:28 | xdebugver | Debug version | read-only | Shows the version of the debug support\. // ``Enumerated Values``( "no_ext_debug" :0 ) ( "ext_debug_spec" :4 ) ( "ext_debug_no_spec" :15 ) | -| 15 | ebreakm | Environment breakpoint m-mode | read-write | Shows the behvior of the ``ebreak`` instruction in machine mode\. // ``Enumerated Values``( "break_as_spec" :0 ) ( "break_to_debug" :1 ) | -| 13 | ebreaks | Environment breakpoint s-mode | read-write | Shows the behvior of the ``ebreak`` instruction in supervisor mode\. // ``Enumerated Values``( "break_as_spec" :0 ) ( "break_to_debug" :1 ) | -| 12 | ebreaku | Environment breakpoint u-mode | read-write | Shows the behvior of the ``ebreak`` instruction in user mode\. // ``Enumerated Values``( "break_as_spec" :0 ) ( "break_to_debug" :1 ) | +| 15 | ebreakm | Environment breakpoint m-mode | read-write | Shows the behavior of the ``ebreak`` instruction in machine mode\. // ``Enumerated Values``( "break_as_spec" :0 ) ( "break_to_debug" :1 ) | +| 13 | ebreaks | Environment breakpoint s-mode | read-write | Shows the behavior of the ``ebreak`` instruction in supervisor mode\. // ``Enumerated Values``( "break_as_spec" :0 ) ( "break_to_debug" :1 ) | +| 12 | ebreaku | Environment breakpoint u-mode | read-write | Shows the behavior of the ``ebreak`` instruction in user mode\. // ``Enumerated Values``( "break_as_spec" :0 ) ( "break_to_debug" :1 ) | | 11 | stepie | Stepping interrupt enable | read-write,WARL | Enables/disables interrupts for single stepping\. The debugger must not change the value of this bit while the hart is running\. // ``Enumerated Values``( "disabled" :0 ) ( "enabled" :1 ) | | 10 | stopcount | Stop counters | read-write,WARL | Starts/stops incrementing counters in debug mode\. // ``Enumerated Values``( "increment_counters" :0 ) ( "dont_increment_counters" :1 ) | | 9 | stoptime | Stop timers | read-write,WARL | Starts/stops incrementing timers in debug mode\. // ``Enumerated Values``( "increment_timers" :0 ) ( "dont_increment_timers" :1 ) | @@ -844,11 +844,11 @@ Instructions-retired counter for RDINSTRET instruction ## Machine Vendor ID Register ### *AddressOffset*: 'hF11 ### *Description*: -This register provids the JEDEC manufacturer ID of the provider of the core. +This register provides the JEDEC manufacturer ID of the provider of the core. | BIT | NAME | displayName | RIGHT | Description | | --- | ----------- | ------------ | ------ | -------------------------------------------------------------------- | | 31:7 | bank | Bank | read-only | Contain encoding for number of one\-byte continuation codes discarding the parity bit\.| -| 6:0 | offset | Offset | read-only | Contain encording for the final byte discarding the parity bit\.| +| 6:0 | offset | Offset | read-only | Contain encoding for the final byte discarding the parity bit\.| ## Machine Architecture ID Register ### *AddressOffset*: 'hF12 diff --git a/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst b/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst index f4190bb896d..24ba5f3a043 100644 --- a/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst +++ b/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst @@ -570,7 +570,7 @@ The ``sip`` register contains information on pending interrupts. - USIP - - read-write,WARL - - A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending \(USIP\) bit.``Legal Values:`` 0. + - A user-level software interrupt is triggered on the current hart by writing 1 to its user software interrupt-pending \(USIP\) bit.``Legal Values:`` 0. Supervisor Address Translation and Protection Register ------------------------------------------------------ @@ -888,7 +888,7 @@ This register contains machine interrupt enable bits. - USIE - - read-write,WARL - - enable U-mode software interrrupts.``Legal Values:`` 0. + - enable U-mode software interrupts.``Legal Values:`` 0. Machine Trap Vector Register ---------------------------- @@ -1428,7 +1428,7 @@ Address register for Physical Memory Protection. - read-write,WARL - Address register for Physical Memory Protection. -Instuction Cache Register +Instruction Cache Register -------------------------- AddressOffset: 'h7C0 -------------------------- @@ -1605,7 +1605,7 @@ AddressOffset: 'h7B0 -------------------------- Description: -------------------------- -Debug ontrol and status register. +Debug control and status register. .. list-table:: :widths: 20 20 15 15 40 @@ -1625,7 +1625,7 @@ Debug ontrol and status register. - ebreakm - Environment breakpoint m-mode - read-write - - Shows the behvior of the ``ebreak`` instruction in machine mode. ``Enumerated Values`` ( "break_as_spec" :0)( "break_to_debug" :1)'\n' + - Shows the behavior of the ``ebreak`` instruction in machine mode. ``Enumerated Values`` ( "break_as_spec" :0)( "break_to_debug" :1)'\n' * - 13 - ebreaks - Environment breakpoint s-mode @@ -2651,7 +2651,7 @@ AddressOffset: 'hF11 -------------------------- Description: -------------------------- -This register provids the JEDEC manufacturer ID of the provider of the core. +This register provides the JEDEC manufacturer ID of the provider of the core. .. list-table:: :widths: 20 20 15 15 40 @@ -2671,7 +2671,7 @@ This register provids the JEDEC manufacturer ID of the provider of the core. - offset - Offset - read-only - - Contain encording for the final byte discarding the parity bit. + - Contain encoding for the final byte discarding the parity bit. Machine Architecture ID Register -------------------------------- diff --git a/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.xml b/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.xml index f6c12612c8f..0feeceeb2b4 100644 --- a/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.xml +++ b/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.xml @@ -1130,7 +1130,7 @@ The value loaded into ``stval`` on an illegal-instruction exception is right-jus USIP - A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0. + A user-level software interrupt is triggered on the current hart by writing 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0. 0 @@ -2066,7 +2066,7 @@ with the index of the bit position equal to the value returned in the ``mcause`` USIE - enable U-mode software interrrupts.``Legal Values:``0. + enable U-mode software interrupts.``Legal Values:``0. 0 @@ -2910,7 +2910,7 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or icache - Instuction Cache + Instruction Cache Custom Register to enable/disable for Icache [bit 0] 'h7C0 32 @@ -3218,7 +3218,7 @@ If ``type`` is not writable, this register may be unimplemented, in which case r dcsr Debug Control and Status - Debug ontrol and status register. + Debug control and status register. 'h7B0 32 true @@ -3258,7 +3258,7 @@ If ``type`` is not writable, this register may be unimplemented, in which case r ebreakm Environment Breakpoint M-mode - Shows the behvior of the ``ebreak`` instruction in machine mode. + Shows the behavior of the ``ebreak`` instruction in machine mode. 15 @@ -3284,7 +3284,7 @@ If ``type`` is not writable, this register may be unimplemented, in which case r ebreaks Environment Breakpoint S-mode - Shows the behvior of the ``ebreak`` instruction in supervisor mode. + Shows the behavior of the ``ebreak`` instruction in supervisor mode. 13 @@ -3310,7 +3310,7 @@ If ``type`` is not writable, this register may be unimplemented, in which case r ebreaku Environment Breakpoint U-mode - Shows the behvior of the ``ebreak`` instruction in user mode. + Shows the behavior of the ``ebreak`` instruction in user mode. 12 @@ -4614,7 +4614,7 @@ When resuming, the hart’s PC is updated to the virtual address stored in ``dpc mvendorid Machine Vendor ID - This register provids the JEDEC manufacturer ID of the provider of the core. + This register provides the JEDEC manufacturer ID of the provider of the core. 'hF11 32 true @@ -4637,7 +4637,7 @@ When resuming, the hart’s PC is updated to the virtual address stored in ``dpc offset Offset - Contain encording for the final byte discarding the parity bit. + Contain encoding for the final byte discarding the parity bit. 0 diff --git a/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.yaml b/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.yaml index 7b9ed4f7ff8..c0bfeff8c51 100644 --- a/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.yaml +++ b/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.yaml @@ -801,7 +801,7 @@ component: vendorExtensions: RISCV_behavior: WARL - name: USIP - description: A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0. + description: A user-level software interrupt is triggered on the current hart by writing 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0. bitOffset: '0' resets: reset: @@ -2072,7 +2072,7 @@ component: vendorExtensions: privilege_mode: M - name: icache - displayName: Instuction Cache + displayName: Instruction Cache description: Custom Register to enable/disable for Icache [bit 0] addressOffset: "'h7C0" size: '32' diff --git a/docs/csr-from-ip-xact/cv32a60x/csr.rst b/docs/csr-from-ip-xact/cv32a60x/csr.rst index 4ff553a2704..9fc79270357 100644 --- a/docs/csr-from-ip-xact/cv32a60x/csr.rst +++ b/docs/csr-from-ip-xact/cv32a60x/csr.rst @@ -116,7 +116,7 @@ The ``mstatus`` register keeps track of and controls the hart’s current operat - Indicates whether machine interrupts were enabled prior to trapping into machine mode\. ``Enumerated Values``( "Disabled" :0)( "Enabled" :1)'\n' * - 6 - UBE - - User mode bit endianess + - User mode bit endianness - 0x0 - read-write,WARL - UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian or big\-endian\.``Legal Values``:0\. ``Enumerated Values``( "Little-endian" :0)( "Big-endian" :1)'\n' @@ -289,7 +289,7 @@ This register contains machine interrupt enable bits. - - 0x0 - read-write,WARL - - enable U\-mode software interrrupts\.``Legal Values:``0\. + - enable U\-mode software interrupts\.``Legal Values:``0\. MTVEC:Machine Trap Vector Register -------------------------- @@ -348,13 +348,13 @@ The ``mstatush`` is the upper 32-bits of Machine status only for RV32. - Reserved * - 4 - SBE - - Supervisor mode bit endianess + - Supervisor mode bit endianness - 0x0 - read-write,WARL - SBE controls whether explicit load and store memory accesses made from S\-mode are little\-endian or big\-endian\.``Legal Values``:0\. ``Enumerated Values``( "Little-endian" :0)( "Big-endian" :1)'\n' * - 5 - MBE - - Machine mode bit endianess + - Machine mode bit endianness - 0x0 - read-write,WARL - MBE controls whether explicit load and store memory accesses made from M\-mode are little\-endian or big\-endian\.``Legal Values``:0\. ``Enumerated Values``( "Little-endian" :0)( "Big-endian" :1)'\n' @@ -3646,7 +3646,7 @@ AddressOffset: 'hF11 -------------------------- Description: -------------------------- -This register provids the JEDEC manufacturer ID of the provider of the core. +This register provides the JEDEC manufacturer ID of the provider of the core. .. list-table:: :widths: 20 20 15 10 15 40 @@ -3669,7 +3669,7 @@ This register provids the JEDEC manufacturer ID of the provider of the core. - Offset - 0x2 - read-only - - Contain encording for the final byte discarding the parity bit\. + - Contain encoding for the final byte discarding the parity bit\. MARCHID:Machine Architecture ID Register -------------------------- diff --git a/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md b/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md index 42b74e652ad..be8e5e0ca0c 100644 --- a/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md +++ b/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md @@ -28,7 +28,7 @@ The ``mstatus`` register keeps track of and controls the hart’s current operat | 10:9 | VS | Vector extension state | 0x0 | read-only,WARL | V extension is not supported\.``Legal Values``:0\.| | 8 | SPP | Supervisor mode prior privilege | 0x0 | read-write | Holds the previous privilege mode for supervisor mode\. // ``Enumerated Values``( "U-mode" :0 ) ( "Otherwise" :1 ) | | 7 | MPIE | Machine mode prior interrupt enable | 0x0 | read-write | Indicates whether machine interrupts were enabled prior to trapping into machine mode\. // ``Enumerated Values``( "Disabled" :0 ) ( "Enabled" :1 ) | -| 6 | UBE | User mode bit endianess | 0x0 | read-write,WARL | UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian or big\-endian\.``Legal Values``:0\. // ``Enumerated Values``( "Little-endian" :0 ) ( "Big-endian" :1 ) | +| 6 | UBE | User mode bit endianness | 0x0 | read-write,WARL | UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian or big\-endian\.``Legal Values``:0\. // ``Enumerated Values``( "Little-endian" :0 ) ( "Big-endian" :1 ) | | 5 | SPIE | Supervisor mode prior interrupt enable | 0x0 | read-write | Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode\. // ``Enumerated Values``( "Disabled" :0 ) ( "Enabled" :1 ) | | 4 | reserved_1 | Reserved | 0x0 | read-write,WPRI | Reserved| | 3 | MIE | Machine mode interrupt enable | 0x0 | read-write | Global interrupt\-enable bit for Machine mode\. // ``Enumerated Values``( "Disabled" :0 ) ( "Enabled" :1 ) | @@ -64,7 +64,7 @@ This register contains machine interrupt enable bits. | 3 | MSIE | M-mode software interrupt enable | 0x0 | read-write | Enables machine mode software interrupts\.| | 2 | Reserved_2 | Reserved | 0x0 | read-write,WARL | Reserved\.``Legal Values:``0\.| | 1 | SSIE | S-mode software interrupt enable | 0x0 | read-write,WARL | Enables supervisor mode software interrupts\.| -| 0 | USIE | | 0x0 | read-write,WARL | enable U\-mode software interrrupts\.``Legal Values:``0\.| +| 0 | USIE | | 0x0 | read-write,WARL | enable U\-mode software interrupts\.``Legal Values:``0\.| ## MTVEC : Machine Trap Vector Register ### *AddressOffset*: 'h305 @@ -82,8 +82,8 @@ The ``mstatush`` is the upper 32-bits of Machine status only for RV32. | BIT | NAME | displayName |Reset| RIGHT | Description | | --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | | 3:0 | reserved_0 | Reserved | 0x0 | read-write,WPRI | Reserved| -| 4 | SBE | Supervisor mode bit endianess | 0x0 | read-write,WARL | SBE controls whether explicit load and store memory accesses made from S\-mode are little\-endian or big\-endian\.``Legal Values``:0\. // ``Enumerated Values``( "Little-endian" :0 ) ( "Big-endian" :1 ) | -| 5 | MBE | Machine mode bit endianess | 0x0 | read-write,WARL | MBE controls whether explicit load and store memory accesses made from M\-mode are little\-endian or big\-endian\.``Legal Values``:0\. // ``Enumerated Values``( "Little-endian" :0 ) ( "Big-endian" :1 ) | +| 4 | SBE | Supervisor mode bit endianness | 0x0 | read-write,WARL | SBE controls whether explicit load and store memory accesses made from S\-mode are little\-endian or big\-endian\.``Legal Values``:0\. // ``Enumerated Values``( "Little-endian" :0 ) ( "Big-endian" :1 ) | +| 5 | MBE | Machine mode bit endianness | 0x0 | read-write,WARL | MBE controls whether explicit load and store memory accesses made from M\-mode are little\-endian or big\-endian\.``Legal Values``:0\. // ``Enumerated Values``( "Little-endian" :0 ) ( "Big-endian" :1 ) | | 31:6 | reserved_1 | Reserved | 0x0 | read-write,WPRI | Reserved| ## MHPMEVENT3 : Machine Hardware Performance-Monitoring Event Selector Register @@ -1115,11 +1115,11 @@ Instructions-retired counter for RDINSTRET instruction. Shadow of minstreth. ## MVENDORID : Machine Vendor ID Register ### *AddressOffset*: 'hF11 ### *Description*: -This register provids the JEDEC manufacturer ID of the provider of the core. +This register provides the JEDEC manufacturer ID of the provider of the core. | BIT | NAME | displayName |Reset| RIGHT | Description | | --- | ----------- | ------------ |-----| ------ | -------------------------------------------------------------------- | | 31:7 | bank | Bank | 0xC | read-only | Contain encoding for number of one\-byte continuation codes discarding the parity bit\.| -| 6:0 | offset | Offset | 0x2 | read-only | Contain encording for the final byte discarding the parity bit\.| +| 6:0 | offset | Offset | 0x2 | read-only | Contain encoding for the final byte discarding the parity bit\.| ## MARCHID : Machine Architecture ID Register ### *AddressOffset*: 'hF12 diff --git a/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.xml b/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.xml index 32bc2c9be09..f216d9e59c9 100644 --- a/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.xml +++ b/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.xml @@ -424,7 +424,7 @@ UBE - User mode Bit Endianess + User mode Bit Endianness UBE controls whether explicit load and store memory accesses made from U-mode are little-endian or big-endian.``Legal Values``:0. 6 @@ -998,7 +998,7 @@ USIE - enable U-mode software interrrupts.``Legal Values:``0. + enable U-mode software interrupts.``Legal Values:``0. 0 @@ -1108,7 +1108,7 @@ SBE - Supervisor mode Bit Endianess + Supervisor mode Bit Endianness SBE controls whether explicit load and store memory accesses made from S-mode are little-endian or big-endian.``Legal Values``:0. 4 @@ -1135,7 +1135,7 @@ MBE - Machine mode Bit Endianess + Machine mode Bit Endianness MBE controls whether explicit load and store memory accesses made from M-mode are little-endian or big-endian.``Legal Values``:0. 5 @@ -4757,7 +4757,7 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or mvendorid Machine Vendor ID - This register provids the JEDEC manufacturer ID of the provider of the core. + This register provides the JEDEC manufacturer ID of the provider of the core. 'hF11 32 true @@ -4780,7 +4780,7 @@ If ``mtval`` is written with a nonzero value when an instruction access-fault or offset Offset - Contain encording for the final byte discarding the parity bit. + Contain encoding for the final byte discarding the parity bit. 0 diff --git a/docs/design/design-manual/source/AXI_Interface.adoc b/docs/design/design-manual/source/AXI_Interface.adoc index 1da1cf31c0d..2430cd5c042 100644 --- a/docs/design/design-manual/source/AXI_Interface.adoc +++ b/docs/design/design-manual/source/AXI_Interface.adoc @@ -16,7 +16,7 @@ Introduction ^^^^^^^^^^^^ In this chapter, we describe in detail the restriction that apply to the supported features. -In order to understand how the AXI memory interface behaves in CVA6, it is necessary to read the AMBA AXI and ACE Protocol Specification (https://developer.arm.com/documentation/ihi0022/hc) and this chapter. +In order to understand how the AXI memory interface behaves in CVA6, it is necessary to read the AXI and ACE Protocol Specification (https://developer.arm.com/documentation/ihi0022/hc) and this chapter. _Applicability of this chapter to configurations:_ @@ -31,7 +31,7 @@ _Applicability of this chapter to configurations:_ About the AXI4 protocol +++++++++++++++++++++++ -The AMBA AXI protocol supports high-performance, high-frequency system designs for communication between Manager and Subordinate components. +The AXI protocol supports high-performance, high-frequency system designs for communication between Manager and Subordinate components. The AXI protocol features are: @@ -61,7 +61,7 @@ AXI4 and CVA6 The AXI bus protocol is used with the CVA6 processor as a memory interface. Since the processor is the one that initiates the connection with the memory, it will have a manager interface to send requests to the subordinate, which will be the memory. -Features supported by CVA6 are the ones in the AMBA AXI4 specification and the Atomic Operation feature from AXI5. With restriction that apply to some features. +Features supported by CVA6 are the ones in the AXI4 specification and the Atomic Operation feature from AXI5. With restriction that apply to some features. This doesn’t mean that all the full set of signals available on an AXI interface are supported by the CVA6. Nevertheless, all required AXI signals are implemented. @@ -747,7 +747,7 @@ _Write Strobe width is equal to (AXI_DATA_WIDTH/8) (n = (AXI_DATA_WIDTH/8)-1)._ _The size of transactions performed by cva6 is equal to the number of data byte lanes containing valid information._ _This means 1, 2, 4, ... or (AXI_DATA_WIDTH/8) byte lanes containing valid information._ -_CVA6 doesn't perform unaligned memory acces, therefore the WSTRB take only combination of aligned access_ +_CVA6 doesn't perform unaligned memory access, therefore the WSTRB take only combination of aligned access_ _If(RV32) WSTRB < 255 (Since AWSIZE lower than 3, so the data bus cannot have more than 4 valid byte lanes)_ *Unaligned transfers* @@ -829,7 +829,7 @@ If the CVA6 requires ordering between transactions that have no ordering guarant Memory locations and Peripheral regions (Section A6.2) ++++++++++++++++++++++++++++++++++++++++++++++++++++++ -The address map in AMBA is made up of Memory locations and Peripheral regions. But the AXI is associated to the memory interface of CVA6. +The address maps in some bus specifications can differentiate Memory locations and Peripheral regions. But the AXI is associated to the memory interface of CVA6. A Memory location has all of the following properties: @@ -873,7 +873,7 @@ An interface that exhibits Ordered Write Observation gives guarantees for write Atomic transactions (Section E1.1) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -AMBA 5 introduces Atomic transactions, which perform more than just a single access and have an operation that is associated with the transaction. Atomic transactions enable sending the operation to the data, permitting the operation to be performed closer to where the data is located. Atomic transactions are suited to situations where the data is located a significant distance from the agent that must perform the operation. +AXI 5 introduces Atomic transactions, which perform more than just a single access and have an operation that is associated with the transaction. Atomic transactions enable sending the operation to the data, permitting the operation to be performed closer to where the data is located. Atomic transactions are suited to situations where the data is located a significant distance from the agent that must perform the operation. _If(RVA) AWATOP = 0 (If AMO instructions are not supported, CVA6 cannot perform Atomic transaction)_ diff --git a/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc b/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc index cfdfdf86071..0ca23120d3b 100644 --- a/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc +++ b/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc @@ -41,7 +41,7 @@ The specification of the CV-X-IF bus protocol can be found at [CV-X-IF]. CV-X-IF aims to: * Create interfaces to connect a coprocessor to the CVA6 to execute instructions. -* Offload CVA6 illegal instrutions to the coprocessor to be executed. +* Offload CVA6 illegal instructions to the coprocessor to be executed. * Get the results of offloaded instructions from the coprocessor so they are written back into the CVA6 register file. * Add standard RISC-V instructions unsupported by CVA6 or custom instructions and implement them in a coprocessor. * Kill offloaded instructions to allow speculative execution in the coprocessor. (Unsupported in CVA6 yet) @@ -234,7 +234,7 @@ Here is _how_ and _to what_ CV-X-IF interfaces are connected to the CVA6. *** [verse] -- Result response is directly connected to writeback bus of the CV-X-IF - functionnal unit. + functional unit. -- *** [verse] -- @@ -283,7 +283,7 @@ CVA6 supports all coprocessors supporting the CV-X-IF specification with the exc is not big enough to have RVC and a custom compressed extension. * Stateful coprocessors.:: ** CVA6 will commit on the Commit interface all its issue transactions. Speculation - informations are only kept in the CVA6 and speculation process is only done in CVA6. + information is only kept in the CVA6 and speculation process is only done in CVA6. The coprocessor shall be stateless otherwise it will not be able to revert its state if CVA6 kills an in-flight instruction (in case of mispredict or flush). diff --git a/docs/design/design-manual/source/Traps_Interrupts_Exceptions.adoc b/docs/design/design-manual/source/Traps_Interrupts_Exceptions.adoc index 078e02584e4..48764d6251d 100644 --- a/docs/design/design-manual/source/Traps_Interrupts_Exceptions.adoc +++ b/docs/design/design-manual/source/Traps_Interrupts_Exceptions.adoc @@ -4,7 +4,7 @@ Traps, Interrupts, Exceptions Traps are composed of interrupts and exceptions. Interrupts are asynchronous events whereas exceptions are synchronous ones. -On one hand, interrupts are occuring independently of the instructions +On one hand, interrupts are occurring independently of the instructions (mainly raised by peripherals or debug module). On the other hand, an instruction may raise exceptions synchronously. diff --git a/docs/design/design-manual/source/cva6_execute.adoc b/docs/design/design-manual/source/cva6_execute.adoc index 55f98719cfe..f39802ffb35 100644 --- a/docs/design/design-manual/source/cva6_execute.adoc +++ b/docs/design/design-manual/source/cva6_execute.adoc @@ -98,7 +98,7 @@ include::port_load_store_unit.adoc[] The store_unit module manages the data store operations. -As stores can be speculative, the store instructions need to be committed by ISSUE_STAGE module before possibily altering the processor state. +As stores can be speculative, the store instructions need to be committed by ISSUE_STAGE module before possibly altering the processor state. Store buffer keeps track of store requests. Outstanding store instructions (which are speculative) are differentiated from committed stores. When ISSUE_STAGE module commits a store instruction, outstanding stores @@ -121,7 +121,7 @@ It stalls until it can satisfy the current request. This means: * Two loads to the same address are allowed. * Two stores to the same address are allowed. * A store after a load to the same address is allowed. -* A load after a store to the same address can only be processed if the store has already been sent to the cache i.e there is no fowarding. +* A load after a store to the same address can only be processed if the store has already been sent to the cache i.e there is no forwarding. After the check of the store buffer, a read request is sent to the D$ with the index field of the address (1). The load unit stalls until the D$ acknowledges this request (2). diff --git a/docs/design/design-manual/source/cva6_frontend.adoc b/docs/design/design-manual/source/cva6_frontend.adoc index ced4d04ffc6..925a3de448b 100644 --- a/docs/design/design-manual/source/cva6_frontend.adoc +++ b/docs/design/design-manual/source/cva6_frontend.adoc @@ -28,7 +28,7 @@ FRONTEND can fetch up to {instr-per-fetch} instructions per cycle, but DECODE mo The module is connected to: -* CACHES module provides fethed instructions to FRONTEND. +* CACHES module provides fetched instructions to FRONTEND. * DECODE module receives instructions from FRONTEND. * CONTROLLER module can order to flush and to halt FRONTEND PC gen stage * EXECUTE, CONTROLLER, CSR and COMMIT modules trigger PC jumping due to @@ -57,8 +57,8 @@ cases are considered: ________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________________ 1. When the instruction is a JALR which corresponds to a return (rs1 = x1 or rs1 = x5). RAS provides next PC as a prediction. -2. When the instruction is a JALR which *does not* correspond to areturn. -If BTB (Branch Target Buffer) returns a valid address, then BTBpredicts next PC. +2. When the instruction is a JALR which *does not* correspond to a return. +If BTB (Branch Target Buffer) returns a valid address, then BTB predicts next PC. Else JALR is not considered as a control flow instruction, which will generate a mispredict. 3. When the instruction is a conditional branch. If BHT (Branch History table) returns a valid address, then BHT predicts next PC. @@ -250,9 +250,9 @@ include::port_instr_realign.adoc[] Instr_queue submodule +++++++++++++++++++++ -The instr_queue receives mutliple instructions from instr_realign submodule to create a valid stream to be executed. +The instr_queue receives multiple instructions from instr_realign submodule to create a valid stream to be executed. Frontend pushes instructions and all related information into the FIFO for storage, including details needed in case of a misprediction or exception: the instructions themselves, instruction control flow type, exception, exception address, and predicted address. -DECODE pops them when decode stage is ready and indicates to the FRONTEND the instruction has been consummed. +DECODE pops them when decode stage is ready and indicates to the FRONTEND the instruction has been consumed. The instruction queue contains two FIFOs: one for instructions and one for addresses, which stores addresses in case of a prediction. @@ -272,7 +272,7 @@ Instr_scan submodule As compressed extension is enabled, {instr-per-fetch} instr_scan are instantiated to handle up to {instr-per-fetch} instructions per cycle. Each instr_scan submodule pre-decodes the fetched instructions coming from the instr_realign module, also calculate the immediate, instructions could be compressed or not. -The instr_scan submodule is a flox controler which provides the intruction type: branch, jump, return, jalr, imm, call or others. +The instr_scan submodule is a flow controller which provides the instruction type: branch, jump, return, jalr, imm, call or others. These outputs are used by the branch prediction feature. include::port_instr_scan.adoc[] diff --git a/docs/design/design-manual/source/cva6_issue_stage.adoc b/docs/design/design-manual/source/cva6_issue_stage.adoc index ab8a1c08e86..d1c113217fe 100644 --- a/docs/design/design-manual/source/cva6_issue_stage.adoc +++ b/docs/design/design-manual/source/cva6_issue_stage.adoc @@ -52,7 +52,7 @@ ISSUE_STAGE has three functionalities. (1) ISSUE_STAGE issues instructions. Instructions from ID_STAGE are sent to Scoreboard module, which forwards them to Issue_read_operands module. -Issue_read_operands queries Scoreboard module for data dependences (Scoreboard is also able to return forwarded values) and gets the list of busy functional units from EX_STAGE. +Issue_read_operands queries Scoreboard module for data dependencies (Scoreboard is also able to return forwarded values) and gets the list of busy functional units from EX_STAGE. Issue_read_operands sends to EX_STAGE the instructions to execute and acknowledges to Scoreboard so that it stores them: the instruction is issued. Issued instructions are acknowledged to ID_STAGE. Each of these steps can block its successors. @@ -86,7 +86,7 @@ Scoreboard is used in all three functionalities of ISSUE_STAGE. (1) ISSUE_STAGE issues instructions. Up to {issue-width} instruction(s) can be received from ID_STAGE each cycle. They are transmitted to Issue_read_operands with incremental transaction IDs which wrap at {NrScoreboardEntries}. -The result buses and Scoreboard entries are also transmitted to Issue_read_operands for it to detect data dependences and perform operand forwarding. +The result buses and Scoreboard entries are also transmitted to Issue_read_operands for it to detect data dependencies and perform operand forwarding. When Issue_read_operands acknowledges an instruction, it is inserted into the FIFO. Scoreboard has a capacity of {NrScoreboardEntries} entries. diff --git a/docs/design/design-manual/source/design.adoc b/docs/design/design-manual/source/design.adoc index 169f9904370..34f1581a9b0 100644 --- a/docs/design/design-manual/source/design.adoc +++ b/docs/design/design-manual/source/design.adoc @@ -21,7 +21,7 @@ ifeval::[{SuperscalarEn} == false] :ifetch-len: 32 :instr-per-fetch: 2 :issue-width: 1 -:commit-width: {NrCommmitPorts} +:commit-width: {NrCommitPorts} endif::[] :SpeculativeSb: {SuperscalarEn} diff --git a/docs/index.rst b/docs/index.rst index ce38770a99a..7cfef391e31 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -38,7 +38,7 @@ The naming convention for these cores is: ``CV <# of pipeline stages> `` Thus, the CV64A60 would be a 64-bit application core with a six stage pipeline. -Note that in this example, the product identifer is "0". +Note that in this example, the product identifier is "0". Organization of this Document @@ -69,5 +69,6 @@ The :doc:`CVA6 APU <05_cva6_apu/index>` describes an Application Processor Unit 01_cva6_user/index.rst 03_cva6_design/index.rst 04_cv32a65x/index.rst + 07_cv32a60x/index.rst 06_cv64a6_mmu/index.rst 05_cva6_apu/index.rst diff --git a/docs/riscv-isa/src/machine.adoc b/docs/riscv-isa/src/machine.adoc index 1f647106c7d..06246d1aa7b 100644 --- a/docs/riscv-isa/src/machine.adoc +++ b/docs/riscv-isa/src/machine.adoc @@ -398,7 +398,7 @@ field is not implemented. The Implementation value should reflect the design of the RISC-V processor itself and not any surrounding system. endif::[] -ifeval::["{ohg-config}" == "CV32A65X"] +ifdef::archi-CV32A60X,archi-CV32A65X[] The `mimpid` CSR provides a unique encoding of the version of the processor implementation. @@ -508,7 +508,7 @@ For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in <>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`. endif::[] -ifeval::["{ohg-config}" == "CV32A65X"] +ifdef::archi-CV32A60X,archi-CV32A65X[] [{ohg-config}] `mstatush` is a 32-bit read/write register formatted as shown in <>. endif::[] @@ -1249,7 +1249,7 @@ different encoding than XS. ==== endif::[] -ifeval::["{ohg-config}" == "CV32A65X"] +ifdef::archi-CV32A60X,archi-CV32A65X[] [{ohg-config}] The FS[1:0] and VS[1:0] *WARL* fields and the XS[1:0] read-only field are used to reduce the cost of context save and restore by setting and tracking the current state of the floating-point unit and any other user-mode @@ -2115,7 +2115,7 @@ ifdef::archi-CVA6[] As the Sscofpmf extension is not implemented, `mip`.LCOFIP and `mie`.LCOFIE are read-only zeros. endif::[] -ifeval::["{ohg-config}" == "CV32A65X"] +ifdef::archi-CV32A60X,archi-CV32A65X[] [{ohg-config}] Multiple simultaneous interrupts destined for M-mode are handled in the following decreasing priority order: MEI, MSI, MTI. @@ -2218,7 +2218,7 @@ As XLEN=64, `mcycleh`, `minstreth`, and `mhpmcounter__n__h` do not exist. endif::[] -ifeval::["{ohg-config}" == "CV32A65X"] +ifdef::archi-CV32A60X,archi-CV32A65X[] As the Sscofpmf extension is not implemented, the `mhpmevent__n__h` CSRs are not provided. endif::[] @@ -3509,7 +3509,7 @@ As "{ohg-config}" does not distinguished different reset conditions, The `mcause` returns 0 after reset. endif::[] -ifeval::["{ohg-config}" == "CV32A65X"] +ifdef::archi-CV32A60X,archi-CV32A65X[] [{ohg-config}] Privilege mode is always M. As little-endian memory accesses are supported, the `mstatus`/`mstatush` field MBE is reset to 0. @@ -4068,6 +4068,13 @@ endif::[] [[pmp]] === Physical Memory Protection +ifeval::[{NrPMPEntries} == 0] +[{ohg-config}] There is no optional physical memory protection (PMP) +unit. +endif::[] + +ifeval::[{NrPMPEntries} != 0] + To support secure processing and contain faults, it is desirable to limit the physical addresses accessible by software running on a hart. An optional physical memory protection (PMP) unit provides per-hart @@ -4491,3 +4498,5 @@ ifeval::["{ohg-config}" == "CV32A65X"] [{ohg-config}] As page-based virtual memory systems is not implemented, memory accesses check the PMP settings synchronously. endif::[] + +endif::[] diff --git a/docs/riscv-isa/src/mm-formal.adoc b/docs/riscv-isa/src/mm-formal.adoc index 200edb8febb..87832d341a1 100644 --- a/docs/riscv-isa/src/mm-formal.adoc +++ b/docs/riscv-isa/src/mm-formal.adoc @@ -2,6 +2,6 @@ == Formal Memory Model Specifications, Version 0.1 [[mm-formal]] -ifeval::["{ohg-config}" == "CV32A65X"] +ifdef::archi-CV32A60X,archi-CV32A65X[] {ohg-config}: No RVWMO memory model. endif::[] diff --git a/docs/riscv-isa/src/rv-32-64g.adoc b/docs/riscv-isa/src/rv-32-64g.adoc index b23abfab43b..4f2e8f2629f 100644 --- a/docs/riscv-isa/src/rv-32-64g.adoc +++ b/docs/riscv-isa/src/rv-32-64g.adoc @@ -16,6 +16,39 @@ ifdef::archi-CVA6[] listings for {ohg-config}. endif::[] +ifeval::[{RVA} == true] +:AMO: AMO +endif::[] +ifeval::[{RVA} == false] +:AMO: not used +endif::[] +ifeval::[{RVF} == true] +:LOAD-FP: LOAD-FP +:STORE-FP: STORE-FP +:MADD: MADD +:MSUB: MSUB +:NMSUB: NMSUB +:NMADD: NMADD +:OP-FP: OP-FP +endif::[] +ifeval::[{RVF} == false] +:LOAD-FP: _not-used_ +:STORE-FP: not used +:MADD: not used +:MSUB: not used +:NMSUB: not used +:NMADD: not used +:OP-FP: not used +endif::[] +ifeval::[{RVV} == true] +:OP-V: OP-V +:OP-VE: OP-VE +endif::[] +ifeval::[{RVV} == false] +:OP-V: not used +:OP-VE: not used +endif::[] + // note: ≥ is unicode for >= [[opcodemap]] .RISC-V base opcode map, inst[1:0]=11 @@ -23,10 +56,10 @@ endif::[] |=== |inst[4:2] .2+|000 .2+|001 .2+|010 .2+|011 .2+|100 .2+|101 .2+|110 .2+|111 (>32b) |inst[6:5] -|00 |LOAD |LOAD-FP |_custom-0_ |MISC-MEM |OP-IMM |AUIPC |OP-IMM-32 |48b -|01 |STORE |STORE-FP |_custom-1_ |AMO |OP |LUI |OP-32 |64b -|10 |MADD |MSUB |NMSUB |NMADD |OP-FP |OP-V |_custom-2/rv128_|48b -|11 |BRANCH |JALR |_reserved_ |JAL |SYSTEM |OP-VE |_custom-3/rv128_|≥80b +|00 |LOAD |{LOAD-FP}|_custom-0_ |MISC-MEM |OP-IMM |AUIPC |OP-IMM-32 |48b +|01 |STORE |{STORE-FP}|_custom-1_|{AMO} |OP |LUI |OP-32 |64b +|10 |{MADD} |{MSUB} |{NMSUB} |{NMADD} |{OP-FP}|{OP-V} |_custom-2/rv128_|48b +|11 |BRANCH |JALR |_reserved_ |JAL |SYSTEM |{OP-VE} |_custom-3/rv128_|≥80b |=== <> shows a map of the major opcodes for diff --git a/docs/riscv-isa/src/zimop.adoc b/docs/riscv-isa/src/zimop.adoc index b66c8364142..98ba3b2a045 100644 --- a/docs/riscv-isa/src/zimop.adoc +++ b/docs/riscv-isa/src/zimop.adoc @@ -7,6 +7,6 @@ endif::[] === "Zcmop" Compressed May-Be-Operations Extension, Version 1.0 -ifeval::[{RVZimop} == false] +ifeval::[{RVZcmop} == false] {ohg-config}: This extension is not supported. endif::[] diff --git a/docs/scripts/classes.py b/docs/scripts/classes.py index cfc79cb1458..f11b5ec8b0a 100644 --- a/docs/scripts/classes.py +++ b/docs/scripts/classes.py @@ -7,7 +7,7 @@ # # Original Author: Jean-Roch COULON - Thales -#!/usr/bin/python3 +#!/usr/bin/env python3 class Parameter: diff --git a/docs/scripts/define_blacklist.py b/docs/scripts/define_blacklist.py index bdee4b2fdfa..2ed886339c5 100644 --- a/docs/scripts/define_blacklist.py +++ b/docs/scripts/define_blacklist.py @@ -7,7 +7,7 @@ # # Original Author: Jean-Roch COULON - Thales -#!/usr/bin/python3 +#!/usr/bin/env python3 def define_blacklist(parameters): diff --git a/docs/scripts/parameters_extractor.py b/docs/scripts/parameters_extractor.py index 09365c263d1..e5ef4dd7666 100644 --- a/docs/scripts/parameters_extractor.py +++ b/docs/scripts/parameters_extractor.py @@ -7,7 +7,7 @@ # # Original Author: Jean-Roch COULON - Thales -#!/usr/bin/python3 +#!/usr/bin/env python3 import sys import os diff --git a/docs/scripts/spec_builder.py b/docs/scripts/spec_builder.py index 31c47ea86cb..1abb760dd19 100755 --- a/docs/scripts/spec_builder.py +++ b/docs/scripts/spec_builder.py @@ -7,7 +7,7 @@ # # Original Author: Jean-Roch COULON - Thales -#!/usr/bin/python3 +#!/usr/bin/env python3 import re import sys @@ -51,14 +51,24 @@ 'RVZabha': False, 'RVZacas': False, 'RVZawrs': False, + 'RVZcmop': False, 'RVZfa': False, 'RVZfbf-RZvfbf': False, 'RVZfh': False, 'RVZfinx': False, 'RVZicbo': False, 'RVZicfilp': False, + 'RVZifencei': False, + 'RVZihintntl': False, + 'RVZihintpause': False, + 'RVZimop': False, + 'RVZk': False, 'RVZpm': False, + 'RVZsmcdeleg': False, + 'RVZsmcntrpmf': False, + 'RVZsmcsrind-RVZsscsrind': False, 'RVZsmctr': False, + 'RVZsmdbltrp': False, 'RVZsmepmp': False, 'RVZsmmpm': False, 'RVZsmrnmi': False, @@ -181,6 +191,7 @@ def main(): file.append("../core/cva6.sv") file.append("../core/frontend/frontend.sv") file.append("../core/frontend/bht.sv") + file.append("../core/frontend/bht2lvl.sv") file.append("../core/frontend/btb.sv") file.append("../core/frontend/ras.sv") file.append("../core/frontend/instr_queue.sv") diff --git a/docs/user_guide/cva6_ug_csr.adoc b/docs/user_guide/cva6_ug_csr.adoc index 113f0b8afb5..a609e83410f 100644 --- a/docs/user_guide/cva6_ug_csr.adoc +++ b/docs/user_guide/cva6_ug_csr.adoc @@ -36,7 +36,7 @@ This is illustrated below for the `12'h7C0`-`12'h7FF` range. |`CSR_SIP`|`12’h144`|Supervisor interrupt pending|Yes|Yes|Supervisor |`CSR_STVEC`|`12’h105`|Supervisor trap handler base address|Yes|Yes|Supervisor |`CSR_SCOUNTEREN`|`12’h106`|Supervisor counter enable|Yes|Yes|Supervisor -|`CSR_SSCRATCH`|`12’h140`|Scartch Register for supervisor trap handlers|Yes|Yes|Supervisor +|`CSR_SSCRATCH`|`12’h140`|Scratch Register for supervisor trap handlers|Yes|Yes|Supervisor |`CSR_SEPC`|`12’h141`|Supervisor exception program counter|Yes|Yes|Supervisor |`CSR_SCAUSE`|`12’h142`|Supervisor trap cause|Yes|Yes|Supervisor |`CSR_STVAL`|`12’h143`|Supervisor bad address or instruction|Yes|Yes|Supervisor diff --git a/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv b/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv deleted file mode 100644 index f933dc6637b..00000000000 --- a/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040.sv +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2023 CEA* - * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) - * - * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - * - * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you - * may not use this file except in compliance with the License, or, at your - * option, the Apache License version 2.0. You may obtain a copy of the - * License at - * - * https://solderpad.org/licenses/SHL-2.1/ - * - * Unless required by applicable law or agreed to in writing, any work - * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ -/* - * Authors : Cesar Fuguet - * Creation Date : March, 2020 - * Description : SRAM behavioral model - * History : - */ -module hpdcache_sram_1rw_00000006_0000001c_00000040 -#( - parameter int unsigned ADDR_SIZE = 6, - parameter int unsigned DATA_SIZE = 28, - parameter int unsigned DEPTH = 2**ADDR_SIZE -) -( - input logic clk, - input logic rst_n, - input logic cs, - input logic we, - input logic [ADDR_SIZE-1:0] addr, - input logic [DATA_SIZE-1:0] wdata, - output logic [DATA_SIZE-1:0] rdata -); - - /* - * Internal memory array declaration - */ - typedef logic [DATA_SIZE-1:0] mem_t [DEPTH]; - mem_t mem; - - /* - * Process to update or read the memory array - */ - always_ff @(posedge clk) - begin : mem_update_ff - if (cs == 1'b1) begin - if (we == 1'b1) begin - mem[addr] <= wdata; - end - rdata <= mem[addr]; - end - end : mem_update_ff -endmodule : hpdcache_sram_1rw_00000006_0000001c_00000040 diff --git a/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040_00000001.sv b/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040_00000001.sv new file mode 100644 index 00000000000..9e72dab90ba --- /dev/null +++ b/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040_00000001.sv @@ -0,0 +1,70 @@ +/* + * Copyright 2023 Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * Copyright 2025 Univ. Grenoble Alpes, Inria, TIMA Laboratory + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : SRAM behavioral model + * History : + */ +module hpdcache_sram_1rw_00000006_0000001c_00000040_00000001 +#( + parameter int unsigned ADDR_SIZE = 6, + parameter int unsigned DATA_SIZE = 28, + parameter int unsigned DEPTH = 2**ADDR_SIZE, + parameter int unsigned NDATA = 1 +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [NDATA-1:0][DATA_SIZE-1:0] wdata, + output logic [NDATA-1:0][DATA_SIZE-1:0] rdata +); + + /* + * Internal memory array declaration + */ + typedef logic [NDATA-1:0][DATA_SIZE-1:0] mem_t [DEPTH]; + mem_t mem; + + /* + * Process to update or read the memory array + */ + always_ff @(posedge clk) + begin : mem_update_ff + if (cs == 1'b1) begin + if (we == 1'b1) begin + mem[addr] <= wdata; + end else begin + rdata <= mem[addr]; + end + end + end : mem_update_ff + + // DPI + // {{{ +`ifdef HPDCACHE_DPI_ON + export "DPI-C" task publicSramSetMask; + export "DPI-C" task publicSramSetData; + + task automatic publicSramSetMask; + input int index; + input logic [NDATA-1:0][DATA_SIZE-1:0] mask; + mem[index] ^= mask; + endtask + + task automatic publicSramSetData; + input int index; + input logic [NDATA-1:0][DATA_SIZE-1:0] data; + mem[index] = data; + endtask +`endif + // }}} +endmodule +// vim: ts=4 : sts=4 : sw=4 : et : tw=100 : spell : spelllang=en diff --git a/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002.sv b/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002.sv new file mode 100644 index 00000000000..ad6b04bd7b5 --- /dev/null +++ b/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002.sv @@ -0,0 +1,75 @@ +/* + * Copyright 2023 Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) + * Copyright 2025 Univ. Grenoble Alpes, Inria, TIMA Laboratory + * + * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + */ +/* + * Authors : Cesar Fuguet + * Creation Date : March, 2020 + * Description : Behavioral model of a 1RW SRAM with write byte enable + * History : + */ +module hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002 +#( + parameter int unsigned ADDR_SIZE = 7, + parameter int unsigned DATA_SIZE = 32, + parameter int unsigned DEPTH = 2**ADDR_SIZE, + parameter int unsigned NDATA = 2 +) +( + input logic clk, + input logic rst_n, + input logic cs, + input logic we, + input logic [ADDR_SIZE-1:0] addr, + input logic [NDATA-1:0][DATA_SIZE-1:0] wdata, + input logic [NDATA-1:0][DATA_SIZE/8-1:0] wbyteenable, + output logic [NDATA-1:0][DATA_SIZE-1:0] rdata +); + + /* + * Internal memory array declaration + */ + typedef logic [NDATA-1:0][DATA_SIZE-1:0] mem_t [DEPTH]; + mem_t mem; + + /* + * Process to update or read the memory array + */ + always_ff @(posedge clk) + begin : mem_update_ff + if (cs == 1'b1) begin + if (we == 1'b1) begin + for (int j = 0; j < NDATA; j++) begin + for (int i = 0; i < DATA_SIZE/8; i++) begin + if (wbyteenable[j][i]) mem[addr][j][i*8 +: 8] <= wdata[j][i*8 +: 8]; + end + end + end else begin + rdata <= mem[addr]; + end + end + end + + // DPI + // {{{ +`ifdef HPDCACHE_DPI_ON + export "DPI-C" task publicSramBeSetMask; + export "DPI-C" task publicSramBeSetData; + + task automatic publicSramBeSetMask; + input int index; + input logic [NDATA-1:0][DATA_SIZE-1:0] mask; + mem[index] ^= mask; + endtask + + task automatic publicSramBeSetData; + input int index; + input logic [NDATA-1:0][DATA_SIZE-1:0] data; + mem[index] = data; + endtask +`endif + // }}} +endmodule +// vim: ts=4 : sts=4 : sw=4 : et : tw=100 : spell : spelllang=en diff --git a/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080.sv b/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080.sv deleted file mode 100644 index cd294ca9553..00000000000 --- a/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080.sv +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2023 CEA* - * *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA) - * - * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - * - * Licensed under the Solderpad Hardware License v 2.1 (the “License”); you - * may not use this file except in compliance with the License, or, at your - * option, the Apache License version 2.0. You may obtain a copy of the - * License at - * - * https://solderpad.org/licenses/SHL-2.1/ - * - * Unless required by applicable law or agreed to in writing, any work - * distributed under the License is distributed on an “AS IS” BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ -/* - * Authors : Cesar Fuguet - * Creation Date : March, 2020 - * Description : Behavioral model of a 1RW SRAM with write byte enable - * History : - */ -module hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080 - -#( - parameter int unsigned ADDR_SIZE = 7, - parameter int unsigned DATA_SIZE = 64, - parameter int unsigned DEPTH = 2**ADDR_SIZE -) -( - input logic clk, - input logic rst_n, - input logic cs, - input logic we, - input logic [ADDR_SIZE-1:0] addr, - input logic [DATA_SIZE-1:0] wdata, - input logic [DATA_SIZE/8-1:0] wbyteenable, - output logic [DATA_SIZE-1:0] rdata -); - - /* - * Internal memory array declaration - */ - typedef logic [DATA_SIZE-1:0] mem_t [DEPTH]; - mem_t mem; - - /* - * Process to update or read the memory array - */ - always_ff @(posedge clk) - begin : mem_update_ff - if (cs == 1'b1) begin - if (we == 1'b1) begin - for (int i = 0; i < DATA_SIZE/8; i++) begin - if (wbyteenable[i]) mem[addr][i*8 +: 8] <= wdata[i*8 +: 8]; - end - end - rdata <= mem[addr]; - end - end : mem_update_ff -endmodule : hpdcache_sram_wbyteenable_1rw_00000007_00000040_00000080 diff --git a/perf-model/README.md b/perf-model/README.md new file mode 100644 index 00000000000..8d8c1137288 --- /dev/null +++ b/perf-model/README.md @@ -0,0 +1,131 @@ +# CVA6 cycle-accurate performance model + +This repository contains a cycle-accurate performance model of CVA6 control-path. + +It was developed to explore microarchitecture changes in CVA6 before implementing them. + +To cite this model, please head to the end of this document. + + +## Getting started + +### Generate an RVFI trace + +To generate an RVFI trace, follow the instructions in the CVA6 repository to run a simulation. +The RVFI trace will be in `verif/sim/out_//.log`. + + +### Running the model + +```bash +python3 model.py verif/sim/out_//.log +``` + +The annotated trace is generated in an `annotated.log` file in the current directory. + +It prints a lot of debug information so that you can see all the events (note: it slows down model execution). +To disable these prints, modify the instantiation with `Model(debug=False)` in the `main` function. + +At the end of the simulation, the model prints statistics with the `print_stats` call in the `main` function. +These statistics can be performed on the timed part, which is filtered with the `filter_timed_part` function. +Feel free to modify the `filter_timed_part` function to suit your needs. + + +### Exploring design space + +In `model.py`, the `main` function runs the model with arguments which override default values. +Generic parameters are available in `Model.__init__`. +You can add new parameters to explore here. + +To perform exploration, run the model in a loop, like `issue_commit_graph` does. +The `display_scores` function is meant to print a 3D plot if you have `matplotlib`. +`issue_commit_graph` prints the scores so that you can store it and display the figure without re-running the model. + + +## Comparing the model and the RTL + +### Adapt RVFI trace generation + +The regular expression expects the cycle number to be in the RVFI trace. +The value is not used by the model but it is used to compare the model and CVA6. + +To emit cycle number in RVFI trace, modify `corev_apu/tb/rvfi_tracer.sv` in CVA6 repository as below. + +```diff +- $fwrite(f, "core 0: 0x%h (0x%h) DASM(%h)\n", +- pc64, rvfi_i[i].insn, rvfi_i[i].insn); ++ $fwrite(f, "core 0: 0x%h (0x%h) @%d DASM(%h)\n", ++ pc64, rvfi_i[i].insn, cycles, rvfi_i[i].insn); +``` + + +### Calculate instruction duration + +Run `cycle_diff.py` for each script. + +```bash +python3 perf-model/cycle_diff.py annotated.log +mv traceout.log model.log +python3 perf-model/cycle_diff.py verif/sim/out_//.log +``` + +Note: the `cycles_diff.py` script filters the "timed" part of the program. +To do this, it tries to find `csrr minstret` instructions. +Feel free to modify the script to suit your needs. + + +### List the differences + +```bash +diff -y traceout.log model.log | less +``` + +## RVFI-based Flamegraph Profiler + +This tool generates execution profile visualizations and performance metrics from CVA6 RISC-V trace logs. +The profiler processes RVFI traces with cycle number (cf Adapt RVFI trace generation) and produces two complementary flamegraph outputs: a standard cycle-attribution and an instruction-level breakdown variant. + +```bash +python perf-model/profile.py dumpfile.dump traceout.log svg_name.svg +``` + +**Parameters:** +- `dumpfile.dump`: ELF binary dump file (generated via `riscv-none-elf-objdump -h test_name.o`) +- `traceout.log`: RVFI execution trace file from CVA6 simulation +- `svg_name.svg`: Output flamegraph basename (generates `svg_name.svg` and `svg_name_with_ins.svg`) + +**Outputs:** +- `svg_name.svg`: Cycle-based flamegraph showing execution hotspots by cycle attribution +- `svg_name_with_ins.svg`: Instruction-level flamegraph with per-instruction cost breakdown + + +## Files + +| Name | Description | +| :--- | :--- | +| `cycle_diff.py` | Calculates duration of each instruction in an RVFI trace | +| `isa.py` | Module to create Python objects from RISC-V instructions | +| `model.py` | The CVA6 performance model | +| `profile.py` | RVFI-based flamegraph profiler | + + +## Citing + +```bibtex +@inproceedings{cf24, + author = {Allart, C\^{o}me and Coulon, Jean-Roch and Sintzoff, Andr\'{e} and Potin, Olivier and Rigaud, Jean-Baptiste}, + title = {Using a Performance Model to Implement a Superscalar CVA6}, + year = {2024}, + isbn = {9798400704925}, + publisher = {Association for Computing Machinery}, + url = {https://doi.org/10.1145/3637543.3652871}, + doi = {10.1145/3637543.3652871}, + abstract = {A performance model of CVA6 RISC-V processor is built to evaluate performance-related modifications before implementing them in RTL. Its accuracy is 99.2\% on CoreMark. This model is used to evaluate a superscalar feature for CVA6. During design phase, the model helped detecting and fixing performance bugs. The superscalar feature resulted in a CVA6 performance improvement of 40\% on CoreMark.}, + booktitle = {Proceedings of the 21st ACM International Conference on Computing Frontiers: Workshops and Special Sessions}, + pages = {43–46}, + numpages = {4}, + keywords = {CVA6, Cycle-Based Model, Multi-Issue, Performance, RISC-V, Superscalar}, + location = {Ischia, Italy}, + series = {CF '24 Companion} +} +``` diff --git a/perf-model/cycle_diff.py b/perf-model/cycle_diff.py new file mode 100644 index 00000000000..436c976aa6f --- /dev/null +++ b/perf-model/cycle_diff.py @@ -0,0 +1,80 @@ +# Copyright 2024 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Côme ALLART - Thales + +import re +import sys + +re_csrr_minstret = re.compile(r"^csrrs\s+\w+,\s*minstret\b") +re_full = re.compile( + r"([a-z]+)\s+0:\s*0x00000000([0-9a-f]+)\s*\(([0-9a-fx]+)\)\s*(\S*)@\s*([0-9]+)\s*(.*)" +) + +class Trace: + def __init__(self, addr, cycle, mnemo, flags): + self.addr = addr + self.cycle = cycle + self.mnemo = mnemo + self.flags = flags + self.delta = None + + def report(self): + """True if the instruction is a loading instruction""" + return f"+{self.delta} {self.flags} 0x{self.addr}: {self.mnemo}" + +def print_data(name, value): + "Prints 'name = data' with alignment of the '='" + spaces = ' ' * (24 - len(name)) + print(f"{name}{spaces} = {value}") + +def read_traces(input_file): + "Collect stage traces from file" + l = [] + def filter_add(trace): + if not hasattr(filter_add, "accepting"): + filter_add.accepting = False + if re_csrr_minstret.search(trace.mnemo): + filter_add.accepting = not filter_add.accepting + return + if filter_add.accepting: + l.append(trace) + with open(input_file, "r", encoding="utf8") as f: + for line in [l.strip() for l in f]: + found = re_full.search(line) + if found: + addr = found.group(2) + flags = found.group(4) + cycle = int(found.group(5)) + mnemo = found.group(6) + filter_add(Trace(addr, cycle, mnemo, flags)) + #l.append(Trace(addr, cycle, mnemo, flags)) + return l + +def write_traces(outfile, traces): + "Write all instructions to output file" + print("output file:", outfile) + with open(outfile, "w", encoding="utf8") as f: + for trace in traces: + f.write(trace.report() + "\n") + +def main(input_file: str): + "Main function" + traces = read_traces(input_file) + cycle = traces[0].cycle + cycle_number = traces[-1].cycle - cycle + 1 + for trace in traces: + trace.delta = trace.cycle - cycle + cycle = trace.cycle + print_data("cycle number", cycle_number) + print_data("Coremark/MHz", 1000000 / cycle_number) + print_data("instruction number", len(traces)) + print_data("IPC", len(traces) / cycle_number) + write_traces("traceout.log", traces) + +if __name__ == "__main__": + main(sys.argv[1]) diff --git a/perf-model/isa.py b/perf-model/isa.py new file mode 100644 index 00000000000..d0c35e83cf8 --- /dev/null +++ b/perf-model/isa.py @@ -0,0 +1,577 @@ +# Copyright 2024 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Côme ALLART - Thales + +""" +Represents the instruction set +""" + +from dataclasses import dataclass + +class Reg: + """Constants to represent registers""" + # ABI names + zero = 0 + ra = 1 + sp = 2 + gp = 3 + tp = 4 + t0 = 5 + t1 = 6 + t2 = 7 + s0 = 8 + fp = 8 + s1 = 9 + a0 = 10 + a1 = 11 + a2 = 12 + a3 = 13 + a4 = 14 + a5 = 15 + a6 = 16 + a7 = 17 + s2 = 18 + s3 = 19 + s4 = 20 + s5 = 21 + s6 = 22 + s7 = 23 + s8 = 24 + s9 = 25 + s10 = 26 + s11 = 27 + t3 = 28 + t4 = 29 + t5 = 30 + t6 = 31 + # Register names + x0 = 0 + x1 = 1 + x2 = 2 + x3 = 3 + x4 = 4 + x5 = 5 + x6 = 6 + x7 = 7 + x8 = 8 + x9 = 9 + x10 = 10 + x11 = 11 + x12 = 12 + x13 = 13 + x14 = 14 + x15 = 15 + x16 = 16 + x17 = 17 + x18 = 18 + x19 = 19 + x20 = 20 + x21 = 21 + x22 = 22 + x23 = 23 + x24 = 24 + x25 = 25 + x26 = 26 + x27 = 27 + x28 = 28 + x29 = 29 + x30 = 30 + x31 = 31 + +def sign_ext(imm, index, xlen=32): + """ + Sign extends a value + imm: value to sign extend + index: index of the sign bit of the value + len: target len for sign extended value + """ + imm_bits = index + 1 + assert (imm >> imm_bits) == 0 + neg = imm >> index + sext_bits = xlen - imm_bits + sext_ones = (1 << sext_bits) - 1 + sext = neg * sext_ones << imm_bits + return sext | imm + +@dataclass +class AddrFields: + """Represents the data used to build a memory address""" + base_reg: int + offset: int + +class Rtype: + """R-type instructions""" + def __init__(self, instr): + self.funct7 = instr.bin >> 25 + self.rs2 = (instr.bin >> 20) & 31 + self.rs1 = (instr.bin >> 15) & 31 + self.funct3 = (instr.bin >> 12) & 7 + self.rd = (instr.bin >> 7) & 31 + self.opcode = instr.bin & 63 + +class Itype: + """I-type instructions""" + def __init__(self, instr): + self.rs1 = (instr.bin >> 15) & 31 + self.funct3 = (instr.bin >> 12) & 7 + self.rd = (instr.bin >> 7) & 31 + self.opcode = instr.bin & 63 + self.imm = sign_ext(instr.bin >> 20, 11) + +class Stype: + """S-type instructions""" + def __init__(self, instr): + self.rs2 = (instr.bin >> 20) & 31 + self.rs1 = (instr.bin >> 15) & 31 + self.funct3 = (instr.bin >> 12) & 7 + self.opcode = instr.bin & 63 + self.imm = sign_ext( + ((instr.bin >> 25) << 5) \ + | ((instr.bin >> 7) & 31) + , 11) + +class Btype: + """B-type instructions""" + def __init__(self, instr): + self.rs2 = (instr.bin >> 20) & 31 + self.rs1 = (instr.bin >> 15) & 31 + self.funct3 = (instr.bin >> 12) & 7 + self.opcode = instr.bin & 63 + self.imm = sign_ext( + ((instr.bin >> 31) << 12) \ + | (((instr.bin >> 7) & 1) << 11) \ + | (((instr.bin >> 25) & 0x3f) << 5) \ + | (((instr.bin >> 8) & 15) << 1) + , 12) + +class Utype: + """U-type instructions""" + def __init__(self, instr): + self.imm_31_12 = instr.bin >> 12 + self.imm_4_0 = (instr.bin >> 7) & 31 + self.rd = (instr.bin >> 7) & 31 + self.opcode = instr.bin & 63 + self.imm = self.imm_31_12 << 12 + +class Jtype: + """J-type instructions""" + def __init__(self, instr): + self.rd = (instr.bin >> 7) & 31 + self.opcode = instr.bin & 63 + self.imm = sign_ext( + ((instr.bin >> 31) << 20) \ + | (((instr.bin >> 12) & 0xff) << 12) \ + | (((instr.bin >> 20) & 1) << 11) \ + | (((instr.bin >> 21) & 0x3ff) << 1) + , 20) + +class MOItype: + """Memory ordering instructions""" + def __init__(self, instr): + self.fm = instr.bin >> 28 + self.PI = (instr.bin >> 27) & 1 + self.PO = (instr.bin >> 26) & 1 + self.PR = (instr.bin >> 25) & 1 + self.PW = (instr.bin >> 24) & 1 + self.SI = (instr.bin >> 23) & 1 + self.SO = (instr.bin >> 22) & 1 + self.SR = (instr.bin >> 21) & 1 + self.SW = (instr.bin >> 20) & 1 + self.rs1 = (instr.bin >> 15) & 31 + self.funct3 = (instr.bin >> 12) & 7 + self.rd = (instr.bin >> 7) & 31 + self.opcode = instr.bin & 63 + +class CRtype: + """Compressed register""" + def __init__(self, instr): + self.funct4 = instr.bin >> 12 + r = (instr.bin >> 7) & 31 + self.rs2 = (instr.bin >> 2) & 31 + self.op = instr.bin & 3 + self.rs1 = r + base = instr.base() + if base == 'C.J[AL]R/C.MV/C.ADD': + if self.funct4 & 1: + if self.rs2 == 0: + if r == 0: + base = 'C.EBREAK' + else: + base = 'C.JALR' + else: + base = 'C.ADD' + else: + if self.rs2 == 0: + base = 'C.JR' + else: + base = 'C.MV' + if base in CRtype.regreg: + self.rd = r + self.name = base + + control = ['C.JR', 'C.JALR'] + regreg = ['C.MV', 'C.ADD'] + +class CItype: + """Compressed immediate""" + def __init__(self, instr): + self.funct3 = instr.bin >> 13 + r = (instr.bin >> 7) & 31 + self.op = instr.bin & 3 + base = instr.base() + if base == 'C.LUI/C.ADDI16SP': + if r == Reg.sp: + base = 'C.ADDI16SP' + else: + base = 'C.LUI' + if base in CItype.SPload + CItype.constgen: + self.rd = r + if base in CItype.SPload: + self.rs1 = Reg.sp + self.offset = CItype.offset[base](instr.bin) + # zero-extended offset + if base == 'C.LI': + self.imm = sign_ext(CItype.imm(instr.bin), 5) + if base == 'C.LUI': + self.nzimm = sign_ext(CItype.imm(instr.bin) << 12, 17) + if base in CItype.regimm: + self.rd = r + self.rs1 = r + if base == 'C.ADDI': + self.nzimm = sign_ext(CItype.imm(instr.bin), 5) + if base == 'C.ADDIW': + self.imm = sign_ext(CItype.imm(instr.bin), 5) + if base == 'C.ADDI16SP': + self.nzimm = sign_ext(CItype.immsp(instr.bin), 9) + if base == 'C.SLLI': + self.shamt = CItype.imm(instr.bin) + + SPload = ['C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP'] + constgen = ['C.LI', 'C.LUI'] + regimm = ['C.ADDI', 'C.ADDIW', 'C.ADDI16SP', 'C.SLLI'] + + Woffset = lambda i: (((i >> 12) & 1) << 5) | (((i >> 4) & 7) << 2) \ + | (((i >> 2) & 3) << 6) + Doffset = lambda i: (((i >> 12) & 1) << 5) | (((i >> 5) & 3) << 3) \ + | (((i >> 2) & 7) << 6) + Qoffset = lambda i: (((i >> 12) & 1) << 5) | (((i >> 6) & 1) << 4) \ + | (((i >> 2) & 15) << 6) + imm = lambda i: (((i >> 12) & 1) << 5) | ((i >> 2) & 31) + immsp = lambda i: (((i >> 12) & 1) << 9) | (((i >> 6) & 1) << 4) \ + | (((i >> 5) & 1) << 6) | (((i >> 3) & 3) << 7) \ + | (((i >> 2) & 1) << 5) + + offset = { + 'C.LWSP': Woffset, + 'C.LDSP': Doffset, + 'C.LQSP': Qoffset, + 'C.FLWSP': Woffset, + 'C.FLDSP': Doffset, + } + +class CSStype: + """Compressed stack-relative store""" + def __init__(self, instr): + self.funct3 = instr.bin >> 13 + self.rs1 = Reg.sp + self.rs2 = (instr.bin >> 2) & 31 + self.op = instr.bin & 3 + self.offset = CSStype.offset[instr.base()](instr.bin) + # zero-extended offset + + Woffset = lambda i: (((i >> 9) & 15) << 2) | (((i >> 7) & 3) << 6) + Doffset = lambda i: (((i >> 10) & 7) << 3) | (((i >> 7) & 7) << 6) + Qoffset = lambda i: (((i >> 11) & 3) << 4) | (((i >> 7) & 15) << 6) + + offset = { + 'C.SWSP': Woffset, + 'C.SDSP': Doffset, + 'C.SQSP': Qoffset, + 'C.FSWSP': Woffset, + 'C.FSDSP': Doffset, + } + +class CIWtype: + """Compressed wide immediate""" + def __init__(self, instr): + i = instr.bin + self.funct3 = i >> 13 + rd_ = (i >> 2) & 7 + self.rd = rd_ + 8 + self.op = i & 3 + self.nzuimm = (((i >> 11) & 3) << 4) | (((i >> 7) & 15) << 6) \ + | (((i >> 6) & 1) << 2) | (((i >> 5) & 1) << 3) + # zero-extended (unsigned) non-zero immediate + if instr.base() == 'C.ADDI4SPN': + self.rs1 = Reg.sp + +CLS_Woffset = lambda i: (((i >> 10) & 7) << 3) | (((i >> 6) & 1) << 2) \ + | (((i >> 5) & 1) << 6) +CLS_Doffset = lambda i: (((i >> 10) & 7) << 3) | (((i >> 5) & 3) << 6) +CLS_Qoffset = lambda i: (((i >> 11) & 3) << 4) | (((i >> 10) & 1) << 8) \ + | (((i >> 5) & 3) << 6) + +class CLtype: + """Compressed load""" + def __init__(self, instr): + self.funct3 = instr.bin >> 13 + rs1_ = (instr.bin >> 7) & 7 + rd_ = (instr.bin >> 2) & 7 + self.rs1 = rs1_ + 8 + self.rd = rd_ + 8 + self.op = instr.bin & 3 + self.offset = CLtype.offset[instr.base()](instr.bin) + # zero-extended offset + + offset = { + 'C.LW': CLS_Woffset, + 'C.LD': CLS_Doffset, + 'C.LQ': CLS_Qoffset, + 'C.FLW': CLS_Woffset, + 'C.FLD': CLS_Doffset, + } + +class CStype: + """Compressed store""" + def __init__(self, instr): + self.funct3 = instr.bin >> 13 + rs1_ = (instr.bin >> 7) & 7 + rs2_ = (instr.bin >> 2) & 7 + self.rs1 = rs1_ + 8 + self.rs2 = rs2_ + 8 + self.op = instr.bin & 3 + self.offset = CStype.offset[instr.base()](instr.bin) + # zero-extended offset + + offset = { + 'C.SW': CLS_Woffset, + 'C.SD': CLS_Doffset, + 'C.SQ': CLS_Qoffset, + 'C.FSW': CLS_Woffset, + 'C.FSD': CLS_Doffset, + } + +class CAtype: + """Compressed arithmetic""" + def __init__(self, instr): + self.funct6 = instr.bin >> 10 + r = (instr.bin >> 7) & 7 + self.rd = r + 8 + self.rs1 = r + 8 + self.funct2 = (instr.bin >> 5) & 3 + self.rs2 = ((instr.bin >> 2) & 7) + 8 + self.op = instr.bin & 3 + +class CBtype: + """Compressed branch""" + def __init__(self, instr): + i = instr.bin + base = instr.base() + self.funct3 = i >> 13 + self.offset = (i >> 10) & 7 + rs1_ = (i >> 7) & 7 + self.rs1 = rs1_ + 8 + self.op = instr.bin & 3 + if base in CBtype.branch: + self.offset = sign_ext( + (((i >> 12) & 1) << 8) \ + | (((i >> 10) & 3) << 3) \ + | (((i >> 5) & 3) << 6) \ + | (((i >> 3) & 3) << 1) \ + | (((i >> 2) & 1) << 5) + , 8) + else: + if (instr.bin >> 10) & 3 == 2: + self.shamt = sign_ext(CItype.imm(i), 5) + else: + self.shamt = CItype.imm(i) + self.rd = self.rs1 + + branch = ['C.BEQZ', 'C.BNEZ'] + regimm = ['C.SRLI', 'C.SRAI', 'C.ANDI'] + +class CJtype: + """Compressed jump""" + def __init__(self, instr): + self.funct3 = instr.bin >> 13 + assert instr.base() in ['C.J', 'C.JAL'] + self.offset = sign_ext(CJtype.offset(instr.bin), 11) + self.jump_target = (instr.bin >> 2) & 0x7ff + self.op = instr.bin & 3 + + offset = lambda i: (((i >> 12) & 1) << 11) | (((i << 11) & 1) << 4) \ + | (((i >> 9) & 3) << 8) | (((i >> 8) & 1) << 10) \ + | (((i >> 7) & 1) << 6) | (((i >> 6) & 1) << 7) \ + | (((i >> 3) & 1) << 1) | (((i >> 2) & 1) << 5) + +class Instr: + """Instructions""" + + table_16_4_RV32 = [ + ['C.ADDI4SPN', 'C.FLD', 'C.LW', 'C.FLW', + 'Reserved', 'C.FSD', 'C.SW', 'C.FSW'], + ['C.ADDI', 'C.JAL', 'C.LI', 'C.LUI/C.ADDI16SP', + 'MISC-ALU', 'C.J', 'C.BEQZ', 'C.BNEZ'], + ['C.SLLI', 'C.FLDSP', 'C.LWSP', 'C.FLWSP', + 'C.J[AL]R/C.MV/C.ADD', 'C.FSDSP', 'C.SWSP', 'C.FSWSP'], + ] + + table_24_1 = [ + ['LOAD', 'LOAD-FP', 'custom-0', 'MISC-MEM', 'OP-IMM', 'AUIPC', 'OP-IMM-32', '48b'], + ['STORE', 'STORE-FP', 'custom-1', 'AMO', 'OP', 'LUI', 'OP-32', '64b'], + ['MADD', 'MSUB', 'NMSUB', 'NMADD', 'OP-FP', 'reserved', 'custom-2/rv128', '48b'], + ['BRANCH', 'JALR', 'reserved', 'JAL', 'SYSTEM', 'reserved', 'custom-3/rv128', '80b'], + ] + type_of_base = { + 'OP-IMM': Itype, + 'LUI': Utype, + 'AUIPC': Utype, + 'OP': Rtype, + 'OP-32': Rtype, + 'JAL': Jtype, + 'JALR': Itype, + 'BRANCH': Btype, + 'LOAD': Itype, + 'STORE': Stype, + 'SYSTEM': Itype, + 'C.LWSP': CItype, + 'C.LDSP': CItype, + 'C.LQSP': CItype, + 'C.FLWSP': CItype, + 'C.FLDSP': CItype, + 'C.SWSP': CSStype, + 'C.SDSP': CSStype, + 'C.SQSP': CSStype, + 'C.FSWSP': CSStype, + 'C.FSDSP': CSStype, + 'C.LW': CLtype, + 'C.LD': CLtype, + 'C.LQ': CLtype, + 'C.FLW': CLtype, + 'C.FLD': CLtype, + 'C.SW': CStype, + 'C.SD': CStype, + 'C.SQ': CStype, + 'C.FSW': CStype, + 'C.FSD': CStype, + 'C.J': CJtype, + 'C.JAL': CJtype, + 'C.J[AL]R/C.MV/C.ADD': CRtype, + 'C.BEQZ': CBtype, + 'C.BNEZ': CBtype, + 'C.LI': CItype, + 'C.LUI/C.ADDI16SP': CItype, + 'C.ADDI': CItype, + 'C.ADDIW': CItype, + 'C.ADDI4SPN': CIWtype, + 'C.SLLI': CItype, + 'MISC-ALU': lambda instr: CAtype(instr) if (instr.bin >> 10) & 3 == 3 else CBtype(instr), + } + iloads = ['C.LW', 'C.LWSP', 'LOAD'] + floads = ['C.FLD', 'C.FLW', 'C.FLDSP', 'C.FLWSP', 'LOAD-FP'] + istores = ['C.SW', 'C.SWSP', 'STORE'] + fstores = ['C.FSD', 'C.FSW', 'C.FSDSP', 'C.FSWSP', 'STORE-FP'] + loads = iloads + floads + stores = istores + fstores + + def __init__(self, bincode): + self.bin = bincode + self.inst_1_0 = self.bin & 3 + + def base(self): + """Get the name of the base instruction""" + result = "" + if self.is_compressed(): + line = self.bin & 3 + col = (self.bin >> 13) & 7 + result = Instr.table_16_4_RV32[line][col] + else: + line = (self.bin >> 5) & 3 + col = (self.bin >> 2) & 7 + result = Instr.table_24_1[line][col] + return result + + def fields(self): + """Get an object with the fields of the instruction""" + return Instr.type_of_base[self.base()](self) + + def is_compressed(self): + """Is the instruction from the C extension?""" + return (self.bin & 3) < 3 + + def size(self): + """Size of the instruction in bytes""" + return 2 if self.is_compressed() else 4 + + def is_load(self): + """Is the instruction a load?""" + return self.base() in Instr.loads + + def is_store(self): + """Is the instruction a store?""" + return self.base() in Instr.stores + + def is_branch(self): + """Is it a taken/not taken branch?""" + return self.base() in ['C.BEQZ', 'C.BNEZ', 'BRANCH'] + + def is_regjump(self): + """Is it a register jump?""" + if self.base() in ['JALR']: + return True + if self.base() == 'C.J[AL]R/C.MV/C.ADD': + return self.fields().name in ['C.JALR', 'C.JR'] + return False + + def is_jump(self): + """Is it an immediate jump?""" + return self.base() in ['JAL', 'C.JAL', 'C.J'] + + def is_muldiv(self): + """Is it a muldiv instruction?""" + if self.base() not in ['OP', 'OP-32']: + return False + f = self.fields() + return f.funct7 == 1 or (f.funct7 == 5 and f.funct3 in [1, 3]) + + def offset(self): + """Get offset from instr (sometimes it is just 'imm' in RISCV spec)""" + fields = self.fields() + return fields.offset if hasattr(fields, 'offset') else fields.imm + + def addr_fields(self): + """Get the register and offset to build an address""" + return AddrFields(self.fields().rs1, self.offset()) + + def has_WAW_from(self, other): + """b.has_WAW_from(a) if a.rd == b.rd""" + a = other.fields() + b = self.fields() + if not (hasattr(a, 'rd') and hasattr(b, 'rd')): + return False + return a.rd == b.rd and a.rd != Reg.zero + + def has_RAW_from(self, other): + """b.has_RAW_from(a) if b.rsX == a.rd""" + a = other.fields() + b = self.fields() + if not hasattr(a, 'rd') or a.rd == Reg.zero: + return False + if hasattr(b, 'rs1') and a.rd == b.rs1: + return True + return hasattr(b, 'rs2') and a.rd == b.rs2 + + def has_WAR_from(self, other): + """b.has_WAR_from(a) if b.rd == a.rsX""" + a = other.fields() + b = self.fields() + if not hasattr(b, 'rd') or b.rd == Reg.zero: + return False + if hasattr(a, 'rs1') and a.rs1 == b.rd: + return True + return hasattr(a, 'rs2') and a.rs2 == b.rd diff --git a/perf-model/model.py b/perf-model/model.py new file mode 100644 index 00000000000..e1f2f61941e --- /dev/null +++ b/perf-model/model.py @@ -0,0 +1,668 @@ +# Copyright 2024 Thales Silicon Security +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Côme ALLART - Thales + +""" +Performance model of the cva6 +""" + +import sys +import re + +from dataclasses import dataclass +from enum import Enum +from collections import defaultdict + +#from matplotlib import pyplot as plt + +from isa import Instr, Reg + +EventKind = Enum('EventKind', [ + 'WAW', 'WAR', 'RAW', + 'BMISS', 'BHIT', + 'STRUCT', + 'issue', 'done', 'commit', +]) + +def to_signed(value, xlen=32): + signed = value + if signed >> (xlen - 1): + signed -= 1 << xlen + return signed + +class Event: + """Represents an event on an instruction""" + def __init__(self, kind, cycle): + self.kind = kind + self.cycle = cycle + + def __repr__(self): + return f"@{self.cycle}: {self.kind}" + +class Instruction(Instr): + """Represents a RISC-V instruction with annotations""" + + def __init__(self, line, address, hex_code, mnemo): + Instr.__init__(self, int(hex_code, base=16)) + self.line = line + self.address = int(address, base=16) + self.hex_code = hex_code + self.mnemo = mnemo + self.events = [] + + def mnemo_name(self): + """The name of the instruction (fisrt word of the mnemo)""" + return self.mnemo.split()[0] + + def next_addr(self): + """Address of next instruction""" + return self.address + self.size() + + _ret_regs = [Reg.ra, Reg.t0] + + def is_ret(self): + "Does CVA6 consider this instruction as a ret?" + f = self.fields() + # Strange conditions, no imm check, no rd-discard check + return self.is_regjump() \ + and f.rs1 in Instruction._ret_regs \ + and (self.is_compressed() or f.rs1 != f.rd) + + def is_call(self): + "Does CVA6 consider this instruction as a ret?" + base = self.base() + f = self.fields() + return base == 'C.JAL' \ + or base == 'C.J[AL]R/C.MV/C.ADD' and f.name == 'C.JALR' \ + or base in ['JAL', 'JALR'] and f.rd in Instruction._ret_regs + + def __repr__(self): + return self.mnemo + +@dataclass +class Entry: + """A scoreboard entry""" + instr: Instruction + cycles_since_issue = 0 + done: bool = False + + def __repr__(self): + status = "DONE" if self.done else "WIP " + addr = f"0x{self.instr.address:08X}" + return f"{status} {addr}:`{self.instr}` for {self.cycles_since_issue}" + +@dataclass +class LastIssue: + """To store the last issued instruction""" + instr: Instruction + issue_cycle: int + +class IqLen: + """Model of the instruction queue with only a size counter""" + def __init__(self, fetch_size, debug=False): + self.fetch_size = 4 + while self.fetch_size < fetch_size: + self.fetch_size <<= 1 + self.debug = debug + self.len = self.fetch_size + self.new_fetch = True + + def fetch(self): + """Fetch bytes""" + self.len += self.fetch_size + self._debug(f"fetched {self.fetch_size}, got {self.len}") + self.new_fetch = True + + def flush(self): + """Flush instruction queue (bmiss or exception)""" + self.len = 0 + self._debug(f"flushed, got {self.len}") + self.new_fetch = False + + def jump(self): + """Loose a fetch cycle and truncate (jump, branch hit taken)""" + if self.new_fetch: + self.len -= self.fetch_size + self._debug(f"jumping, removed {self.fetch_size}, got {self.len}") + self.new_fetch = False + self._truncate() + self._debug(f"jumped, got {self.len}") + + def has(self, instr): + """Does the instruction queue have this instruction?""" + length = self.len + if self._is_crossword(instr): + length -= (self.fetch_size - 2) + self._debug(f"comparing {length} to {instr.size()} ({instr})") + return length >= instr.size() + + def remove(self, instr): + """Remove instruction from queue""" + self.len -= instr.size() + self._debug(f"removed {instr.size()}, got {self.len}") + self._truncate(self._addr_index(instr.next_addr())) + if instr.is_jump(): + self.jump() + + def _addr_index(self, addr): + return addr & (self.fetch_size - 1) + + def _is_crossword(self, instr): + is_last = self._addr_index(instr.address) == self.fetch_size - 2 + return is_last and not instr.is_compressed() + + def _truncate(self, index=0): + occupancy = self.fetch_size - self._addr_index(self.len) + to_remove = index - occupancy + if to_remove < 0: + to_remove += self.fetch_size + self.len -= to_remove + self._debug(f"truncated, removed {to_remove}, got {self.len}") + + def _debug(self, message): + if self.debug: + print(f"iq: {message}") + +class Ras: + "Return Address Stack" + def __init__(self, depth=2, debug=False): + self.depth = depth - 1 + self.stack = [] + self.debug = debug + self.last_dropped = None + + def push(self, addr): + "Push an address on the stack, forget oldest entry if full" + self.stack.append(addr) + self._debug(f"pushed 0x{addr:08X}") + if len(self.stack) > self.depth: + self.stack.pop(0) + self._debug("overflown") + + def drop(self): + "Drop an address from the stack" + self._debug("dropping") + if len(self.stack) > 0: + self.last_dropped = self.stack.pop() + else: + self.last_dropped = None + self._debug("was already empty") + + def read(self): + "Read the top of the stack without modifying it" + self._debug("reading") + if self.last_dropped is not None: + addr = self.last_dropped + self._debug(f"read 0x{addr:08X}") + return addr + self._debug("was empty") + return None + + def resolve(self, instr): + "Push or pop depending on the instruction" + self._debug(f"issuing {instr}") + if instr.is_ret(): + self._debug("detected ret") + self.drop() + if instr.is_call(): + self._debug("detected call") + self.push(instr.next_addr()) + + def _debug(self, message): + if self.debug: + print(f"RAS: {message}") + +class Bht: + "Branch History Table" + + @dataclass + class Entry: + "A BTB entry" + valid: bool = False + sat_counter: int = 0 + + def __init__(self, entries=128): + self.contents = [Bht.Entry() for _ in range(entries)] + + def predict(self, addr): + "Is the branch taken? None if don't know" + entry = self.contents[self._index(addr)] + if entry.valid: + return entry.sat_counter >= 2 + return None + + def resolve(self, addr, taken): + "Update branch prediction" + index = self._index(addr) + entry = self.contents[index] + entry.valid = True + if taken: + if entry.sat_counter < 3: + entry.sat_counter += 1 + else: + if entry.sat_counter > 0: + entry.sat_counter -= 1 + + def _index(self, addr): + return (addr >> 1) % len(self.contents) + +Fu = Enum('Fu', ['ALU', 'MUL', 'BRANCH', 'LDU', 'STU']) + +# We have +# - FLU gathering ALU + BRANCH (+ CSR, not significant in CoreMark) +# - LSU for loads and stores +# - FP gathering MUL + second ALU (+ Floating, unused in CoreMark) +# This way we do not have more write-back ports than currently with F + +def to_fu(instr): + if instr.is_branch() or instr.is_jump() or instr.is_regjump(): + return Fu.BRANCH + if instr.is_muldiv(): + return Fu.MUL + if instr.is_load(): + return Fu.LDU + if instr.is_store(): + return Fu.STU + return Fu.ALU + +class FusBusy: + "Is each functional unit busy" + def __init__(self, has_alu2 = False): + self.has_alu2 = has_alu2 + + self.alu = False + self.mul = False + self.branch = False + self.ldu = False + self.stu = False + self.alu2 = False + + self.issued_mul = False + + def _alu2_ready(self): + return self.has_alu2 and not self.alu2 + + def is_ready(self, fu): + return { + Fu.ALU: self._alu2_ready() or not self.alu, + Fu.MUL: not self.mul, + Fu.BRANCH: not self.branch, + Fu.LDU: not self.ldu, + Fu.STU: not self.stu, + }[fu] + + def is_ready_for(self, instr): + return self.is_ready(to_fu(instr)) + + def issue(self, instr): + return { + Fu.ALU: FusBusy.issue_alu, + Fu.MUL: FusBusy.issue_mul, + Fu.BRANCH: FusBusy.issue_branch, + Fu.LDU: FusBusy.issue_ldu, + Fu.STU: FusBusy.issue_stu, + }[to_fu(instr)](self) + + def issue_mul(self): + self.mul = True + self.issued_mul = True + + def issue_alu(self): + if not self._alu2_ready(): + assert not self.alu + self.alu = True + self.branch = True + else: + self.alu2 = True + + def issue_branch(self): + self.alu = True + self.branch = True + # Stores are not allowed yet + self.stu = True + + def issue_ldu(self): + self.ldu = True + self.stu = True + + def issue_stu(self): + self.stu = True + self.ldu = True + + def cycle(self): + self.alu = self.issued_mul + self.mul = False + self.branch = self.issued_mul + self.ldu = False + self.stu = False + self.alu2 = False + self.issued_mul = False + +class Model: + """Models the scheduling of CVA6""" + + re_instr = re.compile( + r"([a-z]+)\s+0:\s*0x0*([0-9a-f]+)\s*\(([0-9a-fx]+)\)\s*(@\s*[0-9]+)?\s*(.*)" + ) + + def __init__( + self, + debug=False, + issue=1, + commit=2, + sb_len=8, + fetch_size=None, + has_forwarding=True, + has_renaming=True): + self.ras = Ras(debug=debug) + self.bht = Bht() + self.instr_queue = [] + self.scoreboard = [] + self.fus = FusBusy(issue > 1) + self.last_issued = None + self.last_committed = None + self.retired = [] + self.sb_len = sb_len + self.debug = debug + self.iqlen = IqLen(fetch_size or 4 * issue, debug) + self.issue_width = issue + self.commit_width = commit + self.has_forwarding = has_forwarding + self.has_renaming = has_renaming + self.log = [] + + def log_event_on(self, instr, kind, cycle): + """Log an event on the instruction""" + if self.debug: + print(f"{instr}: {kind}") + event = Event(kind, cycle) + instr.events.append(event) + self.log.append((event, instr)) + + def predict_branch(self, instr): + """Predict if branch is taken or not""" + pred = self.bht.predict(instr.address) + if pred is not None: + return pred + return instr.offset() >> 31 != 0 + + def predict_regjump(self, instr): + """Predict destination address of indirect jump""" + if instr.is_ret(): + return self.ras.read() or 0 + return 0 # always miss, as there is no btb yet + + def predict_pc(self, last): + """Predict next program counter depending on last issued instruction""" + if last.is_branch(): + taken = self.predict_branch(last) + offset = to_signed(last.offset()) if taken else last.size() + return last.address + offset + if last.is_regjump(): + return self.predict_regjump(last) + return None + + def issue_manage_last_branch(self, instr, cycle): + """Flush IQ if branch miss, jump if branch hit""" + if self.last_issued is not None: + last = self.last_issued.instr + pred = self.predict_pc(last) + if pred is not None: + bmiss = pred != instr.address + resolved = cycle >= self.last_issued.issue_cycle + 6 + if bmiss and not resolved: + self.iqlen.flush() + branch = EventKind.BMISS if bmiss else EventKind.BHIT + if branch not in [e.kind for e in instr.events]: + self.log_event_on(instr, branch, cycle) + taken = instr.address != last.next_addr() + if taken and not bmiss: + # last (not instr) was like a jump + self.iqlen.jump() + + def commit_manage_last_branch(self, instr, cycle): + "Resolve branch prediction" + if self.last_committed is not None: + last = self.last_committed + if last.is_branch(): + taken = instr.address != last.next_addr() + self.bht.resolve(last.address, taken) + self.last_committed = instr + + def find_data_hazards(self, instr, cycle): + """Detect and log data hazards""" + found = False + for entry in self.scoreboard: + if instr.has_WAW_from(entry.instr) and not self.has_renaming: + self.log_event_on(instr, EventKind.WAW, cycle) + found = True + can_forward = self.has_forwarding and entry.done + if instr.has_RAW_from(entry.instr) and not can_forward: + self.log_event_on(instr, EventKind.RAW, cycle) + found = True + return found + + def find_structural_hazard(self, instr, cycle): + """Detect and log structural hazards""" + if not self.fus.is_ready_for(instr): + self.log_event_on(instr, EventKind.STRUCT, cycle) + return True + return False + + def try_issue(self, cycle): + """Try to issue an instruction""" + if len(self.instr_queue) == 0 or len(self.scoreboard) >= self.sb_len: + return + can_issue = True + instr = self.instr_queue[0] + if self.find_data_hazards(instr, cycle): + can_issue = False + if self.find_structural_hazard(instr, cycle): + can_issue = False + self.issue_manage_last_branch(instr, cycle) + if not self.iqlen.has(instr): + can_issue = False + if can_issue: + self.iqlen.remove(instr) + instr = self.instr_queue.pop(0) + self.log_event_on(instr, EventKind.issue, cycle) + entry = Entry(instr) + self.scoreboard.append(entry) + self.fus.issue(instr) + self.last_issued = LastIssue(instr, cycle) + self.ras.resolve(instr) + + def try_execute(self, cycle): + """Try to execute instructions""" + for entry in self.scoreboard: + entry.cycles_since_issue += 1 + instr = entry.instr + duration = 1 + if instr.is_load() or instr.is_store(): + duration = 2 + if instr.is_muldiv(): + duration = 2 + if entry.cycles_since_issue == duration: + self.log_event_on(instr, EventKind.done, cycle) + entry.done = True + + def try_commit(self, cycle, commit_port): + """Try to commit an instruction""" + if len(self.scoreboard) == 0: + return + entry = self.scoreboard[0] + can_commit = True + if commit_port > 0: + if entry.instr.is_store(): + can_commit = False + if not entry.done: + can_commit = False + if can_commit: + instr = self.scoreboard.pop(0).instr + self.log_event_on(instr, EventKind.commit, cycle) + self.retired.append(instr) + self.commit_manage_last_branch(instr, cycle) + + def run_cycle(self, cycle): + """Runs a cycle""" + self.fus.cycle() + for commit_port in range(self.commit_width): + self.try_commit(cycle, commit_port) + self.try_execute(cycle) + for _ in range(self.issue_width): + self.try_issue(cycle) + self.iqlen.fetch() + + def load_file(self, path): + """Fill a model from a trace file""" + with open(path, "r", encoding="utf8") as file: + for line in [l.strip() for l in file]: + found = Model.re_instr.search(line) + if found: + address = found.group(2) + hex_code = found.group(3) + mnemo = found.group(5) + instr = Instruction(line, address, hex_code, mnemo) + self.instr_queue.append(instr) + + def run(self, cycles=None): + """Run until completion""" + cycle = 0 + while len(self.instr_queue) > 0 or len(self.scoreboard) > 0: + self.run_cycle(cycle) + if self.debug: + print(f"Scoreboard @{cycle}") + for entry in self.scoreboard: + print(f" {entry}") + print(f"iqlen = {self.iqlen.len}") + print() + cycle += 1 + + if cycles is not None and cycle > cycles: + break + return cycle + +def write_trace(output_file, instructions): + """Write cycle-annotated trace""" + pattern = re.compile(r"\)\s*(@\s*[0-9]+)? ") + + lines = [] + for instr in instructions: + commit_event = instr.events[-1] + assert commit_event.kind == EventKind.commit + cycle = commit_event.cycle + annotated = re.sub(pattern, f") @ {cycle} ", instr.line) + #if EventKind.STRUCT in [e.kind for e in instr.events]: + # annotated += " #STRUCT" + #if EventKind.RAW in [e.kind for e in instr.events]: + # annotated += " #RAW" + lines.append(f"{annotated}\n") + + with open(output_file, 'w') as f: + f.writelines(lines) + +def print_data(name, value, ts=24, sep='='): + "Prints 'name = data' with alignment of the '='" + + spaces = ' ' * (ts - len(name)) + print(f"{name}{spaces} {sep} {value}") + +def display_scores(scores): + """Display a 3D graph of scores against commit/issue-wide""" + bars = [] + for x, l in enumerate(scores): + for y, z in enumerate(l): + bars.append((x, y, z)) + + x, y, z, dx, dy, dz = [], [], [], [], [], [] + for bx, by, bz in bars: + x.append(bx) + y.append(by) + z.append(0) + dx.append(.5) + dy.append(.5) + dz.append(bz) + + #fig = plt.figure() + #ax1 = fig.add_subplot(111, projection='3d') + #ax1.bar3d(x, y, z, dx, dy, dz) + #ax1.set_xlabel("issue") + #ax1.set_ylabel("commit") + #ax1.set_zlabel("CoreMark/MHz") + #plt.show() + +def issue_commit_graph(input_file, n = 3): + """Plot the issue/commit graph""" + + r = range(n + 1) + scores = [[0 for _ in r] for _ in r] + + if input_file is None: + scores = [[0, 0, 0, 0, 0, 0], [0, 2.651936045910317, 2.651936045910317, 2.651936045910317, 2.651936045910317, 2.651936045910317], [0, 3.212779150348426, 3.6292766488711137, 3.6292766488711137, 3.6292766488711137, 3.6292766488711137], [0, 3.2550388000624966, 3.900216852056974, 3.914997572701505, 3.914997572701505, 3.914997572701505], [0, 3.2596436557555526, 3.9257869239889134, 3.9420984578510834, 3.9421606193922765, 3.9421606193922765], [0, 3.260695897718491, 3.944757614368385, 3.9623576027736505, 3.9625460150656, 3.9625460150656]] # pylint: disable=line-too-long + else: + r = range(1, n + 1) + for issue in r: + for commit in r: + print("running", issue, commit) + model = Model(issue=issue, commit=commit) + model.load_file(input_file) + model.run() + n_cycles = count_cycles(filter_timed_part(model.retired)) + score = 1000000 / n_cycles + scores[issue][commit] = score + print(scores) + display_scores(scores) + +def filter_timed_part(all_instructions): + "Keep only timed part from a trace" + filtered = [] + re_csrr_minstret = re.compile(r"^csrrs\s+\w+,\s*minstret\b") + accepting = False + for instr in all_instructions: + if re_csrr_minstret.search(instr.mnemo): + accepting = not accepting + continue + if accepting: + filtered.append(instr) + return filtered + +def count_cycles(retired): + start = min(e.cycle for e in retired[0].events) + end = max(e.cycle for e in retired[-1].events) + return end - start + +def print_stats(instructions): + ecount = defaultdict(lambda: 0) + + for instr in instructions: + for e in instr.events: + ecount[e.kind] += 1 + cycle = e.cycle + n_instr = len(instructions) + n_cycles = count_cycles(instructions) + + print_data("cycle number", n_cycles) + print_data("Coremark/MHz", 1000000 / n_cycles) + print_data("instruction number", n_instr) + for ek, count in ecount.items(): + print_data(f"{ek}/instr", f"{100 * count / n_instr:.2f}%") + +def main(input_file: str): + "Entry point" + + model = Model(debug=True, issue=2, commit=2) + model.load_file(input_file) + model.run() + + write_trace('annotated.log', model.retired) + + #print_stats(filter_timed_part(model.retired)) + print_stats(model.retired) + +if __name__ == "__main__": + main(sys.argv[1]) diff --git a/perf-model/profile.py b/perf-model/profile.py new file mode 100644 index 00000000000..9b53a639b52 --- /dev/null +++ b/perf-model/profile.py @@ -0,0 +1,310 @@ +from dataclasses import dataclass +import subprocess +import sys +import re + +import flameprof + +import isa + +re_instr = re.compile( + r"([a-z]+)\s+0:\s*0x00000000([0-9a-f]+)\s*\(([0-9a-fx]+)\)\s*@\s*([0-9]+)\s*(.*)" +) +re_mem = re.compile(r"mem\s*0x([0-9a-f]+)") + +@dataclass +class AsmFunc: + index: int + name: str + size: int + vma: int + lma: int + file_off: int + align: int + + def start_addr(self): + return self.vma + + def end_addr(self): + return self.vma + self.size + + def contains(self, addr): + return self.start_addr() <= addr and addr < self.end_addr() + + def load_elf(path): + with open(path, "r", encoding="utf8") as f: + lines = f.readlines() + return [AsmFunc._from_line(l.split()) for l in lines if ".text." in l] + + def _from_line(line): + return AsmFunc( + index = int(line[0]), + name = line[1][6:], + size = int(line[2], 16), + vma = int(line[3], 16), + lma = int(line[4], 16), + file_off = int(line[5], 16), + align = int(line[6][3:], 16), + ) + +@dataclass +class RvfiInstr: + def __init__(self, address, cycle, op, name, line, next_line=None): + self.address = address + self.cycle = cycle + self.op = isa.Instr(op) + self.line = line + self.name = name + self.mem_address = None + if self.op.is_load() or self.op.is_store(): + assert(next_line is not None) + self.mem_address = int(re_mem.search(next_line).group(1), 16) + + def load_trace(path): + with open(path, "r", encoding="utf8") as f: + lines = f.readlines() + return RvfiInstr._from_lines(lines) + + def _from_lines(lines): + instrs = [] + for i, l in enumerate(lines): + line = l.strip() + found = re_instr.search(line) + if found: + instr = RvfiInstr( + address = int(found.group(2), 16), + cycle = int(found.group(4)), + op = int(found.group(3), 16), + line = line, + name = found.group(5).split(" ")[0], + next_line = lines[i+1] if i + 1 < len(lines) else None, + ) + instrs.append(instr) + return instrs + +class CallStack: + def __init__(self, functions): + self.stack = [] + self.fns = { f.start_addr(): f for f in functions } + + def run(self, instr): + addr = instr.address + + f = self.fns.get(addr) + if f: + e = RawEvent(stack=self.stack_names(), cycle=instr.cycle) + self.stack.append(f) + return e + + if len(self.stack) > 0: + curr = self.stack[-1] + if not curr.contains(addr) and any(f.contains(addr) for f in self.fns.values()): + e = RawEvent(stack=self.stack_names(), cycle=instr.cycle) + self.stack.pop() + return e + + return None + + def stack_names(self): + return [f.name for f in self.stack] + +@dataclass +class RawEvent: + stack: list + cycle: int + +@dataclass +class Event: + stack: list + instr: RvfiInstr + duration: int + icount: int + executed_ins : dict + +def run_all(fns, instrs): + events = [] + cs = CallStack(fns) + last_event_cycle = 0 + last_event_i = 0 + last_instr_cycle = 0 + executed_ins = {} + + for i, instr in enumerate(instrs): + count, tot_duration = executed_ins.get(instr.name, (0, 0)) + count += 1 + tot_duration += instr.cycle - last_instr_cycle + executed_ins[instr.name] = count, tot_duration + last_instr_cycle = instr.cycle + + event = cs.run(instr) + if event: + events.append(Event( + stack = event.stack, + instr = instr, + duration = event.cycle - last_event_cycle, + icount = i - last_event_i, + executed_ins = executed_ins, + )) + last_event_cycle = event.cycle + last_event_i = i + executed_ins = {} + + return events + +def fake_file(func): + return ("", 1, func) + +class Stat: + def __init__(self): + self.cc = 0 + self.nc = 0 + self.tt = 0 + self.ct = 0 + self.icount = 0 + self.callers = {} + + def ipc(self): + return self.icount / self.tt if self.tt > 0 else 0.0 + + def build(self): + callers = { fake_file(func): t for func, t in self.callers.items() } + return (self.cc, self.nc, self.tt, self.ct, callers) + + def add_caller(self, caller, c_cc, c_nc, c_tt, c_ct): + (cc, nc, tt, ct) = self.callers[caller] if caller in self.callers else \ + (0, 0, 0, 0) + + cc += c_cc + nc += c_nc + tt += c_tt + ct += c_ct + + self.callers[caller] = (cc, nc, tt, ct) + +def put_stat(d, name): + if not name in d: + d[name] = Stat() + +def build_stats(events, inst_analysis=False): + stats = {} + last_stack = [] + + for event in events: + if len(event.stack) == 0: + continue + stack = event.stack + # Current function, in the which event.duration has been spent + func = stack[-1] + put_stat(stats, func) + # All time is spent inside instructions + duration = 0 if inst_analysis else event.duration + + if inst_analysis: + for instr_name, (count, d) in event.executed_ins.items(): + put_stat(stats, instr_name) + stats[instr_name].tt += d + stats[instr_name].ct += d + stats[instr_name].add_caller(func, 0, count, d, d) + + # Spent duration right into func + stats[func].tt += duration + stats[func].icount += event.icount + + # Spent duration in func and its parents + for f in stack: + stats[f].ct += event.duration + + # Spent duration while being called directly by caller + if len(stack) > 1: + caller = stack[-2] + stats[func].add_caller(caller, 0, 0, duration, 0) + + # Each function in the call stack spent duration called by its caller + for i, callee in enumerate(stack): + if i > 0: + caller = stack[i - 1] + stats[callee].add_caller(caller, 0, 0, 0, event.duration) + + if len(event.stack) >= len(last_stack): + # Make sure it is a call + assert len(event.stack) == len(last_stack) + 1 + else: + # Make sure it is a ret + assert len(event.stack) == len(last_stack) - 1 + + callee = last_stack[-1] + caller = func + put_stat(stats, caller) + + # The caller called the callee once + # It is not a prim call if the callee was already in the stack. + c_cc = 1 if not callee in event.stack else 0 + stats[callee].add_caller(caller, c_cc, 1, 0, 0) + stats[callee].cc += c_cc + stats[callee].nc += 1 + + last_stack = stack + + return stats + + #{ func: (cc, nc, tt, ct, callers) } + # func = file_name, line_number, func_name + # cc = prim_calls = number of calls if not already in call stack (non-recurse calls)? + # nc = number of calls + # tt = tottime = time spent in this function alone (not callees) + # ct = cumtime = time spent in the function plus all functions that this function called + # callers/clist = { cfunc: t } = { name: (cc, nc, tt, ct) } + +def format_stack_change(old_stack, new_stack): + if len(old_stack) > len(new_stack): + return f"RET FROM {old_stack[-1]} (in {new_stack})" + if len(new_stack) > len(old_stack): + return f"CALL {new_stack[-1]} (in {old_stack})" + return None + +def render(stats, svg_path, threshold=0): + stats = { fake_file(func): stat.build() for func, stat in stats.items() } + + with open(svg_path, 'w') as f: + flameprof.render(stats, f, width=3000, threshold=threshold) + +def filter_events(events, func_name): + return [e for e in events if func_name not in e.stack] + +if __name__ == "__main__": + assert len(sys.argv) == 4 + elf_file = sys.argv[1] + trace_file = sys.argv[2] + path_svg = sys.argv[3] + assert path_svg.endswith(".svg") + + functions = AsmFunc.load_elf(elf_file) + instructions = RvfiInstr.load_trace(trace_file) + + events = run_all(functions, instructions) + + i_event = 0 + for instr in instructions: + if i_event < len(events)-1 and events[i_event].instr is instr: + print(">>>", format_stack_change(events[i_event].stack, events[i_event+1].stack)) + i_event += 1 + print(instr.line) + + stats = build_stats(events) + duration = sum(map(lambda e: e.duration, events)) + icount = sum(map(lambda e: e.icount, events)) + print("duration:", duration) + print("icount:", icount) + print("IPC:", icount / duration) + + ipcs = [(stat.ipc(), func) for func, stat in stats.items()] + ipcs.sort(reverse=True) + for ipc, func in ipcs: + print(f"{ipc:.02f} IPC for {func}") + + render(stats, path_svg) + + stats = build_stats(events, True) + for f, s in stats.items(): + print(f"{f}: {s.ct}") + render(stats, f"{path_svg[:-4]}_with_ins.svg") diff --git a/spyglass/reference_summary.rpt b/spyglass/reference_summary.rpt index 21af934a3b2..0b03cd0570e 100644 --- a/spyglass/reference_summary.rpt +++ b/spyglass/reference_summary.rpt @@ -72,7 +72,7 @@ INFO ElabSummary 1 Generates Elaborated design units +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Severity Rule Name Count Short Help =============================================================================== -ERROR W123 12 A signal or variable has been read but +ERROR W123 18 A signal or variable has been read but is not set ERROR W416 1 Width of return type and return value of a function should be same (Verilog) diff --git a/src_files.yml b/src_files.yml index b71b628b6ea..33c8bf6c05e 100644 --- a/src_files.yml +++ b/src_files.yml @@ -22,6 +22,7 @@ ariane: src/ex_stage.sv, src/frontend/btb.sv, src/frontend/bht.sv, + src/frontend/bht2lvl.sv, src/frontend/ras.sv, src/frontend/instr_scan.sv, src/frontend/frontend.sv, diff --git a/tutorials/asic.md b/tutorials/asic.md new file mode 100644 index 00000000000..2a2ed80fef8 --- /dev/null +++ b/tutorials/asic.md @@ -0,0 +1,23 @@ +## ASIC Synthesis + +How to make cva6 synthesis ? +``` +make -C pd/synth cva6_synth FOUNDRY_PATH=/your/techno/basepath/ TECH_NAME=yourTechnoName TARGET_LIBRARY_FILES="yourLib1.db\ yourLib2.db" PERIOD=10 NAND2_AREA=650 TARGET=cv64a6_imafdc_sv39 ADDITIONAL_SEARCH_PATH="others/libs/paths/one\ others/libs/paths/two" +``` +Don't forget to escape spaces in lists. +Reports are under: pd/synth/ariane/reports + + +## ASIC Gate Simulation with `core-v-verif` repository + +> :warning: **Warning**: this chapter needs to be updated. See Github issue https://github.com/openhwgroup/cva6/issues/1358. + +```sh +export DV_SIMULATORS=veri-testharness,spike +cva6/regress/smoke-tests.sh +make -C pd/synth cva6_synth FOUNDRY_PATH=/your/techno/basepath/ TECH_NAME=yourTechnoName TARGET_LIBRARY_FILES="yourLib1.db\ yourLib2.db" PERIOD=10 NAND2_AREA=650 TARGET=cv64a6_imafdc_sv39 ADDITIONAL_SEARCH_PATH="others/libs/paths/one\ others/libs/paths/two" +sed 's/module SyncSpRamBeNx64_1/module SyncSpRamBeNx64_2/' pd/synth/ariane_synth.v > pd/synth/ariane_synth_modified.v +cd cva6/sim +make vcs_clean +python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-ld --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=spike,vcs-core-gate $DV_OPTS +``` diff --git a/tutorials/fpga.md b/tutorials/fpga.md new file mode 100644 index 00000000000..30f416f3563 --- /dev/null +++ b/tutorials/fpga.md @@ -0,0 +1,279 @@ +# COREV-APU FPGA Emulation + +We currently provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual) and the [Agilex 7 Development Kit](https://www.intel.la/content/www/xl/es/products/details/fpga/development-kits/agilex/agf014.html). + +- **Genesys 2** + + We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/openhwgroup/cva6/releases). + + Tested on Vivado 2018.2. The FPGA currently contains the following peripherals: + + - DDR3 memory controller + - SPI controller to connect to an SDCard + - Ethernet controller + - JTAG port (see debugging section below) + - Bootrom containing zero stage bootloader and device tree. + - UART + - GPIOs connected to LEDs + +> The ethernet controller and the corresponding network connection is still work in progress and not functional at the moment. Expect some updates soon-ish. + +- **Agilex 7** + + Tested on Quartus Prime Version 24.1.0 Pro Edition. The FPGA currently contains the following peripherals: + + - DDR4 memory controller + - JTAG port (see debugging section below) + - Bootrom containing zero stage bootloader + - UART + - GPIOs connected to LEDs + +> The ethernet controller and the corresponding network connection, as well as the SD Card connection and the capability to boot linux are still work in progress and not functional at the moment. Expect some updates soon-ish. + + +## Programming the Memory Configuration File or bitstream + +- **Genesys 2** + + - Open Vivado 2018.2 + - Open the hardware manager and open the target board (Genesys II - `xc7k325t`) + - Tools - Add Configuration Memory Device + - Select the following Spansion SPI flash `s25fl256xxxxxx0` + - Add `ariane_xilinx.mcs` + - Press Ok. Flashing will take a couple of minutes. + - Right click on the FPGA device - Boot from Configuration Memory Device (or press the program button on the FPGA) + +- **Agilex 7** + + - Open Quartus programmer + - Configure HW Setup by selecting the AGF FPGA Development Kit + - Click Auto-Detect to scan the JTAG chain + - In the device list, right click over device AGFB014R24B and add file (.rbf under corev_apu/altera/output_files) + - Click on Start button to program the FPGA + - Right after programming you can connect to the UART and see your CVA6 alive on Agilex! + - For this you need to use the JTAG UART provided with Quartus installation + +``` +.$quartus_installation_path/qprogrammer/quartus/bin/juart-terminal +juart-terminal: connected to hardware target using JTAG UART on cable +juart-terminal: "AGF FPGA Development Kit [1-3]", device 1, instance 0 +juart-terminal: (Use the IDE stop button or Ctrl-C to terminate) + +Hello World! +``` + +## Booting Linux + +The first stage bootloader will boot from SD Card by default. Get yourself a suitable SD Card (we use [this](https://www.amazon.com/Kingston-Digital-Mobility-MBLY10G2-32GB/dp/B00519BEQO) one). Either grab a pre-built Linux image from [here](https://github.com/pulp-platform/ariane-sdk/releases) or generate the Linux image yourself following the README in the [ariane-sdk repository](https://github.com/pulp-platform/ariane-sdk). Prepare the SD Card by following the "Booting from SD card" section in the ariane-sdk repository. + +Connect a terminal to the USB serial device opened by the FTDI chip e.g.: +``` +screen /dev/ttyUSB0 115200 +``` + +Default baudrate set by the bootloader and Linux is `115200`. + +After you've inserted the SD Card and programmed the FPGA you can connect to the serial port of the FPGA and should see the bootloader and afterwards Linux booting. Default username is `root`, no password required. + +## Booting zephyr RTOS + +[zephyr](https://zephyrproject.org/) is a real-time unikernel operating system developed by the Linux Foundation that targets resource-constrained embedded devices. It is highly configurable and optionally provides subsystems like userspace support with the PMP, a full network stack and a file system. + +zephyr natively supports the cva6 SoC and the **Genesys 2** board in two configurations: [cv64a6_imafdc_sv39](https://docs.zephyrproject.org/latest/boards/openhwgroup/cv64a6_genesys_2/doc/index.html) and [cv32a6_imac_sv32](https://docs.zephyrproject.org/latest/boards/openhwgroup/cv32a6_genesys_2/doc/index.html). +See the +`cv64a6_imafdc_sv39` is the configuration that will be synthesized when you follow the steps [below](#generating-a-bitstream). +In order to build `cv32a6_imac_sv32`, use the following command instead: +```bash +target=cv32a6_imac_sv32 make fpga +``` + +In order to build a zephyr application, follow the [zephyr getting started guide](https://docs.zephyrproject.org/latest/develop/getting_started/index.html) to setup the build dependencies and install zephyr's meta tool *west*. +You can then build zephyr applications using the standard process: +```bash +west build -p -b cv64a6_genesys_2 samples/hello_world # for cv64a6_imafdc_sv39 +west build -p -b cv32a6_genesys_2 samples/hello_world # for cv32a6_imac_sv32 +``` + + +You can use zephyr's *west* to debug or flash the application via openocd, akin to [the instructions below](#debugging): +```bash +west flash # loads the application into memory and runs it +west debug # launches an interactive GDB console that loads the application and stops at the first instruction +west attach # attaches to an application loaded using "west load" +``` + +Alternatively, similar to the [Linux instructions](#booting-linux), you may load zephyr from an SD card. +To this end, *after building the application*, use the provided script: +```bash +./util/write-zephyr-sd.sh /dev/sdXXX /path/to/zephyrproject/zephyr # provide correct SD card device and path to top level of cloned zephyrproject/zephyr repository +``` +**WARNING: The script will wipe the partition table and destroy all data on the SD card. Double-check the device path before running the script.** + +You can then insert the SD card into the board and have the zero-stage boot loader load and run zephyr. + + + +## Generating a Bitstream + +- **Genesys 2** + +To generate the FPGA bitstream (and memory configuration) yourself for the Genesys II board run: + +``` +make fpga +``` + +This will produce a bitstream file and memory configuration file (in `fpga/work-fpga`) which you can permanently flash by running the above commands. + +- **Agilex 7** + +To generate the FPGA bitstream yourself for the Agilex 7 board run: + +``` +make altera +``` + +We recommend to set the parameter FpgaAlteraEn (and also FpgaEn) to benefit from the FPGA optimizations. + +This will produce a bitstream file (in `altera/output_files`) which you can program following the previous instructions. **Note: Bear in mind that you need a Quartus Pro Licence to be able to generate this bitstream** + +To clean the project after generating the bitstream, use + +``` +make clean-altera +``` + +## Debugging + +- **Genesys 2** +You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD below. + +To get started, connect the micro USB port that is labeled with JTAG to your machine. This port is attached to the FTDI 2232 USB-to-serial chip on the Genesys 2 board, and is usually used to access the native JTAG interface of the Kintex-7 FPGA (e.g. to program the device using Vivado 2018.2). However, the FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module. + +>If you are on an Ubuntu based system you need to add the following udev rule to `/etc/udev/rules.d/99-ftdi.rules` +>``` +> SUBSYSTEM=="usb", ACTION=="add", ATTRS{idProduct}=="6010", ATTRS{idVendor}=="0403", MODE="664", GROUP="plugdev" +>``` + +Once attached to your system, the FTDI chip should be listed when you type `lsusb`: + +``` +Bus 005 Device 019: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC +``` + +If this is the case, you can go on and start openocd with the `fpga/ariane.cfg` configuration file: + +``` +openocd -f fpga/ariane.cfg + +Open On-Chip Debugger 0.10.0+dev-00195-g933cb87 (2018-09-14-19:32) +Licensed under GNU GPL v2 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +adapter speed: 1000 kHz +Info : auto-selecting first available session transport "jtag". To override use 'transport select '. +Info : clock speed 1000 kHz +Info : TAP riscv.cpu does not have IDCODE +Info : datacount=2 progbufsize=8 +Info : Examined RISC-V core; found 1 harts +Info : hart 0: XLEN=64, misa=0x8000000000141105 +Info : Listening on port 3333 for gdb connections +Ready for Remote Connections +Info : Listening on port 6666 for tcl connections +Info : Listening on port 4444 for telnet connections +Info : accepting 'gdb' connection on tcp/3333 +``` +- **Agilex 7** + +You can debug (and program) the FPGA using a modified version of OpenOCD included with Quartus installation ($quartus_installation_path/qprogrammer/quartus/bin/openocd). + +To get started, connect the micro USB port that is labeled with J13 to your machine. It is the same port that is used for the UART. Both use the JTAG interface and connect to the System Level Debugging (SLD) Hub instantiated inside the FPGA. Then the debugger connection goes to the virtual JTAG IP (vJTAG) which can be accessed with the modified version of OpenOCD. + +You can start openocd with the `altera/cva6.cfg` configuration file: + +``` +./$quartus_installation_path/qprogrammer/quartus/bin/openocd -f altera/cva6.cfg +Open On-Chip Debugger 0.11.0-R22.4 +Licensed under GNU GPL v2 +For bug reports, read + http://openocd.org/doc/doxygen/bugs.html +Info : only one transport option; autoselect 'jtag' +Info : Application name is OpenOCD.20241016093010 +Info : No cable specified, so will be searching for cables + +Info : At present, The first hardware cable will be used [1 cable(s) detected] +Info : Cable 1: device_name=(null), hw_name=AGF FPGA Development Kit, server=(null), port=1-3, chain_id=0x559319c8cde0, persistent_id=1, chain_type=1, features=34816, server_version_info=Version 24.1.0 Build 115 03/21/2024 SC Pro Edition +Info : TAP position 0 (C341A0DD) has 3 SLD nodes +Info : node 0 idcode=00406E00 position_n=0 +Info : node 1 idcode=30006E00 position_n=0 +Info : node 2 idcode=0C006E00 position_n=0 +Info : TAP position 1 (20D10DD) has 1 SLD nodes +Info : node 0 idcode=0C206E00 position_n=0 +Info : Discovered 2 TAP devices +Info : Detected device (tap_position=0) device_id=c341a0dd, instruction_length=10, features=12, device_name=AGFB014R24A(.|R1|R2)/.. +Info : Found an Intel device at tap_position 0.Currently assuming it is SLD Hub +Info : Detected device (tap_position=1) device_id=020d10dd, instruction_length=10, features=4, device_name=VTAP10 +Info : Found an Intel device at tap_position 1.Currently assuming it is SLD Hub +Info : This adapter doesn't support configurable speed +Info : JTAG tap: agilex7.fpga.tap tap/device found: 0xc341a0dd (mfg: 0x06e (Altera), part: 0x341a, ver: 0xc) +Info : JTAG tap: auto0.tap tap/device found: 0x020d10dd (mfg: 0x06e (Altera), part: 0x20d1, ver: 0x0) +Info : JTAG tap: agilex7.fpga.tap Parent Tap found: 0xc341a0dd (mfg: 0x06e (Altera), part: 0x341a, ver: 0xc) +Info : Virtual Tap/SLD node 0x00406E00 found at tap position 0 vtap position 0 +Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 10 -expected-id 0x020d10dd" +Info : datacount=2 progbufsize=8 +Info : Examined RISC-V core; found 1 harts +Info : hart 0: XLEN=32, misa=0x40141107 +Info : starting gdb server for agilex7.cva6.0 on 3333 +Info : Listening on port 3333 for gdb connections +Ready for Remote Connections +Info : Listening on port 6666 for tcl connections +Info : Listening on port 4444 for telnet connections +``` + +- **Common for both boards** + +Then you will be able to either connect through `telnet` or with `gdb`: + +``` +risc-none-elf-gdb /path/to/elf + +(gdb) target remote localhost:3333 +(gdb) load +Loading section .text, size 0x6508 lma 0x80000000 +Loading section .rodata, size 0x900 lma 0x80006508 +(gdb) b putchar +(gdb) c +Continuing. + +Program received signal SIGTRAP, Trace/breakpoint trap. +0x0000000080009126 in putchar (s=72) at lib/qprintf.c:69 +69 uart_sendchar(s); +(gdb) si +0x000000008000912a 69 uart_sendchar(s); +(gdb) p/x $mepc +$1 = 0xfffffffffffdb5ee +``` + +You can read or write device memory by using: +``` +(gdb) x/i 0x1000 + 0x1000: lui t0,0x4 +(gdb) set {int} 0x1000 = 22 +(gdb) set $pc = 0x1000 +``` + + +## Preliminary Support for OpenPiton Cache System + +CVA6 has preliminary support for the OpenPiton distributed cache system from Princeton University. To this end, a different L1 cache subsystem (`src/cache_subsystem/wt_cache_subsystem.sv`) has been developed that follows a write-through protocol and that has support for cache invalidations and atomics. + +The corresponding integration patches will be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton). Check the `README` in that repository to see how to use CVA6 in the OpenPiton setting. + +To activate the different cache system, compile your code with the macro `DCACHE_TYPE`. + + +## Re-generating the Bootcode (ZSBL) + +The zero stage bootloader (ZSBL) for RTL simulation lives in `bootrom/` while the bootcode for the FPGA is in `fpga/src/bootrom`. The RTL bootcode simply jumps to the base of the DRAM where the FSBL takes over. For the FPGA the ZSBL performs additional housekeeping. Both bootloader pass the hartid as well as address to the device tree in argument register `a0` and `a1` respectively. + +To re-generate the bootcode you can use the existing makefile within those directories. To generate the SystemVerilog files you will need the `bitstring` python package installed on your system. diff --git a/tutorials/running_sim.md b/tutorials/running_sim.md new file mode 100644 index 00000000000..c603170b27f --- /dev/null +++ b/tutorials/running_sim.md @@ -0,0 +1,137 @@ +# Running standalone simulations + +Simulating the CVA6 is done by using `verif/sim/cva6.py`. + +The environment variable `DV_SIMULATORS` allows you to specify which simulator to use. + +Four simulation types are supported: +- **veri-testharness**: verilator with corev_apu/testharness testbench +- **veri-testharness-pk**: verilator with corev_apu/testharness and RISC-V Proxy Kernel (for system-level software) +- **vcs-testharness**: vcs with corev_apu/testharness testbench +- **vcs-uvm**: vcs with UVM testbench +- **Spike** ISS + +You can set several simulators, such as : + +```sh +export DV_SIMULATORS=veri-testharness,vcs-testharness,vcs_uvm +``` + +If exactly 2 simulators are given, their trace is compared ([see the Regression tests section](#running-regression-tests-simulations)). + +Here is how you can run the hello world C program with the Verilator model: + +```sh +# Make sure to source this script from the root directory +# to correctly set the environment variables related to the tools +source verif/sim/setup-env.sh + +# Set the NUM_JOBS variable to increase the number of parallel make jobs +# export NUM_JOBS= + +export DV_SIMULATORS=veri-testharness + +cd ./verif/sim + +python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml \ +--c_tests ../tests/custom/hello_world/hello_world.c \ +--linker=../../config/gen_from_riscv_config/linker/link.ld \ +--gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib \ +-nostartfiles -g ../tests/custom/common/syscalls.c \ +../tests/custom/common/crt.S -lgcc \ +-I../tests/custom/env -I../tests/custom/common" +``` + +You can run either assembly programs (check `verif/test/custom/hello_world/custom_test_template.S`) or C programs. Run `python3 cva6.py --help` to have more information on the available parameters. + +## Simulating with the RISC-V proxy kernel +When running C programs, a common requirement is to use standard library functions like printf. On a bare-metal core, these functions do not work because they rely on underlying system calls that have no operating system to handle them. The veri-testharness-pk simulation mode solves this by integrating the [RISC-V proxy kernel](https://github.com/riscv-software-src/riscv-pk), which acts as a lightweight service layer to handle these calls (e.g. to properly display printf output). + +A reference script is provided to demonstrate this flow. It automatically builds the proxy kernel and runs a hello_world test on both a 64-bit and a 32-bit target. +To run the simulation, execute the following from the repository root: +```sh +bash verif/regress/veri-testharness-pk-tests.sh +``` +The C program associated with this test contains printf statement(s) with some text. The associated `.log.iss` logfile will display the corresponding text, confirming that the printf statement was executed properly. + +For more information about this simulation mode, installation directories, logfiles, refer to the comments in `verif/regress/veri-testharness-pk-tests.sh` and `verif/regress/install-pk.sh`. For general information regarding simulation logfiles, see the **Logs** section. + +## Simulating with VCS and Verdi + +You can set the environment variable `VERDI` as such if you want to launch Verdi while simulating with VCS: + +```sh +export VERDI=1 +``` + + +# Running regression tests simulations + +The smoke-tests script installs a random instruction generator and several tests suites: +- [riscv-dv](https://github.com/chipsalliance/riscv-dv) +- [riscv-compliance](https://github.com/lowRISC/riscv-compliance) +- [riscv-tests](https://github.com/riscv-software-src/riscv-tests) +- [riscv-arch-test](https://github.com/riscv-non-isa/riscv-arch-test) + + +The regression tests are done by comparing a model simulation trace with the Spike trace. + +Several tests scripts can be found in `./verif/regress` + +For example, here is how would run the riscv-arch-test regression test suite with the Verilator model: + +```sh +export DV_SIMULATORS=veri-testharness,spike +bash verif/regress/dv-riscv-arch-test.sh +``` + + +# Logs + +The logs from cva6.py are located in `./verif/sim/out_YEAR-MONTH-DAY`. + +Assuming you ran the smoke-tests scripts in the previous step, here is the log directory hierarchy: + +- **directed_asm_tests/**: The compiled (to .o then .bin) assembly tests +- **directed_c_tests/**: The compiled (to .o then .bin) c tests +- **spike_sim/**: Spike simulation log and trace files +- **veri_testharness_sim**: Verilator simulation log and trace files, when simulated using veri-testharness +- **veri-testharness-pk_sim:** Verilator simulation log and trace files, when simulated using veri-testharness-pk +- **iss_regr.log**: The regression test log + +The regression test log summarizes the comparison between the simulator trace and the Spike trace. Beware that a if a test fails before the comparison step, it will not appear in this log, check the output of cva6.py and the logs of the simulation instead. + + +# Waveform generation + +Waveform generation is currently supported for Verilator (`veri-testharness`) +and VCS with full UVM testbench (`vcs-uvm`) simulation types. It is disabled +by default to save simulation time and storage space. + +To enable waveform generation for a supported simulation mode, set either +of the two shell variables that control tracing before running any of the +test scripts under `verif/regress`: +- `export TRACE_FAST=1` enables "fast" waveform generation (keep simulation + time low at the expense of space). This will produce VCD files when using + Verilator, and VPD files when using Synopsys VCS with UVM testbench (`vcs-uvm`). +- `export TRACE_COMPACT=1` enables "compact" waveform generation (keep waveform + files smaller at the expense of increased simulation time). This will + produce FST files when using Verilator, and FSDB files when using Synopsys + VCS with UVM testbench (`vcs-uvm`). + +To generate VCD waveforms of the `smoke-tests` regression suite using Verilator, use: +```sh +export DV_SIMULATORS=veri-testharness,spike +export TRACE_FAST=1 +bash verif/regress/smoke-tests-.sh +``` + +Where `` is one of the following, depending on the CPU variant you want to use. +- `cv32a65x`. +- `cv32a6_imac_sv32`. +- `cv64a6_imafdc_sv39`. + +After each simulation run involving Verilator or VCS, the generated waveforms +will be copied to the directory containing the log files (see above,) with +the name of the current HW configuration added to the file name right before +the file type suffix (e.g., `I-ADD-01.cv32a60x.vcd`). diff --git a/util/sanitize/Makefile b/util/sanitize/Makefile new file mode 100644 index 00000000000..2a386b8ba03 --- /dev/null +++ b/util/sanitize/Makefile @@ -0,0 +1,27 @@ +# Copyright 2026 Univ. Grenoble Alpes, Inria, TIMA Laboratory +# +# SPDX-License-Identifier: Apaches-2.0 WITH SHL-2.1 +# +# Authors : Vincent Verdillon +# Creation Date : June, 2026 +# Description : Sanitize Makefile +# History : +# + +# root path +mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) +root-dir := $(abspath $(dir $(mkfile_path))/..) + +ifndef CVA6_REPO_DIR +$(warning must set CVA6_REPO_DIR to point at the root of CVA6 sources -- doing it for you...) +export CVA6_REPO_DIR = $(abspath $(root-dir)) +endif + +all: verilog xlen + +verilog: + cd $(root-dir) && \ + verible-verilog-format --inplace $$(git ls-tree -r HEAD --name-only core | grep '\.sv$$' | grep -v '^core/include/std_cache_pkg.sv$$' | grep -v cvfpu) + +xlen: + bash $(root-dir)/sanitize/systemverilog/xlen_misuse.sh diff --git a/util/sanitize/README.md b/util/sanitize/README.md new file mode 100644 index 00000000000..701996c5f65 --- /dev/null +++ b/util/sanitize/README.md @@ -0,0 +1,20 @@ + + +# Conform + +This directory provides multiple scripts to apply format and sanitize rules on this project. +You can execute all sanitize rules by executing `make`. +Or execute separately with `make verilog`, `make xlen`. + +- `make verilog` apply RTL format rule from the contributing doc. +- `make xlen` search for use of CVA6Cfg's XLEN attribute in arithmetical operations and IS_XLEN + attribute in logical operations. diff --git a/util/sanitize/systemverilog/xlen_misuse.sh b/util/sanitize/systemverilog/xlen_misuse.sh new file mode 100644 index 00000000000..56f3882dd2d --- /dev/null +++ b/util/sanitize/systemverilog/xlen_misuse.sh @@ -0,0 +1,66 @@ +#!/bin/bash + +# Copyright 2026 Univ. Grenoble Alpes, Inria, TIMA Laboratory +# +# SPDX-License-Identifier: Apaches-2.0 WITH SHL-2.1 +# +# Authors : Vincent Verdillon +# Creation Date : June, 2026 +# Description : Sanitize Makefile +# History : +# + +# check shell version +if [ -n "$BASH_VERSION" ]; then + SCRIPT_PATH="$BASH_SOURCE[0]" +elif [ -n "$ZSH_VERSION" ]; then + SCRIPT_PATH="${(%):-%N}" +else + echo "Error: Non recognized shell." + return +fi +export ROOT_PROJECT=$(readlink -f $(dirname "${SCRIPT_PATH}")/../../..) + +# Print all XLEN use in a logical expressions +# in this order : +# unary logical operators, +# conditional operator +# binary bitwise operators, +# binary logical operators, +# binary logical equality operators +# binary case equality operators, +# binary wildcard equality operators +xlen=$(grep $ROOT_PROJECT -rinHI -E --include="*.sv" --exclude="build_config_pkg.sv" \ + -e "(!|~|&|~&|\||~\||\^|~\^|\^~)[0-9a-zA-Z]*CVA6Cfg\.xlen" \ + -e "CVA6Cfg\.xlen *\?:" \ + -e "CVA6Cfg\.xlen *(&|\||\^|\^~|~^)" \ + -e "CVA6Cfg\.xlen *(&&|\|\||->|<->)" \ + -e "CVA6Cfg\.xlen *(==|!=)" \ + -e "CVA6Cfg\.xlen *(===|!==)" \ + -e "CVA6Cfg\.xlen *(==?|!=?)" | sort -u) + +# Print all IS_XLEN32 or IS_XLEN64 in a arithmetic expression +# unary arithmetic operators +# binary arithmetic operators +# binary shift operators +# binary relational operators +# unary increment, decrement operators +is_xlen=$(grep $ROOT_PROJECT -rinHI -E --include="*.sv" --exclude="build_config_pkg.sv" \ + -e "(\+|\-)[0-9a-zA-Z]*CVA6Cfg\.is_xlen(32|64)" \ + -e "CVA6Cfg\.is_xlen(32|64) *(\+|\-|\*|\/|\*\*|%)" \ + -e "CVA6Cfg\.is_xlen(32|64) *(>>|<<|>>>|<<<)" \ + -e "CVA6Cfg\.is_xlen(32|64) *(<|<=|>|>=)" \ + -e "(\+\+|\-\-)[0-9a-zA-Z]*CVA6Cfg\.is_xlen(32|64)" | sort -u) + +# Check if grep commands return something +if [ -z "$xlen" ] && [ -z "$is_xlen" ]; then + exit 0 +else + echo "There are misuses of CVA6Cfg XLEN attribute." + echo "XLEN misuses in arethmetical operations:" + echo "$xlen" + echo "" + echo "IS_XLEN misuses in logical operations:" + echo "$is_xlen" + exit 1 +fi diff --git a/util/toolchain-builder/README.md b/util/toolchain-builder/README.md index f6b56e5dcb5..9dff777d6bd 100644 --- a/util/toolchain-builder/README.md +++ b/util/toolchain-builder/README.md @@ -53,6 +53,13 @@ upstream toolchain (default: GCC 13.1.0) for bare-metal 32-bit and 64-bit applic # 3. Build and install the toolchain (requires write+create permissions for $INSTALL_DIR.) bash build-toolchain.sh $INSTALL_DIR +Additionally, after getting the GCC toolchain, you can apply +`gcc-cva6-tune.patch` to add support for the `-mtune=cva6` option in GCC. + +```bash +cd util/toolchain-builder/src/gcc && git apply ../../gcc-cva6-tune.patch +``` + ## File and directory structure The base infrastructure for building compilation toolchains consists of two scripts diff --git a/util/toolchain-builder/config/global.sh b/util/toolchain-builder/config/global.sh index dab7b0cba30..c5af7f6a6b1 100755 --- a/util/toolchain-builder/config/global.sh +++ b/util/toolchain-builder/config/global.sh @@ -60,11 +60,7 @@ BINUTILS_CONFIGURE_OPTS() { --target=$1 --prefix=${INSTALL_DIR} --disable-werror - --disable-gdb --disable-nls - --disable-sim - --disable-libdecnumber - --disable-readline ) echo "${OPTS[@]}" } diff --git a/util/toolchain-builder/gcc-cva6-tune.patch b/util/toolchain-builder/gcc-cva6-tune.patch new file mode 100644 index 00000000000..35f6988bb4d --- /dev/null +++ b/util/toolchain-builder/gcc-cva6-tune.patch @@ -0,0 +1,178 @@ +diff --git a/gcc/config/riscv/cva6.md b/gcc/config/riscv/cva6.md +new file mode 100644 +index 000000000..2dc397ee1 +--- /dev/null ++++ b/gcc/config/riscv/cva6.md +@@ -0,0 +1,98 @@ ++(define_automaton "cva6") ++ ++;; CVA6 core ++;; This has 4 functional unit groups: ++;; - ALU + Branch unit + Mult/Div + CSR ++;; - Load unit ++;; - Store Unit ++;; - FPU + ALU2 (for the superscalar configuration) ++ ++;; Issue ports ++(define_cpu_unit "cva6_issue0" "cva6") ++(define_cpu_unit "cva6_issue1" "cva6") ;; if superscalar ++ ++;; Fixed-latency (or so-called) functional units ++(define_cpu_unit "cva6_alu0" "cva6") ;; Includes the result bus ++(define_cpu_unit "cva6_branch" "cva6") ++(define_cpu_unit "cva6_mul" "cva6") ++(define_cpu_unit "cva6_div" "cva6") ++;; FIXME add CSR unit? (define_cpu_unit "cva6_csr" "cva6") ++ ++;; Accelerator/CV-X-IF functional unit ++(define_cpu_unit "cva6_cvxif" "cva6") ++ ++;; Load-Store Unit ++(define_cpu_unit "cva6_load" "cva6") ++(define_cpu_unit "cva6_store" "cva6") ++ ++;; FPU and ALU2 units ++(define_cpu_unit "cva6_fpu" "cva6") ++(define_cpu_unit "cva6_alu2" "cva6") ;; if superscalar ++ ++;; ISSUE can be either ISSUE0 or ISSUE1 ++(define_reservation "cva6_issue" "cva6_issue0|cva6_issue1") ++ ++;; ALU can be either ALU0 or ALU2, and ALU2 is preferred (if available) ++(define_reservation "cva6_alu" "cva6_alu2|cva6_alu0") ++ ++;; Most (integer) instructions are dispatched to the ALUs ++;; (All instructions need an issue port first) ++(define_insn_reservation "cva6_int" 1 ++ (and (eq_attr "tune" "cva6") ++ (eq_attr "type" "const,arith,logical,shift,slt,move,fmove,auipc,nop,bitmanip,rotate,condmove")) ++ "cva6_issue, cva6_alu") ++;; ALU-ALU forwarding is possible between integer instructions ++;;(define_bypass 0 "cva6_int" "cva6_int") ++;; Actually disabled as it decreases performance for now ++ ++;; Branches/jumps/calls use the branch unit and the first ALU ++(define_insn_reservation "cva6_branch" 1 ++ (and (eq_attr "tune" "cva6") ++ (eq_attr "type" "branch,jump,call")) ++ "cva6_issue, cva6_branch+cva6_alu0") ++;; When a branch is used, then the store unit is locked ++(absence_set "cva6_store" "cva6_branch") ++ ++;; Multiplications use the multiplier, then the result bus of the ALU ++(define_insn_reservation "cva6_mul" 2 ;; 2 cycles before the result is available ++ (and (eq_attr "tune" "cva6") ++ (eq_attr "type" "imul")) ++ "cva6_issue, cva6_mul, cva6_alu0") ++ ++;; Divisions make the divider busy for a long time ++(define_insn_reservation "cva6_div" 42 ;; FIXME use a realistic duration instead of 42 ++ (and (eq_attr "tune" "cva6") ++ (eq_attr "type" "idiv")) ++ "cva6_issue, cva6_div*42") ;; FIXME use a realistic duration instead of 42 ++;; FIXME the duration of the division can be XLEN-dependent ++;; Using the divider prevents from using alu0 and mul (and vice versa) ++(exclusion_set "cva6_div" "cva6_alu0,cva6_mul") ++ ++;; Unknown/custom and accelerator transfer instructions use CV-X-IF ++(define_insn_reservation "cva6_cvxif" 1 ;; FIXME update duration ++ (and (eq_attr "tune" "cva6") ++ (eq_attr "type" "mfc,mtc,unknown,multi")) ++ "cva6_issue, cva6_cvxif") ++ ++;; Load instructions, (int or float) use the load unit ++(define_insn_reservation "cva6_load" 2 ;; latency = 2 cycles... ++ (and (eq_attr "tune" "cva6") ++ (eq_attr "type" "load,fpload")) ++ "cva6_issue, cva6_load") ;; ... pipelined: unit busy for 1 cycle only ++ ++;; Store instructions, (int or float) use the store unit ++(define_insn_reservation "cva6_store" 2 ;; latency = 2 cycles... ++ (and (eq_attr "tune" "cva6") ++ (eq_attr "type" "store,fpstore")) ++ "cva6_issue, cva6_store") ;; ... pipelined: unit busy for 1 cycle only ++;; Cannot use load and store units simultaneously ++(exclusion_set "cva6_load" "cva6_store") ++ ++;; Floating point processing use the FPU for a long time ++(define_insn_reservation "cva6_fp" 42 ;; FIXME use a realistic value instead of 42 ++ (and (eq_attr "tune" "cva6") ++ (eq_attr "type" "fadd,fmul,fmadd,fdiv,fcmp,fcvt,fsqrt")) ++ "cva6_fpu*42") ;; FIXME use a realistic value instead of 42 ++;; FIXME the duration of the FP ops can be XLEN-dependent ++;; Using the FPU prevents from using alu2 (and vice versa) ++(exclusion_set "cva6_fpu" "cva6_alu2") ;; if superscalar ++ ++;; FIXME define reservation for the following instructions: ++;; sfb_alu atomic +diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def +index 7d87ab7ce..b0993fd48 100644 +--- a/gcc/config/riscv/riscv-cores.def ++++ b/gcc/config/riscv/riscv-cores.def +@@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info) + RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) + RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) + RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) ++RISCV_TUNE("cva6", cva6, cva6_tune_info) + RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) + RISCV_TUNE("size", generic, optimize_size_tune_info) + +diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h +index cf0cd669b..ff2a5ce33 100644 +--- a/gcc/config/riscv/riscv-opts.h ++++ b/gcc/config/riscv/riscv-opts.h +@@ -52,7 +52,8 @@ extern enum riscv_isa_spec_class riscv_isa_spec; + /* Keep this list in sync with define_attr "tune" in riscv.md. */ + enum riscv_microarchitecture_type { + generic, +- sifive_7 ++ sifive_7, ++ cva6 + }; + extern enum riscv_microarchitecture_type riscv_microarchitecture; + +diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc +index e88fa2d63..46a61b6b8 100644 +--- a/gcc/config/riscv/riscv.cc ++++ b/gcc/config/riscv/riscv.cc +@@ -339,6 +339,20 @@ static const struct riscv_tune_param sifive_7_tune_info = { + true, /* slow_unaligned_access */ + }; + ++/* Costs to use when optimizing for CVA6. */ ++static const struct riscv_tune_param cva6_tune_info = { ++ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ ++ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ ++ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ ++ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ ++ {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ ++ 2, /* issue_rate */ ++ 6, /* branch_cost */ ++ 2, /* memory_cost */ ++ 8, /* fmv_cost */ ++ false, /* slow_unaligned_access */ ++}; ++ + /* Costs to use when optimizing for T-HEAD c906. */ + static const struct riscv_tune_param thead_c906_tune_info = { + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ +diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md +index bc384d9ae..f4dacff34 100644 +--- a/gcc/config/riscv/riscv.md ++++ b/gcc/config/riscv/riscv.md +@@ -437,7 +437,7 @@ + ;; Microarchitectures we know how to tune for. + ;; Keep this in sync with enum riscv_microarchitecture. + (define_attr "tune" +- "generic,sifive_7" ++ "generic,sifive_7,cva6" + (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) + + ;; Describe a user's asm statement. +@@ -3145,5 +3145,6 @@ + (include "pic.md") + (include "generic.md") + (include "sifive-7.md") ++(include "cva6.md") + (include "thead.md") + (include "vector.md") diff --git a/util/user_config.py b/util/user_config.py index 3612dcbd5f3..7e7bab4c063 100644 --- a/util/user_config.py +++ b/util/user_config.py @@ -135,7 +135,7 @@ def build_param(line, value): return param_re.sub(r"\g<1>\g<2>\g<3>" + value + r"\g<5>", line) -cfg_re = re.compile(r"^(\s*)(?P\w+)(\s*:\s*)(?P.*?)(,?\s*)$") +cfg_re = re.compile(r"^(\s*)(?P\w+)(\s*:\s*)(?P.*?)(,?\s*)(//.*)?$") def parse_cfg(line): diff --git a/util/write-zephyr-sd.sh b/util/write-zephyr-sd.sh new file mode 100755 index 00000000000..78dabefc12f --- /dev/null +++ b/util/write-zephyr-sd.sh @@ -0,0 +1,40 @@ +#!/bin/sh + +set -e + +ZEPHYR_BINARY=build/zephyr/zephyr.bin + +usage(){ + echo "Usage: $1 "; + exit 1; +} + +if [ -z $1 ]; then + usage $0 +fi + +if [ -z $2 ]; then + usage $0 +fi + +ZEPHYR_BINARY="$2/${ZEPHYR_BINARY}"; + +SDDEVICE=$1 + +# account for partition table etc. +ZEPHYR_SECTORSTART=2048 +ZEPHYR_BIN_SECTORS=$(ls -l --block-size=512 $ZEPHYR_BINARY | cut -d " " -f5) +ZEPHYR_BIN_SECTORS=$((ZEPHYR_SECTORSTART + ZEPHYR_BIN_SECTORS)) +PART_TWO_START=$((ZEPHYR_BIN_SECTORS + 512)) + +echo "Creating a partition with zephyr from $ZEPHYR_SECTORSTART to $ZEPHYR_BIN_SECTORS and an empty FAT32 partition from $ZEPHYR_BIN_SECTORS to the device end!" +sgdisk --clear -g --new=1:$ZEPHYR_SECTORSTART:$ZEPHYR_BIN_SECTORS --new=2:$PART_TWO_START:0 --typecode=1:3000 --typecode=2:0700 $SDDEVICE + +SDDEVICE_PART1=$(lsblk $SDDEVICE -no PATH | head -2 | tail -1) +SDDEVICE_PART2=$(lsblk $SDDEVICE -no PATH | head -3 | tail -1) + +echo "Copying zephyr image" +dd if=$ZEPHYR_BINARY of=$SDDEVICE_PART1 status=progress oflag=sync bs=1M + +echo "Creating FAT filesystem on second partition!" +mkfs.vfat -F 32 $SDDEVICE_PART2 diff --git a/vendor/pulp-platform/axi_riscv_atomics/CHANGELOG.md b/vendor/pulp-platform/axi_riscv_atomics/CHANGELOG.md new file mode 100644 index 00000000000..f0bdab76028 --- /dev/null +++ b/vendor/pulp-platform/axi_riscv_atomics/CHANGELOG.md @@ -0,0 +1,49 @@ +# Change Log + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/), and this project adheres to +[Semantic Versioning](http://semver.org). + +## Unreleased + +## v0.2.2 - 2019-02-28 + +### Changed +- Update `axi` dependency to v0.6.0 (from an intermediary commit). + +## v0.2.1 - 2019-02-25 + +### Fixed +- `axi_riscv_amos`: Fixed timing of R response (#10). + +## v0.2.0 - 2019-02-21 + +### Changed +- Made SystemVerilog interfaces optional. Top-level modules now expose a flattened port list, and + an optional wrapper provides SystemVerilog interfaces. This improves compatibility with tools + that have poor support for SystemVerilog interfaces. + +## Fixed +- `axi_riscv_amos`: Fixed burst, cache, lock, prot, qos, region, size, and user of ARs. + +## v0.1.1 - 2019-02-20 + +### Fixed +- `axi_res_tbl`: Fixed assignments in `always_ff` process. +- `axi_riscv_amos`: Removed unused register. +- `axi_riscv_amos`: Added missing default assignments in AW FSM. +- `axi_riscv_amos`: Fixed sign extension of 32bit AMOs on 64bit ALU. +- `axi_riscv_amos`: Removed unused signals. +- `axi_riscv_atomics_wrap`: Fixed syntax of interface signal assignments. +- `axi_riscv_lrsc`: Added missing feedthrough of `aw_atop`. +- `axi_riscv_lrsc`: Fixed assignments in `always_ff` process. +- `axi_riscv_lrsc_wrap`: Fixed syntax of interface signal assignments. + +### Added +- Added simple standalone synthesis bench for `axi_riscv_atomics`. +- Added simple standalone synthesis bench for `axi_riscv_lrsc`. + +## v0.1.0 - 2019-02-19 + +Initial public development release diff --git a/vendor/pulp-platform/axi_riscv_atomics/LICENSE b/vendor/pulp-platform/axi_riscv_atomics/LICENSE new file mode 100644 index 00000000000..3a2b87e2d69 --- /dev/null +++ b/vendor/pulp-platform/axi_riscv_atomics/LICENSE @@ -0,0 +1,176 @@ +SOLDERPAD HARDWARE LICENSE version 0.51 + +This license is based closely on the Apache License Version 2.0, but is not +approved or endorsed by the Apache Foundation. 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Use only if you +know what you are doing and are prepared to adapt to wide-reaching changes as the project evolves. +Limited support is available for the latest v0.x version, but only for the latest, and we give no +backwards compatibility guarantees for versions before v1.0. + +The modules in this repository implement atomic operations (AMOs) for RISC-V processors ("A" +extension version 2.0) on the AXI protocol. The modules adheres to the RISC-V Weak Memory Ordering +(RVWMO) memory consistency model (version 0.1). + +## Usage + +Place one of the following modules in your memory hierarchy between an AXI master and slave, where +the slave owns a particular memory location (e.g., exclusive access to a memory controller or +adherence to a cache coherency protocol). Choose depending on your needs: + +- `axi_riscv_lrsc` tracks memory reservations for LR/SC, forwards only successful SCs, and responds + accordingly. This is sufficient to support LR/SC if the processor encodes them as AXI exclusive + memory accesses. Downstream modules do not have to support AXI exclusive memory accesses. + +- `axi_riscv_atomics` implements all RISC-V AMOs in addition to LR/SC. The processor needs to + encode RISC-V AMOs as AXI atomic transactions (`AtomicSwap` for `AMOSWAP`, `AtomicLoad` with the + corresponding opcode for all other AMOs). This is sufficient to support the entire RISC-V "A" + extension. Downstream modules do not have to support AXI atomic transactions or exclusive + memory accesses. + +For each of those modules we additionally provide a wrapper (`_wrap` filename suffix) that exposes +SystemVerilog interfaces instead of `logic` ports. diff --git a/vendor/pulp-platform/axi_riscv_atomics/src/axi_res_tbl.sv b/vendor/pulp-platform/axi_riscv_atomics/src/axi_res_tbl.sv new file mode 100644 index 00000000000..b3c56153347 --- /dev/null +++ b/vendor/pulp-platform/axi_riscv_atomics/src/axi_res_tbl.sv @@ -0,0 +1,93 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI Reservation Table +module axi_res_tbl #( + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0 +) ( + input logic clk_i, + input logic rst_ni, + input logic [AXI_ADDR_WIDTH-1:0] clr_addr_i, + input logic clr_req_i, + output logic clr_gnt_o, + input logic [AXI_ADDR_WIDTH-1:0] set_addr_i, + input logic [AXI_ID_WIDTH-1:0] set_id_i, + input logic set_req_i, + output logic set_gnt_o, + input logic [AXI_ADDR_WIDTH-1:0] check_addr_i, + input logic [AXI_ID_WIDTH-1:0] check_id_i, + output logic check_res_o, + input logic check_req_i, + output logic check_gnt_o +); + + localparam integer N_IDS = 2**AXI_ID_WIDTH; + + // Declarations of Signals and Types + logic [N_IDS-1:0][AXI_ADDR_WIDTH-1:0] tbl_d, tbl_q; + logic clr, + set; + + generate for (genvar i = 0; i < N_IDS; ++i) begin: gen_tbl + always_comb begin + tbl_d[i] = tbl_q[i]; + if (set && i == set_id_i) begin + tbl_d[i] = set_addr_i; + end else if (clr && tbl_q[i] == clr_addr_i) begin + tbl_d[i] = '0; + end + end + end endgenerate + + // Table-Managing Logic + always_comb begin + clr = 1'b0; + set = 1'b0; + clr_gnt_o = 1'b0; + set_gnt_o = 1'b0; + check_res_o = 1'b0; + check_gnt_o = 1'b0; + + if (clr_req_i) begin + clr = 1'b1; + clr_gnt_o = 1'b1; + end else if (set_req_i) begin + set = 1'b1; + set_gnt_o = 1'b1; + end else if (check_req_i) begin + check_res_o = (tbl_q[check_id_i] == check_addr_i); + check_gnt_o = 1'b1; + end + end + + // Registers + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + tbl_q <= '0; + end else begin + tbl_q <= tbl_d; + end + end + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (AXI_ADDR_WIDTH > 0) + else $fatal(1, "AXI_ADDR_WIDTH must be greater than 0!"); + assert (AXI_ID_WIDTH > 0) + else $fatal(1, "AXI_ID_WIDTH must be greater than 0!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos.sv b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos.sv new file mode 100644 index 00000000000..dae2974a877 --- /dev/null +++ b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos.sv @@ -0,0 +1,1006 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI RISC-V Atomic Operations (AMOs) Adapter +// +// This adapter implements atomic memory operations in accordance with the RVWMO memory consistency +// model. +// +// Interface notes: +// - This module has combinational paths between AXI inputs and outputs for minimum latency. Add +// slices upstream or downstream or in both directions if combinatorial paths become too long. +// The module adheres to the AXI ready/valid dependency specification to prevent combinatorial +// loops. + +module axi_riscv_amos #( + // AXI Parameters + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + // Maximum number of AXI write transactions outstanding at the same time + parameter int unsigned AXI_MAX_WRITE_TXNS = 0, + // Word width of the widest RISC-V processor that can issue requests to this module. + // 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are + // supported if `aw_strb` is set correctly. + parameter int unsigned RISCV_WORD_WIDTH = 0, + /// Derived Parameters (do NOT change manually!) + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 +) ( + input logic clk_i, + input logic rst_ni, + + /// Slave Interface + input logic [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i, + input logic [2:0] slv_aw_prot_i, + input logic [3:0] slv_aw_region_i, + input logic [5:0] slv_aw_atop_i, + input logic [7:0] slv_aw_len_i, + input logic [2:0] slv_aw_size_i, + input logic [1:0] slv_aw_burst_i, + input logic slv_aw_lock_i, + input logic [3:0] slv_aw_cache_i, + input logic [3:0] slv_aw_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_aw_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_aw_user_i, + output logic slv_aw_ready_o, + input logic slv_aw_valid_i, + + input logic [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i, + input logic [2:0] slv_ar_prot_i, + input logic [3:0] slv_ar_region_i, + input logic [7:0] slv_ar_len_i, + input logic [2:0] slv_ar_size_i, + input logic [1:0] slv_ar_burst_i, + input logic slv_ar_lock_i, + input logic [3:0] slv_ar_cache_i, + input logic [3:0] slv_ar_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_ar_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_ar_user_i, + output logic slv_ar_ready_o, + input logic slv_ar_valid_i, + + input logic [AXI_DATA_WIDTH-1:0] slv_w_data_i, + input logic [AXI_STRB_WIDTH-1:0] slv_w_strb_i, + input logic [AXI_USER_WIDTH-1:0] slv_w_user_i, + input logic slv_w_last_i, + output logic slv_w_ready_o, + input logic slv_w_valid_i, + + output logic [AXI_DATA_WIDTH-1:0] slv_r_data_o, + output logic [1:0] slv_r_resp_o, + output logic slv_r_last_o, + output logic [AXI_ID_WIDTH-1:0] slv_r_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_r_user_o, + input logic slv_r_ready_i, + output logic slv_r_valid_o, + + output logic [1:0] slv_b_resp_o, + output logic [AXI_ID_WIDTH-1:0] slv_b_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_b_user_o, + input logic slv_b_ready_i, + output logic slv_b_valid_o, + + /// Master Interface + output logic [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o, + output logic [2:0] mst_aw_prot_o, + output logic [3:0] mst_aw_region_o, + output logic [5:0] mst_aw_atop_o, + output logic [7:0] mst_aw_len_o, + output logic [2:0] mst_aw_size_o, + output logic [1:0] mst_aw_burst_o, + output logic mst_aw_lock_o, + output logic [3:0] mst_aw_cache_o, + output logic [3:0] mst_aw_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_aw_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_aw_user_o, + input logic mst_aw_ready_i, + output logic mst_aw_valid_o, + + output logic [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o, + output logic [2:0] mst_ar_prot_o, + output logic [3:0] mst_ar_region_o, + output logic [7:0] mst_ar_len_o, + output logic [2:0] mst_ar_size_o, + output logic [1:0] mst_ar_burst_o, + output logic mst_ar_lock_o, + output logic [3:0] mst_ar_cache_o, + output logic [3:0] mst_ar_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_ar_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_ar_user_o, + input logic mst_ar_ready_i, + output logic mst_ar_valid_o, + + output logic [AXI_DATA_WIDTH-1:0] mst_w_data_o, + output logic [AXI_STRB_WIDTH-1:0] mst_w_strb_o, + output logic [AXI_USER_WIDTH-1:0] mst_w_user_o, + output logic mst_w_last_o, + input logic mst_w_ready_i, + output logic mst_w_valid_o, + + input logic [AXI_DATA_WIDTH-1:0] mst_r_data_i, + input logic [1:0] mst_r_resp_i, + input logic mst_r_last_i, + input logic [AXI_ID_WIDTH-1:0] mst_r_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_r_user_i, + output logic mst_r_ready_o, + input logic mst_r_valid_i, + + input logic [1:0] mst_b_resp_i, + input logic [AXI_ID_WIDTH-1:0] mst_b_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_b_user_i, + output logic mst_b_ready_o, + input logic mst_b_valid_i +); + + localparam int unsigned OUTSTND_BURSTS_WIDTH = $clog2(AXI_MAX_WRITE_TXNS+1); + localparam int unsigned AXI_ALU_RATIO = AXI_DATA_WIDTH/RISCV_WORD_WIDTH; + + // State types + typedef enum logic [1:0] { FEEDTHROUGH_AW, WAIT_RESULT_AW, SEND_AW } aw_state_t; + aw_state_t aw_state_d, aw_state_q; + + typedef enum logic [2:0] { FEEDTHROUGH_W, WAIT_DATA_W, WAIT_RESULT_W, WAIT_CHANNEL_W, SEND_W } w_state_t; + w_state_t w_state_d, w_state_q; + + typedef enum logic [1:0] { FEEDTHROUGH_B, WAIT_COMPLETE_B, WAIT_CHANNEL_B, SEND_B } b_state_t; + b_state_t b_state_d, b_state_q; + + typedef enum logic [1:0] { FEEDTHROUGH_AR, WAIT_CHANNEL_AR, SEND_AR } ar_state_t; + ar_state_t ar_state_d, ar_state_q; + + typedef enum logic [1:0] { FEEDTHROUGH_R, WAIT_DATA_R, WAIT_CHANNEL_R, SEND_R } r_state_t; + r_state_t r_state_d, r_state_q; + + typedef enum logic [1:0] { NONE, INVALID, LOAD, STORE } atop_req_t; + atop_req_t atop_valid_d, atop_valid_q; + + // Signal declarations + // Transaction FF + logic [AXI_ADDR_WIDTH-1:0] addr_d, addr_q; + logic [AXI_ID_WIDTH-1:0] id_d, id_q; + logic [AXI_STRB_WIDTH-1:0] strb_d, strb_q; + logic [2:0] size_d, size_q; + logic [5:0] atop_d, atop_q; + logic [3:0] cache_d, cache_q; + logic [2:0] prot_d, prot_q; + logic [3:0] qos_d, qos_q; + logic [3:0] region_d, region_q; + logic [1:0] r_resp_d, r_resp_q; + logic [AXI_USER_WIDTH-1:0] aw_user_d, aw_user_q, + w_user_d, w_user_q, + r_user_d, r_user_q; + // Data FF + logic [AXI_DATA_WIDTH-1:0] w_data_d, w_data_q; // AMO operand + logic [AXI_DATA_WIDTH-1:0] r_data_d, r_data_q; // Data from memory + logic [AXI_DATA_WIDTH-1:0] result_d, result_q; // Result of AMO operation + logic w_d_valid_d, w_d_valid_q, // AMO operand valid + r_d_valid_d, r_d_valid_q; // Data from memory valid + // Counters + logic [OUTSTND_BURSTS_WIDTH-1:0] w_cnt_d, w_cnt_q; // Outstanding W beats + logic [OUTSTND_BURSTS_WIDTH-1:0] w_cnt_req_d, w_cnt_req_q; // W beats until AMO can read W + logic [OUTSTND_BURSTS_WIDTH-1:0] w_cnt_inj_d, w_cnt_inj_q; // W beats until AMO can insert its W + // States + logic adapter_ready; + logic transaction_collision; + logic aw_valid, aw_ready, aw_free, + w_valid, w_ready, w_free, + b_valid, b_ready, b_free, + ar_valid, ar_ready, ar_free, + r_valid, r_ready, r_free; + logic big_endian; + // ALU Signals + logic [RISCV_WORD_WIDTH-1:0] alu_operand_a; + logic [RISCV_WORD_WIDTH-1:0] alu_operand_b; + logic [RISCV_WORD_WIDTH-1:0] alu_result; + logic [AXI_DATA_WIDTH-1:0] alu_result_ext; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_a; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_b; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_a_sign_ext; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] op_b_sign_ext; + logic [AXI_ALU_RATIO-1:0][RISCV_WORD_WIDTH-1:0] res; + logic [AXI_STRB_WIDTH-1:0][7:0] strb_ext; + logic sign_a; + logic sign_b; + + /** + * Calculate ready signals and channel states + */ + + // Check if all state machines are ready for the next atomic request + assign adapter_ready = (aw_state_q == FEEDTHROUGH_AW) && + ( w_state_q == FEEDTHROUGH_W ) && + ( b_state_q == FEEDTHROUGH_B ) && + (ar_state_q == FEEDTHROUGH_AR) && + ( r_state_q == FEEDTHROUGH_R ); + + // Calculate if the channels are free + assign aw_free = ~aw_valid | aw_ready; + assign w_free = ~ w_valid | w_ready; + assign b_free = ~ b_valid | b_ready; + assign ar_free = ~ar_valid | ar_ready; + assign r_free = ~ r_valid | r_ready; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + aw_valid <= 0; + aw_ready <= 0; + w_valid <= 0; + w_ready <= 0; + b_valid <= 0; + b_ready <= 0; + ar_valid <= 0; + ar_ready <= 0; + r_valid <= 0; + r_ready <= 0; + end else begin + aw_valid <= mst_aw_valid_o; + aw_ready <= mst_aw_ready_i; + w_valid <= mst_w_valid_o; + w_ready <= mst_w_ready_i; + b_valid <= slv_b_valid_o; + b_ready <= slv_b_ready_i; + ar_valid <= mst_ar_valid_o; + ar_ready <= mst_ar_ready_i; + r_valid <= slv_r_valid_o; + r_ready <= slv_r_ready_i; + end + end + + // Calculate if the request interferes with the ongoing atomic transaction + // The protected bytes go from addr_q up to addr_q + (1 << size_q) - 1 + // TODO Bursts need special treatment + assign transaction_collision = (slv_aw_addr_i < ( addr_q + (8'h01 << size_q))) & + ( addr_q < (slv_aw_addr_i + (8'h01 << slv_aw_size_i))); + + always_comb begin : calc_atop_valid + atop_valid_d = atop_valid_q; + if (adapter_ready) begin + atop_valid_d = NONE; + if (slv_aw_valid_i && slv_aw_atop_i) begin + // Default is invalid request + atop_valid_d = INVALID; + // Valid load operation + if ((slv_aw_atop_i == axi_pkg::ATOP_ATOMICSWAP) || + (slv_aw_atop_i[5:4] == {axi_pkg::ATOP_ATOMICLOAD})) begin + atop_valid_d = LOAD; + end + // Valid store operation + if (slv_aw_atop_i[5:4] == {axi_pkg::ATOP_ATOMICSTORE}) begin + atop_valid_d = STORE; + end + // Invalidate valid request if control signals do not match + // Burst or exclusive access + if (slv_aw_len_i | slv_aw_lock_i) begin + atop_valid_d = INVALID; + end + // Unsupported size + if (slv_aw_size_i > $clog2(RISCV_WORD_WIDTH/8)) begin + atop_valid_d = INVALID; + end + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_atop_valid + if(~rst_ni) begin + atop_valid_q <= NONE; + end else begin + atop_valid_q <= atop_valid_d; + end + end + + /** + * Write Channel: AW, W, B + */ + + /*==================================================================== + = AW = + ====================================================================*/ + always_comb begin : axi_aw_channel + // Defaults AXI Bus + mst_aw_id_o = slv_aw_id_i; + mst_aw_addr_o = slv_aw_addr_i; + mst_aw_len_o = slv_aw_len_i; + mst_aw_size_o = slv_aw_size_i; + mst_aw_burst_o = slv_aw_burst_i; + mst_aw_lock_o = slv_aw_lock_i; + mst_aw_cache_o = slv_aw_cache_i; + mst_aw_prot_o = slv_aw_prot_i; + mst_aw_qos_o = slv_aw_qos_i; + mst_aw_region_o = slv_aw_region_i; + mst_aw_atop_o = 6'b0; + mst_aw_user_o = slv_aw_user_i; + // Defaults FF + addr_d = addr_q; + id_d = id_q; + size_d = size_q; + atop_d = atop_q; + cache_d = cache_q; + prot_d = prot_q; + qos_d = qos_q; + region_d = region_q; + aw_user_d = aw_user_q; + w_cnt_inj_d = w_cnt_inj_q; + // State Machine + aw_state_d = aw_state_q; + + // Default control: Block AW channel if... + if (slv_aw_valid_i && slv_aw_atop_i) begin + // Block if atomic request + mst_aw_valid_o = 1'b0; + slv_aw_ready_o = 1'b0; + end else if (w_cnt_q == AXI_MAX_WRITE_TXNS) begin + // Block if counter is overflowing + mst_aw_valid_o = 1'b0; + slv_aw_ready_o = 1'b0; + end else if (slv_aw_valid_i && transaction_collision && !adapter_ready) begin + // Block requests to the same address as current atomic transaction + mst_aw_valid_o = 1'b0; + slv_aw_ready_o = 1'b0; + end else begin + // Forward + mst_aw_valid_o = slv_aw_valid_i; + slv_aw_ready_o = mst_aw_ready_i; + end + + // Count W burst to know when to inject the W data + if (w_cnt_inj_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_inj_d = w_cnt_inj_q - 1; + end + + unique case (aw_state_q) + + FEEDTHROUGH_AW: begin + // Feedthrough slave to master until atomic operation is detected + if (slv_aw_valid_i && slv_aw_atop_i && adapter_ready) begin + // Acknowledge atomic transaction + slv_aw_ready_o = 1'b1; + // Remember request + atop_d = slv_aw_atop_i; + addr_d = slv_aw_addr_i; + id_d = slv_aw_id_i; + size_d = slv_aw_size_i; + cache_d = slv_aw_cache_i; + prot_d = slv_aw_prot_i; + qos_d = slv_aw_qos_i; + region_d = slv_aw_region_i; + aw_user_d = slv_aw_user_i; + // If valid AMO --> wait for result + if (atop_valid_d != INVALID) begin + aw_state_d = WAIT_RESULT_AW; + end + end + + end // FEEDTHROUGH_AW + + WAIT_RESULT_AW, SEND_AW: begin + // If the result is ready and the channel is free --> inject AW request + if ((r_d_valid_q && w_d_valid_q && aw_free) || (aw_state_q == SEND_AW)) begin + // Block + slv_aw_ready_o = 1'b0; + // Make write request + mst_aw_valid_o = 1'b1; + mst_aw_addr_o = addr_q; + mst_aw_len_o = 8'h00; + mst_aw_id_o = id_q; + mst_aw_size_o = size_q; + mst_aw_burst_o = 2'b00; + mst_aw_lock_o = 1'b0; + mst_aw_cache_o = cache_q; + mst_aw_prot_o = prot_q; + mst_aw_qos_o = qos_q; + mst_aw_region_o = region_q; + mst_aw_user_o = aw_user_q; + // Check if request is acknowledged + if (mst_aw_ready_i) begin + aw_state_d = FEEDTHROUGH_AW; + end else begin + aw_state_d = SEND_AW; + end + // Remember outstanding W beats before injected request + if (aw_state_q == WAIT_RESULT_AW) begin + if (w_cnt_q && mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_inj_d = w_cnt_q - 1; + end else begin + w_cnt_inj_d = w_cnt_q; + end + end + end + end // WAIT_RESULT_AW, SEND_AW + + default: aw_state_d = FEEDTHROUGH_AW; + + endcase + end // axi_aw_channel + + /*==================================================================== + = W = + ====================================================================*/ + always_comb begin : axi_w_channel + // Defaults AXI Bus + mst_w_data_o = slv_w_data_i; + mst_w_strb_o = slv_w_strb_i; + mst_w_last_o = slv_w_last_i; + mst_w_user_o = slv_w_user_i; + // Defaults FF + strb_d = strb_q; + w_user_d = w_user_q; + w_data_d = w_data_q; + result_d = result_q; + w_d_valid_d = w_d_valid_q; + w_cnt_req_d = w_cnt_req_q; + // State Machine + w_state_d = w_state_q; + + // Default control + // Make sure no data is sent without knowing if it's atomic + if (w_cnt_q == 0) begin + // Stall W as it precedes the AW request + slv_w_ready_o = 1'b0; + mst_w_valid_o = 1'b0; + end else begin + mst_w_valid_o = slv_w_valid_i; + slv_w_ready_o = mst_w_ready_i; + end + + unique case (w_state_q) + + FEEDTHROUGH_W: begin + if (adapter_ready) begin + // Reset read flag + w_d_valid_d = 1'b0; + result_d = '0; + + if (atop_valid_d != NONE) begin + // Check if data is also available and does not belong to previous request + if (w_cnt_q == 0) begin + // Block downstream + mst_w_valid_o = 1'b0; + // Fetch data and wait for all data + slv_w_ready_o = 1'b1; + if (slv_w_valid_i) begin + if (atop_valid_d != INVALID) begin + w_data_d = slv_w_data_i; + strb_d = slv_w_strb_i; + w_user_d = slv_w_user_i; + w_d_valid_d = 1'b1; + w_state_d = WAIT_RESULT_W; + end + end else begin + w_cnt_req_d = '0; + w_state_d = WAIT_DATA_W; + end + end else begin + // Remember the amount of outstanding bursts and count down + if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_req_d = w_cnt_q - 1; + end else begin + w_cnt_req_d = w_cnt_q; + end + w_state_d = WAIT_DATA_W; + end + end + end + end // FEEDTHROUGH_W + + WAIT_DATA_W: begin + // Count W beats until data arrives that belongs to the AMO request + if (w_cnt_req_q == 0) begin + // Block downstream + mst_w_valid_o = 1'b0; + // Ready upstream + slv_w_ready_o = 1'b1; + + if (slv_w_valid_i) begin + if (atop_valid_q == INVALID) begin + w_state_d = FEEDTHROUGH_W; + end else begin + w_data_d = slv_w_data_i; + strb_d = slv_w_strb_i; + w_user_d = slv_w_user_i; + w_d_valid_d = 1'b1; + w_state_d = WAIT_RESULT_W; + end + end + end else if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_req_d = w_cnt_req_q - 1; + end + end // WAIT_DATA_W + + WAIT_RESULT_W: begin + // If the result is ready, try to write it + if (r_d_valid_q && w_d_valid_q && aw_free) begin + // Check if W channel is free and make sure data is not interleaved + result_d = alu_result_ext; + if (w_free && w_cnt_q == 0) begin + // Block + slv_w_ready_o = 1'b0; + // Send write data + mst_w_valid_o = 1'b1; + mst_w_data_o = alu_result_ext; + mst_w_last_o = 1'b1; + mst_w_strb_o = strb_q; + mst_w_user_o = w_user_q; + if (mst_w_ready_i) begin + w_state_d = FEEDTHROUGH_W; + end else begin + w_state_d = SEND_W; + end + end else begin + w_state_d = WAIT_CHANNEL_W; + end + end + end // WAIT_RESULT_W + + WAIT_CHANNEL_W, SEND_W: begin + // Wait to not interleave the data + if ((w_free && w_cnt_inj_q == 0) || (w_state_q == SEND_W)) begin + // Block + slv_w_ready_o = 1'b0; + // Send write data + mst_w_valid_o = 1'b1; + mst_w_data_o = result_q; + mst_w_last_o = 1'b1; + mst_w_strb_o = strb_q; + mst_w_user_o = w_user_q; + if (mst_w_ready_i) begin + w_state_d = FEEDTHROUGH_W; + end else begin + w_state_d = SEND_W; + end + end + end // WAIT_CHANNEL_W, SEND_W + + default: w_state_d = FEEDTHROUGH_W; + + endcase + end // axi_w_channel + + /*==================================================================== + = B = + ====================================================================*/ + always_comb begin : axi_b_channel + // Defaults AXI Bus + mst_b_ready_o = slv_b_ready_i; + slv_b_id_o = mst_b_id_i; + slv_b_resp_o = mst_b_resp_i; + slv_b_user_o = mst_b_user_i; + slv_b_valid_o = mst_b_valid_i; + // State Machine + b_state_d = b_state_q; + + unique case (b_state_q) + + FEEDTHROUGH_B: begin + if (adapter_ready) begin + if (atop_valid_d == LOAD || atop_valid_d == STORE) begin + // Wait until write is complete + b_state_d = WAIT_COMPLETE_B; + end else if (atop_valid_d == INVALID) begin + // Inject B error resp once the channel is free + if (b_free) begin + // Block downstream + mst_b_ready_o = 1'b0; + // Write B response + slv_b_valid_o = 1'b1; + slv_b_id_o = slv_aw_id_i; + slv_b_resp_o = axi_pkg::RESP_SLVERR; + slv_b_user_o = '0; + if (!slv_b_ready_i) begin + b_state_d = SEND_B; + end + end else begin + b_state_d = WAIT_CHANNEL_B; + end + end + end + end // FEEDTHROUGH_B + + WAIT_CHANNEL_B, SEND_B: begin + if (b_free || (b_state_q == SEND_B)) begin + // Block downstream + mst_b_ready_o = 1'b0; + // Write B response + slv_b_valid_o = 1'b1; + slv_b_id_o = id_q; + slv_b_resp_o = axi_pkg::RESP_SLVERR; + slv_b_user_o = '0; + if (slv_b_ready_i) begin + b_state_d = FEEDTHROUGH_B; + end else begin + b_state_d = SEND_B; + end + end + end // WAIT_CHANNEL_B, SEND_B + + WAIT_COMPLETE_B: begin + if (mst_b_valid_i && (mst_b_id_i == id_q)) begin + b_state_d = FEEDTHROUGH_B; + end + end // WAIT_COMPLETE_B + + default: b_state_d = FEEDTHROUGH_B; + + endcase + end // axi_b_channel + + // Keep track of outstanding downstream write bursts and responses. + always_comb begin + w_cnt_d = w_cnt_q; + if (mst_aw_valid_o && mst_aw_ready_i) begin + w_cnt_d += 1; + end + if (mst_w_valid_o && mst_w_ready_i && mst_w_last_o) begin + w_cnt_d -= 1; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : axi_write_channel_ff + if(~rst_ni) begin + aw_state_q <= FEEDTHROUGH_AW; + w_state_q <= FEEDTHROUGH_W; + b_state_q <= FEEDTHROUGH_B; + w_cnt_q <= '0; + w_cnt_req_q <= '0; + w_cnt_inj_q <= '0; + addr_q <= '0; + id_q <= '0; + size_q <= '0; + strb_q <= '0; + cache_q <= '0; + prot_q <= '0; + qos_q <= '0; + region_q <= '0; + aw_user_q <= '0; + w_user_q <= '0; + w_data_q <= '0; + result_q <= '0; + w_d_valid_q <= '0; + atop_q <= 6'b0; + end else begin + aw_state_q <= aw_state_d; + w_state_q <= w_state_d; + b_state_q <= b_state_d; + w_cnt_q <= w_cnt_d; + w_cnt_req_q <= w_cnt_req_d; + w_cnt_inj_q <= w_cnt_inj_d; + addr_q <= addr_d; + id_q <= id_d; + size_q <= size_d; + strb_q <= strb_d; + cache_q <= cache_d; + prot_q <= prot_d; + qos_q <= qos_d; + region_q <= region_d; + aw_user_q <= aw_user_d; + w_user_q <= w_user_d; + w_data_q <= w_data_d; + result_q <= result_d; + w_d_valid_q <= w_d_valid_d; + atop_q <= atop_d; + end + end + + /** + * Read Channel: AR, R + */ + + /*==================================================================== + = AR = + ====================================================================*/ + always_comb begin : axi_ar_channel + // Defaults AXI Bus + mst_ar_id_o = slv_ar_id_i; + mst_ar_addr_o = slv_ar_addr_i; + mst_ar_len_o = slv_ar_len_i; + mst_ar_size_o = slv_ar_size_i; + mst_ar_burst_o = slv_ar_burst_i; + mst_ar_lock_o = slv_ar_lock_i; + mst_ar_cache_o = slv_ar_cache_i; + mst_ar_prot_o = slv_ar_prot_i; + mst_ar_qos_o = slv_ar_qos_i; + mst_ar_region_o = slv_ar_region_i; + mst_ar_user_o = slv_ar_user_i; + mst_ar_valid_o = 1'b0; + slv_ar_ready_o = 1'b0; + // State Machine + ar_state_d = ar_state_q; + + unique case (ar_state_q) + + FEEDTHROUGH_AR: begin + // Feed through + mst_ar_valid_o = slv_ar_valid_i; + slv_ar_ready_o = mst_ar_ready_i; + + if (adapter_ready) begin + if (atop_valid_d == LOAD | atop_valid_d == STORE) begin + if (ar_free) begin + // Acquire channel + slv_ar_ready_o = 1'b0; + // Immediately start read request + mst_ar_valid_o = 1'b1; + mst_ar_addr_o = slv_aw_addr_i; + mst_ar_id_o = slv_aw_id_i; + mst_ar_len_o = 8'h00; + mst_ar_size_o = slv_aw_size_i; + mst_ar_burst_o = 2'b00; + mst_ar_lock_o = 1'h0; + mst_ar_cache_o = slv_aw_cache_i; + mst_ar_prot_o = slv_aw_prot_i; + mst_ar_qos_o = slv_aw_qos_i; + mst_ar_region_o = slv_aw_region_i; + mst_ar_user_o = slv_aw_user_i; + if (!mst_ar_ready_i) begin + // Hold read request but do not depend on AW + ar_state_d = SEND_AR; + end + end else begin + // Wait until AR is free + ar_state_d = WAIT_CHANNEL_AR; + end + end + end + end // FEEDTHROUGH_AR + + WAIT_CHANNEL_AR, SEND_AR: begin + // Issue read request + if (ar_free || (ar_state_q == SEND_AR)) begin + // Inject read request + mst_ar_valid_o = 1'b1; + mst_ar_addr_o = addr_q; + mst_ar_id_o = id_q; + mst_ar_len_o = 8'h00; + mst_ar_size_o = size_q; + mst_ar_burst_o = 2'b00; + mst_ar_lock_o = 1'h0; + mst_ar_cache_o = cache_q; + mst_ar_prot_o = prot_q; + mst_ar_qos_o = qos_q; + mst_ar_region_o = region_q; + mst_ar_user_o = aw_user_q; + if (mst_ar_ready_i) begin + // Request acknowledged + ar_state_d = FEEDTHROUGH_AR; + end else begin + // Hold read request + ar_state_d = SEND_AR; + end + end else begin + // Wait until AR is free + mst_ar_valid_o = slv_ar_valid_i; + slv_ar_ready_o = mst_ar_ready_i; + end + end // WAIT_CHANNEL_AR, SEND_AR + + default: ar_state_d = FEEDTHROUGH_AR; + + endcase + end // axi_ar_channel + + /*==================================================================== + = R = + ====================================================================*/ + always_comb begin : axi_r_channel + // Defaults AXI Bus + mst_r_ready_o = slv_r_ready_i; + slv_r_id_o = mst_r_id_i; + slv_r_data_o = mst_r_data_i; + slv_r_resp_o = mst_r_resp_i; + slv_r_last_o = mst_r_last_i; + slv_r_user_o = mst_r_user_i; + slv_r_valid_o = mst_r_valid_i; + // Defaults FF + r_data_d = r_data_q; + r_resp_d = r_resp_q; + r_user_d = r_user_q; + r_d_valid_d = r_d_valid_q; + // State Machine + r_state_d = r_state_q; + + unique case (r_state_q) + + FEEDTHROUGH_R: begin + if (adapter_ready) begin + // Reset read flag + r_d_valid_d = 1'b0; + + if (atop_valid_d == LOAD || atop_valid_d == STORE) begin + // Wait for R response to read data + r_state_d = WAIT_DATA_R; + end else if (atop_valid_d == INVALID) begin + // Send R response once channel is free + if (r_free) begin + // Acquire the R channel + // Block downstream + mst_r_ready_o = 1'b0; + // Send R error response + slv_r_valid_o = 1'b1; + slv_r_data_o = '0; + slv_r_id_o = slv_aw_id_i; + slv_r_last_o = 1'b1; + slv_r_resp_o = axi_pkg::RESP_SLVERR; + slv_r_user_o = '0; + if (!slv_r_ready_i) begin + // Hold R response + r_state_d = SEND_R; + end + end else begin + r_state_d = WAIT_CHANNEL_R; + end + end + end + end // FEEDTHROUGH_R + + WAIT_DATA_R: begin + // Read data + if (mst_r_valid_i && (mst_r_id_i == id_q)) begin + // Acknowledge downstream and block upstream + mst_r_ready_o = 1'b1; + slv_r_valid_o = 1'b0; + // Store data + r_data_d = mst_r_data_i; + r_resp_d = mst_r_resp_i; + r_user_d = mst_r_user_i; + r_d_valid_d = 1'b1; + if (atop_valid_q == STORE) begin + r_state_d = FEEDTHROUGH_R; + end else begin + // Wait for B resp before injecting R + r_state_d = WAIT_CHANNEL_R; + end + end + end // WAIT_DATA_R + + WAIT_CHANNEL_R, SEND_R: begin + // Wait for the R channel to become free and B response to be valid + // TODO: Use b_state_d to be one cycle quicker + if ((r_free && (b_state_q != WAIT_COMPLETE_B)) || (r_state_q == SEND_R)) begin + // Block downstream + mst_r_ready_o = 1'b0; + // Send R response + slv_r_valid_o = 1'b1; + slv_r_data_o = r_data_q; + slv_r_id_o = id_q; + slv_r_last_o = 1'b1; + slv_r_resp_o = r_resp_q; + slv_r_user_o = r_user_q; + if (atop_valid_q == INVALID) begin + slv_r_data_o = '0; + slv_r_resp_o = axi_pkg::RESP_SLVERR; + slv_r_user_o = '0; + end + if (slv_r_ready_i) begin + r_state_d = FEEDTHROUGH_R; + end else begin + r_state_d = SEND_R; + end + end + end // WAIT_CHANNEL_R, SEND_R + + default: r_state_d = FEEDTHROUGH_R; + + endcase + end // axi_r_channel + + always_ff @(posedge clk_i or negedge rst_ni) begin : axi_read_channel_ff + if(~rst_ni) begin + ar_state_q <= FEEDTHROUGH_AR; + r_state_q <= FEEDTHROUGH_R; + r_data_q <= '0; + r_resp_q <= '0; + r_user_q <= '0; + r_d_valid_q <= 1'b0; + end else begin + ar_state_q <= ar_state_d; + r_state_q <= r_state_d; + r_data_q <= r_data_d; + r_resp_q <= r_resp_d; + r_user_q <= r_user_d; + r_d_valid_q <= r_d_valid_d; + end + end + + /** + * ALU + */ + + assign big_endian = (atop_q[3] == axi_pkg::ATOP_BIG_END); + assign op_a = big_endian ? {<<8{r_data_q & strb_ext}} : (r_data_q & strb_ext); + assign op_b = big_endian ? {<<8{w_data_q & strb_ext}} : (w_data_q & strb_ext); + assign sign_a = |(op_a & ~(strb_ext >> 1)); + assign sign_b = |(op_b & ~(strb_ext >> 1)); + assign alu_result_ext = big_endian ? {<<8{res}} : res; + + generate + if (AXI_ALU_RATIO == 1 && RISCV_WORD_WIDTH == 32) begin + assign alu_operand_a = op_a; + assign alu_operand_b = op_b; + assign res = alu_result; + end else if (AXI_ALU_RATIO == 1 && RISCV_WORD_WIDTH == 64) begin + assign res = alu_result; + always_comb begin + op_a_sign_ext = op_a | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_a}} & ~strb_ext); + op_b_sign_ext = op_b | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_b}} & ~strb_ext); + + if (atop_q[2:0] == axi_pkg::ATOP_SMAX || atop_q[2:0] == axi_pkg::ATOP_SMIN) begin + // Sign extend + alu_operand_a = op_a_sign_ext; + alu_operand_b = op_b_sign_ext; + end else begin + // No sign extension necessary + alu_operand_a = op_a; + alu_operand_b = op_b; + end + end + end else begin + always_comb begin + op_a_sign_ext = op_a | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_a}} & ~strb_ext); + op_b_sign_ext = op_b | ({AXI_ALU_RATIO*RISCV_WORD_WIDTH{sign_b}} & ~strb_ext); + + if (atop_q[2:0] == axi_pkg::ATOP_SMAX || atop_q[2:0] == axi_pkg::ATOP_SMIN) begin + // Sign extend + alu_operand_a = op_a_sign_ext[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]]; + alu_operand_b = op_b_sign_ext[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]]; + end else begin + // No sign extension necessary + alu_operand_a = op_a[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]]; + alu_operand_b = op_b[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]]; + end + res = '0; + res[addr_q[$clog2(AXI_DATA_WIDTH/8)-1:$clog2(RISCV_WORD_WIDTH/8)]] = alu_result; + end + end + endgenerate + + generate + for (genvar i = 0; i < AXI_STRB_WIDTH; i++) begin + always_comb begin + if (strb_q[i]) begin + strb_ext[i] = 8'hFF; + end else begin + strb_ext[i] = 8'h00; + end + end + end + endgenerate + + axi_riscv_amos_alu #( + .DATA_WIDTH ( RISCV_WORD_WIDTH ) + ) i_amo_alu ( + .amo_op_i ( atop_q ), + .amo_operand_a_i ( alu_operand_a ), + .amo_operand_b_i ( alu_operand_b ), + .amo_result_o ( alu_result ) + ); + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (AXI_ADDR_WIDTH > 0) + else $fatal(1, "AXI_ADDR_WIDTH must be greater than 0!"); + assert (AXI_DATA_WIDTH > 0) + else $fatal(1, "AXI_DATA_WIDTH must be greater than 0!"); + assert (AXI_ID_WIDTH > 0) + else $fatal(1, "AXI_ID_WIDTH must be greater than 0!"); + assert (AXI_MAX_WRITE_TXNS > 0) + else $fatal(1, "AXI_MAX_WRITE_TXNS must be greater than 0!"); + assert (RISCV_WORD_WIDTH == 32 || RISCV_WORD_WIDTH == 64) + else $fatal(1, "RISCV_WORD_WIDTH must be 32 or 64!"); + assert (RISCV_WORD_WIDTH <= AXI_DATA_WIDTH) + else $fatal(1, "RISCV_WORD_WIDTH must not be greater than AXI_DATA_WIDTH!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos_alu.sv b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos_alu.sv new file mode 100644 index 00000000000..40a52b0ec66 --- /dev/null +++ b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos_alu.sv @@ -0,0 +1,78 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI RISC-V Atomic Operations (AMOs) ALU +module axi_riscv_amos_alu # ( + parameter int unsigned DATA_WIDTH = 0 +) ( + input logic [5:0] amo_op_i, + input logic [DATA_WIDTH-1:0] amo_operand_a_i, + input logic [DATA_WIDTH-1:0] amo_operand_b_i, + output logic [DATA_WIDTH-1:0] amo_result_o +); + + logic [DATA_WIDTH:0] adder_sum; + logic [DATA_WIDTH:0] adder_operand_a, adder_operand_b; + + assign adder_sum = adder_operand_a + adder_operand_b; + + always_comb begin + + adder_operand_a = $signed(amo_operand_a_i); + adder_operand_b = $signed(amo_operand_b_i); + + amo_result_o = amo_operand_a_i; + + if (amo_op_i == axi_pkg::ATOP_ATOMICSWAP) begin + // Swap operation + amo_result_o = amo_operand_b_i; + end else if ((amo_op_i[5:4] == axi_pkg::ATOP_ATOMICLOAD) | (amo_op_i[5:4] == axi_pkg::ATOP_ATOMICSTORE)) begin + // Load operation + unique case (amo_op_i[2:0]) + // the default is to output operand_a + axi_pkg::ATOP_ADD: amo_result_o = adder_sum[DATA_WIDTH-1:0]; + axi_pkg::ATOP_CLR: amo_result_o = amo_operand_a_i & (~amo_operand_b_i); + axi_pkg::ATOP_SET: amo_result_o = amo_operand_a_i | amo_operand_b_i; + axi_pkg::ATOP_EOR: amo_result_o = amo_operand_a_i ^ amo_operand_b_i; + axi_pkg::ATOP_SMAX: begin + adder_operand_b = -$signed(amo_operand_b_i); + amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_b_i : amo_operand_a_i; + end + axi_pkg::ATOP_SMIN: begin + adder_operand_b = -$signed(amo_operand_b_i); + amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_a_i : amo_operand_b_i; + end + axi_pkg::ATOP_UMAX: begin + adder_operand_a = $unsigned(amo_operand_a_i); + adder_operand_b = -$unsigned(amo_operand_b_i); + amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_b_i : amo_operand_a_i; + end + axi_pkg::ATOP_UMIN: begin + adder_operand_a = $unsigned(amo_operand_a_i); + adder_operand_b = -$unsigned(amo_operand_b_i); + amo_result_o = adder_sum[DATA_WIDTH] ? amo_operand_a_i : amo_operand_b_i; + end + default: amo_result_o = '0; + endcase + end + end + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (DATA_WIDTH > 0) + else $fatal(1, "DATA_WIDTH must be greater than 0!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics.sv b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics.sv new file mode 100644 index 00000000000..f9b72d34143 --- /dev/null +++ b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics.sv @@ -0,0 +1,400 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI RISC-V Atomics ("A" Extension) Adapter +// +// This AXI adapter implements the RISC-V "A" extension and adheres to the RVWMO memory consistency +// model. +// +// Maintainer: Andreas Kurth + +module axi_riscv_atomics #( + /// AXI Parameters + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + // Maximum number of AXI write bursts outstanding at the same time + parameter int unsigned AXI_MAX_WRITE_TXNS = 0, + // Word width of the widest RISC-V processor that can issue requests to this module. + // 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are + // supported if `aw_strb` is set correctly. + parameter int unsigned RISCV_WORD_WIDTH = 0, + /// Derived Parameters (do NOT change manually!) + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 +) ( + input logic clk_i, + input logic rst_ni, + + /// Slave Interface + input logic [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i, + input logic [2:0] slv_aw_prot_i, + input logic [3:0] slv_aw_region_i, + input logic [5:0] slv_aw_atop_i, + input logic [7:0] slv_aw_len_i, + input logic [2:0] slv_aw_size_i, + input logic [1:0] slv_aw_burst_i, + input logic slv_aw_lock_i, + input logic [3:0] slv_aw_cache_i, + input logic [3:0] slv_aw_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_aw_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_aw_user_i, + output logic slv_aw_ready_o, + input logic slv_aw_valid_i, + + input logic [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i, + input logic [2:0] slv_ar_prot_i, + input logic [3:0] slv_ar_region_i, + input logic [7:0] slv_ar_len_i, + input logic [2:0] slv_ar_size_i, + input logic [1:0] slv_ar_burst_i, + input logic slv_ar_lock_i, + input logic [3:0] slv_ar_cache_i, + input logic [3:0] slv_ar_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_ar_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_ar_user_i, + output logic slv_ar_ready_o, + input logic slv_ar_valid_i, + + input logic [AXI_DATA_WIDTH-1:0] slv_w_data_i, + input logic [AXI_STRB_WIDTH-1:0] slv_w_strb_i, + input logic [AXI_USER_WIDTH-1:0] slv_w_user_i, + input logic slv_w_last_i, + output logic slv_w_ready_o, + input logic slv_w_valid_i, + + output logic [AXI_DATA_WIDTH-1:0] slv_r_data_o, + output logic [1:0] slv_r_resp_o, + output logic slv_r_last_o, + output logic [AXI_ID_WIDTH-1:0] slv_r_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_r_user_o, + input logic slv_r_ready_i, + output logic slv_r_valid_o, + + output logic [1:0] slv_b_resp_o, + output logic [AXI_ID_WIDTH-1:0] slv_b_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_b_user_o, + input logic slv_b_ready_i, + output logic slv_b_valid_o, + + /// Master Interface + output logic [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o, + output logic [2:0] mst_aw_prot_o, + output logic [3:0] mst_aw_region_o, + output logic [5:0] mst_aw_atop_o, + output logic [7:0] mst_aw_len_o, + output logic [2:0] mst_aw_size_o, + output logic [1:0] mst_aw_burst_o, + output logic mst_aw_lock_o, + output logic [3:0] mst_aw_cache_o, + output logic [3:0] mst_aw_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_aw_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_aw_user_o, + input logic mst_aw_ready_i, + output logic mst_aw_valid_o, + + output logic [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o, + output logic [2:0] mst_ar_prot_o, + output logic [3:0] mst_ar_region_o, + output logic [7:0] mst_ar_len_o, + output logic [2:0] mst_ar_size_o, + output logic [1:0] mst_ar_burst_o, + output logic mst_ar_lock_o, + output logic [3:0] mst_ar_cache_o, + output logic [3:0] mst_ar_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_ar_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_ar_user_o, + input logic mst_ar_ready_i, + output logic mst_ar_valid_o, + + output logic [AXI_DATA_WIDTH-1:0] mst_w_data_o, + output logic [AXI_STRB_WIDTH-1:0] mst_w_strb_o, + output logic [AXI_USER_WIDTH-1:0] mst_w_user_o, + output logic mst_w_last_o, + input logic mst_w_ready_i, + output logic mst_w_valid_o, + + input logic [AXI_DATA_WIDTH-1:0] mst_r_data_i, + input logic [1:0] mst_r_resp_i, + input logic mst_r_last_i, + input logic [AXI_ID_WIDTH-1:0] mst_r_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_r_user_i, + output logic mst_r_ready_o, + input logic mst_r_valid_i, + + input logic [1:0] mst_b_resp_i, + input logic [AXI_ID_WIDTH-1:0] mst_b_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_b_user_i, + output logic mst_b_ready_o, + input logic mst_b_valid_i +); + + // Make the entire address range exclusively accessible. Since the AMO adapter does not support + // address ranges, it would not make sense to expose the address range as a parameter of this + // module. + localparam longint unsigned ADDR_BEGIN = '0; + localparam longint unsigned ADDR_END = {AXI_ADDR_WIDTH{1'b1}}; + + logic [AXI_ADDR_WIDTH-1:0] int_axi_aw_addr; + logic [2:0] int_axi_aw_prot; + logic [3:0] int_axi_aw_region; + logic [5:0] int_axi_aw_atop; + logic [7:0] int_axi_aw_len; + logic [2:0] int_axi_aw_size; + logic [1:0] int_axi_aw_burst; + logic int_axi_aw_lock; + logic [3:0] int_axi_aw_cache; + logic [3:0] int_axi_aw_qos; + logic [AXI_ID_WIDTH-1:0] int_axi_aw_id; + logic [AXI_USER_WIDTH-1:0] int_axi_aw_user; + logic int_axi_aw_ready; + logic int_axi_aw_valid; + + logic [AXI_ADDR_WIDTH-1:0] int_axi_ar_addr; + logic [2:0] int_axi_ar_prot; + logic [3:0] int_axi_ar_region; + logic [7:0] int_axi_ar_len; + logic [2:0] int_axi_ar_size; + logic [1:0] int_axi_ar_burst; + logic int_axi_ar_lock; + logic [3:0] int_axi_ar_cache; + logic [3:0] int_axi_ar_qos; + logic [AXI_ID_WIDTH-1:0] int_axi_ar_id; + logic [AXI_USER_WIDTH-1:0] int_axi_ar_user; + logic int_axi_ar_ready; + logic int_axi_ar_valid; + + logic [AXI_DATA_WIDTH-1:0] int_axi_w_data; + logic [AXI_STRB_WIDTH-1:0] int_axi_w_strb; + logic [AXI_USER_WIDTH-1:0] int_axi_w_user; + logic int_axi_w_last; + logic int_axi_w_ready; + logic int_axi_w_valid; + + logic [AXI_DATA_WIDTH-1:0] int_axi_r_data; + logic [1:0] int_axi_r_resp; + logic int_axi_r_last; + logic [AXI_ID_WIDTH-1:0] int_axi_r_id; + logic [AXI_USER_WIDTH-1:0] int_axi_r_user; + logic int_axi_r_ready; + logic int_axi_r_valid; + + logic [1:0] int_axi_b_resp; + logic [AXI_ID_WIDTH-1:0] int_axi_b_id; + logic [AXI_USER_WIDTH-1:0] int_axi_b_user; + logic int_axi_b_ready; + logic int_axi_b_valid; + + axi_riscv_amos #( + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_USER_WIDTH (AXI_USER_WIDTH), + .AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS), + .RISCV_WORD_WIDTH (RISCV_WORD_WIDTH) + ) i_amos ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_aw_addr_i ( slv_aw_addr_i ), + .slv_aw_prot_i ( slv_aw_prot_i ), + .slv_aw_region_i ( slv_aw_region_i ), + .slv_aw_atop_i ( slv_aw_atop_i ), + .slv_aw_len_i ( slv_aw_len_i ), + .slv_aw_size_i ( slv_aw_size_i ), + .slv_aw_burst_i ( slv_aw_burst_i ), + .slv_aw_lock_i ( slv_aw_lock_i ), + .slv_aw_cache_i ( slv_aw_cache_i ), + .slv_aw_qos_i ( slv_aw_qos_i ), + .slv_aw_id_i ( slv_aw_id_i ), + .slv_aw_user_i ( slv_aw_user_i ), + .slv_aw_ready_o ( slv_aw_ready_o ), + .slv_aw_valid_i ( slv_aw_valid_i ), + .slv_ar_addr_i ( slv_ar_addr_i ), + .slv_ar_prot_i ( slv_ar_prot_i ), + .slv_ar_region_i ( slv_ar_region_i ), + .slv_ar_len_i ( slv_ar_len_i ), + .slv_ar_size_i ( slv_ar_size_i ), + .slv_ar_burst_i ( slv_ar_burst_i ), + .slv_ar_lock_i ( slv_ar_lock_i ), + .slv_ar_cache_i ( slv_ar_cache_i ), + .slv_ar_qos_i ( slv_ar_qos_i ), + .slv_ar_id_i ( slv_ar_id_i ), + .slv_ar_user_i ( slv_ar_user_i ), + .slv_ar_ready_o ( slv_ar_ready_o ), + .slv_ar_valid_i ( slv_ar_valid_i ), + .slv_w_data_i ( slv_w_data_i ), + .slv_w_strb_i ( slv_w_strb_i ), + .slv_w_user_i ( slv_w_user_i ), + .slv_w_last_i ( slv_w_last_i ), + .slv_w_ready_o ( slv_w_ready_o ), + .slv_w_valid_i ( slv_w_valid_i ), + .slv_r_data_o ( slv_r_data_o ), + .slv_r_resp_o ( slv_r_resp_o ), + .slv_r_last_o ( slv_r_last_o ), + .slv_r_id_o ( slv_r_id_o ), + .slv_r_user_o ( slv_r_user_o ), + .slv_r_ready_i ( slv_r_ready_i ), + .slv_r_valid_o ( slv_r_valid_o ), + .slv_b_resp_o ( slv_b_resp_o ), + .slv_b_id_o ( slv_b_id_o ), + .slv_b_user_o ( slv_b_user_o ), + .slv_b_ready_i ( slv_b_ready_i ), + .slv_b_valid_o ( slv_b_valid_o ), + .mst_aw_addr_o ( int_axi_aw_addr ), + .mst_aw_prot_o ( int_axi_aw_prot ), + .mst_aw_region_o ( int_axi_aw_region ), + .mst_aw_atop_o ( int_axi_aw_atop ), + .mst_aw_len_o ( int_axi_aw_len ), + .mst_aw_size_o ( int_axi_aw_size ), + .mst_aw_burst_o ( int_axi_aw_burst ), + .mst_aw_lock_o ( int_axi_aw_lock ), + .mst_aw_cache_o ( int_axi_aw_cache ), + .mst_aw_qos_o ( int_axi_aw_qos ), + .mst_aw_id_o ( int_axi_aw_id ), + .mst_aw_user_o ( int_axi_aw_user ), + .mst_aw_ready_i ( int_axi_aw_ready ), + .mst_aw_valid_o ( int_axi_aw_valid ), + .mst_ar_addr_o ( int_axi_ar_addr ), + .mst_ar_prot_o ( int_axi_ar_prot ), + .mst_ar_region_o ( int_axi_ar_region ), + .mst_ar_len_o ( int_axi_ar_len ), + .mst_ar_size_o ( int_axi_ar_size ), + .mst_ar_burst_o ( int_axi_ar_burst ), + .mst_ar_lock_o ( int_axi_ar_lock ), + .mst_ar_cache_o ( int_axi_ar_cache ), + .mst_ar_qos_o ( int_axi_ar_qos ), + .mst_ar_id_o ( int_axi_ar_id ), + .mst_ar_user_o ( int_axi_ar_user ), + .mst_ar_ready_i ( int_axi_ar_ready ), + .mst_ar_valid_o ( int_axi_ar_valid ), + .mst_w_data_o ( int_axi_w_data ), + .mst_w_strb_o ( int_axi_w_strb ), + .mst_w_user_o ( int_axi_w_user ), + .mst_w_last_o ( int_axi_w_last ), + .mst_w_ready_i ( int_axi_w_ready ), + .mst_w_valid_o ( int_axi_w_valid ), + .mst_r_data_i ( int_axi_r_data ), + .mst_r_resp_i ( int_axi_r_resp ), + .mst_r_last_i ( int_axi_r_last ), + .mst_r_id_i ( int_axi_r_id ), + .mst_r_user_i ( int_axi_r_user ), + .mst_r_ready_o ( int_axi_r_ready ), + .mst_r_valid_i ( int_axi_r_valid ), + .mst_b_resp_i ( int_axi_b_resp ), + .mst_b_id_i ( int_axi_b_id ), + .mst_b_user_i ( int_axi_b_user ), + .mst_b_ready_o ( int_axi_b_ready ), + .mst_b_valid_i ( int_axi_b_valid ) + ); + + axi_riscv_lrsc #( + .ADDR_BEGIN (ADDR_BEGIN), + .ADDR_END (ADDR_END), + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_USER_WIDTH (AXI_USER_WIDTH) + ) i_lrsc ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_aw_addr_i ( int_axi_aw_addr ), + .slv_aw_prot_i ( int_axi_aw_prot ), + .slv_aw_region_i ( int_axi_aw_region ), + .slv_aw_atop_i ( int_axi_aw_atop ), + .slv_aw_len_i ( int_axi_aw_len ), + .slv_aw_size_i ( int_axi_aw_size ), + .slv_aw_burst_i ( int_axi_aw_burst ), + .slv_aw_lock_i ( int_axi_aw_lock ), + .slv_aw_cache_i ( int_axi_aw_cache ), + .slv_aw_qos_i ( int_axi_aw_qos ), + .slv_aw_id_i ( int_axi_aw_id ), + .slv_aw_user_i ( int_axi_aw_user ), + .slv_aw_ready_o ( int_axi_aw_ready ), + .slv_aw_valid_i ( int_axi_aw_valid ), + .slv_ar_addr_i ( int_axi_ar_addr ), + .slv_ar_prot_i ( int_axi_ar_prot ), + .slv_ar_region_i ( int_axi_ar_region ), + .slv_ar_len_i ( int_axi_ar_len ), + .slv_ar_size_i ( int_axi_ar_size ), + .slv_ar_burst_i ( int_axi_ar_burst ), + .slv_ar_lock_i ( int_axi_ar_lock ), + .slv_ar_cache_i ( int_axi_ar_cache ), + .slv_ar_qos_i ( int_axi_ar_qos ), + .slv_ar_id_i ( int_axi_ar_id ), + .slv_ar_user_i ( int_axi_ar_user ), + .slv_ar_ready_o ( int_axi_ar_ready ), + .slv_ar_valid_i ( int_axi_ar_valid ), + .slv_w_data_i ( int_axi_w_data ), + .slv_w_strb_i ( int_axi_w_strb ), + .slv_w_user_i ( int_axi_w_user ), + .slv_w_last_i ( int_axi_w_last ), + .slv_w_ready_o ( int_axi_w_ready ), + .slv_w_valid_i ( int_axi_w_valid ), + .slv_r_data_o ( int_axi_r_data ), + .slv_r_resp_o ( int_axi_r_resp ), + .slv_r_last_o ( int_axi_r_last ), + .slv_r_id_o ( int_axi_r_id ), + .slv_r_user_o ( int_axi_r_user ), + .slv_r_ready_i ( int_axi_r_ready ), + .slv_r_valid_o ( int_axi_r_valid ), + .slv_b_resp_o ( int_axi_b_resp ), + .slv_b_id_o ( int_axi_b_id ), + .slv_b_user_o ( int_axi_b_user ), + .slv_b_ready_i ( int_axi_b_ready ), + .slv_b_valid_o ( int_axi_b_valid ), + .mst_aw_addr_o ( mst_aw_addr_o ), + .mst_aw_prot_o ( mst_aw_prot_o ), + .mst_aw_region_o ( mst_aw_region_o ), + .mst_aw_atop_o ( mst_aw_atop_o ), + .mst_aw_len_o ( mst_aw_len_o ), + .mst_aw_size_o ( mst_aw_size_o ), + .mst_aw_burst_o ( mst_aw_burst_o ), + .mst_aw_lock_o ( mst_aw_lock_o ), + .mst_aw_cache_o ( mst_aw_cache_o ), + .mst_aw_qos_o ( mst_aw_qos_o ), + .mst_aw_id_o ( mst_aw_id_o ), + .mst_aw_user_o ( mst_aw_user_o ), + .mst_aw_ready_i ( mst_aw_ready_i ), + .mst_aw_valid_o ( mst_aw_valid_o ), + .mst_ar_addr_o ( mst_ar_addr_o ), + .mst_ar_prot_o ( mst_ar_prot_o ), + .mst_ar_region_o ( mst_ar_region_o ), + .mst_ar_len_o ( mst_ar_len_o ), + .mst_ar_size_o ( mst_ar_size_o ), + .mst_ar_burst_o ( mst_ar_burst_o ), + .mst_ar_lock_o ( mst_ar_lock_o ), + .mst_ar_cache_o ( mst_ar_cache_o ), + .mst_ar_qos_o ( mst_ar_qos_o ), + .mst_ar_id_o ( mst_ar_id_o ), + .mst_ar_user_o ( mst_ar_user_o ), + .mst_ar_ready_i ( mst_ar_ready_i ), + .mst_ar_valid_o ( mst_ar_valid_o ), + .mst_w_data_o ( mst_w_data_o ), + .mst_w_strb_o ( mst_w_strb_o ), + .mst_w_user_o ( mst_w_user_o ), + .mst_w_last_o ( mst_w_last_o ), + .mst_w_ready_i ( mst_w_ready_i ), + .mst_w_valid_o ( mst_w_valid_o ), + .mst_r_data_i ( mst_r_data_i ), + .mst_r_resp_i ( mst_r_resp_i ), + .mst_r_last_i ( mst_r_last_i ), + .mst_r_id_i ( mst_r_id_i ), + .mst_r_user_i ( mst_r_user_i ), + .mst_r_ready_o ( mst_r_ready_o ), + .mst_r_valid_i ( mst_r_valid_i ), + .mst_b_resp_i ( mst_b_resp_i ), + .mst_b_id_i ( mst_b_id_i ), + .mst_b_user_i ( mst_b_user_i ), + .mst_b_ready_o ( mst_b_ready_o ), + .mst_b_valid_i ( mst_b_valid_i ) + ); + +endmodule diff --git a/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv new file mode 100644 index 00000000000..ad3505cf30f --- /dev/null +++ b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv @@ -0,0 +1,151 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Wrapper for the AXI RISC-V Atomics Adapter that exposes AXI SystemVerilog interfaces. +// +// See the header of `axi_riscv_atomics` for a description. +// +// Maintainer: Andreas Kurth + +module axi_riscv_atomics_wrap #( + /// AXI Parameters + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + /// Maximum number of AXI bursts outstanding at the same time + parameter int unsigned AXI_MAX_WRITE_TXNS = 0, + // Word width of the widest RISC-V processor that can issue requests to this module. + // 32 for RV32; 64 for RV64, where both 32-bit (.W suffix) and 64-bit (.D suffix) AMOs are + // supported if `aw_strb` is set correctly. + parameter int unsigned RISCV_WORD_WIDTH = 0, + /// Derived Parameters (do NOT change manually!) + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Master mst, + AXI_BUS.Slave slv +); + + axi_riscv_atomics #( + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_USER_WIDTH (AXI_USER_WIDTH), + .AXI_MAX_WRITE_TXNS (AXI_MAX_WRITE_TXNS), + .RISCV_WORD_WIDTH (RISCV_WORD_WIDTH) + ) i_atomics ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_aw_addr_i ( slv.aw_addr ), + .slv_aw_prot_i ( slv.aw_prot ), + .slv_aw_region_i ( slv.aw_region ), + .slv_aw_atop_i ( slv.aw_atop ), + .slv_aw_len_i ( slv.aw_len ), + .slv_aw_size_i ( slv.aw_size ), + .slv_aw_burst_i ( slv.aw_burst ), + .slv_aw_lock_i ( slv.aw_lock ), + .slv_aw_cache_i ( slv.aw_cache ), + .slv_aw_qos_i ( slv.aw_qos ), + .slv_aw_id_i ( slv.aw_id ), + .slv_aw_user_i ( slv.aw_user ), + .slv_aw_ready_o ( slv.aw_ready ), + .slv_aw_valid_i ( slv.aw_valid ), + .slv_ar_addr_i ( slv.ar_addr ), + .slv_ar_prot_i ( slv.ar_prot ), + .slv_ar_region_i ( slv.ar_region ), + .slv_ar_len_i ( slv.ar_len ), + .slv_ar_size_i ( slv.ar_size ), + .slv_ar_burst_i ( slv.ar_burst ), + .slv_ar_lock_i ( slv.ar_lock ), + .slv_ar_cache_i ( slv.ar_cache ), + .slv_ar_qos_i ( slv.ar_qos ), + .slv_ar_id_i ( slv.ar_id ), + .slv_ar_user_i ( slv.ar_user ), + .slv_ar_ready_o ( slv.ar_ready ), + .slv_ar_valid_i ( slv.ar_valid ), + .slv_w_data_i ( slv.w_data ), + .slv_w_strb_i ( slv.w_strb ), + .slv_w_user_i ( slv.w_user ), + .slv_w_last_i ( slv.w_last ), + .slv_w_ready_o ( slv.w_ready ), + .slv_w_valid_i ( slv.w_valid ), + .slv_r_data_o ( slv.r_data ), + .slv_r_resp_o ( slv.r_resp ), + .slv_r_last_o ( slv.r_last ), + .slv_r_id_o ( slv.r_id ), + .slv_r_user_o ( slv.r_user ), + .slv_r_ready_i ( slv.r_ready ), + .slv_r_valid_o ( slv.r_valid ), + .slv_b_resp_o ( slv.b_resp ), + .slv_b_id_o ( slv.b_id ), + .slv_b_user_o ( slv.b_user ), + .slv_b_ready_i ( slv.b_ready ), + .slv_b_valid_o ( slv.b_valid ), + .mst_aw_addr_o ( mst.aw_addr ), + .mst_aw_prot_o ( mst.aw_prot ), + .mst_aw_region_o ( mst.aw_region ), + .mst_aw_atop_o ( mst.aw_atop ), + .mst_aw_len_o ( mst.aw_len ), + .mst_aw_size_o ( mst.aw_size ), + .mst_aw_burst_o ( mst.aw_burst ), + .mst_aw_lock_o ( mst.aw_lock ), + .mst_aw_cache_o ( mst.aw_cache ), + .mst_aw_qos_o ( mst.aw_qos ), + .mst_aw_id_o ( mst.aw_id ), + .mst_aw_user_o ( mst.aw_user ), + .mst_aw_ready_i ( mst.aw_ready ), + .mst_aw_valid_o ( mst.aw_valid ), + .mst_ar_addr_o ( mst.ar_addr ), + .mst_ar_prot_o ( mst.ar_prot ), + .mst_ar_region_o ( mst.ar_region ), + .mst_ar_len_o ( mst.ar_len ), + .mst_ar_size_o ( mst.ar_size ), + .mst_ar_burst_o ( mst.ar_burst ), + .mst_ar_lock_o ( mst.ar_lock ), + .mst_ar_cache_o ( mst.ar_cache ), + .mst_ar_qos_o ( mst.ar_qos ), + .mst_ar_id_o ( mst.ar_id ), + .mst_ar_user_o ( mst.ar_user ), + .mst_ar_ready_i ( mst.ar_ready ), + .mst_ar_valid_o ( mst.ar_valid ), + .mst_w_data_o ( mst.w_data ), + .mst_w_strb_o ( mst.w_strb ), + .mst_w_user_o ( mst.w_user ), + .mst_w_last_o ( mst.w_last ), + .mst_w_ready_i ( mst.w_ready ), + .mst_w_valid_o ( mst.w_valid ), + .mst_r_data_i ( mst.r_data ), + .mst_r_resp_i ( mst.r_resp ), + .mst_r_last_i ( mst.r_last ), + .mst_r_id_i ( mst.r_id ), + .mst_r_user_i ( mst.r_user ), + .mst_r_ready_o ( mst.r_ready ), + .mst_r_valid_i ( mst.r_valid ), + .mst_b_resp_i ( mst.b_resp ), + .mst_b_id_i ( mst.b_id ), + .mst_b_user_i ( mst.b_user ), + .mst_b_ready_o ( mst.b_ready ), + .mst_b_valid_i ( mst.b_valid ) + ); + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (AXI_STRB_WIDTH == AXI_DATA_WIDTH/8) + else $fatal(1, "AXI_STRB_WIDTH must equal AXI_DATA_WIDTH/8!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc.sv b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc.sv new file mode 100644 index 00000000000..82c132c79ae --- /dev/null +++ b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc.sv @@ -0,0 +1,509 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// AXI RISC-V LR/SC Adapter +// +// This adapter adds support for AXI4 exclusive accesses to a slave that natively does not support +// exclusive accesses. It is to be placed between that slave and the upstream master port, so that +// the `mst` port of this module drives the slave and the `slv` port of this module is driven by +// the upstream master. +// +// Exclusive accesses are only enabled for a range of addresses specified through parameters. All +// addresses within that range are guaranteed to fulfill the constraints described in A7.2 of the +// AXI4 standard, both for normal and exclusive memory accesses. Addresses outside that range +// behave like a slave that does not support exclusive memory accesses (see AXI4, A7.2.5). +// +// Limitations: +// - The adapter allows at most one read and one write access to be outstanding at any given +// time. +// - The adapter does not support bursts in exclusive accessing. Only single words can be +// reserved. +// +// Maintainer: Andreas Kurth + +module axi_riscv_lrsc #( + /// Exclusively-accessible address range (closed interval from ADDR_BEGIN to ADDR_END) + parameter longint unsigned ADDR_BEGIN = 0, + parameter longint unsigned ADDR_END = 0, + /// AXI Parameters + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + /// Derived Parameters (do NOT change manually!) + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 +) ( + input logic clk_i, + input logic rst_ni, + + /// Slave Interface + input logic [AXI_ADDR_WIDTH-1:0] slv_aw_addr_i, + input logic [2:0] slv_aw_prot_i, + input logic [3:0] slv_aw_region_i, + input logic [5:0] slv_aw_atop_i, + input logic [7:0] slv_aw_len_i, + input logic [2:0] slv_aw_size_i, + input logic [1:0] slv_aw_burst_i, + input logic slv_aw_lock_i, + input logic [3:0] slv_aw_cache_i, + input logic [3:0] slv_aw_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_aw_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_aw_user_i, + output logic slv_aw_ready_o, + input logic slv_aw_valid_i, + + input logic [AXI_ADDR_WIDTH-1:0] slv_ar_addr_i, + input logic [2:0] slv_ar_prot_i, + input logic [3:0] slv_ar_region_i, + input logic [7:0] slv_ar_len_i, + input logic [2:0] slv_ar_size_i, + input logic [1:0] slv_ar_burst_i, + input logic slv_ar_lock_i, + input logic [3:0] slv_ar_cache_i, + input logic [3:0] slv_ar_qos_i, + input logic [AXI_ID_WIDTH-1:0] slv_ar_id_i, + input logic [AXI_USER_WIDTH-1:0] slv_ar_user_i, + output logic slv_ar_ready_o, + input logic slv_ar_valid_i, + + input logic [AXI_DATA_WIDTH-1:0] slv_w_data_i, + input logic [AXI_STRB_WIDTH-1:0] slv_w_strb_i, + input logic [AXI_USER_WIDTH-1:0] slv_w_user_i, + input logic slv_w_last_i, + output logic slv_w_ready_o, + input logic slv_w_valid_i, + + output logic [AXI_DATA_WIDTH-1:0] slv_r_data_o, + output logic [1:0] slv_r_resp_o, + output logic slv_r_last_o, + output logic [AXI_ID_WIDTH-1:0] slv_r_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_r_user_o, + input logic slv_r_ready_i, + output logic slv_r_valid_o, + + output logic [1:0] slv_b_resp_o, + output logic [AXI_ID_WIDTH-1:0] slv_b_id_o, + output logic [AXI_USER_WIDTH-1:0] slv_b_user_o, + input logic slv_b_ready_i, + output logic slv_b_valid_o, + + /// Master Interface + output logic [AXI_ADDR_WIDTH-1:0] mst_aw_addr_o, + output logic [2:0] mst_aw_prot_o, + output logic [3:0] mst_aw_region_o, + output logic [5:0] mst_aw_atop_o, + output logic [7:0] mst_aw_len_o, + output logic [2:0] mst_aw_size_o, + output logic [1:0] mst_aw_burst_o, + output logic mst_aw_lock_o, + output logic [3:0] mst_aw_cache_o, + output logic [3:0] mst_aw_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_aw_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_aw_user_o, + input logic mst_aw_ready_i, + output logic mst_aw_valid_o, + + output logic [AXI_ADDR_WIDTH-1:0] mst_ar_addr_o, + output logic [2:0] mst_ar_prot_o, + output logic [3:0] mst_ar_region_o, + output logic [7:0] mst_ar_len_o, + output logic [2:0] mst_ar_size_o, + output logic [1:0] mst_ar_burst_o, + output logic mst_ar_lock_o, + output logic [3:0] mst_ar_cache_o, + output logic [3:0] mst_ar_qos_o, + output logic [AXI_ID_WIDTH-1:0] mst_ar_id_o, + output logic [AXI_USER_WIDTH-1:0] mst_ar_user_o, + input logic mst_ar_ready_i, + output logic mst_ar_valid_o, + + output logic [AXI_DATA_WIDTH-1:0] mst_w_data_o, + output logic [AXI_STRB_WIDTH-1:0] mst_w_strb_o, + output logic [AXI_USER_WIDTH-1:0] mst_w_user_o, + output logic mst_w_last_o, + input logic mst_w_ready_i, + output logic mst_w_valid_o, + + input logic [AXI_DATA_WIDTH-1:0] mst_r_data_i, + input logic [1:0] mst_r_resp_i, + input logic mst_r_last_i, + input logic [AXI_ID_WIDTH-1:0] mst_r_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_r_user_i, + output logic mst_r_ready_o, + input logic mst_r_valid_i, + + input logic [1:0] mst_b_resp_i, + input logic [AXI_ID_WIDTH-1:0] mst_b_id_i, + input logic [AXI_USER_WIDTH-1:0] mst_b_user_i, + output logic mst_b_ready_o, + input logic mst_b_valid_i +); + + // Declarations of Signals and Types + + logic [AXI_ID_WIDTH-1:0] art_check_id, + art_set_id, + w_id_d, w_id_q; + + logic [AXI_ADDR_WIDTH-1:0] art_check_addr, + art_clr_addr, + art_set_addr, + rd_clr_addr, + wr_clr_addr, + w_addr_d, w_addr_q; + + logic art_check_req, art_check_gnt, + art_clr_req, art_clr_gnt, + art_set_req, art_set_gnt, + rd_clr_req, rd_clr_gnt, + wr_clr_req, wr_clr_gnt; + + logic art_check_res; + + logic b_excl_d, b_excl_q, + r_excl_d, r_excl_q; + + typedef enum logic [1:0] {R_IDLE, R_WAIT_AR, R_WAIT_R} r_state_t; + r_state_t r_state_d, r_state_q; + + typedef enum logic [2:0] {AW_IDLE, W_FORWARD, W_BYPASS, W_WAIT_ART_CLR, W_DROP, B_FORWARD, + B_INJECT} w_state_t; + w_state_t w_state_d, w_state_q; + + // AR and R Channel + + // Time-Invariant Signal Assignments + assign mst_ar_addr_o = slv_ar_addr_i; + assign mst_ar_prot_o = slv_ar_prot_i; + assign mst_ar_region_o = slv_ar_region_i; + assign mst_ar_len_o = slv_ar_len_i; + assign mst_ar_size_o = slv_ar_size_i; + assign mst_ar_burst_o = slv_ar_burst_i; + assign mst_ar_lock_o = 1'b0; + assign mst_ar_cache_o = slv_ar_cache_i; + assign mst_ar_qos_o = slv_ar_qos_i; + assign mst_ar_id_o = slv_ar_id_i; + assign mst_ar_user_o = slv_ar_user_i; + assign slv_r_data_o = mst_r_data_i; + assign slv_r_last_o = mst_r_last_i; + assign slv_r_id_o = mst_r_id_i; + assign slv_r_user_o = mst_r_user_i; + + // FSM for Time-Variant Signal Assignments + always_comb begin + mst_ar_valid_o = 1'b0; + slv_ar_ready_o = 1'b0; + mst_r_ready_o = 1'b0; + slv_r_valid_o = 1'b0; + slv_r_resp_o = '0; + art_set_addr = '0; + art_set_id = '0; + art_set_req = 1'b0; + rd_clr_addr = '0; + rd_clr_req = 1'b0; + r_excl_d = r_excl_q; + r_state_d = r_state_q; + + case (r_state_q) + + R_IDLE: begin + if (slv_ar_valid_i) begin + if (slv_ar_addr_i >= ADDR_BEGIN && slv_ar_addr_i <= ADDR_END && slv_ar_lock_i && + slv_ar_len_i == 8'h00) begin + // Inside exclusively-accessible address range and exclusive access and no + // burst + art_set_addr = slv_ar_addr_i; + art_set_id = slv_ar_id_i; + art_set_req = 1'b1; + r_excl_d = 1'b1; + if (art_set_gnt) begin + mst_ar_valid_o = 1'b1; + if (mst_ar_ready_i) begin + slv_ar_ready_o = 1'b1; + r_state_d = R_WAIT_R; + end else begin + r_state_d = R_WAIT_AR; + end + end + end else begin + // Outside exclusively-accessible address range or regular access or burst + r_excl_d = 1'b0; + mst_ar_valid_o = 1'b1; + if (mst_ar_ready_i) begin + slv_ar_ready_o = 1'b1; + r_state_d = R_WAIT_R; + end else begin + r_state_d = R_WAIT_AR; + end + end + end + end + + R_WAIT_AR: begin + mst_ar_valid_o = slv_ar_valid_i; + slv_ar_ready_o = mst_ar_ready_i; + if (mst_ar_ready_i && mst_ar_valid_o) begin + r_state_d = R_WAIT_R; + end + end + + R_WAIT_R: begin + mst_r_ready_o = slv_r_ready_i; + slv_r_valid_o = mst_r_valid_i; + if (mst_r_resp_i[1] == 1'b0) begin + slv_r_resp_o = {1'b0, r_excl_q}; + end else begin + slv_r_resp_o = mst_r_resp_i; + end + if (mst_r_valid_i && mst_r_ready_o && mst_r_last_i) begin + r_excl_d = 1'b0; + r_state_d = R_IDLE; + end + end + + default: begin + r_state_d = R_IDLE; + end + endcase + end + + // AW, W and B Channel + + // Time-Invariant Signal Assignments + assign mst_aw_addr_o = slv_aw_addr_i; + assign mst_aw_prot_o = slv_aw_prot_i; + assign mst_aw_region_o = slv_aw_region_i; + assign mst_aw_atop_o = slv_aw_atop_i; + assign mst_aw_len_o = slv_aw_len_i; + assign mst_aw_size_o = slv_aw_size_i; + assign mst_aw_burst_o = slv_aw_burst_i; + assign mst_aw_lock_o = 1'b0; + assign mst_aw_cache_o = slv_aw_cache_i; + assign mst_aw_qos_o = slv_aw_qos_i; + assign mst_aw_id_o = slv_aw_id_i; + assign mst_aw_user_o = slv_aw_user_i; + assign mst_w_data_o = slv_w_data_i; + assign mst_w_strb_o = slv_w_strb_i; + assign mst_w_user_o = slv_w_user_i; + assign mst_w_last_o = slv_w_last_i; + + always_comb begin + w_addr_d = w_addr_q; + w_id_d = w_id_q; + if (slv_aw_valid_i && slv_aw_ready_o) begin + w_addr_d = slv_aw_addr_i; + w_id_d = slv_aw_id_i; + end + end + + // FSM for Time-Variant Signal Assignments + always_comb begin + mst_aw_valid_o = 1'b0; + slv_aw_ready_o = 1'b0; + mst_w_valid_o = 1'b0; + slv_w_ready_o = 1'b0; + slv_b_valid_o = 1'b0; + mst_b_ready_o = 1'b0; + slv_b_resp_o = '0; + slv_b_id_o = '0; + slv_b_user_o = '0; + art_check_addr = '0; + art_check_id = '0; + art_check_req = 1'b0; + wr_clr_addr = '0; + wr_clr_req = 1'b0; + b_excl_d = b_excl_q; + w_state_d = w_state_q; + + case (w_state_q) + + AW_IDLE: begin + if (slv_aw_valid_i) begin + // New AW, and W channel is idle + if (slv_aw_addr_i >= ADDR_BEGIN && slv_aw_addr_i <= ADDR_END) begin + // Inside exclusively-accessible address range + if (slv_aw_lock_i && slv_aw_len_i == 8'h00) begin + // Exclusive access and no burst, so check if reservation exists + art_check_addr = slv_aw_addr_i; + art_check_id = slv_aw_id_i; + art_check_req = 1'b1; + if (art_check_gnt) begin + if (art_check_res) begin + // Yes, so forward downstream + mst_aw_valid_o = 1'b1; + if (mst_aw_ready_i) begin + slv_aw_ready_o = 1'b1; + b_excl_d = 1'b1; + w_state_d = W_FORWARD; + end + end else begin + // No, drop in W channel. + slv_aw_ready_o = 1'b1; + w_state_d = W_DROP; + end + end + end else begin + // Non-exclusive access or burst, so forward downstream + mst_aw_valid_o = 1'b1; + if (mst_aw_ready_i) begin + slv_aw_ready_o = 1'b1; + w_state_d = W_FORWARD; + end + end + end else begin + // Outside exclusively-accessible address range, so bypass any + // modifications. + mst_aw_valid_o = 1'b1; + slv_aw_ready_o = mst_aw_ready_i; + if (slv_aw_ready_o) begin + w_state_d = W_BYPASS; + end + end + end + end + + W_FORWARD: begin + mst_w_valid_o = slv_w_valid_i; + slv_w_ready_o = mst_w_ready_i; + if (slv_w_valid_i && slv_w_ready_o && slv_w_last_i) begin + wr_clr_addr = w_addr_q; + wr_clr_req = 1'b1; + if (wr_clr_gnt) begin + w_state_d = B_FORWARD; + end else begin + w_state_d = W_WAIT_ART_CLR; + end + end + end + + W_BYPASS: begin + mst_w_valid_o = slv_w_valid_i; + slv_w_ready_o = mst_w_ready_i; + if (slv_w_valid_i && slv_w_ready_o && slv_w_last_i) begin + w_state_d = B_FORWARD; + end + end + + W_WAIT_ART_CLR: begin + wr_clr_addr = w_addr_q; + wr_clr_req = 1'b1; + if (wr_clr_gnt) begin + w_state_d = B_FORWARD; + end + end + + W_DROP: begin + slv_w_ready_o = 1'b1; + if (slv_w_valid_i && slv_w_last_i) begin + w_state_d = B_INJECT; + end + end + + B_FORWARD: begin + mst_b_ready_o = slv_b_ready_i; + slv_b_valid_o = mst_b_valid_i; + slv_b_resp_o[1] = mst_b_resp_i[1]; + slv_b_resp_o[0] = (mst_b_resp_i[1] == 1'b0) ? b_excl_q : mst_b_resp_i[0]; + slv_b_user_o = mst_b_user_i; + slv_b_id_o = mst_b_id_i; + if (slv_b_valid_o && slv_b_ready_i) begin + b_excl_d = 1'b0; + w_state_d = AW_IDLE; + end + end + + B_INJECT: begin + slv_b_id_o = w_id_q; + slv_b_resp_o = 2'b00; + slv_b_valid_o = 1'b1; + if (slv_b_ready_i) begin + w_state_d = AW_IDLE; + end + end + + default: begin + w_state_d = AW_IDLE; + end + endcase + end + + // AXI Reservation Table + axi_res_tbl #( + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH) + ) i_art ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clr_addr_i (art_clr_addr), + .clr_req_i (art_clr_req), + .clr_gnt_o (art_clr_gnt), + .set_addr_i (art_set_addr), + .set_id_i (art_set_id), + .set_req_i (art_set_req), + .set_gnt_o (art_set_gnt), + .check_addr_i (art_check_addr), + .check_id_i (art_check_id), + .check_res_o (art_check_res), + .check_req_i (art_check_req), + .check_gnt_o (art_check_gnt) + ); + + // ART Clear Arbiter + stream_arbiter #( + .DATA_T (logic[AXI_ADDR_WIDTH-1:0]), + .N_INP (2) + ) i_non_excl_acc_arb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .inp_data_i ({rd_clr_addr, wr_clr_addr}), + .inp_valid_i ({rd_clr_req, wr_clr_req}), + .inp_ready_o ({rd_clr_gnt, wr_clr_gnt}), + .oup_data_o (art_clr_addr), + .oup_valid_o (art_clr_req), + .oup_ready_i (art_clr_gnt) + ); + + // Registers + always_ff @(posedge clk_i, negedge rst_ni) begin + if (~rst_ni) begin + b_excl_q <= 1'b0; + r_excl_q <= 1'b0; + r_state_q <= R_IDLE; + w_addr_q <= '0; + w_id_q <= '0; + w_state_q <= AW_IDLE; + end else begin + b_excl_q <= b_excl_d; + r_excl_q <= r_excl_d; + r_state_q <= r_state_d; + w_addr_q <= w_addr_d; + w_id_q <= w_id_d; + w_state_q <= w_state_d; + end + end + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (ADDR_END > ADDR_BEGIN) + else $fatal(1, "ADDR_END must be greater than ADDR_BEGIN!"); + assert (AXI_ADDR_WIDTH > 0) + else $fatal(1, "AXI_ADDR_WIDTH must be greater than 0!"); + assert (AXI_DATA_WIDTH > 0) + else $fatal(1, "AXI_DATA_WIDTH must be greater than 0!"); + assert (AXI_ID_WIDTH > 0) + else $fatal(1, "AXI_ID_WIDTH must be greater than 0!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv new file mode 100644 index 00000000000..3eb409bf35f --- /dev/null +++ b/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv @@ -0,0 +1,148 @@ +// Copyright (c) 2018 ETH Zurich, University of Bologna +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Wrapper for the AXI RISC-V LR/SC Adapter that exposes AXI SystemVerilog interfaces. +// +// See the header of `axi_riscv_lrsc` for a description. +// +// Maintainer: Andreas Kurth + +module axi_riscv_lrsc_wrap #( + /// Exclusively-accessible address range (closed interval from ADDR_BEGIN to ADDR_END) + parameter longint unsigned ADDR_BEGIN = 0, + parameter longint unsigned ADDR_END = 0, + /// AXI Parameters + parameter int unsigned AXI_ADDR_WIDTH = 0, + parameter int unsigned AXI_DATA_WIDTH = 0, + parameter int unsigned AXI_ID_WIDTH = 0, + parameter int unsigned AXI_USER_WIDTH = 0, + /// Derived Parameters (do NOT change manually!) + localparam int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8 +) ( + input logic clk_i, + input logic rst_ni, + AXI_BUS.Master mst, + AXI_BUS.Slave slv +); + + axi_riscv_lrsc #( + .ADDR_BEGIN (ADDR_BEGIN), + .ADDR_END (ADDR_END), + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_USER_WIDTH (AXI_USER_WIDTH) + ) i_lrsc ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_aw_addr_i ( slv.aw_addr ), + .slv_aw_prot_i ( slv.aw_prot ), + .slv_aw_region_i ( slv.aw_region ), + .slv_aw_atop_i ( slv.aw_atop ), + .slv_aw_len_i ( slv.aw_len ), + .slv_aw_size_i ( slv.aw_size ), + .slv_aw_burst_i ( slv.aw_burst ), + .slv_aw_lock_i ( slv.aw_lock ), + .slv_aw_cache_i ( slv.aw_cache ), + .slv_aw_qos_i ( slv.aw_qos ), + .slv_aw_id_i ( slv.aw_id ), + .slv_aw_user_i ( slv.aw_user ), + .slv_aw_ready_o ( slv.aw_ready ), + .slv_aw_valid_i ( slv.aw_valid ), + .slv_ar_addr_i ( slv.ar_addr ), + .slv_ar_prot_i ( slv.ar_prot ), + .slv_ar_region_i ( slv.ar_region ), + .slv_ar_len_i ( slv.ar_len ), + .slv_ar_size_i ( slv.ar_size ), + .slv_ar_burst_i ( slv.ar_burst ), + .slv_ar_lock_i ( slv.ar_lock ), + .slv_ar_cache_i ( slv.ar_cache ), + .slv_ar_qos_i ( slv.ar_qos ), + .slv_ar_id_i ( slv.ar_id ), + .slv_ar_user_i ( slv.ar_user ), + .slv_ar_ready_o ( slv.ar_ready ), + .slv_ar_valid_i ( slv.ar_valid ), + .slv_w_data_i ( slv.w_data ), + .slv_w_strb_i ( slv.w_strb ), + .slv_w_user_i ( slv.w_user ), + .slv_w_last_i ( slv.w_last ), + .slv_w_ready_o ( slv.w_ready ), + .slv_w_valid_i ( slv.w_valid ), + .slv_r_data_o ( slv.r_data ), + .slv_r_resp_o ( slv.r_resp ), + .slv_r_last_o ( slv.r_last ), + .slv_r_id_o ( slv.r_id ), + .slv_r_user_o ( slv.r_user ), + .slv_r_ready_i ( slv.r_ready ), + .slv_r_valid_o ( slv.r_valid ), + .slv_b_resp_o ( slv.b_resp ), + .slv_b_id_o ( slv.b_id ), + .slv_b_user_o ( slv.b_user ), + .slv_b_ready_i ( slv.b_ready ), + .slv_b_valid_o ( slv.b_valid ), + .mst_aw_addr_o ( mst.aw_addr ), + .mst_aw_prot_o ( mst.aw_prot ), + .mst_aw_region_o ( mst.aw_region ), + .mst_aw_atop_o ( mst.aw_atop ), + .mst_aw_len_o ( mst.aw_len ), + .mst_aw_size_o ( mst.aw_size ), + .mst_aw_burst_o ( mst.aw_burst ), + .mst_aw_lock_o ( mst.aw_lock ), + .mst_aw_cache_o ( mst.aw_cache ), + .mst_aw_qos_o ( mst.aw_qos ), + .mst_aw_id_o ( mst.aw_id ), + .mst_aw_user_o ( mst.aw_user ), + .mst_aw_ready_i ( mst.aw_ready ), + .mst_aw_valid_o ( mst.aw_valid ), + .mst_ar_addr_o ( mst.ar_addr ), + .mst_ar_prot_o ( mst.ar_prot ), + .mst_ar_region_o ( mst.ar_region ), + .mst_ar_len_o ( mst.ar_len ), + .mst_ar_size_o ( mst.ar_size ), + .mst_ar_burst_o ( mst.ar_burst ), + .mst_ar_lock_o ( mst.ar_lock ), + .mst_ar_cache_o ( mst.ar_cache ), + .mst_ar_qos_o ( mst.ar_qos ), + .mst_ar_id_o ( mst.ar_id ), + .mst_ar_user_o ( mst.ar_user ), + .mst_ar_ready_i ( mst.ar_ready ), + .mst_ar_valid_o ( mst.ar_valid ), + .mst_w_data_o ( mst.w_data ), + .mst_w_strb_o ( mst.w_strb ), + .mst_w_user_o ( mst.w_user ), + .mst_w_last_o ( mst.w_last ), + .mst_w_ready_i ( mst.w_ready ), + .mst_w_valid_o ( mst.w_valid ), + .mst_r_data_i ( mst.r_data ), + .mst_r_resp_i ( mst.r_resp ), + .mst_r_last_i ( mst.r_last ), + .mst_r_id_i ( mst.r_id ), + .mst_r_user_i ( mst.r_user ), + .mst_r_ready_o ( mst.r_ready ), + .mst_r_valid_i ( mst.r_valid ), + .mst_b_resp_i ( mst.b_resp ), + .mst_b_id_i ( mst.b_id ), + .mst_b_user_i ( mst.b_user ), + .mst_b_ready_o ( mst.b_ready ), + .mst_b_valid_i ( mst.b_valid ) + ); + + // Validate parameters. +// pragma translate_off +`ifndef VERILATOR + initial begin: validate_params + assert (AXI_STRB_WIDTH == AXI_DATA_WIDTH/8) + else $fatal(1, "AXI_STRB_WIDTH must equal AXI_DATA_WIDTH/8!"); + end +`endif +// pragma translate_on + +endmodule diff --git a/vendor/pulp-platform/common_cells/CHANGELOG.md b/vendor/pulp-platform/common_cells/CHANGELOG.md index 8513988e400..c4fcb52c708 100644 --- a/vendor/pulp-platform/common_cells/CHANGELOG.md +++ b/vendor/pulp-platform/common_cells/CHANGELOG.md @@ -71,8 +71,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - `addr_decode`: Use `cf_math_pkg::idx_width` for computing the index width, inline documentation. - `lzc`: Use `cf_math_pkg::idx_width` for computing the index width, inline documentation. - `Bender`: Change levels of modules affected by depending on `cf_math_pkg::idx_width()`. -- `stream_xbar`: Fully connected stream bassed interconnect with variable number of inputs and outputs. -- `stream_xbar`: Fully connected stream-bassed interconnect with a variable number of inputs and outputs. +- `stream_xbar`: Fully connected stream based interconnect with variable number of inputs and outputs. +- `stream_xbar`: Fully connected stream-based interconnect with a variable number of inputs and outputs. - `stream_omega_net`: Stream-based network implementing an omega topology. Variable number of inputs, outputs and radix. Topology is isomorphic to a butterfly network. @@ -128,8 +128,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## 1.14.0 - 2019-10-08 ### Added -- Added spubstitution-permutation hash function module -- Added couning-bloom-filter module +- Added substitution-permutation hash function module +- Added counting-bloom-filter module - `spill_register`: Added Bypass parameter - `counter`: Added sticky overflow - Added counter with variable delta diff --git a/vendor/pulp-platform/fpga-support/README.md b/vendor/pulp-platform/fpga-support/README.md index da5f9c5edcb..58c5da229a0 100644 --- a/vendor/pulp-platform/fpga-support/README.md +++ b/vendor/pulp-platform/fpga-support/README.md @@ -15,7 +15,7 @@ behavioral and post-synthesis simulations, set the `CF_MATH_PKG_PATH` environmen path where you have that package installed. Add all files in the `rtl/` folder to the list of compilation files of your development tool (e.g., -Xilinx Vivado). Read the documentation (header of the source file) of the block that you want to +Xilinx Vivado 2018.2). Read the documentation (header of the source file) of the block that you want to use and use the block as described there. ## Contributing diff --git a/vendor/pulp-platform_axi_riscv_atomics.lock.hjson b/vendor/pulp-platform_axi_riscv_atomics.lock.hjson new file mode 100644 index 00000000000..e27d8bc51d3 --- /dev/null +++ b/vendor/pulp-platform_axi_riscv_atomics.lock.hjson @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file is generated by the util/vendor script. Please do not modify it +// manually. + +{ + upstream: + { + url: https://github.com/pulp-platform/axi_riscv_atomics.git + rev: 550881f12e22dfae405612fc1df6368f4c003e68 + } +} diff --git a/vendor/pulp-platform_axi_riscv_atomics.vendor.hjson b/vendor/pulp-platform_axi_riscv_atomics.vendor.hjson new file mode 100644 index 00000000000..b2c022cc8d4 --- /dev/null +++ b/vendor/pulp-platform_axi_riscv_atomics.vendor.hjson @@ -0,0 +1,31 @@ +// -*- coding: utf-8 -*- +// Copyright (C) 2025 Thales DIS France SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +// Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) + +{ + // Name of the project + name: "pulp_axi_riscv_atomics", + + // Target directory: relative to the location of this script. + target_dir: "pulp-platform/axi_riscv_atomics", + + // Upstream repository + upstream: { + // URL + url: "https://github.com/pulp-platform/axi_riscv_atomics.git", + // revision + rev: "550881f12e22dfae405612fc1df6368f4c003e68", + } + + // Patch dir for local changes + patch_dir: "patches/pulp-platform/axi_riscv_atomics", + + // Exclusions from upstream content + exclude_from_upstream: [ + ".editorconfig", + ".git", + "Bender.yml", + "test", + ] +} diff --git a/verif/bsp/README.md b/verif/bsp/README.md index 8e6d5d44c6b..531cfdb6a43 100644 --- a/verif/bsp/README.md +++ b/verif/bsp/README.md @@ -101,7 +101,7 @@ The following exception handlers may be called from `u_sw_irq_handler`: entered" * `unknown_handler` - called when there is no handler for the interrupt/ exception. This is the only case where `mepc` is not incremented, because we - do not know the appropiate action to take. + do not know the appropriate action to take. Returning from the `u_sw_irq_handler`. All handlers called by `u_sw_irq_handler` increment `mepc` before calling `mret`, except for `unknown_handler`. Handlers diff --git a/verif/core-v-verif b/verif/core-v-verif index 60e57248c48..b3149ab0da3 160000 --- a/verif/core-v-verif +++ b/verif/core-v-verif @@ -1 +1 @@ -Subproject commit 60e57248c48b0f8f90cf52af20aecc5c16e9d6d8 +Subproject commit b3149ab0da3ac8bf2179e24595a4b7a860b668ff diff --git a/verif/docs/VerifPlans/FENCEI/VP_IP002.yml b/verif/docs/VerifPlans/FENCEI/VP_IP002.yml index 5d438577531..5802629bd77 100644 --- a/verif/docs/VerifPlans/FENCEI/VP_IP002.yml +++ b/verif/docs/VerifPlans/FENCEI/VP_IP002.yml @@ -196,8 +196,8 @@ subfeatures: !!omap cores: 56 coverage_loc: '' comments: '' -- 007_AckWithold: !Subfeature - name: 007_AckWithold +- 007_AckWithhold: !Subfeature + name: 007_AckWithhold tag: VP_FENCEI_F002_S007 next_elt_id: 1 display_order: 7 @@ -212,7 +212,7 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: firefox - verif_goals: Upon a req, try witholding ack for a long time and see that the + verif_goals: Upon a req, try withholding ack for a long time and see that the fence.i can be stalled arbitrarily long (should have covers for ack delays of at least {[0:5]}). pfc: 4 diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml index ce490437ac2..d5eface3419 100644 --- a/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml @@ -396,7 +396,7 @@ subfeatures: !!omap - '000': !VerifItem name: '000' tag: VP_ISA_RV32_F000_S006_I000 - description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shifted\ \ into lower bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -415,7 +415,7 @@ subfeatures: !!omap - '001': !VerifItem name: '001' tag: VP_ISA_RV32_F000_S006_I001 - description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shifted\ \ into lower bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -435,7 +435,7 @@ subfeatures: !!omap - '002': !VerifItem name: '002' tag: VP_ISA_RV32_F000_S006_I002 - description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shirfted\ + description: "slli rd, rs, imm[4:0]\nrd = rs << imm[4:0]\nZeros are shifted\ \ into lower bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -459,7 +459,7 @@ subfeatures: !!omap - '000': !VerifItem name: '000' tag: VP_ISA_RV32_F000_S007_I000 - description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shifted\ \ into upper bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -478,7 +478,7 @@ subfeatures: !!omap - '001': !VerifItem name: '001' tag: VP_ISA_RV32_F000_S007_I001 - description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shifted\ \ into upper bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -498,7 +498,7 @@ subfeatures: !!omap - '002': !VerifItem name: '002' tag: VP_ISA_RV32_F000_S007_I002 - description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shifted\ \ into upper bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -561,7 +561,7 @@ subfeatures: !!omap - '002': !VerifItem name: '002' tag: VP_ISA_RV32_F000_S008_I002 - description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shirfted\ + description: "srli rd, rs, imm[4:0]\nrd = rs >> imm[4:0]\nZeros are shifted\ \ into upper bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml index 67a3f707d0f..af07cfabe30 100644 --- a/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml @@ -472,7 +472,7 @@ subfeatures: !!omap - '000': !VerifItem name: '000' tag: VP_ISA_RV32_F001_S007_I000 - description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shifted into\ \ lower bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -493,7 +493,7 @@ subfeatures: !!omap - '001': !VerifItem name: '001' tag: VP_ISA_RV32_F001_S007_I001 - description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shifted into\ \ lower bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -513,7 +513,7 @@ subfeatures: !!omap - '002': !VerifItem name: '002' tag: VP_ISA_RV32_F001_S007_I002 - description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shirfted into\ + description: "sll rd, rs1, rs2\nrd = rs1 << rs2[4:0]\nZeros are shifted into\ \ lower bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -538,7 +538,7 @@ subfeatures: !!omap - '000': !VerifItem name: '000' tag: VP_ISA_RV32_F001_S008_I000 - description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shifted into\ \ upper bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: page @@ -559,7 +559,7 @@ subfeatures: !!omap - '001': !VerifItem name: '001' tag: VP_ISA_RV32_F001_S008_I001 - description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shifted into\ \ upper bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -579,7 +579,7 @@ subfeatures: !!omap - '002': !VerifItem name: '002' tag: VP_ISA_RV32_F001_S008_I002 - description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + description: "srl rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shifted into\ \ upper bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' @@ -644,7 +644,7 @@ subfeatures: !!omap - '002': !VerifItem name: '002' tag: VP_ISA_RV32_F001_S009_I002 - description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shirfted into\ + description: "sra rd, rs1, rs2\nrd = rs1 >> rs2[4:0]\nZeros are shifted into\ \ upper bits" reqt_doc: ./RISCV_Instructions.rst ref_mode: '' diff --git a/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml b/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml index 11e6f403bad..afea799c7fe 100644 --- a/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml +++ b/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml @@ -74,7 +74,7 @@ subfeatures: !!omap ref_section: '' ref_viewer: firefox verif_goals: "Exception:\n\nMisaligned address (non-32-bit aligned) will always\ - \ cause exceptio" + \ cause exception" pfc: 3 test_type: 3 cov_method: 1 diff --git a/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml b/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml index 7149784d8c4..639663a2bbb 100644 --- a/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml +++ b/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml @@ -20,7 +20,7 @@ subfeatures: !!omap \ and non-reserved RWX permissions then test the following in supervisor\ \ and user privilege mode for level1 and level0 PTE.\n\n- Remove read PMP\ \ permission of translated Physical Address in pmpcfg and test the read\ - \ acces.\n- Remvoe write PMP permission of translated Physical Address in\ + \ access.\n- Remove write PMP permission of translated Physical Address in\ \ pmpcfg and test the write access.\n- Remove execute PMP permission of\ \ translated Physical Address in pmpcfg and test the execute access." reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter @@ -54,7 +54,7 @@ subfeatures: !!omap \ it would raise access fault exception of the corresponding access type.\ \ \nWhen satp.mode=sv32, then test the following in supervisor and user\ \ privilege mode for level0 and level1 PTE.\n- Remove read PMP permission\ - \ of PTE address in pmpcfg and test the read acces.\n- Remvoe write PMP\ + \ of PTE address in pmpcfg and test the read access.\n- Remove write PMP\ \ permission of PTE address in pmpcfg and test the write access.\n- Remove\ \ execute PMP permission of PTE address in pmpcfg and test the execute access." reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter @@ -88,12 +88,12 @@ subfeatures: !!omap \ it would raise page fault exception of the corresponding access type.\ \ \nWhen satp.mode=sv32 and PTE has (r,w,x) PMP permissions, then test the\ \ following in supervisor and user privilege mode for level0 and level1\ - \ PTE.\n- Set PTE.V = 0 and test the read acces.\n- Set PTE.V = 0 and test\ + \ PTE.\n- Set PTE.V = 0 and test the read access.\n- Set PTE.V = 0 and test\ \ the write access.\n- Set PTE.V = 0 and test the execute access.\n\n* For\ - \ testing at level0, set all the pte perimssions at level1 to 0 except pte.v,\ + \ testing at level0, set all the pte permissions at level1 to 0 except pte.v,\ \ so that level1 points to level0.\n* Set pte.U=0 when test in Supervisor\ \ mode and Set pte.U=1 when testing in user mode" - reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chpter + reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.2' ref_mode: '' ref_page: '' @@ -124,10 +124,10 @@ subfeatures: !!omap \ accessing it would raise page fault exception of the corresponding access\ \ type. \nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1,\ \ then test the following in supervisor and user privilege mode for level0\ - \ and level1 PTE.\n- Set pte.w=1 & pte.r=0 and test the read acces.\n- Set\ + \ and level1 PTE.\n- Set pte.w=1 & pte.r=0 and test the read access.\n- Set\ \ pte.w=1 & pte.r=0 and test the write access.\n- Set pte.w=1 & pte.r=0\ \ and test the execute access.\n\n* For testing at level0, set all the pte\ - \ perimssions at level1 to 0 except pte.v, so that level1 points to level0.\n\ + \ permissions at level1 to 0 except pte.v, so that level1 points to level0.\n\ * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing\ \ in user mode" reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter @@ -161,10 +161,10 @@ subfeatures: !!omap \ then accessing it would raise page fault exception of the corresponding\ \ access type. \nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions, and\ \ pte.v=1, then test the following in supervisor and user privilege mode\ - \ for level0 PTE.\n- Set pte.x=0 & pte.r=0 & pte.w=0 and test the read acces.\n\ + \ for level0 PTE.\n- Set pte.x=0 & pte.r=0 & pte.w=0 and test the read access.\n\ - Set pte.x=0 & pte.r=0 & pte.w=0 and test the write access.\n- Set pte.x=0\ \ & pte.r=0 & pte.w=0 and test the execute access.\n\n* For testing at level0,\ - \ set all the pte perimssions at level1 to 0 except pte.v, so that level1\ + \ set all the pte permissions at level1 to 0 except pte.v, so that level1\ \ points to level0.\n* Set pte.U=0 when test in Supervisor mode and Set\ \ pte.U=1 when testing in user mode" reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter @@ -203,7 +203,7 @@ subfeatures: !!omap \ privilege mode for level 0 and level 1 PTE.\n- Test the read access for\ \ both pte.r=1 and for pte.r=0\n- Test the write access for both pte.w=1\ \ and for pte.w=0\n- Test the execute access for both pte.x=1 and for pte.x=0\n\ - \n* For testing at level0, set all the pte perimssions at level1 to 0 except\ + \n* For testing at level0, set all the pte permissions at level1 to 0 except\ \ pte.v, so that level1 points to level0." reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.1' @@ -240,9 +240,9 @@ subfeatures: !!omap \ page fault exception of the corresponding access type. \nWhen satp.mode=sv32,\ \ PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, and\ \ pte.v=1, then test the following user privilege mode for level0 and level1\ - \ PTE.\n- Set pte.u=0 and test the read acces.\n- Set pte.u=0 and test the\ + \ PTE.\n- Set pte.u=0 and test the read access.\n- Set pte.u=0 and test the\ \ write access.\n- Set pte.u=0 and test the execute access.\n\n* For testing\ - \ at level0, set all the pte perimssions at level1 to 0 except pte.v, so\ + \ at level0, set all the pte permissions at level1 to 0 except pte.v, so\ \ that level1 points to level0." reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.2' @@ -276,9 +276,9 @@ subfeatures: !!omap \ \nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved\ \ RWX encoding, and pte.v=1, then test the following in supervisor mode\ \ for level 0 and level 1 PTE.\n- Set pte.u=1 & s/mstatus.SUM = 0 and test\ - \ the read acces.\n- Set pte.u=1 & s/mstatus.SUM = 0 and test the write\ + \ the read access.\n- Set pte.u=1 & s/mstatus.SUM = 0 and test the write\ \ access.\n- Set pte.u=1 & s/mstatus.SUM = 0 and test the execute access.\n\ - \n* For testing at level0, set all the pte perimssions at level1 to 0 except\ + \n* For testing at level0, set all the pte permissions at level1 to 0 except\ \ pte.v, so that level1 points to level0." reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.1.6.3, 5.3.2' @@ -313,10 +313,10 @@ subfeatures: !!omap \ fault exception in s-mode.\nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions,\ \ PTE has non-reserved RWX encoding, and pte.v=1, then test the following\ \ in supervisor mode for level0 and level1 PTE.\n- Set pte.r=1 & pte.u=1\ - \ & s/mstatus.SUM = 1 and test the read acces.\n- Set pte.w=1 & pte.u=1\ + \ & s/mstatus.SUM = 1 and test the read access.\n- Set pte.w=1 & pte.u=1\ \ & s/mstatus.SUM = 1 and test the write access.\n- Set pte.x=1 & pte.u=1\ \ & s/mstatus.SUM = 1 and test the execute access.\n\n* For testing at level0,\ - \ set all the pte perimssions at level1 to 0 except pte.v, so that level1\ + \ set all the pte permissions at level1 to 0 except pte.v, so that level1\ \ points to level0." reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter 3.1.6.3, 5.3.2' @@ -326,7 +326,7 @@ subfeatures: !!omap ref_viewer: '' verif_goals: "Read and Write access to the PTE should be successful. So, check\ \ that the load and store works without page fault and expected data is\ - \ stored to and loaded from the memory, repectively.\n\nExecute access should\ + \ stored to and loaded from the memory, respectively.\n\nExecute access should\ \ raise instruction page fault. Check that:\n- m/scause must contain the\ \ exception number of instruction instruction access fault. \n- m/sepc must\ \ contain the virtual address of the instruction at which the trap occurs." @@ -354,7 +354,7 @@ subfeatures: !!omap \ and level1 PTE.\n- Test the read access for both pte.r=1 and for pte.r=0\n\ - Test the write access for both pte.w=1 and for pte.w=0\n- Test the execute\ \ access for both pte.x=1 and for pte.x=0\n\n* For testing at level0, set\ - \ all the pte perimssions at level1 to 0 except pte.v, so that level1 points\ + \ all the pte permissions at level1 to 0 except pte.v, so that level1 points\ \ to level0." reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.2' @@ -390,7 +390,7 @@ subfeatures: !!omap When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then\ \ test the following in supervisor and user privilege mode for level0 and\ \ level1 PTE.\n- Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=0 and test\ - \ the read acces.\n\n* For testing at level0, set all the pte perimssions\ + \ the read access.\n\n* For testing at level0, set all the pte permissions\ \ at level1 to 0 except pte.v, so that level1 points to level0.\n* Set pte.U=0\ \ when test in Supervisor mode and Set pte.U=1 when testing in user mode" reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter @@ -423,7 +423,7 @@ subfeatures: !!omap \ read permission (pte.r=0).\nWhen satp.mode=sv32, PTE has (r,w,x) PMP permissions,\ \ and pte.v=1, then test the following in supervisor and user privilege\ \ mode for level0 and level1 PTE.\n- Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=1\ - \ and test the read acces.\n\n* For testing at level0, set all the pte perimssions\ + \ and test the read access.\n\n* For testing at level0, set all the pte permissions\ \ at level1 to 0 except pte.v, so that level1 points to level0.\n* Set pte.U=0\ \ when test in Supervisor mode and Set pte.U=1 when testing in user mode" reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter @@ -484,10 +484,10 @@ subfeatures: !!omap \ of the corresponding access type. \nWhen satp.mode=sv32, PTE has (r,w,x)\ \ PMP permissions, and pte.v=1, then test the following in supervisor and\ \ user privilege mode for level0 and level1 PTE. Execute sfence.vma before\ - \ accessign the PTE.\n- Set pte.r=1 & pte.a=0 and test the read acces. \n\ + \ accessing the PTE.\n- Set pte.r=1 & pte.a=0 and test the read access. \n\ - Set pte.w=1 & pte.a=0 and test the write access.\n- Set pte.x=1 & pte.a=0\ \ and test the execute access.\n\n* For testing at level0, set all the pte\ - \ perimssions at level1 to 0 except pte.v, so that level1 points to level0.\n\ + \ permissions at level1 to 0 except pte.v, so that level1 points to level0.\n\ * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing\ \ in user mode." reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter @@ -522,8 +522,8 @@ subfeatures: !!omap \ Store/AMO page fault exception.\nWhen satp.mode=sv32, PTE has (r,w,x)\ \ PMP permissions, pte.a=1 and pte.v=1, then test the following in supervisor\ \ and user privilege mode for level0 and level1 PTE. Execute sfence.vma\ - \ before accessign the PTE.\n- Set pte.w=1 & pte.d=0 and test the write\ - \ access.\n\n* For testing at level0, set all the pte perimssions at level1\ + \ before accessing the PTE.\n- Set pte.w=1 & pte.d=0 and test the write\ + \ access.\n\n* For testing at level0, set all the pte permissions at level1\ \ to 0 except pte.v, so that level1 points to level0.\n* Set pte.U=0 when\ \ test in Supervisor mode and Set pte.U=1 when testing in user mode." reqt_doc: 'ISA Volume II: Privilege Architecture Version 20211203, Chapter diff --git a/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml b/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml index 6ae361a877d..437d8baa8a0 100644 --- a/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml +++ b/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml @@ -70,7 +70,7 @@ subfeatures: !!omap ref_page: '' ref_section: '' ref_viewer: '' - verif_goals: Show wirting {zero, non-zero} value to satp when mode=bare the + verif_goals: Show writing {zero, non-zero} value to satp when mode=bare the behaviour follows the design implemention pfc: 3 test_type: 0 diff --git a/verif/docs/VerifPlans/PMP/VP_IP000.yml b/verif/docs/VerifPlans/PMP/VP_IP000.yml new file mode 100644 index 00000000000..8e7da47c6a5 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP000.yml @@ -0,0 +1,358 @@ +!Feature +next_elt_id: 15 +name: TRISTAN Restrictions +id: 0 +display_order: 0 +subfeatures: !!omap +- 000_general: !Subfeature + name: 000_general + tag: VP_PMP_F000_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S000_I000 + description: "\nthe verif plan is written for 32bits architecture only" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 001_number of harts: !Subfeature + name: 001_number of harts + tag: VP_PMP_F000_S001 + next_elt_id: 2 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S001_I000 + description: "\nthere is only 1 hart in cv32a6" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 002_mxlen: !Subfeature + name: 002_mxlen + tag: VP_PMP_F000_S002 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S002_I000 + description: "\nMXLEN is always 32bits" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 003_xlen: !Subfeature + name: 003_xlen + tag: VP_PMP_F000_S003 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S003_I000 + description: "\nXLEN=MXLEN=32, so the PMP address registers are XLEN bits + long, so no zero-extension needed" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 004_granularity: !Subfeature + name: 004_granularity + tag: VP_PMP_F000_S004 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S004_I000 + description: "\nPMP granularity is 8 bytes (G=1), but the verif plan is written + to take G=0 into account (NA4)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 005_number of pmp entries: !Subfeature + name: 005_number of pmp entries + tag: VP_PMP_F000_S005 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S005_I000 + description: "\nthere are 8 HW implemented PMP entries" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 006_hardwired regions: !Subfeature + name: 006_hardwired regions + tag: VP_PMP_F000_S006 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S006_I000 + description: "\nnone of the 8 PMP entries is hardwired privileges" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 007_virtual memory: !Subfeature + name: 007_virtual memory + tag: VP_PMP_F000_S007 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S007_I000 + description: "\nno virtual memory is implemented\nas a consequence no page-based + virtual memory is implemented" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 008_physical memory regions: !Subfeature + name: 008_physical memory regions + tag: VP_PMP_F000_S008 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S008_I000 + description: "\nthe list of all physical memory regions\n - system memory + regions\n - I-$\n - D-$\n - I-scratchpad (preload mode)\n - I-scratchpad + (functional mode)\n - D-scratchpad\n - ahb_periph" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 009_pmp entry disabling: !Subfeature + name: 009_pmp entry disabling + tag: VP_PMP_F000_S009 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S009_I000 + description: "\nwe assume an already written PMP entry (i) can be disabled\n\ + \ - if L=0, by clearing pmpcfg(i)\n - if L=1, only by hart reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 010_access-faults (violations): !Subfeature + name: 010_access-faults (violations) + tag: VP_PMP_F000_S010 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S010_I000 + description: "\nThe testbench/testcases architecture ensures that:\n - any + time there is an access-fault type, we check it matches the related access-type\n + - all violations are trapped at the processor\n\n{Page 56 Volume II: RISC-V + Privileged Architectures V20211203}\nPMP violations are always trapped precisely + at the processor" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 011_testcases modularity: !Subfeature + name: 011_testcases modularity + tag: VP_PMP_F000_S011 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S011_I000 + description: "\nThe verif plan is written assuming there is a way (like SystemVerilog + interaction):\n - to factorize the testcases in code blocks (in particular + configuration code block and access code block)\n - to randomize the code + blocks data and addresses\n - to randomize the sequence of code blocks" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 012_access types: !Subfeature + name: 012_access types + tag: VP_PMP_F000_S012 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S012_I000 + description: "at the time of writing,\nthe verif plan makes no distinction + between load and load-reserved instructions. they are gathered in the same + access type, subtleties unknown\nthe verif plan makes no distinction between + store, store-conditional, and AMO instructions. they are gathered in the + same access type, subtleties unknown" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 013_multiple accesses instructions: !Subfeature + name: 013_multiple accesses instructions + tag: VP_PMP_F000_S013 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S013_I000 + description: "\nwe assume there is no added value to test multiple accesses + instructions" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +- 014_misaligned instructions: !Subfeature + name: 014_misaligned instructions + tag: VP_PMP_F000_S014 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F000_S014_I000 + description: "\nwe assume that instructions are mandatorily aligned" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: '' + pfc: -1 + test_type: -1 + cov_method: -1 + cores: -1 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP001.yml b/verif/docs/VerifPlans/PMP/VP_IP001.yml new file mode 100644 index 00000000000..f7c912bdf8f --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP001.yml @@ -0,0 +1,45 @@ +!Feature +next_elt_id: 1 +name: PMP granularity +id: 1 +display_order: 1 +subfeatures: !!omap +- 000_granularity_check: !Subfeature + name: 000_granularity_check + tag: VP_PMP_F001_S000 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F001_S000_I000 + description: "{Page 59 Volume II: RISC-V Privileged Architectures V20211203}\n + \nSoftware may determine the PMP granularity by writing zero to pmp0cfg, + then writing all ones to pmpaddr0, then reading back pmpaddr0.\nIf G is + the index of the least-significant bit set, the PMP granularity is 2G+2 bytes." + reqt_doc: '' + ref_mode: page + ref_page: '59' + ref_section: '' + ref_viewer: evince + verif_goals: determine the PMP granularity 2^(G+2) bytes by writing zero to + pmp(0)cfg, then writing all ones to pmpaddr(0), then reading back pmpaddr(0). + G is the index G of the least-significant bit set + pfc: 11 + test_type: 2 + cov_method: 0 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR07-b\nSoftware may determine the PMP granularity + by writing zero to pmp0cfg, then writing all ones to pmpaddr0, then reading + back pmpaddr0.\n If G is the index of the least-significant bit set, the + PMP granularity is 2G+2 bytes.\n\n\nTST01 (HIGH-PRIO) => FTR07-b\n[determine + the PMP granularity 2^(G+2) bytes by writing zero to pmp(0)cfg, then writing + all ones to pmpaddr(0), then reading back pmpaddr(0). G is the index G of + the least-significant bit set]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP002.yml b/verif/docs/VerifPlans/PMP/VP_IP002.yml new file mode 100644 index 00000000000..82ecf96ce11 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP002.yml @@ -0,0 +1,159 @@ +!Feature +next_elt_id: 4 +name: CSRs M-mode only +id: 2 +display_order: 2 +subfeatures: !!omap +- 000_configure_1_pmp_entry: !Subfeature + name: 000_configure_1_pmp_entry + tag: VP_PMP_F002_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F002_S001_I000 + description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures + V20211203}\n\nPMP CSRs are only accessible to M-mode" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure 1 PMP entry (i) (the 1st one),\n - check for each + PMP entry (i) reset value (read zero) by reading in M mode\n - check for + each PMP entry (i) that pmp(i)cfg and pmpaddr(i) are not writable/readable + in S or U modes\n - check for each PMP entry (i) that pmp(i)cfg and pmpaddr(i) + are writable/readable in M-mode only\n - check for each PMP entry (i) that + pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST02(group) => FTR02-d\n [check that all 8 HW implemented + PMP entries are writable/readable in M-mode (L=0)]\n [check that no HW + implemented PMP entry are writable/readable in S or U modes (L=0)]\n \ + \ - random values may be used\n - before any configuration (after hart + reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST02-1 + (HIGH-PRIO)\n[configure 1 PMP entry ([FTR02-b1]: maybe mandatorily the first + one): with L=0,\n - if possible, the PMP entry number is a configurable + parameter\n - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) + are not writable/readable in S or U modes\n - check for PMP entry (i) where + L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only\n\ + \ - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are + not writable/readable in S or U modes]" +- 001_configure_2_pmp_entries: !Subfeature + name: 001_configure_2_pmp_entries + tag: VP_PMP_F002_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F002_S002_I000 + description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures + V20211203}\n\nPMP CSRs are only accessible to M-mode" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure 2 PMP entries (the 2 first ones in incrementing order),\n\ + \ - reuse of VP_PMP_F002_S001_I000 sequence" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST02(group) => FTR02-d\n [check that all 8 HW implemented + PMP entries are writable/readable in M-mode (L=0)]\n [check that no HW + implemented PMP entry are writable/readable in S or U modes (L=0)]\n \ + \ - random values may be used\n - before any configuration (after hart + reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST02-2 + (LOW-PRIO) = 2 times reuse/call of TST02-1\n[configure 2 PMP entries ([FTR02-b1]: + maybe mandatorily the 2 first ones): both with L=0,\n - check for PMP entry + (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in + S or U modes\n - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) + are writable/readable in M-mode only\n - check for PMP entry (i) where + L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes]" +- 002_configure_N_pmp_entries: !Subfeature + name: 002_configure_N_pmp_entries + tag: VP_PMP_F002_S003 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F002_S003_I000 + description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures + V20211203}\n\nPMP CSRs are only accessible to M-mode" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure N PMP entries (the N first ones in incrementing order),\n\ + \ - reuse of VP_PMP_F002_S001_I000 sequence" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST02(group) => FTR02-d\n [check that all 8 HW implemented + PMP entries are writable/readable in M-mode (L=0)]\n [check that no HW + implemented PMP entry are writable/readable in S or U modes (L=0)]\n \ + \ - random values may be used\n - before any configuration (after hart + reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST02-3 + (LOW-PRIO) = N times reuse/call of TST02-1\n[configure N PMP entries ([FTR02-b1]: + maybe mandatorily the N first ones): all with L=0,\n - check for PMP entry + (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in + S or U modes\n - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) + are writable/readable in M-mode only\n - check for PMP entry (i) where + L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes]" +- 003_configure_8_pmp_entries: !Subfeature + name: 003_configure_8_pmp_entries + tag: VP_PMP_F002_S004 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F002_S004_I000 + description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures + V20211203}\n\nPMP CSRs are only accessible to M-mode" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure all 8 PMP entries (in incrementing order),\n - reuse + of VP_PMP_F002_S001_I000 sequence" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST02(group) => FTR02-d\n [check that all 8 HW implemented + PMP entries are writable/readable in M-mode (L=0)]\n [check that no HW + implemented PMP entry are writable/readable in S or U modes (L=0)]\n \ + \ - random values may be used\n - before any configuration (after hart + reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST02-4 + (HIGH-PRIO) = 8 times reuse/call of TST02-1\n[configure 8 PMP entries: all + with L=0,\n - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) + are not writable/readable in S or U modes\n - check for PMP entry (i) where + L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only\n\ + \ - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are + not writable/readable in S or U modes]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP003.yml b/verif/docs/VerifPlans/PMP/VP_IP003.yml new file mode 100644 index 00000000000..dbc0945d8bd --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP003.yml @@ -0,0 +1,277 @@ +!Feature +next_elt_id: 5 +name: CSRs locked access +id: 3 +display_order: 3 +subfeatures: !!omap +- 000_configure_1_pmp_entry: !Subfeature + name: 000_configure_1_pmp_entry + tag: VP_PMP_F003_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F003_S001_I000 + description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP + entry is locked, i.e., writes to the configuration register and associated + address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg + and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart + is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: + RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the + PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry + (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are + ignored" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure 1 PMP entry (the 1st one) with L=1,\n - write PMP + entry (i) with L=1 in M-mode\n - A is random, should also be tried with + A=OFF when L=1 (to cover feature above)\n - check PMP entry (i) written + value in M-mode\n - check for PMP entry (i) where L=1 that pmp(i)cfg and + pmpaddr(i) are effectively locked (M-mode check only)\n - also check for + PMP entry (i) where L=1 and pmp(i)cfg.A=TOR that pmpaddr(i-1) is effectively + locked\n - apply hart reset\n - check for PMP entry (i) reset value (read + zero) by reading in M mode\n - write PMP entry (i) in M-mode\n - check + PMP entry (i) written value in M-mode\n\nREUSABILITY\n - if possible, the + PMP entry number (i) is a configurable parameter\n - if possible, (L) value + is a configurable parameter\n - so the same sub-functions are reused with + varying (i) and (L) parameters" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n [check that HW + implemented PMP entries are not writable/readable in M-mode (L=1)]\n [check + that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\ + \ - before any configuration, check all pmp(i)cfg and pmpaddr(i) are + M-mode read zero\n - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg + and pmpaddr(i) maybe random values\n - execute following tests specific + checks\n - check only hart reset unlocks all => FTR08-b\n - check + reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-1 + (HIGH-PRIO)\n[configure 1 PMP entry ([FTR02-b1]: maybe mandatorily the first + one): with L=1,\n - if possible, the PMP entry number is a configurable + parameter\n - if possible, L value is a configurable parameter\n - check + for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively + locked whatever the SW mode => FTR08-a\n - check for PMP entry (i) where + L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes]" +- 001_configure_2_pmp_entries_L1: !Subfeature + name: 001_configure_2_pmp_entries_L1 + tag: VP_PMP_F003_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F003_S002_I000 + description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP + entry is locked, i.e., writes to the configuration register and associated + address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg + and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart + is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: + RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the + PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry + (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are + ignored" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure 2 PMP entries (the 2 first ones in incrementing order) + with L=1,\n - reuse of VP_PMP_F003_S001_I000 sequence" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n [check that HW + implemented PMP entries are not writable/readable in M-mode (L=1)]\n [check + that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\ + \ - before any configuration, check all pmp(i)cfg and pmpaddr(i) are + M-mode read zero\n - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg + and pmpaddr(i) maybe random values\n - execute following tests specific + checks\n - check only hart reset unlocks all => FTR08-b\n - check + reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-2 + (LOW-PRIO) = 2 times reuse/call of TST02-1\n[configure 2 PMP entries ([FTR02-b1]: + maybe mandatorily the 2 first ones): both with L=1,\n - check for PMP entry + (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever + the SW mode => FTR08-a\n - check for PMP entry (i) where L=1 that pmp(i)cfg + and pmpaddr(i) are not writable/readable in S or U modes]" +- 002_configure_2_pmp_entries_L0_L1: !Subfeature + name: 002_configure_2_pmp_entries_L0_L1 + tag: VP_PMP_F003_S003 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F003_S003_I000 + description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP + entry is locked, i.e., writes to the configuration register and associated + address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg + and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart + is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: + RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the + PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry + (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are + ignored" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure 2 PMP entries (the 2 first ones in incrementing order) + at least one with L=1 and one with L=0,\n - write PMP entry (i) with L=0/1 + in M-mode\n - A is random, should also be tried with A=OFF when L=1 (to + cover feature above)\n - check PMP entry (i) written value in M-mode\n\ + \ - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are + writable in M mode (read back the written value in M mode)\n - check for + PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked + (M-mode check only)\n - also check for PMP entry (i) where L=1 and pmp(i)cfg.A=TOR + that pmpaddr(i-1) is effectively locked\n - apply hart reset\n - check + for PMP entry (i) reset value (read zero) by reading in M mode\n - write + PMP entry (i) in M-mode\n - check PMP entry (i) written value in M-mode\n\ + \nREUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, (L) value is a configurable parameter\n - so + the same sub-functions are reused with varying (i) and (L) parameters" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n [check that HW + implemented PMP entries are not writable/readable in M-mode (L=1)]\n [check + that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\ + \ - before any configuration, check all pmp(i)cfg and pmpaddr(i) are + M-mode read zero\n - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg + and pmpaddr(i) maybe random values\n - execute following tests specific + checks\n - check only hart reset unlocks all => FTR08-b\n - check + reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-3 + (HIGH-PRIO) = 2 times reuse/call of TST02-1\n[configure 2 PMP entries ([FTR02-b1]: + maybe mandatorily the 2 first ones): one with L=1 and one with L=0,\n - + check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively + locked whatever the SW mode => FTR08-a\n - check for PMP entry (i) where + L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes\n\ + \ - check locked PMP entry (i) has no effect on unlocked PMP entry (j)\n\ + \ - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are + writable/readable in M-mode only\n - check for PMP entry (i) where L=0 + that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes]" +- 003_configure_N_pmp_entries: !Subfeature + name: 003_configure_N_pmp_entries + tag: VP_PMP_F003_S004 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F003_S004_I000 + description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP + entry is locked, i.e., writes to the configuration register and associated + address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg + and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart + is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: + RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the + PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry + (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are + ignored" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure N PMP entries (the N first ones in incrementing order) + at least one with L=1 and one with L=0,\n - reuse of VP_PMP_F003_S003_I000 + sequence" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n [check that HW + implemented PMP entries are not writable/readable in M-mode (L=1)]\n [check + that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\ + \ - before any configuration, check all pmp(i)cfg and pmpaddr(i) are + M-mode read zero\n - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg + and pmpaddr(i) maybe random values\n - execute following tests specific + checks\n - check only hart reset unlocks all => FTR08-b\n - check + reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-4 + (LOW-PRIO) = N times reuse/call of TST02-1\n[configure N PMP entries ([FTR02-b1]: + maybe mandatorily the N first ones): at least one with L=1 and one with + L=0,\n - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) + are effectively locked whatever the SW mode => FTR08-a\n - check for PMP + entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable + in S or U modes\n - check locked PMP entry (i) has no effect on unlocked + PMP entry (j)\n - check for PMP entry (i) where L=0 that pmp(i)cfg and + pmpaddr(i) are writable/readable in M-mode only\n - check for PMP entry + (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in + S or U modes]" +- 004_configure_8_pmp_entries: !Subfeature + name: 004_configure_8_pmp_entries + tag: VP_PMP_F003_S005 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F003_S005_I000 + description: "{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\n\nThe L bit indicates that the PMP + entry is locked, i.e., writes to the configuration register and associated + address registers are ignored\nIf PMP entry (i) is locked, writes to pmp(i)cfg + and pmpaddr(i) are ignored\nLocked PMP entries remain locked until the hart + is reset\n\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: + RISC-V Privileged Architectures V20211203}\n\nSetting the L bit locks the + PMP entry even when the A field is set to OFF\n\nAdditionally, if PMP entry + (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are + ignored" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure all 8 PMP entries (in incrementing order) at least + one with L=1 and one with L=0,\n - reuse of VP_PMP_F003_S003_I000 sequence" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST03(group) => FTR08-a and FTR08-b\n [check that HW + implemented PMP entries are not writable/readable in M-mode (L=1)]\n [check + that no HW implemented PMP entry are writable/readable in S or U modes (L=1)]\n\ + \ - before any configuration, check all pmp(i)cfg and pmpaddr(i) are + M-mode read zero\n - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg + and pmpaddr(i) maybe random values\n - execute following tests specific + checks\n - check only hart reset unlocks all => FTR08-b\n - check + reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero\n\nTST03-5 + (HIGH-PRIO) = 8 times reuse/call of TST02-1\n[configure 8 PMP entries: at + least one with L=1 and one with L=0,\n - check for PMP entry (i) where + L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW + mode => FTR08-a\n - check for PMP entry (i) where L=1 that pmp(i)cfg and + pmpaddr(i) are not writable/readable in S or U modes\n - check locked PMP + entry (i) has no effect on unlocked PMP entry (j)\n - check for PMP entry + (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode + only\n - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) + are not writable/readable in S or U modes]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP004.yml b/verif/docs/VerifPlans/PMP/VP_IP004.yml new file mode 100644 index 00000000000..80ed9259c8a --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP004.yml @@ -0,0 +1,146 @@ +!Feature +next_elt_id: 4 +name: CSRs programming order +id: 4 +display_order: 4 +subfeatures: !!omap +- 000_configure_1_pmp_entry: !Subfeature + name: 000_configure_1_pmp_entry + tag: VP_PMP_F004_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F004_S001_I000 + description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures + V20211203}\n\nthe lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)\nAll PMP CSR fields are WARL and may be read-only + zero (QUESTION: does read-only zero mean not implemented?)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure any PMP entry (i), but the first one\n - reuse of + VP_PMP_F003_S003_I000 sequence (Feature: \"CSRs locked access\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST04 => FTR02-b1 and FTR02-b2\n [check if the lowest-numbered + PMP CSRs must be programmed first before programming higher-numbered ones]\n + \nTST04-1 (LOW-PRIO) extends TST02-1\n[configure any PMP entry, but the + first one\n - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) + are writable/readable in M-mode only\n - check for not configured PMP entry + (i), pmp(i)cfg and pmpaddr(i) are M-mode read zero]" +- 001_configure_2_pmp_entries: !Subfeature + name: 001_configure_2_pmp_entries + tag: VP_PMP_F004_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F004_S002_I000 + description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures + V20211203}\n\nthe lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)\nAll PMP CSR fields are WARL and may be read-only + zero (QUESTION: does read-only zero mean not implemented?)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure 2 non-adjacent PMP entries (highest-numbered ones + first) (avoid the first PMP entry)\n - reuse of VP_PMP_F003_S003_I000 sequence + (Feature: \"CSRs locked access\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST04 => FTR02-b1 and FTR02-b2\n [check if the lowest-numbered + PMP CSRs must be programmed first before programming higher-numbered ones]\n + \nTST04-2 (HIGH-PRIO) extends TST02-2\n[configure 2 non-adjacent PMP entries + (highest-numbered ones first) (avoid the first PMP entry)\n - check for + configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable + in M-mode only\n - check for not configured PMP entry (i), pmp(i)cfg and + pmpaddr(i) are M-mode read zero]" +- 002_configure_N_pmp_entries: !Subfeature + name: 002_configure_N_pmp_entries + tag: VP_PMP_F004_S003 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F004_S003_I000 + description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures + V20211203}\n\nthe lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)\nAll PMP CSR fields are WARL and may be read-only + zero (QUESTION: does read-only zero mean not implemented?)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure N PMP entries (highest-numbered ones first) (as non-adjacent + as possible, and avoid the first PMP entry)\n - reuse of VP_PMP_F003_S003_I000 + sequence (Feature: \"CSRs locked access\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST04 => FTR02-b1 and FTR02-b2\n [check if the lowest-numbered + PMP CSRs must be programmed first before programming higher-numbered ones]\n + \nTST04-3 (LOW-PRIO) extends TST02-3\n[configure N PMP entries (highest-numbered + ones first) (as non-adjacent as possible, and avoid the first PMP entry)\n\ + \ - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable + in M-mode only\n - check for not configured PMP entry (i), pmp(i)cfg and + pmpaddr(i) are M-mode read zero]" +- 003_configure_8_pmp_entries: !Subfeature + name: 003_configure_8_pmp_entries + tag: VP_PMP_F004_S004 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F004_S004_I000 + description: "{Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures + V20211203}\n\nthe lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)\nAll PMP CSR fields are WARL and may be read-only + zero (QUESTION: does read-only zero mean not implemented?)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure all 8 PMP entries (highest-numbered ones first)\n\ + \ - reuse of VP_PMP_F003_S003_I000 sequence (Feature: \"CSRs locked access\"\ + )" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST04 => FTR02-b1 and FTR02-b2\n [check if the lowest-numbered + PMP CSRs must be programmed first before programming higher-numbered ones]\n + \nTST04-4 (HIGH-PRIO) extends TST02-4\n[configure 8 PMP entries (highest-numbered + ones first)\n - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) + are writable/readable in M-mode only]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP005.yml b/verif/docs/VerifPlans/PMP/VP_IP005.yml new file mode 100644 index 00000000000..1c295592384 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP005.yml @@ -0,0 +1,90 @@ +!Feature +next_elt_id: 2 +name: CSRs Hardwired regions +id: 5 +display_order: 5 +subfeatures: !!omap +- 000_access with L=0: !Subfeature + name: 000_access with L=0 + tag: VP_PMP_F005_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F005_S001_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + Certain regions’ privileges can be hardwired: so only ever be visible in + machine mode but in no lower-privilege layers.\n\n{Section 3.7.1 Page 57 + Volume II: RISC-V Privileged Architectures V20211203}\nImplementations may + implement zero, 16, or 64 PMP CSRs\n\n{https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/PMP.html}\n + A maximum of 16 PMP entries are supported.\nAll PMP CSRs are always implemented, + but CSRs (or bitfields of CSRs) related to PMP entries with number CVA6Cfg.NrPMPEntries + and above are hardwired to zero.\n\nTRISTAN\n8 PMP entries are implemented" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure the first 8 PMP entries with L=0\n - for each PMP + entry (i), check several times that pmp(i)cfg and pmpaddr(i) can be written + and can be read back exactly the same (in M-mode)\n\nfor the last 8 PMP + entries, check that pmp(i)cfg and pmpaddr(i) always read zero after being + written (in M-mode with L=0)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST05 => FTR01-c and FTR01-c-extended\n [check all + regions are configurable in M-mode to make sure none is hardwired]\n [regions + hardwired privileges might only ever be visible in M-mode]\n\nTST05-1 (HIGH-PRIO) + extends TST02-4\n - check the written pmp(i)cfg and pmpaddr(i) values can + be read exactly the same as written" +- 001_access with L=1: !Subfeature + name: 001_access with L=1 + tag: VP_PMP_F005_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F005_S002_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + Certain regions’ privileges can be hardwired: so only ever be visible in + machine mode but in no lower-privilege layers.\n\n{Section 3.7.1 Page 57 + Volume II: RISC-V Privileged Architectures V20211203}\nImplementations may + implement zero, 16, or 64 PMP CSRs\n\n{https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/PMP.html}\n + A maximum of 16 PMP entries are supported.\nAll PMP CSRs are always implemented, + but CSRs (or bitfields of CSRs) related to PMP entries with number CVA6Cfg.NrPMPEntries + and above are hardwired to zero.\n\nTRISTAN\n8 PMP entries are implemented" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure the first 8 PMP entries with L=1\n - for each PMP + entry (i), check once that pmp(i)cfg and pmpaddr(i) can be written and can + be read back exactly the same (in M-mode)\n - apply hart reset\n - for + each PMP entry (i), check once that pmp(i)cfg and pmpaddr(i) can be written + and can be read back exactly the same (in M-mode)\n\nfor the last 8 PMP + entries, check that pmp(i)cfg and pmpaddr(i) always read zero after being + written (in M-mode with L=1)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST05 => FTR01-c and FTR01-c-extended\n [check all + regions are configurable in M-mode to make sure none is hardwired]\n [regions + hardwired privileges might only ever be visible in M-mode]\n\nTST05-2 (LOW-PRIO) + extends TST03-5\n - check the written pmp(i)cfg and pmpaddr(i) values can + be read exactly the same as written (before hart reset)" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP006.yml b/verif/docs/VerifPlans/PMP/VP_IP006.yml new file mode 100644 index 00000000000..f59c2d35678 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP006.yml @@ -0,0 +1,82 @@ +!Feature +next_elt_id: 2 +name: CSRs reserved values +id: 6 +display_order: 6 +subfeatures: !!omap +- 000_access with L=0: !Subfeature + name: 000_access with L=0 + tag: VP_PMP_F006_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F006_S001_I000 + description: "{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n + \nThe R, W, and X fields form a collective WARL field for which the combinations + with R=0 and W=1 are reserved." + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "repeat following sequence several times on some PMP entries\n\ + \ - write totally random values to pmp(i)cfg and pmpaddr(i), but with L=0\n\ + \ - check all pmp(i)cfg and pmpaddr(i) can be read back exactly the same + as written except:\n - except with the reserved combinations [R=0 and + W=1]\n - except with A=NA4 which must not be selectable as G>0" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST06 => FTR04-a\n[PMP CSR fields are WARL: PMP entry + combinations with R=0 and W=1 are reserved/can’t be read]\n[permissions + fields could be randomly written; should we try randomization ?]\n\nTST06-1 + (HIGH-PRIO) extends TST02-4\n - write totally random values to pmp(i)cfg + and pmpaddr(i)\n - check all pmp(i)cfg and pmpaddr(i) can be read exactly + the same as written except for the reserved combinations with R=0 and W=1" +- 001_access with L=1: !Subfeature + name: 001_access with L=1 + tag: VP_PMP_F006_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F006_S002_I000 + description: "{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n + \nThe R, W, and X fields form a collective WARL field for which the combinations + with R=0 and W=1 are reserved." + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "repeat following sequence several times on some PMP entries\n\ + \ - write totally random values to pmp(i)cfg and pmpaddr(i), but with L=1\n\ + \ - check all pmp(i)cfg and pmpaddr(i) can be read back exactly the same + as written:\n - except with the reserved combinations [R=0 and W=1]\n\ + \ - except with A=NA4 which must not be selectable as G>0\n - apply + hart reset" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST06 => FTR04-a\n[PMP CSR fields are WARL: PMP entry + combinations with R=0 and W=1 are reserved/can’t be read]\n[permissions + fields could be randomly written; should we try randomization ?]\n\nTST06-2 + (LOW-PRIO) extends TST03-5\n - write totally random values to pmp(i)cfg + and pmpaddr(i)\n - check all pmp(i)cfg and pmpaddr(i) can be read exactly + the same as written except for the reserved combinations with R=0 and W=1 + (before hart reset)" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP010.yml b/verif/docs/VerifPlans/PMP/VP_IP010.yml new file mode 100644 index 00000000000..e44684c1925 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP010.yml @@ -0,0 +1,128 @@ +!Feature +next_elt_id: 4 +name: no cfg matching/defined +id: 10 +display_order: 10 +subfeatures: !!omap +- 000_no matching entry - M mode access: !Subfeature + name: 000_no matching entry - M mode access + tag: VP_PMP_F010_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F010_S001_I000 + description: "{Page 60 Section \"Priority and Matching Logic\" Volume II: + RISC-V Privileged Architectures V20211203}\n\nIf no PMP entry matches an + M-mode access, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: check M-mode access succeeds if no PMP entry matches + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR09-e\n[If no PMP entry matches an M-mode access, + the access succeeds]\n \nTST10-1 (HIGH-PRIO) => FTR09-e\n[check M-mode access + succeeds if no PMP entry matches]" +- 001_no defined entry - M mode access: !Subfeature + name: 001_no defined entry - M mode access + tag: VP_PMP_F010_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F010_S002_I000 + description: "{Page 60 Section \"Priority and Matching Logic\" Volume II: + RISC-V Privileged Architectures V20211203}\n\nIf no PMP entry matches an + M-mode access, the access succeeds\nQUESTION: what happens if no PMP entry + is implemented ?\nASSUMPTION: access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: check M-mode access succeeds if no PMP entry defined + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR09-e-question\n[what happens if no PMP entry is implemented + ?]\n \nTST10-2 (HIGH-PRIO) => FTR09-e-question\n[check M-mode access succeeds + if no PMP entry defined]" +- 002_no matching entry - S/U mode access: !Subfeature + name: 002_no matching entry - S/U mode access + tag: VP_PMP_F010_S003 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F010_S003_I000 + description: "{Page 60 Section \"Priority and Matching Logic\" Volume II: + RISC-V Privileged Architectures V20211203}\n\nIf no PMP entry matches an + S-mode or U-mode access, but at least one PMP entry is implemented, the + access fails" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: check S or U mode access fails when no PMP entry matching and + at least one PMP entry implemented + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR09-f\n[If no PMP entry matches an S-mode or U-mode + access, but at least one PMP entry is implemented, the access fails]\n\n + TST10-3 (HIGH-PRIO) => FTR09-f\n[check S or U mode access fails when no + PMP entry matching and at least one PMP entry implemented]" +- 003_no defined entry - S/U mode access: !Subfeature + name: 003_no defined entry - S/U mode access + tag: VP_PMP_F010_S004 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F010_S004_I000 + description: "{Page 60 Section \"Priority and Matching Logic\" Volume II: + RISC-V Privileged Architectures V20211203}\n\nIf no PMP entry matches an + S-mode or U-mode access, but at least one PMP entry is implemented, the + access fails\nQUESTION: what happens if no PMP entry is implemented ?\n + ASSUMPTION: access fails" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: check S or U mode access fails when no PMP entry implemented + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR09-f-question\n[what happens if no PMP entry is implemented + ?]\n \nTST10-4 (HIGH-PRIO) => FTR09-f-question\n[check S or U mode access + fails when no PMP entry implemented]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP011.yml b/verif/docs/VerifPlans/PMP/VP_IP011.yml new file mode 100644 index 00000000000..3c6de2ba9d9 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP011.yml @@ -0,0 +1,2069 @@ +!Feature +next_elt_id: 30 +name: cfg NA4 access S/U (G=0) +id: 11 +display_order: 11 +subfeatures: !!omap +- 000_fetch_L0_X1_addr_hit: !Subfeature + name: 000_fetch_L0_X1_addr_hit + tag: VP_PMP_F011_S011 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S011_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access instruction fetch inside defined NA4 + address range with execute permissions and with L=0\n - choose an executable + pmp region and address range\n - choose only one PMP entry (i)\n\nCONFIGURATION\n\ + \ - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with reserve on R=0 & W=1\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - fetch an instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check no access-fault exception\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-1x(group) + => FTR01-d\n [PMP check on instruction fetch where effective privilege + mode is S or U:\n - choose an executable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access instruction fetch in + S and U mode]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-11 (HIGH-PRIO)\n [with L=0 => FTR08-e2-2 (refers to + FTR09-d2-2),\n - configure the PMP entry with execute permissions for the + PMP region\n - fetch an instruction from that region (with exact address-matching)\n\ + \ - check no access-fault exception]" +- 001_fetch_L0_X0_addr_hit: !Subfeature + name: 001_fetch_L0_X0_addr_hit + tag: VP_PMP_F011_S012 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S012_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n + Attempting to fetch an instruction from a PMP region that does not have + execute permissions raises an instruction access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access instruction fetch inside defined NA4 + address range without execute permissions and with L=0\n - choose an + executable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, X=0, L=0, R/W:random, with + reserve on R=0 & W=1\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\ + \nACCESS\n - fetch an instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check instruction fetch access-fault exception raised\n\n\ + REUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-b\n + [Attempting to fetch an instruction from a PMP region that does not have + execute permissions raises an instruction access-fault exception]\n \nTST11-1x(group) + => FTR01-d\n [PMP check on instruction fetch where effective privilege + mode is S or U:\n - choose an executable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access instruction fetch in + S and U mode]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-12 (MEDIUM-PRIO)\n[with L=0 => FTR08-e2-2 (refers + to FTR09-d2-2),\n - configure the PMP entry without execute permissions + for the PMP region\n - fetch an instruction from that region (with exact + address-matching)\n - check instruction fetch access-fault exception raised + => FTR04-b]" +- 002_fetch_L0_X1_addr_miss: !Subfeature + name: 002_fetch_L0_X1_addr_miss + tag: VP_PMP_F011_S013 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S013_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access instruction fetch from outside defined + NA4 address range with execute permissions and with L=0\n - choose an + executable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with + reserve on R=0 & W=1\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\ + \nACCESS\n - fetch an instruction from outside all PMP defined regions\n\ + \nCHECK\n - check instruction fetch access-fault exception raised\n\n\ + REUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-1x(group) + => FTR01-d\n [PMP check on instruction fetch where effective privilege + mode is S or U:\n - choose an executable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access instruction fetch in + S and U mode]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-13 (MEDIUM-PRIO)\n [with L=0 => FTR08-e2-2 (refers + to FTR09-d2-2),\n - configure the PMP entry with execute permissions for + the PMP region\n - fetch an instruction from outside all PMP defined regions\n\ + \ - check instruction fetch access-fault exception raised]" +- 003_fetch_L1_X1_addr_hit: !Subfeature + name: 003_fetch_L1_X1_addr_hit + tag: VP_PMP_F011_S014 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S014_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access instruction fetch inside defined NA4 + address range with execute permissions and with L=1\n - choose an executable + pmp region and address range\n - choose only one PMP entry (i)\n\nCONFIGURATION\n\ + \ - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with reserve on R=0 & W=1\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - fetch an instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check no access-fault exception\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\n\nTST11-1x(group) + => FTR01-d\n [PMP check on instruction fetch where effective privilege + mode is S or U:\n - choose an executable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access instruction fetch in + S and U mode]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-14 (LOW-PRIO)\n[with L=1 => FTR08-e1 (refers to FTR01-f) + (refers to FTR09-d2-1),\n - configure the PMP entry with execute permissions + for the PMP region\n - fetch an instruction from that region (with exact + address-matching)\n - check no access-fault exception]" +- 004_fetch_L1_X0_addr_hit: !Subfeature + name: 004_fetch_L1_X0_addr_hit + tag: VP_PMP_F011_S015 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S015_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume + II: RISC-V Privileged Architectures V20211203}\nAttempting to fetch an instruction + from a PMP region that does not have execute permissions raises an instruction + access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access instruction fetch inside defined NA4 + address range without execute permissions and with L=1\n - choose an + executable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, X=0, L=1, R/W:random, with + reserve on R=0 & W=1\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\ + \nACCESS\n - fetch an instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check instruction fetch access-fault exception raised\n\n\ + REUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-b\n + [Attempting to fetch an instruction from a PMP region that does not have + execute permissions raises an instruction access-fault exception]\n\nTST11-1x(group) + => FTR01-d\n [PMP check on instruction fetch where effective privilege + mode is S or U:\n - choose an executable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access instruction fetch in + S and U mode]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-15 (LOW-PRIO)\n[with L=1 => FTR08-e1 (refers to FTR01-f) + (refers to FTR09-d2-1),\n - configure the PMP entry without execute permissions + for the PMP region\n - fetch an instruction from that region (with exact + address-matching)\n - check instruction fetch access-fault exception raised + => FTR04-b]" +- 005_fetch_L1_X1_addr_miss: !Subfeature + name: 005_fetch_L1_X1_addr_miss + tag: VP_PMP_F011_S016 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S016_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access instruction fetch from outside defined + NA4 address range with execute permissions and with L=1\n - choose an + executable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with + reserve on R=0 & W=1\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\ + \nACCESS\n - fetch an instruction from outside all PMP defined regions\n\ + \nCHECK\n - check instruction fetch access-fault exception raised\n\n\ + REUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nTST11-1x(group) + => FTR01-d\n [PMP check on instruction fetch where effective privilege + mode is S or U:\n - choose an executable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access instruction fetch in + S and U mode]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-16 (LOW-PRIO)\n[with L=1 => FTR08-e1 (refers to FTR01-f) + (refers to FTR09-d2-1),\n - configure the PMP entry with execute permissions + for the PMP region\n - fetch an instruction from outside all PMP defined + regions\n - check instruction fetch access-fault exception raised]" +- 006_load_L0_R1_addr_hit: !Subfeature + name: 006_load_L0_R1_addr_hit + tag: VP_PMP_F011_S021 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S021_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + inside defined NA4 address range with read permissions and with L=0\n \ + \ - choose a readable pmp region and address range\n - choose only one + PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - execute a load or load-reserved instruction from that region (with + exact address-matching)\n\nCHECK\n - check no access-fault exception\n\ + \nREUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-2x(group) + => FTR01-d\n [PMP check on load or load-reserved instruction where effective + privilege mode is S or U:\n - choose a data readable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + S and U mode when the bit mstatus.MPRV=0]\n [create scenarios where PMP + entries with A=2 (NA4) and with/without matching permissions\n - check + only NA4 defined addresses are matching]\nTST11-21 (HIGH-PRIO)\n[with L=0 + => FTR08-e2-2 (refers to FTR09-d2-2),\n - configure the PMP entry with + read permissions for the PMP region\n - execute a load or load-reserved + instruction from that region (with exact address-matching)\n - check no + access-fault exception]" +- 007_load_L0_R0_addr_hit: !Subfeature + name: 007_load_L0_R0_addr_hit + tag: VP_PMP_F011_S022 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S022_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n + Attempting to execute a load or load-reserved instruction which accesses + a physical address within a PMP region without read permissions raises a + load access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + inside defined NA4 address range without read permissions and with L=0\n\ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=0, L=0, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - execute a load or load-reserved instruction from that region (with + exact address-matching)\n\nCHECK\n - check load access-fault exception + raised\n\nREUSABILITY\n - if possible, the PMP entry number (i) is a + configurable parameter\n - if possible, the PMP entry lock (L) is a configurable + parameter\n - if possible, the PMP entry permissions (R,W,X) are configurable + parameters\n - if possible, the PMP entry address-matching mode (A) is + a configurable parameter\n - if possible, the PMP entry address range + (pmpaddr) is a configurable parameter\n - if possible, the PMP entry + associated access address is a configurable parameter\n - so a single + CONFIGURATION function and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-c\n + [Attempting to execute a load or load-reserved instruction which accesses + a physical address within a PMP region without read permissions raises a + load access-fault exception]\n\nTST11-2x(group) => FTR01-d\n [PMP check + on load or load-reserved instruction where effective privilege mode is S + or U:\n - choose a data readable pmp region and address range\n - + choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n\ + \ - if possible, the PMP entry number is a configurable parameter\n \ + \ - choose pmpcfg(i).A=NA4\n - single access data load in S and U mode + when the bit mstatus.MPRV=0]\n [create scenarios where PMP entries with + A=2 (NA4) and with/without matching permissions\n - check only NA4 defined + addresses are matching]\nTST11-22 (MEDIUM-PRIO)\n[with L=0 => FTR08-e2-2 + (refers to FTR09-d2-2),\n - configure the PMP entry without read permissions + for the PMP region\n - execute a load or load-reserved instruction from + that region (with exact address-matching)\n - check load access-fault exception + raised => FTR04-c]" +- 008_load_L0_R1_addr_miss: !Subfeature + name: 008_load_L0_R1_addr_miss + tag: VP_PMP_F011_S023 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S023_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + from outside defined NA4 address range with read permissions and with L=0\n\ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - execute a load or load-reserved instruction from outside all PMP defined + regions\n\nCHECK\n - check load access-fault exception raised\n\nREUSABILITY\n\ + \ - if possible, the PMP entry number (i) is a configurable parameter\n\ + \ - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-2x(group) + => FTR01-d\n [PMP check on load or load-reserved instruction where effective + privilege mode is S or U:\n - choose a data readable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + S and U mode when the bit mstatus.MPRV=0]\n [create scenarios where PMP + entries with A=2 (NA4) and with/without matching permissions\n - check + only NA4 defined addresses are matching]\nTST11-23 (MEDIUM-PRIO)\n[with + L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n - configure the PMP entry with + read permissions for the PMP region\n - execute a load or load-reserved + instruction from outside all PMP defined regions\n - check load access-fault + exception raised]" +- 009_load_L1_R1_addr_hit: !Subfeature + name: 009_load_L1_R1_addr_hit + tag: VP_PMP_F011_S024 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S024_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + inside defined NA4 address range with read permissions and with L=1\n \ + \ - choose a readable pmp region and address range\n - choose only one + PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - execute a load or load-reserved instruction from that region (with + exact address-matching)\n\nCHECK\n - check no access-fault exception\n\ + \nREUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nTST11-2x(group) + => FTR01-d\n [PMP check on load or load-reserved instruction where effective + privilege mode is S or U:\n - choose a data readable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + S and U mode when the bit mstatus.MPRV=0]\n [create scenarios where PMP + entries with A=2 (NA4) and with/without matching permissions\n - check + only NA4 defined addresses are matching]\nTST11-24 (LOW-PRIO)\n[with L=1 + => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure the + PMP entry with read permissions for the PMP region\n - execute a load or + load-reserved instruction from that region (with exact address-matching)\n\ + \ - check no access-fault exception]" +- 010_load_L1_R0_addr_hit: !Subfeature + name: 010_load_L1_R0_addr_hit + tag: VP_PMP_F011_S025 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S025_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume + II: RISC-V Privileged Architectures V20211203}\nAttempting to execute a + load or load-reserved instruction which accesses a physical address within + a PMP region without read permissions raises a load access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + inside defined NA4 address range without read permissions and with L=1\n\ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=0, L=1, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - execute a load or load-reserved instruction from that region (with + exact address-matching)\n\nCHECK\n - check load access-fault exception + raised\n\nREUSABILITY\n - if possible, the PMP entry number (i) is a + configurable parameter\n - if possible, the PMP entry lock (L) is a configurable + parameter\n - if possible, the PMP entry permissions (R,W,X) are configurable + parameters\n - if possible, the PMP entry address-matching mode (A) is + a configurable parameter\n - if possible, the PMP entry address range + (pmpaddr) is a configurable parameter\n - if possible, the PMP entry + associated access address is a configurable parameter\n - so a single + CONFIGURATION function and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-c\n + [Attempting to execute a load or load-reserved instruction which accesses + a physical address within a PMP region without read permissions raises a + load access-fault exception]\n \nTST11-2x(group) => FTR01-d\n [PMP check + on load or load-reserved instruction where effective privilege mode is S + or U:\n - choose a data readable pmp region and address range\n - + choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n\ + \ - if possible, the PMP entry number is a configurable parameter\n \ + \ - choose pmpcfg(i).A=NA4\n - single access data load in S and U mode + when the bit mstatus.MPRV=0]\n [create scenarios where PMP entries with + A=2 (NA4) and with/without matching permissions\n - check only NA4 defined + addresses are matching]\nTST11-25 (LOW-PRIO)\n [with L=1 => FTR08-e1 (refers + to FTR01-f) (refers to FTR09-d2-1),\n - configure the PMP entry without + read permissions for the PMP region\n - execute a load or load-reserved + instruction from that region (with exact address-matching)\n - check load + access-fault exception raised => FTR04-c]" +- 011_load_L1_R1_addr_miss: !Subfeature + name: 011_load_L1_R1_addr_miss + tag: VP_PMP_F011_S026 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S026_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + from outside defined NA4 address range with read permissions and with L=1\n\ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - execute a load or load-reserved instruction from outside all PMP defined + regions\n\nCHECK\n - check load access-fault exception raised\n\nREUSABILITY\n\ + \ - if possible, the PMP entry number (i) is a configurable parameter\n\ + \ - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nTST11-2x(group) + => FTR01-d\n [PMP check on load or load-reserved instruction where effective + privilege mode is S or U:\n - choose a data readable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + S and U mode when the bit mstatus.MPRV=0]\n [create scenarios where PMP + entries with A=2 (NA4) and with/without matching permissions\n - check + only NA4 defined addresses are matching]\nTST11-26 (LOW-PRIO)\n[with L=1 + => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure the + PMP entry with read permissions for the PMP region\n - execute a load or + load-reserved instruction from outside all PMP defined regions\n - check + load access-fault exception raised]" +- 012_store_L0_W1_addr_hit: !Subfeature + name: 012_store_L0_W1_addr_hit + tag: VP_PMP_F011_S031 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S031_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range with write permissions and with L=0\n \ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n\nCHECK\n - check no access-fault + exception\n\nREUSABILITY\n - if possible, the PMP entry number (i) is + a configurable parameter\n - if possible, the PMP entry lock (L) is a + configurable parameter\n - if possible, the PMP entry permissions (R,W,X) + are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-3x(group) + => FTR01-d\n [PMP check on store, store-conditional, or AMO instruction + where effective privilege mode is S or U:\n - choose a data writable + pmp region and address range\n - choose only one PMP entry (i) ([FTR02-b1]: + maybe mandatorily the 1st one)\n - if possible, the PMP entry number + is a configurable parameter\n - choose pmpcfg(i).A=NA4\n - single + access data store in S and U mode when the bit mstatus.MPRV=0]\n [create + scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\ + \ - check only NA4 defined addresses are matching]\nTST11-31 (HIGH-PRIO)\n + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n - configure the PMP entry + with write permissions for the PMP region\n - execute a store, store-conditional, + or AMO instruction to that region (with exact address-matching)\n - check + no access-fault exception]" +- 013_store_L0_W0_addr_hit: !Subfeature + name: 013_store_L0_W0_addr_hit + tag: VP_PMP_F011_S032 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S032_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n + Attempting to execute a store, store-conditional, or AMO instruction which + accesses a physical address within a PMP region without write permissions + raises a store access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range without write permissions and with L=0\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=0, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n\nCHECK\n - check store access-fault + exception raised\n\nREUSABILITY\n - if possible, the PMP entry number + (i) is a configurable parameter\n - if possible, the PMP entry lock (L) + is a configurable parameter\n - if possible, the PMP entry permissions + (R,W,X) are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-d\n + [Attempting to execute a store, store-conditional, or AMO instruction which + accesses a physical address within a PMP region without write permissions + raises a store access-fault exception]\n\nTST11-3x(group) => FTR01-d\n \ + \ [PMP check on store, store-conditional, or AMO instruction where effective + privilege mode is S or U:\n - choose a data writable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data store + in S and U mode when the bit mstatus.MPRV=0]\n [create scenarios where + PMP entries with A=2 (NA4) and with/without matching permissions\n - + check only NA4 defined addresses are matching]\nTST11-32 (MEDIUM-PRIO)\n + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n - configure the PMP entry + without write permissions for the PMP region\n - execute a store, store-conditional, + or AMO instruction to that region (with exact address-matching)\n - check + store access-fault exception raised => FTR04-d]" +- 014_store_L0_W1_addr_miss: !Subfeature + name: 014_store_L0_W1_addr_miss + tag: VP_PMP_F011_S033 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S033_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + from outside defined NA4 address range with write permissions and with L=0\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + outside all PMP defined regions\n\nCHECK\n - check store access-fault + exception raised\n\nREUSABILITY\n - if possible, the PMP entry number + (i) is a configurable parameter\n - if possible, the PMP entry lock (L) + is a configurable parameter\n - if possible, the PMP entry permissions + (R,W,X) are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-3x(group) + => FTR01-d\n [PMP check on store, store-conditional, or AMO instruction + where effective privilege mode is S or U:\n - choose a data writable + pmp region and address range\n - choose only one PMP entry (i) ([FTR02-b1]: + maybe mandatorily the 1st one)\n - if possible, the PMP entry number + is a configurable parameter\n - choose pmpcfg(i).A=NA4\n - single + access data store in S and U mode when the bit mstatus.MPRV=0]\n [create + scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\ + \ - check only NA4 defined addresses are matching]\nTST11-33 (MEDIUM-PRIO)\n + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n - configure the PMP entry + with write permissions for the PMP region\n - execute a store, store-conditional, + or AMO instruction to outside all PMP defined regions\n - check store access-fault + exception raised]" +- 015_store_L1_W1_addr_hit: !Subfeature + name: 015_store_L1_W1_addr_hit + tag: VP_PMP_F011_S034 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S034_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range with write permissions and with L=1\n \ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n\nCHECK\n - check no access-fault + exception\n\nREUSABILITY\n - if possible, the PMP entry number (i) is + a configurable parameter\n - if possible, the PMP entry lock (L) is a + configurable parameter\n - if possible, the PMP entry permissions (R,W,X) + are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nTST11-3x(group) + => FTR01-d\n [PMP check on store, store-conditional, or AMO instruction + where effective privilege mode is S or U:\n - choose a data writable + pmp region and address range\n - choose only one PMP entry (i) ([FTR02-b1]: + maybe mandatorily the 1st one)\n - if possible, the PMP entry number + is a configurable parameter\n - choose pmpcfg(i).A=NA4\n - single + access data store in S and U mode when the bit mstatus.MPRV=0]\n [create + scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\ + \ - check only NA4 defined addresses are matching]\nTST11-34 (LOW-PRIO)\n + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure + the PMP entry with write permissions for the PMP region\n - execute a store, + store-conditional, or AMO instruction to that region (with exact address-matching)\n\ + \ - check no access-fault exception]" +- 016_store_L1_W0_addr_hit: !Subfeature + name: 016_store_L1_W0_addr_hit + tag: VP_PMP_F011_S035 + next_elt_id: 1 + display_order: 16 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S035_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume + II: RISC-V Privileged Architectures V20211203}\nAttempting to execute a + store, store-conditional, or AMO instruction which accesses a physical address + within a PMP region without write permissions raises a store access-fault + exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range without write permissions and with L=1\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=0, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n\nCHECK\n - check store access-fault + exception raised\n\nREUSABILITY\n - if possible, the PMP entry number + (i) is a configurable parameter\n - if possible, the PMP entry lock (L) + is a configurable parameter\n - if possible, the PMP entry permissions + (R,W,X) are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-d\n + [Attempting to execute a store, store-conditional, or AMO instruction which + accesses a physical address within a PMP region without write permissions + raises a store access-fault exception]\n\nTST11-3x(group) => FTR01-d\n \ + \ [PMP check on store, store-conditional, or AMO instruction where effective + privilege mode is S or U:\n - choose a data writable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data store + in S and U mode when the bit mstatus.MPRV=0]\n [create scenarios where + PMP entries with A=2 (NA4) and with/without matching permissions\n - + check only NA4 defined addresses are matching]\nTST11-35 (LOW-PRIO)\n[with + L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure + the PMP entry without write permissions for the PMP region\n - execute + a store, store-conditional, or AMO instruction to that region (with exact + address-matching)\n - check store access-fault exception raised => FTR04-d]" +- 017_store_L1_W1_addr_miss: !Subfeature + name: 017_store_L1_W1_addr_miss + tag: VP_PMP_F011_S036 + next_elt_id: 1 + display_order: 17 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S036_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + from outside defined NA4 address range with write permissions and with L=1\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + outside all PMP defined regions\n\nCHECK\n - check store access-fault + exception raised\n\nREUSABILITY\n - if possible, the PMP entry number + (i) is a configurable parameter\n - if possible, the PMP entry lock (L) + is a configurable parameter\n - if possible, the PMP entry permissions + (R,W,X) are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nTST11-3x(group) + => FTR01-d\n [PMP check on store, store-conditional, or AMO instruction + where effective privilege mode is S or U:\n - choose a data writable + pmp region and address range\n - choose only one PMP entry (i) ([FTR02-b1]: + maybe mandatorily the 1st one)\n - if possible, the PMP entry number + is a configurable parameter\n - choose pmpcfg(i).A=NA4\n - single + access data store in S and U mode when the bit mstatus.MPRV=0]\n [create + scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\ + \ - check only NA4 defined addresses are matching]\nTST11-36 (LOW-PRIO)\n + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure + the PMP entry with write permissions for the PMP region\n - execute a store, + store-conditional, or AMO instruction to outside all PMP defined regions\n\ + \ - check store access-fault exception raised]" +- 018_load_MPP_L0_R1_addr_hit: !Subfeature + name: 018_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F011_S041 + next_elt_id: 1 + display_order: 18 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S041_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + inside defined NA4 address range with read permissions and with L=0\n \ + \ - choose a readable pmp region and address range\n - choose only one + PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains S or U\n\nACCESS\n - execute a load or load-reserved instruction + from that region (with exact address-matching)\n\nCHECK\n - check no + access-fault exception\n\nREUSABILITY\n - if possible, the PMP entry + number (i) is a configurable parameter\n - if possible, the PMP entry + lock (L) is a configurable parameter\n - if possible, the PMP entry permissions + (R,W,X) are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-4x(group) + => FTR01-d\n [PMP check on load or load-reserved instruction where effective + privilege mode is S or U:\n - choose a data readable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n\ + \ [create scenarios where PMP entries with A=2 (NA4) and with/without matching + permissions\n - check only NA4 defined addresses are matching]\nTST11-41 + (LOWEST-PRIO)\n [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n - configure + the PMP entry with read permissions for the PMP region\n - execute a load + or load-reserved instruction from that region (with exact address-matching)\n\ + \ - check no access-fault exception]" +- 019_load_MPP_L0_R0_addr_hit: !Subfeature + name: 019_load_MPP_L0_R0_addr_hit + tag: VP_PMP_F011_S042 + next_elt_id: 1 + display_order: 19 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S042_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n + Attempting to execute a load or load-reserved instruction which accesses + a physical address within a PMP region without read permissions raises a + load access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + inside defined NA4 address range without read permissions and with L=0\n\ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=0, L=0, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains S or U\n\nACCESS\n - execute a load or load-reserved instruction + from that region (with exact address-matching)\n\nCHECK\n - check load + access-fault exception raised\n\nREUSABILITY\n - if possible, the PMP + entry number (i) is a configurable parameter\n - if possible, the PMP + entry lock (L) is a configurable parameter\n - if possible, the PMP entry + permissions (R,W,X) are configurable parameters\n - if possible, the + PMP entry address-matching mode (A) is a configurable parameter\n - if + possible, the PMP entry address range (pmpaddr) is a configurable parameter\n\ + \ - if possible, the PMP entry associated access address is a configurable + parameter\n - so a single CONFIGURATION function and a single ACCESS + function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-c\n + [Attempting to execute a load or load-reserved instruction which accesses + a physical address within a PMP region without read permissions raises a + load access-fault exception]\n\nTST11-4x(group) => FTR01-d\n [PMP check + on load or load-reserved instruction where effective privilege mode is S + or U:\n - choose a data readable pmp region and address range\n - + choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n\ + \ - if possible, the PMP entry number is a configurable parameter\n \ + \ - choose pmpcfg(i).A=NA4\n - single access data load in any mode + when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n [create + scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\ + \ - check only NA4 defined addresses are matching]\nTST11-42 (LOWEST-PRIO)\n + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n - configure the PMP entry + without read permissions for the PMP region\n - execute a load or load-reserved + instruction from that region (with exact address-matching)\n - check load + access-fault exception raised => FTR04-c]" +- 020_load_MPP_L0_R1_addr_miss: !Subfeature + name: 020_load_MPP_L0_R1_addr_miss + tag: VP_PMP_F011_S043 + next_elt_id: 1 + display_order: 20 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S043_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + from outside defined NA4 address range with read permissions and with L=0\n\ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains S or U\n\nACCESS\n - execute a load or load-reserved instruction + from outside all PMP defined regions\n\nCHECK\n - check load access-fault + exception raised\n\nREUSABILITY\n - if possible, the PMP entry number + (i) is a configurable parameter\n - if possible, the PMP entry lock (L) + is a configurable parameter\n - if possible, the PMP entry permissions + (R,W,X) are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-4x(group) + => FTR01-d\n [PMP check on load or load-reserved instruction where effective + privilege mode is S or U:\n - choose a data readable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n\ + \ [create scenarios where PMP entries with A=2 (NA4) and with/without matching + permissions\n - check only NA4 defined addresses are matching]\nTST11-43 + (LOWEST-PRIO)\n [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n - configure + the PMP entry with read permissions for the PMP region\n - execute a load + or load-reserved instruction from outside all PMP defined regions\n - check + load access-fault exception raised]" +- 021_load_MPP_L1_R1_addr_hit: !Subfeature + name: 021_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F011_S044 + next_elt_id: 1 + display_order: 21 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S044_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + inside defined NA4 address range with read permissions and with L=1\n \ + \ - choose a readable pmp region and address range\n - choose only one + PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains S or U\n\nACCESS\n - execute a load or load-reserved instruction + from that region (with exact address-matching)\n\nCHECK\n - check no + access-fault exception\n\nREUSABILITY\n - if possible, the PMP entry + number (i) is a configurable parameter\n - if possible, the PMP entry + lock (L) is a configurable parameter\n - if possible, the PMP entry permissions + (R,W,X) are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nTST11-4x(group) + => FTR01-d\n [PMP check on load or load-reserved instruction where effective + privilege mode is S or U:\n - choose a data readable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n\ + \ [create scenarios where PMP entries with A=2 (NA4) and with/without matching + permissions\n - check only NA4 defined addresses are matching]\nTST11-44 + (LOWEST-PRIO)\n [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n\ + \ - configure the PMP entry with read permissions for the PMP region\n\ + \ - execute a load or load-reserved instruction from that region (with + exact address-matching)\n - check no access-fault exception]" +- 022_load_MPP_L1_R0_addr_hit: !Subfeature + name: 022_load_MPP_L1_R0_addr_hit + tag: VP_PMP_F011_S045 + next_elt_id: 1 + display_order: 22 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S045_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume + II: RISC-V Privileged Architectures V20211203}\nAttempting to execute a + load or load-reserved instruction which accesses a physical address within + a PMP region without read permissions raises a load access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + inside defined NA4 address range without read permissions and with L=1\n\ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=0, L=1, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains S or U\n\nACCESS\n - execute a load or load-reserved instruction + from that region (with exact address-matching)\n\nCHECK\n - check load + access-fault exception raised\n\nREUSABILITY\n - if possible, the PMP + entry number (i) is a configurable parameter\n - if possible, the PMP + entry lock (L) is a configurable parameter\n - if possible, the PMP entry + permissions (R,W,X) are configurable parameters\n - if possible, the + PMP entry address-matching mode (A) is a configurable parameter\n - if + possible, the PMP entry address range (pmpaddr) is a configurable parameter\n\ + \ - if possible, the PMP entry associated access address is a configurable + parameter\n - so a single CONFIGURATION function and a single ACCESS + function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-c\n + [Attempting to execute a load or load-reserved instruction which accesses + a physical address within a PMP region without read permissions raises a + load access-fault exception]\n \nTST11-4x(group) => FTR01-d\n [PMP check + on load or load-reserved instruction where effective privilege mode is S + or U:\n - choose a data readable pmp region and address range\n - + choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n\ + \ - if possible, the PMP entry number is a configurable parameter\n \ + \ - choose pmpcfg(i).A=NA4\n - single access data load in any mode + when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n [create + scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\ + \ - check only NA4 defined addresses are matching]\nTST11-45 (LOWEST-PRIO)\n + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure + the PMP entry without read permissions for the PMP region\n - execute a + load or load-reserved instruction from that region (with exact address-matching)\n\ + \ - check load access-fault exception raised => FTR04-c]" +- 023_load_MPP_L1_R1_addr_miss: !Subfeature + name: 023_load_MPP_L1_R1_addr_miss + tag: VP_PMP_F011_S046 + next_elt_id: 1 + display_order: 23 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S046_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access load or load-reserved instruction + from outside defined NA4 address range with read permissions and with L=1\n\ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains S or U\n\nACCESS\n - execute a load or load-reserved instruction + from outside all PMP defined regions\n\nCHECK\n - check load access-fault + exception raised\n\nREUSABILITY\n - if possible, the PMP entry number + (i) is a configurable parameter\n - if possible, the PMP entry lock (L) + is a configurable parameter\n - if possible, the PMP entry permissions + (R,W,X) are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nTST11-4x(group) + => FTR01-d\n [PMP check on load or load-reserved instruction where effective + privilege mode is S or U:\n - choose a data readable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U]\n\ + \ [create scenarios where PMP entries with A=2 (NA4) and with/without matching + permissions\n - check only NA4 defined addresses are matching]\nTST11-46 + (LOWEST-PRIO)\n [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n\ + \ - configure the PMP entry with read permissions for the PMP region\n\ + \ - execute a load or load-reserved instruction from outside all PMP defined + regions\n - check load access-fault exception raised]" +- 024_store_MPP_L0_W1_addr_hit: !Subfeature + name: 024_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F011_S051 + next_elt_id: 1 + display_order: 24 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S051_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range with write permissions and with L=0\n \ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains S or U\n\nACCESS\n - execute a store, store-conditional, + or AMO instruction to that region (with exact address-matching)\n\nCHECK\n\ + \ - check no access-fault exception\n\nREUSABILITY\n - if possible, + the PMP entry number (i) is a configurable parameter\n - if possible, + the PMP entry lock (L) is a configurable parameter\n - if possible, the + PMP entry permissions (R,W,X) are configurable parameters\n - if possible, + the PMP entry address-matching mode (A) is a configurable parameter\n \ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-5x(group) + => FTR01-d\n [PMP check on store, store-conditional, or AMO instruction + where effective privilege mode is S or U:\n - choose a data writable + pmp region and address range\n - choose only one PMP entry (i) ([FTR02-b1]: + maybe mandatorily the 1st one)\n - if possible, the PMP entry number + is a configurable parameter\n - choose pmpcfg(i).A=NA4\n - single + access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP + contains S or U]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-51 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-2 (refers + to FTR09-d2-2),\n - configure the PMP entry with write permissions for + the PMP region\n - execute a store, store-conditional, or AMO instruction + to that region (with exact address-matching)\n - check no access-fault + exception]" +- 025_store_MPP_L0_W0_addr_hit: !Subfeature + name: 025_store_MPP_L0_W0_addr_hit + tag: VP_PMP_F011_S052 + next_elt_id: 1 + display_order: 25 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S052_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set\n\n{Page 58 Volume II: RISC-V Privileged Architectures V20211203}\n + Attempting to execute a store, store-conditional, or AMO instruction which + accesses a physical address within a PMP region without write permissions + raises a store access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range without write permissions and with L=0\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=0, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains S or U\n\nACCESS\n - execute a store, store-conditional, + or AMO instruction to that region (with exact address-matching)\n\nCHECK\n\ + \ - check store access-fault exception raised\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nFTR04-d\n + [Attempting to execute a store, store-conditional, or AMO instruction which + accesses a physical address within a PMP region without write permissions + raises a store access-fault exception]\n\nTST11-5x(group) => FTR01-d\n \ + \ [PMP check on store, store-conditional, or AMO instruction where effective + privilege mode is S or U:\n - choose a data writable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data store + in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or + U]\n [create scenarios where PMP entries with A=2 (NA4) and with/without + matching permissions\n - check only NA4 defined addresses are matching]\n + TST11-52 (LOWEST-PRIO)\n [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2),\n\ + \ - configure the PMP entry without write permissions for the PMP region\n\ + \ - execute a store, store-conditional, or AMO instruction to that region + (with exact address-matching)\n - check store access-fault exception raised + => FTR04-d]" +- 026_store_MPP_L0_W1_addr_miss: !Subfeature + name: 026_store_MPP_L0_W1_addr_miss + tag: VP_PMP_F011_S053 + next_elt_id: 1 + display_order: 26 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S053_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is clear, the R/W/X + permissions apply only to S and U modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + from outside defined NA4 address range with write permissions and with L=0\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains S or U\n\nACCESS\n - execute a store, store-conditional, + or AMO instruction to outside all PMP defined regions\n\nCHECK\n - check + store access-fault exception raised\n\nREUSABILITY\n - if possible, the + PMP entry number (i) is a configurable parameter\n - if possible, the + PMP entry lock (L) is a configurable parameter\n - if possible, the PMP + entry permissions (R,W,X) are configurable parameters\n - if possible, + the PMP entry address-matching mode (A) is a configurable parameter\n \ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e2-2 (refers to + FTR09-d2-2)\n [When the L bit is clear, the R/W/X permissions apply only + to S and U modes]\n FTR09-d2-2 (L=0 refers to FTR08-e2-2)\n[if the privilege + mode of the access is S or U (whatever L), then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\n\nTST11-5x(group) + => FTR01-d\n [PMP check on store, store-conditional, or AMO instruction + where effective privilege mode is S or U:\n - choose a data writable + pmp region and address range\n - choose only one PMP entry (i) ([FTR02-b1]: + maybe mandatorily the 1st one)\n - if possible, the PMP entry number + is a configurable parameter\n - choose pmpcfg(i).A=NA4\n - single + access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP + contains S or U]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-53 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-2 (refers + to FTR09-d2-2),\n - configure the PMP entry with write permissions for + the PMP region\n - execute a store, store-conditional, or AMO instruction + to outside all PMP defined regions\n - check store access-fault exception + raised]" +- 027_store_MPP_L1_W1_addr_hit: !Subfeature + name: 027_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F011_S054 + next_elt_id: 1 + display_order: 27 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S054_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range with write permissions and with L=1\n \ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains S or U\n\nACCESS\n - execute a store, store-conditional, + or AMO instruction to that region (with exact address-matching)\n\nCHECK\n\ + \ - check no access-fault exception\n\nREUSABILITY\n - if possible, + the PMP entry number (i) is a configurable parameter\n - if possible, + the PMP entry lock (L) is a configurable parameter\n - if possible, the + PMP entry permissions (R,W,X) are configurable parameters\n - if possible, + the PMP entry address-matching mode (A) is a configurable parameter\n \ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nTST11-5x(group) + => FTR01-d\n [PMP check on store, store-conditional, or AMO instruction + where effective privilege mode is S or U:\n - choose a data writable + pmp region and address range\n - choose only one PMP entry (i) ([FTR02-b1]: + maybe mandatorily the 1st one)\n - if possible, the PMP entry number + is a configurable parameter\n - choose pmpcfg(i).A=NA4\n - single + access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP + contains S or U]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-54 (LOWEST-PRIO)\n[with L=1 => FTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1),\n - configure the PMP entry with write + permissions for the PMP region\n - execute a store, store-conditional, + or AMO instruction to that region (with exact address-matching)\n - check + no access-fault exception]" +- 028_store_MPP_L1_W0_addr_hit: !Subfeature + name: 028_store_MPP_L1_W0_addr_hit + tag: VP_PMP_F011_S055 + next_elt_id: 1 + display_order: 28 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S055_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset\n\n{Page 58 Volume + II: RISC-V Privileged Architectures V20211203}\nAttempting to execute a + store, store-conditional, or AMO instruction which accesses a physical address + within a PMP region without write permissions raises a store access-fault + exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range without write permissions and with L=1\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=0, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains S or U\n\nACCESS\n - execute a store, store-conditional, + or AMO instruction to that region (with exact address-matching)\n\nCHECK\n\ + \ - check store access-fault exception raised\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nFTR04-d\n + [Attempting to execute a store, store-conditional, or AMO instruction which + accesses a physical address within a PMP region without write permissions + raises a store access-fault exception]\n\nTST11-5x(group) => FTR01-d\n \ + \ [PMP check on store, store-conditional, or AMO instruction where effective + privilege mode is S or U:\n - choose a data writable pmp region and address + range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily + the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data store + in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or + U]\n [create scenarios where PMP entries with A=2 (NA4) and with/without + matching permissions\n - check only NA4 defined addresses are matching]\n + TST11-55 (LOWEST-PRIO)\n [with L=1 => FTR08-e1 (refers to FTR01-f) (refers + to FTR09-d2-1),\n - configure the PMP entry without write permissions for + the PMP region\n - execute a store, store-conditional, or AMO instruction + to that region (with exact address-matching)\n - check store access-fault + exception raised => FTR04-d]" +- 029_store_MPP_L1_W1_addr_miss: !Subfeature + name: 029_store_MPP_L1_W1_addr_miss + tag: VP_PMP_F011_S056 + next_elt_id: 1 + display_order: 29 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F011_S056_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks are applied to all accesses whose effective privilege mode is + S or U\n\n{Page 60 Section \"Locking and Privilege Mode\" Volume II: RISC-V + Privileged Architectures V20211203}\nWhen the L bit is set, these permissions + are enforced for all privilege modes\n\n{Page 60 Section \"Priority and + Matching Logic\" Volume II: RISC-V Privileged Architectures V20211203}\n + if the L bit is set, then the access succeeds only if the R, W, or X bit + corresponding to the access type is set\n\n{Page 60 Section \"Locking and + Privilege Mode\" Volume II: RISC-V Privileged Architectures V20211203}\n + Locked PMP entries remain locked until the hart is reset" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "S or U mode single access store, store-conditional, or AMO instruction + from outside defined NA4 address range with write permissions and with L=1\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains S or U\n\nACCESS\n - execute a store, store-conditional, + or AMO instruction to outside all PMP defined regions\n\nCHECK\n - check + store access-fault exception raised\n\nREUSABILITY\n - if possible, the + PMP entry number (i) is a configurable parameter\n - if possible, the + PMP entry lock (L) is a configurable parameter\n - if possible, the PMP + entry permissions (R,W,X) are configurable parameters\n - if possible, + the PMP entry address-matching mode (A) is a configurable parameter\n \ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-d\n[PMP checks are applied to all accesses whose effective privilege + mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\nFTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1)\n [When the L bit is set, these permissions + are enforced for all privilege modes]\n FTR09-d2-1 (refers to FTR08-e1) + (refers to FTR01-f)\n [if the L bit is set, then the access succeeds only + if the R, W, or X bit corresponding to the access type is set]\nFTR08-b\n + [Locked PMP entries remain locked until the hart is reset]\n\nTST11-5x(group) + => FTR01-d\n [PMP check on store, store-conditional, or AMO instruction + where effective privilege mode is S or U:\n - choose a data writable + pmp region and address range\n - choose only one PMP entry (i) ([FTR02-b1]: + maybe mandatorily the 1st one)\n - if possible, the PMP entry number + is a configurable parameter\n - choose pmpcfg(i).A=NA4\n - single + access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP + contains S or U]\n [create scenarios where PMP entries with A=2 (NA4) and + with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST11-56 (LOWEST-PRIO)\n[with L=1 => FTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1),\n - configure the PMP entry with write + permissions for the PMP region\n - execute a store, store-conditional, + or AMO instruction to outside all PMP defined regions\n - check store access-fault + exception raised]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP012.yml b/verif/docs/VerifPlans/PMP/VP_IP012.yml new file mode 100644 index 00000000000..7f8c4a2e2d2 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP012.yml @@ -0,0 +1,2052 @@ +!Feature +next_elt_id: 30 +name: cfg NA4 access M (G=0) +id: 12 +display_order: 12 +subfeatures: !!omap +- 000_fetch_L0_X1_addr_hit: !Subfeature + name: 000_fetch_L0_X1_addr_hit + tag: VP_PMP_F012_S011 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S011_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access instruction fetch inside defined NA4 address + range with execute permissions and with L=0\n - choose an executable + pmp region and address range\n - choose only one PMP entry (i)\n\nCONFIGURATION\n\ + \ - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with reserve on R=0 & W=1\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - fetch an instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check no access-fault exception\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-1x(group) => FTR01-f\n [PMP check + on instruction fetch where effective privilege mode is M:\n - choose + an executable pmp region and address range\n - choose only one PMP entry + (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n - if possible, the + PMP entry number is a configurable parameter\n - choose pmpcfg(i).A=NA4\n\ + \ - single access instruction fetch in M mode]\n [create scenarios where + PMP entries with A=2 (NA4) and with/without matching permissions\n - + check only NA4 defined addresses are matching]\nTST12-11 (LOW-PRIO)\n [with + L=0 => FTR08-e2-1 (refers to FTR09-d1),\n - configure the PMP entry with + execute permissions for the PMP region\n - fetch an instruction from that + region (with exact address-matching)\n - check no access-fault exception]" +- 001_fetch_L0_X0_addr_hit: !Subfeature + name: 001_fetch_L0_X0_addr_hit + tag: VP_PMP_F012_S012 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S012_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access instruction fetch inside defined NA4 address + range without execute permissions and with L=0\n - choose an executable + pmp region and address range\n - choose only one PMP entry (i)\n\nCONFIGURATION\n\ + \ - pmpcfg(i): A=NA4, X=0, L=0, R/W:random, with reserve on R=0 & W=1\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - fetch an instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check no access-fault exception\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-1x(group) => FTR01-f\n [PMP check + on instruction fetch where effective privilege mode is M:\n - choose + an executable pmp region and address range\n - choose only one PMP entry + (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n - if possible, the + PMP entry number is a configurable parameter\n - choose pmpcfg(i).A=NA4\n\ + \ - single access instruction fetch in M mode]\n [create scenarios where + PMP entries with A=2 (NA4) and with/without matching permissions\n - + check only NA4 defined addresses are matching]\nTST12-12 (LOW-PRIO)\n [with + L=0 => FTR08-e2-1 (refers to FTR09-d1),\n - configure the PMP entry without + execute permissions for the PMP region\n - fetch an instruction from that + region (with exact address-matching)\n - check no access-fault exception]" +- 002_fetch_L0_X1_addr_miss: !Subfeature + name: 002_fetch_L0_X1_addr_miss + tag: VP_PMP_F012_S013 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S013_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access instruction fetch from outside defined + NA4 address range with execute permissions and with L=0\n - choose an + executable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with + reserve on R=0 & W=1\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\ + \nACCESS\n - fetch an instruction from outside all PMP defined regions\n\ + \nCHECK\n - check no access-fault exception (Feature: \"no cfg matching\"\ + )\n\nREUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-1x(group) => FTR01-f\n [PMP check + on instruction fetch where effective privilege mode is M:\n - choose + an executable pmp region and address range\n - choose only one PMP entry + (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n - if possible, the + PMP entry number is a configurable parameter\n - choose pmpcfg(i).A=NA4\n\ + \ - single access instruction fetch in M mode]\n [create scenarios where + PMP entries with A=2 (NA4) and with/without matching permissions\n - + check only NA4 defined addresses are matching]\nTST12-13 (LOW-PRIO)\n [with + L=0 => FTR08-e2-1 (refers to FTR09-d1),\n - configure the PMP entry with + execute permissions for the PMP region\n - fetch an instruction from outside + all PMP defined regions\n - check no access-fault exception] //TODO: CHECK + IF M-MODE ALLOWED" +- 003_fetch_L1_X1_addr_hit: !Subfeature + name: 003_fetch_L1_X1_addr_hit + tag: VP_PMP_F012_S014 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S014_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access instruction fetch inside defined NA4 address + range with execute permissions and with L=1\n - choose an executable + pmp region and address range\n - choose only one PMP entry (i)\n\nCONFIGURATION\n\ + \ - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with reserve on R=0 & W=1\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - fetch an instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check no access-fault exception\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-1x(group) => FTR01-f\n [PMP check + on instruction fetch where effective privilege mode is M:\n - choose + an executable pmp region and address range\n - choose only one PMP entry + (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n - if possible, the + PMP entry number is a configurable parameter\n - choose pmpcfg(i).A=NA4\n\ + \ - single access instruction fetch in M mode]\n [create scenarios where + PMP entries with A=2 (NA4) and with/without matching permissions\n - + check only NA4 defined addresses are matching]\nTST12-14 (HIGH-PRIO)\n [with + L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure + the PMP entry with execute permissions for the PMP region\n - fetch an + instruction from that region (with exact address-matching)\n - check no + access-fault exception]" +- 004_fetch_L1_X0_addr_hit: !Subfeature + name: 004_fetch_L1_X0_addr_hit + tag: VP_PMP_F012_S015 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S015_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set\n\n{Page + 58 Volume II: RISC-V Privileged Architectures V20211203}\nAttempting to + fetch an instruction from a PMP region that does not have execute permissions + raises an instruction access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access instruction fetch inside defined NA4 address + range without execute permissions and with L=1\n - choose an executable + pmp region and address range\n - choose only one PMP entry (i)\n\nCONFIGURATION\n\ + \ - pmpcfg(i): A=NA4, X=0, L=1, R/W:random, with reserve on R=0 & W=1\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - fetch an instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check instruction fetch access-fault exception raised\n\n\ + REUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR04-b\n[Attempting to fetch an instruction from a PMP region that does + not have execute permissions raises an instruction access-fault exception]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n \nTST12-1x(group) => FTR01-f\n [PMP check + on instruction fetch where effective privilege mode is M:\n - choose + an executable pmp region and address range\n - choose only one PMP entry + (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n - if possible, the + PMP entry number is a configurable parameter\n - choose pmpcfg(i).A=NA4\n\ + \ - single access instruction fetch in M mode]\n [create scenarios where + PMP entries with A=2 (NA4) and with/without matching permissions\n - + check only NA4 defined addresses are matching]\nTST12-15 (MEDIUM-PRIO)\n + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure + the PMP entry without execute permissions for the PMP region\n - fetch + an instruction from that region (with exact address-matching)\n - check + instruction fetch access-fault exception raised => FTR04-b]" +- 005_fetch_L1_X1_addr_miss: !Subfeature + name: 005_fetch_L1_X1_addr_miss + tag: VP_PMP_F012_S016 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S016_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access instruction fetch from outside defined + NA4 address range with execute permissions and with L=1\n - choose an + executable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with + reserve on R=0 & W=1\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\ + \nACCESS\n - fetch an instruction from outside all PMP defined regions\n\ + \nCHECK\n - check no access-fault exception (Feature: \"no cfg matching\"\ + )\n\nREUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-1x(group) => FTR01-f\n [PMP check + on instruction fetch where effective privilege mode is M:\n - choose + an executable pmp region and address range\n - choose only one PMP entry + (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n - if possible, the + PMP entry number is a configurable parameter\n - choose pmpcfg(i).A=NA4\n\ + \ - single access instruction fetch in M mode]\n [create scenarios where + PMP entries with A=2 (NA4) and with/without matching permissions\n - + check only NA4 defined addresses are matching]\nTST12-16 (HIGH-PRIO)\n [with + L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure + the PMP entry with execute permissions for the PMP region\n - fetch an + instruction from outside all PMP defined regions\n - check no access-fault + exception] //TODO: CHECK IF M-MODE ALLOWED" +- 006_load_L0_R1_addr_hit: !Subfeature + name: 006_load_L0_R1_addr_hit + tag: VP_PMP_F012_S021 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S021_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction inside + defined NA4 address range with read permissions and with L=0\n - choose + a readable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n \ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n - + execute a load or load-reserved instruction from that region (with exact + address-matching)\n\nCHECK\n - check no access-fault exception\n\nREUSABILITY\n\ + \ - if possible, the PMP entry number (i) is a configurable parameter\n\ + \ - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-2x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in M mode when the + bit mstatus.MPRV=0]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\nTST12-21 (LOW-PRIO)\n[with L=0 => FTR08-e2-1 (refers to \ + \ FTR09-d1)\n - configure the PMP entry with read permissions for the PMP + region\n - execute a load or load-reserved instruction from that region + (with exact address-matching)\n - check no access-fault exception]" +- 007_load_L0_R0_addr_hit: !Subfeature + name: 007_load_L0_R0_addr_hit + tag: VP_PMP_F012_S022 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S022_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction inside + defined NA4 address range without read permissions and with L=0\n - choose + a readable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=0, L=0, X/W:random\n \ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n - + execute a load or load-reserved instruction from that region (with exact + address-matching)\n\nCHECK\n - check no access-fault exception\n\nREUSABILITY\n\ + \ - if possible, the PMP entry number (i) is a configurable parameter\n\ + \ - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-2x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in M mode when the + bit mstatus.MPRV=0]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\nTST12-22 (LOW-PRIO)\n[with L=0 => FTR08-e2-1 (refers to \ + \ FTR09-d1)\n - configure the PMP entry without read permissions for the + PMP region\n - execute a load or load-reserved instruction from that region + (with exact address-matching)\n - check no access-fault exception]" +- 008_load_L0_R1_addr_miss: !Subfeature + name: 008_load_L0_R1_addr_miss + tag: VP_PMP_F012_S023 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S023_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction from + outside defined NA4 address range with read permissions and with L=0\n \ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - execute a load or load-reserved instruction from outside all PMP defined + regions\n\nCHECK\n - check no access-fault exception (Feature: \"no cfg + matching\")\n\nREUSABILITY\n - if possible, the PMP entry number (i) + is a configurable parameter\n - if possible, the PMP entry lock (L) is + a configurable parameter\n - if possible, the PMP entry permissions (R,W,X) + are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-2x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in M mode when the + bit mstatus.MPRV=0]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\nTST12-23 (LOW-PRIO)\n[with L=0 => FTR08-e2-1 (refers to \ + \ FTR09-d1)\n - configure the PMP entry with read permissions for the PMP + region\n - execute a load or load-reserved instruction from outside all + PMP defined regions\n - check no access-fault exception] //TODO: CHECK + IF M-MODE ALLOWED" +- 009_load_L1_R1_addr_hit: !Subfeature + name: 009_load_L1_R1_addr_hit + tag: VP_PMP_F012_S024 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S024_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction inside + defined NA4 address range with read permissions and with L=1\n - choose + a readable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n \ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n - + execute a load or load-reserved instruction from that region (with exact + address-matching)\n\nCHECK\n - check no access-fault exception\n\nREUSABILITY\n\ + \ - if possible, the PMP entry number (i) is a configurable parameter\n\ + \ - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-2x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in M mode when the + bit mstatus.MPRV=0]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\nTST12-24 (HIGH-PRIO)\n[with L=1 => FTR08-e1 (refers to FTR01-f) + (refers to FTR09-d2-1),\n - configure the PMP entry with read permissions + for the PMP region\n - execute a load or load-reserved instruction from + that region (with exact address-matching)\n - check no access-fault exception]" +- 010_load_L1_R0_addr_hit: !Subfeature + name: 010_load_L1_R0_addr_hit + tag: VP_PMP_F012_S025 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S025_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set\n\n{Page + 58 Volume II: RISC-V Privileged Architectures V20211203}\nAttempting to + execute a load or load-reserved instruction which accesses a physical address + within a PMP region without read permissions raises a load access-fault + exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction inside + defined NA4 address range without read permissions and with L=1\n - choose + a readable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=0, L=1, X/W:random\n \ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n - + execute a load or load-reserved instruction from that region (with exact + address-matching)\n\nCHECK\n - check load access-fault exception raised\n\ + \nREUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR04-c\n[Attempting to execute a load or load-reserved instruction which + accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\nFTR02-b1\n[the lowest-numbered + PMP CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nTST12-2x(group) => FTR01-f\n [PMP check on load or load-reserved instruction + where effective privilege mode is M:\n - choose a data readable pmp region + and address range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe + mandatorily the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + M mode when the bit mstatus.MPRV=0]\n [create scenarios where PMP entries + with A=2 (NA4) and with/without matching permissions\n - check only NA4 + defined addresses are matching]\nTST12-25 (MEDIUM-PRIO)\n[with L=1 => FTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure the PMP entry + without read permissions for the PMP region\n - execute a load or load-reserved + instruction from that region (with exact address-matching)\n - check load + access-fault exception raised => FTR04-c]" +- 011_load_L1_R1_addr_miss: !Subfeature + name: 011_load_L1_R1_addr_miss + tag: VP_PMP_F012_S026 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S026_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction from + outside defined NA4 address range with read permissions and with L=1\n \ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\nACCESS\n \ + \ - execute a load or load-reserved instruction from outside all PMP defined + regions\n\nCHECK\n - check no access-fault exception (Feature: \"no cfg + matching\")\n\nREUSABILITY\n - if possible, the PMP entry number (i) + is a configurable parameter\n - if possible, the PMP entry lock (L) is + a configurable parameter\n - if possible, the PMP entry permissions (R,W,X) + are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-2x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in M mode when the + bit mstatus.MPRV=0]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\nTST12-26 (HIGH-PRIO)\n[with L=1 => FTR08-e1 (refers to FTR01-f) + (refers to FTR09-d2-1),\n - configure the PMP entry with read permissions + for the PMP region\n - execute a load or load-reserved instruction from + outside all PMP defined regions\n - check no access-fault exception] //TODO: + CHECK IF M-MODE ALLOWED" +- 012_store_L0_W1_addr_hit: !Subfeature + name: 012_store_L0_W1_addr_hit + tag: VP_PMP_F012_S031 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S031_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range with write permissions and with L=0\n \ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n\nCHECK\n - check no access-fault + exception\n\nREUSABILITY\n - if possible, the PMP entry number (i) is + a configurable parameter\n - if possible, the PMP entry lock (L) is a + configurable parameter\n - if possible, the PMP entry permissions (R,W,X) + are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-3x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in M mode + when the bit mstatus.MPRV=0]\n [create scenarios where PMP entries with + A=2 (NA4) and with/without matching permissions\n - check only NA4 defined + addresses are matching]\nTST12-31 (LOW-PRIO)\n[with L=0 => FTR08-e2-1 (refers + to FTR09-d1)\n - configure the PMP entry with write permissions for the + PMP region\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n - check no access-fault exception]" +- 013_store_L0_W0_addr_hit: !Subfeature + name: 013_store_L0_W0_addr_hit + tag: VP_PMP_F012_S032 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S032_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range without write permissions and with L=0\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=0, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n\nCHECK\n - check no access-fault + exception\n\nREUSABILITY\n - if possible, the PMP entry number (i) is + a configurable parameter\n - if possible, the PMP entry lock (L) is a + configurable parameter\n - if possible, the PMP entry permissions (R,W,X) + are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-3x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in M mode + when the bit mstatus.MPRV=0]\n [create scenarios where PMP entries with + A=2 (NA4) and with/without matching permissions\n - check only NA4 defined + addresses are matching]\nTST12-32 (LOW-PRIO)\n[with L=0 => FTR08-e2-1 (refers + to FTR09-d1)\n - configure the PMP entry without write permissions for + the PMP region\n - execute a store, store-conditional, or AMO instruction + to that region (with exact address-matching)\n - check no access-fault + exception]" +- 014_store_L0_W1_addr_miss: !Subfeature + name: 014_store_L0_W1_addr_miss + tag: VP_PMP_F012_S033 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S033_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + from outside defined NA4 address range with write permissions and with L=0\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + outside all PMP defined regions\n\nCHECK\n - check no access-fault exception + (Feature: \"no cfg matching\")\n\nREUSABILITY\n - if possible, the PMP + entry number (i) is a configurable parameter\n - if possible, the PMP + entry lock (L) is a configurable parameter\n - if possible, the PMP entry + permissions (R,W,X) are configurable parameters\n - if possible, the + PMP entry address-matching mode (A) is a configurable parameter\n - if + possible, the PMP entry address range (pmpaddr) is a configurable parameter\n\ + \ - if possible, the PMP entry associated access address is a configurable + parameter\n - so a single CONFIGURATION function and a single ACCESS + function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-3x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in M mode + when the bit mstatus.MPRV=0]\n [create scenarios where PMP entries with + A=2 (NA4) and with/without matching permissions\n - check only NA4 defined + addresses are matching]\nTST12-33 (LOW-PRIO)\n[with L=0 => FTR08-e2-1 (refers + to FTR09-d1)\n - configure the PMP entry with write permissions for the + PMP region\n - execute a store, store-conditional, or AMO instruction to + outside all PMP defined regions\n - check no access-fault exception] //TODO: + CHECK IF M-MODE ALLOWED" +- 015_store_L1_W1_addr_hit: !Subfeature + name: 015_store_L1_W1_addr_hit + tag: VP_PMP_F012_S034 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S034_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range with write permissions and with L=1\n \ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n\nCHECK\n - check no access-fault + exception\n\nREUSABILITY\n - if possible, the PMP entry number (i) is + a configurable parameter\n - if possible, the PMP entry lock (L) is a + configurable parameter\n - if possible, the PMP entry permissions (R,W,X) + are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-3x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in M mode + when the bit mstatus.MPRV=0]\n [create scenarios where PMP entries with + A=2 (NA4) and with/without matching permissions\n - check only NA4 defined + addresses are matching]\nTST12-34 (HIGH-PRIO)\n[with L=1 => FTR08-e1 (refers + to FTR01-f) (refers to FTR09-d2-1),\n - configure the PMP entry with write + permissions for the PMP region\n - execute a store, store-conditional, + or AMO instruction to that region (with exact address-matching)\n - check + no access-fault exception]" +- 016_store_L1_W0_addr_hit: !Subfeature + name: 016_store_L1_W0_addr_hit + tag: VP_PMP_F012_S035 + next_elt_id: 1 + display_order: 16 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S035_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set\n\n{Page + 58 Volume II: RISC-V Privileged Architectures V20211203}\nAttempting to + execute a store, store-conditional, or AMO instruction which accesses a + physical address within a PMP region without write permissions raises a + store access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range without write permissions and with L=1\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=0, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n\nCHECK\n - check store access-fault + exception raised\n\nREUSABILITY\n - if possible, the PMP entry number + (i) is a configurable parameter\n - if possible, the PMP entry lock (L) + is a configurable parameter\n - if possible, the PMP entry permissions + (R,W,X) are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR04-d\n[Attempting to execute a store, store-conditional, or AMO instruction + which accesses a physical address within a PMP region without write permissions + raises a store access-fault exception]\n\nFTR02-b1\n[the lowest-numbered + PMP CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \n TST12-3x(group) => FTR01-f\n [PMP check on store, store-conditional, + or AMO instruction where effective privilege mode is M:\n - choose a + data writable pmp region and address range\n - choose only one PMP entry + (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n - if possible, the + PMP entry number is a configurable parameter\n - choose pmpcfg(i).A=NA4\n\ + \ - single access data store in M mode when the bit mstatus.MPRV=0]\n\ + \ [create scenarios where PMP entries with A=2 (NA4) and with/without matching + permissions\n - check only NA4 defined addresses are matching]\nTST12-35 + (MEDIUM-PRIO)\n[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n\ + \ - configure the PMP entry without write permissions for the PMP region\n\ + \ - execute a store, store-conditional, or AMO instruction to that region + (with exact address-matching)\n - check store access-fault exception raised + => FTR04-d]" +- 017_store_L1_W1_addr_miss: !Subfeature + name: 017_store_L1_W1_addr_miss + tag: VP_PMP_F012_S036 + next_elt_id: 1 + display_order: 17 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S036_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + from outside defined NA4 address range with write permissions and with L=1\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=0\n\n\ + ACCESS\n - execute a store, store-conditional, or AMO instruction to + outside all PMP defined regions\n\nCHECK\n - check no access-fault exception + (Feature: \"no cfg matching\")\n\nREUSABILITY\n - if possible, the PMP + entry number (i) is a configurable parameter\n - if possible, the PMP + entry lock (L) is a configurable parameter\n - if possible, the PMP entry + permissions (R,W,X) are configurable parameters\n - if possible, the + PMP entry address-matching mode (A) is a configurable parameter\n - if + possible, the PMP entry address range (pmpaddr) is a configurable parameter\n\ + \ - if possible, the PMP entry associated access address is a configurable + parameter\n - so a single CONFIGURATION function and a single ACCESS + function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-3x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in M mode + when the bit mstatus.MPRV=0]\n [create scenarios where PMP entries with + A=2 (NA4) and with/without matching permissions\n - check only NA4 defined + addresses are matching]\nTST12-36 (HIGH-PRIO)\n[with L=1 => FTR08-e1 (refers + to FTR01-f) (refers to FTR09-d2-1),\n - configure the PMP entry with write + permissions for the PMP region\n - execute a store, store-conditional, + or AMO instruction to outside all PMP defined regions\n - check no access-fault + exception] //TODO: CHECK IF M-MODE ALLOWED" +- 018_load_MPP_L0_R1_addr_hit: !Subfeature + name: 018_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F012_S041 + next_elt_id: 1 + display_order: 18 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S041_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction inside + defined NA4 address range with read permissions and with L=0\n - choose + a readable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n \ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute a load + or load-reserved instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check no access-fault exception\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-4x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in any mode when the + bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING + SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) and with/without + matching permissions\n - check only NA4 defined addresses are matching]\n + TST12-41 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-1 (refers to FTR09-d1)\n\ + \ - configure the PMP entry with read permissions for the PMP region\n\ + \ - execute a load or load-reserved instruction from that region (with + exact address-matching)\n - check no access-fault exception]" +- 019_load_MPP_L0_R0_addr_hit: !Subfeature + name: 019_load_MPP_L0_R0_addr_hit + tag: VP_PMP_F012_S042 + next_elt_id: 1 + display_order: 19 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S042_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction inside + defined NA4 address range without read permissions and with L=0\n - choose + a readable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=0, L=0, X/W:random\n \ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute a load + or load-reserved instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check no access-fault exception\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-4x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in any mode when the + bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING + SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) and with/without + matching permissions\n - check only NA4 defined addresses are matching]\n + TST12-42 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-1 (refers to FTR09-d1)\n\ + \ - configure the PMP entry without read permissions for the PMP region\n\ + \ - execute a load or load-reserved instruction from that region (with + exact address-matching)\n - check no access-fault exception]" +- 020_load_MPP_L0_R1_addr_miss: !Subfeature + name: 020_load_MPP_L0_R1_addr_miss + tag: VP_PMP_F012_S043 + next_elt_id: 1 + display_order: 20 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S043_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction from + outside defined NA4 address range with read permissions and with L=0\n \ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=0, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute a load + or load-reserved instruction from outside all PMP defined regions\n\nCHECK\n\ + \ - check no access-fault exception (Feature: \"no cfg matching\")\n\n\ + REUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-4x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in any mode when the + bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING + SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) and with/without + matching permissions\n - check only NA4 defined addresses are matching]\n + TST12-43 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-1 (refers to FTR09-d1)\n\ + \ - configure the PMP entry with read permissions for the PMP region\n\ + \ - execute a load or load-reserved instruction from outside all PMP defined + regions\n - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED" +- 021_load_MPP_L1_R1_addr_hit: !Subfeature + name: 021_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F012_S044 + next_elt_id: 1 + display_order: 21 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S044_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction inside + defined NA4 address range with read permissions and with L=1\n - choose + a readable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n \ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute a load + or load-reserved instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check no access-fault exception\n\nREUSABILITY\n - if + possible, the PMP entry number (i) is a configurable parameter\n - if + possible, the PMP entry lock (L) is a configurable parameter\n - if possible, + the PMP entry permissions (R,W,X) are configurable parameters\n - if + possible, the PMP entry address-matching mode (A) is a configurable parameter\n\ + \ - if possible, the PMP entry address range (pmpaddr) is a configurable + parameter\n - if possible, the PMP entry associated access address is + a configurable parameter\n - so a single CONFIGURATION function and a + single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-4x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in any mode when the + bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING + SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) and with/without + matching permissions\n - check only NA4 defined addresses are matching]\n + TST12-44 (LOWEST-PRIO)\n [with L=1 => FTR08-e1 (refers to FTR01-f) (refers + to FTR09-d2-1),\n - configure the PMP entry with read permissions for the + PMP region\n - execute a load or load-reserved instruction from that region + (with exact address-matching)\n - check no access-fault exception]" +- 022_load_MPP_L1_R0_addr_hit: !Subfeature + name: 022_load_MPP_L1_R0_addr_hit + tag: VP_PMP_F012_S045 + next_elt_id: 1 + display_order: 22 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S045_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set\n\n{Page + 58 Volume II: RISC-V Privileged Architectures V20211203}\nAttempting to + execute a load or load-reserved instruction which accesses a physical address + within a PMP region without read permissions raises a load access-fault + exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction inside + defined NA4 address range without read permissions and with L=1\n - choose + a readable pmp region and address range\n - choose only one PMP entry + (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=0, L=1, X/W:random\n \ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute a load + or load-reserved instruction from that region (with exact address-matching)\n\ + \nCHECK\n - check load access-fault exception raised\n\nREUSABILITY\n\ + \ - if possible, the PMP entry number (i) is a configurable parameter\n\ + \ - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR04-c\n[Attempting to execute a load or load-reserved instruction which + accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\nFTR02-b1\n[the lowest-numbered + PMP CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nTST12-4x(group) => FTR01-f\n [PMP check on load or load-reserved instruction + where effective privilege mode is M:\n - choose a data readable pmp region + and address range\n - choose only one PMP entry (i) ([FTR02-b1]: maybe + mandatorily the 1st one)\n - if possible, the PMP entry number is a configurable + parameter\n - choose pmpcfg(i).A=NA4\n - single access data load in + any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: + CHECK IF MAKING SENSE)]\n [create scenarios where PMP entries with A=2 + (NA4) and with/without matching permissions\n - check only NA4 defined + addresses are matching]\nTST12-45 (LOWEST-PRIO)\n[with L=1 => FTR08-e1 (refers + to FTR01-f) (refers to FTR09-d2-1),\n - configure the PMP entry without + read permissions for the PMP region\n - execute a load or load-reserved + instruction from that region (with exact address-matching)\n - check load + access-fault exception raised => FTR04-c]" +- 023_load_MPP_L1_R1_addr_miss: !Subfeature + name: 023_load_MPP_L1_R1_addr_miss + tag: VP_PMP_F012_S046 + next_elt_id: 1 + display_order: 23 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S046_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access load or load-reserved instruction from + outside defined NA4 address range with read permissions and with L=1\n \ + \ - choose a readable pmp region and address range\n - choose only + one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, R=1, L=1, X/W:random\n\ + \ - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and mstatus.MPP + contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute a load + or load-reserved instruction from outside all PMP defined regions\n\nCHECK\n\ + \ - check no access-fault exception (Feature: \"no cfg matching\")\n\n\ + REUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-4x(group) => FTR01-f\n [PMP check + on load or load-reserved instruction where effective privilege mode is M:\n\ + \ - choose a data readable pmp region and address range\n - choose + only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n \ + \ - if possible, the PMP entry number is a configurable parameter\n - + choose pmpcfg(i).A=NA4\n - single access data load in any mode when the + bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING + SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) and with/without + matching permissions\n - check only NA4 defined addresses are matching]\n + TST12-46 (LOWEST-PRIO)\n [with L=1 => FTR08-e1 (refers to FTR01-f) (refers + to FTR09-d2-1),\n - configure the PMP entry with read permissions for the + PMP region\n - execute a load or load-reserved instruction from outside + all PMP defined regions\n - check no access-fault exception] //TODO: CHECK + IF M-MODE ALLOWED" +- 024_store_MPP_L0_W1_addr_hit: !Subfeature + name: 024_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F012_S051 + next_elt_id: 1 + display_order: 24 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S051_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range with write permissions and with L=0\n \ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute + a store, store-conditional, or AMO instruction to that region (with exact + address-matching)\n\nCHECK\n - check no access-fault exception\n\nREUSABILITY\n\ + \ - if possible, the PMP entry number (i) is a configurable parameter\n\ + \ - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-5x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in any mode + when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK + IF MAKING SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\nTST12-51 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-1 (refers to\ + \ FTR09-d1)\n - configure the PMP entry with write permissions for the + PMP region\n - execute a store, store-conditional, or AMO instruction to + that region (with exact address-matching)\n - check no access-fault exception]" +- 025_store_MPP_L0_W0_addr_hit: !Subfeature + name: 025_store_MPP_L0_W0_addr_hit + tag: VP_PMP_F012_S052 + next_elt_id: 1 + display_order: 25 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S052_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range without write permissions and with L=0\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=0, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute + a store, store-conditional, or AMO instruction to that region (with exact + address-matching)\n\nCHECK\n - check no access-fault exception\n\nREUSABILITY\n\ + \ - if possible, the PMP entry number (i) is a configurable parameter\n\ + \ - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-5x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in any mode + when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK + IF MAKING SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\nTST12-52 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-1 (refers to\ + \ FTR09-d1)\n - configure the PMP entry without write permissions for + the PMP region\n - execute a store, store-conditional, or AMO instruction + to that region (with exact address-matching)\n - check no access-fault + exception]" +- 026_store_MPP_L0_W1_addr_miss: !Subfeature + name: 026_store_MPP_L0_W1_addr_miss + tag: VP_PMP_F012_S053 + next_elt_id: 1 + display_order: 26 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S053_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is clear, any M-mode access matching the PMP entry will succeed\n\n + {Page 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nIf the L bit is clear and the privilege mode of + the access is M, the access succeeds" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + from outside defined NA4 address range with write permissions and with L=0\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=0, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute + a store, store-conditional, or AMO instruction to outside all PMP defined + regions\n\nCHECK\n - check no access-fault exception (Feature: \"no cfg + matching\")\n\nREUSABILITY\n - if possible, the PMP entry number (i) + is a configurable parameter\n - if possible, the PMP entry lock (L) is + a configurable parameter\n - if possible, the PMP entry permissions (R,W,X) + are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e2-1 + (refers to FTR09-d1)\n[When the L bit is clear, any M-mode access matching + the PMP entry will succeed]\nFTR09-d1 (refers to FTR08-e2-1)\n [If the L + bit is clear and the privilege mode of the access is M, the access succeeds]\n + \nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-5x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in any mode + when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK + IF MAKING SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\nTST12-53 (LOWEST-PRIO)\n[with L=0 => FTR08-e2-1 (refers to\ + \ FTR09-d1)\n - configure the PMP entry with write permissions for the + PMP region\n - execute a store, store-conditional, or AMO instruction to + outside all PMP defined regions\n - check no access-fault exception] //TODO: + CHECK IF M-MODE ALLOWED" +- 027_store_MPP_L1_W1_addr_hit: !Subfeature + name: 027_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F012_S054 + next_elt_id: 1 + display_order: 27 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S054_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range with write permissions and with L=1\n \ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute + a store, store-conditional, or AMO instruction to that region (with exact + address-matching)\n\nCHECK\n - check no access-fault exception\n\nREUSABILITY\n\ + \ - if possible, the PMP entry number (i) is a configurable parameter\n\ + \ - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-5x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in any mode + when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK + IF MAKING SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST12-54 (LOWEST-PRIO)\n[with L=1 => FTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1),\n - configure the PMP entry with write + permissions for the PMP region\n - execute a store, store-conditional, + or AMO instruction to that region (with exact address-matching)\n - check + no access-fault exception]" +- 028_store_MPP_L1_W0_addr_hit: !Subfeature + name: 028_store_MPP_L1_W0_addr_hit + tag: VP_PMP_F012_S055 + next_elt_id: 1 + display_order: 28 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S055_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set\n\n{Page + 58 Volume II: RISC-V Privileged Architectures V20211203}\nAttempting to + execute a store, store-conditional, or AMO instruction which accesses a + physical address within a PMP region without write permissions raises a + store access-fault exception" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + inside defined NA4 address range without write permissions and with L=1\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=0, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute + a store, store-conditional, or AMO instruction to that region (with exact + address-matching)\n\nCHECK\n - check store access-fault exception raised\n\ + \nREUSABILITY\n - if possible, the PMP entry number (i) is a configurable + parameter\n - if possible, the PMP entry lock (L) is a configurable parameter\n\ + \ - if possible, the PMP entry permissions (R,W,X) are configurable parameters\n\ + \ - if possible, the PMP entry address-matching mode (A) is a configurable + parameter\n - if possible, the PMP entry address range (pmpaddr) is a + configurable parameter\n - if possible, the PMP entry associated access + address is a configurable parameter\n - so a single CONFIGURATION function + and a single ACCESS function can be reused and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR04-d\n[Attempting to execute a store, store-conditional, or AMO instruction + which accesses a physical address within a PMP region without write permissions + raises a store access-fault exception]\n\nFTR02-b1\n[the lowest-numbered + PMP CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \n TST12-5x(group) => FTR01-f\n [PMP check on store, store-conditional, + or AMO instruction where effective privilege mode is M:\n - choose a + data writable pmp region and address range\n - choose only one PMP entry + (i) ([FTR02-b1]: maybe mandatorily the 1st one)\n - if possible, the + PMP entry number is a configurable parameter\n - choose pmpcfg(i).A=NA4\n\ + \ - single access data store in any mode when the bit mstatus.MPRV=1 + and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)]\n [create + scenarios where PMP entries with A=2 (NA4) and with/without matching permissions\n\ + \ - check only NA4 defined addresses are matching]\n TST12-55 (LOWEST-PRIO)\n + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1),\n - configure + the PMP entry without write permissions for the PMP region\n - execute + a store, store-conditional, or AMO instruction to that region (with exact + address-matching)\n - check store access-fault exception raised => FTR04-d]" +- 029_store_MPP_L1_W1_addr_miss: !Subfeature + name: 029_store_MPP_L1_W1_addr_miss + tag: VP_PMP_F012_S056 + next_elt_id: 1 + display_order: 29 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F012_S056_I000 + description: "{Page 56 Volume II: RISC-V Privileged Architectures V20211203}\n + PMP checks may additionally apply to M-mode accesses, in which case the + PMP registers themselves are locked, so that even M-mode software cannot + change them until the hart is reset\n\n{Page 60 Section \"Locking and Privilege + Mode\" Volume II: RISC-V Privileged Architectures V20211203}\nWhen the L + bit is set, these permissions are enforced for all privilege modes\n\n{Page + 60 Section \"Priority and Matching Logic\" Volume II: RISC-V Privileged + Architectures V20211203}\nif the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "M mode single access store, store-conditional, or AMO instruction + from outside defined NA4 address range with write permissions and with L=1\n\ + \ - choose a data writable pmp region and address range\n - choose + only one PMP entry (i)\n\nCONFIGURATION\n - pmpcfg(i): A=NA4, W=1, L=1, + X/R:random\n - pmpaddr(i): NA4 address range\n - mstatus.MPRV=1 and + mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)\n\nACCESS\n - execute + a store, store-conditional, or AMO instruction to outside all PMP defined + regions\n\nCHECK\n - check no access-fault exception (Feature: \"no cfg + matching\")\n\nREUSABILITY\n - if possible, the PMP entry number (i) + is a configurable parameter\n - if possible, the PMP entry lock (L) is + a configurable parameter\n - if possible, the PMP entry permissions (R,W,X) + are configurable parameters\n - if possible, the PMP entry address-matching + mode (A) is a configurable parameter\n - if possible, the PMP entry address + range (pmpaddr) is a configurable parameter\n - if possible, the PMP + entry associated access address is a configurable parameter\n - so a + single CONFIGURATION function and a single ACCESS function can be reused + and combined" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<>\n\n<< link to the + old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) + : reading below not mandatory but may help for better understanding >>\n + \nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally apply to M-mode + accesses, in which case the PMP registers themselves are locked, so that + even M-mode software cannot change them until the hart is reset]\n \nFTR08-e1 + (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the L bit is set, these + permissions are enforced for all privilege modes]\nFTR09-d2-1 (refers to + FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access succeeds + only if the R, W, or X bit corresponding to the access type is set]\n\n + FTR02-b1\n[the lowest-numbered PMP CSRs must be implemented first (QUESTION: + does it mean programmed first)]\n\nTST12-5x(group) => FTR01-f\n [PMP check + on store, store-conditional, or AMO instruction where effective privilege + mode is M:\n - choose a data writable pmp region and address range\n\ + \ - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the + 1st one)\n - if possible, the PMP entry number is a configurable parameter\n\ + \ - choose pmpcfg(i).A=NA4\n - single access data store in any mode + when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK + IF MAKING SENSE)]\n [create scenarios where PMP entries with A=2 (NA4) + and with/without matching permissions\n - check only NA4 defined addresses + are matching]\n TST12-56 (LOWEST-PRIO)\n[with L=1 => FTR08-e1 (refers to + FTR01-f) (refers to FTR09-d2-1),\n - configure the PMP entry with write + permissions for the PMP region\n - execute a store, store-conditional, + or AMO instruction to outside all PMP defined regions\n - check no access-fault + exception] //TODO: CHECK IF M-MODE ALLOWED" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP013.yml b/verif/docs/VerifPlans/PMP/VP_IP013.yml new file mode 100644 index 00000000000..a0a659155d1 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP013.yml @@ -0,0 +1,1133 @@ +!Feature +next_elt_id: 30 +name: cfg NAPOT access S/U +id: 13 +display_order: 13 +subfeatures: !!omap +- 000_fetch_L0_X1_addr_hit: !Subfeature + name: 000_fetch_L0_X1_addr_hit + tag: VP_PMP_F013_S011 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S011_I000 + description: 'reuse of VP_PMP_F011_S011_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-11 (HIGH-PRIO)\n [same as TST11-11(group), but with pmpcfg(i).A=NAPOT]" +- 001_fetch_L0_X0_addr_hit: !Subfeature + name: 001_fetch_L0_X0_addr_hit + tag: VP_PMP_F013_S012 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S012_I000 + description: 'reuse of VP_PMP_F011_S012_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S012_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-b\n [Attempting to fetch an instruction from a PMP region + that does not have execute permissions raises an instruction access-fault + exception]\n \n\nTST13-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-12 (MEDIUM-PRIO)\n [same as TST11-12(group), but with pmpcfg(i).A=NAPOT]" +- 002_fetch_L0_X1_addr_miss: !Subfeature + name: 002_fetch_L0_X1_addr_miss + tag: VP_PMP_F013_S013 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S013_I000 + description: 'reuse of VP_PMP_F011_S013_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S013_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-13 (MEDIUM-PRIO)\n [same as TST11-13(group), but with pmpcfg(i).A=NAPOT]" +- 003_fetch_L1_X1_addr_hit: !Subfeature + name: 003_fetch_L1_X1_addr_hit + tag: VP_PMP_F013_S014 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S014_I000 + description: 'reuse of VP_PMP_F011_S014_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-14 (LOW-PRIO)\n [same as TST11-14(group), but with pmpcfg(i).A=NAPOT]" +- 004_fetch_L1_X0_addr_hit: !Subfeature + name: 004_fetch_L1_X0_addr_hit + tag: VP_PMP_F013_S015 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S015_I000 + description: 'reuse of VP_PMP_F011_S015_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S015_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-b\n[Attempting to fetch an instruction from a PMP region that + does not have execute permissions raises an instruction access-fault exception]\n\ + \n\nTST13-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-15 (LOW-PRIO)\n [same as TST11-15(group), but with pmpcfg(i).A=NAPOT]" +- 005_fetch_L1_X1_addr_miss: !Subfeature + name: 005_fetch_L1_X1_addr_miss + tag: VP_PMP_F013_S016 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S016_I000 + description: 'reuse of VP_PMP_F011_S016_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S016_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-16 (LOW-PRIO)\n [same as TST11-16(group), but with pmpcfg(i).A=NAPOT]" +- 006_load_L0_R1_addr_hit: !Subfeature + name: 006_load_L0_R1_addr_hit + tag: VP_PMP_F013_S021 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S021_I000 + description: 'reuse of VP_PMP_F011_S021_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-21 (HIGH-PRIO)\n [same as TST11-21(group), but with pmpcfg(i).A=NAPOT]" +- 007_load_L0_R0_addr_hit: !Subfeature + name: 007_load_L0_R0_addr_hit + tag: VP_PMP_F013_S022 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S022_I000 + description: 'reuse of VP_PMP_F011_S022_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S022_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n [Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST13-2x(group)\n [same as TST11-2x(group), + but with pmpcfg(i).A=NAPOT]\nTST13-22 (MEDIUM-PRIO)\n [same as TST11-22(group), + but with pmpcfg(i).A=NAPOT]" +- 008_load_L0_R1_addr_miss: !Subfeature + name: 008_load_L0_R1_addr_miss + tag: VP_PMP_F013_S023 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S023_I000 + description: 'reuse of VP_PMP_F011_S023_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S023_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-23 (MEDIUM-PRIO)\n [same as TST11-23(group), but with pmpcfg(i).A=NAPOT]" +- 009_load_L1_R1_addr_hit: !Subfeature + name: 009_load_L1_R1_addr_hit + tag: VP_PMP_F013_S024 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S024_I000 + description: 'reuse of VP_PMP_F011_S024_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-24 (LOW-PRIO)\n [same as TST11-24(group), but with pmpcfg(i).A=NAPOT]" +- 010_load_L1_R0_addr_hit: !Subfeature + name: 010_load_L1_R0_addr_hit + tag: VP_PMP_F013_S025 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S025_I000 + description: 'reuse of VP_PMP_F011_S025_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S025_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST13-2x(group)\n [same as TST11-2x(group), + but with pmpcfg(i).A=NAPOT]\n TST13-25 (LOW-PRIO)\n [same as TST11-25(group), + but with pmpcfg(i).A=NAPOT]" +- 011_load_L1_R1_addr_miss: !Subfeature + name: 011_load_L1_R1_addr_miss + tag: VP_PMP_F013_S026 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S026_I000 + description: 'reuse of VP_PMP_F011_S026_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S026_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-26 (LOW-PRIO)\n [same as TST11-26(group), but with pmpcfg(i).A=NAPOT]" +- 012_store_L0_W1_addr_hit: !Subfeature + name: 012_store_L0_W1_addr_hit + tag: VP_PMP_F013_S031 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S031_I000 + description: 'reuse of VP_PMP_F011_S031_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-31 (HIGH-PRIO)\n [same as TST11-31(group), but with pmpcfg(i).A=NAPOT]" +- 013_store_L0_W0_addr_hit: !Subfeature + name: 013_store_L0_W0_addr_hit + tag: VP_PMP_F013_S032 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S032_I000 + description: 'reuse of VP_PMP_F011_S032_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S032_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n [Attempting to execute a store, store-conditional, or + AMO instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST13-3x(group)\n\ + \ [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT]\nTST13-32 (MEDIUM-PRIO)\n\ + \ [same as TST11-32(group), but with pmpcfg(i).A=NAPOT]" +- 014_store_L0_W1_addr_miss: !Subfeature + name: 014_store_L0_W1_addr_miss + tag: VP_PMP_F013_S033 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S033_I000 + description: 'reuse of VP_PMP_F011_S033_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S033_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-33 (MEDIUM-PRIO)\n [same as TST11-33(group), but with pmpcfg(i).A=NAPOT]" +- 015_store_L1_W1_addr_hit: !Subfeature + name: 015_store_L1_W1_addr_hit + tag: VP_PMP_F013_S034 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S034_I000 + description: 'reuse of VP_PMP_F011_S034_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-34 (LOW-PRIO)\n [same as TST11-34(group), but with pmpcfg(i).A=NAPOT]" +- 016_store_L1_W0_addr_hit: !Subfeature + name: 016_store_L1_W0_addr_hit + tag: VP_PMP_F013_S035 + next_elt_id: 1 + display_order: 16 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S035_I000 + description: 'reuse of VP_PMP_F011_S035_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S035_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, or AMO + instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST13-3x(group)\n\ + \ [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT]\nTST13-35 (LOW-PRIO)\n\ + \ [same as TST11-35(group), but with pmpcfg(i).A=NAPOT]" +- 017_store_L1_W1_addr_miss: !Subfeature + name: 017_store_L1_W1_addr_miss + tag: VP_PMP_F013_S036 + next_elt_id: 1 + display_order: 17 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S036_I000 + description: 'reuse of VP_PMP_F011_S036_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S036_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-36 (LOW-PRIO)\n [same as TST11-36(group), but with pmpcfg(i).A=NAPOT]" +- 018_load_MPP_L0_R1_addr_hit: !Subfeature + name: 018_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F013_S041 + next_elt_id: 1 + display_order: 18 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S041_I000 + description: 'reuse of VP_PMP_F011_S041_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S041_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-41 (LOWEST-PRIO)\n [same as TST11-41(group), but with pmpcfg(i).A=NAPOT]" +- 019_load_MPP_L0_R0_addr_hit: !Subfeature + name: 019_load_MPP_L0_R0_addr_hit + tag: VP_PMP_F013_S042 + next_elt_id: 1 + display_order: 19 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S042_I000 + description: 'reuse of VP_PMP_F011_S042_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S042_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n [Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST13-4x(group)\n [same as TST11-4x(group), + but with pmpcfg(i).A=NAPOT]\nTST13-42 (LOWEST-PRIO)\n [same as TST11-42(group), + but with pmpcfg(i).A=NAPOT]" +- 020_load_MPP_L0_R1_addr_miss: !Subfeature + name: 020_load_MPP_L0_R1_addr_miss + tag: VP_PMP_F013_S043 + next_elt_id: 1 + display_order: 20 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S043_I000 + description: 'reuse of VP_PMP_F011_S043_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S043_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-43 (LOWEST-PRIO)\n [same as TST11-43(group), but with pmpcfg(i).A=NAPOT]" +- 021_load_MPP_L1_R1_addr_hit: !Subfeature + name: 021_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F013_S044 + next_elt_id: 1 + display_order: 21 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S044_I000 + description: 'reuse of VP_PMP_F011_S044_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S044_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-44 (LOWEST-PRIO)\n [same as TST11-44(group), but with pmpcfg(i).A=NAPOT]" +- 022_load_MPP_L1_R0_addr_hit: !Subfeature + name: 022_load_MPP_L1_R0_addr_hit + tag: VP_PMP_F013_S045 + next_elt_id: 1 + display_order: 22 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S045_I000 + description: 'reuse of VP_PMP_F011_S045_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S045_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST13-4x(group)\n [same as TST11-4x(group), + but with pmpcfg(i).A=NAPOT]\n TST13-45 (LOWEST-PRIO)\n [same as TST11-45(group), + but with pmpcfg(i).A=NAPOT]" +- 023_load_MPP_L1_R1_addr_miss: !Subfeature + name: 023_load_MPP_L1_R1_addr_miss + tag: VP_PMP_F013_S046 + next_elt_id: 1 + display_order: 23 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S046_I000 + description: 'reuse of VP_PMP_F011_S046_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S046_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-46 (LOWEST-PRIO)\n [same as TST11-46(group), but with pmpcfg(i).A=NAPOT]" +- 024_store_MPP_L0_W1_addr_hit: !Subfeature + name: 024_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F013_S051 + next_elt_id: 1 + display_order: 24 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S051_I000 + description: 'reuse of VP_PMP_F011_S051_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S051_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-51 (LOWEST-PRIO)\n [same as TST11-51(group), but with pmpcfg(i).A=NAPOT]" +- 025_store_MPP_L0_W0_addr_hit: !Subfeature + name: 025_store_MPP_L0_W0_addr_hit + tag: VP_PMP_F013_S052 + next_elt_id: 1 + display_order: 25 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S052_I000 + description: 'reuse of VP_PMP_F011_S052_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S052_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n [Attempting to execute a store, store-conditional, or + AMO instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST13-5x(group)\n\ + \ [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT]\nTST13-52 (LOWEST-PRIO)\n\ + \ [same as TST11-52(group), but with pmpcfg(i).A=NAPOT]" +- 026_store_MPP_L0_W1_addr_miss: !Subfeature + name: 026_store_MPP_L0_W1_addr_miss + tag: VP_PMP_F013_S053 + next_elt_id: 1 + display_order: 26 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S053_I000 + description: 'reuse of VP_PMP_F011_S053_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S053_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-53 (LOWEST-PRIO)\n [same as TST11-53(group), but with pmpcfg(i).A=NAPOT]" +- 027_store_MPP_L1_W1_addr_hit: !Subfeature + name: 027_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F013_S054 + next_elt_id: 1 + display_order: 27 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S054_I000 + description: 'reuse of VP_PMP_F011_S054_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S054_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-54 (LOWEST-PRIO)\n [same as TST11-54(group), but with pmpcfg(i).A=NAPOT]" +- 028_store_MPP_L1_W0_addr_hit: !Subfeature + name: 028_store_MPP_L1_W0_addr_hit + tag: VP_PMP_F013_S055 + next_elt_id: 1 + display_order: 28 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S055_I000 + description: 'reuse of VP_PMP_F011_S055_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S055_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, or AMO + instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST13-5x(group)\n\ + \ [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT]\nTST13-55 (LOWEST-PRIO)\n\ + \ [same as TST11-55(group), but with pmpcfg(i).A=NAPOT]" +- 029_store_MPP_L1_W1_addr_miss: !Subfeature + name: 029_store_MPP_L1_W1_addr_miss + tag: VP_PMP_F013_S056 + next_elt_id: 1 + display_order: 29 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F013_S056_I000 + description: 'reuse of VP_PMP_F011_S056_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S056_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n \ + \ - pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST13-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT]\n + TST13-56 (LOWEST-PRIO)\n [same as TST11-56(group), but with pmpcfg(i).A=NAPOT]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP014.yml b/verif/docs/VerifPlans/PMP/VP_IP014.yml new file mode 100644 index 00000000000..6d5b1e0ba49 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP014.yml @@ -0,0 +1,1119 @@ +!Feature +next_elt_id: 30 +name: cfg NAPOT access M +id: 14 +display_order: 14 +subfeatures: !!omap +- 000_fetch_L0_X1_addr_hit: !Subfeature + name: 000_fetch_L0_X1_addr_hit + tag: VP_PMP_F014_S011 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S011_I000 + description: 'reuse of VP_PMP_F012_S011_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT]\nTST14-11 (LOW-PRIO)\n\ + \ [same as TST12-11(group), but with pmpcfg(i).A=NAPOT]" +- 001_fetch_L0_X0_addr_hit: !Subfeature + name: 001_fetch_L0_X0_addr_hit + tag: VP_PMP_F014_S012 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S012_I000 + description: 'reuse of VP_PMP_F012_S012_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S012_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT]\nTST14-12 (LOW-PRIO)\n\ + \ [same as TST12-12(group), but with pmpcfg(i).A=NAPOT]" +- 002_fetch_L0_X1_addr_miss: !Subfeature + name: 002_fetch_L0_X1_addr_miss + tag: VP_PMP_F014_S013 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S013_I000 + description: 'reuse of VP_PMP_F012_S013_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S013_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT]\nTST14-13 (LOW-PRIO)\n\ + \ [same as TST12-13(group), but with pmpcfg(i).A=NAPOT]" +- 003_fetch_L1_X1_addr_hit: !Subfeature + name: 003_fetch_L1_X1_addr_hit + tag: VP_PMP_F014_S014 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S014_I000 + description: 'reuse of VP_PMP_F012_S014_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT]\nTST14-14 (HIGH-PRIO)\n\ + \ [same as TST12-14(group), but with pmpcfg(i).A=NAPOT]" +- 004_fetch_L1_X0_addr_hit: !Subfeature + name: 004_fetch_L1_X0_addr_hit + tag: VP_PMP_F014_S015 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S015_I000 + description: 'reuse of VP_PMP_F012_S015_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S015_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-b\n[Attempting to fetch an instruction from + a PMP region that does not have execute permissions raises an instruction + access-fault exception]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT]\nTST14-15 (MEDIUM-PRIO)\n\ + \ [same as TST12-15(group), but with pmpcfg(i).A=NAPOT]" +- 005_fetch_L1_X1_addr_miss: !Subfeature + name: 005_fetch_L1_X1_addr_miss + tag: VP_PMP_F014_S016 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S016_I000 + description: 'reuse of VP_PMP_F012_S016_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S016_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT]\nTST14-16 (HIGH-PRIO)\n\ + \ [same as TST12-16(group), but with pmpcfg(i).A=NAPOT]" +- 006_load_L0_R1_addr_hit: !Subfeature + name: 006_load_L0_R1_addr_hit + tag: VP_PMP_F014_S021 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S021_I000 + description: 'reuse of VP_PMP_F012_S021_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT]\nTST14-21 (LOW-PRIO)\n\ + \ [same as TST12-21(group), but with pmpcfg(i).A=NAPOT]" +- 007_load_L0_R0_addr_hit: !Subfeature + name: 007_load_L0_R0_addr_hit + tag: VP_PMP_F014_S022 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S022_I000 + description: 'reuse of VP_PMP_F012_S022_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S022_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT]\nTST14-22 (LOW-PRIO)\n\ + \ [same as TST12-22(group), but with pmpcfg(i).A=NAPOT]" +- 008_load_L0_R1_addr_miss: !Subfeature + name: 008_load_L0_R1_addr_miss + tag: VP_PMP_F014_S023 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S023_I000 + description: 'reuse of VP_PMP_F012_S023_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S023_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT]\nTST14-23 (LOW-PRIO)\n\ + \ [same as TST12-23(group), but with pmpcfg(i).A=NAPOT]" +- 009_load_L1_R1_addr_hit: !Subfeature + name: 009_load_L1_R1_addr_hit + tag: VP_PMP_F014_S024 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S024_I000 + description: 'reuse of VP_PMP_F012_S024_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT]\nTST14-24 (HIGH-PRIO)\n\ + \ [same as TST12-24(group), but with pmpcfg(i).A=NAPOT]" +- 010_load_L1_R0_addr_hit: !Subfeature + name: 010_load_L1_R0_addr_hit + tag: VP_PMP_F014_S025 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S025_I000 + description: 'reuse of VP_PMP_F012_S025_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S025_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved + instruction which accesses a physical address within a PMP region without + read permissions raises a load access-fault exception]\n\nFTR02-b1\n[the + lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean + programmed first)]\n \n\nTST14-2x(group)\n [same as TST12-2x(group), but + with pmpcfg(i).A=NAPOT]\n TST14-25 (MEDIUM-PRIO)\n [same as TST12-25(group), + but with pmpcfg(i).A=NAPOT]" +- 011_load_L1_R1_addr_miss: !Subfeature + name: 011_load_L1_R1_addr_miss + tag: VP_PMP_F014_S026 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S026_I000 + description: 'reuse of VP_PMP_F012_S026_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S026_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT]\nTST14-26 (HIGH-PRIO)\n\ + \ [same as TST12-26(group), but with pmpcfg(i).A=NAPOT]" +- 012_store_L0_W1_addr_hit: !Subfeature + name: 012_store_L0_W1_addr_hit + tag: VP_PMP_F014_S031 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S031_I000 + description: 'reuse of VP_PMP_F012_S031_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT]\nTST14-31 (LOW-PRIO)\n\ + \ [same as TST12-31(group), but with pmpcfg(i).A=NAPOT]" +- 013_store_L0_W0_addr_hit: !Subfeature + name: 013_store_L0_W0_addr_hit + tag: VP_PMP_F014_S032 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S032_I000 + description: 'reuse of VP_PMP_F012_S032_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S032_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT]\nTST14-32 (LOW-PRIO)\n\ + \ [same as TST12-32(group), but with pmpcfg(i).A=NAPOT]" +- 014_store_L0_W1_addr_miss: !Subfeature + name: 014_store_L0_W1_addr_miss + tag: VP_PMP_F014_S033 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S033_I000 + description: 'reuse of VP_PMP_F012_S033_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S033_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT]\nTST14-33 (LOW-PRIO)\n\ + \ [same as TST12-33(group), but with pmpcfg(i).A=NAPOT]" +- 015_store_L1_W1_addr_hit: !Subfeature + name: 015_store_L1_W1_addr_hit + tag: VP_PMP_F014_S034 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S034_I000 + description: 'reuse of VP_PMP_F012_S034_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT]\nTST14-34 (HIGH-PRIO)\n\ + \ [same as TST12-34(group), but with pmpcfg(i).A=NAPOT]" +- 016_store_L1_W0_addr_hit: !Subfeature + name: 016_store_L1_W0_addr_hit + tag: VP_PMP_F014_S035 + next_elt_id: 1 + display_order: 16 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S035_I000 + description: 'reuse of VP_PMP_F012_S035_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S035_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, + or AMO instruction which accesses a physical address within a PMP region + without write permissions raises a store access-fault exception]\n\nFTR02-b1\n + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does + it mean programmed first)]\n\n\nTST14-3x(group)\n [same as TST12-3x(group), + but with pmpcfg(i).A=NAPOT]\nTST14-35 (MEDIUM-PRIO)\n [same as TST12-35(group), + but with pmpcfg(i).A=NAPOT]" +- 017_store_L1_W1_addr_miss: !Subfeature + name: 017_store_L1_W1_addr_miss + tag: VP_PMP_F014_S036 + next_elt_id: 1 + display_order: 17 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S036_I000 + description: 'reuse of VP_PMP_F012_S036_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S036_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT]\nTST14-36 (HIGH-PRIO)\n\ + \ [same as TST12-36(group), but with pmpcfg(i).A=NAPOT]" +- 018_load_MPP_L0_R1_addr_hit: !Subfeature + name: 018_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F014_S041 + next_elt_id: 1 + display_order: 18 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S041_I000 + description: 'reuse of VP_PMP_F012_S041_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S041_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT]\nTST14-41 (LOWEST-PRIO)\n\ + \ [same as TST12-41(group), but with pmpcfg(i).A=NAPOT]" +- 019_load_MPP_L0_R0_addr_hit: !Subfeature + name: 019_load_MPP_L0_R0_addr_hit + tag: VP_PMP_F014_S042 + next_elt_id: 1 + display_order: 19 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S042_I000 + description: 'reuse of VP_PMP_F012_S042_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S042_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT]\nTST14-42 (LOWEST-PRIO)\n\ + \ [same as TST12-42(group), but with pmpcfg(i).A=NAPOT]" +- 020_load_MPP_L0_R1_addr_miss: !Subfeature + name: 020_load_MPP_L0_R1_addr_miss + tag: VP_PMP_F014_S043 + next_elt_id: 1 + display_order: 20 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S043_I000 + description: 'reuse of VP_PMP_F012_S043_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S043_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT]\nTST14-43 (LOWEST-PRIO)\n\ + \ [same as TST12-43(group), but with pmpcfg(i).A=NAPOT]" +- 021_load_MPP_L1_R1_addr_hit: !Subfeature + name: 021_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F014_S044 + next_elt_id: 1 + display_order: 21 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S044_I000 + description: 'reuse of VP_PMP_F012_S044_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S044_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT]\nTST14-44 (LOWEST-PRIO)\n\ + \ [same as TST12-44(group), but with pmpcfg(i).A=NAPOT]" +- 022_load_MPP_L1_R0_addr_hit: !Subfeature + name: 022_load_MPP_L1_R0_addr_hit + tag: VP_PMP_F014_S045 + next_elt_id: 1 + display_order: 22 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S045_I000 + description: 'reuse of VP_PMP_F012_S045_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S045_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved + instruction which accesses a physical address within a PMP region without + read permissions raises a load access-fault exception]\n\nFTR02-b1\n[the + lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean + programmed first)]\n \n\nTST14-4x(group)\n [same as TST12-4x(group), but + with pmpcfg(i).A=NAPOT]\n TST14-45 (LOWEST-PRIO)\n [same as TST12-45(group), + but with pmpcfg(i).A=NAPOT]" +- 023_load_MPP_L1_R1_addr_miss: !Subfeature + name: 023_load_MPP_L1_R1_addr_miss + tag: VP_PMP_F014_S046 + next_elt_id: 1 + display_order: 23 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S046_I000 + description: 'reuse of VP_PMP_F012_S046_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S046_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT]\nTST14-46 (LOWEST-PRIO)\n\ + \ [same as TST12-46(group), but with pmpcfg(i).A=NAPOT]" +- 024_store_MPP_L0_W1_addr_hit: !Subfeature + name: 024_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F014_S051 + next_elt_id: 1 + display_order: 24 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S051_I000 + description: 'reuse of VP_PMP_F012_S051_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S051_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT]\nTST14-51 (LOWEST-PRIO)\n\ + \ [same as TST12-51(group), but with pmpcfg(i).A=NAPOT]" +- 025_store_MPP_L0_W0_addr_hit: !Subfeature + name: 025_store_MPP_L0_W0_addr_hit + tag: VP_PMP_F014_S052 + next_elt_id: 1 + display_order: 25 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S052_I000 + description: 'reuse of VP_PMP_F012_S052_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S052_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT]\nTST14-52 (LOWEST-PRIO)\n\ + \ [same as TST12-52(group), but with pmpcfg(i).A=NAPOT]" +- 026_store_MPP_L0_W1_addr_miss: !Subfeature + name: 026_store_MPP_L0_W1_addr_miss + tag: VP_PMP_F014_S053 + next_elt_id: 1 + display_order: 26 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S053_I000 + description: 'reuse of VP_PMP_F012_S053_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S053_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST14-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT]\nTST14-53 (LOWEST-PRIO)\n\ + \ [same as TST12-53(group), but with pmpcfg(i).A=NAPOT]" +- 027_store_MPP_L1_W1_addr_hit: !Subfeature + name: 027_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F014_S054 + next_elt_id: 1 + display_order: 27 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S054_I000 + description: 'reuse of VP_PMP_F012_S054_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S054_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT]\nTST14-54 (LOWEST-PRIO)\n\ + \ [same as TST12-54(group), but with pmpcfg(i).A=NAPOT]" +- 028_store_MPP_L1_W0_addr_hit: !Subfeature + name: 028_store_MPP_L1_W0_addr_hit + tag: VP_PMP_F014_S055 + next_elt_id: 1 + display_order: 28 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S055_I000 + description: 'reuse of VP_PMP_F012_S055_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S055_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, + or AMO instruction which accesses a physical address within a PMP region + without write permissions raises a store access-fault exception]\n\nFTR02-b1\n + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does + it mean programmed first)]\n\n\nTST14-5x(group)\n [same as TST12-5x(group), + but with pmpcfg(i).A=NAPOT]\nTST14-55 (LOWEST-PRIO)\n [same as TST12-55(group), + but with pmpcfg(i).A=NAPOT]" +- 029_store_MPP_L1_W1_addr_miss: !Subfeature + name: 029_store_MPP_L1_W1_addr_miss + tag: VP_PMP_F014_S056 + next_elt_id: 1 + display_order: 29 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F014_S056_I000 + description: 'reuse of VP_PMP_F012_S056_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S056_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=NAPOT\n - + pmpaddr(i): any NAPOT address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST14-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT]\nTST14-56 (LOWEST-PRIO)\n\ + \ [same as TST12-56(group), but with pmpcfg(i).A=NAPOT]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP015.yml b/verif/docs/VerifPlans/PMP/VP_IP015.yml new file mode 100644 index 00000000000..a84fd152c55 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP015.yml @@ -0,0 +1,1502 @@ +!Feature +next_elt_id: 36 +name: cfg TOR access S/U +id: 15 +display_order: 15 +subfeatures: !!omap +- 000_fetch_L0_X1_addr_hit: !Subfeature + name: 000_fetch_L0_X1_addr_hit + tag: VP_PMP_F015_S011 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S011_I000 + description: 'reuse of VP_PMP_F011_S011_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=TOR]\n + TST15-11 (HIGH-PRIO)\n [same as TST11-11(group), but with pmpcfg(i).A=TOR]" +- 001_fetch_L0_X0_addr_hit: !Subfeature + name: 001_fetch_L0_X0_addr_hit + tag: VP_PMP_F015_S012 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S012_I000 + description: 'reuse of VP_PMP_F011_S012_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S012_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-b\n [Attempting to fetch an instruction from a PMP region + that does not have execute permissions raises an instruction access-fault + exception]\n \n\nTST15-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=TOR]\n + TST15-12 (MEDIUM-PRIO)\n [same as TST11-12(group), but with pmpcfg(i).A=TOR]" +- 002_fetch_L0_X1_addr_miss: !Subfeature + name: 002_fetch_L0_X1_addr_miss + tag: VP_PMP_F015_S013 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S013_I000 + description: 'reuse of VP_PMP_F011_S013_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S013_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=TOR]\n + TST15-13 (MEDIUM-PRIO)\n [same as TST11-13(group), but with pmpcfg(i).A=TOR]" +- 003_fetch_L1_X1_addr_hit: !Subfeature + name: 003_fetch_L1_X1_addr_hit + tag: VP_PMP_F015_S014 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S014_I000 + description: 'reuse of VP_PMP_F011_S014_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=TOR]\n + TST15-14 (LOW-PRIO)\n [same as TST11-14(group), but with pmpcfg(i).A=TOR]" +- 004_fetch_L1_X0_addr_hit: !Subfeature + name: 004_fetch_L1_X0_addr_hit + tag: VP_PMP_F015_S015 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S015_I000 + description: 'reuse of VP_PMP_F011_S015_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S015_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-b\n[Attempting to fetch an instruction from a PMP region that + does not have execute permissions raises an instruction access-fault exception]\n\ + \n\nTST15-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=TOR]\n + TST15-15 (LOW-PRIO)\n [same as TST11-15(group), but with pmpcfg(i).A=TOR]" +- 005_fetch_L1_X1_addr_miss: !Subfeature + name: 005_fetch_L1_X1_addr_miss + tag: VP_PMP_F015_S016 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S016_I000 + description: 'reuse of VP_PMP_F011_S016_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S016_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=TOR]\n + TST15-16 (LOW-PRIO)\n [same as TST11-16(group), but with pmpcfg(i).A=TOR]" +- 006_load_L0_R1_addr_hit: !Subfeature + name: 006_load_L0_R1_addr_hit + tag: VP_PMP_F015_S021 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S021_I000 + description: 'reuse of VP_PMP_F011_S021_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=TOR]\n + TST15-21 (HIGH-PRIO)\n [same as TST11-21(group), but with pmpcfg(i).A=TOR]" +- 007_load_L0_R0_addr_hit: !Subfeature + name: 007_load_L0_R0_addr_hit + tag: VP_PMP_F015_S022 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S022_I000 + description: 'reuse of VP_PMP_F011_S022_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S022_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n [Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST15-2x(group)\n [same as TST11-2x(group), + but with pmpcfg(i).A=TOR]\nTST15-22 (MEDIUM-PRIO)\n [same as TST11-22(group), + but with pmpcfg(i).A=TOR]" +- 008_load_L0_R1_addr_miss: !Subfeature + name: 008_load_L0_R1_addr_miss + tag: VP_PMP_F015_S023 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S023_I000 + description: 'reuse of VP_PMP_F011_S023_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S023_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=TOR]\n + TST15-23 (MEDIUM-PRIO)\n [same as TST11-23(group), but with pmpcfg(i).A=TOR]" +- 009_load_L1_R1_addr_hit: !Subfeature + name: 009_load_L1_R1_addr_hit + tag: VP_PMP_F015_S024 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S024_I000 + description: 'reuse of VP_PMP_F011_S024_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=TOR]\n + TST15-24 (LOW-PRIO)\n [same as TST11-24(group), but with pmpcfg(i).A=TOR]" +- 010_load_L1_R0_addr_hit: !Subfeature + name: 010_load_L1_R0_addr_hit + tag: VP_PMP_F015_S025 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S025_I000 + description: 'reuse of VP_PMP_F011_S025_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S025_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST15-2x(group)\n [same as TST11-2x(group), + but with pmpcfg(i).A=TOR]\n TST15-25 (LOW-PRIO)\n [same as TST11-25(group), + but with pmpcfg(i).A=TOR]" +- 011_load_L1_R1_addr_miss: !Subfeature + name: 011_load_L1_R1_addr_miss + tag: VP_PMP_F015_S026 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S026_I000 + description: 'reuse of VP_PMP_F011_S026_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S026_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=TOR]\n + TST15-26 (LOW-PRIO)\n [same as TST11-26(group), but with pmpcfg(i).A=TOR]" +- 012_store_L0_W1_addr_hit: !Subfeature + name: 012_store_L0_W1_addr_hit + tag: VP_PMP_F015_S031 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S031_I000 + description: 'reuse of VP_PMP_F011_S031_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=TOR]\n + TST15-31 (HIGH-PRIO)\n [same as TST11-31(group), but with pmpcfg(i).A=TOR]" +- 013_store_L0_W0_addr_hit: !Subfeature + name: 013_store_L0_W0_addr_hit + tag: VP_PMP_F015_S032 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S032_I000 + description: 'reuse of VP_PMP_F011_S032_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S032_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n [Attempting to execute a store, store-conditional, or + AMO instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST15-3x(group)\n\ + \ [same as TST11-3x(group), but with pmpcfg(i).A=TOR]\nTST15-32 (MEDIUM-PRIO)\n\ + \ [same as TST11-32(group), but with pmpcfg(i).A=TOR]" +- 014_store_L0_W1_addr_miss: !Subfeature + name: 014_store_L0_W1_addr_miss + tag: VP_PMP_F015_S033 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S033_I000 + description: 'reuse of VP_PMP_F011_S033_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S033_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=TOR]\n + TST15-33 (MEDIUM-PRIO)\n [same as TST11-33(group), but with pmpcfg(i).A=TOR]" +- 015_store_L1_W1_addr_hit: !Subfeature + name: 015_store_L1_W1_addr_hit + tag: VP_PMP_F015_S034 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S034_I000 + description: 'reuse of VP_PMP_F011_S034_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=TOR]\n + TST15-34 (LOW-PRIO)\n [same as TST11-34(group), but with pmpcfg(i).A=TOR]" +- 016_store_L1_W0_addr_hit: !Subfeature + name: 016_store_L1_W0_addr_hit + tag: VP_PMP_F015_S035 + next_elt_id: 1 + display_order: 16 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S035_I000 + description: 'reuse of VP_PMP_F011_S035_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S035_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, or AMO + instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST15-3x(group)\n\ + \ [same as TST11-3x(group), but with pmpcfg(i).A=TOR]\nTST15-35 (LOW-PRIO)\n\ + \ [same as TST11-35(group), but with pmpcfg(i).A=TOR]" +- 017_store_L1_W1_addr_miss: !Subfeature + name: 017_store_L1_W1_addr_miss + tag: VP_PMP_F015_S036 + next_elt_id: 1 + display_order: 17 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S036_I000 + description: 'reuse of VP_PMP_F011_S036_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S036_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=TOR]\n + TST15-36 (LOW-PRIO)\n [same as TST11-36(group), but with pmpcfg(i).A=TOR]" +- 018_load_MPP_L0_R1_addr_hit: !Subfeature + name: 018_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F015_S041 + next_elt_id: 1 + display_order: 18 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S041_I000 + description: 'reuse of VP_PMP_F011_S041_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S041_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=TOR]\n + TST15-41 (LOWEST-PRIO)\n [same as TST11-41(group), but with pmpcfg(i).A=TOR]" +- 019_load_MPP_L0_R0_addr_hit: !Subfeature + name: 019_load_MPP_L0_R0_addr_hit + tag: VP_PMP_F015_S042 + next_elt_id: 1 + display_order: 19 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S042_I000 + description: 'reuse of VP_PMP_F011_S042_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S042_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n [Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST15-4x(group)\n [same as TST11-4x(group), + but with pmpcfg(i).A=TOR]\nTST15-42 (LOWEST-PRIO)\n [same as TST11-42(group), + but with pmpcfg(i).A=TOR]" +- 020_load_MPP_L0_R1_addr_miss: !Subfeature + name: 020_load_MPP_L0_R1_addr_miss + tag: VP_PMP_F015_S043 + next_elt_id: 1 + display_order: 20 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S043_I000 + description: 'reuse of VP_PMP_F011_S043_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S043_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=TOR]\n + TST15-43 (LOWEST-PRIO)\n [same as TST11-43(group), but with pmpcfg(i).A=TOR]" +- 021_load_MPP_L1_R1_addr_hit: !Subfeature + name: 021_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F015_S044 + next_elt_id: 1 + display_order: 21 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S044_I000 + description: 'reuse of VP_PMP_F011_S044_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S044_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=TOR]\n + TST15-44 (LOWEST-PRIO)\n [same as TST11-44(group), but with pmpcfg(i).A=TOR]" +- 022_load_MPP_L1_R0_addr_hit: !Subfeature + name: 022_load_MPP_L1_R0_addr_hit + tag: VP_PMP_F015_S045 + next_elt_id: 1 + display_order: 22 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S045_I000 + description: 'reuse of VP_PMP_F011_S045_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S045_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST15-4x(group)\n [same as TST11-4x(group), + but with pmpcfg(i).A=TOR]\n TST15-45 (LOWEST-PRIO)\n [same as TST11-45(group), + but with pmpcfg(i).A=TOR]" +- 023_load_MPP_L1_R1_addr_miss: !Subfeature + name: 023_load_MPP_L1_R1_addr_miss + tag: VP_PMP_F015_S046 + next_elt_id: 1 + display_order: 23 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S046_I000 + description: 'reuse of VP_PMP_F011_S046_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S046_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=TOR]\n + TST15-46 (LOWEST-PRIO)\n [same as TST11-46(group), but with pmpcfg(i).A=TOR]" +- 024_store_MPP_L0_W1_addr_hit: !Subfeature + name: 024_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F015_S051 + next_elt_id: 1 + display_order: 24 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S051_I000 + description: 'reuse of VP_PMP_F011_S051_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S051_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=TOR]\n + TST15-51 (LOWEST-PRIO)\n [same as TST11-51(group), but with pmpcfg(i).A=TOR]" +- 025_store_MPP_L0_W0_addr_hit: !Subfeature + name: 025_store_MPP_L0_W0_addr_hit + tag: VP_PMP_F015_S052 + next_elt_id: 1 + display_order: 25 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S052_I000 + description: 'reuse of VP_PMP_F011_S052_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S052_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n [Attempting to execute a store, store-conditional, or + AMO instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST15-5x(group)\n\ + \ [same as TST11-5x(group), but with pmpcfg(i).A=TOR]\nTST15-52 (LOWEST-PRIO)\n\ + \ [same as TST11-52(group), but with pmpcfg(i).A=TOR]" +- 026_store_MPP_L0_W1_addr_miss: !Subfeature + name: 026_store_MPP_L0_W1_addr_miss + tag: VP_PMP_F015_S053 + next_elt_id: 1 + display_order: 26 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S053_I000 + description: 'reuse of VP_PMP_F011_S053_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S053_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=TOR]\n + TST15-53 (LOWEST-PRIO)\n [same as TST11-53(group), but with pmpcfg(i).A=TOR]" +- 027_store_MPP_L1_W1_addr_hit: !Subfeature + name: 027_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F015_S054 + next_elt_id: 1 + display_order: 27 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S054_I000 + description: 'reuse of VP_PMP_F011_S054_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S054_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=TOR]\n + TST15-54 (LOWEST-PRIO)\n [same as TST11-54(group), but with pmpcfg(i).A=TOR]" +- 028_store_MPP_L1_W0_addr_hit: !Subfeature + name: 028_store_MPP_L1_W0_addr_hit + tag: VP_PMP_F015_S055 + next_elt_id: 1 + display_order: 28 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S055_I000 + description: 'reuse of VP_PMP_F011_S055_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S055_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, or AMO + instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST15-5x(group)\n\ + \ [same as TST11-5x(group), but with pmpcfg(i).A=TOR]\nTST15-55 (LOWEST-PRIO)\n\ + \ [same as TST11-55(group), but with pmpcfg(i).A=TOR]" +- 029_store_MPP_L1_W1_addr_miss: !Subfeature + name: 029_store_MPP_L1_W1_addr_miss + tag: VP_PMP_F015_S056 + next_elt_id: 1 + display_order: 29 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S056_I000 + description: 'reuse of VP_PMP_F011_S056_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S056_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] + pmpaddr(0) > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=TOR]\n + TST15-56 (LOWEST-PRIO)\n [same as TST11-56(group), but with pmpcfg(i).A=TOR]" +- 030_fetch_L0_X1_addr_forbidden: !Subfeature + name: 030_fetch_L0_X1_addr_forbidden + tag: VP_PMP_F015_S061 + next_elt_id: 1 + display_order: 30 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S061_I000 + description: "reuse of VP_PMP_F011_S011_I000 feature description (Cf. Feature: + \"cfg NA4 access S/U\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for + i=0] pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)\n\nCHECK UPDATE\n\ + \ - check instruction fetch access-fault exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=TOR]\n + TST15-11 (LOW-PRIO)\n [same as TST11-11(group), but with pmpcfg(i).A=TOR]\n + \n\n//TO COMPLETE => FTR06-b\nTST25 = same as TST15+TST16 (groups) with + PMP entry (0) with pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) + with PMP entry (0) with pmpaddr(0) = 0\n [create scenario where PMP entry + pmpcfg(0) with TOR:\n - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO + COMPLETE => FTR06-c\n TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) + and with pmpcfg(i) and pmpcfg(i-1) correct\n [create scenario where PMP + entry pmpcfg(i) with TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry + pmpcfg(i-1) correct]\n [create scenario where PMP entry pmpcfg(0) with + TOR:\n - pmpaddr(0) >= pmpaddr(1/2/3/…)]" +- 031_fetch_L1_X1_addr_forbidden: !Subfeature + name: 031_fetch_L1_X1_addr_forbidden + tag: VP_PMP_F015_S062 + next_elt_id: 1 + display_order: 31 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S062_I000 + description: "reuse of VP_PMP_F011_S014_I000 feature description (Cf. Feature: + \"cfg NA4 access S/U\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for + i=0] pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)\n\nCHECK UPDATE\n\ + \ - check instruction fetch access-fault exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=TOR]\n + TST15-14 (LOW-PRIO)\n [same as TST11-14(group), but with pmpcfg(i).A=TOR]\n + \n\n//TO COMPLETE => FTR06-b\nTST25 = same as TST15+TST16 (groups) with + PMP entry (0) with pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) + with PMP entry (0) with pmpaddr(0) = 0\n [create scenario where PMP entry + pmpcfg(0) with TOR:\n - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO + COMPLETE => FTR06-c\n TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) + and with pmpcfg(i) and pmpcfg(i-1) correct\n [create scenario where PMP + entry pmpcfg(i) with TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry + pmpcfg(i-1) correct]\n [create scenario where PMP entry pmpcfg(0) with + TOR:\n - pmpaddr(0) >= pmpaddr(1/2/3/…)]" +- 032_load_L0_R1_addr_forbidden: !Subfeature + name: 032_load_L0_R1_addr_forbidden + tag: VP_PMP_F015_S063 + next_elt_id: 1 + display_order: 32 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S063_I000 + description: "reuse of VP_PMP_F011_S021_I000 feature description (Cf. Feature: + \"cfg NA4 access S/U\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for + i=0] pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)\n\nCHECK UPDATE\n\ + \ - check load access-fault exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=TOR]\n + TST15-21 (HIGH-PRIO)\n [same as TST11-21(group), but with pmpcfg(i).A=TOR]\n + \n\n//TO COMPLETE => FTR06-b\nTST25 = same as TST15+TST16 (groups) with + PMP entry (0) with pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) + with PMP entry (0) with pmpaddr(0) = 0\n [create scenario where PMP entry + pmpcfg(0) with TOR:\n - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO + COMPLETE => FTR06-c\n TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) + and with pmpcfg(i) and pmpcfg(i-1) correct\n [create scenario where PMP + entry pmpcfg(i) with TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry + pmpcfg(i-1) correct]\n [create scenario where PMP entry pmpcfg(0) with + TOR:\n - pmpaddr(0) >= pmpaddr(1/2/3/…)]" +- 033_load_L1_R1_addr_forbidden: !Subfeature + name: 033_load_L1_R1_addr_forbidden + tag: VP_PMP_F015_S064 + next_elt_id: 1 + display_order: 33 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S064_I000 + description: "reuse of VP_PMP_F011_S024_I000 feature description (Cf. Feature: + \"cfg NA4 access S/U\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for + i=0] pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)\n\nCHECK UPDATE\n\ + \ - check load access-fault exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=TOR]\n + TST15-24 (LOW-PRIO)\n [same as TST11-24(group), but with pmpcfg(i).A=TOR]\n + \n\n//TO COMPLETE => FTR06-b\nTST25 = same as TST15+TST16 (groups) with + PMP entry (0) with pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) + with PMP entry (0) with pmpaddr(0) = 0\n [create scenario where PMP entry + pmpcfg(0) with TOR:\n - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO + COMPLETE => FTR06-c\n TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) + and with pmpcfg(i) and pmpcfg(i-1) correct\n [create scenario where PMP + entry pmpcfg(i) with TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry + pmpcfg(i-1) correct]\n [create scenario where PMP entry pmpcfg(0) with + TOR:\n - pmpaddr(0) >= pmpaddr(1/2/3/…)]" +- 034_store_L0_W1_addr_forbidden: !Subfeature + name: 034_store_L0_W1_addr_forbidden + tag: VP_PMP_F015_S065 + next_elt_id: 1 + display_order: 34 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S065_I000 + description: "reuse of VP_PMP_F011_S031_I000 feature description (Cf. Feature: + \"cfg NA4 access S/U\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for + i=0] pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)\n\nCHECK UPDATE\n\ + \ - check store access-fault exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=TOR]\n + TST15-31 (HIGH-PRIO)\n [same as TST11-31(group), but with pmpcfg(i).A=TOR]\n + \n\n//TO COMPLETE => FTR06-b\nTST25 = same as TST15+TST16 (groups) with + PMP entry (0) with pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) + with PMP entry (0) with pmpaddr(0) = 0\n [create scenario where PMP entry + pmpcfg(0) with TOR:\n - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO + COMPLETE => FTR06-c\n TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) + and with pmpcfg(i) and pmpcfg(i-1) correct\n [create scenario where PMP + entry pmpcfg(i) with TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry + pmpcfg(i-1) correct]\n [create scenario where PMP entry pmpcfg(0) with + TOR:\n - pmpaddr(0) >= pmpaddr(1/2/3/…)]" +- 035_store_L1_W1_addr_forbidden: !Subfeature + name: 035_store_L1_W1_addr_forbidden + tag: VP_PMP_F015_S066 + next_elt_id: 1 + display_order: 35 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F015_S066_I000 + description: "reuse of VP_PMP_F011_S034_I000 feature description (Cf. Feature: + \"cfg NA4 access S/U\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - + [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for + i=0] pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)\n\nCHECK UPDATE\n\ + \ - check store access-fault exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST15-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=TOR]\n + TST15-34 (LOW-PRIO)\n [same as TST11-34(group), but with pmpcfg(i).A=TOR]\n + \n\n//TO COMPLETE => FTR06-b\nTST25 = same as TST15+TST16 (groups) with + PMP entry (0) with pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) + with PMP entry (0) with pmpaddr(0) = 0\n [create scenario where PMP entry + pmpcfg(0) with TOR:\n - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO + COMPLETE => FTR06-c\n TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) + and with pmpcfg(i) and pmpcfg(i-1) correct\n [create scenario where PMP + entry pmpcfg(i) with TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry + pmpcfg(i-1) correct]\n [create scenario where PMP entry pmpcfg(0) with + TOR:\n - pmpaddr(0) >= pmpaddr(1/2/3/…)]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP016.yml b/verif/docs/VerifPlans/PMP/VP_IP016.yml new file mode 100644 index 00000000000..e1902745074 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP016.yml @@ -0,0 +1,1482 @@ +!Feature +next_elt_id: 36 +name: cfg TOR access M +id: 16 +display_order: 16 +subfeatures: !!omap +- 000_fetch_L0_X1_addr_hit: !Subfeature + name: 000_fetch_L0_X1_addr_hit + tag: VP_PMP_F016_S011 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S011_I000 + description: 'reuse of VP_PMP_F012_S011_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=TOR]\nTST16-11 (LOW-PRIO)\n\ + \ [same as TST12-11(group), but with pmpcfg(i).A=TOR]" +- 001_fetch_L0_X0_addr_hit: !Subfeature + name: 001_fetch_L0_X0_addr_hit + tag: VP_PMP_F016_S012 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S012_I000 + description: 'reuse of VP_PMP_F012_S012_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S012_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=TOR]\nTST16-12 (LOW-PRIO)\n\ + \ [same as TST12-12(group), but with pmpcfg(i).A=TOR]" +- 002_fetch_L0_X1_addr_miss: !Subfeature + name: 002_fetch_L0_X1_addr_miss + tag: VP_PMP_F016_S013 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S013_I000 + description: 'reuse of VP_PMP_F012_S013_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S013_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=TOR]\nTST16-13 (LOW-PRIO)\n\ + \ [same as TST12-13(group), but with pmpcfg(i).A=TOR]" +- 003_fetch_L1_X1_addr_hit: !Subfeature + name: 003_fetch_L1_X1_addr_hit + tag: VP_PMP_F016_S014 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S014_I000 + description: 'reuse of VP_PMP_F012_S014_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=TOR]\nTST16-14 (HIGH-PRIO)\n\ + \ [same as TST12-14(group), but with pmpcfg(i).A=TOR]" +- 004_fetch_L1_X0_addr_hit: !Subfeature + name: 004_fetch_L1_X0_addr_hit + tag: VP_PMP_F016_S015 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S015_I000 + description: 'reuse of VP_PMP_F012_S015_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S015_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-b\n[Attempting to fetch an instruction from + a PMP region that does not have execute permissions raises an instruction + access-fault exception]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=TOR]\nTST16-15 (MEDIUM-PRIO)\n\ + \ [same as TST12-15(group), but with pmpcfg(i).A=TOR]" +- 005_fetch_L1_X1_addr_miss: !Subfeature + name: 005_fetch_L1_X1_addr_miss + tag: VP_PMP_F016_S016 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S016_I000 + description: 'reuse of VP_PMP_F012_S016_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S016_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=TOR]\nTST16-16 (HIGH-PRIO)\n\ + \ [same as TST12-16(group), but with pmpcfg(i).A=TOR]" +- 006_load_L0_R1_addr_hit: !Subfeature + name: 006_load_L0_R1_addr_hit + tag: VP_PMP_F016_S021 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S021_I000 + description: 'reuse of VP_PMP_F012_S021_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=TOR]\nTST16-21 (LOW-PRIO)\n\ + \ [same as TST12-21(group), but with pmpcfg(i).A=TOR]" +- 007_load_L0_R0_addr_hit: !Subfeature + name: 007_load_L0_R0_addr_hit + tag: VP_PMP_F016_S022 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S022_I000 + description: 'reuse of VP_PMP_F012_S022_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S022_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=TOR]\nTST16-22 (LOW-PRIO)\n\ + \ [same as TST12-22(group), but with pmpcfg(i).A=TOR]" +- 008_load_L0_R1_addr_miss: !Subfeature + name: 008_load_L0_R1_addr_miss + tag: VP_PMP_F016_S023 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S023_I000 + description: 'reuse of VP_PMP_F012_S023_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S023_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=TOR]\nTST16-23 (LOW-PRIO)\n\ + \ [same as TST12-23(group), but with pmpcfg(i).A=TOR]" +- 009_load_L1_R1_addr_hit: !Subfeature + name: 009_load_L1_R1_addr_hit + tag: VP_PMP_F016_S024 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S024_I000 + description: 'reuse of VP_PMP_F012_S024_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=TOR]\nTST16-24 (HIGH-PRIO)\n\ + \ [same as TST12-24(group), but with pmpcfg(i).A=TOR]" +- 010_load_L1_R0_addr_hit: !Subfeature + name: 010_load_L1_R0_addr_hit + tag: VP_PMP_F016_S025 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S025_I000 + description: 'reuse of VP_PMP_F012_S025_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S025_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved + instruction which accesses a physical address within a PMP region without + read permissions raises a load access-fault exception]\n\nFTR02-b1\n[the + lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean + programmed first)]\n \n\nTST16-2x(group)\n [same as TST12-2x(group), but + with pmpcfg(i).A=TOR]\n TST16-25 (MEDIUM-PRIO)\n [same as TST12-25(group), + but with pmpcfg(i).A=TOR]" +- 011_load_L1_R1_addr_miss: !Subfeature + name: 011_load_L1_R1_addr_miss + tag: VP_PMP_F016_S026 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S026_I000 + description: 'reuse of VP_PMP_F012_S026_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S026_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=TOR]\nTST16-26 (HIGH-PRIO)\n\ + \ [same as TST12-26(group), but with pmpcfg(i).A=TOR]" +- 012_store_L0_W1_addr_hit: !Subfeature + name: 012_store_L0_W1_addr_hit + tag: VP_PMP_F016_S031 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S031_I000 + description: 'reuse of VP_PMP_F012_S031_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=TOR]\nTST16-31 (LOW-PRIO)\n\ + \ [same as TST12-31(group), but with pmpcfg(i).A=TOR]" +- 013_store_L0_W0_addr_hit: !Subfeature + name: 013_store_L0_W0_addr_hit + tag: VP_PMP_F016_S032 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S032_I000 + description: 'reuse of VP_PMP_F012_S032_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S032_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=TOR]\nTST16-32 (LOW-PRIO)\n\ + \ [same as TST12-32(group), but with pmpcfg(i).A=TOR]" +- 014_store_L0_W1_addr_miss: !Subfeature + name: 014_store_L0_W1_addr_miss + tag: VP_PMP_F016_S033 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S033_I000 + description: 'reuse of VP_PMP_F012_S033_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S033_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=TOR]\nTST16-33 (LOW-PRIO)\n\ + \ [same as TST12-33(group), but with pmpcfg(i).A=TOR]" +- 015_store_L1_W1_addr_hit: !Subfeature + name: 015_store_L1_W1_addr_hit + tag: VP_PMP_F016_S034 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S034_I000 + description: 'reuse of VP_PMP_F012_S034_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=TOR]\nTST16-34 (HIGH-PRIO)\n\ + \ [same as TST12-34(group), but with pmpcfg(i).A=TOR]" +- 016_store_L1_W0_addr_hit: !Subfeature + name: 016_store_L1_W0_addr_hit + tag: VP_PMP_F016_S035 + next_elt_id: 1 + display_order: 16 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S035_I000 + description: 'reuse of VP_PMP_F012_S035_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S035_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, + or AMO instruction which accesses a physical address within a PMP region + without write permissions raises a store access-fault exception]\n\nFTR02-b1\n + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does + it mean programmed first)]\n\n\nTST16-3x(group)\n [same as TST12-3x(group), + but with pmpcfg(i).A=TOR]\nTST16-35 (MEDIUM-PRIO)\n [same as TST12-35(group), + but with pmpcfg(i).A=TOR]" +- 017_store_L1_W1_addr_miss: !Subfeature + name: 017_store_L1_W1_addr_miss + tag: VP_PMP_F016_S036 + next_elt_id: 1 + display_order: 17 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S036_I000 + description: 'reuse of VP_PMP_F012_S036_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S036_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=TOR]\nTST16-36 (HIGH-PRIO)\n\ + \ [same as TST12-36(group), but with pmpcfg(i).A=TOR]" +- 018_load_MPP_L0_R1_addr_hit: !Subfeature + name: 018_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F016_S041 + next_elt_id: 1 + display_order: 18 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S041_I000 + description: 'reuse of VP_PMP_F012_S041_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S041_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=TOR]\nTST16-41 (LOWEST-PRIO)\n\ + \ [same as TST12-41(group), but with pmpcfg(i).A=TOR]" +- 019_load_MPP_L0_R0_addr_hit: !Subfeature + name: 019_load_MPP_L0_R0_addr_hit + tag: VP_PMP_F016_S042 + next_elt_id: 1 + display_order: 19 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S042_I000 + description: 'reuse of VP_PMP_F012_S042_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S042_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=TOR]\nTST16-42 (LOWEST-PRIO)\n\ + \ [same as TST12-42(group), but with pmpcfg(i).A=TOR]" +- 020_load_MPP_L0_R1_addr_miss: !Subfeature + name: 020_load_MPP_L0_R1_addr_miss + tag: VP_PMP_F016_S043 + next_elt_id: 1 + display_order: 20 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S043_I000 + description: 'reuse of VP_PMP_F012_S043_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S043_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=TOR]\nTST16-43 (LOWEST-PRIO)\n\ + \ [same as TST12-43(group), but with pmpcfg(i).A=TOR]" +- 021_load_MPP_L1_R1_addr_hit: !Subfeature + name: 021_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F016_S044 + next_elt_id: 1 + display_order: 21 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S044_I000 + description: 'reuse of VP_PMP_F012_S044_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S044_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=TOR]\nTST16-44 (LOWEST-PRIO)\n\ + \ [same as TST12-44(group), but with pmpcfg(i).A=TOR]" +- 022_load_MPP_L1_R0_addr_hit: !Subfeature + name: 022_load_MPP_L1_R0_addr_hit + tag: VP_PMP_F016_S045 + next_elt_id: 1 + display_order: 22 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S045_I000 + description: 'reuse of VP_PMP_F012_S045_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S045_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved + instruction which accesses a physical address within a PMP region without + read permissions raises a load access-fault exception]\n\nFTR02-b1\n[the + lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean + programmed first)]\n \n\nTST16-4x(group)\n [same as TST12-4x(group), but + with pmpcfg(i).A=TOR]\n TST16-45 (LOWEST-PRIO)\n [same as TST12-45(group), + but with pmpcfg(i).A=TOR]" +- 023_load_MPP_L1_R1_addr_miss: !Subfeature + name: 023_load_MPP_L1_R1_addr_miss + tag: VP_PMP_F016_S046 + next_elt_id: 1 + display_order: 23 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S046_I000 + description: 'reuse of VP_PMP_F012_S046_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S046_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=TOR]\nTST16-46 (LOWEST-PRIO)\n\ + \ [same as TST12-46(group), but with pmpcfg(i).A=TOR]" +- 024_store_MPP_L0_W1_addr_hit: !Subfeature + name: 024_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F016_S051 + next_elt_id: 1 + display_order: 24 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S051_I000 + description: 'reuse of VP_PMP_F012_S051_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S051_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=TOR]\nTST16-51 (LOWEST-PRIO)\n\ + \ [same as TST12-51(group), but with pmpcfg(i).A=TOR]" +- 025_store_MPP_L0_W0_addr_hit: !Subfeature + name: 025_store_MPP_L0_W0_addr_hit + tag: VP_PMP_F016_S052 + next_elt_id: 1 + display_order: 25 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S052_I000 + description: 'reuse of VP_PMP_F012_S052_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S052_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=TOR]\nTST16-52 (LOWEST-PRIO)\n\ + \ [same as TST12-52(group), but with pmpcfg(i).A=TOR]" +- 026_store_MPP_L0_W1_addr_miss: !Subfeature + name: 026_store_MPP_L0_W1_addr_miss + tag: VP_PMP_F016_S053 + next_elt_id: 1 + display_order: 26 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S053_I000 + description: 'reuse of VP_PMP_F012_S053_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S053_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=TOR]\nTST16-53 (LOWEST-PRIO)\n\ + \ [same as TST12-53(group), but with pmpcfg(i).A=TOR]" +- 027_store_MPP_L1_W1_addr_hit: !Subfeature + name: 027_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F016_S054 + next_elt_id: 1 + display_order: 27 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S054_I000 + description: 'reuse of VP_PMP_F012_S054_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S054_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=TOR]\nTST16-54 (LOWEST-PRIO)\n\ + \ [same as TST12-54(group), but with pmpcfg(i).A=TOR]" +- 028_store_MPP_L1_W0_addr_hit: !Subfeature + name: 028_store_MPP_L1_W0_addr_hit + tag: VP_PMP_F016_S055 + next_elt_id: 1 + display_order: 28 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S055_I000 + description: 'reuse of VP_PMP_F012_S055_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S055_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, + or AMO instruction which accesses a physical address within a PMP region + without write permissions raises a store access-fault exception]\n\nFTR02-b1\n + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does + it mean programmed first)]\n\n\nTST16-5x(group)\n [same as TST12-5x(group), + but with pmpcfg(i).A=TOR]\nTST16-55 (LOWEST-PRIO)\n [same as TST12-55(group), + but with pmpcfg(i).A=TOR]" +- 029_store_MPP_L1_W1_addr_miss: !Subfeature + name: 029_store_MPP_L1_W1_addr_miss + tag: VP_PMP_F016_S056 + next_elt_id: 1 + display_order: 29 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S056_I000 + description: 'reuse of VP_PMP_F012_S056_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S056_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range\n - [for i=0] pmpaddr(0) + > 0: any TOR address range\n - [for j=unused] pmpaddr(j)=random: only + in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=TOR]\nTST16-56 (LOWEST-PRIO)\n\ + \ [same as TST12-56(group), but with pmpcfg(i).A=TOR]" +- 030_fetch_L0_X1_addr_forbidden: !Subfeature + name: 030_fetch_L0_X1_addr_forbidden + tag: VP_PMP_F016_S061 + next_elt_id: 1 + display_order: 30 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S061_I000 + description: "reuse of VP_PMP_F012_S011_I000 feature description (Cf. Feature: + \"cfg NA4 access M\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for i=0] + pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=TOR]\n TST16-11 (LOW-PRIO)\n\ + \ [same as TST12-11(group), but with pmpcfg(i).A=TOR]\n \n\n//TO COMPLETE + => FTR06-b\nTST25 = same as TST15+TST16 (groups) with PMP entry (0) with + pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) with PMP entry (0) + with pmpaddr(0) = 0\n [create scenario where PMP entry pmpcfg(0) with TOR:\n\ + \ - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO COMPLETE => FTR06-c\n + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) + and pmpcfg(i-1) correct\n [create scenario where PMP entry pmpcfg(i) with + TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct]\n\ + \ [create scenario where PMP entry pmpcfg(0) with TOR:\n - pmpaddr(0) + >= pmpaddr(1/2/3/…)]" +- 031_fetch_L1_X1_addr_forbidden: !Subfeature + name: 031_fetch_L1_X1_addr_forbidden + tag: VP_PMP_F016_S062 + next_elt_id: 1 + display_order: 31 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S062_I000 + description: "reuse of VP_PMP_F012_S014_I000 feature description (Cf. Feature: + \"cfg NA4 access M\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for i=0] + pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=TOR]\nTST16-14 (LOW-PRIO)\n\ + \ [same as TST12-14(group), but with pmpcfg(i).A=TOR]\n\n\n//TO COMPLETE + => FTR06-b\n TST25 = same as TST15+TST16 (groups) with PMP entry (0) with + pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) with PMP entry (0) + with pmpaddr(0) = 0\n [create scenario where PMP entry pmpcfg(0) with TOR:\n\ + \ - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO COMPLETE => FTR06-c\n + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) + and pmpcfg(i-1) correct\n [create scenario where PMP entry pmpcfg(i) with + TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct]\n\ + \ [create scenario where PMP entry pmpcfg(0) with TOR:\n - pmpaddr(0) + >= pmpaddr(1/2/3/…)]" +- 032_load_L0_R1_addr_forbidden: !Subfeature + name: 032_load_L0_R1_addr_forbidden + tag: VP_PMP_F016_S063 + next_elt_id: 1 + display_order: 32 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S063_I000 + description: "reuse of VP_PMP_F012_S021_I000 feature description (Cf. Feature: + \"cfg NA4 access M\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for i=0] + pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=TOR]\n TST16-21 (HIGH-PRIO)\n\ + \ [same as TST12-21(group), but with pmpcfg(i).A=TOR]\n \n\n//TO COMPLETE + => FTR06-b\nTST25 = same as TST15+TST16 (groups) with PMP entry (0) with + pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) with PMP entry (0) + with pmpaddr(0) = 0\n [create scenario where PMP entry pmpcfg(0) with TOR:\n\ + \ - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO COMPLETE => FTR06-c\n + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) + and pmpcfg(i-1) correct\n [create scenario where PMP entry pmpcfg(i) with + TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct]\n\ + \ [create scenario where PMP entry pmpcfg(0) with TOR:\n - pmpaddr(0) + >= pmpaddr(1/2/3/…)]" +- 033_load_L1_R1_addr_forbidden: !Subfeature + name: 033_load_L1_R1_addr_forbidden + tag: VP_PMP_F016_S064 + next_elt_id: 1 + display_order: 33 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S064_I000 + description: "reuse of VP_PMP_F012_S024_I000 feature description (Cf. Feature: + \"cfg NA4 access M\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for i=0] + pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=TOR]\nTST16-24 (LOW-PRIO)\n\ + \ [same as TST12-24(group), but with pmpcfg(i).A=TOR]\n\n\n//TO COMPLETE + => FTR06-b\n TST25 = same as TST15+TST16 (groups) with PMP entry (0) with + pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) with PMP entry (0) + with pmpaddr(0) = 0\n [create scenario where PMP entry pmpcfg(0) with TOR:\n\ + \ - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO COMPLETE => FTR06-c\n + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) + and pmpcfg(i-1) correct\n [create scenario where PMP entry pmpcfg(i) with + TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct]\n\ + \ [create scenario where PMP entry pmpcfg(0) with TOR:\n - pmpaddr(0) + >= pmpaddr(1/2/3/…)]" +- 034_store_L0_W1_addr_forbidden: !Subfeature + name: 034_store_L0_W1_addr_forbidden + tag: VP_PMP_F016_S065 + next_elt_id: 1 + display_order: 34 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S065_I000 + description: "reuse of VP_PMP_F012_S031_I000 feature description (Cf. Feature: + \"cfg NA4 access M\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for i=0] + pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST16-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=TOR]\n TST16-31 (HIGH-PRIO)\n\ + \ [same as TST12-31(group), but with pmpcfg(i).A=TOR]\n \n\n//TO COMPLETE + => FTR06-b\nTST25 = same as TST15+TST16 (groups) with PMP entry (0) with + pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) with PMP entry (0) + with pmpaddr(0) = 0\n [create scenario where PMP entry pmpcfg(0) with TOR:\n\ + \ - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO COMPLETE => FTR06-c\n + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) + and pmpcfg(i-1) correct\n [create scenario where PMP entry pmpcfg(i) with + TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct]\n\ + \ [create scenario where PMP entry pmpcfg(0) with TOR:\n - pmpaddr(0) + >= pmpaddr(1/2/3/…)]" +- 035_store_L1_W1_addr_forbidden: !Subfeature + name: 035_store_L1_W1_addr_forbidden + tag: VP_PMP_F016_S066 + next_elt_id: 1 + display_order: 35 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F016_S066_I000 + description: "reuse of VP_PMP_F012_S034_I000 feature description (Cf. Feature: + \"cfg NA4 access M\")\n\n{Page 59 Volume II: RISC-V Privileged Architectures + V20211203}\nIf pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i + matches no addresses\nIf PMP entry 0’s A field is set to TOR, zero is used + for the lower bound, and so it matches any address y < pmpaddr(0)" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=TOR\n - [for + i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range\n - [for i=0] + pmpaddr(0) = 0: invalid TOR address range\n - [for j=unused] pmpaddr(j)=random: + only in single entry configuration case (not in reuse case)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST16-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=TOR]\nTST16-34 (LOW-PRIO)\n\ + \ [same as TST12-34(group), but with pmpcfg(i).A=TOR]\n\n\n//TO COMPLETE + => FTR06-b\n TST25 = same as TST15+TST16 (groups) with PMP entry (0) with + pmpaddr(0) > 0\nTST26 = same as TST15+TST16 (groups) with PMP entry (0) + with pmpaddr(0) = 0\n [create scenario where PMP entry pmpcfg(0) with TOR:\n\ + \ - pmpaddr(0) > 0\n - pmpaddr(0) = 0]\n\n//TO COMPLETE => FTR06-c\n + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) + and pmpcfg(i-1) correct\n [create scenario where PMP entry pmpcfg(i) with + TOR:\n - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct]\n\ + \ [create scenario where PMP entry pmpcfg(0) with TOR:\n - pmpaddr(0) + >= pmpaddr(1/2/3/…)]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP017.yml b/verif/docs/VerifPlans/PMP/VP_IP017.yml new file mode 100644 index 00000000000..3a3989a734b --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP017.yml @@ -0,0 +1,1153 @@ +!Feature +next_elt_id: 30 +name: cfg OFF access S/U +id: 17 +display_order: 17 +subfeatures: !!omap +- 000_fetch_L0_X1_addr_hit: !Subfeature + name: 000_fetch_L0_X1_addr_hit + tag: VP_PMP_F017_S011 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S011_I000 + description: 'reuse of VP_PMP_F011_S011_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check instruction fetch + access-fault exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=OFF]\n + TST17-11 (HIGH-PRIO)\n [same as TST11-11(group), but with pmpcfg(i).A=OFF\n\ + \ - check instruction fetch access-fault exception raised]" +- 001_fetch_L0_X0_addr_hit: !Subfeature + name: 001_fetch_L0_X0_addr_hit + tag: VP_PMP_F017_S012 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S012_I000 + description: 'reuse of VP_PMP_F011_S012_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S012_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-b\n [Attempting to fetch an instruction from a PMP region + that does not have execute permissions raises an instruction access-fault + exception]\n \n\nTST17-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=OFF]\n + TST17-12 (MEDIUM-PRIO)\n [same as TST11-12(group), but with pmpcfg(i).A=OFF]" +- 002_fetch_L0_X1_addr_miss: !Subfeature + name: 002_fetch_L0_X1_addr_miss + tag: VP_PMP_F017_S013 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S013_I000 + description: 'reuse of VP_PMP_F011_S013_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S013_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=OFF]\n + TST17-13 (MEDIUM-PRIO)\n [same as TST11-13(group), but with pmpcfg(i).A=OFF]" +- 003_fetch_L1_X1_addr_hit: !Subfeature + name: 003_fetch_L1_X1_addr_hit + tag: VP_PMP_F017_S014 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S014_I000 + description: 'reuse of VP_PMP_F011_S014_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check instruction fetch + access-fault exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=OFF]\n + TST17-14 (LOW-PRIO)\n [same as TST11-14(group), but with pmpcfg(i).A=OFF\n\ + \ - check instruction fetch access-fault exception raised]" +- 004_fetch_L1_X0_addr_hit: !Subfeature + name: 004_fetch_L1_X0_addr_hit + tag: VP_PMP_F017_S015 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S015_I000 + description: 'reuse of VP_PMP_F011_S015_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S015_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-b\n[Attempting to fetch an instruction from a PMP region that + does not have execute permissions raises an instruction access-fault exception]\n\ + \n\nTST17-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=OFF]\n + TST17-15 (LOW-PRIO)\n [same as TST11-15(group), but with pmpcfg(i).A=OFF]" +- 005_fetch_L1_X1_addr_miss: !Subfeature + name: 005_fetch_L1_X1_addr_miss + tag: VP_PMP_F017_S016 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S016_I000 + description: 'reuse of VP_PMP_F011_S016_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S016_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-1x(group)\n [same as TST11-1x(group), but with pmpcfg(i).A=OFF]\n + TST17-16 (LOW-PRIO)\n [same as TST11-16(group), but with pmpcfg(i).A=OFF]" +- 006_load_L0_R1_addr_hit: !Subfeature + name: 006_load_L0_R1_addr_hit + tag: VP_PMP_F017_S021 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S021_I000 + description: 'reuse of VP_PMP_F011_S021_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check load access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=OFF]\n + TST17-21 (HIGH-PRIO)\n [same as TST11-21(group), but with pmpcfg(i).A=OFF\n\ + \ - check load access-fault exception raised]" +- 007_load_L0_R0_addr_hit: !Subfeature + name: 007_load_L0_R0_addr_hit + tag: VP_PMP_F017_S022 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S022_I000 + description: 'reuse of VP_PMP_F011_S022_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S022_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n [Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST17-2x(group)\n [same as TST11-2x(group), + but with pmpcfg(i).A=OFF]\nTST17-22 (MEDIUM-PRIO)\n [same as TST11-22(group), + but with pmpcfg(i).A=OFF]" +- 008_load_L0_R1_addr_miss: !Subfeature + name: 008_load_L0_R1_addr_miss + tag: VP_PMP_F017_S023 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S023_I000 + description: 'reuse of VP_PMP_F011_S023_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S023_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=OFF]\n + TST17-23 (MEDIUM-PRIO)\n [same as TST11-23(group), but with pmpcfg(i).A=OFF]" +- 009_load_L1_R1_addr_hit: !Subfeature + name: 009_load_L1_R1_addr_hit + tag: VP_PMP_F017_S024 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S024_I000 + description: 'reuse of VP_PMP_F011_S024_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check load access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=OFF]\n + TST17-24 (LOW-PRIO)\n [same as TST11-24(group), but with pmpcfg(i).A=OFF\n\ + \ - check load access-fault exception raised]" +- 010_load_L1_R0_addr_hit: !Subfeature + name: 010_load_L1_R0_addr_hit + tag: VP_PMP_F017_S025 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S025_I000 + description: 'reuse of VP_PMP_F011_S025_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S025_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST17-2x(group)\n [same as TST11-2x(group), + but with pmpcfg(i).A=OFF]\n TST17-25 (LOW-PRIO)\n [same as TST11-25(group), + but with pmpcfg(i).A=OFF]" +- 011_load_L1_R1_addr_miss: !Subfeature + name: 011_load_L1_R1_addr_miss + tag: VP_PMP_F017_S026 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S026_I000 + description: 'reuse of VP_PMP_F011_S026_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S026_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-2x(group)\n [same as TST11-2x(group), but with pmpcfg(i).A=OFF]\n + TST17-26 (LOW-PRIO)\n [same as TST11-26(group), but with pmpcfg(i).A=OFF]" +- 012_store_L0_W1_addr_hit: !Subfeature + name: 012_store_L0_W1_addr_hit + tag: VP_PMP_F017_S031 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S031_I000 + description: 'reuse of VP_PMP_F011_S031_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check store access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=OFF]\n + TST17-31 (HIGH-PRIO)\n [same as TST11-31(group), but with pmpcfg(i).A=OFF\n\ + \ - check store access-fault exception raised]" +- 013_store_L0_W0_addr_hit: !Subfeature + name: 013_store_L0_W0_addr_hit + tag: VP_PMP_F017_S032 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S032_I000 + description: 'reuse of VP_PMP_F011_S032_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S032_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n [Attempting to execute a store, store-conditional, or + AMO instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST17-3x(group)\n\ + \ [same as TST11-3x(group), but with pmpcfg(i).A=OFF]\nTST17-32 (MEDIUM-PRIO)\n\ + \ [same as TST11-32(group), but with pmpcfg(i).A=OFF]" +- 014_store_L0_W1_addr_miss: !Subfeature + name: 014_store_L0_W1_addr_miss + tag: VP_PMP_F017_S033 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S033_I000 + description: 'reuse of VP_PMP_F011_S033_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S033_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=OFF]\n + TST17-33 (MEDIUM-PRIO)\n [same as TST11-33(group), but with pmpcfg(i).A=OFF]" +- 015_store_L1_W1_addr_hit: !Subfeature + name: 015_store_L1_W1_addr_hit + tag: VP_PMP_F017_S034 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S034_I000 + description: 'reuse of VP_PMP_F011_S034_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check store access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=OFF]\n + TST17-34 (LOW-PRIO)\n [same as TST11-34(group), but with pmpcfg(i).A=OFF\n\ + \ - check store access-fault exception raised]" +- 016_store_L1_W0_addr_hit: !Subfeature + name: 016_store_L1_W0_addr_hit + tag: VP_PMP_F017_S035 + next_elt_id: 1 + display_order: 16 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S035_I000 + description: 'reuse of VP_PMP_F011_S035_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S035_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, or AMO + instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST17-3x(group)\n\ + \ [same as TST11-3x(group), but with pmpcfg(i).A=OFF]\nTST17-35 (LOW-PRIO)\n\ + \ [same as TST11-35(group), but with pmpcfg(i).A=OFF]" +- 017_store_L1_W1_addr_miss: !Subfeature + name: 017_store_L1_W1_addr_miss + tag: VP_PMP_F017_S036 + next_elt_id: 1 + display_order: 17 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S036_I000 + description: 'reuse of VP_PMP_F011_S036_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S036_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-3x(group)\n [same as TST11-3x(group), but with pmpcfg(i).A=OFF]\n + TST17-36 (LOW-PRIO)\n [same as TST11-36(group), but with pmpcfg(i).A=OFF]" +- 018_load_MPP_L0_R1_addr_hit: !Subfeature + name: 018_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F017_S041 + next_elt_id: 1 + display_order: 18 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S041_I000 + description: 'reuse of VP_PMP_F011_S041_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S041_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check load access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=OFF]\n + TST17-41 (LOWEST-PRIO)\n [same as TST11-41(group), but with pmpcfg(i).A=OFF\n\ + \ - check load access-fault exception raised]" +- 019_load_MPP_L0_R0_addr_hit: !Subfeature + name: 019_load_MPP_L0_R0_addr_hit + tag: VP_PMP_F017_S042 + next_elt_id: 1 + display_order: 19 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S042_I000 + description: 'reuse of VP_PMP_F011_S042_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S042_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n [Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST17-4x(group)\n [same as TST11-4x(group), + but with pmpcfg(i).A=OFF]\nTST17-42 (LOWEST-PRIO)\n [same as TST11-42(group), + but with pmpcfg(i).A=OFF]" +- 020_load_MPP_L0_R1_addr_miss: !Subfeature + name: 020_load_MPP_L0_R1_addr_miss + tag: VP_PMP_F017_S043 + next_elt_id: 1 + display_order: 20 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S043_I000 + description: 'reuse of VP_PMP_F011_S043_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S043_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=OFF]\n + TST17-43 (LOWEST-PRIO)\n [same as TST11-43(group), but with pmpcfg(i).A=OFF]" +- 021_load_MPP_L1_R1_addr_hit: !Subfeature + name: 021_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F017_S044 + next_elt_id: 1 + display_order: 21 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S044_I000 + description: 'reuse of VP_PMP_F011_S044_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S044_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check load access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=OFF]\n + TST17-44 (LOWEST-PRIO)\n [same as TST11-44(group), but with pmpcfg(i).A=OFF\n\ + \ - check load access-fault exception raised]" +- 022_load_MPP_L1_R0_addr_hit: !Subfeature + name: 022_load_MPP_L1_R0_addr_hit + tag: VP_PMP_F017_S045 + next_elt_id: 1 + display_order: 22 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S045_I000 + description: 'reuse of VP_PMP_F011_S045_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S045_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved instruction + which accesses a physical address within a PMP region without read permissions + raises a load access-fault exception]\n\n\nTST17-4x(group)\n [same as TST11-4x(group), + but with pmpcfg(i).A=OFF]\n TST17-45 (LOWEST-PRIO)\n [same as TST11-45(group), + but with pmpcfg(i).A=OFF]" +- 023_load_MPP_L1_R1_addr_miss: !Subfeature + name: 023_load_MPP_L1_R1_addr_miss + tag: VP_PMP_F017_S046 + next_elt_id: 1 + display_order: 23 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S046_I000 + description: 'reuse of VP_PMP_F011_S046_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S046_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-4x(group)\n [same as TST11-4x(group), but with pmpcfg(i).A=OFF]\n + TST17-46 (LOWEST-PRIO)\n [same as TST11-46(group), but with pmpcfg(i).A=OFF]" +- 024_store_MPP_L0_W1_addr_hit: !Subfeature + name: 024_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F017_S051 + next_elt_id: 1 + display_order: 24 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S051_I000 + description: 'reuse of VP_PMP_F011_S051_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S051_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check store access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=OFF]\n + TST17-51 (LOWEST-PRIO)\n [same as TST11-51(group), but with pmpcfg(i).A=OFF\n\ + \ - check store access-fault exception raised]" +- 025_store_MPP_L0_W0_addr_hit: !Subfeature + name: 025_store_MPP_L0_W0_addr_hit + tag: VP_PMP_F017_S052 + next_elt_id: 1 + display_order: 25 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S052_I000 + description: 'reuse of VP_PMP_F011_S052_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S052_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n [Attempting to execute a store, store-conditional, or + AMO instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST17-5x(group)\n\ + \ [same as TST11-5x(group), but with pmpcfg(i).A=OFF]\nTST17-52 (LOWEST-PRIO)\n\ + \ [same as TST11-52(group), but with pmpcfg(i).A=OFF]" +- 026_store_MPP_L0_W1_addr_miss: !Subfeature + name: 026_store_MPP_L0_W1_addr_miss + tag: VP_PMP_F017_S053 + next_elt_id: 1 + display_order: 26 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S053_I000 + description: 'reuse of VP_PMP_F011_S053_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S053_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e2-2 (refers to FTR09-d2-2)\n[When the L bit is clear, the R/W/X + permissions apply only to S and U modes]\nFTR09-d2-2 (L=0 refers to FTR08-e2-2)\n + [if the privilege mode of the access is S or U (whatever L), then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=OFF]\n + TST17-53 (LOWEST-PRIO)\n [same as TST11-53(group), but with pmpcfg(i).A=OFF]" +- 027_store_MPP_L1_W1_addr_hit: !Subfeature + name: 027_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F017_S054 + next_elt_id: 1 + display_order: 27 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S054_I000 + description: 'reuse of VP_PMP_F011_S054_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S054_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range\n\nCHECK UPDATE\n - check store access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=OFF]\n + TST17-54 (LOWEST-PRIO)\n [same as TST11-54(group), but with pmpcfg(i).A=OFF\n\ + \ - check store access-fault exception raised]" +- 028_store_MPP_L1_W0_addr_hit: !Subfeature + name: 028_store_MPP_L1_W0_addr_hit + tag: VP_PMP_F017_S055 + next_elt_id: 1 + display_order: 28 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S055_I000 + description: 'reuse of VP_PMP_F011_S055_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S055_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, or AMO + instruction which accesses a physical address within a PMP region without + write permissions raises a store access-fault exception]\n\n\nTST17-5x(group)\n\ + \ [same as TST11-5x(group), but with pmpcfg(i).A=OFF]\nTST17-55 (LOWEST-PRIO)\n\ + \ [same as TST11-55(group), but with pmpcfg(i).A=OFF]" +- 029_store_MPP_L1_W1_addr_miss: !Subfeature + name: 029_store_MPP_L1_W1_addr_miss + tag: VP_PMP_F017_S056 + next_elt_id: 1 + display_order: 29 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F017_S056_I000 + description: 'reuse of VP_PMP_F011_S056_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F011_S056_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - + pmpaddr(i): NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-d\n[PMP checks are applied to all accesses whose + effective privilege mode is S or U]\n\nFTR02-b1\n[the lowest-numbered PMP + CSRs must be implemented first (QUESTION: does it mean programmed first)]\n + \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n [When the L bit + is set, these permissions are enforced for all privilege modes]\nFTR01-f + (refers to FTR08-e1)\n [PMP checks may additionally apply to M-mode accesses, + in which case the PMP registers themselves are locked, so that even M-mode + software cannot change them until the hart is reset]\n FTR09-d2-1 (refers + to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, then the access + succeeds only if the R, W, or X bit corresponding to the access type is + set]\n\n\nTST17-5x(group)\n [same as TST11-5x(group), but with pmpcfg(i).A=OFF]\n + TST17-56 (LOWEST-PRIO)\n [same as TST11-56(group), but with pmpcfg(i).A=OFF]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP018.yml b/verif/docs/VerifPlans/PMP/VP_IP018.yml new file mode 100644 index 00000000000..f0183d4188b --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP018.yml @@ -0,0 +1,1129 @@ +!Feature +next_elt_id: 30 +name: cfg OFF access M +id: 18 +display_order: 18 +subfeatures: !!omap +- 000_fetch_L0_X1_addr_hit: !Subfeature + name: 000_fetch_L0_X1_addr_hit + tag: VP_PMP_F018_S011 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S011_I000 + description: 'reuse of VP_PMP_F012_S011_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=OFF]\nTST18-11 (LOW-PRIO)\n\ + \ [same as TST12-11(group), but with pmpcfg(i).A=OFF]" +- 001_fetch_L0_X0_addr_hit: !Subfeature + name: 001_fetch_L0_X0_addr_hit + tag: VP_PMP_F018_S012 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S012_I000 + description: 'reuse of VP_PMP_F012_S012_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S012_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=OFF]\nTST18-12 (LOW-PRIO)\n\ + \ [same as TST12-12(group), but with pmpcfg(i).A=OFF]" +- 002_fetch_L0_X1_addr_miss: !Subfeature + name: 002_fetch_L0_X1_addr_miss + tag: VP_PMP_F018_S013 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S013_I000 + description: 'reuse of VP_PMP_F012_S013_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S013_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=OFF]\nTST18-13 (LOW-PRIO)\n\ + \ [same as TST12-13(group), but with pmpcfg(i).A=OFF]" +- 003_fetch_L1_X1_addr_hit: !Subfeature + name: 003_fetch_L1_X1_addr_hit + tag: VP_PMP_F018_S014 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S014_I000 + description: 'reuse of VP_PMP_F012_S014_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=OFF]\nTST18-14 (HIGH-PRIO)\n\ + \ [same as TST12-14(group), but with pmpcfg(i).A=OFF\n - check instruction + fetch access-fault exception raised]" +- 004_fetch_L1_X0_addr_hit: !Subfeature + name: 004_fetch_L1_X0_addr_hit + tag: VP_PMP_F018_S015 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S015_I000 + description: 'reuse of VP_PMP_F012_S015_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S015_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-b\n[Attempting to fetch an instruction from + a PMP region that does not have execute permissions raises an instruction + access-fault exception]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=OFF]\nTST18-15 (MEDIUM-PRIO)\n\ + \ [same as TST12-15(group), but with pmpcfg(i).A=OFF]" +- 005_fetch_L1_X1_addr_miss: !Subfeature + name: 005_fetch_L1_X1_addr_miss + tag: VP_PMP_F018_S016 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S016_I000 + description: 'reuse of VP_PMP_F012_S016_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S016_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-1x(group)\n\ + \ [same as TST12-1x(group), but with pmpcfg(i).A=OFF]\nTST18-16 (HIGH-PRIO)\n\ + \ [same as TST12-16(group), but with pmpcfg(i).A=OFF]" +- 006_load_L0_R1_addr_hit: !Subfeature + name: 006_load_L0_R1_addr_hit + tag: VP_PMP_F018_S021 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S021_I000 + description: 'reuse of VP_PMP_F012_S021_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=OFF]\nTST18-21 (LOW-PRIO)\n\ + \ [same as TST12-21(group), but with pmpcfg(i).A=OFF]" +- 007_load_L0_R0_addr_hit: !Subfeature + name: 007_load_L0_R0_addr_hit + tag: VP_PMP_F018_S022 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S022_I000 + description: 'reuse of VP_PMP_F012_S022_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S022_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=OFF]\nTST18-22 (LOW-PRIO)\n\ + \ [same as TST12-22(group), but with pmpcfg(i).A=OFF]" +- 008_load_L0_R1_addr_miss: !Subfeature + name: 008_load_L0_R1_addr_miss + tag: VP_PMP_F018_S023 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S023_I000 + description: 'reuse of VP_PMP_F012_S023_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S023_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=OFF]\nTST18-23 (LOW-PRIO)\n\ + \ [same as TST12-23(group), but with pmpcfg(i).A=OFF]" +- 009_load_L1_R1_addr_hit: !Subfeature + name: 009_load_L1_R1_addr_hit + tag: VP_PMP_F018_S024 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S024_I000 + description: 'reuse of VP_PMP_F012_S024_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=OFF]\nTST18-24 (HIGH-PRIO)\n\ + \ [same as TST12-24(group), but with pmpcfg(i).A=OFF\n - check instruction + fetch access-fault exception raised]" +- 010_load_L1_R0_addr_hit: !Subfeature + name: 010_load_L1_R0_addr_hit + tag: VP_PMP_F018_S025 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S025_I000 + description: 'reuse of VP_PMP_F012_S025_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S025_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved + instruction which accesses a physical address within a PMP region without + read permissions raises a load access-fault exception]\n\nFTR02-b1\n[the + lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean + programmed first)]\n \n\nTST18-2x(group)\n [same as TST12-2x(group), but + with pmpcfg(i).A=OFF]\n TST18-25 (MEDIUM-PRIO)\n [same as TST12-25(group), + but with pmpcfg(i).A=OFF]" +- 011_load_L1_R1_addr_miss: !Subfeature + name: 011_load_L1_R1_addr_miss + tag: VP_PMP_F018_S026 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S026_I000 + description: 'reuse of VP_PMP_F012_S026_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S026_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-2x(group)\n\ + \ [same as TST12-2x(group), but with pmpcfg(i).A=OFF]\nTST18-26 (HIGH-PRIO)\n\ + \ [same as TST12-26(group), but with pmpcfg(i).A=OFF]" +- 012_store_L0_W1_addr_hit: !Subfeature + name: 012_store_L0_W1_addr_hit + tag: VP_PMP_F018_S031 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S031_I000 + description: 'reuse of VP_PMP_F012_S031_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=OFF]\nTST18-31 (LOW-PRIO)\n\ + \ [same as TST12-31(group), but with pmpcfg(i).A=OFF]" +- 013_store_L0_W0_addr_hit: !Subfeature + name: 013_store_L0_W0_addr_hit + tag: VP_PMP_F018_S032 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S032_I000 + description: 'reuse of VP_PMP_F012_S032_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S032_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=OFF]\nTST18-32 (LOW-PRIO)\n\ + \ [same as TST12-32(group), but with pmpcfg(i).A=OFF]" +- 014_store_L0_W1_addr_miss: !Subfeature + name: 014_store_L0_W1_addr_miss + tag: VP_PMP_F018_S033 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S033_I000 + description: 'reuse of VP_PMP_F012_S033_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S033_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=OFF]\nTST18-33 (LOW-PRIO)\n\ + \ [same as TST12-33(group), but with pmpcfg(i).A=OFF]" +- 015_store_L1_W1_addr_hit: !Subfeature + name: 015_store_L1_W1_addr_hit + tag: VP_PMP_F018_S034 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S034_I000 + description: 'reuse of VP_PMP_F012_S034_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=OFF]\nTST18-34 (HIGH-PRIO)\n\ + \ [same as TST12-34(group), but with pmpcfg(i).A=OFF\n - check instruction + fetch access-fault exception raised]" +- 016_store_L1_W0_addr_hit: !Subfeature + name: 016_store_L1_W0_addr_hit + tag: VP_PMP_F018_S035 + next_elt_id: 1 + display_order: 16 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S035_I000 + description: 'reuse of VP_PMP_F012_S035_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S035_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, + or AMO instruction which accesses a physical address within a PMP region + without write permissions raises a store access-fault exception]\n\nFTR02-b1\n + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does + it mean programmed first)]\n\n\nTST18-3x(group)\n [same as TST12-3x(group), + but with pmpcfg(i).A=OFF]\nTST18-35 (MEDIUM-PRIO)\n [same as TST12-35(group), + but with pmpcfg(i).A=OFF]" +- 017_store_L1_W1_addr_miss: !Subfeature + name: 017_store_L1_W1_addr_miss + tag: VP_PMP_F018_S036 + next_elt_id: 1 + display_order: 17 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S036_I000 + description: 'reuse of VP_PMP_F012_S036_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S036_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-3x(group)\n\ + \ [same as TST12-3x(group), but with pmpcfg(i).A=OFF]\nTST18-36 (HIGH-PRIO)\n\ + \ [same as TST12-36(group), but with pmpcfg(i).A=OFF]" +- 018_load_MPP_L0_R1_addr_hit: !Subfeature + name: 018_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F018_S041 + next_elt_id: 1 + display_order: 18 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S041_I000 + description: 'reuse of VP_PMP_F012_S041_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S041_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=OFF]\nTST18-41 (LOWEST-PRIO)\n\ + \ [same as TST12-41(group), but with pmpcfg(i).A=OFF]" +- 019_load_MPP_L0_R0_addr_hit: !Subfeature + name: 019_load_MPP_L0_R0_addr_hit + tag: VP_PMP_F018_S042 + next_elt_id: 1 + display_order: 19 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S042_I000 + description: 'reuse of VP_PMP_F012_S042_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S042_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=OFF]\nTST18-42 (LOWEST-PRIO)\n\ + \ [same as TST12-42(group), but with pmpcfg(i).A=OFF]" +- 020_load_MPP_L0_R1_addr_miss: !Subfeature + name: 020_load_MPP_L0_R1_addr_miss + tag: VP_PMP_F018_S043 + next_elt_id: 1 + display_order: 20 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S043_I000 + description: 'reuse of VP_PMP_F012_S043_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S043_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=OFF]\nTST18-43 (LOWEST-PRIO)\n\ + \ [same as TST12-43(group), but with pmpcfg(i).A=OFF]" +- 021_load_MPP_L1_R1_addr_hit: !Subfeature + name: 021_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F018_S044 + next_elt_id: 1 + display_order: 21 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S044_I000 + description: 'reuse of VP_PMP_F012_S044_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S044_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=OFF]\nTST18-44 (LOWEST-PRIO)\n\ + \ [same as TST12-44(group), but with pmpcfg(i).A=OFF\n - check instruction + fetch access-fault exception raised]" +- 022_load_MPP_L1_R0_addr_hit: !Subfeature + name: 022_load_MPP_L1_R0_addr_hit + tag: VP_PMP_F018_S045 + next_elt_id: 1 + display_order: 22 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S045_I000 + description: 'reuse of VP_PMP_F012_S045_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S045_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-c\n[Attempting to execute a load or load-reserved + instruction which accesses a physical address within a PMP region without + read permissions raises a load access-fault exception]\n\nFTR02-b1\n[the + lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean + programmed first)]\n \n\nTST18-4x(group)\n [same as TST12-4x(group), but + with pmpcfg(i).A=OFF]\n TST18-45 (LOWEST-PRIO)\n [same as TST12-45(group), + but with pmpcfg(i).A=OFF]" +- 023_load_MPP_L1_R1_addr_miss: !Subfeature + name: 023_load_MPP_L1_R1_addr_miss + tag: VP_PMP_F018_S046 + next_elt_id: 1 + display_order: 23 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S046_I000 + description: 'reuse of VP_PMP_F012_S046_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S046_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-4x(group)\n\ + \ [same as TST12-4x(group), but with pmpcfg(i).A=OFF]\nTST18-46 (LOWEST-PRIO)\n\ + \ [same as TST12-46(group), but with pmpcfg(i).A=OFF]" +- 024_store_MPP_L0_W1_addr_hit: !Subfeature + name: 024_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F018_S051 + next_elt_id: 1 + display_order: 24 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S051_I000 + description: 'reuse of VP_PMP_F012_S051_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S051_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=OFF]\nTST18-51 (LOWEST-PRIO)\n\ + \ [same as TST12-51(group), but with pmpcfg(i).A=OFF]" +- 025_store_MPP_L0_W0_addr_hit: !Subfeature + name: 025_store_MPP_L0_W0_addr_hit + tag: VP_PMP_F018_S052 + next_elt_id: 1 + display_order: 25 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S052_I000 + description: 'reuse of VP_PMP_F012_S052_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S052_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=OFF]\nTST18-52 (LOWEST-PRIO)\n\ + \ [same as TST12-52(group), but with pmpcfg(i).A=OFF]" +- 026_store_MPP_L0_W1_addr_miss: !Subfeature + name: 026_store_MPP_L0_W1_addr_miss + tag: VP_PMP_F018_S053 + next_elt_id: 1 + display_order: 26 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S053_I000 + description: 'reuse of VP_PMP_F012_S053_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S053_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e2-1 (refers to FTR09-d1)\n[When the L bit is clear, any + M-mode access matching the PMP entry will succeed]\nFTR09-d1 (refers to + FTR08-e2-1)\n [If the L bit is clear and the privilege mode of the access + is M, the access succeeds]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must + be implemented first (QUESTION: does it mean programmed first)]\n\n\nTST18-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=OFF]\nTST18-53 (LOWEST-PRIO)\n\ + \ [same as TST12-53(group), but with pmpcfg(i).A=OFF]" +- 027_store_MPP_L1_W1_addr_hit: !Subfeature + name: 027_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F018_S054 + next_elt_id: 1 + display_order: 27 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S054_I000 + description: 'reuse of VP_PMP_F012_S054_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S054_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=OFF]\nTST18-54 (LOWEST-PRIO)\n\ + \ [same as TST12-54(group), but with pmpcfg(i).A=OFF\n - check instruction + fetch access-fault exception raised]" +- 028_store_MPP_L1_W0_addr_hit: !Subfeature + name: 028_store_MPP_L1_W0_addr_hit + tag: VP_PMP_F018_S055 + next_elt_id: 1 + display_order: 28 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S055_I000 + description: 'reuse of VP_PMP_F012_S055_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S055_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR04-d\n[Attempting to execute a store, store-conditional, + or AMO instruction which accesses a physical address within a PMP region + without write permissions raises a store access-fault exception]\n\nFTR02-b1\n + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does + it mean programmed first)]\n\n\nTST18-5x(group)\n [same as TST12-5x(group), + but with pmpcfg(i).A=OFF]\nTST18-55 (LOWEST-PRIO)\n [same as TST12-55(group), + but with pmpcfg(i).A=OFF]" +- 029_store_MPP_L1_W1_addr_miss: !Subfeature + name: 029_store_MPP_L1_W1_addr_miss + tag: VP_PMP_F018_S056 + next_elt_id: 1 + display_order: 29 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F018_S056_I000 + description: 'reuse of VP_PMP_F012_S056_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F012_S056_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - pmpcfg(i): A=OFF\n - pmpaddr(i): + NA4 address range" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nFTR01-f (refers to FTR08-e1)\n[PMP checks may additionally + apply to M-mode accesses, in which case the PMP registers themselves are + locked, so that even M-mode software cannot change them until the hart is + reset]\n \nFTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1)\n[When the + L bit is set, these permissions are enforced for all privilege modes]\n + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f)\n[if the L bit is set, + then the access succeeds only if the R, W, or X bit corresponding to the + access type is set]\n\nFTR02-b1\n[the lowest-numbered PMP CSRs must be implemented + first (QUESTION: does it mean programmed first)]\n\n\nTST18-5x(group)\n\ + \ [same as TST12-5x(group), but with pmpcfg(i).A=OFF]\nTST18-56 (LOWEST-PRIO)\n\ + \ [same as TST12-56(group), but with pmpcfg(i).A=OFF]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP019.yml b/verif/docs/VerifPlans/PMP/VP_IP019.yml new file mode 100644 index 00000000000..76d9a7ad6c3 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP019.yml @@ -0,0 +1,525 @@ +!Feature +next_elt_id: 20 +name: cfg NA4 not selectable +id: 19 +display_order: 19 +subfeatures: !!omap +- 000_fetch_L0_X1_addr_hit: !Subfeature + name: 000_fetch_L0_X1_addr_hit + tag: VP_PMP_F019_S011 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S011_I000 + description: 'reuse of VP_PMP_F019_S011_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check instruction fetch access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 001_fetch_L1_X1_addr_hit: !Subfeature + name: 001_fetch_L1_X1_addr_hit + tag: VP_PMP_F019_S014 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S014_I000 + description: 'reuse of VP_PMP_F019_S014_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check instruction fetch access-fault + exception raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 002_load_L0_R1_addr_hit: !Subfeature + name: 002_load_L0_R1_addr_hit + tag: VP_PMP_F019_S021 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S021_I000 + description: 'reuse of VP_PMP_F019_S021_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check load access-fault exception + raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 003_load_L1_R1_addr_hit: !Subfeature + name: 003_load_L1_R1_addr_hit + tag: VP_PMP_F019_S024 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S024_I000 + description: 'reuse of VP_PMP_F019_S024_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check load access-fault exception + raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 004_store_L0_W1_addr_hit: !Subfeature + name: 004_store_L0_W1_addr_hit + tag: VP_PMP_F019_S031 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S031_I000 + description: 'reuse of VP_PMP_F019_S031_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check store access-fault exception + raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 005_store_L1_W1_addr_hit: !Subfeature + name: 005_store_L1_W1_addr_hit + tag: VP_PMP_F019_S034 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S034_I000 + description: 'reuse of VP_PMP_F019_S034_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check store access-fault exception + raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 006_load_MPP_L0_R1_addr_hit: !Subfeature + name: 006_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F019_S041 + next_elt_id: 1 + display_order: 6 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S041_I000 + description: 'reuse of VP_PMP_F019_S041_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S041_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check load access-fault exception + raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 007_load_MPP_L1_R1_addr_hit: !Subfeature + name: 007_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F019_S044 + next_elt_id: 1 + display_order: 7 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S044_I000 + description: 'reuse of VP_PMP_F019_S044_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S044_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check load access-fault exception + raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 008_store_MPP_L0_W1_addr_hit: !Subfeature + name: 008_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F019_S051 + next_elt_id: 1 + display_order: 8 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S051_I000 + description: 'reuse of VP_PMP_F019_S051_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S051_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check store access-fault exception + raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 009_store_MPP_L1_W1_addr_hit: !Subfeature + name: 009_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F019_S054 + next_elt_id: 1 + display_order: 9 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S054_I000 + description: 'reuse of VP_PMP_F019_S054_I000 feature description (Cf. Feature: + "cfg NA4 access S/U")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S054_I000 verification goals (Cf. Feature: + \"cfg NA4 access S/U\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check store access-fault exception + raised" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 010_fetch_L0_X1_addr_hit: !Subfeature + name: 010_fetch_L0_X1_addr_hit + tag: VP_PMP_F019_S011 + next_elt_id: 1 + display_order: 10 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S011_I000 + description: 'reuse of VP_PMP_F019_S011_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S011_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 011_fetch_L1_X1_addr_hit: !Subfeature + name: 011_fetch_L1_X1_addr_hit + tag: VP_PMP_F019_S014 + next_elt_id: 1 + display_order: 11 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S014_I000 + description: 'reuse of VP_PMP_F019_S014_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S014_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 012_load_L0_R1_addr_hit: !Subfeature + name: 012_load_L0_R1_addr_hit + tag: VP_PMP_F019_S021 + next_elt_id: 1 + display_order: 12 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S021_I000 + description: 'reuse of VP_PMP_F019_S021_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S021_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 013_load_L1_R1_addr_hit: !Subfeature + name: 013_load_L1_R1_addr_hit + tag: VP_PMP_F019_S024 + next_elt_id: 1 + display_order: 13 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S024_I000 + description: 'reuse of VP_PMP_F019_S024_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S024_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 014_store_L0_W1_addr_hit: !Subfeature + name: 014_store_L0_W1_addr_hit + tag: VP_PMP_F019_S031 + next_elt_id: 1 + display_order: 14 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S031_I000 + description: 'reuse of VP_PMP_F019_S031_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S031_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 015_store_L1_W1_addr_hit: !Subfeature + name: 015_store_L1_W1_addr_hit + tag: VP_PMP_F019_S034 + next_elt_id: 1 + display_order: 15 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S034_I000 + description: 'reuse of VP_PMP_F019_S034_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S034_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 016_load_MPP_L0_R1_addr_hit: !Subfeature + name: 016_load_MPP_L0_R1_addr_hit + tag: VP_PMP_F019_S041 + next_elt_id: 1 + display_order: 16 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S041_I000 + description: 'reuse of VP_PMP_F019_S041_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S041_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 017_load_MPP_L1_R1_addr_hit: !Subfeature + name: 017_load_MPP_L1_R1_addr_hit + tag: VP_PMP_F019_S044 + next_elt_id: 1 + display_order: 17 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S044_I000 + description: 'reuse of VP_PMP_F019_S044_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S044_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 018_store_MPP_L0_W1_addr_hit: !Subfeature + name: 018_store_MPP_L0_W1_addr_hit + tag: VP_PMP_F019_S051 + next_elt_id: 1 + display_order: 18 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S051_I000 + description: 'reuse of VP_PMP_F019_S051_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S051_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 019_store_MPP_L1_W1_addr_hit: !Subfeature + name: 019_store_MPP_L1_W1_addr_hit + tag: VP_PMP_F019_S054 + next_elt_id: 1 + display_order: 19 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F019_S054_I000 + description: 'reuse of VP_PMP_F019_S054_I000 feature description (Cf. Feature: + "cfg NA4 access M")' + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "reuse of VP_PMP_F019_S054_I000 verification goals (Cf. Feature: + \"cfg NA4 access M\")\n\nCONFIGURATION\n - check that pmpcfg(i).A=OFF + (by reading back)\n\nCHECK UPDATE\n - check store access-fault exception + raised (TODO: is M mode access prevented by A=OFF)" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP021.yml b/verif/docs/VerifPlans/PMP/VP_IP021.yml new file mode 100644 index 00000000000..67368810213 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP021.yml @@ -0,0 +1,376 @@ +!Feature +next_elt_id: 6 +name: multi entries NA4 +id: 21 +display_order: 21 +subfeatures: !!omap +- 000_1_entry: !Subfeature + name: 000_1_entry + tag: VP_PMP_F021_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F021_S001_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n - + for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: + \"cfg NA4 access S/U/M\")\n - make sure the pmp entries address ranges + are not overlapping/intersecting\n - NB: obviously, pmp entry configurations + with different mstatus.MPRV/MPP values cannot be mixed in same test\n\n\ + CHECK\n - for each pmp entry, we should obtain the expected CHECK result\n\ + \nREUSABILITY\n - if possible, the number of PMP entries (N) is a configurable + parameter\n - so a single test function can be reused" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST21(group)\n [create scenarios where PMP entries + with A=2 (NA4) and with/without matching permissions\n - check only NA4 + defined addresses are matching]\nTST21-1 = extension of (TST11-11, TST11-21, + TST11-31, TST11-41, TST11-51,\n TST11-12, TST11-22, + TST11-32, TST11-42, TST11-52,\n TST11-13, TST11-23, + TST11-33, TST11-43, TST11-53,\n TST11-14, TST11-24, + TST11-34, TST11-44, TST11-54,\n TST11-15, TST11-25, + TST11-35, TST11-45, TST11-55,\n TST11-16, TST11-26, + TST11-36, TST11-46, TST11-56,\n TST12-11, TST12-21, + TST12-31, TST12-41, TST12-51,\n TST12-12, TST12-22, + TST12-32, TST12-42, TST12-52,\n TST12-13, TST12-23, + TST12-33, TST12-43, TST12-53,\n TST12-14, TST12-24, + TST12-34, TST12-44, TST12-54,\n TST12-15, TST12-25, + TST12-35, TST12-45, TST12-55,\n TST12-16, TST12-26, + TST12-36, TST12-46, TST12-56)\n[configure only one (any, but the first one) + PMP entry\n - use A=NA4 for the PMP entry configuration\n - execute the + chosen kind of access\n - should be same result]" +- 001_2_isolated_entries: !Subfeature + name: 001_2_isolated_entries + tag: VP_PMP_F021_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F021_S002_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F021_S001_I000 feature + description (Cf. Feature: \"multi entries NA4\")" + pfc: 3 + test_type: 4 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST21(group)\n [create scenarios where PMP entries + with A=2 (NA4) and with/without matching permissions\n - check only NA4 + defined addresses are matching]\nTST21-2 = extension of compatible pair + of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51,\n \ + \ \t\t\t\t\t\t\t\t\t TST11-12, TST11-22, TST11-32, TST11-42, TST11-52,\n\ + \ \t\t\t\t\t\t\t\t\t TST11-13, TST11-23, TST11-33, + TST11-43, TST11-53,\n \t\t\t\t\t\t\t\t\t TST11-14, + TST11-24, TST11-34, TST11-44, TST11-54,\n \t\t\t\t + \t\t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n \ + \ \t\t\t\t \t\t\t\t\t TST11-16, TST11-26, TST11-36, TST11-46, + TST11-56,\n \t\t\t\t\t\t\t\t\t TST12-11, TST12-21, + TST12-31, TST12-41, TST12-51,\n \t\t\t\t\t\t\t\t\t + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52,\n \ + \ \t\t\t\t\t\t\t\t\t TST12-13, TST12-23, TST12-33, TST12-43, TST12-53,\n\ + \ \t\t\t\t\t\t\t\t\t TST12-14, TST12-24, TST12-34, + TST12-44, TST12-54,\n \t\t\t\t\t\t\t\t\t TST12-15, + TST12-25, TST12-35, TST12-45, TST12-55,\n \t\t\t\t + \t\t\t\t\t TST12-16, TST12-26, TST12-36, TST12-46, TST12-56)\n[configure + 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first + PMP entry)\n - use A=NA4 for each PMP entry configuration\n - execute + the 2 kinds of accesses (if possible to chain due to potential access-fault + exception)\n - should be same 2 results]" +- 002_N_isolated_entries: !Subfeature + name: 002_N_isolated_entries + tag: VP_PMP_F021_S003 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F021_S003_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any N PMP entries (2>\n\nTST21(group)\n [create scenarios where PMP entries + with A=2 (NA4) and with/without matching permissions\n - check only NA4 + defined addresses are matching]\nTST21-3 = extension of compatible group(N) + of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST11-12, TST11-22, TST11-32, TST11-42, + TST11-52,\n \t\t\t\t\t\t\t\t\t\t\t TST11-13, TST11-23, + TST11-33, TST11-43, TST11-53,\n \t\t\t\t\t\t\t\t\t + \t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, + TST11-55,\n \t\t\t\t\t\t\t\t\t\t\t TST11-16, TST11-26, + TST11-36, TST11-46, TST11-56,\n \t\t\t\t\t\t\t\t\t + \t\t TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST12-12, TST12-22, TST12-32, TST12-42, + TST12-52,\n \t\t\t\t\t\t\t\t\t\t\t TST12-13, TST12-23, + TST12-33, TST12-43, TST12-53,\n \t\t\t\t\t\t\t\t\t + \t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, + TST12-55,\n \t\t\t\t\t\t\t\t\t\t\t TST12-16, TST12-26, + TST12-36, TST12-46, TST12-56)\n[configure N PMP entries (highest-numbered + ones first) (as non-adjacent as possible, and avoid the first PMP entry)\n\ + \ - use A=NA4 for each PMP entry configuration\n - execute the N kinds + of accesses (if possible to chain due to potential access-fault exception)\n\ + \ - should be same N results]" +- 003_8_isolated_entries: !Subfeature + name: 003_8_isolated_entries + tag: VP_PMP_F021_S004 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F021_S004_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose all 8 PMP entries\n\nreuse of VP_PMP_F021_S001_I000 feature + description (Cf. Feature: \"multi entries NA4\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST21(group)\n [create scenarios where PMP entries + with A=2 (NA4) and with/without matching permissions\n - check only NA4 + defined addresses are matching]\nTST21-4 = extension of compatible group(8) + of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST11-12, TST11-22, TST11-32, TST11-42, + TST11-52,\n \t\t\t\t\t\t\t\t\t\t\t TST11-13, TST11-23, + TST11-33, TST11-43, TST11-53,\n \t\t\t\t\t\t\t\t\t + \t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, + TST11-55,\n \t\t\t\t\t\t\t\t\t\t\t TST11-16, TST11-26, + TST11-36, TST11-46, TST11-56,\n \t\t\t\t\t\t\t\t\t + \t\t TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST12-12, TST12-22, TST12-32, TST12-42, + TST12-52,\n \t\t\t\t\t\t\t\t\t\t\t TST12-13, TST12-23, + TST12-33, TST12-43, TST12-53,\n \t\t\t\t\t\t\t\t\t + \t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, + TST12-55,\n \t\t\t\t\t\t\t\t\t\t\t TST12-16, TST12-26, + TST12-36, TST12-46, TST12-56)\n[configure 8 PMP entries (highest-numbered + ones first)\n - use A=NA4 for each PMP entry configuration\n - execute + the 8 kinds of accesses (if possible to chain due to potential access-fault + exception)\n - should be same 8 results]" +- 004_2_intersecting_entries_fail: !Subfeature + name: 004_2_intersecting_entries_fail + tag: VP_PMP_F021_S005 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F021_S005_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature: + \"cfg NA4 access S/U/M\")\n - for the least-numbered pmp entry, apply + any CONFIGURATION+ACCESS scenario with access-fault\n - for the highest-numbered + pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault\n\ + \ - make sure the pmp entries address ranges are overlapping/intersecting + (at least at 4 consecutive bytes)\n - for each pmp entry, execute one + access in its associated pmp address region but outside the overlapping/intersecting + address range\n - execute one additional access inside the overlapping/intersecting + address range\n - NB: obviously, pmp entry configurations with different + access-modes (S/U vs. M) cannot be easily mixed in same test\n - NB: + obviously, pmp entry configurations with different mstatus.MPRV/MPP values + cannot be mixed in same test\n\nCHECK\n - for each pmp entry, access + outside the overlapping/intersecting address range should give the expected + CHECK result\n - access inside the overlapping/intersecting address range + should generate the access-type related access-fault\n\nREUSABILITY\n \ + \ - if possible, the number of PMP entries (N) is a configurable parameter\n\ + \ - so a single test function can be reused" + pfc: 3 + test_type: 4 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n [create + scenarios where 2 PMP entries with same pmpaddr\n - one without matching + permissions or with A=OFF\n - one with matching permissions and A=NA4/NAPOT/TOR\n\ + \ - any of them can be the lowest-numbered PMP entry]\nTST51-1\n[configure + 2 PMP entries\n - configure the lowest-numbered PMP entry with (TST11-12, + TST11-22, TST11-32, TST11-42, TST11-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22, + TST12-32, TST12-42, TST12-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n \ + \ TST13-12, TST13-22, TST13-32, TST13-42, + TST13-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-15, + TST13-25, TST13-35, TST13-45, TST13-55,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, TST14-25, + TST14-35, TST14-45, TST14-55,\n \ + \ TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, TST15-35, + TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45, + TST16-55,\n TST17-12, + TST17-22, TST17-32, TST17-42, TST17-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, TST17-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, TST18-22, + TST18-32, TST18-42, TST18-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n - configure + the highest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, + TST11-51,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST11-14, + TST11-24, TST11-34, TST11-44, TST11-54,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-14, TST12-24, + TST12-34, TST12-44, TST12-54,\n \ + \ TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST13-14, TST13-24, TST13-34, + TST13-44, TST13-54,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + \tTST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST14-14, TST14-24, TST14-34, TST14-44, + TST14-54,\n TST15-11, + TST15-21, TST15-31, TST15-41, TST15-51,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-11, TST16-21, + TST16-31, TST16-41, TST16-51,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44, TST16-54)\n - execute + the associated access\n - check associated access-fault exception raised]" +- 005_2_intersecting_entries_succeed: !Subfeature + name: 005_2_intersecting_entries_succeed + tag: VP_PMP_F021_S006 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F021_S006_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature: + \"cfg NA4 access S/U/M\")\n - for the least-numbered pmp entry, apply + any CONFIGURATION+ACCESS scenario without access-fault\n - for the highest-numbered + pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault\n \ + \ - make sure the pmp entries address ranges are overlapping/intersecting + (at least at 4 consecutive bytes)\n - for each pmp entry, execute one + access in its associated pmp address region but outside the overlapping/intersecting + address range\n - execute one additional access inside the overlapping/intersecting + address range\n - NB: obviously, pmp entry configurations with different + access-modes (S/U vs. M) cannot be easily mixed in same test\n - NB: + obviously, pmp entry configurations with different mstatus.MPRV/MPP values + cannot be mixed in same test\n\nCHECK\n - for each pmp entry, access + outside the overlapping/intersecting address range should give the expected + CHECK result\n - access inside the overlapping/intersecting address range + should not generate any access-fault\n\nREUSABILITY\n - if possible, + the number of PMP entries (N) is a configurable parameter\n - so a single + test function can be reused" + pfc: 3 + test_type: 4 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n [create + scenarios where 2 PMP entries with same pmpaddr\n - one without matching + permissions or with A=OFF\n - one with matching permissions and A=NA4/NAPOT/TOR\n\ + \ - any of them can be the lowest-numbered PMP entry]\nTST51-2\n[configure + 2 PMP entries\n - configure the lowest-numbered PMP entry with (TST11-11, + TST11-21, TST11-31, TST11-41, TST11-51,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-11, TST12-21, + TST12-31, TST12-41, TST12-51,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n \ + \ TST13-11, TST13-21, TST13-31, TST13-41, + TST13-51,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-14, + TST13-24, TST13-34, TST13-44, TST13-54,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-14, TST14-24, + TST14-34, TST14-44, TST14-54,\n \ + \ TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34, + TST15-44, TST15-54,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44, + TST16-54)\n - configure the highest-numbered PMP entry with (TST11-12, + TST11-22, TST11-32, TST11-42, TST11-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22, + TST12-32, TST12-42, TST12-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n \ + \ TST13-12, TST13-22, TST13-32, + TST13-42, TST13-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t\ + \ TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, + TST14-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, + TST14-25, TST14-35, TST14-45, TST14-55,\n \ + \ TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, + TST15-35, TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, + TST16-45, TST16-55,\n \ + \ TST17-12, TST17-22, TST17-32, TST17-42, TST17-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, + TST17-55,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, + TST18-22, TST18-32, TST18-42, TST18-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n\ + \ - execute the associated access\n - check no access-fault exception]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP022.yml b/verif/docs/VerifPlans/PMP/VP_IP022.yml new file mode 100644 index 00000000000..7412bcc7bfb --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP022.yml @@ -0,0 +1,376 @@ +!Feature +next_elt_id: 6 +name: multi entries NAPOT +id: 22 +display_order: 22 +subfeatures: !!omap +- 000_1_entry: !Subfeature + name: 000_1_entry + tag: VP_PMP_F022_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F022_S001_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n - + for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: + \"cfg NAPOT access S/U/M\")\n - make sure the pmp entries address ranges + are not overlapping/intersecting\n - NB: obviously, pmp entry configurations + with different mstatus.MPRV/MPP values cannot be mixed in same test\n\n\ + CHECK\n - for each pmp entry, we should obtain the expected CHECK result\n\ + \nREUSABILITY\n - if possible, the number of PMP entries (N) is a configurable + parameter\n - so a single test function can be reused" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST22(group)\n [create scenarios where PMP entries + with A=3 (NAPOT) and with/without matching permissions\n - check only + NAPOT defined addresses are matching]\nTST22-1 = extension of (TST13-11, + TST13-21, TST13-31, TST13-41, TST13-51,\n TST13-12, + TST13-22, TST13-32, TST13-42, TST13-52,\n TST13-13, + TST13-23, TST13-33, TST13-43, TST13-53,\n TST13-14, + TST13-24, TST13-34, TST13-44, TST13-54,\n TST13-15, + TST13-25, TST13-35, TST13-45, TST13-55,\n TST13-16, + TST13-26, TST13-36, TST13-46, TST13-56,\n TST14-11, + TST14-21, TST14-31, TST14-41, TST14-51,\n TST14-12, + TST14-22, TST14-32, TST14-42, TST14-52,\n TST14-13, + TST14-23, TST14-33, TST14-43, TST14-53,\n TST14-14, + TST14-24, TST14-34, TST14-44, TST14-54,\n TST14-15, + TST14-25, TST14-35, TST14-45, TST14-55,\n TST14-16, + TST14-26, TST14-36, TST14-46, TST14-56)\n[configure only one (any, but the + first one) PMP entry\n - use A=NAPOT for the PMP entry configuration\n\ + \ - execute the chosen kind of access\n - should be same result]" +- 001_2_isolated_entries: !Subfeature + name: 001_2_isolated_entries + tag: VP_PMP_F022_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F022_S002_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F022_S001_I000 feature + description (Cf. Feature: \"multi entries NAPOT\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST22(group)\n [create scenarios where PMP entries + with A=3 (NAPOT) and with/without matching permissions\n - check only + NAPOT defined addresses are matching]\nTST22-2 = extension of compatible + pair of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n \ + \ \t\t\t\t\t\t\t\t\t TST13-12, TST13-22, TST13-32, TST13-42, + TST13-52,\n \t\t\t\t\t\t\t\t\t TST13-13, TST13-23, + TST13-33, TST13-43, TST13-53,\n \t\t\t\t\t\t\t\t\t + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54,\n \ + \ \t\t\t\t\t\t\t\t\t TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n\ + \ \t\t\t\t \t\t\t\t\t TST13-16, TST13-26, TST13-36, + TST13-46, TST13-56,\n \t\t\t\t\t\t\t\t\t TST14-11, + TST14-21, TST14-31, TST14-41, TST14-51,\n \t\t\t\t + \t\t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n \ + \ \t\t\t\t\t\t\t\t\t TST14-13, TST14-23, TST14-33, TST14-43, + TST14-53,\n \t\t\t\t\t\t\t\t\t TST14-14, TST14-24, + TST14-34, TST14-44, TST14-54,\n \t\t\t\t\t\t\t\t\t + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55,\n \ + \ \t\t\t\t\t\t\t\t\t TST14-16, TST14-26, TST14-36, TST14-46, TST14-56)\n + [configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid + the first PMP entry)\n - use A=NAPOT for each PMP entry configuration\n\ + \ - execute the 2 kinds of accesses (if possible to chain due to potential + access-fault exception)\n - should be same 2 results]" +- 002_N_isolated_entries: !Subfeature + name: 002_N_isolated_entries + tag: VP_PMP_F022_S003 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F022_S003_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any N PMP entries (2>\n\nTST22(group)\n [create scenarios where PMP entries + with A=3 (NAPOT) and with/without matching permissions\n - check only + NAPOT defined addresses are matching]\nTST22-3 = extension of compatible + group(N) of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST13-12, TST13-22, TST13-32, + TST13-42, TST13-52,\n \t\t\t\t\t\t\t\t\t\t\t TST13-13, + TST13-23, TST13-33, TST13-43, TST13-53,\n \t\t\t\t + \t\t\t\t\t\t\t TST13-14, TST13-24, TST13-34, TST13-44, TST13-54,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST13-15, TST13-25, TST13-35, + TST13-45, TST13-55,\n \t\t\t\t\t\t\t\t\t\t\t TST13-16, + TST13-26, TST13-36, TST13-46, TST13-56,\n \t\t\t\t + \t\t\t\t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST14-12, TST14-22, TST14-32, + TST14-42, TST14-52,\n \t\t\t\t\t\t\t\t\t\t\t TST14-13, + TST14-23, TST14-33, TST14-43, TST14-53,\n \t\t\t\t + \t\t\t\t\t\t\t TST14-14, TST14-24, TST14-34, TST14-44, TST14-54,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST14-15, TST14-25, TST14-35, + TST14-45, TST14-55,\n \t\t\t\t\t\t\t\t\t\t\t TST14-16, + TST14-26, TST14-36, TST14-46, TST14-56)\n[configure N PMP entries (highest-numbered + ones first) (as non-adjacent as possible, and avoid the first PMP entry)\n\ + \ - use A=NAPOT for each PMP entry configuration\n - execute the N kinds + of accesses (if possible to chain due to potential access-fault exception)\n\ + \ - should be same N results]" +- 003_8_isolated_entries: !Subfeature + name: 003_8_isolated_entries + tag: VP_PMP_F022_S004 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F022_S004_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose all 8 PMP entries\n\nreuse of VP_PMP_F022_S001_I000 feature + description (Cf. Feature: \"multi entries NAPOT\")" + pfc: 3 + test_type: 3 + cov_method: 0 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST22(group)\n [create scenarios where PMP entries + with A=3 (NAPOT) and with/without matching permissions\n - check only + NAPOT defined addresses are matching]\nTST22-4 = extension of compatible + group(8) of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST13-12, TST13-22, TST13-32, + TST13-42, TST13-52,\n \t\t\t\t\t\t\t\t\t\t\t TST13-13, + TST13-23, TST13-33, TST13-43, TST13-53,\n \t\t\t\t + \t\t\t\t\t\t\t TST13-14, TST13-24, TST13-34, TST13-44, TST13-54,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST13-15, TST13-25, TST13-35, + TST13-45, TST13-55,\n \t\t\t\t\t\t\t\t\t\t\t TST13-16, + TST13-26, TST13-36, TST13-46, TST13-56,\n \t\t\t\t + \t\t\t\t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST14-12, TST14-22, TST14-32, + TST14-42, TST14-52,\n \t\t\t\t\t\t\t\t\t\t\t TST14-13, + TST14-23, TST14-33, TST14-43, TST14-53,\n \t\t\t\t + \t\t\t\t\t\t\t TST14-14, TST14-24, TST14-34, TST14-44, TST14-54,\n \ + \ \t\t\t\t \t\t\t\t\t\t\t TST14-15, TST14-25, TST14-35, + TST14-45, TST14-55,\n \t\t\t\t\t\t\t\t\t\t\t TST14-16, + TST14-26, TST14-36, TST14-46, TST14-56)\n[configure 8 PMP entries (highest-numbered + ones first)\n - use A=NAPOT for each PMP entry configuration\n - execute + the 8 kinds of accesses (if possible to chain due to potential access-fault + exception)\n - should be same 8 results]" +- 004_2_intersecting_entries_fail: !Subfeature + name: 004_2_intersecting_entries_fail + tag: VP_PMP_F022_S005 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F022_S005_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature: + \"cfg NAPOT access S/U/M\")\n - for the least-numbered pmp entry, apply + any CONFIGURATION+ACCESS scenario with access-fault\n - for the highest-numbered + pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault\n\ + \ - make sure the pmp entries address ranges are overlapping/intersecting + (at least at 4 consecutive bytes)\n - for each pmp entry, execute one + access in its associated pmp address region but outside the overlapping/intersecting + address range\n - execute one additional access inside the overlapping/intersecting + address range\n - NB: obviously, pmp entry configurations with different + access-modes (S/U vs. M) cannot be easily mixed in same test\n - NB: + obviously, pmp entry configurations with different mstatus.MPRV/MPP values + cannot be mixed in same test\n\nCHECK\n - for each pmp entry, access + outside the overlapping/intersecting address range should give the expected + CHECK result\n - access inside the overlapping/intersecting address range + should generate the access-type related access-fault\n\nREUSABILITY\n \ + \ - if possible, the number of PMP entries (N) is a configurable parameter\n\ + \ - so a single test function can be reused" + pfc: 3 + test_type: 4 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n [create + scenarios where 2 PMP entries with same pmpaddr\n - one without matching + permissions or with A=OFF\n - one with matching permissions and A=NA4/NAPOT/TOR\n\ + \ - any of them can be the lowest-numbered PMP entry]\nTST51-1\n[configure + 2 PMP entries\n - configure the lowest-numbered PMP entry with (TST11-12, + TST11-22, TST11-32, TST11-42, TST11-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22, + TST12-32, TST12-42, TST12-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n \ + \ TST13-12, TST13-22, TST13-32, TST13-42, + TST13-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-15, + TST13-25, TST13-35, TST13-45, TST13-55,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, TST14-25, + TST14-35, TST14-45, TST14-55,\n \ + \ TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, TST15-35, + TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45, + TST16-55,\n TST17-12, + TST17-22, TST17-32, TST17-42, TST17-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, TST17-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, TST18-22, + TST18-32, TST18-42, TST18-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n - configure + the highest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, + TST11-51,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST11-14, + TST11-24, TST11-34, TST11-44, TST11-54,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-14, TST12-24, + TST12-34, TST12-44, TST12-54,\n \ + \ TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST13-14, TST13-24, TST13-34, + TST13-44, TST13-54,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + \tTST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST14-14, TST14-24, TST14-34, TST14-44, + TST14-54,\n TST15-11, + TST15-21, TST15-31, TST15-41, TST15-51,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-11, TST16-21, + TST16-31, TST16-41, TST16-51,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44, TST16-54)\n - execute + the associated access\n - check associated access-fault exception raised]" +- 005_2_intersecting_entries_succeed: !Subfeature + name: 005_2_intersecting_entries_succeed + tag: VP_PMP_F022_S006 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F022_S006_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature: + \"cfg NAPOT access S/U/M\")\n - for the least-numbered pmp entry, apply + any CONFIGURATION+ACCESS scenario without access-fault\n - for the highest-numbered + pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault\n \ + \ - make sure the pmp entries address ranges are overlapping/intersecting + (at least at 4 consecutive bytes)\n - for each pmp entry, execute one + access in its associated pmp address region but outside the overlapping/intersecting + address range\n - execute one additional access inside the overlapping/intersecting + address range\n - NB: obviously, pmp entry configurations with different + access-modes (S/U vs. M) cannot be easily mixed in same test\n - NB: + obviously, pmp entry configurations with different mstatus.MPRV/MPP values + cannot be mixed in same test\n\nCHECK\n - for each pmp entry, access + outside the overlapping/intersecting address range should give the expected + CHECK result\n - access inside the overlapping/intersecting address range + should not generate any access-fault\n\nREUSABILITY\n - if possible, + the number of PMP entries (N) is a configurable parameter\n - so a single + test function can be reused" + pfc: 3 + test_type: 4 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n [create + scenarios where 2 PMP entries with same pmpaddr\n - one without matching + permissions or with A=OFF\n - one with matching permissions and A=NA4/NAPOT/TOR\n\ + \ - any of them can be the lowest-numbered PMP entry]\nTST51-2\n[configure + 2 PMP entries\n - configure the lowest-numbered PMP entry with (TST11-11, + TST11-21, TST11-31, TST11-41, TST11-51,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-11, TST12-21, + TST12-31, TST12-41, TST12-51,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n \ + \ TST13-11, TST13-21, TST13-31, TST13-41, + TST13-51,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-14, + TST13-24, TST13-34, TST13-44, TST13-54,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-14, TST14-24, + TST14-34, TST14-44, TST14-54,\n \ + \ TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34, + TST15-44, TST15-54,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44, + TST16-54)\n - configure the highest-numbered PMP entry with (TST11-12, + TST11-22, TST11-32, TST11-42, TST11-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22, + TST12-32, TST12-42, TST12-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n \ + \ TST13-12, TST13-22, TST13-32, + TST13-42, TST13-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t\ + \ TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, + TST14-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, + TST14-25, TST14-35, TST14-45, TST14-55,\n \ + \ TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, + TST15-35, TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, + TST16-45, TST16-55,\n \ + \ TST17-12, TST17-22, TST17-32, TST17-42, TST17-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, + TST17-55,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, + TST18-22, TST18-32, TST18-42, TST18-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n\ + \ - execute the associated access\n - check no access-fault exception]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP023.yml b/verif/docs/VerifPlans/PMP/VP_IP023.yml new file mode 100644 index 00000000000..b09fcd938aa --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP023.yml @@ -0,0 +1,378 @@ +!Feature +next_elt_id: 6 +name: multi entries TOR +id: 23 +display_order: 23 +subfeatures: !!omap +- 000_1_entry: !Subfeature + name: 000_1_entry + tag: VP_PMP_F023_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F023_S001_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n - + for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: + \"cfg TOR access S/U/M\")\n - make sure the pmp entries address ranges + are not overlapping/intersecting\n - NB: obviously, pmp entry configurations + with different mstatus.MPRV/MPP values cannot be mixed in same test\n\n\ + CHECK\n - for each pmp entry, we should obtain the expected CHECK result\n\ + \nREUSABILITY\n - if possible, the number of PMP entries (N) is a configurable + parameter\n - so a single test function can be reused" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST23(group) => \n [create scenarios where PMP entries + with A=1 (TOR) and with/without matching permissions\n - pmpaddr(i−1) + < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions\n\ + \ - check only TOR defined addresses are matching]\nTST23-1 = extension + of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n \ + \ TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n \ + \ TST15-13, TST15-23, TST15-33, TST15-43, TST15-53,\n \ + \ TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n \ + \ TST15-15, TST15-25, TST15-35, TST15-45, TST15-55,\n\ + \ TST15-16, TST15-26, TST15-36, TST15-46, TST15-56,\n\ + \ TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n\ + \ TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n\ + \ TST16-13, TST16-23, TST16-33, TST16-43, TST16-53,\n\ + \ TST16-14, TST16-24, TST16-34, TST16-44, TST16-54,\n\ + \ TST16-15, TST16-25, TST16-35, TST16-45, TST16-55,\n\ + \ TST16-16, TST16-26, TST16-36, TST16-46, TST16-56)\n + [configure only one (any, but the first one) PMP entry\n - execute the + chosen kind of access\n - should be same result]" +- 001_2_isolated_entries: !Subfeature + name: 001_2_isolated_entries + tag: VP_PMP_F023_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F023_S002_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F023_S001_I000 feature + description (Cf. Feature: \"multi entries TOR\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST23(group) => \n [create scenarios where PMP entries + with A=1 (TOR) and with/without matching permissions\n - pmpaddr(i−1) + < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions\n\ + \ - check only TOR defined addresses are matching]\nTST23-2 = extension + of compatible pair of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n\ + \ \t\t\t\t\t\t\t\t\t TST15-12, TST15-22, TST15-32, + TST15-42, TST15-52,\n \t\t\t\t\t\t\t\t\t TST15-13, + TST15-23, TST15-33, TST15-43, TST15-53,\n \t\t\t\t + \t\t\t\t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n \ + \ \t\t\t\t\t\t\t\t\t TST15-15, TST15-25, TST15-35, TST15-45, + TST15-55,\n \t\t\t\t\t\t\t\t\t TST15-16, TST15-26, + TST15-36, TST15-46, TST15-56,\n \t\t\t\t\t\t\t\t\t + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n \ + \ \t\t\t\t \t\t\t\t\t TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n\ + \ \t\t\t\t\t\t\t\t\t TST16-13, TST16-23, TST16-33, + TST16-43, TST16-53,\n \t\t\t\t\t\t\t\t\t TST16-14, + TST16-24, TST16-34, TST16-44, TST16-54,\n \t\t\t\t + \t\t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45, TST16-55,\n \ + \ \t\t\t\t\t\t\t\t\t TST16-16, TST16-26, TST16-36, TST16-46, + TST16-56)\n [configure 2 non-adjacent PMP entries (highest-numbered ones + first) (avoid the first PMP entry)\n - execute the 2 kinds of accesses + (if possible to chain due to potential access-fault exception)\n - should + be same 2 results]" +- 002_N_isolated_entries: !Subfeature + name: 002_N_isolated_entries + tag: VP_PMP_F023_S003 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F023_S003_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any N PMP entries (2>\n\nTST23(group) => \n [create scenarios where PMP entries + with A=1 (TOR) and with/without matching permissions\n - pmpaddr(i−1) + < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions\n\ + \ - check only TOR defined addresses are matching]\nTST23-3 = extension + of compatible group(N) of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n\ + \ \t\t\t\t\t\t\t\t\t\t\t TST15-12, TST15-22, TST15-32, + TST15-42, TST15-52,\n \t\t\t\t\t\t\t\t\t\t\t TST15-13, + TST15-23, TST15-33, TST15-43, TST15-53,\n \t\t\t\t + \t\t\t\t\t \t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n \ + \ \t\t\t\t\t\t\t\t\t\t\t TST15-15, TST15-25, TST15-35, + TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t\t\t TST15-16, + TST15-26, TST15-36, TST15-46, TST15-56,\n \t\t\t\t + \t\t\t\t\t \t\t TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n \ + \ \t\t\t\t\t\t\t\t\t\t\t TST16-12, TST16-22, TST16-32, + TST16-42, TST16-52,\n \t\t\t\t\t\t\t\t\t\t\t TST16-13, + TST16-23, TST16-33, TST16-43, TST16-53,\n \t\t\t\t + \t\t\t\t\t \t\t TST16-14, TST16-24, TST16-34, TST16-44, TST16-54,\n \ + \ \t\t\t\t\t\t\t\t\t\t\t TST16-15, TST16-25, TST16-35, + TST16-45, TST16-55,\n \t\t\t\t\t\t\t\t\t\t\t TST16-16, + TST16-26, TST16-36, TST16-46, TST16-56)\n[configure N PMP entries (highest-numbered + ones first) (as non-adjacent as possible, and avoid the first PMP entry)\n\ + \ - execute the N kinds of accesses (if possible to chain due to potential + access-fault exception)\n - should be same N results]" +- 003_8_isolated_entries: !Subfeature + name: 003_8_isolated_entries + tag: VP_PMP_F023_S004 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F023_S004_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose all 8 PMP entries\n\nreuse of VP_PMP_F023_S001_I000 feature + description (Cf. Feature: \"multi entries TOR\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST23(group) => \n [create scenarios where PMP entries + with A=1 (TOR) and with/without matching permissions\n - pmpaddr(i−1) + < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions\n\ + \ - check only TOR defined addresses are matching]\nTST23-4 = extension + of compatible group(8) of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n\ + \ \t\t\t\t\t\t\t\t\t\t\t TST15-12, TST15-22, TST15-32, + TST15-42, TST15-52,\n \t\t\t\t\t\t\t\t\t\t\t TST15-13, + TST15-23, TST15-33, TST15-43, TST15-53,\n \t\t\t\t + \t\t\t\t\t \t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n \ + \ \t\t\t\t\t\t\t\t\t\t\t TST15-15, TST15-25, TST15-35, + TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t\t\t TST15-16, + TST15-26, TST15-36, TST15-46, TST15-56,\n \t\t\t\t + \t\t\t\t\t \t\t TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n \ + \ \t\t\t\t\t\t\t\t\t\t\t TST16-12, TST16-22, TST16-32, + TST16-42, TST16-52,\n \t\t\t\t\t\t\t\t\t\t\t TST16-13, + TST16-23, TST16-33, TST16-43, TST16-53,\n \t\t\t\t + \t\t\t\t\t \t\t TST16-14, TST16-24, TST16-34, TST16-44, TST16-54,\n \ + \ \t\t\t\t\t\t\t\t\t\t\t TST16-15, TST16-25, TST16-35, + TST16-45, TST16-55,\n \t\t\t\t\t\t\t\t\t\t\t TST16-16, + TST16-26, TST16-36, TST16-46, TST16-56)\n[configure 8 PMP entries (highest-numbered + ones first)\n - execute the 8 kinds of accesses (if possible to chain due + to potential access-fault exception)\n - should be same 8 results]" +- 004_2_intersecting_entries_fail: !Subfeature + name: 004_2_intersecting_entries_fail + tag: VP_PMP_F023_S005 + next_elt_id: 1 + display_order: 4 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F023_S005_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature: + \"cfg TOR access S/U/M\")\n - for the least-numbered pmp entry, apply + any CONFIGURATION+ACCESS scenario with access-fault\n - for the highest-numbered + pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault\n\ + \ - make sure the pmp entries address ranges are overlapping/intersecting + (at least at 4 consecutive bytes)\n - for each pmp entry, execute one + access in its associated pmp address region but outside the overlapping/intersecting + address range\n - execute one additional access inside the overlapping/intersecting + address range\n - NB: obviously, pmp entry configurations with different + access-modes (S/U vs. M) cannot be easily mixed in same test\n - NB: + obviously, pmp entry configurations with different mstatus.MPRV/MPP values + cannot be mixed in same test\n\nCHECK\n - for each pmp entry, access + outside the overlapping/intersecting address range should give the expected + CHECK result\n - access inside the overlapping/intersecting address range + should generate the access-type related access-fault\n\nREUSABILITY\n \ + \ - if possible, the number of PMP entries (N) is a configurable parameter\n\ + \ - so a single test function can be reused" + pfc: 3 + test_type: 4 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n [create + scenarios where 2 PMP entries with same pmpaddr\n - one without matching + permissions or with A=OFF\n - one with matching permissions and A=NA4/NAPOT/TOR\n\ + \ - any of them can be the lowest-numbered PMP entry]\nTST51-1\n[configure + 2 PMP entries\n - configure the lowest-numbered PMP entry with (TST11-12, + TST11-22, TST11-32, TST11-42, TST11-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22, + TST12-32, TST12-42, TST12-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n \ + \ TST13-12, TST13-22, TST13-32, TST13-42, + TST13-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-15, + TST13-25, TST13-35, TST13-45, TST13-55,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, TST14-25, + TST14-35, TST14-45, TST14-55,\n \ + \ TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, TST15-35, + TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45, + TST16-55,\n TST17-12, + TST17-22, TST17-32, TST17-42, TST17-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, TST17-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, TST18-22, + TST18-32, TST18-42, TST18-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n - configure + the highest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, + TST11-51,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST11-14, + TST11-24, TST11-34, TST11-44, TST11-54,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-14, TST12-24, + TST12-34, TST12-44, TST12-54,\n \ + \ TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST13-14, TST13-24, TST13-34, + TST13-44, TST13-54,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + \tTST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST14-14, TST14-24, TST14-34, TST14-44, + TST14-54,\n TST15-11, + TST15-21, TST15-31, TST15-41, TST15-51,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-11, TST16-21, + TST16-31, TST16-41, TST16-51,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44, TST16-54)\n - execute + the associated access\n - check associated access-fault exception raised]" +- 005_2_intersecting_entries_succeed: !Subfeature + name: 005_2_intersecting_entries_succeed + tag: VP_PMP_F023_S006 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F023_S006_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature: + \"cfg TOR access S/U/M\")\n - for the least-numbered pmp entry, apply + any CONFIGURATION+ACCESS scenario without access-fault\n - for the highest-numbered + pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault\n \ + \ - make sure the pmp entries address ranges are overlapping/intersecting + (at least at 4 consecutive bytes)\n - for each pmp entry, execute one + access in its associated pmp address region but outside the overlapping/intersecting + address range\n - execute one additional access inside the overlapping/intersecting + address range\n - NB: obviously, pmp entry configurations with different + access-modes (S/U vs. M) cannot be easily mixed in same test\n - NB: + obviously, pmp entry configurations with different mstatus.MPRV/MPP values + cannot be mixed in same test\n\nCHECK\n - for each pmp entry, access + outside the overlapping/intersecting address range should give the expected + CHECK result\n - access inside the overlapping/intersecting address range + should not generate any access-fault\n\nREUSABILITY\n - if possible, + the number of PMP entries (N) is a configurable parameter\n - so a single + test function can be reused" + pfc: 3 + test_type: 4 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n [create + scenarios where 2 PMP entries with same pmpaddr\n - one without matching + permissions or with A=OFF\n - one with matching permissions and A=NA4/NAPOT/TOR\n\ + \ - any of them can be the lowest-numbered PMP entry]\nTST51-2\n[configure + 2 PMP entries\n - configure the lowest-numbered PMP entry with (TST11-11, + TST11-21, TST11-31, TST11-41, TST11-51,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-11, TST12-21, + TST12-31, TST12-41, TST12-51,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n \ + \ TST13-11, TST13-21, TST13-31, TST13-41, + TST13-51,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-14, + TST13-24, TST13-34, TST13-44, TST13-54,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-14, TST14-24, + TST14-34, TST14-44, TST14-54,\n \ + \ TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34, + TST15-44, TST15-54,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44, + TST16-54)\n - configure the highest-numbered PMP entry with (TST11-12, + TST11-22, TST11-32, TST11-42, TST11-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22, + TST12-32, TST12-42, TST12-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n \ + \ TST13-12, TST13-22, TST13-32, + TST13-42, TST13-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t\ + \ TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, + TST14-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, + TST14-25, TST14-35, TST14-45, TST14-55,\n \ + \ TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, + TST15-35, TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, + TST16-45, TST16-55,\n \ + \ TST17-12, TST17-22, TST17-32, TST17-42, TST17-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, + TST17-55,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, + TST18-22, TST18-32, TST18-42, TST18-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n\ + \ - execute the associated access\n - check no access-fault exception]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP024.yml b/verif/docs/VerifPlans/PMP/VP_IP024.yml new file mode 100644 index 00000000000..824f2ef61d5 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP024.yml @@ -0,0 +1,200 @@ +!Feature +next_elt_id: 4 +name: multi entries OFF +id: 24 +display_order: 24 +subfeatures: !!omap +- 000_1_entry: !Subfeature + name: 000_1_entry + tag: VP_PMP_F024_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F024_S001_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n - + for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: + \"cfg OFF access S/U/M\")\n - make sure the pmp entries address ranges + are not overlapping/intersecting\n - NB: obviously, pmp entry configurations + with different mstatus.MPRV/MPP values cannot be mixed in same test\n\n\ + CHECK\n - for each pmp entry, we should obtain the expected CHECK result\n\ + \nREUSABILITY\n - if possible, the number of PMP entries (N) is a configurable + parameter\n - so a single test function can be reused" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST24(group) => FTR09-g\n [create scenarios where PMP + entries with A=0 (OFF) and with matching permissions\n - check no address + matching for those PMP entries]\n [create scenarios where all PMP entries + with A=0 (OFF) and with matching permissions\n - check no address matching + for all PMP entries]\n [check S or U mode access fails when all A=OFF with + at least one PMP entry implemented] => FTR09-g\nTST24-1 = extension of (TST17-11, + TST17-21, TST17-31, TST17-41, TST17-51,\n TST17-13, + TST17-23, TST17-33, TST17-43, TST17-53,\n TST17-14, + TST17-24, TST17-34, TST17-44, TST17-54,\n TST17-16, + TST17-26, TST17-36, TST17-46, TST17-56,\n TST18-14, + TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an + exception\n TST18-16, TST18-26, TST18-36, TST18-46, + TST18-56) //TODO: M-mode may not raise an exception\n \ + \ //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51,\n\ + \ TST18-13, TST18-23, TST18-33, + TST18-43, TST18-53) ?\n[configure only one (any, but the first one) PMP + entry\n - execute the chosen kind of access\n - check appropriate access-fault + exception raised]" +- 001_2_isolated_entries: !Subfeature + name: 001_2_isolated_entries + tag: VP_PMP_F024_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F024_S002_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F024_S001_I000 feature + description (Cf. Feature: \"multi entries OFF\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST24(group) => FTR09-g\n [create scenarios where PMP + entries with A=0 (OFF) and with matching permissions\n - check no address + matching for those PMP entries]\n [create scenarios where all PMP entries + with A=0 (OFF) and with matching permissions\n - check no address matching + for all PMP entries]\n [check S or U mode access fails when all A=OFF with + at least one PMP entry implemented] => FTR09-g\nTST24-2 = extension of compatible + pair of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51,\n \ + \ \t\t\t\t\t\t\t\t\t TST17-13, TST17-23, TST17-33, TST17-43, + TST17-53,\n \t\t\t\t\t\t\t\t\t TST17-14, TST17-24, + TST17-34, TST17-44, TST17-54,\n \t\t\t\t\t\t\t\t + \t TST17-16, TST17-26, TST17-36, TST17-46, TST17-56,\n \ + \ \t\t\t\t\t\t\t\t\t TST18-14, TST18-24, TST18-34, TST18-44, TST18-54, + //TODO: M-mode may not raise an exception\n \t\t + \t\t\t\t\t\t\t TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO: + M-mode may not raise an exception\n //TODO: SHOULD + WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51,\n \ + \ TST18-13, TST18-23, TST18-33, TST18-43, + TST18-53) ?\n[configure 2 non-adjacent PMP entries (highest-numbered ones + first) (avoid the first PMP entry)\n - execute the 2 kinds of accesses + (if possible to chain due to access-fault)\n - check 2 appropriate access-fault + exceptions raised]" +- 002_N_isolated_entries: !Subfeature + name: 002_N_isolated_entries + tag: VP_PMP_F024_S003 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F024_S003_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any N PMP entries (2>\n\nTST24(group) => FTR09-g\n [create scenarios where PMP + entries with A=0 (OFF) and with matching permissions\n - check no address + matching for those PMP entries]\n [create scenarios where all PMP entries + with A=0 (OFF) and with matching permissions\n - check no address matching + for all PMP entries]\n [check S or U mode access fails when all A=OFF with + at least one PMP entry implemented] => FTR09-g\nTST24-3 = extension of compatible + group(N) of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51,\n \ + \ \t\t\t\t\t\t\t\t\t\t TST17-13, TST17-23, TST17-33, TST17-43, + TST17-53,\n \t\t\t\t\t\t\t\t\t\t TST17-14, TST17-24, + TST17-34, TST17-44, TST17-54,\n \t\t\t\t\t\t\t\t + \t\t TST17-16, TST17-26, TST17-36, TST17-46, TST17-56,\n \ + \ \t\t\t\t\t\t\t\t\t\t TST18-14, TST18-24, TST18-34, TST18-44, + TST18-54, //TODO: M-mode may not raise an exception\n \ + \ \t\t\t\t\t\t\t\t\t\t TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) + //TODO: M-mode may not raise an exception\n //TODO: + SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51,\n \ + \ TST18-13, TST18-23, TST18-33, + TST18-43, TST18-53) ?\n[configure N PMP entries (highest-numbered ones first) + (as non-adjacent as possible, and avoid the first PMP entry)\n - execute + the N kinds of accesses (if possible to chain due to access-fault)\n - + check N appropriate access-fault exceptions raised]" +- 003_8_isolated_entries: !Subfeature + name: 003_8_isolated_entries + tag: VP_PMP_F024_S004 + next_elt_id: 1 + display_order: 3 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F024_S004_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose all 8 PMP entries\n\nreuse of VP_PMP_F024_S001_I000 feature + description (Cf. Feature: \"multi entries OFF\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST24(group) => FTR09-g\n [create scenarios where PMP + entries with A=0 (OFF) and with matching permissions\n - check no address + matching for those PMP entries]\n [create scenarios where all PMP entries + with A=0 (OFF) and with matching permissions\n - check no address matching + for all PMP entries]\n [check S or U mode access fails when all A=OFF with + at least one PMP entry implemented] => FTR09-g\nTST24-4 = extension of compatible + group(8) of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51,\n \ + \ \t\t\t\t\t\t\t\t\t\t\t TST17-13, TST17-23, TST17-33, TST17-43, + TST17-53,\n \t\t\t\t\t\t\t\t\t\t\t TST17-14, TST17-24, + TST17-34, TST17-44, TST17-54,\n \t\t\t\t\t\t\t\t\t + \t\t TST17-16, TST17-26, TST17-36, TST17-46, TST17-56,\n \ + \ \t\t\t\t\t\t\t\t\t\t\t TST18-14, TST18-24, TST18-34, TST18-44, + TST18-54, //TODO: M-mode may not raise an exception\n \ + \ \t\t\t\t\t\t\t\t\t\t\t TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) + //TODO: M-mode may not raise an exception\n //TODO: + SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51,\n \ + \ TST18-13, TST18-23, TST18-33, + TST18-43, TST18-53) ?\n[configure 8 PMP entries (highest-numbered ones first)\n\ + \ - execute the 8 kinds of accesses (if possible to chain due to access-fault)\n\ + \ - check 8 appropriate access-fault exceptions raised]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP025.yml b/verif/docs/VerifPlans/PMP/VP_IP025.yml new file mode 100644 index 00000000000..db3587a8b3b --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP025.yml @@ -0,0 +1,290 @@ +!Feature +next_elt_id: 6 +name: multi entries ALL +id: 25 +display_order: 25 +subfeatures: !!omap +- 000_1_entry: !Subfeature + name: 000_1_entry + tag: VP_PMP_F025_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F025_S001_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose a single PMP entry\n\nCONFIGURATION and ACCESS\n - + for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: + \"cfg NA4/NAPOT/TOR/OFF access S/U/M\")\n - make sure the pmp entries + address ranges are not overlapping/intersecting\n - NB: obviously, pmp + entry configurations with different mstatus.MPRV/MPP values cannot be mixed + in same test\n\nCHECK\n - for each pmp entry, we should obtain the expected + CHECK result\n\nREUSABILITY\n - if possible, the number of PMP entries + (N) is a configurable parameter\n - so a single test function can be + reused" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 001_2_isolated_entries: !Subfeature + name: 001_2_isolated_entries + tag: VP_PMP_F025_S002 + next_elt_id: 1 + display_order: 1 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F025_S002_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nreuse of VP_PMP_F025_S001_I000 feature + description (Cf. Feature: \"multi entries ALL\")" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +- 002_N_isolated_entries: !Subfeature + name: 002_N_isolated_entries + tag: VP_PMP_F025_S003 + next_elt_id: 1 + display_order: 2 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F025_S003_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any N PMP entries (2>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n [create + scenarios where 2 PMP entries with same pmpaddr\n - one without matching + permissions or with A=OFF\n - one with matching permissions and A=NA4/NAPOT/TOR\n\ + \ - any of them can be the lowest-numbered PMP entry]\nTST51-1\n[configure + 2 PMP entries\n - configure the lowest-numbered PMP entry with (TST11-12, + TST11-22, TST11-32, TST11-42, TST11-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22, + TST12-32, TST12-42, TST12-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n \ + \ TST13-12, TST13-22, TST13-32, TST13-42, + TST13-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-15, + TST13-25, TST13-35, TST13-45, TST13-55,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, TST14-52,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, TST14-25, + TST14-35, TST14-45, TST14-55,\n \ + \ TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, TST15-35, + TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, TST16-45, + TST16-55,\n TST17-12, + TST17-22, TST17-32, TST17-42, TST17-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, TST17-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, TST18-22, + TST18-32, TST18-42, TST18-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n - configure + the highest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, + TST11-51,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST11-14, + TST11-24, TST11-34, TST11-44, TST11-54,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST12-11, TST12-21, TST12-31, TST12-41, TST12-51,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-14, TST12-24, + TST12-34, TST12-44, TST12-54,\n \ + \ TST13-11, TST13-21, TST13-31, TST13-41, TST13-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST13-14, TST13-24, TST13-34, + TST13-44, TST13-54,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + \tTST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t\tTST14-14, TST14-24, TST14-34, TST14-44, + TST14-54,\n TST15-11, + TST15-21, TST15-31, TST15-41, TST15-51,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34, TST15-44, TST15-54,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-11, TST16-21, + TST16-31, TST16-41, TST16-51,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44, TST16-54)\n - execute + the associated access\n - check associated access-fault exception raised]" +- 005_2_intersecting_entries_succeed: !Subfeature + name: 005_2_intersecting_entries_succeed + tag: VP_PMP_F025_S006 + next_elt_id: 1 + display_order: 5 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F025_S006_I000 + description: "{Page 57 Section \"3.7.1 Physical Memory Protection CSRs\" Volume + II: RISC-V Privileged Architectures V20211203}\n\nUp to 64 PMP entries are + supported" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "choose any 2 PMP entries\n\nCONFIGURATION and ACCESS (Cf. Feature: + \"cfg NA4/NAPOT/TOR/OFF access S/U/M\")\n - for the least-numbered pmp + entry, apply any CONFIGURATION+ACCESS scenario without access-fault\n \ + \ - for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS + scenario with access-fault\n - make sure the pmp entries address ranges + are overlapping/intersecting (at least at 4 consecutive bytes)\n - for + each pmp entry, execute one access in its associated pmp address region + but outside the overlapping/intersecting address range\n - execute one + additional access inside the overlapping/intersecting address range\n \ + \ - NB: obviously, pmp entry configurations with different access-modes + (S/U vs. M) cannot be easily mixed in same test\n - NB: obviously, pmp + entry configurations with different mstatus.MPRV/MPP values cannot be mixed + in same test\n\nCHECK\n - for each pmp entry, access outside the overlapping/intersecting + address range should give the expected CHECK result\n - access inside + the overlapping/intersecting address range should not generate any access-fault\n\ + \nREUSABILITY\n - if possible, the number of PMP entries (N) is a configurable + parameter\n - so a single test function can be reused" + pfc: 3 + test_type: 4 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: "<< link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt + files (not up-to-date) : reading below not mandatory but may help for better + understanding >>\n\nTST51(group) => FTR09-a, FTR09-b and FTR09-c\n [create + scenarios where 2 PMP entries with same pmpaddr\n - one without matching + permissions or with A=OFF\n - one with matching permissions and A=NA4/NAPOT/TOR\n\ + \ - any of them can be the lowest-numbered PMP entry]\nTST51-2\n[configure + 2 PMP entries\n - configure the lowest-numbered PMP entry with (TST11-11, + TST11-21, TST11-31, TST11-41, TST11-51,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-14, TST11-24, TST11-34, TST11-44, TST11-54,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-11, TST12-21, + TST12-31, TST12-41, TST12-51,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-14, TST12-24, TST12-34, TST12-44, TST12-54,\n \ + \ TST13-11, TST13-21, TST13-31, TST13-41, + TST13-51,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST13-14, + TST13-24, TST13-34, TST13-44, TST13-54,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST14-11, TST14-21, TST14-31, TST14-41, TST14-51,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-14, TST14-24, + TST14-34, TST14-44, TST14-54,\n \ + \ TST15-11, TST15-21, TST15-31, TST15-41, TST15-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-14, TST15-24, TST15-34, + TST15-44, TST15-54,\n \t\t\t\t\t\t\t\t\t \t\t\t\t + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-14, TST16-24, TST16-34, TST16-44, + TST16-54)\n - configure the highest-numbered PMP entry with (TST11-12, + TST11-22, TST11-32, TST11-42, TST11-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST11-15, TST11-25, TST11-35, TST11-45, TST11-55,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST12-12, TST12-22, + TST12-32, TST12-42, TST12-52,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST12-15, TST12-25, TST12-35, TST12-45, TST12-55,\n \ + \ TST13-12, TST13-22, TST13-32, + TST13-42, TST13-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t\ + \ TST13-15, TST13-25, TST13-35, TST13-45, TST13-55,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-12, TST14-22, TST14-32, TST14-42, + TST14-52,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST14-15, + TST14-25, TST14-35, TST14-45, TST14-55,\n \ + \ TST15-12, TST15-22, TST15-32, TST15-42, TST15-52,\n\ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST15-15, TST15-25, + TST15-35, TST15-45, TST15-55,\n \t\t\t\t\t\t\t\t\t + \t\t\t\t TST16-12, TST16-22, TST16-32, TST16-42, TST16-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST16-15, TST16-25, TST16-35, + TST16-45, TST16-55,\n \ + \ TST17-12, TST17-22, TST17-32, TST17-42, TST17-52,\n \ + \ \t\t\t\t\t\t\t\t\t \t\t\t\t TST17-15, TST17-25, TST17-35, TST17-45, + TST17-55,\n \t\t\t\t\t\t\t\t\t \t\t\t\t TST18-12, + TST18-22, TST18-32, TST18-42, TST18-52,\n \t\t\t\t + \t\t\t\t\t \t\t\t\t TST18-15, TST18-25, TST18-35, TST18-45, TST18-55)\n\ + \ - execute the associated access\n - check no access-fault exception]" +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/VP_IP031.yml b/verif/docs/VerifPlans/PMP/VP_IP031.yml new file mode 100644 index 00000000000..45ff1790a9a --- /dev/null +++ b/verif/docs/VerifPlans/PMP/VP_IP031.yml @@ -0,0 +1,51 @@ +!Feature +next_elt_id: 1 +name: entry reconfiguration +id: 31 +display_order: 31 +subfeatures: !!omap +- 000_reconfigure_N_pmp_entries: !Subfeature + name: 000_reconfigure_N_pmp_entries + tag: VP_PMP_F031_S001 + next_elt_id: 1 + display_order: 0 + items: !!omap + - '000': !VerifItem + name: '000' + tag: VP_PMP_F031_S001_I000 + description: "reuse of feature descriptions (Cf. Feature: \"cfg NA4/NAPOT/TOR/OFF + access S/U/M\")\nreuse of feature descriptions (Cf. Feature: \"CSRs M-mode + only\")\nreuse of feature descriptions (Cf. Feature: \"CSRs locked access\"\ + )\nreuse of feature descriptions (Cf. Feature: \"multi entries NA4/NAPOT/TOR/OFF\"\ + )" + reqt_doc: '' + ref_mode: page + ref_page: '' + ref_section: '' + ref_viewer: firefox + verif_goals: "configure any N PMP entries, possibly some with L=1\n\nCONFIGURATION + and ACCESS\n - for each pmp entry, apply any CONFIGURATION+ACCESS scenario + above (Cf. Feature: \"cfg NA4/NAPOT/TOR/OFF access S/U/M\")\n - make + sure the pmp entries address ranges are not overlapping/intersecting\n \ + \ - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP + values cannot be mixed in same test\n\nRECONFIGURATION and ACCESS\n - + for each pmp entry with L=0, apply any other CONFIGURATION+ACCESS scenario + above (Cf. Feature: \"cfg NA4/NAPOT/TOR/OFF access S/U/M\")\n - make + sure the pmp entries address ranges are not overlapping/intersecting\n \ + \ - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP + values cannot be mixed in same test\n\nRESET\n - if there is any pmp + entry with L=1, apply hart reset (or only PMP reset if possible)\n - + and restart with CONFIGURATION and RESET\n\nCHECK\n - for each pmp entry, + we should obtain the expected CHECK result\n\nREUSABILITY\n - if possible, + the number of PMP entries (N) is a configurable parameter\n - so a single + test function can be reused" + pfc: 3 + test_type: 3 + cov_method: 1 + cores: -1 + coverage_loc: '' + comments: '' +vptool_gitrev: '$Id: a8b561f68549658061625891c533e7d45996bc9e $' +io_fmt_gitrev: '$Id: 61ab4e53ca49e21d56c416f0af0fa04d148e8001 $' +config_gitrev: '$Id: 5192fced2cfa10be5e18e827922e31e7489ed987 $' +ymlcfg_gitrev: '$Id: ce5e73bd5e8e0099334cb657afb7a624a99afbda $' diff --git a/verif/docs/VerifPlans/PMP/pmp_verif_plan.txt b/verif/docs/VerifPlans/PMP/pmp_verif_plan.txt new file mode 100644 index 00000000000..ea860b601c0 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/pmp_verif_plan.txt @@ -0,0 +1,1739 @@ +/////////////////////////////////////////////////////////////////////////////////// +INITIAL VERIF PLAN (cv32a6_embedded_copro): list of memory regions +/////////////////////////////////////////////////////////////////////////////////// + + + +Check no LSU Fault/Exception and correct access propagation +- LOAD+STORE allowed ahb_periph regions +- LOAD allowed D-scratchpad +- LOAD+STORE allowed I-scratchpad (preload mode) +- LOAD+STORE allowed D-$ +- LOAD+STORE system memory + +Check no FETCH Fault/Exception and correct access propagation +- FETCH allowed I-$ +- FETCH allowed I-scratchpad (functional mode) +- FETCH system memory + +Check LSU Fault/Exception and NO access propagation +- LOAD+STORE disabled ahb_periph (if enabling/disabling still specified) +- LOAD+STORE forbidden ahb_periph regions (if definable) +- LOAD+STORE disabled D-scratchpad (if enabling/disabling still specified) +- LOAD forbidden D-scratchpad (if definable) +- STORE D-scratchpad (maybe not PMP related, but structurally forbidden) +- LOAD+STORE disabled I-scratchpad (if enabling/disabling still specified) +- LOAD+STORE I-scratchpad (functional mode) (maybe not PMP related, but structurally forbidden) +- LOAD+STORE forbidden I-scratchpad (if definable) +- LOAD+STORE forbidden D-$ (if definable) +- LOAD+STORE I-$ (inexistent path) +- LOAD+STORE unallocated System Memory (inexistent path) + +Check FETCH Fault/Exception and NO access propagation +- FETCH forbidden I-$ (if definable) +- FETCH disabled I-scratchpad (if enabling/disabling still specified) +- FETCH I-scratchpad (preload mode) +- FETCH forbidden I-scratchpad (if definable) +- FETCH D-scratchpad (inexistent path) (not PMP related) +- FETCH ahb_periph (inexistent path) (not PMP related) +- FETCH unallocated System Memory (inexistent path) (not PMP related) + + + +/////////////////////////////////////////////////////////////////////////////////// +ADDITIONAL VERIF PLAN +/////////////////////////////////////////////////////////////////////////////////// + +[we assume there is only 1 hart in cv32a6] + +[we assume MXLEN is always 32bits] + +[we assume XLEN=MXLEN=32, so the PMP address registers are XLEN bits long, so no zero-extension needed] + +[we assume there is no region with hardwired privileges in PMP] + +[we assume the PMP granularity is 4 bytes (G=0)] + +[we assume there are 8 HW implemented PMP entries] + +[we assume no virtual memory is implemented] +[we assume page-based virtual memory is not implemented] + +[we assume the list of all physical memory regions] + - system memory regions + - I-$ + - D-$ + - I-scratchpad (preload mode) + - I-scratchpad (functional mode) + - D-scratchpad + - ahb_periph + +[check the role/definitions of mstatus.MPRV and mstatus.MPP later] //TODO + +[we assume an already written PMP entry (i) can be disabled + - if L=0, by clearing pmpcfg(i) + - if L=1, only by hart reset] + +//////////////////////////// + +TB01 => FTR01-h +[check that all violations are trapped at the processor] +[any time there is an access-fault type, check it matches the access-type] + +//TODO: TB02 +Determine how to use SV to factorize the similar tests + +//////////////////////////// + +TST01 (HIGH-PRIO) => FTR07-b +[determine the PMP granularity 2^(G+2) bytes by writing zero to pmp(0)cfg, then writing all ones to pmpaddr(0), then reading back pmpaddr(0). G is the index G of the least-significant bit set] + +TST02(group) => FTR02-d + [check that all 8 HW implemented PMP entries are writable/readable in M-mode (L=0)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=0)] + - random values may be used + - before any configuration (after hart reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero +TST02-1 (HIGH-PRIO) +[configure 1 PMP entry ([FTR02-b1]: maybe mandatorily the first one): with L=0, + - if possible, the PMP entry number is a configurable parameter + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +TST02-2 (LOW-PRIO) = 2 times reuse/call of TST02-1 +[configure 2 PMP entries ([FTR02-b1]: maybe mandatorily the 2 first ones): both with L=0, + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +TST02-3 (LOW-PRIO) = N times reuse/call of TST02-1 +[configure N PMP entries ([FTR02-b1]: maybe mandatorily the N first ones): all with L=0, + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +TST02-4 (HIGH-PRIO) = 8 times reuse/call of TST02-1 +[configure 8 PMP entries: all with L=0, + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] + +TST03(group) => FTR08-a and FTR08-b + [check that HW implemented PMP entries are not writable/readable in M-mode (L=1)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=1)] + - before any configuration, check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg and pmpaddr(i) maybe random values + - execute following tests specific checks + - check only hart reset unlocks all => FTR08-b + - check reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero +TST03-1 (HIGH-PRIO) +[configure 1 PMP entry ([FTR02-b1]: maybe mandatorily the first one): with L=1, + - if possible, the PMP entry number is a configurable parameter + - if possible, L value is a configurable parameter + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +TST03-2 (LOW-PRIO) = 2 times reuse/call of TST02-1 +[configure 2 PMP entries ([FTR02-b1]: maybe mandatorily the 2 first ones): both with L=1, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +TST03-3 (HIGH-PRIO) = 2 times reuse/call of TST02-1 +[configure 2 PMP entries ([FTR02-b1]: maybe mandatorily the 2 first ones): one with L=1 and one with L=0, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check locked PMP entry (i) has no effect on unlocked PMP entry (j) + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +TST03-4 (LOW-PRIO) = N times reuse/call of TST02-1 +[configure N PMP entries ([FTR02-b1]: maybe mandatorily the N first ones): at least one with L=1 and one with L=0, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check locked PMP entry (i) has no effect on unlocked PMP entry (j) + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +TST03-5 (HIGH-PRIO) = 8 times reuse/call of TST02-1 +[configure 8 PMP entries: at least one with L=1 and one with L=0, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check locked PMP entry (i) has no effect on unlocked PMP entry (j) + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] + +TST04 => FTR02-b1 and FTR02-b2 + [check if the lowest-numbered PMP CSRs must be programmed first before programming higher-numbered ones] +TST04-1 (LOW-PRIO) extends TST02-1 +[configure any PMP entry, but the first one + - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for not configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are M-mode read zero] +TST04-2 (HIGH-PRIO) extends TST02-2 +[configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for not configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are M-mode read zero] +TST04-3 (LOW-PRIO) extends TST02-3 +[configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for not configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are M-mode read zero] +TST04-4 (HIGH-PRIO) extends TST02-4 +[configure 8 PMP entries (highest-numbered ones first) + - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only] + +TST05 => FTR01-c and FTR01-c-extended + [check all regions are configurable in M-mode to make sure none is hardwired] + [regions hardwired privileges might only ever be visible in M-mode] +TST05-1 (HIGH-PRIO) extends TST02-4 + - check the written pmp(i)cfg and pmpaddr(i) values can be read exactly the same as written +TST05-2 (LOW-PRIO) extends TST03-5 + - check the written pmp(i)cfg and pmpaddr(i) values can be read exactly the same as written (before hart reset) + +TST06 => FTR04-a +[PMP CSR fields are WARL: PMP entry combinations with R=0 and W=1 are reserved/can’t be read] +[permissions fields could be randomly written; should we try randomization ?] +TST06-1 (HIGH-PRIO) extends TST02-4 + - write totally random values to pmp(i)cfg and pmpaddr(i) + - check all pmp(i)cfg and pmpaddr(i) can be read exactly the same as written except for the reserved combinations with R=0 and W=1 +TST06-2 (LOW-PRIO) extends TST03-5 + - write totally random values to pmp(i)cfg and pmpaddr(i) + - check all pmp(i)cfg and pmpaddr(i) can be read exactly the same as written except for the reserved combinations with R=0 and W=1 (before hart reset) + +//////////////////////////// + +TST10-1 (HIGH-PRIO) => FTR09-e +[check M-mode access succeeds if no PMP entry matches] +TST10-2 (HIGH-PRIO) => FTR09-e-question +[check M-mode access succeeds if no PMP entry defined] + +TST10-3 (HIGH-PRIO) => FTR09-f +[check S or U mode access fails when no PMP entry matching and at least one PMP entry implemented] +TST10-4 (HIGH-PRIO) => FTR09-f-question +[check S or U mode access fails when no PMP entry implemented] + +//////////////////////////// + +TST11-1x(group) => FTR01-d + [PMP check on instruction fetch where effective privilege mode is S or U: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in S and U mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST11-11 (HIGH-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +TST11-12 (MEDIUM-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check instruction fetch access-fault exception raised => FTR04-b] +TST11-13 (MEDIUM-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from outside all PMP defined regions + - check instruction fetch access-fault exception raised] +TST11-14 (LOW-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +TST11-15 (LOW-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check instruction fetch access-fault exception raised => FTR04-b] +TST11-16 (LOW-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from outside all PMP defined regions + - check instruction fetch access-fault exception raised] + +--------------------------- + +TST11-2x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST11-21 (HIGH-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST11-22 (MEDIUM-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +TST11-23 (MEDIUM-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check load access-fault exception raised] +TST11-24 (LOW-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST11-25 (LOW-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +TST11-26 (LOW-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check load access-fault exception raised] + +--------------------------- + +TST11-3x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST11-31 (HIGH-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST11-32 (MEDIUM-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +TST11-33 (MEDIUM-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check store access-fault exception raised] +TST11-34 (LOW-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST11-35 (LOW-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +TST11-36 (LOW-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check store access-fault exception raised] + +--------------------------- + +TST11-4x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST11-41 (LOWEST-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST11-42 (LOWEST-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +TST11-43 (LOWEST-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check load access-fault exception raised] +TST11-44 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST11-45 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +TST11-46 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check load access-fault exception raised] + +--------------------------- + +TST11-5x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST11-51 (LOWEST-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST11-52 (LOWEST-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +TST11-53 (LOWEST-PRIO) +[with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check store access-fault exception raised] +TST11-54 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST11-55 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +TST11-56 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check store access-fault exception raised] + +//////////////////////////// + +TST12-1x(group) => FTR01-f + [PMP check on instruction fetch where effective privilege mode is M: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in M mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST12-11 (LOW-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +TST12-12 (LOW-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1), + - configure the PMP entry without execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +TST12-13 (LOW-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +TST12-14 (HIGH-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +TST12-15 (MEDIUM-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check instruction fetch access-fault exception raised => FTR04-b] +TST12-16 (HIGH-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED + +--------------------------- + +TST12-2x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST12-21 (LOW-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST12-22 (LOW-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST12-23 (LOW-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +TST12-24 (HIGH-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST12-25 (MEDIUM-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +TST12-26 (HIGH-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED + +--------------------------- + +TST12-3x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST12-31 (LOW-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST12-32 (LOW-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST12-33 (LOW-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +TST12-34 (HIGH-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST12-35 (MEDIUM-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +TST12-36 (HIGH-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED + +--------------------------- + +TST12-4x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST12-41 (LOWEST-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST12-42 (LOWEST-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST12-43 (LOWEST-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +TST12-44 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +TST12-45 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +TST12-46 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED + +--------------------------- + +TST12-5x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST12-51 (LOWEST-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST12-52 (LOWEST-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST12-53 (LOWEST-PRIO) +[with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +TST12-54 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +TST12-55 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +TST12-56 (LOWEST-PRIO) +[with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED + +//////////////////////////// +//TODO: complete specificities for A=NAPOT + +TST13-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT] +TST13-11 (HIGH-PRIO) + [same as TST11-11(group), but with pmpcfg(i).A=NAPOT] +TST13-12 (MEDIUM-PRIO) + [same as TST11-12(group), but with pmpcfg(i).A=NAPOT] +TST13-13 (MEDIUM-PRIO) + [same as TST11-13(group), but with pmpcfg(i).A=NAPOT] +TST13-14 (LOW-PRIO) + [same as TST11-14(group), but with pmpcfg(i).A=NAPOT] +TST13-15 (LOW-PRIO) + [same as TST11-15(group), but with pmpcfg(i).A=NAPOT] +TST13-16 (LOW-PRIO) + [same as TST11-16(group), but with pmpcfg(i).A=NAPOT] + +--------------------------- + +TST13-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT] +TST13-21 (HIGH-PRIO) + [same as TST11-21(group), but with pmpcfg(i).A=NAPOT] +TST13-22 (MEDIUM-PRIO) + [same as TST11-22(group), but with pmpcfg(i).A=NAPOT] +TST13-23 (MEDIUM-PRIO) + [same as TST11-23(group), but with pmpcfg(i).A=NAPOT] +TST13-24 (LOW-PRIO) + [same as TST11-24(group), but with pmpcfg(i).A=NAPOT] +TST13-25 (LOW-PRIO) + [same as TST11-25(group), but with pmpcfg(i).A=NAPOT] +TST13-26 (LOW-PRIO) + [same as TST11-26(group), but with pmpcfg(i).A=NAPOT] + +--------------------------- + +TST13-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT] +TST13-31 (HIGH-PRIO) + [same as TST11-31(group), but with pmpcfg(i).A=NAPOT] +TST13-32 (MEDIUM-PRIO) + [same as TST11-32(group), but with pmpcfg(i).A=NAPOT] +TST13-33 (MEDIUM-PRIO) + [same as TST11-33(group), but with pmpcfg(i).A=NAPOT] +TST13-34 (LOW-PRIO) + [same as TST11-34(group), but with pmpcfg(i).A=NAPOT] +TST13-35 (LOW-PRIO) + [same as TST11-35(group), but with pmpcfg(i).A=NAPOT] +TST13-36 (LOW-PRIO) + [same as TST11-36(group), but with pmpcfg(i).A=NAPOT] + +--------------------------- + +TST13-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT] +TST13-41 (LOWEST-PRIO) + [same as TST11-41(group), but with pmpcfg(i).A=NAPOT] +TST13-42 (LOWEST-PRIO) + [same as TST11-42(group), but with pmpcfg(i).A=NAPOT] +TST13-43 (LOWEST-PRIO) + [same as TST11-43(group), but with pmpcfg(i).A=NAPOT] +TST13-44 (LOWEST-PRIO) + [same as TST11-44(group), but with pmpcfg(i).A=NAPOT] +TST13-45 (LOWEST-PRIO) + [same as TST11-45(group), but with pmpcfg(i).A=NAPOT] +TST13-46 (LOWEST-PRIO) + [same as TST11-46(group), but with pmpcfg(i).A=NAPOT] + +--------------------------- + +TST13-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT] +TST13-51 (LOWEST-PRIO) + [same as TST11-51(group), but with pmpcfg(i).A=NAPOT] +TST13-52 (LOWEST-PRIO) + [same as TST11-52(group), but with pmpcfg(i).A=NAPOT] +TST13-53 (LOWEST-PRIO) + [same as TST11-53(group), but with pmpcfg(i).A=NAPOT] +TST13-54 (LOWEST-PRIO) + [same as TST11-54(group), but with pmpcfg(i).A=NAPOT] +TST13-55 (LOWEST-PRIO) + [same as TST11-55(group), but with pmpcfg(i).A=NAPOT] +TST13-56 (LOWEST-PRIO) + [same as TST11-56(group), but with pmpcfg(i).A=NAPOT] + +//////////////////////////// + +TST14-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT] +TST14-11 (LOW-PRIO) + [same as TST12-11(group), but with pmpcfg(i).A=NAPOT] +TST14-12 (LOW-PRIO) + [same as TST12-12(group), but with pmpcfg(i).A=NAPOT] +TST14-13 (LOW-PRIO) + [same as TST12-13(group), but with pmpcfg(i).A=NAPOT] +TST14-14 (HIGH-PRIO) + [same as TST12-14(group), but with pmpcfg(i).A=NAPOT] +TST14-15 (MEDIUM-PRIO) + [same as TST12-15(group), but with pmpcfg(i).A=NAPOT] +TST14-16 (HIGH-PRIO) + [same as TST12-16(group), but with pmpcfg(i).A=NAPOT] + +--------------------------- + +TST14-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT] +TST14-21 (LOW-PRIO) + [same as TST12-21(group), but with pmpcfg(i).A=NAPOT] +TST14-22 (LOW-PRIO) + [same as TST12-22(group), but with pmpcfg(i).A=NAPOT] +TST14-23 (LOW-PRIO) + [same as TST12-23(group), but with pmpcfg(i).A=NAPOT] +TST14-24 (HIGH-PRIO) + [same as TST12-24(group), but with pmpcfg(i).A=NAPOT] +TST14-25 (MEDIUM-PRIO) + [same as TST12-25(group), but with pmpcfg(i).A=NAPOT] +TST14-26 (HIGH-PRIO) + [same as TST12-26(group), but with pmpcfg(i).A=NAPOT] + +--------------------------- + +TST14-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT] +TST14-31 (LOW-PRIO) + [same as TST12-31(group), but with pmpcfg(i).A=NAPOT] +TST14-32 (LOW-PRIO) + [same as TST12-32(group), but with pmpcfg(i).A=NAPOT] +TST14-33 (LOW-PRIO) + [same as TST12-33(group), but with pmpcfg(i).A=NAPOT] +TST14-34 (HIGH-PRIO) + [same as TST12-34(group), but with pmpcfg(i).A=NAPOT] +TST14-35 (MEDIUM-PRIO) + [same as TST12-35(group), but with pmpcfg(i).A=NAPOT] +TST14-36 (HIGH-PRIO) + [same as TST12-36(group), but with pmpcfg(i).A=NAPOT] + +--------------------------- + +TST14-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT] +TST14-41 (LOWEST-PRIO) + [same as TST12-41(group), but with pmpcfg(i).A=NAPOT] +TST14-42 (LOWEST-PRIO) + [same as TST12-42(group), but with pmpcfg(i).A=NAPOT] +TST14-43 (LOWEST-PRIO) + [same as TST12-43(group), but with pmpcfg(i).A=NAPOT] +TST14-44 (LOWEST-PRIO) + [same as TST12-44(group), but with pmpcfg(i).A=NAPOT] +TST14-45 (LOWEST-PRIO) + [same as TST12-45(group), but with pmpcfg(i).A=NAPOT] +TST14-46 (LOWEST-PRIO) + [same as TST12-46(group), but with pmpcfg(i).A=NAPOT] + +--------------------------- + +TST14-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT] +TST14-51 (LOWEST-PRIO) + [same as TST12-51(group), but with pmpcfg(i).A=NAPOT] +TST14-52 (LOWEST-PRIO) + [same as TST12-52(group), but with pmpcfg(i).A=NAPOT] +TST14-53 (LOWEST-PRIO) + [same as TST12-53(group), but with pmpcfg(i).A=NAPOT] +TST14-54 (LOWEST-PRIO) + [same as TST12-54(group), but with pmpcfg(i).A=NAPOT] +TST14-55 (LOWEST-PRIO) + [same as TST12-55(group), but with pmpcfg(i).A=NAPOT] +TST14-56 (LOWEST-PRIO) + [same as TST12-56(group), but with pmpcfg(i).A=NAPOT] + +//////////////////////////// +//TODO: complete specificities for A=TOR + +TST15-1x(group) => FTR06-a + [same as TST11-1x(group), but with pmpcfg(i).A=TOR] +TST15-11 (HIGH-PRIO) + [same as TST11-11(group), but with pmpcfg(i).A=TOR] +TST15-12 (MEDIUM-PRIO) + [same as TST11-12(group), but with pmpcfg(i).A=TOR] +TST15-13 (MEDIUM-PRIO) + [same as TST11-13(group), but with pmpcfg(i).A=TOR] +TST15-14 (LOW-PRIO) + [same as TST11-14(group), but with pmpcfg(i).A=TOR] +TST15-15 (LOW-PRIO) + [same as TST11-15(group), but with pmpcfg(i).A=TOR] +TST15-16 (LOW-PRIO) + [same as TST11-16(group), but with pmpcfg(i).A=TOR] + +--------------------------- + +TST15-2x(group) => FTR06-a + [same as TST11-2x(group), but with pmpcfg(i).A=TOR] +TST15-21 (HIGH-PRIO) + [same as TST11-21(group), but with pmpcfg(i).A=TOR] +TST15-22 (MEDIUM-PRIO) + [same as TST11-22(group), but with pmpcfg(i).A=TOR] +TST15-23 (MEDIUM-PRIO) + [same as TST11-23(group), but with pmpcfg(i).A=TOR] +TST15-24 (LOW-PRIO) + [same as TST11-24(group), but with pmpcfg(i).A=TOR] +TST15-25 (LOW-PRIO) + [same as TST11-25(group), but with pmpcfg(i).A=TOR] +TST15-26 (LOW-PRIO) + [same as TST11-26(group), but with pmpcfg(i).A=TOR] + +--------------------------- + +TST15-3x(group) => FTR06-a + [same as TST11-3x(group), but with pmpcfg(i).A=TOR] +TST15-31 (HIGH-PRIO) + [same as TST11-31(group), but with pmpcfg(i).A=TOR] +TST15-32 (MEDIUM-PRIO) + [same as TST11-32(group), but with pmpcfg(i).A=TOR] +TST15-33 (MEDIUM-PRIO) + [same as TST11-33(group), but with pmpcfg(i).A=TOR] +TST15-34 (LOW-PRIO) + [same as TST11-34(group), but with pmpcfg(i).A=TOR] +TST15-35 (LOW-PRIO) + [same as TST11-35(group), but with pmpcfg(i).A=TOR] +TST15-36 (LOW-PRIO) + [same as TST11-36(group), but with pmpcfg(i).A=TOR] + +--------------------------- + +TST15-4x(group) => FTR06-a + [same as TST11-4x(group), but with pmpcfg(i).A=TOR] +TST15-41 (LOWEST-PRIO) + [same as TST11-41(group), but with pmpcfg(i).A=TOR] +TST15-42 (LOWEST-PRIO) + [same as TST11-42(group), but with pmpcfg(i).A=TOR] +TST15-43 (LOWEST-PRIO) + [same as TST11-43(group), but with pmpcfg(i).A=TOR] +TST15-44 (LOWEST-PRIO) + [same as TST11-44(group), but with pmpcfg(i).A=TOR] +TST15-45 (LOWEST-PRIO) + [same as TST11-45(group), but with pmpcfg(i).A=TOR] +TST15-46 (LOWEST-PRIO) + [same as TST11-46(group), but with pmpcfg(i).A=TOR] + +--------------------------- + +TST15-5x(group) => FTR06-a + [same as TST11-5x(group), but with pmpcfg(i).A=TOR] +TST15-51 (LOWEST-PRIO) + [same as TST11-51(group), but with pmpcfg(i).A=TOR] +TST15-52 (LOWEST-PRIO) + [same as TST11-52(group), but with pmpcfg(i).A=TOR] +TST15-53 (LOWEST-PRIO) + [same as TST11-53(group), but with pmpcfg(i).A=TOR] +TST15-54 (LOWEST-PRIO) + [same as TST11-54(group), but with pmpcfg(i).A=TOR] +TST15-55 (LOWEST-PRIO) + [same as TST11-55(group), but with pmpcfg(i).A=TOR] +TST15-56 (LOWEST-PRIO) + [same as TST11-56(group), but with pmpcfg(i).A=TOR] + +//////////////////////////// + +TST16-1x(group) => FTR06-a + [same as TST12-1x(group), but with pmpcfg(i).A=TOR] +TST16-11 (LOW-PRIO) + [same as TST12-11(group), but with pmpcfg(i).A=TOR] +TST16-12 (LOW-PRIO) + [same as TST12-12(group), but with pmpcfg(i).A=TOR] +TST16-13 (LOW-PRIO) + [same as TST12-13(group), but with pmpcfg(i).A=TOR] +TST16-14 (HIGH-PRIO) + [same as TST12-14(group), but with pmpcfg(i).A=TOR] +TST16-15 (MEDIUM-PRIO) + [same as TST12-15(group), but with pmpcfg(i).A=TOR] +TST16-16 (HIGH-PRIO) + [same as TST12-16(group), but with pmpcfg(i).A=TOR] + +--------------------------- + +TST16-2x(group) => FTR06-a + [same as TST12-2x(group), but with pmpcfg(i).A=TOR] +TST16-21 (LOW-PRIO) + [same as TST12-21(group), but with pmpcfg(i).A=TOR] +TST16-22 (LOW-PRIO) + [same as TST12-22(group), but with pmpcfg(i).A=TOR] +TST16-23 (LOW-PRIO) + [same as TST12-23(group), but with pmpcfg(i).A=TOR] +TST16-24 (HIGH-PRIO) + [same as TST12-24(group), but with pmpcfg(i).A=TOR] +TST16-25 (MEDIUM-PRIO) + [same as TST12-25(group), but with pmpcfg(i).A=TOR] +TST16-26 (HIGH-PRIO) + [same as TST12-26(group), but with pmpcfg(i).A=TOR] + +--------------------------- + +TST16-3x(group) => FTR06-a + [same as TST12-3x(group), but with pmpcfg(i).A=TOR] +TST16-31 (LOW-PRIO) + [same as TST12-31(group), but with pmpcfg(i).A=TOR] +TST16-32 (LOW-PRIO) + [same as TST12-32(group), but with pmpcfg(i).A=TOR] +TST16-33 (LOW-PRIO) + [same as TST12-33(group), but with pmpcfg(i).A=TOR] +TST16-34 (HIGH-PRIO) + [same as TST12-34(group), but with pmpcfg(i).A=TOR] +TST16-35 (MEDIUM-PRIO) + [same as TST12-35(group), but with pmpcfg(i).A=TOR] +TST16-36 (HIGH-PRIO) + [same as TST12-36(group), but with pmpcfg(i).A=TOR] + +--------------------------- + +TST16-4x(group) => FTR06-a + [same as TST12-4x(group), but with pmpcfg(i).A=TOR] +TST16-41 (LOWEST-PRIO) + [same as TST12-41(group), but with pmpcfg(i).A=TOR] +TST16-42 (LOWEST-PRIO) + [same as TST12-42(group), but with pmpcfg(i).A=TOR] +TST16-43 (LOWEST-PRIO) + [same as TST12-43(group), but with pmpcfg(i).A=TOR] +TST16-44 (LOWEST-PRIO) + [same as TST12-44(group), but with pmpcfg(i).A=TOR] +TST16-45 (LOWEST-PRIO) + [same as TST12-45(group), but with pmpcfg(i).A=TOR] +TST16-46 (LOWEST-PRIO) + [same as TST12-46(group), but with pmpcfg(i).A=TOR] + +--------------------------- + +TST16-5x(group) => FTR06-a + [same as TST12-5x(group), but with pmpcfg(i).A=TOR] +TST16-51 (LOWEST-PRIO) + [same as TST12-51(group), but with pmpcfg(i).A=TOR] +TST16-52 (LOWEST-PRIO) + [same as TST12-52(group), but with pmpcfg(i).A=TOR] +TST16-53 (LOWEST-PRIO) + [same as TST12-53(group), but with pmpcfg(i).A=TOR] +TST16-54 (LOWEST-PRIO) + [same as TST12-54(group), but with pmpcfg(i).A=TOR] +TST16-55 (LOWEST-PRIO) + [same as TST12-55(group), but with pmpcfg(i).A=TOR] +TST16-56 (LOWEST-PRIO) + [same as TST12-56(group), but with pmpcfg(i).A=TOR] + +//////////////////////////// +//TODO: complete specificities for A=OFF + +TST17-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=OFF] +TST17-11 (HIGH-PRIO) + [same as TST11-11(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +TST17-12 (MEDIUM-PRIO) + [same as TST11-12(group), but with pmpcfg(i).A=OFF] +TST17-13 (MEDIUM-PRIO) + [same as TST11-13(group), but with pmpcfg(i).A=OFF] +TST17-14 (LOW-PRIO) + [same as TST11-14(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +TST17-15 (LOW-PRIO) + [same as TST11-15(group), but with pmpcfg(i).A=OFF] +TST17-16 (LOW-PRIO) + [same as TST11-16(group), but with pmpcfg(i).A=OFF] + +--------------------------- + +TST17-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=OFF] +TST17-21 (HIGH-PRIO) + [same as TST11-21(group), but with pmpcfg(i).A=OFF + - check load access-fault exception raised] +TST17-22 (MEDIUM-PRIO) + [same as TST11-22(group), but with pmpcfg(i).A=OFF] +TST17-23 (MEDIUM-PRIO) + [same as TST11-23(group), but with pmpcfg(i).A=OFF] +TST17-24 (LOW-PRIO) + [same as TST11-24(group), but with pmpcfg(i).A=OFF + - check load access-fault exception raised] +TST17-25 (LOW-PRIO) + [same as TST11-25(group), but with pmpcfg(i).A=OFF] +TST17-26 (LOW-PRIO) + [same as TST11-26(group), but with pmpcfg(i).A=OFF] + +--------------------------- + +TST17-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=OFF] +TST17-31 (HIGH-PRIO) + [same as TST11-31(group), but with pmpcfg(i).A=OFF + - check store access-fault exception raised] +TST17-32 (MEDIUM-PRIO) + [same as TST11-32(group), but with pmpcfg(i).A=OFF] +TST17-33 (MEDIUM-PRIO) + [same as TST11-33(group), but with pmpcfg(i).A=OFF] +TST17-34 (LOW-PRIO) + [same as TST11-34(group), but with pmpcfg(i).A=OFF + - check store access-fault exception raised] +TST17-35 (LOW-PRIO) + [same as TST11-35(group), but with pmpcfg(i).A=OFF] +TST17-36 (LOW-PRIO) + [same as TST11-36(group), but with pmpcfg(i).A=OFF] + +--------------------------- + +TST17-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=OFF] +TST17-41 (LOWEST-PRIO) + [same as TST11-41(group), but with pmpcfg(i).A=OFF + - check load access-fault exception raised] +TST17-42 (LOWEST-PRIO) + [same as TST11-42(group), but with pmpcfg(i).A=OFF] +TST17-43 (LOWEST-PRIO) + [same as TST11-43(group), but with pmpcfg(i).A=OFF] +TST17-44 (LOWEST-PRIO) + [same as TST11-44(group), but with pmpcfg(i).A=OFF + - check load access-fault exception raised] +TST17-45 (LOWEST-PRIO) + [same as TST11-45(group), but with pmpcfg(i).A=OFF] +TST17-46 (LOWEST-PRIO) + [same as TST11-46(group), but with pmpcfg(i).A=OFF] + +--------------------------- + +TST17-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=OFF] +TST17-51 (LOWEST-PRIO) + [same as TST11-51(group), but with pmpcfg(i).A=OFF + - check store access-fault exception raised] +TST17-52 (LOWEST-PRIO) + [same as TST11-52(group), but with pmpcfg(i).A=OFF] +TST17-53 (LOWEST-PRIO) + [same as TST11-53(group), but with pmpcfg(i).A=OFF] +TST17-54 (LOWEST-PRIO) + [same as TST11-54(group), but with pmpcfg(i).A=OFF + - check store access-fault exception raised] +TST17-55 (LOWEST-PRIO) + [same as TST11-55(group), but with pmpcfg(i).A=OFF] +TST17-56 (LOWEST-PRIO) + [same as TST11-56(group), but with pmpcfg(i).A=OFF] + +//////////////////////////// + +TST18-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=OFF] +TST18-11 (LOW-PRIO) + [same as TST12-11(group), but with pmpcfg(i).A=OFF] +TST18-12 (LOW-PRIO) + [same as TST12-12(group), but with pmpcfg(i).A=OFF] +TST18-13 (LOW-PRIO) + [same as TST12-13(group), but with pmpcfg(i).A=OFF] +TST18-14 (HIGH-PRIO) + [same as TST12-14(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +TST18-15 (MEDIUM-PRIO) + [same as TST12-15(group), but with pmpcfg(i).A=OFF] +TST18-16 (HIGH-PRIO) + [same as TST12-16(group), but with pmpcfg(i).A=OFF] + +--------------------------- + +TST18-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=OFF] +TST18-21 (LOW-PRIO) + [same as TST12-21(group), but with pmpcfg(i).A=OFF] +TST18-22 (LOW-PRIO) + [same as TST12-22(group), but with pmpcfg(i).A=OFF] +TST18-23 (LOW-PRIO) + [same as TST12-23(group), but with pmpcfg(i).A=OFF] +TST18-24 (HIGH-PRIO) + [same as TST12-24(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +TST18-25 (MEDIUM-PRIO) + [same as TST12-25(group), but with pmpcfg(i).A=OFF] +TST18-26 (HIGH-PRIO) + [same as TST12-26(group), but with pmpcfg(i).A=OFF] + +--------------------------- + +TST18-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=OFF] +TST18-31 (LOW-PRIO) + [same as TST12-31(group), but with pmpcfg(i).A=OFF] +TST18-32 (LOW-PRIO) + [same as TST12-32(group), but with pmpcfg(i).A=OFF] +TST18-33 (LOW-PRIO) + [same as TST12-33(group), but with pmpcfg(i).A=OFF] +TST18-34 (HIGH-PRIO) + [same as TST12-34(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +TST18-35 (MEDIUM-PRIO) + [same as TST12-35(group), but with pmpcfg(i).A=OFF] +TST18-36 (HIGH-PRIO) + [same as TST12-36(group), but with pmpcfg(i).A=OFF] + +--------------------------- + +TST18-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=OFF] +TST18-41 (LOWEST-PRIO) + [same as TST12-41(group), but with pmpcfg(i).A=OFF] +TST18-42 (LOWEST-PRIO) + [same as TST12-42(group), but with pmpcfg(i).A=OFF] +TST18-43 (LOWEST-PRIO) + [same as TST12-43(group), but with pmpcfg(i).A=OFF] +TST18-44 (LOWEST-PRIO) + [same as TST12-44(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +TST18-45 (LOWEST-PRIO) + [same as TST12-45(group), but with pmpcfg(i).A=OFF] +TST18-46 (LOWEST-PRIO) + [same as TST12-46(group), but with pmpcfg(i).A=OFF] + +--------------------------- + +TST18-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=OFF] +TST18-51 (LOWEST-PRIO) + [same as TST12-51(group), but with pmpcfg(i).A=OFF] +TST18-52 (LOWEST-PRIO) + [same as TST12-52(group), but with pmpcfg(i).A=OFF] +TST18-53 (LOWEST-PRIO) + [same as TST12-53(group), but with pmpcfg(i).A=OFF] +TST18-54 (LOWEST-PRIO) + [same as TST12-54(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +TST18-55 (LOWEST-PRIO) + [same as TST12-55(group), but with pmpcfg(i).A=OFF] +TST18-56 (LOWEST-PRIO) + [same as TST12-56(group), but with pmpcfg(i).A=OFF] + +//////////////////////////// + +TST21(group) + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] +TST21-1 = extension of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-13, TST11-23, TST11-33, TST11-43, TST11-53, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST11-16, TST11-26, TST11-36, TST11-46, TST11-56, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-13, TST12-23, TST12-33, TST12-43, TST12-53, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST12-16, TST12-26, TST12-36, TST12-46, TST12-56) +[configure only one (any, but the first one) PMP entry + - use A=NA4 for the PMP entry configuration + - execute the chosen kind of access + - should be same result] +TST21-2 = extension of compatible pair of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-13, TST11-23, TST11-33, TST11-43, TST11-53, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST11-16, TST11-26, TST11-36, TST11-46, TST11-56, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-13, TST12-23, TST12-33, TST12-43, TST12-53, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST12-16, TST12-26, TST12-36, TST12-46, TST12-56) +[configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - use A=NA4 for each PMP entry configuration + - execute the 2 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 2 results] +TST21-3 = extension of compatible group(N) of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-13, TST11-23, TST11-33, TST11-43, TST11-53, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST11-16, TST11-26, TST11-36, TST11-46, TST11-56, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-13, TST12-23, TST12-33, TST12-43, TST12-53, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST12-16, TST12-26, TST12-36, TST12-46, TST12-56) +[configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - use A=NA4 for each PMP entry configuration + - execute the N kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same N results] +TST21-4 = extension of compatible group(8) of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-13, TST11-23, TST11-33, TST11-43, TST11-53, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST11-16, TST11-26, TST11-36, TST11-46, TST11-56, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-13, TST12-23, TST12-33, TST12-43, TST12-53, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST12-16, TST12-26, TST12-36, TST12-46, TST12-56) +[configure 8 PMP entries (highest-numbered ones first) + - use A=NA4 for each PMP entry configuration + - execute the 8 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 8 results] + +--------------------------- + +TST22(group) + [create scenarios where PMP entries with A=3 (NAPOT) and with/without matching permissions + - check only NAPOT defined addresses are matching] +TST22-1 = extension of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-13, TST13-23, TST13-33, TST13-43, TST13-53, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST13-16, TST13-26, TST13-36, TST13-46, TST13-56, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-13, TST14-23, TST14-33, TST14-43, TST14-53, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST14-16, TST14-26, TST14-36, TST14-46, TST14-56) +[configure only one (any, but the first one) PMP entry + - use A=NAPOT for the PMP entry configuration + - execute the chosen kind of access + - should be same result] +TST22-2 = extension of compatible pair of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-13, TST13-23, TST13-33, TST13-43, TST13-53, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST13-16, TST13-26, TST13-36, TST13-46, TST13-56, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-13, TST14-23, TST14-33, TST14-43, TST14-53, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST14-16, TST14-26, TST14-36, TST14-46, TST14-56) +[configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - use A=NAPOT for each PMP entry configuration + - execute the 2 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 2 results] +TST22-3 = extension of compatible group(N) of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-13, TST13-23, TST13-33, TST13-43, TST13-53, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST13-16, TST13-26, TST13-36, TST13-46, TST13-56, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-13, TST14-23, TST14-33, TST14-43, TST14-53, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST14-16, TST14-26, TST14-36, TST14-46, TST14-56) +[configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - use A=NAPOT for each PMP entry configuration + - execute the N kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same N results] +TST22-4 = extension of compatible group(8) of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-13, TST13-23, TST13-33, TST13-43, TST13-53, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST13-16, TST13-26, TST13-36, TST13-46, TST13-56, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-13, TST14-23, TST14-33, TST14-43, TST14-53, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST14-16, TST14-26, TST14-36, TST14-46, TST14-56) +[configure 8 PMP entries (highest-numbered ones first) + - use A=NAPOT for each PMP entry configuration + - execute the 8 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 8 results] + +--------------------------- + +TST23(group) => + [create scenarios where PMP entries with A=1 (TOR) and with/without matching permissions + - pmpaddr(i−1) < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions + - check only TOR defined addresses are matching] +TST23-1 = extension of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-13, TST15-23, TST15-33, TST15-43, TST15-53, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST15-16, TST15-26, TST15-36, TST15-46, TST15-56, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-13, TST16-23, TST16-33, TST16-43, TST16-53, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST16-16, TST16-26, TST16-36, TST16-46, TST16-56) +[configure only one (any, but the first one) PMP entry + - execute the chosen kind of access + - should be same result] +TST23-2 = extension of compatible pair of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-13, TST15-23, TST15-33, TST15-43, TST15-53, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST15-16, TST15-26, TST15-36, TST15-46, TST15-56, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-13, TST16-23, TST16-33, TST16-43, TST16-53, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST16-16, TST16-26, TST16-36, TST16-46, TST16-56) +[configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - execute the 2 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 2 results] +TST23-3 = extension of compatible group(N) of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-13, TST15-23, TST15-33, TST15-43, TST15-53, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST15-16, TST15-26, TST15-36, TST15-46, TST15-56, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-13, TST16-23, TST16-33, TST16-43, TST16-53, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST16-16, TST16-26, TST16-36, TST16-46, TST16-56) +[configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - execute the N kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same N results] +TST23-4 = extension of compatible group(8) of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-13, TST15-23, TST15-33, TST15-43, TST15-53, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST15-16, TST15-26, TST15-36, TST15-46, TST15-56, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-13, TST16-23, TST16-33, TST16-43, TST16-53, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST16-16, TST16-26, TST16-36, TST16-46, TST16-56) +[configure 8 PMP entries (highest-numbered ones first) + - execute the 8 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 8 results] + +--------------------------- + +TST24(group) => FTR09-g + [create scenarios where PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for those PMP entries] + [create scenarios where all PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for all PMP entries] + [check S or U mode access fails when all A=OFF with at least one PMP entry implemented] => FTR09-g +TST24-1 = extension of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-13, TST17-23, TST17-33, TST17-43, TST17-53, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST17-16, TST17-26, TST17-36, TST17-46, TST17-56, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an exception + TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO: M-mode may not raise an exception + //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-13, TST18-23, TST18-33, TST18-43, TST18-53) ? +[configure only one (any, but the first one) PMP entry + - execute the chosen kind of access + - check appropriate access-fault exception raised] +TST24-2 = extension of compatible pair of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-13, TST17-23, TST17-33, TST17-43, TST17-53, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST17-16, TST17-26, TST17-36, TST17-46, TST17-56, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an exception + TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO: M-mode may not raise an exception + //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-13, TST18-23, TST18-33, TST18-43, TST18-53) ? +[configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - execute the 2 kinds of accesses (if possible to chain due to access-fault) + - check 2 appropriate access-fault exceptions raised] +TST24-3 = extension of compatible group(N) of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-13, TST17-23, TST17-33, TST17-43, TST17-53, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST17-16, TST17-26, TST17-36, TST17-46, TST17-56, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an exception + TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO: M-mode may not raise an exception + //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-13, TST18-23, TST18-33, TST18-43, TST18-53) ? +[configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - execute the N kinds of accesses (if possible to chain due to access-fault) + - check N appropriate access-fault exceptions raised] +TST24-4 = extension of compatible group(8) of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-13, TST17-23, TST17-33, TST17-43, TST17-53, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST17-16, TST17-26, TST17-36, TST17-46, TST17-56, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an exception + TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO: M-mode may not raise an exception + //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-13, TST18-23, TST18-33, TST18-43, TST18-53) ? +[configure 8 PMP entries (highest-numbered ones first) + - execute the 8 kinds of accesses (if possible to chain due to access-fault) + - check 8 appropriate access-fault exceptions raised] + +--------------------------- + +//TO COMPLETE => FTR06-b +TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 +TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + +//TO COMPLETE => FTR06-c +TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] + +//////////////////////////// + +TST31(group) => FTR08-a and FTR08-b + [create scenario where L=0 for PMP entry (i) + - check pmp(i)cfg and pmpaddr(i) are writable in M-mode only] + [create scenario where L=1 for PMP entry (i) + - check pmp(i)cfg and pmpaddr(i) are effectively locked whatever the mode] + [create scenario where PMP entries are locked L=1 + - check only the hart reset unlocks all PMP entries + - execute following tests specific checks + - check only hart reset unlocks all => FTR08-b + - check reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero] +TST31-1 = extension of (TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54) +[configure only one ([FTR02-b1]: maybe mandatorily the 1st) PMP entry: with L=1 + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a] +TST31-2 = extension of compatible pair of (TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54) +[configure 2 PMP entries ([FTR02-b1]: maybe mandatorily the 2 first ones): both with L=1 + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a] +TST31-3 = extension of compatible pair of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54) +[configure 2 PMP entries ([FTR02-b1]: maybe mandatorily the 2 first ones): one with L=1 and the other with L=0, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check locked PMP entry (i) has no effect on unlocked PMP entry (j) + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only] +TST31-4 = extension of compatible group(N) of (TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54) +[configure N PMP entries ([FTR02-b1]: maybe mandatorily the N first ones): all with L=1 + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a] +TST31-5 = extension of compatible group(N) of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54) +[configure N PMP entries ([FTR02-b1]: maybe mandatorily the N first ones): at least one with L=1 and one with L=0, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check locked PMP entry (i) has no effect on unlocked PMP entry (j) + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only] +TST31-6 = extension of compatible group(8) of (TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54) +[configure 8 PMP entries: all with L=1 + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a] +TST31-7 = extension of compatible group(8) of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54) +[configure 8 PMP entries: at least one with L=1 and one with L=0, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check locked PMP entry (i) has no effect on unlocked PMP entry (j) + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only] + +--------------------------- + +TST32(group) => FTR08-a and FTR08-b + [create scenario where pmp(i)cfg.L=1 and pmp(i)cfg.A=NAPOT for PMP entry (i)] +TST32-1 = same as TST31-1 but with extension of (TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54) +TST32-2 = same as TST31-2 but with extension of (TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54) +TST32-3 = same as TST31-3 but with extension of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54) +TST32-4 = same as TST31-4 but with extension of (TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54) +TST32-5 = same as TST31-5 but with extension of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54) +TST32-6 = same as TST31-6 but with extension of (TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54) +TST32-7 = same as TST31-7 but with extension of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54) + +--------------------------- + +TST33(group) => FTR08-a and FTR08-b + [create scenario where pmp(i)cfg.L=1 and pmp(i)cfg.A=TOR for PMP entry (i) + - additionally, check writes to pmpaddr(i-1) are ignored] +TST33-1 = same as TST31-1 but with extension of (TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) +TST33-2 = same as TST31-2 but with extension of (TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) +TST33-3 = same as TST31-3 but with extension of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) +TST33-4 = same as TST31-4 but with extension of (TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) +TST33-5 = same as TST31-5 but with extension of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) +TST33-6 = same as TST31-6 but with extension of (TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) +TST33-7 = same as TST31-7 but with extension of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + +--------------------------- + +TST34(group) => FTR08-a and FTR08-b + [create scenario where pmp(i)cfg.A=OFF, then pmp(i)cfg.L=1 for PMP entry (i) + - check writes to pmp(i)cfg are ignored] +TST34-1 = same as TST31-1 but with extension of (TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54) +TST34-2 = same as TST31-2 but with extension of (TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54) +TST34-3 = same as TST31-3 but with extension of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54) +TST34-4 = same as TST31-4 but with extension of (TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54) +TST34-5 = same as TST31-5 but with extension of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54) +TST34-6 = same as TST31-6 but with extension of (TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54) +TST34-7 = same as TST31-7 but with extension of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54) + +--------------------------- + +TST39(group) => FTR08-a and FTR08-b + [create scenario where pmp(i)cfg.L=1 and pmp(i)cfg.A=NA4/NAPOT/TOR/OFF for PMP entry (i)] +TST39-1 = same as TST31-1 but with extension of (TST1*-14, TST1*-24, TST1*-34, TST1*-44, TST1*-54) +TST39-2 = same as TST31-2 but with extension of (TST1*-14, TST1*-24, TST1*-34, TST1*-44, TST1*-54) +TST39-3 = same as TST31-3 but with extension of (TST1*-11, TST1*-21, TST1*-31, TST1*-41, TST1*-51, + TST1*-14, TST1*-24, TST1*-34, TST1*-44, TST1*-54) +TST39-4 = same as TST31-4 but with extension of (TST1*-14, TST1*-24, TST1*-34, TST1*-44, TST1*-54) +TST39-5 = same as TST31-5 but with extension of (TST1*-11, TST1*-21, TST1*-31, TST1*-41, TST1*-51, + TST1*-14, TST1*-24, TST1*-34, TST1*-44, TST1*-54) +TST39-6 = same as TST31-6 but with extension of (TST1*-14, TST1*-24, TST1*-34, TST1*-44, TST1*-54) +TST39-7 = same as TST31-7 but with extension of (TST1*-11, TST1*-21, TST1*-31, TST1*-41, TST1*-51, + TST1*-14, TST1*-24, TST1*-34, TST1*-44, TST1*-54) + +//////////////////////////// + +TST42(group) => FTR02-b1 + [check if the lowest-numbered PMP CSRs must be programmed for higher-numbered ones to be taken into account in PMP checks] +TST42-1 = extension of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) +[configure only one (any, but the first one) PMP entry + - execute the chosen kind of access several times + - check no access-fault exception] +TST42-2 = extension of compatible pair of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) +[configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - execute the 2 kinds of accesses several times + - check no access-fault exception] +TST42-3 = extension of compatible group(N) of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) +[configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - execute all the kinds of accesses several times + - check no access-fault exception] + +//////////////////////////// + +TST51(group) => FTR09-a, FTR09-b and FTR09-c + [create scenarios where 2 PMP entries with same pmpaddr + - one without matching permissions or with A=OFF + - one with matching permissions and A=NA4/NAPOT/TOR + - any of them can be the lowest-numbered PMP entry] +TST51-1 +[configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - configure the highest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - execute the associated access + - check associated access-fault exception raised] +TST51-2 +[configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - configure the highest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - execute the associated access + - check no access-fault exception] + +// //IMPOSSIBLE TO IMPLEMENT (4-BYTE GRANULARITY) => FTR09-a +// [implement checks for priority: +// for each access length (1byte, 2bytes, 3bytes or 4bytes) +// for each byte position on the 32bits bus +// for each kind of permissions/mode access settings +// - set a low-numbered any-single-byte-address-matching PMP entry with non-matching permissions/mode settings +// - set a higher-numbered all-bytes-address-matching PMP entry with matching permissions/mode settings +// - set intermediate-numbered not-all-bytes-address-matching PMP entries with matching permissions/mode settings +// - NB: can be randomized +// - check the accesses fail (so reaching the low-numbered any-single-byte-address-matching PMP entry) +// for each access length (1byte, 2bytes, 3bytes or 4bytes) +// for each byte position on the 32bits bus +// for each kind of permissions/mode access settings +// - set a low-numbered all-bytes-address-matching PMP entry with matching permissions/mode settings +// - set a higher-numbered any-single-byte-address-matching PMP entry with non-matching permissions/mode settings +// - set intermediate-numbered not-all-bytes-address-matching PMP entries with non-matching permissions/mode settings +// - NB: can be randomized +// - check the accesses pass (so reaching the low-numbered all-bytes-address-matching PMP entry)] + +// //IMPOSSIBLE TO IMPLEMENT (4-BYTE GRANUARITY) => FTR09-b and FTR09-c +// [check access fails if only part of the access bytes are matching the PMP entry whatever the permissions and the mode] +// for each access length (1byte, 2bytes, 3bytes or 4bytes) +// for each byte position on the 32bits bus +// for each kind of permissions/mode access settings +// - set a low-numbered all-bytes-address-matching PMP entry with non-matching permissions/mode settings +// - set a higher-numbered any-single-byte-address-matching PMP entry with matching permissions/mode settings +// - set intermediate-numbered not-all-bytes-address-matching PMP entries with matching permissions/mode settings +// - NB: can be randomized +// - check the accesses fail] + +//////////////////////////// + +TST61 => FTR10-a +[check multiple-accesses instructions not generating any access-fault exceptions] + +TST62 +[check multiple-accesses instructions generating access-fault exceptions with only one non-matching access] + +TST63 +[check multiple-accesses instructions generating access-fault exceptions with multiple non-matching accesses] + +TST64 +[create scenario where instruction-associated multiple accesses are not mutually atomic] //TODO: UNDERSTAND THE MEANING + +//TST65 => FTR10-c +[create scenario with misaligned loads, stores, and instruction fetches generating multiple accesses for which: + - access-fault exception occurs at 1st, 2nd, … last access + - other accesses succeed] +[if floating-point is enabled, create scenario for floating-point store wider than XLEN bits (e.g. FSD instruction) + + + diff --git a/verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt b/verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt new file mode 100644 index 00000000000..520e0d99949 --- /dev/null +++ b/verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt @@ -0,0 +1,224 @@ + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +-19-FTR01 + +FTR01-a +[PMP allows physical memory access privileges (read, write, execute) to be specified for each physical memory region] + +FTR01-b +[the standard PMP encoding supports regions as small as four bytes.] + +FTR01-c +[Certain regions’ privileges can be hardwired: so only ever be visible in machine mode but in no lower-privilege layers.] +FTR01-c-extended +[PMP regions hardwired privileges can only be observed in M-mode] + +FTR01-d +[PMP checks are applied to all accesses whose effective privilege mode is S or U] + +FTR01-e +[PMP checks are also applied to page-table accesses for virtual-address translation, for which the effective privilege mode is S] + +FTR01-f (refers to FTR08-e1) +[PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + +FTR01-g1 +[by default (PMP entry not yet configured), S and U modes have no PMP permissions] +FTR01-g2 +[by default (PMP entry not yet configured), M-mode has full permissions.] + +FTR01-h +[PMP violations are always trapped precisely at the processor] + +//////////////////////////// +-21-FTR02 + +FTR02-a +[Up to 64 PMP entries are supported] + +FTR02-b1 +[the lowest-numbered PMP CSRs must be implemented first (does it mean programmed first)] +FTR02-b2 +[All PMP CSR fields are WARL and may be read-only zero (does read-only zero mean not implemented?)] + +FTR02-d +[PMP CSRs are only accessible to M-mode] + +FTR02-e +[2 CSRs, pmpcfg0–pmpcfg1, hold the configurations pmp0cfg–pmp7cfg for the 8 PMP entries] + + +//////////////////////////// +-23-FTR03 + +FTR03-a +[Each PMP address register encodes bits 33–2 of a 34-bit physical address] + +FTR03-b (NOT TOTALLY UNDERSTOOD!!!) +[Not all physical address bits may be implemented, and so the pmpaddr registers are WARL] + +//////////////////////////// +-25-FTR04 + +FTR04-a +[The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved.] + +FTR04-b +[Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + +FTR04-c +[Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + +FTR04-d +[Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + +FTR04-e +[if MXLEN is changed, the contents of the pmp(x)cfg fields are preserved, but appear in the pmpcfg(y) CSR prescribed by the new setting of MXLEN] +FTR04-e-assumption +[we assume MXLEN is always 32bits] + +//////////////////////////// +-27-FTR05 + +FTR05-a +[The A field in a PMP entry’s configuration register encodes the address-matching mode of the associated PMP address register] +[When A=OFF, this PMP entry is disabled and matches no addresses] +[When A=TOR, top boundary of an arbitrary range] +[When A=NA4, naturally aligned four-byte regions] +[When A=NAPOT, naturally aligned power-of-2 regions] +[These modes support four-bytes granularity] + +//////////////////////////// +-28-FTR06 + +FTR06-a +[If PMP entry i’s A field is set to TOR, the entry matches any address y such that pmpaddr(i−1) ≤ y < pmpaddr(i) (irrespective of the value of pmpcfg(i−1))] + +FTR06-b +[If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0)] + +FTR06-c +[If pmpaddr(i−1) ≥ pmpaddr(i) and pmpcfg(i).A=TOR, then PMP entry i matches no addresses] + +//////////////////////////// +-30-FTR07 + +FTR07-a +[Although the PMP mechanism supports regions as small as 4 bytes, platforms may specify coarser PMP regions] +[the PMP grain is 2^(G+2) bytes and must be the same across all PMP regions] + +FTR07-b +[Software may determine the PMP granularity by writing zero to pmp(0)cfg, then writing all ones to pmpaddr(0), then reading back pmpaddr(0). If G is the index of the least-significant bit set, the PMP granularity is 2^(G+2) bytes] + +FTR07-c +[If the current XLEN is greater than MXLEN, the PMP address registers are zero-extended from MXLEN to XLEN bits for the purposes of address matching] +FTR07-c-assumption +[we assume XLEN=MXLEN=32 bits] + +//////////////////////////// +-32-FTR08 + +FTR08-a +[The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored] +[If PMP entry (i) is locked, writes to pmp(i)cfg and pmpaddr(i) are ignored] + +FTR08-b +[Locked PMP entries remain locked until the hart is reset] + +FTR08-c +[if PMP entry (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are ignored] + +FTR08-d +[Setting the L bit locks the PMP entry even when the A field is set to OFF] + +FTR08-e +[L bit indicates whether the R/W/X permissions are enforced on M-mode accesses] +FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) +[When the L bit is set, these permissions are enforced for all privilege modes] +FTR08-e2-1 (refers to FTR09-d1) +[When the L bit is clear, any M-mode access matching the PMP entry will succeed] +FTR08-e2-2 (refers to FTR09-d2-2) +[When the L bit is clear, the R/W/X permissions apply only to S and U modes] + +//////////////////////////// +-34-FTR09 + +FTR09-a +[PMP entries are statically prioritized] +[The lowest-numbered PMP entry that matches any byte of an access determines whether that access succeeds or fails] + +FTR09-b +[The matching PMP entry must match all bytes of an access, or the access fails, irrespective of the L, R, W, and X bits] + +FTR09-c +[If a PMP entry matches all bytes of an access, then the L, R, W, and X bits determine whether the access succeeds or fails] + +FTR09-d1 (refers to FTR08-e2-1) +[If the L bit is clear and the privilege mode of the access is M, the access succeeds] +FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) +[if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] +FTR09-d2-2 (L=0 refers to FTR08-e2-2) +[if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + +FTR09-e +[If no PMP entry matches an M-mode access, the access succeeds] +FTR09-e-question +[what happens if no PMP entry is implemented ?] + +FTR09-f +[If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails] +FTR09-f-question +[what happens if no PMP entry is implemented ?] + +FTR09-g +[If at least one PMP entry is implemented, but all PMP entries’ A fields are set to OFF, then all S-mode and U-mode memory accesses will fail] +FTR09-g-question (same as FTR09-f-question if 'memory access' is no different matter) +[what happens if no PMP entry is implemented ?] + +question are the pmpaddr(i) aligned to 4bytes ? + - NA4: naturally aligned four-byte regions + - NAPOT: naturally aligned power-of-2 regions + - TOR: + These modes support four-byte granularity + Each PMP address register encodes bits 33–2 of a 34-bit physical address for RV32 + +//////////////////////////// +-36-FTR10 + +FTR10-a +[An access-fault exception is generated if at least one access generated by an instruction fails, though other accesses generated by that instruction may succeed with visible side effects] + +FTR10-b +[instructions that reference virtual memory are decomposed into multiple accesses] +FTR10-b-assumption +[we assume no virtual memory is implemented] +[we assume page-based virtual memory is not implemented] + +FTR10-c +[misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before an access-fault exception occurs] + +//////////////////////////// +-38-FTR11 +FTR11-assumption +[we assume no virtual memory is implemented] +[we assume page-based virtual memory is not implemented] + +FTR11-a +[instructions that access virtual memory may result in multiple physical-memory accesses, including implicit references to the page tables. The PMP checks apply to all of these accesses] + +FTR11-b +[The effective privilege mode for implicit page-table accesses is S] + +FTR11-c +[The PMP settings for the resulting physical address may be checked (and possibly cached) at any point between the address +translation and the explicit memory access] + +FTR11-d +[when the PMP settings are modified, M-mode software must synchronize the PMP settings with the virtual memory system and any PMP or address-translation caches] + +FTR11-e +[If page-based virtual memory is not implemented, memory accesses check the PMP settings synchronously, so no SFENCE.VMA is needed] + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/verif/docs/VerifPlans/PMP/runme.sh b/verif/docs/VerifPlans/PMP/runme.sh new file mode 100644 index 00000000000..08508cfb81e --- /dev/null +++ b/verif/docs/VerifPlans/PMP/runme.sh @@ -0,0 +1,34 @@ +############################################################################# +# Copyright (C) 2022 Thales DIS France SAS +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0. +# +# Original Author: Zbigniew Chamski (zbigniew.chamski@thalesgroup.com) +############################################################################# +#!/bin/sh + +# Location of project-specific directories +ROOTDIR=`readlink -f $(dirname "${BASH_SOURCE[0]}")` + +# Set up platform location. It can be anywhere but should contain +# a valid `vp_config.py` file in `vptool` directory. +# Here we use the verification tree from the example directory. +export PLATFORM_TOP_DIR="$ROOTDIR" + +# Set the printable name for the project that will be used +# in the human-readable documentation. +export PROJECT_NAME="PMP" + +# Set the alphanumerical identifier of the project that +# will be used to construct file names etc. +export PROJECT_IDENT="PMP" + +# Set the destination directory of Markdown files for this project. +# Since it will be used by VPTOOL, it shall NOT be a relative path. +export MARKDOWN_OUTPUT_DIR=`readlink -f "$ROOTDIR/../source"` + +# Run VPTOOL overriding the default theme from Yaml config with 'winxpblue'. +# FIXME: Introduce a suitably named shell variable that points to the root +# directory of the tool set (TOOL_TOP etc.) +# FORNOW use a hardcoded relative path. +sh $ROOTDIR/../../../core-v-verif/tools/vptool/vptool.sh $* diff --git a/verif/docs/VerifPlans/csr_access/cva6_csr.rst b/verif/docs/VerifPlans/csr_access/cva6_csr.rst index 0d7e8ce2912..cac3081b9af 100644 --- a/verif/docs/VerifPlans/csr_access/cva6_csr.rst +++ b/verif/docs/VerifPlans/csr_access/cva6_csr.rst @@ -540,7 +540,7 @@ The ``sip`` register contains information on pending interrupts. - USIP - - read-write - - A user\-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt\-pending \(USIP\) bit + - A user\-level software interrupt is triggered on the current hart by writing 1 to its user software interrupt\-pending \(USIP\) bit Supervisor Address Translation and Protection Register -------------------------- @@ -1338,7 +1338,7 @@ Address register for Physical Memory Protection. - read-write - Address register for Physical Memory Protection\. -Instuction Cache Register +Instruction Cache Register -------------------------- AddressOffset: 'h700 -------------------------- @@ -2561,7 +2561,7 @@ AddressOffset: 'hF11 -------------------------- Description: -------------------------- -This register provids the JEDEC manufacturer ID of the provider of the core. +This register provides the JEDEC manufacturer ID of the provider of the core. .. list-table:: :widths: 20 20 15 15 40 @@ -2581,7 +2581,7 @@ This register provids the JEDEC manufacturer ID of the provider of the core. - offset - Offset - read-only - - Contain encording for the final byte discarding the parity bit\. + - Contain encoding for the final byte discarding the parity bit\. Machine Architecture ID Register -------------------------- diff --git a/verif/docs/VerifPlans/csr_embedded_access/VP_IP001.yml b/verif/docs/VerifPlans/csr_embedded_access/VP_IP001.yml index 908ccaafdfa..6d8b277cfc4 100644 --- a/verif/docs/VerifPlans/csr_embedded_access/VP_IP001.yml +++ b/verif/docs/VerifPlans/csr_embedded_access/VP_IP001.yml @@ -47,7 +47,7 @@ subfeatures: !!omap description: 'Check the correctness of RISCV CVA6 Read-Only CSRs by writing CSRs in a random order values: Inverted reset, 0xaaaaaaaa, 0x555555, random values. Then confirm that write into RO CSRs generates illegal exception. - Finaly read back the CSR and check register value has not changed and matchs + Finally read back the CSR and check register value has not changed and matches reference model.' reqt_doc: https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html diff --git a/verif/docs/VerifPlans/csr_embedded_access/cva6_embedded_csr.rst b/verif/docs/VerifPlans/csr_embedded_access/cva6_embedded_csr.rst index 29ee70b5ce3..a0066ff8786 100644 --- a/verif/docs/VerifPlans/csr_embedded_access/cva6_embedded_csr.rst +++ b/verif/docs/VerifPlans/csr_embedded_access/cva6_embedded_csr.rst @@ -85,7 +85,7 @@ The ``mstatus`` register keeps track of and controls the hart’s current operat - Indicates whether machine interrupts were enabled prior to trapping into machine mode\. ``Enumerated Values``( "Disabled" :0)( "Enabled" :1)'\n' * - 6 - UBE - - User mode bit endianess + - User mode bit endianness - read-write,WARL - UBE controls whether explicit load and store memory accesses made from U\-mode are little\-endian or big\-endian\.``Legal Values``:0\. ``Enumerated Values``( "Little-endian" :0)( "Big-endian" :1)'\n' * - 5 @@ -193,7 +193,7 @@ This register contains machine interrupt enable bits. - USIE - - read-write,WARL - - enable U\-mode software interrrupts\.``Legal Values:``0\. + - enable U\-mode software interrupts\.``Legal Values:``0\. Machine Trap Vector Register -------------------------- @@ -3239,7 +3239,7 @@ AddressOffset: 'hF11 -------------------------- Description: -------------------------- -This register provids the JEDEC manufacturer ID of the provider of the core. +This register provides the JEDEC manufacturer ID of the provider of the core. .. list-table:: :widths: 20 20 15 15 40 @@ -3259,7 +3259,7 @@ This register provids the JEDEC manufacturer ID of the provider of the core. - offset - Offset - read-only - - Contain encording for the final byte discarding the parity bit\. + - Contain encoding for the final byte discarding the parity bit\. Machine Architecture ID Register -------------------------- diff --git a/verif/docs/VerifPlans/csr_embedded_access/dvplan_csr-embedded-access.md b/verif/docs/VerifPlans/csr_embedded_access/dvplan_csr-embedded-access.md index 343fffcaa05..4e29721fea6 100644 --- a/verif/docs/VerifPlans/csr_embedded_access/dvplan_csr-embedded-access.md +++ b/verif/docs/VerifPlans/csr_embedded_access/dvplan_csr-embedded-access.md @@ -137,7 +137,7 @@ Jean-Roch Coulon - Thales * **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html * **Feature Description** - Check the correctness of RISCV CVA6 Read-Only CSRs by writing CSRs in a random order values: Inverted reset, 0xaaaaaaaa, 0x555555, random values. Then confirm that write into RO CSRs generates illegal exception. Finaly read back the CSR and check register value has not changed and matchs reference model. + Check the correctness of RISCV CVA6 Read-Only CSRs by writing CSRs in a random order values: Inverted reset, 0xaaaaaaaa, 0x555555, random values. Then confirm that write into RO CSRs generates illegal exception. Finally read back the CSR and check register value has not changed and matches reference model. * **Verification Goals** 1.Attempt to write a RO CSR. @@ -159,7 +159,7 @@ Jean-Roch Coulon - Thales * **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html * **Feature Description** - Check the correctness of RISCV CVA6 all CSR addresses write and read operations by writing random value to CSR address from 0 to 0xFFF in a random order. Then confirm that write into unmapped addresses generates illegal exception. Finaly read the CSRs in a random order and check that it also generates illegal exception in unmapped addresses. + Check the correctness of RISCV CVA6 all CSR addresses write and read operations by writing random value to CSR address from 0 to 0xFFF in a random order. Then confirm that write into unmapped addresses generates illegal exception. Finally read the CSRs in a random order and check that it also generates illegal exception in unmapped addresses. * **Verification Goals** 1.Write and read all CSR addresses. diff --git a/verif/docs/VerifPlans/source/dvplan_CVXIF.md b/verif/docs/VerifPlans/source/dvplan_CVXIF.md index ba6de7ee0fd..1c67cde5710 100644 --- a/verif/docs/VerifPlans/source/dvplan_CVXIF.md +++ b/verif/docs/VerifPlans/source/dvplan_CVXIF.md @@ -192,7 +192,7 @@ *(none)* -### Sub-feature: 006_issue uniquness +### Sub-feature: 006_issue uniqueness #### Item: 000 @@ -283,7 +283,7 @@ *(none)* -### Sub-feature: 001_commit transaction uniquness +### Sub-feature: 001_commit transaction uniqueness #### Item: 000 @@ -392,7 +392,7 @@ *(none)* -### Sub-feature: 002_result transaction uniquness +### Sub-feature: 002_result transaction uniqueness #### Item: 000 diff --git a/verif/docs/VerifPlans/source/dvplan_FENCEI.md b/verif/docs/VerifPlans/source/dvplan_FENCEI.md index 2f77ee43e26..395788e4f04 100644 --- a/verif/docs/VerifPlans/source/dvplan_FENCEI.md +++ b/verif/docs/VerifPlans/source/dvplan_FENCEI.md @@ -80,7 +80,7 @@ https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction. * **Verification Goals** - Let the instruction right before a fence.i write a different instruction to the address following the fence.i, then observe that the written instruction is executed instead of the original one and that no side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit instructions to force a noticable difference). + Let the instruction right before a fence.i write a different instruction to the address following the fence.i, then observe that the written instruction is executed instead of the original one and that no side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit instructions to force a noticeable difference). * **Pass/Fail Criteria:** Self-Check * **Test Type:** Directed SelfChk * **Coverage Method:** Testcase @@ -259,7 +259,7 @@ https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf *(none)* -### Sub-feature: 007_AckWithold +### Sub-feature: 007_AckWithhold #### Item: 000 @@ -269,7 +269,7 @@ https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf If req is high, but ack never comes, then the core keeps on stalling and the fence.i is blocked from completing. * **Verification Goals** - Upon a req, try witholding ack for a long time and see that the fence.i can be stalled arbitrarily long (should have covers for ack delays of at least {[0:5]}). + Upon a req, try withholding ack for a long time and see that the fence.i can be stalled arbitrarily long (should have covers for ack delays of at least {[0:5]}). * **Pass/Fail Criteria:** Assertion * **Test Type:** ENV Capability * **Coverage Method:** Functional Coverage @@ -308,7 +308,7 @@ https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf * **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence * **Feature Description** - If the fence.i ends up not retiring because it was preceeded by a taken branch or a jump, then the fencei_flush_req_o shall not go high + If the fence.i ends up not retiring because it was preceded by a taken branch or a jump, then the fencei_flush_req_o shall not go high * **Verification Goals** Take a branch or do a jump to skip a fence.i, and ensure that fencei_flush_req_o doesn't go high. @@ -354,7 +354,7 @@ https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf * **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fenceThis is a pointer to the source Requirements document of the Features in question. The pointer should state the version of the target document. It is free-form, so it can also indicate the specific section/page/paragraph. * **Feature Description** - Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted). + Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about synchronization with instruction fetch, but rather seeing that the stores are not aborted). * **Verification Goals** Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged). @@ -375,7 +375,7 @@ https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf * **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence * **Feature Description** - Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted). + Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about synchronization with instruction fetch, but rather seeing that the stores are not aborted). * **Verification Goals** Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged). @@ -398,7 +398,7 @@ https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf * **Requirement location:** CVA6 User Manual; https://cva6.readthedocs.io/en/latest/01_cva6_user/RISCV_Instructions.html#rv32zifencei-instruction-fetch-fence * **Feature Description** - When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually supressed. + When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually suppressed. * **Verification Goals** Check that a fence.i will cause flushing of the pipeline, prefetcher, write buffer, and data_req_o. diff --git a/verif/docs/VerifPlans/source/dvplan_FRONTEND.md b/verif/docs/VerifPlans/source/dvplan_FRONTEND.md index 0910860f260..ab90d885427 100644 --- a/verif/docs/VerifPlans/source/dvplan_FRONTEND.md +++ b/verif/docs/VerifPlans/source/dvplan_FRONTEND.md @@ -53,7 +53,7 @@ * **Requirement location:** FRONTEND sub-system/functionality/PC generation stage/Branch Predict * **Feature Description** - If instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. + If instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consumed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated. * **Verification Goals** Execute test with RET instructions. Functional cov: RET is executed and RAS output is not valid. @@ -225,7 +225,7 @@ The Branch History table is a two-bit saturation counter that takes the virtual address of the current fetched instruction by the CACHE. It states whether the current branch request should be taken or not. The two bit counter is updated by the successive execution of the current instructions as shown in the following figure. * **Verification Goals** - Execute a serie of taken and not taken branch to check the saturation mechanism + Execute a series of taken and not taken branch to check the saturation mechanism * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) diff --git a/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md b/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md index 5e625de9c01..6df0dbd7947 100644 --- a/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md +++ b/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md @@ -517,7 +517,7 @@ isacov.rv32i_sltiu_cg.cp_immi_toggle slli rd, rs, imm[4:0] rd = rs << imm[4:0] - Zeros are shirfted into lower bits + Zeros are shifted into lower bits * **Verification Goals** Register operands: @@ -544,7 +544,7 @@ isacov.rv32i_slli_cg.cp_rd_rs1_hazard slli rd, rs, imm[4:0] rd = rs << imm[4:0] - Zeros are shirfted into lower bits + Zeros are shifted into lower bits * **Verification Goals** Input operands: @@ -573,7 +573,7 @@ isacov.rv32i_slli_cg.cp_rs1_toggle slli rd, rs, imm[4:0] rd = rs << imm[4:0] - Zeros are shirfted into lower bits + Zeros are shifted into lower bits * **Verification Goals** Output result: @@ -600,7 +600,7 @@ isacov.rv32i_slli_cg.cp_rd_toggle srli rd, rs, imm[4:0] rd = rs >> imm[4:0] - Zeros are shirfted into upper bits + Zeros are shifted into upper bits * **Verification Goals** Register operands: @@ -627,7 +627,7 @@ isacov.rv32i_srli_cg.cp_rd_rs1_hazard srli rd, rs, imm[4:0] rd = rs >> imm[4:0] - Zeros are shirfted into upper bits + Zeros are shifted into upper bits * **Verification Goals** Input operands: @@ -656,7 +656,7 @@ isacov.rv32i_srli_cg.cp_rs1_toggle srli rd, rs, imm[4:0] rd = rs >> imm[4:0] - Zeros are shirfted into upper bits + Zeros are shifted into upper bits * **Verification Goals** Output result: @@ -739,7 +739,7 @@ isacov.rv32i_srai_cg.cp_rs1_toggle srli rd, rs, imm[4:0] rd = rs >> imm[4:0] - Zeros are shirfted into upper bits + Zeros are shifted into upper bits * **Verification Goals** Output result: @@ -1550,7 +1550,7 @@ isacov.rv32i_sltu_cg.cp_rs2_toggle sll rd, rs1, rs2 rd = rs1 << rs2[4:0] - Zeros are shirfted into lower bits + Zeros are shifted into lower bits * **Verification Goals** Register operands: @@ -1581,7 +1581,7 @@ isacov.rv32i_sll_cg.cp_rd_rs2_hazard sll rd, rs1, rs2 rd = rs1 << rs2[4:0] - Zeros are shirfted into lower bits + Zeros are shifted into lower bits * **Verification Goals** Input operands: @@ -1610,7 +1610,7 @@ isacov.rv32i_sll_cg.cp_rs1_toggle sll rd, rs1, rs2 rd = rs1 << rs2[4:0] - Zeros are shirfted into lower bits + Zeros are shifted into lower bits * **Verification Goals** Output result: @@ -1639,7 +1639,7 @@ isacov.rv32i_sll_cg.cp_rd_toggle srl rd, rs1, rs2 rd = rs1 >> rs2[4:0] - Zeros are shirfted into upper bits + Zeros are shifted into upper bits * **Verification Goals** Register operands: @@ -1670,7 +1670,7 @@ isacov.rv32i_srl_cg.cp_rd_rs2_hazard srl rd, rs1, rs2 rd = rs1 >> rs2[4:0] - Zeros are shirfted into upper bits + Zeros are shifted into upper bits * **Verification Goals** Input operands: @@ -1699,7 +1699,7 @@ isacov.rv32i_srl_cg.cp_rs1_toggle srl rd, rs1, rs2 rd = rs1 >> rs2[4:0] - Zeros are shirfted into upper bits + Zeros are shifted into upper bits * **Verification Goals** Output result: @@ -1786,7 +1786,7 @@ isacov.rv32i_sra_cg.cp_rs1_toggle sra rd, rs1, rs2 rd = rs1 >> rs2[4:0] - Zeros are shirfted into upper bits + Zeros are shifted into upper bits * **Verification Goals** Output result: @@ -3946,7 +3946,7 @@ isacov.rv32m_remu_cg.cp_rd_toggle Exception: - Misaligned address (non-32-bit aligned) will always cause exceptio + Misaligned address (non-32-bit aligned) will always cause exception * **Pass/Fail Criteria:** Check RM * **Test Type:** Constrained Random * **Coverage Method:** Functional Coverage @@ -7054,7 +7054,7 @@ isacov.rv32m_remu_cg.cp_rd_toggle * **Requirement location:** ./RISCV_Instructions.rst * **Feature Description** - All suported instructions for the core are executed + All supported instructions for the core are executed * **Verification Goals** Instruction is executed @@ -7073,7 +7073,7 @@ isacov.rv32m_remu_cg.cp_rd_toggle * **Requirement location:** ./RISCV_Instructions.rst * **Feature Description** - All suported instructions for the core are executed + All supported instructions for the core are executed * **Verification Goals** All back-to-back supported instruction sequences are executed @@ -7178,7 +7178,7 @@ isacov.rv32m_remu_cg.cp_rd_toggle CSR writes from the program are executed in conjunction with all instruction groups * **Verification Goals** - Each instruction group is executed after each supported CSR is written with a Zicsri write instructio + Each instruction group is executed after each supported CSR is written with a Zicsri write instruction * **Pass/Fail Criteria:** NDY (Not Defined Yet) * **Test Type:** NDY (Not Defined Yet) * **Coverage Method:** NDY (Not Defined Yet) diff --git a/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md b/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md index 55cd6efa671..a2b5d014001 100644 --- a/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md +++ b/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md @@ -12,8 +12,8 @@ If PTE has valid and non-reserved RWX permissions, but the translated Physical address (pte.ppn of leaf PTE + offset) does not have (r,w,x) PMP permissions, then accessing the translated Physical address would raise access fault exception. When satp.mode=sv32, and PTE has valid and non-reserved RWX permissions then test the following in supervisor and user privilege mode for level1 and level0 PTE. - - Remove read PMP permission of translated Physical Address in pmpcfg and test the read acces. - - Remvoe write PMP permission of translated Physical Address in pmpcfg and test the write access. + - Remove read PMP permission of translated Physical Address in pmpcfg and test the read access. + - Remove write PMP permission of translated Physical Address in pmpcfg and test the write access. - Remove execute PMP permission of translated Physical Address in pmpcfg and test the execute access. * **Verification Goals** @@ -42,8 +42,8 @@ If PTE does not have (r,w,x) PMP permissions, then accessing it would raise access fault exception of the corresponding access type. When satp.mode=sv32, then test the following in supervisor and user privilege mode for level0 and level1 PTE. - - Remove read PMP permission of PTE address in pmpcfg and test the read acces. - - Remvoe write PMP permission of PTE address in pmpcfg and test the write access. + - Remove read PMP permission of PTE address in pmpcfg and test the read access. + - Remove write PMP permission of PTE address in pmpcfg and test the write access. - Remove execute PMP permission of PTE address in pmpcfg and test the execute access. * **Verification Goals** @@ -67,16 +67,16 @@ #### Item: 000 -* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chpter 5.3.2 +* **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.3.2 * **Feature Description** If PTE does not have Valid (pte.V=0) permission, then accessing it would raise page fault exception of the corresponding access type. When satp.mode=sv32 and PTE has (r,w,x) PMP permissions, then test the following in supervisor and user privilege mode for level0 and level1 PTE. - - Set PTE.V = 0 and test the read acces. + - Set PTE.V = 0 and test the read access. - Set PTE.V = 0 and test the write access. - Set PTE.V = 0 and test the execute access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode * **Verification Goals** @@ -105,11 +105,11 @@ If PTE has reserved RWX encodings (pte.w=1 & pte.r=0), then accessing it would raise page fault exception of the corresponding access type. When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. - - Set pte.w=1 & pte.r=0 and test the read acces. + - Set pte.w=1 & pte.r=0 and test the read access. - Set pte.w=1 & pte.r=0 and test the write access. - Set pte.w=1 & pte.r=0 and test the execute access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode * **Verification Goals** @@ -138,11 +138,11 @@ If PTE at level0 has non-leaf RWX permissions (pte.x=0 & pte.r=0), then accessing it would raise page fault exception of the corresponding access type. When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 PTE. - - Set pte.x=0 & pte.r=0 & pte.w=0 and test the read acces. + - Set pte.x=0 & pte.r=0 & pte.w=0 and test the read access. - Set pte.x=0 & pte.r=0 & pte.w=0 and test the write access. - Set pte.x=0 & pte.r=0 & pte.w=0 and test the execute access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode * **Verification Goals** @@ -175,7 +175,7 @@ - Test the write access for both pte.w=1 and for pte.w=0 - Test the execute access for both pte.x=1 and for pte.x=0 - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * **Verification Goals** RWX access should be successful if the corresponding permissions are granted in the PTE. Check that load, store and execute works without any page fault. @@ -204,11 +204,11 @@ If PTE belongs to supervisor mode i.e. its U permission bit is clear (pte.u = 0), then accessing that PTE in user mode would raise page fault exception of the corresponding access type. When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, and pte.v=1, then test the following user privilege mode for level0 and level1 PTE. - - Set pte.u=0 and test the read acces. + - Set pte.u=0 and test the read access. - Set pte.u=0 and test the write access. - Set pte.u=0 and test the execute access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * **Verification Goals** Page fault exception should be raised according to {x,r,w} access type. Check that: @@ -233,11 +233,11 @@ If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1) and m/sstatus.SUM = 0, then accessing that PTE in supervisor mode would raise page fault exception of the corresponding access type. When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, and pte.v=1, then test the following in supervisor mode for level 0 and level 1 PTE. - - Set pte.u=1 & s/mstatus.SUM = 0 and test the read acces. + - Set pte.u=1 & s/mstatus.SUM = 0 and test the read access. - Set pte.u=1 & s/mstatus.SUM = 0 and test the write access. - Set pte.u=1 & s/mstatus.SUM = 0 and test the execute access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * **Verification Goals** Page fault exception should be raised according to {x,r,w} access type. Check that: @@ -265,14 +265,14 @@ If PTE belongs to user mode i.e. its U permission bit is set (pte.u = 1) and m/sstatus.SUM = 1, then RW access to that PTE in supervisor mode would be successful but eXecute access would raise instruction page fault exception in s-mode. When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX encoding, and pte.v=1, then test the following in supervisor mode for level0 and level1 PTE. - - Set pte.r=1 & pte.u=1 & s/mstatus.SUM = 1 and test the read acces. + - Set pte.r=1 & pte.u=1 & s/mstatus.SUM = 1 and test the read access. - Set pte.w=1 & pte.u=1 & s/mstatus.SUM = 1 and test the write access. - Set pte.x=1 & pte.u=1 & s/mstatus.SUM = 1 and test the execute access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * **Verification Goals** - Read and Write access to the PTE should be successful. So, check that the load and store works without page fault and expected data is stored to and loaded from the memory, repectively. + Read and Write access to the PTE should be successful. So, check that the load and store works without page fault and expected data is stored to and loaded from the memory, respectively. Execute access should raise instruction page fault. Check that: - m/scause must contain the exception number of instruction instruction access fault. @@ -300,7 +300,7 @@ - Test the write access for both pte.w=1 and for pte.w=0 - Test the execute access for both pte.x=1 and for pte.x=0 - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * **Verification Goals** RWX access should be successful if the corresponding permissions are granted in the PTE. Check that load, store and execute works without any page fault. @@ -330,9 +330,9 @@ If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=0, then read access on that PTE should raise load page fault exception. When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. - - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=0 and test the read acces. + - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=0 and test the read access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode * **Verification Goals** @@ -358,9 +358,9 @@ If PTE has only execute permission (pte.x = 1) and s/mstatus.MXR=1, then read access on that PTE should be successful without having explicit read permission (pte.r=0). When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. - - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=1 and test the read acces. + - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=1 and test the read access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode * **Verification Goals** @@ -404,12 +404,12 @@ * **Feature Description** If implementation does not sets the pte.A on accessing the PTE, and PTE has pte.A=0, then accessing it would raise page fault exception of the corresponding access type. - When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. Execute sfence.vma before accessign the PTE. - - Set pte.r=1 & pte.a=0 and test the read acces. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. Execute sfence.vma before accessing the PTE. + - Set pte.r=1 & pte.a=0 and test the read access. - Set pte.w=1 & pte.a=0 and test the write access. - Set pte.x=1 & pte.a=0 and test the execute access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode. * **Verification Goals** @@ -437,10 +437,10 @@ * **Feature Description** If implementation does not sets the pte.D when PTE is written, and PTE has pte.D=0, then attempting to store on that PTE would raise Store/AMO page fault exception. - When satp.mode=sv32, PTE has (r,w,x) PMP permissions, pte.a=1 and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. Execute sfence.vma before accessign the PTE. + When satp.mode=sv32, PTE has (r,w,x) PMP permissions, pte.a=1 and pte.v=1, then test the following in supervisor and user privilege mode for level0 and level1 PTE. Execute sfence.vma before accessing the PTE. - Set pte.w=1 & pte.d=0 and test the write access. - * For testing at level0, set all the pte perimssions at level1 to 0 except pte.v, so that level1 points to level0. + * For testing at level0, set all the pte permissions at level1 to 0 except pte.v, so that level1 points to level0. * Set pte.U=0 when test in Supervisor mode and Set pte.U=1 when testing in user mode. * **Verification Goals** @@ -563,10 +563,10 @@ * **Requirement location:** ISA Volume II: Privilege Architecture Version 20211203, Chapter 5.1.11 * **Feature Description** - Selecting MODE=Bare the remaining feild should be zero. Other encoding for remaining feild in satp is reserved + Selecting MODE=Bare the remaining field should be zero. Other encoding for remaining field in satp is reserved * **Verification Goals** - Show wirting {zero, non-zero} value to satp when mode=bare the behaviour follows the design implemention + Show writing {zero, non-zero} value to satp when mode=bare the behaviour follows the design implementation * **Pass/Fail Criteria:** Check RM * **Test Type:** RISC-V Arch-test * **Coverage Method:** Testcase diff --git a/verif/docs/VerifPlans/source/dvplan_PMP.md b/verif/docs/VerifPlans/source/dvplan_PMP.md new file mode 100644 index 00000000000..184e3882799 --- /dev/null +++ b/verif/docs/VerifPlans/source/dvplan_PMP.md @@ -0,0 +1,16607 @@ +# Module: PMP + +## Feature: TRISTAN Restrictions + +### Sub-feature: 000_general + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + the verif plan is written for 32bits architecture only +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S000_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_number of harts + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + there is only 1 hart in cv32a6 +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_mxlen + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + MXLEN is always 32bits +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_xlen + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + XLEN=MXLEN=32, so the PMP address registers are XLEN bits long, so no zero-extension needed +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S003_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_granularity + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + PMP granularity is 8 bytes (G=1), but the verif plan is written to take G=0 into account (NA4) +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S004_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_number of pmp entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + there are 8 HW implemented PMP entries +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S005_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_hardwired regions + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + none of the 8 PMP entries is hardwired privileges +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S006_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_virtual memory + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + no virtual memory is implemented + as a consequence no page-based virtual memory is implemented +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S007_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_physical memory regions + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + the list of all physical memory regions + - system memory regions + - I-$ + - D-$ + - I-scratchpad (preload mode) + - I-scratchpad (functional mode) + - D-scratchpad + - ahb_periph +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S008_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 009_pmp entry disabling + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + we assume an already written PMP entry (i) can be disabled + - if L=0, by clearing pmpcfg(i) + - if L=1, only by hart reset +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S009_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 010_access-faults (violations) + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + The testbench/testcases architecture ensures that: + - any time there is an access-fault type, we check it matches the related access-type + - all violations are trapped at the processor + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP violations are always trapped precisely at the processor +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S010_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 011_testcases modularity + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + The verif plan is written assuming there is a way (like SystemVerilog interaction): + - to factorize the testcases in code blocks (in particular configuration code block and access code block) + - to randomize the code blocks data and addresses + - to randomize the sequence of code blocks +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S011_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 012_access types + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + at the time of writing, + the verif plan makes no distinction between load and load-reserved instructions. they are gathered in the same access type, subtleties unknown + the verif plan makes no distinction between store, store-conditional, and AMO instructions. they are gathered in the same access type, subtleties unknown +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S012_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 013_multiple accesses instructions + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + we assume there is no added value to test multiple accesses instructions +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S013_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 014_misaligned instructions + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + + we assume that instructions are mandatorily aligned +* **Verification Goals** + + +* **Pass/Fail Criteria:** NDY (Not Defined Yet) +* **Test Type:** NDY (Not Defined Yet) +* **Coverage Method:** NDY (Not Defined Yet) +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F000_S014_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: PMP granularity + +### Sub-feature: 000_granularity_check + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + + Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones to pmpaddr0, then reading back pmpaddr0. + If G is the index of the least-significant bit set, the PMP granularity is 2G+2 bytes. +* **Verification Goals** + + determine the PMP granularity 2^(G+2) bytes by writing zero to pmp(0)cfg, then writing all ones to pmpaddr(0), then reading back pmpaddr(0). G is the index G of the least-significant bit set +* **Pass/Fail Criteria:** Other +* **Test Type:** Directed Non-SelfChk +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F001_S000_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR07-b + Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones to pmpaddr0, then reading back pmpaddr0. + If G is the index of the least-significant bit set, the PMP granularity is 2G+2 bytes. + + + TST01 (HIGH-PRIO) => FTR07-b + [determine the PMP granularity 2^(G+2) bytes by writing zero to pmp(0)cfg, then writing all ones to pmpaddr(0), then reading back pmpaddr(0). G is the index G of the least-significant bit set] +## Feature: CSRs M-mode only + +### Sub-feature: 000_configure_1_pmp_entry + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + + PMP CSRs are only accessible to M-mode +* **Verification Goals** + + configure 1 PMP entry (i) (the 1st one), + - check for each PMP entry (i) reset value (read zero) by reading in M mode + - check for each PMP entry (i) that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check for each PMP entry (i) that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for each PMP entry (i) that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F002_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST02(group) => FTR02-d + [check that all 8 HW implemented PMP entries are writable/readable in M-mode (L=0)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=0)] + - random values may be used + - before any configuration (after hart reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + + TST02-1 (HIGH-PRIO) + [configure 1 PMP entry ([FTR02-b1]: maybe mandatorily the first one): with L=0, + - if possible, the PMP entry number is a configurable parameter + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +### Sub-feature: 001_configure_2_pmp_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + + PMP CSRs are only accessible to M-mode +* **Verification Goals** + + configure 2 PMP entries (the 2 first ones in incrementing order), + - reuse of VP_PMP_F002_S001_I000 sequence +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F002_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST02(group) => FTR02-d + [check that all 8 HW implemented PMP entries are writable/readable in M-mode (L=0)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=0)] + - random values may be used + - before any configuration (after hart reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + + TST02-2 (LOW-PRIO) = 2 times reuse/call of TST02-1 + [configure 2 PMP entries ([FTR02-b1]: maybe mandatorily the 2 first ones): both with L=0, + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +### Sub-feature: 002_configure_N_pmp_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + + PMP CSRs are only accessible to M-mode +* **Verification Goals** + + configure N PMP entries (the N first ones in incrementing order), + - reuse of VP_PMP_F002_S001_I000 sequence +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F002_S003_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST02(group) => FTR02-d + [check that all 8 HW implemented PMP entries are writable/readable in M-mode (L=0)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=0)] + - random values may be used + - before any configuration (after hart reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + + TST02-3 (LOW-PRIO) = N times reuse/call of TST02-1 + [configure N PMP entries ([FTR02-b1]: maybe mandatorily the N first ones): all with L=0, + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +### Sub-feature: 003_configure_8_pmp_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + + PMP CSRs are only accessible to M-mode +* **Verification Goals** + + configure all 8 PMP entries (in incrementing order), + - reuse of VP_PMP_F002_S001_I000 sequence +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F002_S004_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST02(group) => FTR02-d + [check that all 8 HW implemented PMP entries are writable/readable in M-mode (L=0)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=0)] + - random values may be used + - before any configuration (after hart reset), check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + + TST02-4 (HIGH-PRIO) = 8 times reuse/call of TST02-1 + [configure 8 PMP entries: all with L=0, + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +## Feature: CSRs locked access + +### Sub-feature: 000_configure_1_pmp_entry + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored + If PMP entry (i) is locked, writes to pmp(i)cfg and pmpaddr(i) are ignored + Locked PMP entries remain locked until the hart is reset + + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + Setting the L bit locks the PMP entry even when the A field is set to OFF + + Additionally, if PMP entry (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are ignored +* **Verification Goals** + + configure 1 PMP entry (the 1st one) with L=1, + - write PMP entry (i) with L=1 in M-mode + - A is random, should also be tried with A=OFF when L=1 (to cover feature above) + - check PMP entry (i) written value in M-mode + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked (M-mode check only) + - also check for PMP entry (i) where L=1 and pmp(i)cfg.A=TOR that pmpaddr(i-1) is effectively locked + - apply hart reset + - check for PMP entry (i) reset value (read zero) by reading in M mode + - write PMP entry (i) in M-mode + - check PMP entry (i) written value in M-mode + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, (L) value is a configurable parameter + - so the same sub-functions are reused with varying (i) and (L) parameters +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F003_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST03(group) => FTR08-a and FTR08-b + [check that HW implemented PMP entries are not writable/readable in M-mode (L=1)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=1)] + - before any configuration, check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg and pmpaddr(i) maybe random values + - execute following tests specific checks + - check only hart reset unlocks all => FTR08-b + - check reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero + + TST03-1 (HIGH-PRIO) + [configure 1 PMP entry ([FTR02-b1]: maybe mandatorily the first one): with L=1, + - if possible, the PMP entry number is a configurable parameter + - if possible, L value is a configurable parameter + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +### Sub-feature: 001_configure_2_pmp_entries_L1 + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored + If PMP entry (i) is locked, writes to pmp(i)cfg and pmpaddr(i) are ignored + Locked PMP entries remain locked until the hart is reset + + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + Setting the L bit locks the PMP entry even when the A field is set to OFF + + Additionally, if PMP entry (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are ignored +* **Verification Goals** + + configure 2 PMP entries (the 2 first ones in incrementing order) with L=1, + - reuse of VP_PMP_F003_S001_I000 sequence +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F003_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST03(group) => FTR08-a and FTR08-b + [check that HW implemented PMP entries are not writable/readable in M-mode (L=1)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=1)] + - before any configuration, check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg and pmpaddr(i) maybe random values + - execute following tests specific checks + - check only hart reset unlocks all => FTR08-b + - check reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero + + TST03-2 (LOW-PRIO) = 2 times reuse/call of TST02-1 + [configure 2 PMP entries ([FTR02-b1]: maybe mandatorily the 2 first ones): both with L=1, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +### Sub-feature: 002_configure_2_pmp_entries_L0_L1 + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored + If PMP entry (i) is locked, writes to pmp(i)cfg and pmpaddr(i) are ignored + Locked PMP entries remain locked until the hart is reset + + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + Setting the L bit locks the PMP entry even when the A field is set to OFF + + Additionally, if PMP entry (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are ignored +* **Verification Goals** + + configure 2 PMP entries (the 2 first ones in incrementing order) at least one with L=1 and one with L=0, + - write PMP entry (i) with L=0/1 in M-mode + - A is random, should also be tried with A=OFF when L=1 (to cover feature above) + - check PMP entry (i) written value in M-mode + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable in M mode (read back the written value in M mode) + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked (M-mode check only) + - also check for PMP entry (i) where L=1 and pmp(i)cfg.A=TOR that pmpaddr(i-1) is effectively locked + - apply hart reset + - check for PMP entry (i) reset value (read zero) by reading in M mode + - write PMP entry (i) in M-mode + - check PMP entry (i) written value in M-mode + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, (L) value is a configurable parameter + - so the same sub-functions are reused with varying (i) and (L) parameters +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F003_S003_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST03(group) => FTR08-a and FTR08-b + [check that HW implemented PMP entries are not writable/readable in M-mode (L=1)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=1)] + - before any configuration, check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg and pmpaddr(i) maybe random values + - execute following tests specific checks + - check only hart reset unlocks all => FTR08-b + - check reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero + + TST03-3 (HIGH-PRIO) = 2 times reuse/call of TST02-1 + [configure 2 PMP entries ([FTR02-b1]: maybe mandatorily the 2 first ones): one with L=1 and one with L=0, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check locked PMP entry (i) has no effect on unlocked PMP entry (j) + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +### Sub-feature: 003_configure_N_pmp_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored + If PMP entry (i) is locked, writes to pmp(i)cfg and pmpaddr(i) are ignored + Locked PMP entries remain locked until the hart is reset + + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + Setting the L bit locks the PMP entry even when the A field is set to OFF + + Additionally, if PMP entry (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are ignored +* **Verification Goals** + + configure N PMP entries (the N first ones in incrementing order) at least one with L=1 and one with L=0, + - reuse of VP_PMP_F003_S003_I000 sequence +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F003_S004_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST03(group) => FTR08-a and FTR08-b + [check that HW implemented PMP entries are not writable/readable in M-mode (L=1)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=1)] + - before any configuration, check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg and pmpaddr(i) maybe random values + - execute following tests specific checks + - check only hart reset unlocks all => FTR08-b + - check reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero + + TST03-4 (LOW-PRIO) = N times reuse/call of TST02-1 + [configure N PMP entries ([FTR02-b1]: maybe mandatorily the N first ones): at least one with L=1 and one with L=0, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check locked PMP entry (i) has no effect on unlocked PMP entry (j) + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +### Sub-feature: 004_configure_8_pmp_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored + If PMP entry (i) is locked, writes to pmp(i)cfg and pmpaddr(i) are ignored + Locked PMP entries remain locked until the hart is reset + + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + + Setting the L bit locks the PMP entry even when the A field is set to OFF + + Additionally, if PMP entry (i) is locked and pmp(i)cfg.A is set to TOR, writes to pmpaddr(i-1) are ignored +* **Verification Goals** + + configure all 8 PMP entries (in incrementing order) at least one with L=1 and one with L=0, + - reuse of VP_PMP_F003_S003_I000 sequence +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F003_S005_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST03(group) => FTR08-a and FTR08-b + [check that HW implemented PMP entries are not writable/readable in M-mode (L=1)] + [check that no HW implemented PMP entry are writable/readable in S or U modes (L=1)] + - before any configuration, check all pmp(i)cfg and pmpaddr(i) are M-mode read zero + - configure PMP entry (i) with L=1 (or 0): pmp(i)cfg and pmpaddr(i) maybe random values + - execute following tests specific checks + - check only hart reset unlocks all => FTR08-b + - check reset values: all pmp(i)cfg and pmpaddr(i) are M-mode read zero + + TST03-5 (HIGH-PRIO) = 8 times reuse/call of TST02-1 + [configure 8 PMP entries: at least one with L=1 and one with L=0, + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are effectively locked whatever the SW mode => FTR08-a + - check for PMP entry (i) where L=1 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes + - check locked PMP entry (i) has no effect on unlocked PMP entry (j) + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for PMP entry (i) where L=0 that pmp(i)cfg and pmpaddr(i) are not writable/readable in S or U modes] +## Feature: CSRs programming order + +### Sub-feature: 000_configure_1_pmp_entry + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + + the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first) + All PMP CSR fields are WARL and may be read-only zero (QUESTION: does read-only zero mean not implemented?) +* **Verification Goals** + + configure any PMP entry (i), but the first one + - reuse of VP_PMP_F003_S003_I000 sequence (Feature: "CSRs locked access") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F004_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST04 => FTR02-b1 and FTR02-b2 + [check if the lowest-numbered PMP CSRs must be programmed first before programming higher-numbered ones] + + TST04-1 (LOW-PRIO) extends TST02-1 + [configure any PMP entry, but the first one + - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for not configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are M-mode read zero] +### Sub-feature: 001_configure_2_pmp_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + + the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first) + All PMP CSR fields are WARL and may be read-only zero (QUESTION: does read-only zero mean not implemented?) +* **Verification Goals** + + configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - reuse of VP_PMP_F003_S003_I000 sequence (Feature: "CSRs locked access") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F004_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST04 => FTR02-b1 and FTR02-b2 + [check if the lowest-numbered PMP CSRs must be programmed first before programming higher-numbered ones] + + TST04-2 (HIGH-PRIO) extends TST02-2 + [configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for not configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are M-mode read zero] +### Sub-feature: 002_configure_N_pmp_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + + the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first) + All PMP CSR fields are WARL and may be read-only zero (QUESTION: does read-only zero mean not implemented?) +* **Verification Goals** + + configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - reuse of VP_PMP_F003_S003_I000 sequence (Feature: "CSRs locked access") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F004_S003_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST04 => FTR02-b1 and FTR02-b2 + [check if the lowest-numbered PMP CSRs must be programmed first before programming higher-numbered ones] + + TST04-3 (LOW-PRIO) extends TST02-3 + [configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only + - check for not configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are M-mode read zero] +### Sub-feature: 003_configure_8_pmp_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + + the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first) + All PMP CSR fields are WARL and may be read-only zero (QUESTION: does read-only zero mean not implemented?) +* **Verification Goals** + + configure all 8 PMP entries (highest-numbered ones first) + - reuse of VP_PMP_F003_S003_I000 sequence (Feature: "CSRs locked access") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F004_S004_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST04 => FTR02-b1 and FTR02-b2 + [check if the lowest-numbered PMP CSRs must be programmed first before programming higher-numbered ones] + + TST04-4 (HIGH-PRIO) extends TST02-4 + [configure 8 PMP entries (highest-numbered ones first) + - check for configured PMP entry (i), pmp(i)cfg and pmpaddr(i) are writable/readable in M-mode only] +## Feature: CSRs Hardwired regions + +### Sub-feature: 000_access with L=0 + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + Certain regions’ privileges can be hardwired: so only ever be visible in machine mode but in no lower-privilege layers. + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + Implementations may implement zero, 16, or 64 PMP CSRs + + {https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/PMP.html} + A maximum of 16 PMP entries are supported. + All PMP CSRs are always implemented, but CSRs (or bitfields of CSRs) related to PMP entries with number CVA6Cfg.NrPMPEntries and above are hardwired to zero. + + TRISTAN + 8 PMP entries are implemented +* **Verification Goals** + + configure the first 8 PMP entries with L=0 + - for each PMP entry (i), check several times that pmp(i)cfg and pmpaddr(i) can be written and can be read back exactly the same (in M-mode) + + for the last 8 PMP entries, check that pmp(i)cfg and pmpaddr(i) always read zero after being written (in M-mode with L=0) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F005_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST05 => FTR01-c and FTR01-c-extended + [check all regions are configurable in M-mode to make sure none is hardwired] + [regions hardwired privileges might only ever be visible in M-mode] + + TST05-1 (HIGH-PRIO) extends TST02-4 + - check the written pmp(i)cfg and pmpaddr(i) values can be read exactly the same as written +### Sub-feature: 001_access with L=1 + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + Certain regions’ privileges can be hardwired: so only ever be visible in machine mode but in no lower-privilege layers. + + {Section 3.7.1 Page 57 Volume II: RISC-V Privileged Architectures V20211203} + Implementations may implement zero, 16, or 64 PMP CSRs + + {https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/PMP.html} + A maximum of 16 PMP entries are supported. + All PMP CSRs are always implemented, but CSRs (or bitfields of CSRs) related to PMP entries with number CVA6Cfg.NrPMPEntries and above are hardwired to zero. + + TRISTAN + 8 PMP entries are implemented +* **Verification Goals** + + configure the first 8 PMP entries with L=1 + - for each PMP entry (i), check once that pmp(i)cfg and pmpaddr(i) can be written and can be read back exactly the same (in M-mode) + - apply hart reset + - for each PMP entry (i), check once that pmp(i)cfg and pmpaddr(i) can be written and can be read back exactly the same (in M-mode) + + for the last 8 PMP entries, check that pmp(i)cfg and pmpaddr(i) always read zero after being written (in M-mode with L=1) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F005_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST05 => FTR01-c and FTR01-c-extended + [check all regions are configurable in M-mode to make sure none is hardwired] + [regions hardwired privileges might only ever be visible in M-mode] + + TST05-2 (LOW-PRIO) extends TST03-5 + - check the written pmp(i)cfg and pmpaddr(i) values can be read exactly the same as written (before hart reset) +## Feature: CSRs reserved values + +### Sub-feature: 000_access with L=0 + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + + The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved. +* **Verification Goals** + + repeat following sequence several times on some PMP entries + - write totally random values to pmp(i)cfg and pmpaddr(i), but with L=0 + - check all pmp(i)cfg and pmpaddr(i) can be read back exactly the same as written except: + - except with the reserved combinations [R=0 and W=1] + - except with A=NA4 which must not be selectable as G>0 +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F006_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST06 => FTR04-a + [PMP CSR fields are WARL: PMP entry combinations with R=0 and W=1 are reserved/can’t be read] + [permissions fields could be randomly written; should we try randomization ?] + + TST06-1 (HIGH-PRIO) extends TST02-4 + - write totally random values to pmp(i)cfg and pmpaddr(i) + - check all pmp(i)cfg and pmpaddr(i) can be read exactly the same as written except for the reserved combinations with R=0 and W=1 +### Sub-feature: 001_access with L=1 + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + + The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved. +* **Verification Goals** + + repeat following sequence several times on some PMP entries + - write totally random values to pmp(i)cfg and pmpaddr(i), but with L=1 + - check all pmp(i)cfg and pmpaddr(i) can be read back exactly the same as written: + - except with the reserved combinations [R=0 and W=1] + - except with A=NA4 which must not be selectable as G>0 + - apply hart reset +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F006_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST06 => FTR04-a + [PMP CSR fields are WARL: PMP entry combinations with R=0 and W=1 are reserved/can’t be read] + [permissions fields could be randomly written; should we try randomization ?] + + TST06-2 (LOW-PRIO) extends TST03-5 + - write totally random values to pmp(i)cfg and pmpaddr(i) + - check all pmp(i)cfg and pmpaddr(i) can be read exactly the same as written except for the reserved combinations with R=0 and W=1 (before hart reset) +## Feature: no cfg matching/defined + +### Sub-feature: 000_no matching entry - M mode access + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + + If no PMP entry matches an M-mode access, the access succeeds +* **Verification Goals** + + check M-mode access succeeds if no PMP entry matches +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F010_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR09-e + [If no PMP entry matches an M-mode access, the access succeeds] + + TST10-1 (HIGH-PRIO) => FTR09-e + [check M-mode access succeeds if no PMP entry matches] +### Sub-feature: 001_no defined entry - M mode access + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + + If no PMP entry matches an M-mode access, the access succeeds + QUESTION: what happens if no PMP entry is implemented ? + ASSUMPTION: access succeeds +* **Verification Goals** + + check M-mode access succeeds if no PMP entry defined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F010_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR09-e-question + [what happens if no PMP entry is implemented ?] + + TST10-2 (HIGH-PRIO) => FTR09-e-question + [check M-mode access succeeds if no PMP entry defined] +### Sub-feature: 002_no matching entry - S/U mode access + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + + If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails +* **Verification Goals** + + check S or U mode access fails when no PMP entry matching and at least one PMP entry implemented +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F010_S003_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR09-f + [If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails] + + TST10-3 (HIGH-PRIO) => FTR09-f + [check S or U mode access fails when no PMP entry matching and at least one PMP entry implemented] +### Sub-feature: 003_no defined entry - S/U mode access + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + + If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails + QUESTION: what happens if no PMP entry is implemented ? + ASSUMPTION: access fails +* **Verification Goals** + + check S or U mode access fails when no PMP entry implemented +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F010_S004_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR09-f-question + [what happens if no PMP entry is implemented ?] + + TST10-4 (HIGH-PRIO) => FTR09-f-question + [check S or U mode access fails when no PMP entry implemented] +## Feature: cfg NA4 access S/U (G=0) + +### Sub-feature: 000_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access instruction fetch inside defined NA4 address range with execute permissions and with L=0 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S011_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-1x(group) => FTR01-d + [PMP check on instruction fetch where effective privilege mode is S or U: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in S and U mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-11 (HIGH-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 001_fetch_L0_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception +* **Verification Goals** + + S or U mode single access instruction fetch inside defined NA4 address range without execute permissions and with L=0 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=0, L=0, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from that region (with exact address-matching) + + CHECK + - check instruction fetch access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S012_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + TST11-1x(group) => FTR01-d + [PMP check on instruction fetch where effective privilege mode is S or U: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in S and U mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-12 (MEDIUM-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check instruction fetch access-fault exception raised => FTR04-b] +### Sub-feature: 002_fetch_L0_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access instruction fetch from outside defined NA4 address range with execute permissions and with L=0 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from outside all PMP defined regions + + CHECK + - check instruction fetch access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S013_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-1x(group) => FTR01-d + [PMP check on instruction fetch where effective privilege mode is S or U: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in S and U mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-13 (MEDIUM-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from outside all PMP defined regions + - check instruction fetch access-fault exception raised] +### Sub-feature: 003_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access instruction fetch inside defined NA4 address range with execute permissions and with L=1 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S014_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + + TST11-1x(group) => FTR01-d + [PMP check on instruction fetch where effective privilege mode is S or U: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in S and U mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-14 (LOW-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 004_fetch_L1_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception +* **Verification Goals** + + S or U mode single access instruction fetch inside defined NA4 address range without execute permissions and with L=1 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=0, L=1, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from that region (with exact address-matching) + + CHECK + - check instruction fetch access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S015_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + TST11-1x(group) => FTR01-d + [PMP check on instruction fetch where effective privilege mode is S or U: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in S and U mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-15 (LOW-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check instruction fetch access-fault exception raised => FTR04-b] +### Sub-feature: 005_fetch_L1_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access instruction fetch from outside defined NA4 address range with execute permissions and with L=1 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from outside all PMP defined regions + + CHECK + - check instruction fetch access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S016_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + TST11-1x(group) => FTR01-d + [PMP check on instruction fetch where effective privilege mode is S or U: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in S and U mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-16 (LOW-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from outside all PMP defined regions + - check instruction fetch access-fault exception raised] +### Sub-feature: 006_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access load or load-reserved instruction inside defined NA4 address range with read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S021_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-2x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-21 (HIGH-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 007_load_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception +* **Verification Goals** + + S or U mode single access load or load-reserved instruction inside defined NA4 address range without read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=0, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S022_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + TST11-2x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-22 (MEDIUM-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +### Sub-feature: 008_load_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access load or load-reserved instruction from outside defined NA4 address range with read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from outside all PMP defined regions + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S023_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-2x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-23 (MEDIUM-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check load access-fault exception raised] +### Sub-feature: 009_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access load or load-reserved instruction inside defined NA4 address range with read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S024_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + TST11-2x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-24 (LOW-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 010_load_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception +* **Verification Goals** + + S or U mode single access load or load-reserved instruction inside defined NA4 address range without read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=0, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S025_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + TST11-2x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-25 (LOW-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +### Sub-feature: 011_load_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access load or load-reserved instruction from outside defined NA4 address range with read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from outside all PMP defined regions + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S026_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + TST11-2x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-26 (LOW-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check load access-fault exception raised] +### Sub-feature: 012_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction inside defined NA4 address range with write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S031_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-3x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-31 (HIGH-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 013_store_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction inside defined NA4 address range without write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=0, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S032_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + TST11-3x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-32 (MEDIUM-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +### Sub-feature: 014_store_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction from outside defined NA4 address range with write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S033_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-3x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-33 (MEDIUM-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check store access-fault exception raised] +### Sub-feature: 015_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction inside defined NA4 address range with write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S034_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + TST11-3x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-34 (LOW-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 016_store_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction inside defined NA4 address range without write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=0, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S035_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + TST11-3x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-35 (LOW-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +### Sub-feature: 017_store_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction from outside defined NA4 address range with write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S036_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + TST11-3x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in S and U mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-36 (LOW-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check store access-fault exception raised] +### Sub-feature: 018_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access load or load-reserved instruction inside defined NA4 address range with read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S041_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-4x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-41 (LOWEST-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 019_load_MPP_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception +* **Verification Goals** + + S or U mode single access load or load-reserved instruction inside defined NA4 address range without read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=0, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S042_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + TST11-4x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-42 (LOWEST-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +### Sub-feature: 020_load_MPP_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access load or load-reserved instruction from outside defined NA4 address range with read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a load or load-reserved instruction from outside all PMP defined regions + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S043_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-4x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-43 (LOWEST-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check load access-fault exception raised] +### Sub-feature: 021_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access load or load-reserved instruction inside defined NA4 address range with read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S044_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + TST11-4x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-44 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 022_load_MPP_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception +* **Verification Goals** + + S or U mode single access load or load-reserved instruction inside defined NA4 address range without read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=0, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S045_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + TST11-4x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-45 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +### Sub-feature: 023_load_MPP_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access load or load-reserved instruction from outside defined NA4 address range with read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a load or load-reserved instruction from outside all PMP defined regions + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S046_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + TST11-4x(group) => FTR01-d + [PMP check on load or load-reserved instruction where effective privilege mode is S or U: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-46 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check load access-fault exception raised] +### Sub-feature: 024_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction inside defined NA4 address range with write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S051_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-5x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-51 (LOWEST-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 025_store_MPP_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction inside defined NA4 address range without write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=0, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S052_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + TST11-5x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-52 (LOWEST-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +### Sub-feature: 026_store_MPP_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, the R/W/X permissions apply only to S and U modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction from outside defined NA4 address range with write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S053_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + TST11-5x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-53 (LOWEST-PRIO) + [with L=0 => FTR08-e2-2 (refers to FTR09-d2-2), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check store access-fault exception raised] +### Sub-feature: 027_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction inside defined NA4 address range with write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S054_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + TST11-5x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-54 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 028_store_MPP_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction inside defined NA4 address range without write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=0, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S055_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + TST11-5x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-55 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +### Sub-feature: 029_store_MPP_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks are applied to all accesses whose effective privilege mode is S or U + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + Locked PMP entries remain locked until the hart is reset +* **Verification Goals** + + S or U mode single access store, store-conditional, or AMO instruction from outside defined NA4 address range with write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains S or U + + ACCESS + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F011_S056_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + FTR08-b + [Locked PMP entries remain locked until the hart is reset] + + TST11-5x(group) => FTR01-d + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is S or U: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains S or U] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST11-56 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check store access-fault exception raised] +## Feature: cfg NA4 access M (G=0) + +### Sub-feature: 000_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access instruction fetch inside defined NA4 address range with execute permissions and with L=0 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S011_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-1x(group) => FTR01-f + [PMP check on instruction fetch where effective privilege mode is M: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in M mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-11 (LOW-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 001_fetch_L0_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access instruction fetch inside defined NA4 address range without execute permissions and with L=0 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=0, L=0, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S012_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-1x(group) => FTR01-f + [PMP check on instruction fetch where effective privilege mode is M: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in M mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-12 (LOW-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1), + - configure the PMP entry without execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 002_fetch_L0_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access instruction fetch from outside defined NA4 address range with execute permissions and with L=0 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=1, L=0, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S013_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-1x(group) => FTR01-f + [PMP check on instruction fetch where effective privilege mode is M: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in M mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-13 (LOW-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +### Sub-feature: 003_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access instruction fetch inside defined NA4 address range with execute permissions and with L=1 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S014_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-1x(group) => FTR01-f + [PMP check on instruction fetch where effective privilege mode is M: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in M mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-14 (HIGH-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 004_fetch_L1_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception +* **Verification Goals** + + M mode single access instruction fetch inside defined NA4 address range without execute permissions and with L=1 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=0, L=1, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from that region (with exact address-matching) + + CHECK + - check instruction fetch access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S015_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-1x(group) => FTR01-f + [PMP check on instruction fetch where effective privilege mode is M: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in M mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-15 (MEDIUM-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without execute permissions for the PMP region + - fetch an instruction from that region (with exact address-matching) + - check instruction fetch access-fault exception raised => FTR04-b] +### Sub-feature: 005_fetch_L1_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access instruction fetch from outside defined NA4 address range with execute permissions and with L=1 + - choose an executable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, X=1, L=1, R/W:random, with reserve on R=0 & W=1 + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - fetch an instruction from outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S016_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-1x(group) => FTR01-f + [PMP check on instruction fetch where effective privilege mode is M: + - choose an executable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access instruction fetch in M mode] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-16 (HIGH-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with execute permissions for the PMP region + - fetch an instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +### Sub-feature: 006_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access load or load-reserved instruction inside defined NA4 address range with read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S021_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-2x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-21 (LOW-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 007_load_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access load or load-reserved instruction inside defined NA4 address range without read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=0, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S022_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-2x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-22 (LOW-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 008_load_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access load or load-reserved instruction from outside defined NA4 address range with read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S023_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-2x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-23 (LOW-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +### Sub-feature: 009_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access load or load-reserved instruction inside defined NA4 address range with read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S024_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-2x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-24 (HIGH-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 010_load_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception +* **Verification Goals** + + M mode single access load or load-reserved instruction inside defined NA4 address range without read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=0, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S025_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-2x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-25 (MEDIUM-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +### Sub-feature: 011_load_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access load or load-reserved instruction from outside defined NA4 address range with read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a load or load-reserved instruction from outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S026_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-2x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-26 (HIGH-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +### Sub-feature: 012_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction inside defined NA4 address range with write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S031_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-3x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-31 (LOW-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 013_store_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction inside defined NA4 address range without write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=0, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S032_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-3x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-32 (LOW-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 014_store_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction from outside defined NA4 address range with write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S033_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-3x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-33 (LOW-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +### Sub-feature: 015_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction inside defined NA4 address range with write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S034_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-3x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-34 (HIGH-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 016_store_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction inside defined NA4 address range without write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=0, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S035_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-3x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-35 (MEDIUM-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +### Sub-feature: 017_store_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction from outside defined NA4 address range with write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=0 + + ACCESS + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S036_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-3x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in M mode when the bit mstatus.MPRV=0] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-36 (HIGH-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +### Sub-feature: 018_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access load or load-reserved instruction inside defined NA4 address range with read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S041_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-4x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-41 (LOWEST-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 019_load_MPP_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access load or load-reserved instruction inside defined NA4 address range without read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=0, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S042_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-4x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-42 (LOWEST-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 020_load_MPP_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access load or load-reserved instruction from outside defined NA4 address range with read permissions and with L=0 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=0, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a load or load-reserved instruction from outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S043_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-4x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-43 (LOWEST-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +### Sub-feature: 021_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access load or load-reserved instruction inside defined NA4 address range with read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S044_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-4x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-44 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 022_load_MPP_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception +* **Verification Goals** + + M mode single access load or load-reserved instruction inside defined NA4 address range without read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=0, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a load or load-reserved instruction from that region (with exact address-matching) + + CHECK + - check load access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S045_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-4x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-45 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without read permissions for the PMP region + - execute a load or load-reserved instruction from that region (with exact address-matching) + - check load access-fault exception raised => FTR04-c] +### Sub-feature: 023_load_MPP_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access load or load-reserved instruction from outside defined NA4 address range with read permissions and with L=1 + - choose a readable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, R=1, L=1, X/W:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a load or load-reserved instruction from outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S046_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-4x(group) => FTR01-f + [PMP check on load or load-reserved instruction where effective privilege mode is M: + - choose a data readable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data load in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-46 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with read permissions for the PMP region + - execute a load or load-reserved instruction from outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +### Sub-feature: 024_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction inside defined NA4 address range with write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S051_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-5x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-51 (LOWEST-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 025_store_MPP_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction inside defined NA4 address range without write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=0, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S052_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-5x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-52 (LOWEST-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 026_store_MPP_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is clear, any M-mode access matching the PMP entry will succeed + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + If the L bit is clear and the privilege mode of the access is M, the access succeeds +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction from outside defined NA4 address range with write permissions and with L=0 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=0, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S053_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-5x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-53 (LOWEST-PRIO) + [with L=0 => FTR08-e2-1 (refers to FTR09-d1) + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +### Sub-feature: 027_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction inside defined NA4 address range with write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check no access-fault exception + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S054_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-5x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-54 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check no access-fault exception] +### Sub-feature: 028_store_MPP_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set + + {Page 58 Volume II: RISC-V Privileged Architectures V20211203} + Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction inside defined NA4 address range without write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=0, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + + CHECK + - check store access-fault exception raised + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S055_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-5x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-55 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry without write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to that region (with exact address-matching) + - check store access-fault exception raised => FTR04-d] +### Sub-feature: 029_store_MPP_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 56 Volume II: RISC-V Privileged Architectures V20211203} + PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset + + {Page 60 Section "Locking and Privilege Mode" Volume II: RISC-V Privileged Architectures V20211203} + When the L bit is set, these permissions are enforced for all privilege modes + + {Page 60 Section "Priority and Matching Logic" Volume II: RISC-V Privileged Architectures V20211203} + if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set +* **Verification Goals** + + M mode single access store, store-conditional, or AMO instruction from outside defined NA4 address range with write permissions and with L=1 + - choose a data writable pmp region and address range + - choose only one PMP entry (i) + + CONFIGURATION + - pmpcfg(i): A=NA4, W=1, L=1, X/R:random + - pmpaddr(i): NA4 address range + - mstatus.MPRV=1 and mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE) + + ACCESS + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + + CHECK + - check no access-fault exception (Feature: "no cfg matching") + + REUSABILITY + - if possible, the PMP entry number (i) is a configurable parameter + - if possible, the PMP entry lock (L) is a configurable parameter + - if possible, the PMP entry permissions (R,W,X) are configurable parameters + - if possible, the PMP entry address-matching mode (A) is a configurable parameter + - if possible, the PMP entry address range (pmpaddr) is a configurable parameter + - if possible, the PMP entry associated access address is a configurable parameter + - so a single CONFIGURATION function and a single ACCESS function can be reused and combined +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F012_S056_I000 +* **Link to Coverage:** +* **Comments** + + <> + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + TST12-5x(group) => FTR01-f + [PMP check on store, store-conditional, or AMO instruction where effective privilege mode is M: + - choose a data writable pmp region and address range + - choose only one PMP entry (i) ([FTR02-b1]: maybe mandatorily the 1st one) + - if possible, the PMP entry number is a configurable parameter + - choose pmpcfg(i).A=NA4 + - single access data store in any mode when the bit mstatus.MPRV=1 and the mstatus.MPP contains M (TODO: CHECK IF MAKING SENSE)] + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST12-56 (LOWEST-PRIO) + [with L=1 => FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1), + - configure the PMP entry with write permissions for the PMP region + - execute a store, store-conditional, or AMO instruction to outside all PMP defined regions + - check no access-fault exception] //TODO: CHECK IF M-MODE ALLOWED +## Feature: cfg NAPOT access S/U + +### Sub-feature: 000_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S011_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S011_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S011_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT] + TST13-11 (HIGH-PRIO) + [same as TST11-11(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 001_fetch_L0_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S012_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S012_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S012_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + + TST13-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT] + TST13-12 (MEDIUM-PRIO) + [same as TST11-12(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 002_fetch_L0_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S013_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S013_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S013_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT] + TST13-13 (MEDIUM-PRIO) + [same as TST11-13(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 003_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S014_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S014_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S014_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT] + TST13-14 (LOW-PRIO) + [same as TST11-14(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 004_fetch_L1_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S015_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S015_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S015_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + + TST13-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT] + TST13-15 (LOW-PRIO) + [same as TST11-15(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 005_fetch_L1_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S016_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S016_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S016_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=NAPOT] + TST13-16 (LOW-PRIO) + [same as TST11-16(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 006_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S021_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S021_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S021_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT] + TST13-21 (HIGH-PRIO) + [same as TST11-21(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 007_load_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S022_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S022_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S022_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST13-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT] + TST13-22 (MEDIUM-PRIO) + [same as TST11-22(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 008_load_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S023_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S023_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S023_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT] + TST13-23 (MEDIUM-PRIO) + [same as TST11-23(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 009_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S024_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S024_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S024_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT] + TST13-24 (LOW-PRIO) + [same as TST11-24(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 010_load_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S025_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S025_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S025_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST13-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT] + TST13-25 (LOW-PRIO) + [same as TST11-25(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 011_load_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S026_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S026_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S026_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=NAPOT] + TST13-26 (LOW-PRIO) + [same as TST11-26(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 012_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S031_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S031_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S031_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT] + TST13-31 (HIGH-PRIO) + [same as TST11-31(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 013_store_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S032_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S032_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S032_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST13-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT] + TST13-32 (MEDIUM-PRIO) + [same as TST11-32(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 014_store_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S033_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S033_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S033_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT] + TST13-33 (MEDIUM-PRIO) + [same as TST11-33(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 015_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S034_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S034_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S034_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT] + TST13-34 (LOW-PRIO) + [same as TST11-34(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 016_store_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S035_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S035_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S035_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST13-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT] + TST13-35 (LOW-PRIO) + [same as TST11-35(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 017_store_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S036_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S036_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S036_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=NAPOT] + TST13-36 (LOW-PRIO) + [same as TST11-36(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 018_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S041_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S041_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S041_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT] + TST13-41 (LOWEST-PRIO) + [same as TST11-41(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 019_load_MPP_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S042_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S042_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S042_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST13-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT] + TST13-42 (LOWEST-PRIO) + [same as TST11-42(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 020_load_MPP_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S043_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S043_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S043_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT] + TST13-43 (LOWEST-PRIO) + [same as TST11-43(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 021_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S044_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S044_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S044_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT] + TST13-44 (LOWEST-PRIO) + [same as TST11-44(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 022_load_MPP_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S045_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S045_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S045_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST13-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT] + TST13-45 (LOWEST-PRIO) + [same as TST11-45(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 023_load_MPP_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S046_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S046_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S046_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=NAPOT] + TST13-46 (LOWEST-PRIO) + [same as TST11-46(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 024_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S051_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S051_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S051_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT] + TST13-51 (LOWEST-PRIO) + [same as TST11-51(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 025_store_MPP_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S052_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S052_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S052_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST13-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT] + TST13-52 (LOWEST-PRIO) + [same as TST11-52(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 026_store_MPP_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S053_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S053_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S053_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT] + TST13-53 (LOWEST-PRIO) + [same as TST11-53(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 027_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S054_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S054_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S054_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT] + TST13-54 (LOWEST-PRIO) + [same as TST11-54(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 028_store_MPP_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S055_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S055_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S055_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST13-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT] + TST13-55 (LOWEST-PRIO) + [same as TST11-55(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 029_store_MPP_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S056_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S056_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F013_S056_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST13-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=NAPOT] + TST13-56 (LOWEST-PRIO) + [same as TST11-56(group), but with pmpcfg(i).A=NAPOT] +## Feature: cfg NAPOT access M + +### Sub-feature: 000_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S011_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S011_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S011_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT] + TST14-11 (LOW-PRIO) + [same as TST12-11(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 001_fetch_L0_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S012_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S012_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S012_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT] + TST14-12 (LOW-PRIO) + [same as TST12-12(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 002_fetch_L0_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S013_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S013_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S013_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT] + TST14-13 (LOW-PRIO) + [same as TST12-13(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 003_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S014_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S014_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S014_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT] + TST14-14 (HIGH-PRIO) + [same as TST12-14(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 004_fetch_L1_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S015_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S015_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S015_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT] + TST14-15 (MEDIUM-PRIO) + [same as TST12-15(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 005_fetch_L1_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S016_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S016_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S016_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=NAPOT] + TST14-16 (HIGH-PRIO) + [same as TST12-16(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 006_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S021_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S021_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S021_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT] + TST14-21 (LOW-PRIO) + [same as TST12-21(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 007_load_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S022_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S022_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S022_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT] + TST14-22 (LOW-PRIO) + [same as TST12-22(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 008_load_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S023_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S023_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S023_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT] + TST14-23 (LOW-PRIO) + [same as TST12-23(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 009_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S024_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S024_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S024_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT] + TST14-24 (HIGH-PRIO) + [same as TST12-24(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 010_load_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S025_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S025_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S025_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT] + TST14-25 (MEDIUM-PRIO) + [same as TST12-25(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 011_load_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S026_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S026_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S026_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=NAPOT] + TST14-26 (HIGH-PRIO) + [same as TST12-26(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 012_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S031_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S031_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S031_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT] + TST14-31 (LOW-PRIO) + [same as TST12-31(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 013_store_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S032_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S032_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S032_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT] + TST14-32 (LOW-PRIO) + [same as TST12-32(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 014_store_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S033_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S033_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S033_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT] + TST14-33 (LOW-PRIO) + [same as TST12-33(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 015_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S034_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S034_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S034_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT] + TST14-34 (HIGH-PRIO) + [same as TST12-34(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 016_store_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S035_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S035_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S035_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT] + TST14-35 (MEDIUM-PRIO) + [same as TST12-35(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 017_store_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S036_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S036_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S036_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=NAPOT] + TST14-36 (HIGH-PRIO) + [same as TST12-36(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 018_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S041_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S041_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S041_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT] + TST14-41 (LOWEST-PRIO) + [same as TST12-41(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 019_load_MPP_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S042_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S042_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S042_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT] + TST14-42 (LOWEST-PRIO) + [same as TST12-42(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 020_load_MPP_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S043_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S043_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S043_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT] + TST14-43 (LOWEST-PRIO) + [same as TST12-43(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 021_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S044_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S044_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S044_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT] + TST14-44 (LOWEST-PRIO) + [same as TST12-44(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 022_load_MPP_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S045_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S045_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S045_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT] + TST14-45 (LOWEST-PRIO) + [same as TST12-45(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 023_load_MPP_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S046_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S046_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S046_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=NAPOT] + TST14-46 (LOWEST-PRIO) + [same as TST12-46(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 024_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S051_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S051_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S051_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT] + TST14-51 (LOWEST-PRIO) + [same as TST12-51(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 025_store_MPP_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S052_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S052_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S052_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT] + TST14-52 (LOWEST-PRIO) + [same as TST12-52(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 026_store_MPP_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S053_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S053_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S053_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT] + TST14-53 (LOWEST-PRIO) + [same as TST12-53(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 027_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S054_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S054_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S054_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT] + TST14-54 (LOWEST-PRIO) + [same as TST12-54(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 028_store_MPP_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S055_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S055_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S055_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT] + TST14-55 (LOWEST-PRIO) + [same as TST12-55(group), but with pmpcfg(i).A=NAPOT] +### Sub-feature: 029_store_MPP_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S056_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S056_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=NAPOT + - pmpaddr(i): any NAPOT address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F014_S056_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST14-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=NAPOT] + TST14-56 (LOWEST-PRIO) + [same as TST12-56(group), but with pmpcfg(i).A=NAPOT] +## Feature: cfg TOR access S/U + +### Sub-feature: 000_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S011_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S011_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S011_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=TOR] + TST15-11 (HIGH-PRIO) + [same as TST11-11(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 001_fetch_L0_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S012_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S012_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S012_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + + TST15-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=TOR] + TST15-12 (MEDIUM-PRIO) + [same as TST11-12(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 002_fetch_L0_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S013_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S013_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S013_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=TOR] + TST15-13 (MEDIUM-PRIO) + [same as TST11-13(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 003_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S014_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S014_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S014_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=TOR] + TST15-14 (LOW-PRIO) + [same as TST11-14(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 004_fetch_L1_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S015_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S015_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S015_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + + TST15-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=TOR] + TST15-15 (LOW-PRIO) + [same as TST11-15(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 005_fetch_L1_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S016_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S016_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S016_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=TOR] + TST15-16 (LOW-PRIO) + [same as TST11-16(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 006_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S021_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S021_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S021_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=TOR] + TST15-21 (HIGH-PRIO) + [same as TST11-21(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 007_load_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S022_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S022_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S022_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST15-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=TOR] + TST15-22 (MEDIUM-PRIO) + [same as TST11-22(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 008_load_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S023_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S023_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S023_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=TOR] + TST15-23 (MEDIUM-PRIO) + [same as TST11-23(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 009_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S024_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S024_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S024_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=TOR] + TST15-24 (LOW-PRIO) + [same as TST11-24(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 010_load_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S025_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S025_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S025_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST15-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=TOR] + TST15-25 (LOW-PRIO) + [same as TST11-25(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 011_load_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S026_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S026_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S026_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=TOR] + TST15-26 (LOW-PRIO) + [same as TST11-26(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 012_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S031_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S031_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S031_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=TOR] + TST15-31 (HIGH-PRIO) + [same as TST11-31(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 013_store_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S032_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S032_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S032_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST15-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=TOR] + TST15-32 (MEDIUM-PRIO) + [same as TST11-32(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 014_store_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S033_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S033_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S033_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=TOR] + TST15-33 (MEDIUM-PRIO) + [same as TST11-33(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 015_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S034_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S034_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S034_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=TOR] + TST15-34 (LOW-PRIO) + [same as TST11-34(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 016_store_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S035_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S035_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S035_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST15-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=TOR] + TST15-35 (LOW-PRIO) + [same as TST11-35(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 017_store_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S036_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S036_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S036_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=TOR] + TST15-36 (LOW-PRIO) + [same as TST11-36(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 018_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S041_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S041_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S041_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=TOR] + TST15-41 (LOWEST-PRIO) + [same as TST11-41(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 019_load_MPP_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S042_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S042_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S042_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST15-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=TOR] + TST15-42 (LOWEST-PRIO) + [same as TST11-42(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 020_load_MPP_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S043_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S043_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S043_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=TOR] + TST15-43 (LOWEST-PRIO) + [same as TST11-43(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 021_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S044_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S044_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S044_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=TOR] + TST15-44 (LOWEST-PRIO) + [same as TST11-44(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 022_load_MPP_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S045_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S045_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S045_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST15-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=TOR] + TST15-45 (LOWEST-PRIO) + [same as TST11-45(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 023_load_MPP_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S046_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S046_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S046_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=TOR] + TST15-46 (LOWEST-PRIO) + [same as TST11-46(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 024_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S051_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S051_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S051_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=TOR] + TST15-51 (LOWEST-PRIO) + [same as TST11-51(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 025_store_MPP_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S052_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S052_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S052_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST15-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=TOR] + TST15-52 (LOWEST-PRIO) + [same as TST11-52(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 026_store_MPP_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S053_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S053_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S053_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=TOR] + TST15-53 (LOWEST-PRIO) + [same as TST11-53(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 027_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S054_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S054_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S054_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=TOR] + TST15-54 (LOWEST-PRIO) + [same as TST11-54(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 028_store_MPP_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S055_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S055_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S055_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST15-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=TOR] + TST15-55 (LOWEST-PRIO) + [same as TST11-55(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 029_store_MPP_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S056_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S056_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S056_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=TOR] + TST15-56 (LOWEST-PRIO) + [same as TST11-56(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 030_fetch_L0_X1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S011_I000 feature description (Cf. Feature: "cfg NA4 access S/U") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F011_S011_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) + + CHECK UPDATE + - check instruction fetch access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S061_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=TOR] + TST15-11 (LOW-PRIO) + [same as TST11-11(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 031_fetch_L1_X1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S014_I000 feature description (Cf. Feature: "cfg NA4 access S/U") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F011_S014_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) + + CHECK UPDATE + - check instruction fetch access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S062_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=TOR] + TST15-14 (LOW-PRIO) + [same as TST11-14(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 032_load_L0_R1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S021_I000 feature description (Cf. Feature: "cfg NA4 access S/U") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F011_S021_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S063_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=TOR] + TST15-21 (HIGH-PRIO) + [same as TST11-21(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 033_load_L1_R1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S024_I000 feature description (Cf. Feature: "cfg NA4 access S/U") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F011_S024_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S064_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=TOR] + TST15-24 (LOW-PRIO) + [same as TST11-24(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 034_store_L0_W1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S031_I000 feature description (Cf. Feature: "cfg NA4 access S/U") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F011_S031_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S065_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=TOR] + TST15-31 (HIGH-PRIO) + [same as TST11-31(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 035_store_L1_W1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S034_I000 feature description (Cf. Feature: "cfg NA4 access S/U") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F011_S034_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F015_S066_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST15-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=TOR] + TST15-34 (LOW-PRIO) + [same as TST11-34(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +## Feature: cfg TOR access M + +### Sub-feature: 000_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S011_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S011_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S011_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=TOR] + TST16-11 (LOW-PRIO) + [same as TST12-11(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 001_fetch_L0_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S012_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S012_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S012_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=TOR] + TST16-12 (LOW-PRIO) + [same as TST12-12(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 002_fetch_L0_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S013_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S013_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S013_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=TOR] + TST16-13 (LOW-PRIO) + [same as TST12-13(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 003_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S014_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S014_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S014_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=TOR] + TST16-14 (HIGH-PRIO) + [same as TST12-14(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 004_fetch_L1_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S015_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S015_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S015_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=TOR] + TST16-15 (MEDIUM-PRIO) + [same as TST12-15(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 005_fetch_L1_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S016_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S016_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S016_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=TOR] + TST16-16 (HIGH-PRIO) + [same as TST12-16(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 006_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S021_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S021_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S021_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=TOR] + TST16-21 (LOW-PRIO) + [same as TST12-21(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 007_load_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S022_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S022_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S022_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=TOR] + TST16-22 (LOW-PRIO) + [same as TST12-22(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 008_load_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S023_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S023_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S023_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=TOR] + TST16-23 (LOW-PRIO) + [same as TST12-23(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 009_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S024_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S024_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S024_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=TOR] + TST16-24 (HIGH-PRIO) + [same as TST12-24(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 010_load_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S025_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S025_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S025_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=TOR] + TST16-25 (MEDIUM-PRIO) + [same as TST12-25(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 011_load_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S026_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S026_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S026_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=TOR] + TST16-26 (HIGH-PRIO) + [same as TST12-26(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 012_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S031_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S031_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S031_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=TOR] + TST16-31 (LOW-PRIO) + [same as TST12-31(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 013_store_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S032_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S032_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S032_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=TOR] + TST16-32 (LOW-PRIO) + [same as TST12-32(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 014_store_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S033_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S033_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S033_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=TOR] + TST16-33 (LOW-PRIO) + [same as TST12-33(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 015_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S034_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S034_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S034_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=TOR] + TST16-34 (HIGH-PRIO) + [same as TST12-34(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 016_store_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S035_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S035_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S035_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=TOR] + TST16-35 (MEDIUM-PRIO) + [same as TST12-35(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 017_store_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S036_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S036_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S036_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=TOR] + TST16-36 (HIGH-PRIO) + [same as TST12-36(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 018_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S041_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S041_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S041_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=TOR] + TST16-41 (LOWEST-PRIO) + [same as TST12-41(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 019_load_MPP_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S042_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S042_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S042_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=TOR] + TST16-42 (LOWEST-PRIO) + [same as TST12-42(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 020_load_MPP_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S043_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S043_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S043_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=TOR] + TST16-43 (LOWEST-PRIO) + [same as TST12-43(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 021_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S044_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S044_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S044_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=TOR] + TST16-44 (LOWEST-PRIO) + [same as TST12-44(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 022_load_MPP_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S045_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S045_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S045_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=TOR] + TST16-45 (LOWEST-PRIO) + [same as TST12-45(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 023_load_MPP_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S046_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S046_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S046_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=TOR] + TST16-46 (LOWEST-PRIO) + [same as TST12-46(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 024_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S051_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S051_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S051_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=TOR] + TST16-51 (LOWEST-PRIO) + [same as TST12-51(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 025_store_MPP_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S052_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S052_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S052_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=TOR] + TST16-52 (LOWEST-PRIO) + [same as TST12-52(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 026_store_MPP_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S053_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S053_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S053_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=TOR] + TST16-53 (LOWEST-PRIO) + [same as TST12-53(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 027_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S054_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S054_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S054_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=TOR] + TST16-54 (LOWEST-PRIO) + [same as TST12-54(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 028_store_MPP_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S055_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S055_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S055_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=TOR] + TST16-55 (LOWEST-PRIO) + [same as TST12-55(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 029_store_MPP_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S056_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S056_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i) > pmpaddr(i-1): any TOR address range + - [for i=0] pmpaddr(0) > 0: any TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S056_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=TOR] + TST16-56 (LOWEST-PRIO) + [same as TST12-56(group), but with pmpcfg(i).A=TOR] +### Sub-feature: 030_fetch_L0_X1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S011_I000 feature description (Cf. Feature: "cfg NA4 access M") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F012_S011_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S061_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=TOR] + TST16-11 (LOW-PRIO) + [same as TST12-11(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 031_fetch_L1_X1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S014_I000 feature description (Cf. Feature: "cfg NA4 access M") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F012_S014_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S062_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=TOR] + TST16-14 (LOW-PRIO) + [same as TST12-14(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 032_load_L0_R1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S021_I000 feature description (Cf. Feature: "cfg NA4 access M") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F012_S021_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S063_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=TOR] + TST16-21 (HIGH-PRIO) + [same as TST12-21(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 033_load_L1_R1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S024_I000 feature description (Cf. Feature: "cfg NA4 access M") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F012_S024_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S064_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=TOR] + TST16-24 (LOW-PRIO) + [same as TST12-24(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 034_store_L0_W1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S031_I000 feature description (Cf. Feature: "cfg NA4 access M") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F012_S031_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S065_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=TOR] + TST16-31 (HIGH-PRIO) + [same as TST12-31(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +### Sub-feature: 035_store_L1_W1_addr_forbidden + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S034_I000 feature description (Cf. Feature: "cfg NA4 access M") + + {Page 59 Volume II: RISC-V Privileged Architectures V20211203} + If pmpaddri−1 ≥ pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses + If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr(0) +* **Verification Goals** + + reuse of VP_PMP_F012_S034_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=TOR + - [for i>0] pmpaddr(i-1) > pmpaddr(i): invalid TOR address range + - [for i=0] pmpaddr(0) = 0: invalid TOR address range + - [for j=unused] pmpaddr(j)=random: only in single entry configuration case (not in reuse case) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F016_S066_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST16-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=TOR] + TST16-34 (LOW-PRIO) + [same as TST12-34(group), but with pmpcfg(i).A=TOR] + + + //TO COMPLETE => FTR06-b + TST25 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) > 0 + TST26 = same as TST15+TST16 (groups) with PMP entry (0) with pmpaddr(0) = 0 + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) > 0 + - pmpaddr(0) = 0] + + //TO COMPLETE => FTR06-c + TST27 = same as TST23-2 but with pmpaddr(i) ≤ pmpaddr(i-1) and with pmpcfg(i) and pmpcfg(i-1) correct + [create scenario where PMP entry pmpcfg(i) with TOR: + - pmpaddr(i) ≤ pmpaddr(i-1) and PMP entry pmpcfg(i-1) correct] + [create scenario where PMP entry pmpcfg(0) with TOR: + - pmpaddr(0) >= pmpaddr(1/2/3/…)] +## Feature: cfg OFF access S/U + +### Sub-feature: 000_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S011_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S011_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check instruction fetch access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S011_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=OFF] + TST17-11 (HIGH-PRIO) + [same as TST11-11(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +### Sub-feature: 001_fetch_L0_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S012_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S012_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S012_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + + TST17-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=OFF] + TST17-12 (MEDIUM-PRIO) + [same as TST11-12(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 002_fetch_L0_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S013_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S013_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S013_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=OFF] + TST17-13 (MEDIUM-PRIO) + [same as TST11-13(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 003_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S014_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S014_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check instruction fetch access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S014_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=OFF] + TST17-14 (LOW-PRIO) + [same as TST11-14(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +### Sub-feature: 004_fetch_L1_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S015_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S015_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S015_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + + TST17-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=OFF] + TST17-15 (LOW-PRIO) + [same as TST11-15(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 005_fetch_L1_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S016_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S016_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S016_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-1x(group) + [same as TST11-1x(group), but with pmpcfg(i).A=OFF] + TST17-16 (LOW-PRIO) + [same as TST11-16(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 006_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S021_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S021_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S021_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=OFF] + TST17-21 (HIGH-PRIO) + [same as TST11-21(group), but with pmpcfg(i).A=OFF + - check load access-fault exception raised] +### Sub-feature: 007_load_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S022_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S022_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S022_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST17-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=OFF] + TST17-22 (MEDIUM-PRIO) + [same as TST11-22(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 008_load_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S023_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S023_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S023_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=OFF] + TST17-23 (MEDIUM-PRIO) + [same as TST11-23(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 009_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S024_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S024_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S024_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=OFF] + TST17-24 (LOW-PRIO) + [same as TST11-24(group), but with pmpcfg(i).A=OFF + - check load access-fault exception raised] +### Sub-feature: 010_load_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S025_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S025_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S025_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST17-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=OFF] + TST17-25 (LOW-PRIO) + [same as TST11-25(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 011_load_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S026_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S026_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S026_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-2x(group) + [same as TST11-2x(group), but with pmpcfg(i).A=OFF] + TST17-26 (LOW-PRIO) + [same as TST11-26(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 012_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S031_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S031_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S031_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=OFF] + TST17-31 (HIGH-PRIO) + [same as TST11-31(group), but with pmpcfg(i).A=OFF + - check store access-fault exception raised] +### Sub-feature: 013_store_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S032_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S032_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S032_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST17-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=OFF] + TST17-32 (MEDIUM-PRIO) + [same as TST11-32(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 014_store_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S033_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S033_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S033_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=OFF] + TST17-33 (MEDIUM-PRIO) + [same as TST11-33(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 015_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S034_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S034_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S034_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=OFF] + TST17-34 (LOW-PRIO) + [same as TST11-34(group), but with pmpcfg(i).A=OFF + - check store access-fault exception raised] +### Sub-feature: 016_store_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S035_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S035_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S035_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST17-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=OFF] + TST17-35 (LOW-PRIO) + [same as TST11-35(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 017_store_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S036_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S036_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S036_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-3x(group) + [same as TST11-3x(group), but with pmpcfg(i).A=OFF] + TST17-36 (LOW-PRIO) + [same as TST11-36(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 018_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S041_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S041_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S041_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=OFF] + TST17-41 (LOWEST-PRIO) + [same as TST11-41(group), but with pmpcfg(i).A=OFF + - check load access-fault exception raised] +### Sub-feature: 019_load_MPP_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S042_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S042_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S042_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST17-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=OFF] + TST17-42 (LOWEST-PRIO) + [same as TST11-42(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 020_load_MPP_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S043_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S043_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S043_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=OFF] + TST17-43 (LOWEST-PRIO) + [same as TST11-43(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 021_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S044_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S044_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S044_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=OFF] + TST17-44 (LOWEST-PRIO) + [same as TST11-44(group), but with pmpcfg(i).A=OFF + - check load access-fault exception raised] +### Sub-feature: 022_load_MPP_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S045_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S045_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S045_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + + TST17-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=OFF] + TST17-45 (LOWEST-PRIO) + [same as TST11-45(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 023_load_MPP_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S046_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S046_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S046_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-4x(group) + [same as TST11-4x(group), but with pmpcfg(i).A=OFF] + TST17-46 (LOWEST-PRIO) + [same as TST11-46(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 024_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S051_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S051_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S051_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=OFF] + TST17-51 (LOWEST-PRIO) + [same as TST11-51(group), but with pmpcfg(i).A=OFF + - check store access-fault exception raised] +### Sub-feature: 025_store_MPP_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S052_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S052_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S052_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST17-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=OFF] + TST17-52 (LOWEST-PRIO) + [same as TST11-52(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 026_store_MPP_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S053_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S053_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S053_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e2-2 (refers to FTR09-d2-2) + [When the L bit is clear, the R/W/X permissions apply only to S and U modes] + FTR09-d2-2 (L=0 refers to FTR08-e2-2) + [if the privilege mode of the access is S or U (whatever L), then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=OFF] + TST17-53 (LOWEST-PRIO) + [same as TST11-53(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 027_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S054_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S054_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S054_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=OFF] + TST17-54 (LOWEST-PRIO) + [same as TST11-54(group), but with pmpcfg(i).A=OFF + - check store access-fault exception raised] +### Sub-feature: 028_store_MPP_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S055_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S055_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S055_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + + TST17-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=OFF] + TST17-55 (LOWEST-PRIO) + [same as TST11-55(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 029_store_MPP_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F011_S056_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F011_S056_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F017_S056_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-d + [PMP checks are applied to all accesses whose effective privilege mode is S or U] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + + TST17-5x(group) + [same as TST11-5x(group), but with pmpcfg(i).A=OFF] + TST17-56 (LOWEST-PRIO) + [same as TST11-56(group), but with pmpcfg(i).A=OFF] +## Feature: cfg OFF access M + +### Sub-feature: 000_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S011_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S011_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S011_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=OFF] + TST18-11 (LOW-PRIO) + [same as TST12-11(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 001_fetch_L0_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S012_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S012_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S012_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=OFF] + TST18-12 (LOW-PRIO) + [same as TST12-12(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 002_fetch_L0_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S013_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S013_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S013_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=OFF] + TST18-13 (LOW-PRIO) + [same as TST12-13(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 003_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S014_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S014_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S014_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=OFF] + TST18-14 (HIGH-PRIO) + [same as TST12-14(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +### Sub-feature: 004_fetch_L1_X0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S015_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S015_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S015_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-b + [Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=OFF] + TST18-15 (MEDIUM-PRIO) + [same as TST12-15(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 005_fetch_L1_X1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S016_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S016_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S016_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-1x(group) + [same as TST12-1x(group), but with pmpcfg(i).A=OFF] + TST18-16 (HIGH-PRIO) + [same as TST12-16(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 006_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S021_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S021_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S021_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=OFF] + TST18-21 (LOW-PRIO) + [same as TST12-21(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 007_load_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S022_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S022_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S022_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=OFF] + TST18-22 (LOW-PRIO) + [same as TST12-22(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 008_load_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S023_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S023_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S023_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=OFF] + TST18-23 (LOW-PRIO) + [same as TST12-23(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 009_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S024_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S024_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S024_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=OFF] + TST18-24 (HIGH-PRIO) + [same as TST12-24(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +### Sub-feature: 010_load_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S025_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S025_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S025_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=OFF] + TST18-25 (MEDIUM-PRIO) + [same as TST12-25(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 011_load_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S026_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S026_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S026_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-2x(group) + [same as TST12-2x(group), but with pmpcfg(i).A=OFF] + TST18-26 (HIGH-PRIO) + [same as TST12-26(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 012_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S031_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S031_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S031_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=OFF] + TST18-31 (LOW-PRIO) + [same as TST12-31(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 013_store_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S032_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S032_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S032_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=OFF] + TST18-32 (LOW-PRIO) + [same as TST12-32(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 014_store_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S033_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S033_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S033_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=OFF] + TST18-33 (LOW-PRIO) + [same as TST12-33(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 015_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S034_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S034_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S034_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=OFF] + TST18-34 (HIGH-PRIO) + [same as TST12-34(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +### Sub-feature: 016_store_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S035_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S035_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S035_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=OFF] + TST18-35 (MEDIUM-PRIO) + [same as TST12-35(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 017_store_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S036_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S036_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S036_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-3x(group) + [same as TST12-3x(group), but with pmpcfg(i).A=OFF] + TST18-36 (HIGH-PRIO) + [same as TST12-36(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 018_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S041_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S041_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S041_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=OFF] + TST18-41 (LOWEST-PRIO) + [same as TST12-41(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 019_load_MPP_L0_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S042_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S042_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S042_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=OFF] + TST18-42 (LOWEST-PRIO) + [same as TST12-42(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 020_load_MPP_L0_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S043_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S043_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S043_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=OFF] + TST18-43 (LOWEST-PRIO) + [same as TST12-43(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 021_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S044_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S044_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S044_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=OFF] + TST18-44 (LOWEST-PRIO) + [same as TST12-44(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +### Sub-feature: 022_load_MPP_L1_R0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S045_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S045_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S045_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-c + [Attempting to execute a load or load-reserved instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=OFF] + TST18-45 (LOWEST-PRIO) + [same as TST12-45(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 023_load_MPP_L1_R1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S046_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S046_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S046_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-4x(group) + [same as TST12-4x(group), but with pmpcfg(i).A=OFF] + TST18-46 (LOWEST-PRIO) + [same as TST12-46(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 024_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S051_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S051_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S051_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=OFF] + TST18-51 (LOWEST-PRIO) + [same as TST12-51(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 025_store_MPP_L0_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S052_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S052_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S052_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=OFF] + TST18-52 (LOWEST-PRIO) + [same as TST12-52(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 026_store_MPP_L0_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S053_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S053_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S053_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e2-1 (refers to FTR09-d1) + [When the L bit is clear, any M-mode access matching the PMP entry will succeed] + FTR09-d1 (refers to FTR08-e2-1) + [If the L bit is clear and the privilege mode of the access is M, the access succeeds] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=OFF] + TST18-53 (LOWEST-PRIO) + [same as TST12-53(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 027_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S054_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S054_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S054_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=OFF] + TST18-54 (LOWEST-PRIO) + [same as TST12-54(group), but with pmpcfg(i).A=OFF + - check instruction fetch access-fault exception raised] +### Sub-feature: 028_store_MPP_L1_W0_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S055_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S055_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S055_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR04-d + [Attempting to execute a store, store-conditional, or AMO instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=OFF] + TST18-55 (LOWEST-PRIO) + [same as TST12-55(group), but with pmpcfg(i).A=OFF] +### Sub-feature: 029_store_MPP_L1_W1_addr_miss + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F012_S056_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F012_S056_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - pmpcfg(i): A=OFF + - pmpaddr(i): NA4 address range +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F018_S056_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + FTR01-f (refers to FTR08-e1) + [PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset] + + FTR08-e1 (refers to FTR01-f) (refers to FTR09-d2-1) + [When the L bit is set, these permissions are enforced for all privilege modes] + FTR09-d2-1 (refers to FTR08-e1) (refers to FTR01-f) + [if the L bit is set, then the access succeeds only if the R, W, or X bit corresponding to the access type is set] + + FTR02-b1 + [the lowest-numbered PMP CSRs must be implemented first (QUESTION: does it mean programmed first)] + + + TST18-5x(group) + [same as TST12-5x(group), but with pmpcfg(i).A=OFF] + TST18-56 (LOWEST-PRIO) + [same as TST12-56(group), but with pmpcfg(i).A=OFF] +## Feature: cfg NA4 not selectable + +### Sub-feature: 000_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S011_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S011_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check instruction fetch access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S011_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S014_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S014_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check instruction fetch access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S014_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S021_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S021_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S021_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 003_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S024_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S024_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S024_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 004_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S031_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S031_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S031_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 005_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S034_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S034_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S034_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 006_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S041_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S041_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S041_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 007_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S044_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S044_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check load access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S044_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 008_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S051_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S051_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S051_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 009_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S054_I000 feature description (Cf. Feature: "cfg NA4 access S/U") +* **Verification Goals** + + reuse of VP_PMP_F019_S054_I000 verification goals (Cf. Feature: "cfg NA4 access S/U") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check store access-fault exception raised +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S054_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 010_fetch_L0_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S011_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S011_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S011_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 011_fetch_L1_X1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S014_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S014_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S014_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 012_load_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S021_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S021_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S021_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 013_load_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S024_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S024_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S024_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 014_store_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S031_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S031_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S031_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 015_store_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S034_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S034_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S034_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 016_load_MPP_L0_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S041_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S041_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S041_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 017_load_MPP_L1_R1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S044_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S044_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S044_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 018_store_MPP_L0_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S051_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S051_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S051_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 019_store_MPP_L1_W1_addr_hit + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of VP_PMP_F019_S054_I000 feature description (Cf. Feature: "cfg NA4 access M") +* **Verification Goals** + + reuse of VP_PMP_F019_S054_I000 verification goals (Cf. Feature: "cfg NA4 access M") + + CONFIGURATION + - check that pmpcfg(i).A=OFF (by reading back) + + CHECK UPDATE + - check store access-fault exception raised (TODO: is M mode access prevented by A=OFF) +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F019_S054_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +## Feature: multi entries NA4 + +### Sub-feature: 000_1_entry + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose a single PMP entry + + CONFIGURATION and ACCESS + - for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: "cfg NA4 access S/U/M") + - make sure the pmp entries address ranges are not overlapping/intersecting + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, we should obtain the expected CHECK result + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F021_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST21(group) + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST21-1 = extension of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-13, TST11-23, TST11-33, TST11-43, TST11-53, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST11-16, TST11-26, TST11-36, TST11-46, TST11-56, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-13, TST12-23, TST12-33, TST12-43, TST12-53, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST12-16, TST12-26, TST12-36, TST12-46, TST12-56) + [configure only one (any, but the first one) PMP entry + - use A=NA4 for the PMP entry configuration + - execute the chosen kind of access + - should be same result] +### Sub-feature: 001_2_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + reuse of VP_PMP_F021_S001_I000 feature description (Cf. Feature: "multi entries NA4") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F021_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST21(group) + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST21-2 = extension of compatible pair of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-13, TST11-23, TST11-33, TST11-43, TST11-53, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST11-16, TST11-26, TST11-36, TST11-46, TST11-56, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-13, TST12-23, TST12-33, TST12-43, TST12-53, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST12-16, TST12-26, TST12-36, TST12-46, TST12-56) + [configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - use A=NA4 for each PMP entry configuration + - execute the 2 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 2 results] +### Sub-feature: 002_N_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any N PMP entries (2> + + TST21(group) + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST21-3 = extension of compatible group(N) of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-13, TST11-23, TST11-33, TST11-43, TST11-53, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST11-16, TST11-26, TST11-36, TST11-46, TST11-56, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-13, TST12-23, TST12-33, TST12-43, TST12-53, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST12-16, TST12-26, TST12-36, TST12-46, TST12-56) + [configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - use A=NA4 for each PMP entry configuration + - execute the N kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same N results] +### Sub-feature: 003_8_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose all 8 PMP entries + + reuse of VP_PMP_F021_S001_I000 feature description (Cf. Feature: "multi entries NA4") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F021_S004_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST21(group) + [create scenarios where PMP entries with A=2 (NA4) and with/without matching permissions + - check only NA4 defined addresses are matching] + TST21-4 = extension of compatible group(8) of (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-13, TST11-23, TST11-33, TST11-43, TST11-53, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST11-16, TST11-26, TST11-36, TST11-46, TST11-56, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-13, TST12-23, TST12-33, TST12-43, TST12-53, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST12-16, TST12-26, TST12-36, TST12-46, TST12-56) + [configure 8 PMP entries (highest-numbered ones first) + - use A=NA4 for each PMP entry configuration + - execute the 8 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 8 results] +### Sub-feature: 004_2_intersecting_entries_fail + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + CONFIGURATION and ACCESS (Cf. Feature: "cfg NA4 access S/U/M") + - for the least-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault + - for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault + - make sure the pmp entries address ranges are overlapping/intersecting (at least at 4 consecutive bytes) + - for each pmp entry, execute one access in its associated pmp address region but outside the overlapping/intersecting address range + - execute one additional access inside the overlapping/intersecting address range + - NB: obviously, pmp entry configurations with different access-modes (S/U vs. M) cannot be easily mixed in same test + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, access outside the overlapping/intersecting address range should give the expected CHECK result + - access inside the overlapping/intersecting address range should generate the access-type related access-fault + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F021_S005_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST51(group) => FTR09-a, FTR09-b and FTR09-c + [create scenarios where 2 PMP entries with same pmpaddr + - one without matching permissions or with A=OFF + - one with matching permissions and A=NA4/NAPOT/TOR + - any of them can be the lowest-numbered PMP entry] + TST51-1 + [configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - configure the highest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - execute the associated access + - check associated access-fault exception raised] +### Sub-feature: 005_2_intersecting_entries_succeed + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + CONFIGURATION and ACCESS (Cf. Feature: "cfg NA4 access S/U/M") + - for the least-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault + - for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault + - make sure the pmp entries address ranges are overlapping/intersecting (at least at 4 consecutive bytes) + - for each pmp entry, execute one access in its associated pmp address region but outside the overlapping/intersecting address range + - execute one additional access inside the overlapping/intersecting address range + - NB: obviously, pmp entry configurations with different access-modes (S/U vs. M) cannot be easily mixed in same test + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, access outside the overlapping/intersecting address range should give the expected CHECK result + - access inside the overlapping/intersecting address range should not generate any access-fault + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F021_S006_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST51(group) => FTR09-a, FTR09-b and FTR09-c + [create scenarios where 2 PMP entries with same pmpaddr + - one without matching permissions or with A=OFF + - one with matching permissions and A=NA4/NAPOT/TOR + - any of them can be the lowest-numbered PMP entry] + TST51-2 + [configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - configure the highest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - execute the associated access + - check no access-fault exception] +## Feature: multi entries NAPOT + +### Sub-feature: 000_1_entry + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose a single PMP entry + + CONFIGURATION and ACCESS + - for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: "cfg NAPOT access S/U/M") + - make sure the pmp entries address ranges are not overlapping/intersecting + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, we should obtain the expected CHECK result + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F022_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST22(group) + [create scenarios where PMP entries with A=3 (NAPOT) and with/without matching permissions + - check only NAPOT defined addresses are matching] + TST22-1 = extension of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-13, TST13-23, TST13-33, TST13-43, TST13-53, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST13-16, TST13-26, TST13-36, TST13-46, TST13-56, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-13, TST14-23, TST14-33, TST14-43, TST14-53, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST14-16, TST14-26, TST14-36, TST14-46, TST14-56) + [configure only one (any, but the first one) PMP entry + - use A=NAPOT for the PMP entry configuration + - execute the chosen kind of access + - should be same result] +### Sub-feature: 001_2_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + reuse of VP_PMP_F022_S001_I000 feature description (Cf. Feature: "multi entries NAPOT") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F022_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST22(group) + [create scenarios where PMP entries with A=3 (NAPOT) and with/without matching permissions + - check only NAPOT defined addresses are matching] + TST22-2 = extension of compatible pair of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-13, TST13-23, TST13-33, TST13-43, TST13-53, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST13-16, TST13-26, TST13-36, TST13-46, TST13-56, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-13, TST14-23, TST14-33, TST14-43, TST14-53, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST14-16, TST14-26, TST14-36, TST14-46, TST14-56) + [configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - use A=NAPOT for each PMP entry configuration + - execute the 2 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 2 results] +### Sub-feature: 002_N_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any N PMP entries (2> + + TST22(group) + [create scenarios where PMP entries with A=3 (NAPOT) and with/without matching permissions + - check only NAPOT defined addresses are matching] + TST22-3 = extension of compatible group(N) of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-13, TST13-23, TST13-33, TST13-43, TST13-53, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST13-16, TST13-26, TST13-36, TST13-46, TST13-56, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-13, TST14-23, TST14-33, TST14-43, TST14-53, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST14-16, TST14-26, TST14-36, TST14-46, TST14-56) + [configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - use A=NAPOT for each PMP entry configuration + - execute the N kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same N results] +### Sub-feature: 003_8_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose all 8 PMP entries + + reuse of VP_PMP_F022_S001_I000 feature description (Cf. Feature: "multi entries NAPOT") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Testcase +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F022_S004_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST22(group) + [create scenarios where PMP entries with A=3 (NAPOT) and with/without matching permissions + - check only NAPOT defined addresses are matching] + TST22-4 = extension of compatible group(8) of (TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-13, TST13-23, TST13-33, TST13-43, TST13-53, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST13-16, TST13-26, TST13-36, TST13-46, TST13-56, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-13, TST14-23, TST14-33, TST14-43, TST14-53, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST14-16, TST14-26, TST14-36, TST14-46, TST14-56) + [configure 8 PMP entries (highest-numbered ones first) + - use A=NAPOT for each PMP entry configuration + - execute the 8 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 8 results] +### Sub-feature: 004_2_intersecting_entries_fail + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + CONFIGURATION and ACCESS (Cf. Feature: "cfg NAPOT access S/U/M") + - for the least-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault + - for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault + - make sure the pmp entries address ranges are overlapping/intersecting (at least at 4 consecutive bytes) + - for each pmp entry, execute one access in its associated pmp address region but outside the overlapping/intersecting address range + - execute one additional access inside the overlapping/intersecting address range + - NB: obviously, pmp entry configurations with different access-modes (S/U vs. M) cannot be easily mixed in same test + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, access outside the overlapping/intersecting address range should give the expected CHECK result + - access inside the overlapping/intersecting address range should generate the access-type related access-fault + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F022_S005_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST51(group) => FTR09-a, FTR09-b and FTR09-c + [create scenarios where 2 PMP entries with same pmpaddr + - one without matching permissions or with A=OFF + - one with matching permissions and A=NA4/NAPOT/TOR + - any of them can be the lowest-numbered PMP entry] + TST51-1 + [configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - configure the highest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - execute the associated access + - check associated access-fault exception raised] +### Sub-feature: 005_2_intersecting_entries_succeed + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + CONFIGURATION and ACCESS (Cf. Feature: "cfg NAPOT access S/U/M") + - for the least-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault + - for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault + - make sure the pmp entries address ranges are overlapping/intersecting (at least at 4 consecutive bytes) + - for each pmp entry, execute one access in its associated pmp address region but outside the overlapping/intersecting address range + - execute one additional access inside the overlapping/intersecting address range + - NB: obviously, pmp entry configurations with different access-modes (S/U vs. M) cannot be easily mixed in same test + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, access outside the overlapping/intersecting address range should give the expected CHECK result + - access inside the overlapping/intersecting address range should not generate any access-fault + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F022_S006_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST51(group) => FTR09-a, FTR09-b and FTR09-c + [create scenarios where 2 PMP entries with same pmpaddr + - one without matching permissions or with A=OFF + - one with matching permissions and A=NA4/NAPOT/TOR + - any of them can be the lowest-numbered PMP entry] + TST51-2 + [configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - configure the highest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - execute the associated access + - check no access-fault exception] +## Feature: multi entries TOR + +### Sub-feature: 000_1_entry + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose a single PMP entry + + CONFIGURATION and ACCESS + - for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: "cfg TOR access S/U/M") + - make sure the pmp entries address ranges are not overlapping/intersecting + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, we should obtain the expected CHECK result + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F023_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST23(group) => + [create scenarios where PMP entries with A=1 (TOR) and with/without matching permissions + - pmpaddr(i−1) < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions + - check only TOR defined addresses are matching] + TST23-1 = extension of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-13, TST15-23, TST15-33, TST15-43, TST15-53, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST15-16, TST15-26, TST15-36, TST15-46, TST15-56, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-13, TST16-23, TST16-33, TST16-43, TST16-53, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST16-16, TST16-26, TST16-36, TST16-46, TST16-56) + [configure only one (any, but the first one) PMP entry + - execute the chosen kind of access + - should be same result] +### Sub-feature: 001_2_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + reuse of VP_PMP_F023_S001_I000 feature description (Cf. Feature: "multi entries TOR") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F023_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST23(group) => + [create scenarios where PMP entries with A=1 (TOR) and with/without matching permissions + - pmpaddr(i−1) < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions + - check only TOR defined addresses are matching] + TST23-2 = extension of compatible pair of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-13, TST15-23, TST15-33, TST15-43, TST15-53, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST15-16, TST15-26, TST15-36, TST15-46, TST15-56, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-13, TST16-23, TST16-33, TST16-43, TST16-53, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST16-16, TST16-26, TST16-36, TST16-46, TST16-56) + [configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - execute the 2 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 2 results] +### Sub-feature: 002_N_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any N PMP entries (2> + + TST23(group) => + [create scenarios where PMP entries with A=1 (TOR) and with/without matching permissions + - pmpaddr(i−1) < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions + - check only TOR defined addresses are matching] + TST23-3 = extension of compatible group(N) of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-13, TST15-23, TST15-33, TST15-43, TST15-53, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST15-16, TST15-26, TST15-36, TST15-46, TST15-56, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-13, TST16-23, TST16-33, TST16-43, TST16-53, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST16-16, TST16-26, TST16-36, TST16-46, TST16-56) + [configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - execute the N kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same N results] +### Sub-feature: 003_8_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose all 8 PMP entries + + reuse of VP_PMP_F023_S001_I000 feature description (Cf. Feature: "multi entries TOR") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F023_S004_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST23(group) => + [create scenarios where PMP entries with A=1 (TOR) and with/without matching permissions + - pmpaddr(i−1) < pmpaddr(i), pmpcfg(i).A=TOR and pmpcfg(i-1) with/without matching permissions + - check only TOR defined addresses are matching] + TST23-4 = extension of compatible group(8) of (TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-13, TST15-23, TST15-33, TST15-43, TST15-53, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST15-16, TST15-26, TST15-36, TST15-46, TST15-56, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-13, TST16-23, TST16-33, TST16-43, TST16-53, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST16-16, TST16-26, TST16-36, TST16-46, TST16-56) + [configure 8 PMP entries (highest-numbered ones first) + - execute the 8 kinds of accesses (if possible to chain due to potential access-fault exception) + - should be same 8 results] +### Sub-feature: 004_2_intersecting_entries_fail + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + CONFIGURATION and ACCESS (Cf. Feature: "cfg TOR access S/U/M") + - for the least-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault + - for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault + - make sure the pmp entries address ranges are overlapping/intersecting (at least at 4 consecutive bytes) + - for each pmp entry, execute one access in its associated pmp address region but outside the overlapping/intersecting address range + - execute one additional access inside the overlapping/intersecting address range + - NB: obviously, pmp entry configurations with different access-modes (S/U vs. M) cannot be easily mixed in same test + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, access outside the overlapping/intersecting address range should give the expected CHECK result + - access inside the overlapping/intersecting address range should generate the access-type related access-fault + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F023_S005_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST51(group) => FTR09-a, FTR09-b and FTR09-c + [create scenarios where 2 PMP entries with same pmpaddr + - one without matching permissions or with A=OFF + - one with matching permissions and A=NA4/NAPOT/TOR + - any of them can be the lowest-numbered PMP entry] + TST51-1 + [configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - configure the highest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - execute the associated access + - check associated access-fault exception raised] +### Sub-feature: 005_2_intersecting_entries_succeed + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + CONFIGURATION and ACCESS (Cf. Feature: "cfg TOR access S/U/M") + - for the least-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault + - for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault + - make sure the pmp entries address ranges are overlapping/intersecting (at least at 4 consecutive bytes) + - for each pmp entry, execute one access in its associated pmp address region but outside the overlapping/intersecting address range + - execute one additional access inside the overlapping/intersecting address range + - NB: obviously, pmp entry configurations with different access-modes (S/U vs. M) cannot be easily mixed in same test + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, access outside the overlapping/intersecting address range should give the expected CHECK result + - access inside the overlapping/intersecting address range should not generate any access-fault + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F023_S006_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST51(group) => FTR09-a, FTR09-b and FTR09-c + [create scenarios where 2 PMP entries with same pmpaddr + - one without matching permissions or with A=OFF + - one with matching permissions and A=NA4/NAPOT/TOR + - any of them can be the lowest-numbered PMP entry] + TST51-2 + [configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - configure the highest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - execute the associated access + - check no access-fault exception] +## Feature: multi entries OFF + +### Sub-feature: 000_1_entry + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose a single PMP entry + + CONFIGURATION and ACCESS + - for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: "cfg OFF access S/U/M") + - make sure the pmp entries address ranges are not overlapping/intersecting + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, we should obtain the expected CHECK result + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F024_S001_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST24(group) => FTR09-g + [create scenarios where PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for those PMP entries] + [create scenarios where all PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for all PMP entries] + [check S or U mode access fails when all A=OFF with at least one PMP entry implemented] => FTR09-g + TST24-1 = extension of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-13, TST17-23, TST17-33, TST17-43, TST17-53, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST17-16, TST17-26, TST17-36, TST17-46, TST17-56, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an exception + TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO: M-mode may not raise an exception + //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-13, TST18-23, TST18-33, TST18-43, TST18-53) ? + [configure only one (any, but the first one) PMP entry + - execute the chosen kind of access + - check appropriate access-fault exception raised] +### Sub-feature: 001_2_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + reuse of VP_PMP_F024_S001_I000 feature description (Cf. Feature: "multi entries OFF") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F024_S002_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST24(group) => FTR09-g + [create scenarios where PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for those PMP entries] + [create scenarios where all PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for all PMP entries] + [check S or U mode access fails when all A=OFF with at least one PMP entry implemented] => FTR09-g + TST24-2 = extension of compatible pair of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-13, TST17-23, TST17-33, TST17-43, TST17-53, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST17-16, TST17-26, TST17-36, TST17-46, TST17-56, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an exception + TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO: M-mode may not raise an exception + //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-13, TST18-23, TST18-33, TST18-43, TST18-53) ? + [configure 2 non-adjacent PMP entries (highest-numbered ones first) (avoid the first PMP entry) + - execute the 2 kinds of accesses (if possible to chain due to access-fault) + - check 2 appropriate access-fault exceptions raised] +### Sub-feature: 002_N_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any N PMP entries (2> + + TST24(group) => FTR09-g + [create scenarios where PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for those PMP entries] + [create scenarios where all PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for all PMP entries] + [check S or U mode access fails when all A=OFF with at least one PMP entry implemented] => FTR09-g + TST24-3 = extension of compatible group(N) of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-13, TST17-23, TST17-33, TST17-43, TST17-53, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST17-16, TST17-26, TST17-36, TST17-46, TST17-56, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an exception + TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO: M-mode may not raise an exception + //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-13, TST18-23, TST18-33, TST18-43, TST18-53) ? + [configure N PMP entries (highest-numbered ones first) (as non-adjacent as possible, and avoid the first PMP entry) + - execute the N kinds of accesses (if possible to chain due to access-fault) + - check N appropriate access-fault exceptions raised] +### Sub-feature: 003_8_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose all 8 PMP entries + + reuse of VP_PMP_F024_S001_I000 feature description (Cf. Feature: "multi entries OFF") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F024_S004_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST24(group) => FTR09-g + [create scenarios where PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for those PMP entries] + [create scenarios where all PMP entries with A=0 (OFF) and with matching permissions + - check no address matching for all PMP entries] + [check S or U mode access fails when all A=OFF with at least one PMP entry implemented] => FTR09-g + TST24-4 = extension of compatible group(8) of (TST17-11, TST17-21, TST17-31, TST17-41, TST17-51, + TST17-13, TST17-23, TST17-33, TST17-43, TST17-53, + TST17-14, TST17-24, TST17-34, TST17-44, TST17-54, + TST17-16, TST17-26, TST17-36, TST17-46, TST17-56, + TST18-14, TST18-24, TST18-34, TST18-44, TST18-54, //TODO: M-mode may not raise an exception + TST18-16, TST18-26, TST18-36, TST18-46, TST18-56) //TODO: M-mode may not raise an exception + //TODO: SHOULD WE ADD (TST18-11, TST18-21, TST18-31, TST18-41, TST18-51, + TST18-13, TST18-23, TST18-33, TST18-43, TST18-53) ? + [configure 8 PMP entries (highest-numbered ones first) + - execute the 8 kinds of accesses (if possible to chain due to access-fault) + - check 8 appropriate access-fault exceptions raised] +## Feature: multi entries ALL + +### Sub-feature: 000_1_entry + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose a single PMP entry + + CONFIGURATION and ACCESS + - for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: "cfg NA4/NAPOT/TOR/OFF access S/U/M") + - make sure the pmp entries address ranges are not overlapping/intersecting + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, we should obtain the expected CHECK result + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F025_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 001_2_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + reuse of VP_PMP_F025_S001_I000 feature description (Cf. Feature: "multi entries ALL") +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F025_S002_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + +### Sub-feature: 002_N_isolated_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any N PMP entries (2> + + TST51(group) => FTR09-a, FTR09-b and FTR09-c + [create scenarios where 2 PMP entries with same pmpaddr + - one without matching permissions or with A=OFF + - one with matching permissions and A=NA4/NAPOT/TOR + - any of them can be the lowest-numbered PMP entry] + TST51-1 + [configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - configure the highest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - execute the associated access + - check associated access-fault exception raised] +### Sub-feature: 005_2_intersecting_entries_succeed + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + {Page 57 Section "3.7.1 Physical Memory Protection CSRs" Volume II: RISC-V Privileged Architectures V20211203} + + Up to 64 PMP entries are supported +* **Verification Goals** + + choose any 2 PMP entries + + CONFIGURATION and ACCESS (Cf. Feature: "cfg NA4/NAPOT/TOR/OFF access S/U/M") + - for the least-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario without access-fault + - for the highest-numbered pmp entry, apply any CONFIGURATION+ACCESS scenario with access-fault + - make sure the pmp entries address ranges are overlapping/intersecting (at least at 4 consecutive bytes) + - for each pmp entry, execute one access in its associated pmp address region but outside the overlapping/intersecting address range + - execute one additional access inside the overlapping/intersecting address range + - NB: obviously, pmp entry configurations with different access-modes (S/U vs. M) cannot be easily mixed in same test + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + CHECK + - for each pmp entry, access outside the overlapping/intersecting address range should give the expected CHECK result + - access inside the overlapping/intersecting address range should not generate any access-fault + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** ENV Capability +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F025_S006_I000 +* **Link to Coverage:** +* **Comments** + + << link to the old pmp_verif_plan.txt and pmp_verif_plan_features.txt files (not up-to-date) : reading below not mandatory but may help for better understanding >> + + TST51(group) => FTR09-a, FTR09-b and FTR09-c + [create scenarios where 2 PMP entries with same pmpaddr + - one without matching permissions or with A=OFF + - one with matching permissions and A=NA4/NAPOT/TOR + - any of them can be the lowest-numbered PMP entry] + TST51-2 + [configure 2 PMP entries + - configure the lowest-numbered PMP entry with (TST11-11, TST11-21, TST11-31, TST11-41, TST11-51, + TST11-14, TST11-24, TST11-34, TST11-44, TST11-54, + TST12-11, TST12-21, TST12-31, TST12-41, TST12-51, + TST12-14, TST12-24, TST12-34, TST12-44, TST12-54, + TST13-11, TST13-21, TST13-31, TST13-41, TST13-51, + TST13-14, TST13-24, TST13-34, TST13-44, TST13-54, + TST14-11, TST14-21, TST14-31, TST14-41, TST14-51, + TST14-14, TST14-24, TST14-34, TST14-44, TST14-54, + TST15-11, TST15-21, TST15-31, TST15-41, TST15-51, + TST15-14, TST15-24, TST15-34, TST15-44, TST15-54, + TST16-11, TST16-21, TST16-31, TST16-41, TST16-51, + TST16-14, TST16-24, TST16-34, TST16-44, TST16-54) + - configure the highest-numbered PMP entry with (TST11-12, TST11-22, TST11-32, TST11-42, TST11-52, + TST11-15, TST11-25, TST11-35, TST11-45, TST11-55, + TST12-12, TST12-22, TST12-32, TST12-42, TST12-52, + TST12-15, TST12-25, TST12-35, TST12-45, TST12-55, + TST13-12, TST13-22, TST13-32, TST13-42, TST13-52, + TST13-15, TST13-25, TST13-35, TST13-45, TST13-55, + TST14-12, TST14-22, TST14-32, TST14-42, TST14-52, + TST14-15, TST14-25, TST14-35, TST14-45, TST14-55, + TST15-12, TST15-22, TST15-32, TST15-42, TST15-52, + TST15-15, TST15-25, TST15-35, TST15-45, TST15-55, + TST16-12, TST16-22, TST16-32, TST16-42, TST16-52, + TST16-15, TST16-25, TST16-35, TST16-45, TST16-55, + TST17-12, TST17-22, TST17-32, TST17-42, TST17-52, + TST17-15, TST17-25, TST17-35, TST17-45, TST17-55, + TST18-12, TST18-22, TST18-32, TST18-42, TST18-52, + TST18-15, TST18-25, TST18-35, TST18-45, TST18-55) + - execute the associated access + - check no access-fault exception] +## Feature: entry reconfiguration + +### Sub-feature: 000_reconfigure_N_pmp_entries + +#### Item: 000 + +* **Requirement location:** +* **Feature Description** + + reuse of feature descriptions (Cf. Feature: "cfg NA4/NAPOT/TOR/OFF access S/U/M") + reuse of feature descriptions (Cf. Feature: "CSRs M-mode only") + reuse of feature descriptions (Cf. Feature: "CSRs locked access") + reuse of feature descriptions (Cf. Feature: "multi entries NA4/NAPOT/TOR/OFF") +* **Verification Goals** + + configure any N PMP entries, possibly some with L=1 + + CONFIGURATION and ACCESS + - for each pmp entry, apply any CONFIGURATION+ACCESS scenario above (Cf. Feature: "cfg NA4/NAPOT/TOR/OFF access S/U/M") + - make sure the pmp entries address ranges are not overlapping/intersecting + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + RECONFIGURATION and ACCESS + - for each pmp entry with L=0, apply any other CONFIGURATION+ACCESS scenario above (Cf. Feature: "cfg NA4/NAPOT/TOR/OFF access S/U/M") + - make sure the pmp entries address ranges are not overlapping/intersecting + - NB: obviously, pmp entry configurations with different mstatus.MPRV/MPP values cannot be mixed in same test + + RESET + - if there is any pmp entry with L=1, apply hart reset (or only PMP reset if possible) + - and restart with CONFIGURATION and RESET + + CHECK + - for each pmp entry, we should obtain the expected CHECK result + + REUSABILITY + - if possible, the number of PMP entries (N) is a configurable parameter + - so a single test function can be reused +* **Pass/Fail Criteria:** Check RM +* **Test Type:** Constrained Random +* **Coverage Method:** Functional Coverage +* **Applicable Cores:** CV32E40P, CV32E40S, CV32E40X, CV32A6_v0.1.0, CV32A6-step2, CV64A6-step3 +* **Unique verification tag:** VP_PMP_F031_S001_I000 +* **Link to Coverage:** +* **Comments** + + *(none)* + diff --git a/verif/docs/VerifPlans/source/dvplan_csr-embedded-access.md b/verif/docs/VerifPlans/source/dvplan_csr-embedded-access.md index cd1339333b6..ec022800363 100644 --- a/verif/docs/VerifPlans/source/dvplan_csr-embedded-access.md +++ b/verif/docs/VerifPlans/source/dvplan_csr-embedded-access.md @@ -55,7 +55,7 @@ * **Requirement location:** https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/CV32A6_Control_Status_Registers.html * **Feature Description** - Check the correctness of RISCV CVA6 Read-Only CSRs by writing CSRs in a random order values: Inverted reset, 0xaaaaaaaa, 0x555555, random values. Then confirm that write into RO CSRs generates illegal exception. Finaly read back the CSR and check register value has not changed and matchs reference model. + Check the correctness of RISCV CVA6 Read-Only CSRs by writing CSRs in a random order values: Inverted reset, 0xaaaaaaaa, 0x555555, random values. Then confirm that write into RO CSRs generates illegal exception. Finally read back the CSR and check register value has not changed and matches reference model. * **Verification Goals** 1.Attempt to write a RO CSR. diff --git a/verif/env/corev-dv/cva6_asm_program_gen.sv b/verif/env/corev-dv/cva6_asm_program_gen.sv index d3a6f9a673c..dd9482178dd 100644 --- a/verif/env/corev-dv/cva6_asm_program_gen.sv +++ b/verif/env/corev-dv/cva6_asm_program_gen.sv @@ -159,7 +159,7 @@ class cva6_asm_program_gen_c extends riscv_asm_program_gen; // Generate the interrupt and trap handler for different privileged mode. // The trap handler checks the xCAUSE to determine the type of the exception and jumps to - // corresponding exeception handling routine. + // corresponding exception handling routine. virtual function void gen_trap_handler_section(int hart, string mode, privileged_reg_t cause, privileged_reg_t tvec, diff --git a/verif/env/corev-dv/cva6_illegal_instr.sv b/verif/env/corev-dv/cva6_illegal_instr.sv index 49d108e4513..8163a3da9d0 100644 --- a/verif/env/corev-dv/cva6_illegal_instr.sv +++ b/verif/env/corev-dv/cva6_illegal_instr.sv @@ -27,7 +27,7 @@ class cva6_illegal_instr_c extends riscv_illegal_instr; `uvm_object_utils(cva6_illegal_instr_c) `uvm_object_new - //Overriding the riscv_illegal_instr to ovveride this constraint, and disable kReservedC* constraint + //Overriding the riscv_illegal_instr to override this constraint, and disable kReservedC* constraint constraint reserved_compressed_instr_c { solve exception before reserved_c; solve exception before opcode; diff --git a/verif/env/corev-dv/cva6_instr_base_test.sv b/verif/env/corev-dv/cva6_instr_base_test.sv index 2c32c1ede7f..da6ef5b4ebb 100644 --- a/verif/env/corev-dv/cva6_instr_base_test.sv +++ b/verif/env/corev-dv/cva6_instr_base_test.sv @@ -43,7 +43,7 @@ class cva6_instr_base_test_c extends riscv_instr_base_test; `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) uvm_factory::get().set_type_override_by_type(riscv_asm_program_gen::get_type(), cva6_asm_program_gen_c::get_type()); - `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + `uvm_info("CVA6_DV", $sformatf("Override done "), UVM_LOW) endfunction virtual function void override_gen_config(); diff --git a/verif/env/corev-dv/cva6_instr_hazard_test.sv b/verif/env/corev-dv/cva6_instr_hazard_test.sv index 2652dbf5e97..19ea5de0ce0 100644 --- a/verif/env/corev-dv/cva6_instr_hazard_test.sv +++ b/verif/env/corev-dv/cva6_instr_hazard_test.sv @@ -41,7 +41,7 @@ class cva6_instr_hazard_test_c extends riscv_instr_base_test; `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) uvm_factory::get().set_type_override_by_type(riscv_asm_program_gen::get_type(), cva6_asm_program_gen_c::get_type()); - `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + `uvm_info("CVA6_DV", $sformatf("Override done "), UVM_LOW) endfunction virtual function void override_gen_config(); diff --git a/verif/env/corev-dv/cva6_unsupported_instr.sv b/verif/env/corev-dv/cva6_unsupported_instr.sv index fabd89fd662..8e075d62b0b 100644 --- a/verif/env/corev-dv/cva6_unsupported_instr.sv +++ b/verif/env/corev-dv/cva6_unsupported_instr.sv @@ -268,6 +268,15 @@ class cva6_unsupported_instr_c extends uvm_object; instr_bin[6:2] == 5'b0; instr_bin[12] == 1'b0; } + if (c_msb == 3'b101) { + if (instr_bin[12]) { + !(instr_bin[11:8] inside {4'b1000, 4'b1010, 4'b1100, 4'b1110}); + } + else { + instr_bin[11:10] != 2'b11; + !(instr_bin[6:5] inside {2'b01, 2'b11}); + } + } } } } @@ -291,7 +300,10 @@ class cva6_unsupported_instr_c extends uvm_object; c_op inside {2'b00, 2'b01}; c_msb == 3'b100; if (c_op == 2'b00) { - !(instr_bin[12:10] inside {3'b000, 3'b001, 3'b010, 3'b011}); + !(instr_bin[12:10] inside {3'b000, 3'b001, 3'b010}); + if (instr_bin[12:10] == 3'b011) { + instr_bin[6] == 1'b1; + } } if (c_op == 2'b01) { instr_bin[12:10] == 3'b111; diff --git a/verif/env/corev-dv/simulator.yaml b/verif/env/corev-dv/simulator.yaml index 6aafabf62cf..0cb6d01f93e 100644 --- a/verif/env/corev-dv/simulator.yaml +++ b/verif/env/corev-dv/simulator.yaml @@ -15,7 +15,7 @@ # # SPDX-License-Identifier: Apache-2.0 -###### This file is based on /cva6-simuator.yaml +###### This file is based on /cva6-simulator.yaml - tool: xrun compile: @@ -61,3 +61,28 @@ cov_opts: > -cm_dir /test.vdb -cm_log /dev/null -cm_name test__ +- tool: questa + compile: + cmd: + - "vlog -64 + +incdir+$QUESTASIM_HOME/verilog_src/uvm-1.2/src + +incdir+ + +incdir+ + +acc + $QUESTASIM_HOME/verilog_src/uvm-1.2/src/uvm_pkg.sv + -f /../env/corev-dv/cva6-files.f + -sv + -mfcu -cuname design_cuname + +define+UVM_REGEX_NO_DPI + -writetoplevels /top.list + -l /compile.log " + - "vopt -64 -debug + +designfile -f /top.list + -l /optimize.log + -o design_opt" + sim: + cmd: > + vsim -64 -c -do /dv/questa_sim.tcl design_opt -sv_seed -sv_lib $QUESTASIM_HOME/uvm-1.2/linux_x86_64/uvm_dpi + cov_opts: > + -do "coverage save -onexit /cov.ucdb;" + diff --git a/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv b/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv index f5772bf4c59..0d7040322b3 100644 --- a/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv +++ b/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv @@ -80,7 +80,7 @@ parameter int SELEN = 8; // Maximum size of a single vector element (encoded in vsew format) parameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3; -// Maxium LMUL supported by the core +// Maximum LMUL supported by the core parameter int MAX_LMUL = 8; // ---------------------------------------------------------------------------- @@ -91,10 +91,10 @@ parameter int MAX_LMUL = 8; parameter int NUM_HARTS = 1; // ---------------------------------------------------------------------------- -// Previleged CSR implementation +// Privileged CSR implementation // ---------------------------------------------------------------------------- -// Implemented previlieged CSR list +// Implemented privileged CSR list `ifdef DSIM privileged_reg_t implemented_csr[] = { `else diff --git a/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv b/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv index 8a665b928bc..10dfab13652 100644 --- a/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv +++ b/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv @@ -87,7 +87,7 @@ parameter int SELEN = 8; // Maximum size of a single vector element (encoded in vsew format) parameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3; -// Maxium LMUL supported by the core +// Maximum LMUL supported by the core parameter int MAX_LMUL = 8; // ---------------------------------------------------------------------------- @@ -98,10 +98,10 @@ parameter int MAX_LMUL = 8; parameter int NUM_HARTS = 1; // ---------------------------------------------------------------------------- -// Previleged CSR implementation +// Privileged CSR implementation // ---------------------------------------------------------------------------- -// Implemented previlieged CSR list +// Implemented privileged CSR list `ifdef DSIM privileged_reg_t implemented_csr[] = { `else diff --git a/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv b/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv index 386c675712d..adc2caed3c5 100644 --- a/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv +++ b/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv @@ -64,10 +64,10 @@ parameter int SLEN = 64; parameter int NUM_HARTS = 1; // ---------------------------------------------------------------------------- -// Previleged CSR implementation +// Privileged CSR implementation // ---------------------------------------------------------------------------- -// Implemented previlieged CSR list +// Implemented privileged CSR list `ifdef DSIM privileged_reg_t implemented_csr[] = { `else diff --git a/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv b/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv new file mode 100644 index 00000000000..732c7213146 --- /dev/null +++ b/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv @@ -0,0 +1,188 @@ +/* + * Copyright 2019 Google LLC + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//----------------------------------------------------------------------------- +// Processor feature configuration +//----------------------------------------------------------------------------- +// XLEN +parameter int XLEN = 64; + +// Parameter for SATP mode, set to BARE if address translation is not supported +parameter satp_mode_t SATP_MODE = SV39; + +// Supported Privileged mode +privileged_mode_t supported_privileged_mode[] = {USER_MODE, SUPERVISOR_MODE, MACHINE_MODE}; + +// Unsupported instructions +riscv_instr_name_t unsupported_instr[]; + +// ISA supported by the processor +riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV64I, RV64M, RV32C, RV64C, RV32A, RV64A, + RV32F, RV64F, RV32D, RV64D}; +// Interrupt mode support +mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED}; + +// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is +// supported +int max_interrupt_vector_num = 16; + +// Physical memory protection support +bit support_pmp = 0; + +// Enhanced physical memory protection support +bit support_epmp = 0; + +// Debug mode support +bit support_debug_mode = 0; + +// Support delegate trap to user mode +bit support_umode_trap = 0; + +// Support sfence.vma instruction +bit support_sfence = 1; + +// Support unaligned load/store +bit support_unaligned_load_store = 1'b1; + +// GPR setting +parameter int NUM_FLOAT_GPR = 32; +parameter int NUM_GPR = 32; +parameter int NUM_VEC_GPR = 32; + +// ---------------------------------------------------------------------------- +// Vector extension configuration +// ---------------------------------------------------------------------------- + +// Parameter for vector extension +parameter int VECTOR_EXTENSION_ENABLE = 0; + +parameter int VLEN = 512; + +// Maximum size of a single vector element +parameter int ELEN = 32; + +// Minimum size of a sub-element, which must be at most 8-bits. +parameter int SELEN = 8; + +// Maximum size of a single vector element (encoded in vsew format) +parameter int VELEN = int'($ln(ELEN)/$ln(2)) - 3; + +// Maximum LMUL supported by the core +parameter int MAX_LMUL = 8; + +// ---------------------------------------------------------------------------- +// Multi-harts configuration +// ---------------------------------------------------------------------------- + +// Number of harts +parameter int NUM_HARTS = 1; + +// ---------------------------------------------------------------------------- +// Privileged CSR implementation +// ---------------------------------------------------------------------------- + +// Implemented privileged CSR list +`ifdef DSIM +privileged_reg_t implemented_csr[] = { +`else +const privileged_reg_t implemented_csr[] = { +`endif + // User mode CSR + USTATUS, // User status + UIE, // User interrupt-enable register + UTVEC, // User trap-handler base address + USCRATCH, // Scratch register for user trap handlers + UEPC, // User exception program counter + UCAUSE, // User trap cause + UTVAL, // User bad address or instruction + UIP, // User interrupt pending + // Supervisor mode CSR + SSTATUS, // Supervisor status + SEDELEG, // Supervisor exception delegation register + SIDELEG, // Supervisor interrupt delegation register + SIE, // Supervisor interrupt-enable register + STVEC, // Supervisor trap-handler base address + SCOUNTEREN, // Supervisor counter enable + SSCRATCH, // Scratch register for supervisor trap handlers + SEPC, // Supervisor exception program counter + SCAUSE, // Supervisor trap cause + STVAL, // Supervisor bad address or instruction + SIP, // Supervisor interrupt pending + SATP, // Supervisor address translation and protection + // Machine mode mode CSR + MVENDORID, // Vendor ID + MARCHID, // Architecture ID + MIMPID, // Implementation ID + MHARTID, // Hardware thread ID + MSTATUS, // Machine status + MISA, // ISA and extensions + MEDELEG, // Machine exception delegation register + MIDELEG, // Machine interrupt delegation register + MIE, // Machine interrupt-enable register + MTVEC, // Machine trap-handler base address + MCOUNTEREN, // Machine counter enable + MSCRATCH, // Scratch register for machine trap handlers + MEPC, // Machine exception program counter + MCAUSE, // Machine trap cause + MTVAL, // Machine bad address or instruction + MIP, // Machine interrupt pending + // Floating point CSR + FCSR // Floating point control and status +}; + +// Implementation-specific custom CSRs +bit [11:0] custom_csr[] = { +}; + +// ---------------------------------------------------------------------------- +// Supported interrupt/exception setting, used for functional coverage +// ---------------------------------------------------------------------------- + +`ifdef DSIM +interrupt_cause_t implemented_interrupt[] = { +`else +const interrupt_cause_t implemented_interrupt[] = { +`endif + U_SOFTWARE_INTR, + S_SOFTWARE_INTR, + M_SOFTWARE_INTR, + U_TIMER_INTR, + S_TIMER_INTR, + M_TIMER_INTR, + U_EXTERNAL_INTR, + S_EXTERNAL_INTR, + M_EXTERNAL_INTR +}; + +`ifdef DSIM +exception_cause_t implemented_exception[] = { +`else +const exception_cause_t implemented_exception[] = { +`endif + INSTRUCTION_ACCESS_FAULT, + ILLEGAL_INSTRUCTION, + BREAKPOINT, + LOAD_ADDRESS_MISALIGNED, + LOAD_ACCESS_FAULT, + STORE_AMO_ADDRESS_MISALIGNED, + STORE_AMO_ACCESS_FAULT, + ECALL_UMODE, + ECALL_SMODE, + ECALL_MMODE, + INSTRUCTION_PAGE_FAULT, + LOAD_PAGE_FAULT, + STORE_AMO_PAGE_FAULT +}; diff --git a/verif/env/uvme/cov/uvme_axi_covg.sv b/verif/env/uvme/cov/uvme_axi_covg.sv index 3e853656665..f4abd9cf0d6 100644 --- a/verif/env/uvme/cov/uvme_axi_covg.sv +++ b/verif/env/uvme/cov/uvme_axi_covg.sv @@ -13,7 +13,7 @@ /* * Covergroups - * Decalred at package-level to enable mutliple instances per monitor class (e.g. read/write) + * Declared at package-level to enable multiple instances per monitor class (e.g. read/write) */ covergroup cg_axi_w_channel(string name) diff --git a/verif/env/uvme/cov/uvme_axi_ext_covg.sv b/verif/env/uvme/cov/uvme_axi_ext_covg.sv index 12d8facb050..ff8f17eb6fc 100644 --- a/verif/env/uvme/cov/uvme_axi_ext_covg.sv +++ b/verif/env/uvme/cov/uvme_axi_ext_covg.sv @@ -13,7 +13,7 @@ /* * Covergroups - * Decalred at package-level to enable mutliple instances per monitor class (e.g. read/write) + * Declared at package-level to enable multiple instances per monitor class (e.g. read/write) */ covergroup cg_axi_aw_order(string name) diff --git a/verif/env/uvme/cov/uvme_cvxif_covg.sv b/verif/env/uvme/cov/uvme_cvxif_covg.sv index 58c13b71e8b..53ea6b94fdd 100644 --- a/verif/env/uvme/cov/uvme_cvxif_covg.sv +++ b/verif/env/uvme/cov/uvme_cvxif_covg.sv @@ -102,7 +102,7 @@ covergroup cg_cus_add_instr( `CVXIF_CP_BITWISE(cp_rs1_toggle, req_item.issue_req.rs[0], 1) `CVXIF_CP_BITWISE(cp_rs2_toggle, req_item.issue_req.rs[1], 1) - `CVXIF_CP_BITWISE(cp_rs3_toggle, req_item.issue_req.rs[2], rs3_valid) //TODO : fix need more filtring + `CVXIF_CP_BITWISE(cp_rs3_toggle, req_item.issue_req.rs[2], rs3_valid) //TODO : fix need more filtering endgroup: cg_cus_add_instr diff --git a/verif/env/uvme/cov/uvme_exception_covg.sv b/verif/env/uvme/cov/uvme_exception_covg.sv index a91e730ef6b..a2466b69bae 100644 --- a/verif/env/uvme/cov/uvme_exception_covg.sv +++ b/verif/env/uvme/cov/uvme_exception_covg.sv @@ -34,7 +34,6 @@ covergroup cg_exception( option.per_instance = 1; option.name = name; -`ifndef QUESTA cp_exception: coverpoint instr.cause { bins BREAKPOINT = {3} iff (instr.trap); @@ -155,7 +154,6 @@ covergroup cg_exception( ignore_bins IGN_EXC = !binsof(cp_exception) intersect{6}; ignore_bins IGN_ADD = binsof(cp_add_mem) intersect{0}; } -`endif endgroup : cg_exception diff --git a/verif/env/uvme/cov/uvme_illegal_instr_covg.sv b/verif/env/uvme/cov/uvme_illegal_instr_covg.sv index e71c9c91326..dc3df6bcd48 100644 --- a/verif/env/uvme/cov/uvme_illegal_instr_covg.sv +++ b/verif/env/uvme/cov/uvme_illegal_instr_covg.sv @@ -150,7 +150,7 @@ class uvme_illegal_instr_cov_model_c extends uvm_component; `uvm_component_utils(uvme_illegal_instr_cov_model_c) - //Covergroup of Illegal instrcution + //Covergroup of Illegal instruction cg_illegal_i illegal_i_cg; cg_illegal_m illegal_m_cg; cg_illegal_zicsr illegal_zicsr_cg; diff --git a/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst b/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst index 406dd501420..375225dad0b 100644 --- a/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst +++ b/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst @@ -36,7 +36,7 @@ Except for 4 of them using opcode `MADD, MSUB, NMADD, NMSUB` **Description**: add register rs1 to rs1, and store the result in rd. Any rs2 value can be given. It should be ignored by CPU. - Exists to check that register depedencies is well implemented in CPU. + Exists to check that register dependencies is well implemented in CPU. **Pseudocode**: x[rd] = x[rs1] + x[rs1] diff --git a/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv b/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv index fa09076983e..ce7b1dc6e1e 100644 --- a/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv +++ b/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv @@ -47,7 +47,7 @@ class uvma_cva6_core_cntrl_agent_c extends uvma_core_cntrl_agent_c; extern virtual function void retrieve_vif(); /** - * Spawn active sequnces + * Spawn active sequences */ extern virtual task run_phase(uvm_phase phase); diff --git a/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv b/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv index 48a98c828a3..fe1636c011e 100644 --- a/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv +++ b/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv @@ -19,7 +19,7 @@ `define __UVMA_CVA6_CORE_CNTRL_DRV_SV__ /** - * Component driving bootstrap pins and other misecllaneous I/O for cva6 core + * Component driving bootstrap pins and other miscellaneous I/O for cva6 core */ class uvma_cva6_core_cntrl_drv_c extends uvma_core_cntrl_drv_c; diff --git a/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv b/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv index d9dfabe3621..731190b743b 100644 --- a/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv +++ b/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv @@ -21,7 +21,14 @@ covergroup cg_interrupt( option.name = name; cp_interrupt_req : coverpoint req_item.interrupt_vector { - bins INTERRUPTS[] = {[0:$]} with (item inside {[0:(2**(num_irq_supported))-1]}); + // FIXME: Tanuj Khandelwal + // Questa is crashing on this CG + // Hence it has been changed a little to make it pass + `ifndef QUESTA + bins INTERRUPTS[] = {[0:$]} with (item inside {[0:((2**(num_irq_supported))-1)]}); + `else + bins INTERRUPTS[] = {[0:((2**(num_irq_supported))-1)]}; + `endif } endgroup: cg_interrupt diff --git a/verif/env/uvme/uvma_interrupt/uvma_interrupt_cfg.sv b/verif/env/uvme/uvma_interrupt/uvma_interrupt_cfg.sv index fa1673d6465..598d4475dd9 100644 --- a/verif/env/uvme/uvma_interrupt/uvma_interrupt_cfg.sv +++ b/verif/env/uvme/uvma_interrupt/uvma_interrupt_cfg.sv @@ -30,7 +30,7 @@ class uvma_interrupt_cfg_c extends uvm_object; // Interrupt memory ack rand bit [XLEN-1:0] irq_addr; - // enbale/disable clear mechanism + // enable/disable clear mechanism rand bit enable_clear_irq; // Number of cycle before Timeout if the agent failed to write into irq_add diff --git a/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv b/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv index 6663accf23a..252925ca5dc 100644 --- a/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv +++ b/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv @@ -64,7 +64,7 @@ class uvma_interrupt_mon_c extends uvm_monitor; endclass : uvma_interrupt_mon_c -function uvma_interrupt_mon_c::new(string name = "uvma_interrupt_mon", uvm_component parent); +function uvma_interrupt_mon_c::new(string name = "uvma_interrupt_mon", uvm_component parent = null); super.new(name, parent); endfunction diff --git a/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv b/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv index 0a08d68af42..7870031e6d1 100644 --- a/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv +++ b/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv @@ -17,6 +17,7 @@ `include "uvml_hrtbt_macros.sv" `include "uvma_interrupt_macros.sv" +`include "uvma_axi_macros.sv" /** * Encapsulates all the types needed for an UVM agent capable of driving and/or * monitoring Clock & Reset. diff --git a/verif/env/uvme/uvme_cva6_sb.sv b/verif/env/uvme/uvme_cva6_sb.sv index cf15c8f53d6..a0606869b56 100644 --- a/verif/env/uvme/uvme_cva6_sb.sv +++ b/verif/env/uvme/uvme_cva6_sb.sv @@ -323,7 +323,7 @@ endfunction : check_mepc function bit [XLEN:0] uvme_cva6_sb_c::check_mcycle_h(uvma_isacov_instr_c instr, uvma_isacov_instr_c instr_prev, int cycle_count); // Check mcycle value after a CSR read - if (instr_prev == null) return; + if (instr_prev == null) return 0; write_in_mcycle = (instr_prev.is_csr_write() && instr_prev.csr_val == 12'hb00) ? 1 : 0; if (cfg.xlen == 32) begin diff --git a/verif/regress/Instr_tracing_test.sh b/verif/regress/Instr_tracing_test.sh new file mode 100755 index 00000000000..e4a0078b485 --- /dev/null +++ b/verif/regress/Instr_tracing_test.sh @@ -0,0 +1,127 @@ +#!/bin/bash + +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales + +# Usage ./compare_iti_trace.sh +# Exit 0 if iti traces match, 1 otherwise. + +exit_error() { + echo "$1" >&2 + exit ${2:-1} +} + +clean_file_preserve_header() { + local input_f="$1" + local output_f="$2" + local start_skip="$3" + local end_skip="$4" + + local total_lines lines_to_keep + total_lines=$(wc -l < "$input_f") + lines_to_keep=$((total_lines - start_skip - end_skip)) + + if [ "$lines_to_keep" -le 0 ]; then + exit_error "Error: not enought lines in $input_f" + fi + + { + head -n1 "$input_f" + tail -n "+$((start_skip + 1))" "$input_f" | head -n "$lines_to_keep" + } | sed $'s/\r$//'> "$output_f" +} + +if [ "$#" -ne 1 ]; then + exit_error "Usage: $0 " 2 +fi + +exe="$1" +base=$(basename "$exe" .o) +mkdir verif/sim/Instr_tracing_artifact +workdir="$(realpath verif/sim/Instr_tracing_artifact)" + + +if ! bash verif/regress/iti_test.sh "$exe"; then + exit_error "Error: iti_test.sh failed" +fi + +if [ ! -f verif/sim/iti.traces ]; then + exit_error "Error: iti.traces does not exist" +fi +if [ ! -f verif/sim/encaps.traces ]; then + exit_error "Error: encaps.traces does not exist" +fi + +cp verif/sim/iti.traces "$workdir/iti.trace" +cp verif/sim/encaps.traces "$workdir/encaps.trace" + +rm verif/sim/iti.traces +rm verif/sim/encaps.traces + +cd "$workdir" +git clone https://github.com/riscv-non-isa/riscv-trace-spec.git +cd riscv-trace-spec +git checkout dca761264721068c4576eebd206e2c8b0b9d58b6 +cd referenceFlow +bash scripts/build.sh + +tmp_riscv="$workdir/riscv-trace-spec/referenceFlow/tests/test_files/$base.riscv" +cd ../../.. +cp "$exe" "$tmp_riscv" +cd Instr_tracing_artifact/riscv-trace-spec/referenceFlow +if ! ./scripts/run_regression.sh -t itype3_debug --annotate --debug $tmp_riscv; then + exit_error "Error: run_regression failed" +fi + +reg_dir=$(ls -td ./regression_* 2>/dev/null | head -n1) +if [ -z "$reg_dir" ]; then + exit_error "Error: Folder regression does not exist" +fi + +iti_out="$reg_dir/itype3_debug/$base.encoder_input" +if [ ! -f "$iti_out" ]; then + exit_error "Error: $iti_out does not exist" +fi +encod_out="$reg_dir/itype3_debug/$base.te_inst" +if [ ! -f "$iti_out" ]; then + exit_error "Error: $encod_out does not exist" +fi + +cp "$iti_out" "$workdir/iti_reg.trace" +cp "$encod_out" "$workdir/encod_reg.trace" + +clean_file_preserve_header "$workdir/iti_reg.trace" "$workdir/iti_reg_cleaned.trace" 6 2 +clean_file_preserve_header "$workdir/iti.trace" "$workdir/iti_cleaned.trace" 7 0 + +if diff -q "$workdir/iti_reg_cleaned.trace" "$workdir/iti_cleaned.trace" > /dev/null; then + echo "SUCESS: Same ITI Traces" +else + diff -u "$workdir/iti_reg_cleaned.trace" "$workdir/iti_cleaned.trace" + exit_error "FAILED: ITI traces do not match" +fi + +decapsuler_path="$workdir/../../../corev_apu/instr_tracing/Decapsuler" + +if ! make -C "$decapsuler_path"; then + exit_error "Error: Compilation of Decapsuler failed" +fi + +if ! "$decapsuler_path/Decapsuler" "$workdir/encaps.trace"; then + exit_error "Error: Decapsulation failed" +fi + +clean_file_preserve_header "$workdir/encod_reg.trace" "$workdir/encod_reg_cleaned.trace" 3 2 +clean_file_preserve_header "$workdir/encaps.csv" "$workdir/encaps_cleaned.trace" 3 0 + +if diff -q "$workdir/encod_reg_cleaned.trace" "$workdir/encaps_cleaned.trace" > /dev/null; then + echo "SUCESS: Same Encoder Packets" +else + python3 "$decapsuler_path/diff_color.py" "$workdir/encaps.csv" "$workdir/encod_reg.trace" + exit_error "FAILED: Encoder Packets do not match" +fi \ No newline at end of file diff --git a/verif/regress/coremark.sh b/verif/regress/coremark.sh index 23038dbf3db..cabcc585aee 100644 --- a/verif/regress/coremark.sh +++ b/verif/regress/coremark.sh @@ -76,7 +76,7 @@ cflags_opt=( cflags=( "${cflags_opt[@]}" "-DCOMPILER_FLAGS='\"${cflags_opt[*]}\"'" - -DITERATIONS=4 + -DITERATIONS=1 -DPERFORMANCE_RUN -DSKIP_TIME_CHECK -I../tests/custom/env diff --git a/verif/regress/cv32a6_tests.sh b/verif/regress/cv32a6_tests.sh index 0af6cc0231d..28f3b284d31 100644 --- a/verif/regress/cv32a6_tests.sh +++ b/verif/regress/cv32a6_tests.sh @@ -46,6 +46,10 @@ cd verif/sim/ errors=0 +# Regression for #3535: Zcmp macro expansion must wait for issue acknowledgement. +make -C ../tb/macro_decoder_unit +[[ $? > 0 ]] && ((errors++)) + # 32-bit configurations without MMU riscv_tests_list=( rv32ui-p-add @@ -63,6 +67,38 @@ python3 cva6.py --target ${DV_TARGET} --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -lgcc -I../tests/custom/env -I../tests/custom/common" $DV_OPTS [[ $? > 0 ]] && ((errors++)) +# Regression for #3464: cm.mva01s permits equal compact-register operands. +if [ "$DV_TARGET" = "cv32a60x" ]; then + # Rebuild for the generated hwconfig because the preceding tests use + # the default cv32a60x configuration, where RVZCMP is disabled. + make -C ../.. clean + + env -u SPIKE_TANDEM python3 cva6.py \ + --testlist=../tests/testlist_issues.yaml \ + --test zcmp-mva01s-equal-regs-rv32 \ + --iss_yaml cva6.yaml \ + --target hwconfig \ + --hwconfig_opts="cv32a60x *RVZCMP=1" \ + --iss=veri-testharness \ + --linker="../../config/gen_from_riscv_config/cv32a60x/linker/link.ld" \ + $DV_OPTS + [[ $? > 0 ]] && ((errors++)) +fi + +# Regression for #3465: reserved Zcmp rlist values must trap as illegal. +if [ "$DV_TARGET" = "cv32a60x" ]; then + python3 cva6.py \ + --testlist=../tests/testlist_issues.yaml \ + --test zcmp-reserved-rlist-rv32 \ + --iss_yaml cva6.yaml \ + --target hwconfig \ + --hwconfig_opts="cv32a60x *RVZCMP=1" \ + --iss=$DV_SIMULATORS \ + --linker="../../config/gen_from_riscv_config/cv32a60x/linker/link.ld" \ + $DV_OPTS + [[ $? > 0 ]] && ((errors++)) +fi + make -C ../.. clean make clean_all diff --git a/verif/regress/cv64a6_imafdc_tests.sh b/verif/regress/cv64a6_imafdc_tests.sh index e5164f40e6f..edd3001156e 100644 --- a/verif/regress/cv64a6_imafdc_tests.sh +++ b/verif/regress/cv64a6_imafdc_tests.sh @@ -66,6 +66,18 @@ python3 cva6.py --target ${DV_TARGET} --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../../config/gen_from_riscv_config/linker/link.ld" $DV_OPTS [[ $? > 0 ]] && ((errors++)) +# Regression for #3342: pmpaddr bit 0 must not affect either TOR boundary +# when the PMP grain is eight bytes. Run the DUT alone because the default +# CV64 Spike configuration does not describe CVA6's PMP granularity. +env -u SPIKE_TANDEM python3 cva6.py \ + --testlist=../tests/testlist_issues.yaml \ + --test pmp-tor-grain-rv64 \ + --iss_yaml cva6.yaml \ + --target ${DV_TARGET} \ + --iss=veri-testharness \ + $DV_OPTS +[[ $? > 0 ]] && ((errors++)) + make -C ../.. clean make clean_all diff --git a/verif/regress/install-pk.sh b/verif/regress/install-pk.sh new file mode 100755 index 00000000000..8788d0427f4 --- /dev/null +++ b/verif/regress/install-pk.sh @@ -0,0 +1,107 @@ +#!/bin/bash +# Copyright 2025 Isaar AHMAD +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Isaar AHMAD +# +# ============================================================================== +# This script installs RISCV proxy kernel at ${ROOT_PROJECT}/tools/pk, +# where ROOT_PROJECT is base of the CVA6 repository. +# ============================================================================== +set -e # Exit immediately if a command fails + +PK_ARCH=$1 +PK_MABI=$2 +PK_REPO="https://github.com/riscv-software-src/riscv-pk.git" +PK_BRANCH="master" +PK_COMMIT_HASH="e5563d1044bd6790325c4602c49f89e1182fa91a" + +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return 1 +fi + +PATH=$RISCV/bin:$PATH +# Customise this to a fast local disk +ROOT_PROJECT=$(readlink -f $(dirname "${BASH_SOURCE[0]}")/../../) + +if [ -z "$NUM_JOBS" ]; then + NUM_JOBS=1 +fi + +# Unset historical variable PK_ROOT as it collides with the build process. +if [ -n "$PK_ROOT" ]; then + unset PK_ROOT +fi + +echo "[install-pk.sh] Entry values:" +echo " PK_BUILD_DIR='$PK_BUILD_DIR'" +echo " PK_INSTALL_DIR='$PK_INSTALL_DIR'" + +# If not set, define the installation location of pk to the local path +# +# /tools/pk +# +# Continuous Integration may need to override this particular variable +# to use a preinstalled build of Verilator. +if [ -z "$PK_INSTALL_DIR" ]; then + export PK_INSTALL_DIR="$ROOT_PROJECT/tools/pk" + echo "Setting PK_INSTALL_DIR to '$PK_INSTALL_DIR'..." +fi + +# Define the default src+build location of pk in case it needs to be (re)built. +# No need to force this location in Continuous Integration scripts. +if [ -z "$PK_BUILD_DIR" ]; then + export PK_BUILD_DIR="$PK_INSTALL_DIR/build-pk" + echo "Setting PK_BUILD_DIR to '$PK_BUILD_DIR'..." +fi + +# Clean previous installation directory to ensure a fresh install +echo "Cleaning old installation directory: $PK_INSTALL_DIR" +rm -rf "$PK_INSTALL_DIR" + +# Build and install pk only if the final binary is not present. +# Note: The script now always rebuilds due to the rm -rf above. +if [ ! -f "$PK_INSTALL_DIR/riscv-none-elf/bin/pk" ]; then + echo "Building pk in '$PK_BUILD_DIR'..." + echo "pk will be installed in '$PK_INSTALL_DIR'" + echo "PK_REPO=$PK_REPO" + echo "PK_COMMIT_HASH=$PK_COMMIT_HASH" + echo "NUM_JOBS=$NUM_JOBS" + + mkdir -p "$PK_BUILD_DIR" + pushd "$PK_BUILD_DIR" + # Fetch repository only if the ".git" directory does not exist. + # Do not remove the content arbitrarily if ".git" does not exist in order + # to preserve user content - let git fail instead. + if [ ! -d ".git" ]; then + echo "Cloning full repository from ${PK_REPO}..." + git clone "${PK_REPO}" . + else + echo "Repository already exists. Fetching updates..." + git fetch origin + fi + + echo "Checking out commit: ${PK_COMMIT_HASH}" + git checkout "${PK_COMMIT_HASH}" + + # Proceed with the build + mkdir -p build + pushd build + ../configure --prefix="$PK_INSTALL_DIR" --host=riscv-none-elf --with-arch="$PK_ARCH" + make -j${NUM_JOBS} + make install + popd # build + popd # $PK_BUILD_DIR +else + echo "pk already installed in '$PK_INSTALL_DIR'." +fi + +# Add pk bin directory to PATH if not already present. +echo "$PATH" | grep -q "$PK_INSTALL_DIR/bin:" || \ + export PATH="$PK_INSTALL_DIR/bin:$PATH" + +echo "Successfully configured RISC-V Proxy Kernel." diff --git a/verif/regress/install-riscv-tests.sh b/verif/regress/install-riscv-tests.sh index 2023d29e791..27fbc5245fa 100755 --- a/verif/regress/install-riscv-tests.sh +++ b/verif/regress/install-riscv-tests.sh @@ -8,7 +8,7 @@ # Original Author: Jean-Roch COULON - Thales if ! [ -n "$TESTS_REPO" ]; then - TESTS_REPO="https://github.com/riscv/riscv-tests.git" + TESTS_REPO="https://github.com/riscv-software-src/riscv-tests.git" TESTS_BRANCH="master" TESTS_HASH="f92842f91644092960ac7946a61ec2895e543cec" fi diff --git a/verif/regress/install-spike.sh b/verif/regress/install-spike.sh index e240f64bdbb..b6389575146 100755 --- a/verif/regress/install-spike.sh +++ b/verif/regress/install-spike.sh @@ -43,7 +43,10 @@ if ! [ -f "$SPIKE_INSTALL_DIR/bin/spike" ]; then cd build WITH_BOOST="" if [[ ! -z "$BOOST_INSTALL_DIR" ]]; then - WITH_BOOST="--with-boost=${BOOST_INSTALL_DIR}" + WITH_BOOST="${WITH_BOOST} --with-boost=${BOOST_INSTALL_DIR}" + fi + if [[ ! -z "$BOOST_LIBDIR" ]]; then + WITH_BOOST="${WITH_BOOST} --with-boost-libdir=${BOOST_LIBDIR}" fi if [ ! -f config.log ]; then ../configure --prefix="$SPIKE_INSTALL_DIR" ${WITH_BOOST} diff --git a/verif/regress/issue-tests.sh b/verif/regress/issue-tests.sh index 01209c36174..37aaaf07fe0 100644 --- a/verif/regress/issue-tests.sh +++ b/verif/regress/issue-tests.sh @@ -33,4 +33,57 @@ python3 cva6.py --testlist=../tests/testlist_issues.yaml --test compressed-fpreg make clean make -C verif/sim clean_all + +# Check the complete eight-bit Zcmt JVT index with a directed assembly test. +python3 cva6.py \ + --testlist=../tests/testlist_issues.yaml \ + --test zcmt-jvt-index-rv32 \ + --iss_yaml cva6.yaml \ + --target hwconfig \ + --hwconfig_opts="cv32a60x *RVZCMT=1" \ + --iss=veri-testharness \ + --linker="../../config/gen_from_riscv_config/cv32a60x/linker/link.ld" + +zcmt_status=$? +if [ "$zcmt_status" -ne 0 ]; then + echo "Error: Zcmt JVT index assembly regression failed" + cd ../.. + return "$zcmt_status" 2>/dev/null || exit "$zcmt_status" +fi + + +# Check that cm.jt clears bit 0 of the loaded JVT target. +python3 cva6.py \ + --testlist=../tests/testlist_issues.yaml \ + --test zcmt-jt-target-lsb-rv32 \ + --iss_yaml cva6.yaml \ + --target hwconfig \ + --hwconfig_opts="cv32a60x *RVZCMT=1" \ + --iss=veri-testharness \ + --linker="../../config/gen_from_riscv_config/cv32a60x/linker/link.ld" + +zcmt_jt_lsb_status=$? +if [ "$zcmt_jt_lsb_status" -ne 0 ]; then + echo "Error: Zcmt cm.jt target LSB regression failed" + cd ../.. + return "$zcmt_jt_lsb_status" 2>/dev/null || exit "$zcmt_jt_lsb_status" +fi + +# Check that cm.jalt clears bit 0 of the loaded JVT target. +python3 cva6.py \ + --testlist=../tests/testlist_issues.yaml \ + --test zcmt-jalt-target-lsb-rv32 \ + --iss_yaml cva6.yaml \ + --target hwconfig \ + --hwconfig_opts="cv32a60x *RVZCMT=1" \ + --iss=veri-testharness \ + --linker="../../config/gen_from_riscv_config/cv32a60x/linker/link.ld" + +zcmt_jalt_lsb_status=$? +if [ "$zcmt_jalt_lsb_status" -ne 0 ]; then + echo "Error: Zcmt cm.jalt target LSB regression failed" + cd ../.. + return "$zcmt_jalt_lsb_status" 2>/dev/null || exit "$zcmt_jalt_lsb_status" +fi + cd - diff --git a/verif/regress/iti_test.sh b/verif/regress/iti_test.sh new file mode 100644 index 00000000000..1b914d202a0 --- /dev/null +++ b/verif/regress/iti_test.sh @@ -0,0 +1,56 @@ +# Copyright 2025 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Author: Maxime Colson - Thales + +if [ "$#" -eq 1 ]; then + ELF_ARG="$1" +elif [ "$#" -gt 1 ]; then + echo "Usage: $0 " + exit 1 +else + ELF_ARG="../tests/custom/ITI/test_iti_asm.o" +fi +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-testharness +fi + +# install the required tools +if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then + source ./verif/regress/install-verilator.sh +fi +source ./verif/regress/install-spike.sh + +# setup sim env +source ./verif/sim/setup-env.sh + +echo "$SPIKE_INSTALL_DIR$" + +if ! [ -n "$UVM_VERBOSITY" ]; then + export UVM_VERBOSITY=UVM_NONE +fi + +export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY" + +CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S ../tests/custom/ITI/iti_asm.S -I../tests/custom/env -I../tests/custom/common -lgcc" + +cd verif/sim/ + +make -C ../.. clean +make clean_all +python3 cva6.py --elf_tests "$ELF_ARG" --target cv32a60x --iss_yaml cva6.yaml --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld $DV_OPTS +#python3 cva6.py --c_tests ../tests/custom/ITI/test_iti_asm.c --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS +make -C ../.. clean +make clean_all + +cd - diff --git a/verif/regress/pmp_cv32a65x_tests.sh b/verif/regress/pmp_cv32a65x_tests.sh new file mode 100644 index 00000000000..5e65fb70075 --- /dev/null +++ b/verif/regress/pmp_cv32a65x_tests.sh @@ -0,0 +1,41 @@ +##----------------------------------------------------------------------------- +## Copyright 2024 Robert Bosch GmbH +## +## SPDX-License-Identifier: SHL-0.51 +## +## Original Author: Konstantinos Leventos - Robert Bosch France SAS +##----------------------------------------------------------------------------- + +# Where the tools are +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# Install the required tools +source ./verif/regress/install-spike.sh + +# Setup sim env +source ./verif/sim/setup-env.sh + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm +fi + +if ! [ -n "$UVM_VERBOSITY" ]; then + UVM_VERBOSITY=UVM_NONE +fi + +export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY" + +export DV_TARGET=cv32a65x + +make clean +cd verif/sim/ +make clean_all + +python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld + +make clean_all +cd - +make clean diff --git a/verif/regress/pmp_lsu_transaction.sh b/verif/regress/pmp_lsu_transaction.sh new file mode 100644 index 00000000000..428570bd5bb --- /dev/null +++ b/verif/regress/pmp_lsu_transaction.sh @@ -0,0 +1,69 @@ +#!/usr/bin/env bash +# Copyright 2026 OpenHW Group +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +set -eo pipefail + +if [[ -z "${RISCV:-}" ]]; then + echo "Error: RISCV variable undefined" >&2 + exit 1 +fi + +source verif/sim/setup-env.sh +set -u + +# These are self-checking architectural tests. Do not enable Spike tandem +# execution because the OpenHW RV64 Spike target does not describe these PMP +# regions. +unset SPIKE_TANDEM + +readonly standard_target="${DV_TARGET:-cv64a6_imafdc_sv39}" +readonly linker="../../config/gen_from_riscv_config/linker/link.ld" +readonly testlist="../tests/testlist_issues.yaml" +readonly no_mmu_options="${standard_target}"\ +" +CVA6ConfigDcacheFlushOnFence=0"\ +" +CVA6ConfigDcacheFlushOnFenceI=0"\ +" +CVA6ConfigDcacheInvalidateOnFlush=0"\ +" *MmuPresent=0" + +cd verif/sim + +run_test() { + local test_name="$1" + local target="$2" + shift 2 + + python3 cva6.py \ + --testlist="${testlist}" \ + --test="${test_name}" \ + --target="${target}" \ + --iss_yaml=cva6.yaml \ + --iss=veri-testharness \ + --linker="${linker}" \ + --issrun_opts=+debug_disable=1 \ + "$@" +} + +# Discard a model left by a previous run with a different configuration. +make -C ../.. clean + +run_test pmp-lsu-transaction-rv64 "${standard_target}" +run_test pmp-amo-access-fault-rv64 "${standard_target}" + +# The generated model does not track configuration variables as dependencies, +# so discard it before switching to the no-MMU configuration. +make -C ../.. clean + +run_test pmp-lsu-transaction-no-mmu-rv64 hwconfig \ + --hwconfig_opts="${no_mmu_options}" + +# HLVX carries its execute-permission requirement with the response too. +make -C ../.. clean +run_test pmp-hlvx-access-fault-rv64 cv64a6_imafdch_sv39 + +make -C ../.. clean +run_test pmp-hlvx-access-fault-rv64 hwconfig \ + --hwconfig_opts="cv64a6_imafdch_sv39 +CVA6ConfigDcacheFlushOnFence=0 +CVA6ConfigDcacheFlushOnFenceI=0 +CVA6ConfigDcacheInvalidateOnFlush=0 *MmuPresent=0" diff --git a/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh b/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh index d60ce010d24..311a9644247 100644 --- a/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh +++ b/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh @@ -13,6 +13,10 @@ if ! [ -n "$RISCV" ]; then return fi +if ! [ -n "$TARGET" ]; then + TARGET=cv64a6_imafdc_sv39 +fi + if ! [ -n "$DV_SIMULATORS" ]; then DV_SIMULATORS=vcs-testharness,spike fi @@ -46,12 +50,13 @@ cd verif/sim/ make -C ../.. clean make clean_all -python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld -python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS -python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --gcc_opts="$CC_OPTS -nostdlib -lgcc" $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld +python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target ${TARGET} --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target ${TARGET} --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target ${TARGET} --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64si-p-noncanonical --iss_yaml cva6.yaml --target ${TARGET} --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target ${TARGET} --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld +python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target ${TARGET} --iss=$DV_SIMULATORS $DV_OPTS +python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target ${TARGET} --iss=$DV_SIMULATORS --gcc_opts="$CC_OPTS -nostdlib -lgcc" $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld make -C ../.. clean make clean_all diff --git a/verif/regress/triggers-tests-cv32a60x.sh b/verif/regress/triggers-tests-cv32a60x.sh new file mode 100644 index 00000000000..01d35348636 --- /dev/null +++ b/verif/regress/triggers-tests-cv32a60x.sh @@ -0,0 +1,58 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Mounsaf YOUSFI - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-testharness,spike +fi + +# install the required tools +if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then + source ./verif/regress/install-verilator.sh +fi +source ./verif/regress/install-spike.sh + +# setup sim env +source ./verif/sim/setup-env.sh + +echo "$SPIKE_INSTALL_DIR$" + +if ! [ -n "$UVM_VERBOSITY" ]; then + export UVM_VERBOSITY=UVM_NONE +fi + +export DV_OPTS="$DV_OPTS --issrun_opts=+enable_interrupt+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY" + +CC_OPTS="-static \ + -mcmodel=medany \ + -fvisibility=hidden \ + -nostartfiles \ + -g \ + -O0 \ + ../tests/custom/common/syscalls.c \ + ../tests/custom/common/crt.S \ + -I../tests/custom/env \ + -I../tests/custom/common" + +DV_HWCONFIG_OPTS="cv32a60x Sdtrig=1 SdtrigMcontrol6=1 SdtrigMcontrol6ExecAddr=1 SdtrigMcontrol6ExecData=1 SdtrigMcontrol6Store=1 SdtrigMcontrol6LoadAddr=1 SdtrigMcontrol6LoadData=1 SdtrigIcount=1 SdtrigEtrigger=1 SdtrigItrigger=1 SdtrigNrTriggers=4 SdtrigTriggerChaining=1 SdtrigSupportedActions=2'b01 SdtrigSupportedMatch=10'b11_1111_1111 SdtrigSupportTextra=0" + +cd verif/sim/ + +make -C ../.. clean +make clean_all +python3 cva6.py --target hwconfig --hwconfig_opts="$DV_HWCONFIG_OPTS" --asm_tests=../tests/custom/trigger_tests/trigger_main.S --iss_yaml cva6.yaml --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1 +make -C ../.. clean +make clean_all + +cd - diff --git a/verif/regress/triggers-tests-cv32a65x.sh b/verif/regress/triggers-tests-cv32a65x.sh new file mode 100644 index 00000000000..9d03a026901 --- /dev/null +++ b/verif/regress/triggers-tests-cv32a65x.sh @@ -0,0 +1,58 @@ +# Copyright 2021 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Mounsaf YOUSFI - Thales + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-testharness,spike +fi + +# install the required tools +if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then + source ./verif/regress/install-verilator.sh +fi +source ./verif/regress/install-spike.sh + +# setup sim env +source ./verif/sim/setup-env.sh + +echo "$SPIKE_INSTALL_DIR$" + +if ! [ -n "$UVM_VERBOSITY" ]; then + export UVM_VERBOSITY=UVM_NONE +fi + +export DV_OPTS="$DV_OPTS --issrun_opts=+enable_interrupt+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY" + +CC_OPTS="-static \ + -mcmodel=medany \ + -fvisibility=hidden \ + -nostartfiles \ + -g \ + -O0 \ + ../tests/custom/common/syscalls.c \ + ../tests/custom/common/crt.S \ + -I../tests/custom/env \ + -I../tests/custom/common" + +DV_HWCONFIG_OPTS="cv32a65x Sdtrig=1 SdtrigMcontrol6=1 SdtrigMcontrol6ExecAddr=1 SdtrigMcontrol6ExecData=1 SdtrigMcontrol6Store=1 SdtrigMcontrol6LoadAddr=1 SdtrigMcontrol6LoadData=1 SdtrigIcount=1 SdtrigEtrigger=1 SdtrigItrigger=1 SdtrigNrTriggers=4 SdtrigTriggerChaining=1 SdtrigSupportedActions=2'b01 SdtrigSupportedMatch=10'b11_1111_1111 SdtrigSupportTextra=0" + +cd verif/sim/ + +make -C ../.. clean +make clean_all +python3 cva6.py --target hwconfig --hwconfig_opts="$DV_HWCONFIG_OPTS" --asm_tests=../tests/custom/trigger_tests/trigger_main.S --iss_yaml cva6.yaml --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1 +make -C ../.. clean +make clean_all + +cd - diff --git a/verif/regress/veri-testharness-pk-tests.sh b/verif/regress/veri-testharness-pk-tests.sh new file mode 100644 index 00000000000..8973a5401e0 --- /dev/null +++ b/verif/regress/veri-testharness-pk-tests.sh @@ -0,0 +1,129 @@ +#!/bin/bash +# Copyright 2025 Isaar AHMAD +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Isaar AHMAD +# +# ============================================================================== +# This script demonstrates how to simulate the CVA6 core using Verilator and the +# RISC-V Proxy Kernel (PK), using the DV_SIMULATOR "veri-testharness-pk". +# It runs two hello world simulations, one for a 64-bit target, and one for a +# 32-bit target. Both simulations are run in separate subshell(s) to isolate +# environment changes and directory moves. +# +# Usage (from the base of the repository): +# bash verif/regress/veri-testharness-pk-tests.sh +# +# ============================================================================== +# Exit immediately if a command exits with a non-zero status. +set -e + +# where are the tools +if ! [ -n "$RISCV" ]; then + echo "Error: The RISCV environment variable is not defined." + return +fi + +# Set the NUM_JOBS variable to increase the number of parallel make jobs +# export NUM_JOBS= + +# Global simulation settings, common to all runs. +export DV_SIMULATORS="veri-testharness-pk" +TIMEOUT_WALLCLOCK="800" +TIMEOUT_TICKS="5000000" + +# ============================================================================== +# Core simulation function +# This function wraps the entire process for running a single CVA6 +# simulation. It is parameterized to handle different target configurations. +# +# Args: +# $1: Target architecture (DV_TARGET) +# $2: Proxy kernel architecture (PK_ARCH) +# $3: Proxy kernel ABI (PK_MABI) +# ============================================================================== +run_cva6_simulation() { + # Use local variables to avoid polluting the global scope. + local DV_TARGET=$1 + local PK_ARCH=$2 + local PK_MABI=$3 + + # Run the logic in a subshell to isolate environment changes. + ( + # Exit this subshell immediately if a command fails. + set -e + + # Export the configuration specific to this simulation run. + export DV_TARGET + export PK_ARCH + export PK_MABI + + echo "--------------------------------------------------------" + echo "[ CVA6 ] Target: ${DV_TARGET}" + echo "[ CVA6 ] PK Arch: ${PK_ARCH}" + echo "[ CVA6 ] PK MABI: ${PK_MABI}" + echo "--------------------------------------------------------" + + # Install verilator if required by the simulator choice. + if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then + source ./verif/regress/install-verilator.sh + fi + + # Install RISC-V Proxy Kernel for the specified architecture. + # The log file is named after the target to prevent overwrites. + if [[ "$DV_SIMULATORS" == *"veri-testharness-pk"* ]]; then + local pk_log_file="./verif/sim/pk-install-${DV_TARGET}.log" + echo "[ riscv-pk ] Installing RISC-V proxy kernel for ${DV_TARGET}..." + source ./verif/regress/install-pk.sh ${PK_ARCH} ${PK_MABI} > ${pk_log_file} 2>&1 + echo "[ riscv-pk ] Installation logs available at: $(pwd)/${pk_log_file}" + echo "[ riscv-pk ] PK_INSTALL_DIR is ${PK_INSTALL_DIR}" + fi + + # Set up the simulation environment. navigate to simulation directory. + source ./verif/sim/setup-env.sh + cd ./verif/sim + + # GCC options (customize if needed). + local CC_OPTS="" + + echo "[ CVA6 ] Starting pytohn simulation script..." + # Execute the main simulation command. + python3 cva6.py \ + --target "$DV_TARGET" \ + --iss="$DV_SIMULATORS" \ + --iss_yaml=cva6.yaml \ + --iss_timeout="$TIMEOUT_WALLCLOCK" \ + --c_tests ../tests/custom/hello_world/hello_world.c \ + --gcc_opts="$CC_OPTS" \ + --issrun_opts="+time_out=$TIMEOUT_TICKS" + ) +} + +# ============================================================================== +# Main Execution +# This block calls run_simulation_cva6 twice - once for each simulation run. +# ============================================================================== +export DV_TARGET1="cv64a6_imafdc_sv39" +export PK_ARCH1="rv64gc_zba_zbb_zbs_zbc_zbkb_zbkx_zkne_zknd_zknh" +export PK_MABI1="lp64d" + +export DV_TARGET2="cv32a6_imac_sv32" +export PK_ARCH2="rv32imac_zbkb_zbkx_zkne_zknd_zknh_zicsr_zifencei" +export PK_MABI2="ilp32" + +COLOR_GREEN='\033[0;32m' +COLOR_NONE='\033[0m' # No Color +# --- Simulation 1: cv64a6_imafdc_sv39 +echo -e "${COLOR_GREEN} ============== Starting simualtion 1: ${DV_TARGET1} ====================== ${COLOR_NONE}" +run_cva6_simulation ${DV_TARGET1} ${PK_ARCH1} ${PK_MABI1} +echo -e "${COLOR_GREEN} ============== Finished simulation 1: ${DV_TARGET1} ====================== ${COLOR_NONE}" + +# --- Simulation 2: cv32a6_imac_sv32 --- +echo -e "${COLOR_GREEN} ============== Starting simualtion 2: ${DV_TARGET2} ====================== ${COLOR_NONE}" +run_cva6_simulation ${DV_TARGET2} ${PK_ARCH2} ${PK_MABI2} +echo -e "${COLOR_GREEN} ============== Finished simulation 2: ${DV_TARGET2} ====================== ${COLOR_NONE}" + +echo "All simulations finished successfully." diff --git a/verif/sim/Makefile b/verif/sim/Makefile index 1a71754c0f2..05efa32b57f 100644 --- a/verif/sim/Makefile +++ b/verif/sim/Makefile @@ -350,8 +350,7 @@ questa_uvm_comp: -suppress vlog-2745 -suppress vlog-8386 \ -suppress vlog-8607 \ +define+UNSUPPORTED_WITH+ \ - +define+QUESTA+ \ - $(cov-comp-opt) $(isscomp_opts) + +define+QUESTA vopt -work $(VSIM_WORK_DIR) \ -64 +acc uvmt_cva6_tb -o uvmt_cva6_tb_opt @@ -359,6 +358,7 @@ questa_uvm_run: @echo "[QUESTA] Running Model" vsim -64 \ $(COMMON_RUN_UVM_FLAGS) \ + $(COMMON_RUN_ARGS) \ -sv_lib $(QUESTASIM_HOME)/uvm-1.2/linux_x86_64/uvm_dpi \ -c -do "run -all; " \ -work $(VSIM_WORK_DIR) -t 1ns \ @@ -366,13 +366,14 @@ questa_uvm_run: -suppress 3829 -suppress vsim-8386\ +permissive \ -sv_seed 0 \ - $(cov-run-opt) $(issrun_opts) \ + -noautoldlibpath \ +define+UNSUPPORTED_WITH+ \ + $(issrun_opts) \ uvmt_cva6_tb_opt + $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) + grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm # TODO: Add support for waveform collection. - #$(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log) - #grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm questa-uvm: make questa_uvm_comp @@ -411,6 +412,22 @@ vcs-testharness: $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm +veri-testharness-pk: + rm -rf $(path_var)/work-ver + @echo "Trace compact value $(TRACE_COMPACT)" + make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts)) + $(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) \ + $(PK_INSTALL_DIR)/riscv-none-elf/bin/pk $(elf) \ + +tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(PK_INSTALL_DIR)/riscv-none-elf/bin/pk | grep -w tohost | cut -d' ' -f1) \ + $(issrun_opts) + # If present, move default waveform files to log directory. + # Keep track of target in waveform file name. + [ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.fst + [ ! -f verilator.vcd ] || mv verilator.vcd `dirname $(log)`/`basename $(log) .log`.vcd + # Generate disassembled log. + $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log) + grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm + veri-testharness: make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts)) $(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \ @@ -452,6 +469,7 @@ clean_all: vcs_clean_all rm -f trace*.log rm -f trace*.dasm rm -f *.vpd *.fsdb *.vcd *.fst + rm -f *.trace help: @echo "Shell environment:" diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py index 4c5075ec89e..8e678f53f89 100644 --- a/verif/sim/cva6.py +++ b/verif/sim/cva6.py @@ -508,13 +508,20 @@ def run_test(test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir, if test_type != "o": # gcc compilation logging.info("Compiling test: %s" % test_path) - cmd = ("%s %s \ - -I%s/dv/user_extension \ - -T%s %s -o %s " % \ - (get_env_var("RISCV_CC", debug_cmd = debug_cmd), test_path, cwd, - linker, gcc_opts, elf)) - cmd += (" -march=%s" % isa) - cmd += (" -mabi=%s" % mabi) + if "veri-testharness-pk" not in iss_list: + + cmd = ("%s %s \ + -I%s/dv/user_extension \ + -T%s %s -o %s " % \ + (get_env_var("RISCV_CC", debug_cmd = debug_cmd), test_path, cwd, + linker, gcc_opts, elf)) + else: # veri-testharness with proxy kernel enabled. + cmd= ("%s %s %s -o %s " % (get_env_var("RISCV_CC", debug_cmd = debug_cmd), test_path, gcc_opts, elf)) + if not re.search(r"(?:^|\s)-march=", cmd): + cmd += (" -march=%s" % isa) + if not re.search(r"(?:^|\s)-mabi=", cmd): + cmd += (" -mabi=%s" % mabi) + logging.info("Compilation cmd: %s" % cmd) run_cmd(cmd, debug_cmd = debug_cmd) log_list = [] # ISS simulation @@ -884,12 +891,12 @@ def load_config(args, cwd): if base in ("cv64a6_imafdch_sv39", "cv64a6_imafdch_sv39_wb"): args.mabi = "lp64d" args.isa = "rv64gch_zba_zbb_zbs_zbc" - elif base in ("cv64a6_imafdc_sv39_wb"): + elif base in ("cv64a6_imafdc_sv39_wb",): args.mabi = "lp64d" args.isa = "rv64gc_zba_zbb_zbs_zbc" elif base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_hpdcache_wb"): args.mabi = "lp64d" - args.isa = "rv64gc_zba_zbb_zbs_zbc_zbkb" + args.isa = "rv64gc_zba_zbb_zbs_zbc_zbkb_zbkx_zkne_zknd_zknh" elif base == "cv32a60x": args.mabi = "ilp32" args.isa = "rv32imc_zba_zbb_zbs_zbc" @@ -906,7 +913,7 @@ def load_config(args, cwd): args.isa = "rv32imac" elif base == "cv32a6_imac_sv32": args.mabi = "ilp32" - args.isa = "rv32imac_zbkb" + args.isa = "rv32imac_zbkb_zbkx_zkne_zknd_zknh" elif base == "cv32a6_imafc_sv32": args.mabi = "ilp32f" args.isa = "rv32imafc" @@ -1025,7 +1032,8 @@ def check_spike_version(): logging.info(f"Spike Version: {user_spike_stderr_string}") - if user_spike_stderr_string != spike_version: + n = min(len(user_spike_stderr_string), len(spike_version)) + if user_spike_stderr_string[:n] != spike_version[:n]: incorrect_version_exit("Spike", user_spike_stderr_string, spike_version) diff --git a/verif/sim/cva6.yaml b/verif/sim/cva6.yaml index 6011296027a..5286f2494d8 100644 --- a/verif/sim/cva6.yaml +++ b/verif/sim/cva6.yaml @@ -30,6 +30,16 @@ cmd: > make veri-testharness target= variant= elf= path_var= tool_path= isscomp_opts= issrun_opts= isspostrun_opts= log= +############################################################################### +# Verilator with RISCV proxy kernel support +############################################################################### +- iss: veri-testharness-pk + path_var: RTL_PATH + tool_path: SPIKE_PATH + tb_path: TB_PATH + cmd: > + make veri-testharness-pk target= variant= elf= path_var= tool_path= isscomp_opts= issrun_opts= isspostrun_opts= log= + ############################################################################### # Synopsys VCS specific commands, variables ############################################################################### diff --git a/verif/sim/dv b/verif/sim/dv index f0c570d1123..7e54b678ab7 160000 --- a/verif/sim/dv +++ b/verif/sim/dv @@ -1 +1 @@ -Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580 +Subproject commit 7e54b678ab7499040336255550cdbd99ae887431 diff --git a/verif/tb/core/Flist.cva6_tb b/verif/tb/core/Flist.cva6_tb index a7dbd115911..4ec7dae6131 100644 --- a/verif/tb/core/Flist.cva6_tb +++ b/verif/tb/core/Flist.cva6_tb @@ -20,7 +20,7 @@ // // Manifest for the CVA6 TB. // - This is a CORE-ONLY testbench. -// - Relevent simulation scripts/Makefiles must set the shell ENV variable +// - Relevant simulation scripts/Makefiles must set the shell ENV variable // CVA6_TB_DIR as required. // /////////////////////////////////////////////////////////////////////////////// diff --git a/verif/tb/core/README.md b/verif/tb/core/README.md index eb3c4f63b12..de3edcac3ec 100644 --- a/verif/tb/core/README.md +++ b/verif/tb/core/README.md @@ -1,5 +1,5 @@ ## Experimental Stand-alone testbench for the CVA6 -This do-nothing TB supports experiments with the CVA6 to develop a standalone testbenech for the CVA6. +This do-nothing TB supports experiments with the CVA6 to develop a standalone testbench for the CVA6. It uses a "core-only" manifest file `Flist.cva6`. ### Current status: diff --git a/verif/tb/core/bootrom/Makefile b/verif/tb/core/bootrom/Makefile index 86708317c8d..2d44fea2bca 100644 --- a/verif/tb/core/bootrom/Makefile +++ b/verif/tb/core/bootrom/Makefile @@ -1,7 +1,7 @@ ############################################################################### # $@ is the file being generated. -# $< is first prerequiste. -# $^ is all prerequistes. +# $< is first prerequisite. +# $^ is all prerequisites. # $* is file_name (w/o extension) of target DTB ?= cva6.dtb diff --git a/verif/tb/core/cva6_tb_verilator.cpp b/verif/tb/core/cva6_tb_verilator.cpp index b0ebe688a22..e1ac95dae66 100644 --- a/verif/tb/core/cva6_tb_verilator.cpp +++ b/verif/tb/core/cva6_tb_verilator.cpp @@ -20,7 +20,7 @@ ******************************************************************************* * * Verilator top for the CVA6 "core_only" testbench. - * Genrates clock, reset and optionally dumps waves. + * Generates clock, reset and optionally dumps waves. * ******************************************************************************* */ diff --git a/verif/tb/csr_unit/Makefile b/verif/tb/csr_unit/Makefile new file mode 100644 index 00000000000..8aee7b55c5b --- /dev/null +++ b/verif/tb/csr_unit/Makefile @@ -0,0 +1,19 @@ +ROOT := ../../.. +BUILD := .build/mstatus_wpri_test + +SOURCES := \ + $(ROOT)/core/include/config_pkg.sv \ + $(ROOT)/core/include/cv64a6_imafdc_sv39_config_pkg.sv \ + $(ROOT)/core/include/build_config_pkg.sv \ + $(ROOT)/core/include/riscv_pkg.sv \ + $(ROOT)/core/include/ariane_pkg.sv \ + $(ROOT)/core/include/triggers_pkg.sv \ + $(ROOT)/core/trigger_module.sv \ + $(ROOT)/core/csr_regfile.sv \ + mstatus_wpri_test.sv + +.PHONY: mstatus_wpri_test +mstatus_wpri_test: + mkdir -p .build + verilator --binary --assert --timing -Wno-fatal -Wno-PINMISSING -Wno-WIDTHTRUNC -Wno-WIDTHEXPAND -Wno-MULTIDRIVEN -I$(ROOT)/core/include --top-module mstatus_wpri_test --Mdir $(BUILD) $(SOURCES) + $(BUILD)/Vmstatus_wpri_test diff --git a/verif/tb/csr_unit/mstatus_wpri_test.sv b/verif/tb/csr_unit/mstatus_wpri_test.sv new file mode 100644 index 00000000000..079132ef8a3 --- /dev/null +++ b/verif/tb/csr_unit/mstatus_wpri_test.sv @@ -0,0 +1,107 @@ +`include "rvfi_types.svh" + +module mstatus_wpri_test; + import ariane_pkg::*; + + localparam config_pkg::cva6_cfg_t CVA6Cfg = build_config_pkg::build_config( + cva6_config_pkg::cva6_cfg + ); + + typedef struct packed { + logic [CVA6Cfg.XLEN-1:0] cause; + logic [CVA6Cfg.XLEN-1:0] tval; + logic [CVA6Cfg.GPLEN-1:0] tval2; + logic [31:0] tinst; + logic gva; + logic valid; + logic timing; + } exception_t; + + typedef struct packed { + logic [CVA6Cfg.VLEN-1:0] predict_address; + } branchpredict_t; + + typedef struct packed { + logic [CVA6Cfg.VLEN-1:0] pc; + fu_t fu; + branchpredict_t bp; + logic is_compressed; + } scoreboard_entry_t; + + typedef struct packed { + logic [CVA6Cfg.XLEN-7:0] base; + logic [5:0] mode; + } jvt_t; + + typedef struct packed { + logic [CVA6Cfg.XLEN-1:0] mie; + logic [CVA6Cfg.XLEN-1:0] mip; + logic [CVA6Cfg.XLEN-1:0] mideleg; + logic [CVA6Cfg.XLEN-1:0] hideleg; + logic sie; + logic global_enable; + } irq_ctrl_t; + + typedef `RVFI_PROBES_CSR_T(CVA6Cfg) rvfi_probes_csr_t; + + logic clk_i; + logic rst_ni; + scoreboard_entry_t commit_instr_i; + logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i; + exception_t ex_i; + fu_op csr_op_i; + logic [11:0] csr_addr_i; + logic [CVA6Cfg.XLEN-1:0] csr_wdata_i; + logic [CVA6Cfg.XLEN-1:0] csr_rdata_o; + exception_t csr_exception_o; + + always #1 clk_i = ~clk_i; + + csr_regfile #( + .CVA6Cfg(CVA6Cfg), + .exception_t(exception_t), + .jvt_t(jvt_t), + .irq_ctrl_t(irq_ctrl_t), + .scoreboard_entry_t(scoreboard_entry_t), + .rvfi_probes_csr_t(rvfi_probes_csr_t) + ) dut ( + .clk_i, + .rst_ni, + .commit_instr_i, + .commit_ack_i, + .ex_i, + .csr_op_i, + .csr_addr_i, + .csr_wdata_i, + .csr_rdata_o, + .csr_exception_o + ); + + initial begin + clk_i = 1'b0; + rst_ni = 1'b0; + commit_instr_i = '0; + commit_ack_i = '0; + ex_i = '0; + csr_op_i = CSR_READ; + csr_addr_i = riscv::CSR_MSTATUS; + csr_wdata_i = '0; + + #3; + rst_ni = 1'b1; + @(negedge clk_i); + + csr_op_i = CSR_WRITE; + csr_wdata_i = (64'(1) << 62) | (64'(1) << 50) | (64'(1) << 38); + @(negedge clk_i); + + csr_op_i = CSR_READ; + #1; + + assert (!csr_exception_o.valid) else $fatal(1, "mstatus access failed"); + assert ((csr_rdata_o & csr_wdata_i) == '0) else $fatal(1, "reserved mstatus bits are writable"); + + $display("PASS: reserved mstatus bits stay zero"); + $finish; + end +endmodule diff --git a/verif/tb/decoder_unit/Makefile b/verif/tb/decoder_unit/Makefile new file mode 100644 index 00000000000..7d6a0903108 --- /dev/null +++ b/verif/tb/decoder_unit/Makefile @@ -0,0 +1,26 @@ +ROOT := ../../.. +BUILD := .build/zicbom_permissions_test + +SOURCES := \ + $(ROOT)/core/include/config_pkg.sv \ + $(ROOT)/core/include/cv64a6_imafdch_sv39_config_pkg.sv \ + $(ROOT)/core/include/build_config_pkg.sv \ + $(ROOT)/core/include/riscv_pkg.sv \ + $(ROOT)/core/include/ariane_pkg.sv \ + $(ROOT)/core/decoder.sv \ + zicbom_permissions_test.sv + +.PHONY: zicbom_permissions_test +zicbom_permissions_test: + mkdir -p .build + verilator --binary --assert --timing \ + -Wno-fatal \ + -Wno-PINMISSING \ + -Wno-UNOPTFLAT \ + -Wno-WIDTHTRUNC \ + -Wno-WIDTHEXPAND \ + -I$(ROOT)/core/include \ + --top-module zicbom_permissions_test \ + --Mdir $(BUILD) \ + $(SOURCES) + $(BUILD)/Vzicbom_permissions_test diff --git a/verif/tb/decoder_unit/zicbom_permissions_test.sv b/verif/tb/decoder_unit/zicbom_permissions_test.sv new file mode 100644 index 00000000000..3d5c29148ed --- /dev/null +++ b/verif/tb/decoder_unit/zicbom_permissions_test.sv @@ -0,0 +1,352 @@ +module zicbom_permissions_test; + import ariane_pkg::*; + + function automatic config_pkg::cva6_cfg_t make_test_cfg(); + config_pkg::cva6_user_cfg_t cfg; + cfg = cva6_config_pkg::cva6_cfg; + + // The stock H configuration has RVH enabled but Zicbom disabled. + // Enable Zicbom locally for this decoder regression. + cfg.RVZiCbom = 1'b1; + + // Disable CV-X-IF so decoder-generated illegal instructions directly + // become architectural exceptions in this standalone test. + cfg.CvxifEn = 1'b0; + + return build_config_pkg::build_config(cfg); + endfunction + + localparam config_pkg::cva6_cfg_t CVA6Cfg = make_test_cfg(); + + typedef struct packed { + cf_t cf; + logic [CVA6Cfg.VLEN-1:0] predict_address; + } branchpredict_sbe_t; + + typedef struct packed { + logic [CVA6Cfg.XLEN-1:0] cause; + logic [CVA6Cfg.XLEN-1:0] tval; + logic [CVA6Cfg.GPLEN-1:0] tval2; + logic [31:0] tinst; + logic gva; + logic valid; + logic timing; + } exception_t; + + typedef struct packed { + logic [CVA6Cfg.VLEN-1:0] pc; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id; + fu_t fu; + fu_op op; + logic [REG_ADDR_SIZE-1:0] rs1; + logic [REG_ADDR_SIZE-1:0] rs2; + logic [REG_ADDR_SIZE-1:0] rd; + logic [CVA6Cfg.XLEN-1:0] result; + logic valid; + logic use_imm; + logic use_zimm; + logic use_pc; + exception_t ex; + branchpredict_sbe_t bp; + logic is_compressed; + logic is_macro_instr; + logic is_last_macro_instr; + logic is_double_rd_macro_instr; + logic vfp; + logic is_zcmt; + } scoreboard_entry_t; + + typedef struct packed { + logic [CVA6Cfg.XLEN-1:0] mie; + logic [CVA6Cfg.XLEN-1:0] mip; + logic [CVA6Cfg.XLEN-1:0] mideleg; + logic [CVA6Cfg.XLEN-1:0] hideleg; + logic sie; + logic global_enable; + } irq_ctrl_t; + + typedef struct packed { + logic [CVA6Cfg.XLEN-1:0] S_SW; + logic [CVA6Cfg.XLEN-1:0] VS_SW; + logic [CVA6Cfg.XLEN-1:0] M_SW; + logic [CVA6Cfg.XLEN-1:0] S_TIMER; + logic [CVA6Cfg.XLEN-1:0] VS_TIMER; + logic [CVA6Cfg.XLEN-1:0] M_TIMER; + logic [CVA6Cfg.XLEN-1:0] S_EXT; + logic [CVA6Cfg.XLEN-1:0] VS_EXT; + logic [CVA6Cfg.XLEN-1:0] M_EXT; + logic [CVA6Cfg.XLEN-1:0] HS_EXT; + } interrupts_t; + + localparam interrupts_t INTERRUPTS = '0; + + localparam logic [31:0] CBO_INVAL_INSN = 32'h0000_200f; + localparam logic [31:0] CBO_CLEAN_INSN = 32'h0010_200f; + localparam logic [31:0] CBO_FLUSH_INSN = 32'h0020_200f; + + logic debug_req_i; + logic [CVA6Cfg.VLEN-1:0] pc_i; + logic is_compressed_i; + logic [15:0] compressed_instr_i; + logic is_illegal_i; + logic [31:0] instruction_i; + logic is_macro_instr_i; + logic is_last_macro_instr_i; + logic is_double_rd_macro_instr_i; + logic is_zcmt_i; + logic [CVA6Cfg.XLEN-1:0] jump_address_i; + branchpredict_sbe_t branch_predict_i; + exception_t ex_i; + logic [1:0] irq_i; + irq_ctrl_t irq_ctrl_i; + riscv::priv_lvl_t priv_lvl_i; + logic v_i; + logic debug_mode_i; + riscv::xs_t fs_i; + riscv::xs_t vfs_i; + logic [2:0] frm_i; + riscv::xs_t vs_i; + logic tvm_i; + logic tw_i; + logic vtw_i; + logic tsr_i; + logic hu_i; + + riscv::cbie_t mcbie_i; + riscv::cbie_t scbie_i; + riscv::cbie_t hcbie_i; + + logic mcbcfe_i; + logic scbcfe_i; + logic hcbcfe_i; + + scoreboard_entry_t instruction_o; + logic [31:0] orig_instr_o; + logic is_control_flow_instr_o; + logic [CVA6Cfg.XLEN-1:0] sdtrig_decoder_action_i; + + integer errors; + + decoder #( + .CVA6Cfg(CVA6Cfg), + .branchpredict_sbe_t(branchpredict_sbe_t), + .exception_t(exception_t), + .irq_ctrl_t(irq_ctrl_t), + .scoreboard_entry_t(scoreboard_entry_t), + .interrupts_t(interrupts_t), + .INTERRUPTS(INTERRUPTS) + ) dut ( + .debug_req_i, + .pc_i, + .is_compressed_i, + .compressed_instr_i, + .is_illegal_i, + .instruction_i, + .is_macro_instr_i, + .is_last_macro_instr_i, + .is_double_rd_macro_instr_i, + .is_zcmt_i, + .jump_address_i, + .branch_predict_i, + .ex_i, + .irq_i, + .irq_ctrl_i, + .priv_lvl_i, + .v_i, + .debug_mode_i, + .fs_i, + .vfs_i, + .frm_i, + .vs_i, + .tvm_i, + .tw_i, + .vtw_i, + .tsr_i, + .hu_i, + .mcbie_i, + .scbie_i, + .hcbie_i, + .mcbcfe_i, + .scbcfe_i, + .hcbcfe_i, + .instruction_o, + .orig_instr_o, + .is_control_flow_instr_o, + .sdtrig_decoder_action_i + ); + + task automatic run_case(input string name, input logic [31:0] instr_word, + input riscv::priv_lvl_t priv, input logic v, input logic hu, + input riscv::cbie_t mcbie, input riscv::cbie_t scbie, + input riscv::cbie_t hcbie, input logic mcbcfe, input logic scbcfe, + input logic hcbcfe, input logic expected_trap, + input logic [CVA6Cfg.XLEN-1:0] expected_cause, input fu_op expected_op); + begin + instruction_i = instr_word; + priv_lvl_i = priv; + v_i = v; + hu_i = hu; + + mcbie_i = mcbie; + scbie_i = scbie; + hcbie_i = hcbie; + + mcbcfe_i = mcbcfe; + scbcfe_i = scbcfe; + hcbcfe_i = hcbcfe; + + #1; + + if (instruction_o.ex.valid !== expected_trap) begin + $display("FAIL: %s: trap valid=%0b expected=%0b", name, instruction_o.ex.valid, + expected_trap); + errors = errors + 1; + end else if (expected_trap && instruction_o.ex.cause !== expected_cause) begin + $display("FAIL: %s: cause=%0d expected=%0d", name, instruction_o.ex.cause, expected_cause); + errors = errors + 1; + end else if (!expected_trap && instruction_o.op !== expected_op) begin + $display("FAIL: %s: op=%0d expected=%0d", name, instruction_o.op, expected_op); + errors = errors + 1; + end else begin + $display("PASS: %s", name); + end + end + endtask + + initial begin + errors = 0; + + debug_req_i = 1'b0; + pc_i = '0; + is_compressed_i = 1'b0; + compressed_instr_i = '0; + is_illegal_i = 1'b0; + instruction_i = '0; + is_macro_instr_i = 1'b0; + is_last_macro_instr_i = 1'b0; + is_double_rd_macro_instr_i = 1'b0; + is_zcmt_i = 1'b0; + jump_address_i = '0; + branch_predict_i = '0; + ex_i = '0; + irq_i = '0; + irq_ctrl_i = '0; + priv_lvl_i = riscv::PRIV_LVL_M; + v_i = 1'b0; + debug_mode_i = 1'b0; + fs_i = riscv::Off; + vfs_i = riscv::Off; + frm_i = '0; + vs_i = riscv::Off; + tvm_i = 1'b0; + tw_i = 1'b0; + vtw_i = 1'b0; + tsr_i = 1'b0; + hu_i = 1'b0; + mcbie_i = riscv::CBIE_INVAL; + scbie_i = riscv::CBIE_INVAL; + hcbie_i = riscv::CBIE_INVAL; + mcbcfe_i = 1'b1; + scbcfe_i = 1'b1; + hcbcfe_i = 1'b1; + sdtrig_decoder_action_i = '0; + + #1; + + // HU must not turn ordinary host U-mode into VU. + run_case("host U ignores HU for INVAL", CBO_INVAL_INSN, riscv::PRIV_LVL_U, 1'b0, 1'b1, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b1, 1'b1, 1'b1, 1'b0, '0, + ariane_pkg::CBO_INVAL); + + // VU + senvcfg.CBIE=00 -> virtual-instruction. + run_case("VU sCBIE illegal is virtual", CBO_INVAL_INSN, riscv::PRIV_LVL_U, 1'b1, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_ILLEGAL, riscv::CBIE_INVAL, 1'b1, 1'b1, 1'b1, 1'b1, + riscv::VIRTUAL_INSTRUCTION, ariane_pkg::CBO_INVAL); + + // VS + henvcfg.CBIE=00 -> virtual-instruction. + run_case("VS hCBIE illegal is virtual", CBO_INVAL_INSN, riscv::PRIV_LVL_S, 1'b1, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_ILLEGAL, 1'b1, 1'b1, 1'b1, 1'b1, + riscv::VIRTUAL_INSTRUCTION, ariane_pkg::CBO_INVAL); + + // VU + henvcfg.CBIE=00 -> virtual-instruction. + run_case("VU hCBIE illegal is virtual", CBO_INVAL_INSN, riscv::PRIV_LVL_U, 1'b1, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_ILLEGAL, 1'b1, 1'b1, 1'b1, 1'b1, + riscv::VIRTUAL_INSTRUCTION, ariane_pkg::CBO_INVAL); + + // henvcfg does not govern HS execution. + run_case("HS ignores hCBIE", CBO_INVAL_INSN, riscv::PRIV_LVL_S, 1'b0, 1'b0, riscv::CBIE_INVAL, + riscv::CBIE_INVAL, riscv::CBIE_ILLEGAL, 1'b1, 1'b1, 1'b1, 1'b0, '0, + ariane_pkg::CBO_INVAL); + + // VS henvcfg.CBIE=01 performs a flush. + run_case("VS hCBIE flush", CBO_INVAL_INSN, riscv::PRIV_LVL_S, 1'b1, 1'b0, riscv::CBIE_INVAL, + riscv::CBIE_INVAL, riscv::CBIE_FLUSH, 1'b1, 1'b1, 1'b1, 1'b0, '0, + ariane_pkg::CBO_FLUSH); + + // VU senvcfg.CBIE=01 performs a flush. + run_case("VU sCBIE flush", CBO_INVAL_INSN, riscv::PRIV_LVL_U, 1'b1, 1'b0, riscv::CBIE_INVAL, + riscv::CBIE_FLUSH, riscv::CBIE_INVAL, 1'b1, 1'b1, 1'b1, 1'b0, '0, + ariane_pkg::CBO_FLUSH); + + // VU henvcfg.CBIE=01 performs a flush. + run_case("VU hCBIE flush", CBO_INVAL_INSN, riscv::PRIV_LVL_U, 1'b1, 1'b0, riscv::CBIE_INVAL, + riscv::CBIE_INVAL, riscv::CBIE_FLUSH, 1'b1, 1'b1, 1'b1, 1'b0, '0, + ariane_pkg::CBO_FLUSH); + + // VS CBO.CLEAN with henvcfg.CBCFE=0 -> virtual-instruction. + run_case("VS CLEAN hCBCFE disabled", CBO_CLEAN_INSN, riscv::PRIV_LVL_S, 1'b1, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b1, 1'b1, 1'b0, 1'b1, + riscv::VIRTUAL_INSTRUCTION, ariane_pkg::CBO_CLEAN); + + // VU requires both henvcfg.CBCFE and senvcfg.CBCFE. + run_case("VU FLUSH hCBCFE disabled", CBO_FLUSH_INSN, riscv::PRIV_LVL_U, 1'b1, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b1, 1'b1, 1'b0, 1'b1, + riscv::VIRTUAL_INSTRUCTION, ariane_pkg::CBO_FLUSH); + + run_case("VU FLUSH sCBCFE disabled", CBO_FLUSH_INSN, riscv::PRIV_LVL_U, 1'b1, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b1, 1'b0, 1'b1, 1'b1, + riscv::VIRTUAL_INSTRUCTION, ariane_pkg::CBO_FLUSH); + + // Ordinary host U still gets cause 2 from senvcfg.CBCFE. + run_case("host U CLEAN sCBCFE disabled", CBO_CLEAN_INSN, riscv::PRIV_LVL_U, 1'b0, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b1, 1'b0, 1'b1, 1'b1, + riscv::ILLEGAL_INSTR, ariane_pkg::CBO_CLEAN); + + // An INVAL converted to FLUSH by CBIE must not be rejected by CBCFE. + run_case("S INVAL-as-FLUSH ignores mCBCFE", CBO_INVAL_INSN, riscv::PRIV_LVL_S, 1'b0, 1'b0, + riscv::CBIE_FLUSH, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b0, 1'b1, 1'b1, 1'b0, '0, + ariane_pkg::CBO_FLUSH); + + run_case("U INVAL-as-FLUSH ignores sCBCFE", CBO_INVAL_INSN, riscv::PRIV_LVL_U, 1'b0, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_FLUSH, riscv::CBIE_INVAL, 1'b1, 1'b0, 1'b1, 1'b0, '0, + ariane_pkg::CBO_FLUSH); + + // Genuine FLUSH remains governed by CBCFE. + run_case("S genuine FLUSH obeys mCBCFE", CBO_FLUSH_INSN, riscv::PRIV_LVL_S, 1'b0, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b0, 1'b1, 1'b1, 1'b1, + riscv::ILLEGAL_INSTR, ariane_pkg::CBO_FLUSH); + + run_case("U genuine FLUSH obeys sCBCFE", CBO_FLUSH_INSN, riscv::PRIV_LVL_U, 1'b0, 1'b0, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b1, 1'b0, 1'b1, 1'b1, + riscv::ILLEGAL_INSTR, ariane_pkg::CBO_FLUSH); + + // menvcfg checks have higher priority and still produce cause 2 + // even while V=1. + run_case("guest mCBIE illegal remains illegal", CBO_INVAL_INSN, riscv::PRIV_LVL_S, 1'b1, 1'b0, + riscv::CBIE_ILLEGAL, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b1, 1'b1, 1'b1, 1'b1, + riscv::ILLEGAL_INSTR, ariane_pkg::CBO_INVAL); + + // HU must likewise not make host U subject to henvcfg.CBCFE. + run_case("host U ignores HU for CBCFE", CBO_CLEAN_INSN, riscv::PRIV_LVL_U, 1'b0, 1'b1, + riscv::CBIE_INVAL, riscv::CBIE_INVAL, riscv::CBIE_INVAL, 1'b1, 1'b1, 1'b0, 1'b0, '0, + ariane_pkg::CBO_CLEAN); + + if (errors != 0) begin + $fatal(1, "FAIL: %0d Zicbom permission checks failed", errors); + end + + $display("PASS: all Zicbom permission checks passed"); + $finish; + end + +endmodule diff --git a/verif/tb/macro_decoder_unit/Makefile b/verif/tb/macro_decoder_unit/Makefile new file mode 100644 index 00000000000..173fbdaac9f --- /dev/null +++ b/verif/tb/macro_decoder_unit/Makefile @@ -0,0 +1,33 @@ +ROOT := ../../.. +BUILD := .build/macro_decoder_issue_ack_test + +SOURCES := \ + $(ROOT)/core/include/config_pkg.sv \ + $(ROOT)/core/include/cv32a6_imac_sv32_config_pkg.sv \ + $(ROOT)/core/include/build_config_pkg.sv \ + $(ROOT)/core/include/riscv_pkg.sv \ + $(ROOT)/core/macro_decoder.sv \ + macro_decoder_issue_ack_test.sv + +.PHONY: all macro_decoder_issue_ack_test clean + +all: macro_decoder_issue_ack_test + +macro_decoder_issue_ack_test: + mkdir -p .build + verilator \ + --binary \ + --assert \ + --timing \ + -Wno-fatal \ + -Wno-PINMISSING \ + -Wno-WIDTHTRUNC \ + -Wno-WIDTHEXPAND \ + -I$(ROOT)/core/include \ + --top-module macro_decoder_issue_ack_test \ + --Mdir $(BUILD) \ + $(SOURCES) + $(BUILD)/Vmacro_decoder_issue_ack_test + +clean: + rm -rf .build diff --git a/verif/tb/macro_decoder_unit/macro_decoder_issue_ack_test.sv b/verif/tb/macro_decoder_unit/macro_decoder_issue_ack_test.sv new file mode 100644 index 00000000000..0307a302b1d --- /dev/null +++ b/verif/tb/macro_decoder_unit/macro_decoder_issue_ack_test.sv @@ -0,0 +1,166 @@ +module macro_decoder_issue_ack_test; + + localparam config_pkg::cva6_cfg_t CVA6Cfg = build_config_pkg::build_config( + cva6_config_pkg::cva6_cfg + ); + + // macro_decoder FSM encoding. + localparam logic [2:0] ST_IDLE = 3'd0; + localparam logic [2:0] ST_PUSH_ADDI = 3'd2; + localparam logic [2:0] ST_POPRETZ_1 = 3'd3; + localparam logic [2:0] ST_MOVE = 3'd4; + localparam logic [2:0] ST_PUSH_POP_INSTR_2 = 3'd5; + + logic clk_i; + logic rst_ni; + logic [31:0] instr_i; + logic is_macro_instr_i; + logic illegal_instr_i; + logic is_compressed_i; + logic issue_ack_i; + + logic [31:0] instr_o; + logic illegal_instr_o; + logic is_compressed_o; + logic fetch_stall_o; + logic is_last_macro_instr_o; + logic is_double_rd_macro_instr_o; + + always #5 clk_i = ~clk_i; + + macro_decoder #( + .CVA6Cfg(CVA6Cfg) + ) dut ( + .instr_i, + .clk_i, + .rst_ni, + .is_macro_instr_i, + .illegal_instr_i, + .is_compressed_i, + .issue_ack_i, + .instr_o, + .illegal_instr_o, + .is_compressed_o, + .fetch_stall_o, + .is_last_macro_instr_o, + .is_double_rd_macro_instr_o + ); + + task automatic reset_dut; + begin + is_macro_instr_i = 1'b0; + illegal_instr_i = 1'b0; + is_compressed_i = 1'b1; + issue_ack_i = 1'b0; + instr_i = '0; + + rst_ni = 1'b0; + repeat (2) @(posedge clk_i); + + // Deassert reset away from the active clock edge. + @(negedge clk_i); + rst_ni = 1'b1; + #1; + + assert (dut.state_q == ST_IDLE) + else $fatal(1, "decoder did not reset to IDLE"); + end + endtask + + task automatic check_stalled_first_uop( + input logic [15:0] encoding, input logic [2:0] expected_next_state, input string test_name); + logic [31:0] first_uop; + + begin + reset_dut(); + + // Drive the macro between clock edges and explicitly hold the + // issue acknowledgement low. + instr_i = {16'h0000, encoding}; + is_macro_instr_i = 1'b1; + issue_ack_i = 1'b0; + + // Allow combinational decoder outputs to settle before sampling. + #1; + + assert (!illegal_instr_o) + else $fatal(1, "%s decoded as illegal", test_name); + + assert (dut.state_q == ST_IDLE) + else $fatal(1, "%s did not start in IDLE", test_name); + + assert (fetch_stall_o) + else $fatal(1, "%s did not stall instruction fetch", test_name); + + first_uop = instr_o; + + // Cross exactly one active clock edge with issue_ack_i low. + @(posedge clk_i); + @(negedge clk_i); + #1; + + assert (dut.state_q == ST_IDLE) + else $fatal(1, "%s left IDLE without issue_ack_i (state=%0d)", test_name, dut.state_q); + + assert (instr_o === first_uop) + else $fatal(1, "%s changed the first micro-op while issue_ack_i was low", test_name); + + // Acknowledge the first micro-op well before the next positive edge. + issue_ack_i = 1'b1; + #1; + + // Cross exactly one active edge and sample before another active edge. + @(posedge clk_i); + @(negedge clk_i); + #1; + + assert (dut.state_q == expected_next_state) + else + $fatal( + 1, + "%s did not advance after issue_ack_i (state=%0d expected=%0d)", + test_name, + dut.state_q, + expected_next_state + ); + + $display("PASS: %s", test_name); + end + endtask + + initial begin + clk_i = 1'b0; + rst_ni = 1'b0; + instr_i = '0; + is_macro_instr_i = 1'b0; + illegal_instr_i = 1'b0; + is_compressed_i = 1'b1; + issue_ack_i = 1'b0; + + // Encodings generated with GNU binutils Zcmp support. + // + // Each of these instructions has a special transition directly + // from IDLE which must occur only after issue_ack_i is asserted. + + check_stalled_first_uop(16'hacaa, ST_MOVE, "cm.mvsa01"); + + check_stalled_first_uop(16'hacea, ST_MOVE, "cm.mva01s"); + + check_stalled_first_uop(16'hb842, ST_PUSH_ADDI, "cm.push {ra}, -16"); + + check_stalled_first_uop(16'hba42, ST_PUSH_ADDI, "cm.pop {ra}, 16"); + + check_stalled_first_uop(16'hbe42, ST_PUSH_ADDI, "cm.popret {ra}, 16"); + + check_stalled_first_uop(16'hbc42, ST_POPRETZ_1, "cm.popretz {ra}, 16"); + + check_stalled_first_uop(16'hb8f2, ST_PUSH_POP_INSTR_2, "cm.push {ra, s0-s11}, -64"); + + check_stalled_first_uop(16'hbaf2, ST_PUSH_POP_INSTR_2, "cm.pop {ra, s0-s11}, 64"); + + $display("PASS: macro decoder holds every affected first micro-op until issue_ack_i"); + + $finish; + end + +endmodule diff --git a/verif/tb/unit/Makefile b/verif/tb/unit/Makefile new file mode 100644 index 00000000000..93f5dd22cb5 --- /dev/null +++ b/verif/tb/unit/Makefile @@ -0,0 +1,48 @@ +VERILATOR ?= verilator +ROOT := ../../.. +BUILD_ROOT ?= .build +TESTS := $(patsubst %.sv,%,$(notdir $(wildcard *_test.sv))) + +.PHONY: all clean $(TESTS) + +RV64_CFG := $(ROOT)/core/include/cv64a6_imafdc_sv39_config_pkg.sv +RV32_CFG := $(ROOT)/core/include/cv32a6_imac_sv32_config_pkg.sv + +# Build and run test $(1) with the configuration package $(3), in the build directory $(1)_$(2) +define run_xlen_test + mkdir -p $(BUILD_ROOT) + $(VERILATOR) --binary --assert --timing -Wno-fatal -Wno-WIDTHTRUNC -Wno-WIDTHEXPAND -Wno-MULTIDRIVEN --top-module $(1) --Mdir $(BUILD_ROOT)/$(1)_$(2) $(ROOT)/core/include/config_pkg.sv $(3) $(ROOT)/core/include/build_config_pkg.sv $(ROOT)/core/include/riscv_pkg.sv $(ROOT)/core/include/ariane_pkg.sv $(ROOT)/core/include/triggers_pkg.sv $(ROOT)/core/trigger_module.sv $(1).sv + $(BUILD_ROOT)/$(1)_$(2)/V$(1) +endef + +all: $(TESTS) + +trigger_loadaddr_test: + mkdir -p $(BUILD_ROOT) + $(VERILATOR) --binary --assert --timing -Wno-fatal -Wno-WIDTHTRUNC -Wno-WIDTHEXPAND -Wno-MULTIDRIVEN --top-module $@ --Mdir $(BUILD_ROOT)/$@ $(ROOT)/core/include/config_pkg.sv $(ROOT)/core/include/cv64a6_imafdc_sv39_config_pkg.sv $(ROOT)/core/include/build_config_pkg.sv $(ROOT)/core/include/riscv_pkg.sv $(ROOT)/core/include/ariane_pkg.sv $(ROOT)/core/include/triggers_pkg.sv $(ROOT)/core/trigger_module.sv $@.sv + $(BUILD_ROOT)/$@/V$@ + +trigger_dmode_test: + mkdir -p $(BUILD_ROOT) + $(VERILATOR) --binary --assert --timing -Wno-fatal -Wno-WIDTHTRUNC -Wno-WIDTHEXPAND -Wno-MULTIDRIVEN --top-module $@ --Mdir $(BUILD_ROOT)/$@ $(ROOT)/core/include/config_pkg.sv $(ROOT)/core/include/cv64a6_imafdc_sv39_config_pkg.sv $(ROOT)/core/include/build_config_pkg.sv $(ROOT)/core/include/riscv_pkg.sv $(ROOT)/core/include/ariane_pkg.sv $(ROOT)/core/include/triggers_pkg.sv $(ROOT)/core/trigger_module.sv $@.sv + $(BUILD_ROOT)/$@/V$@ + +trigger_napot_test: + mkdir -p $(BUILD_ROOT) + $(VERILATOR) --binary --assert --timing --top-module $@ --Mdir $(BUILD_ROOT)/$@ $(ROOT)/core/include/triggers_pkg.sv $@.sv + $(BUILD_ROOT)/$@/V$@ + +trigger_tdata1_test: + $(call run_xlen_test,$@,rv64,$(RV64_CFG)) + $(call run_xlen_test,$@,rv32,$(RV32_CFG)) + +trigger_xtrigger_test: + $(call run_xlen_test,$@,rv64,$(RV64_CFG)) + $(call run_xlen_test,$@,rv32,$(RV32_CFG)) + +trigger_icount_test: + $(call run_xlen_test,$@,rv64,$(RV64_CFG)) + $(call run_xlen_test,$@,rv32,$(RV32_CFG)) + +clean: + rm -rf $(BUILD_ROOT) diff --git a/verif/tb/unit/trigger_dmode_test.sv b/verif/tb/unit/trigger_dmode_test.sv new file mode 100644 index 00000000000..9cc288f885d --- /dev/null +++ b/verif/tb/unit/trigger_dmode_test.sv @@ -0,0 +1,133 @@ +module trigger_dmode_test; + typedef struct packed { + logic valid; + logic [63:0] cause; + } exception_t; + + function automatic config_pkg::cva6_cfg_t test_config(); + config_pkg::cva6_cfg_t cfg; + cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg); + cfg.Sdtrig = 1; + cfg.SdtrigMcontrol6 = 1; + cfg.SdtrigNrTriggers = 2; + cfg.SdtrigSupportedActions = 2'b11; + cfg.SdtrigSupportedMatch = 10'b11_1111_1111; + return cfg; + endfunction + + localparam config_pkg::cva6_cfg_t TestCfg = test_config(); + + logic clk = 0; + logic rst_n = 0; + logic debug_mode; + logic [63:0] tdata1_i; + logic [63:0] tdata2_i; + logic tdata1_we; + logic tdata2_we; + logic [63:0] tdata1_o; + logic [63:0] tdata2_o; + + always #1 clk = !clk; + + trigger_module #( + .CVA6Cfg(TestCfg), + .exception_t(exception_t) + ) dut ( + .clk_i(clk), + .rst_ni(rst_n), + .commit_ack_i('0), + .ex_i('0), + .priv_lvl_i(riscv::PRIV_LVL_M), + .debug_mode_i(debug_mode), + .mret_i(1'b0), + .sret_i(1'b0), + .mstatus_mie_i(1'b1), + .mstatus_sie_i(1'b1), + .medeleg_breakpoint_i(1'b0), + .sdtrig_lsu_inputs_vaddr_i('0), + .sdtrig_lsu_inputs_data_i('0), + .sdtrig_lsu_inputs_fu_i(1'b0), + .sdtrig_lsu_inputs_op_i(ariane_pkg::ADD), + .sdtrig_lsu_inputs_valid_i(1'b0), + .sdtrig_load_data_i('0), + .sdtrig_load_valid_i(1'b0), + .scontext_i('0), + .tdata1_i(tdata1_i), + .tdata2_i(tdata2_i), + .tdata3_i('0), + .tselect_i('0), + .tselect_we(1'b0), + .tdata1_we(tdata1_we), + .tdata2_we(tdata2_we), + .tdata3_we(1'b0), + .tselect_o(), + .tdata1_o(tdata1_o), + .tdata2_o(tdata2_o), + .tdata3_o(), + .flush_o(), + .mepc_i('0), + .mcause_i('0), + .mtval_i('0), + .etrigger_context_saved_valid_o(), + .etrigger_context_mepc_o(), + .etrigger_context_mcause_o(), + .etrigger_context_mtval_o(), + .fetch_sdtrig_pc_i('0), + .fetch_sdtrig_instr_i('0), + .sdtrig_decoder_action_o(), + .sdtrig_load_stall_o(), + .sdtrig_load_cancel_o(), + .sdtrig_load_action_o(), + .sdtrig_store_stall_o(), + .sdtrig_store_action_o(), + .sdtrig_commit_std_exception_valid_o(), + .sdtrig_commit_icount_valid_o(), + .sdtrig_commit_action_o(), + .sdtrig_commit_icount_nr_instr_o() + ); + + task automatic write_tdata1(input logic [63:0] value); + tdata1_i = value; + tdata1_we = 1; + @(posedge clk); + #1; + tdata1_we = 0; + endtask + + task automatic write_tdata2(input logic [63:0] value); + tdata2_i = value; + tdata2_we = 1; + @(posedge clk); + #1; + tdata2_we = 0; + endtask + + initial begin + debug_mode = 0; + tdata1_i = 0; + tdata2_i = 0; + tdata1_we = 0; + tdata2_we = 0; + repeat (2) @(posedge clk); + rst_n = 1; + + write_tdata1(64'h6800_0000_0000_0004); + assert (!tdata1_o[59]); + assert (tdata1_o[2]); + + debug_mode = 1; + write_tdata1(64'h6800_0000_0000_0004); + assert (tdata1_o[59]); + write_tdata2(64'h55); + assert (tdata2_o == 64'h55); + + debug_mode = 0; + write_tdata1(64'h6000_0000_0000_0000); + assert (tdata1_o[59]); + assert (tdata1_o[2]); + write_tdata2(64'hAA); + assert (tdata2_o == 64'h55); + + $finish; + end +endmodule diff --git a/verif/tb/unit/trigger_icount_test.sv b/verif/tb/unit/trigger_icount_test.sv new file mode 100644 index 00000000000..157b2b6362f --- /dev/null +++ b/verif/tb/unit/trigger_icount_test.sv @@ -0,0 +1,279 @@ +module trigger_icount_test; + timeunit 1ns; timeprecision 1ps; + localparam int unsigned XLEN = cva6_config_pkg::CVA6ConfigXlen; + + typedef struct packed { + logic valid; + logic [XLEN-1:0] cause; + } exception_t; + + function automatic config_pkg::cva6_cfg_t test_config(); + config_pkg::cva6_cfg_t cfg; + cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg); + cfg.Sdtrig = 1; + cfg.SdtrigIcount = 1; + cfg.SdtrigNrTriggers = 4; + cfg.SdtrigSupportedActions = 2'b11; + return cfg; + endfunction + + localparam config_pkg::cva6_cfg_t TestCfg = test_config(); + localparam int unsigned NrW = $clog2(TestCfg.NrCommitPorts); + + logic clk = 0; + logic rst_n = 0; + logic debug_mode; + riscv::priv_lvl_t priv_lvl; + exception_t ex; + logic mret; + logic [TestCfg.NrCommitPorts-1:0] commit_ack; + logic [XLEN-1:0] tdata1_i; + logic tdata1_we; + logic [XLEN-1:0] tdata1_o; + logic icount_valid; + logic [NrW-1:0] icount_nr; + logic [XLEN-1:0] icount_action; + + always #1 clk = !clk; + + trigger_module #( + .CVA6Cfg(TestCfg), + .exception_t(exception_t) + ) dut ( + .clk_i(clk), + .rst_ni(rst_n), + .commit_ack_i(commit_ack), + .ex_i(ex), + .priv_lvl_i(priv_lvl), + .debug_mode_i(debug_mode), + .mret_i(mret), + .sret_i(1'b0), + .mstatus_mie_i(1'b1), + .mstatus_sie_i(1'b1), + .medeleg_breakpoint_i(1'b0), + .sdtrig_lsu_inputs_vaddr_i('0), + .sdtrig_lsu_inputs_data_i('0), + .sdtrig_lsu_inputs_fu_i(1'b0), + .sdtrig_lsu_inputs_op_i(ariane_pkg::ADD), + .sdtrig_lsu_inputs_valid_i(1'b0), + .sdtrig_load_data_i('0), + .sdtrig_load_valid_i(1'b0), + .scontext_i('0), + .tdata1_i(tdata1_i), + .tdata2_i('0), + .tdata3_i('0), + .tselect_i('0), + .tselect_we(1'b0), + .tdata1_we(tdata1_we), + .tdata2_we(1'b0), + .tdata3_we(1'b0), + .tselect_o(), + .tdata1_o(tdata1_o), + .tdata2_o(), + .tdata3_o(), + .flush_o(), + .mepc_i('0), + .mcause_i('0), + .mtval_i('0), + .etrigger_context_saved_valid_o(), + .etrigger_context_mepc_o(), + .etrigger_context_mcause_o(), + .etrigger_context_mtval_o(), + .fetch_sdtrig_pc_i('0), + .fetch_sdtrig_instr_i('0), + .sdtrig_decoder_action_o(), + .sdtrig_load_stall_o(), + .sdtrig_load_cancel_o(), + .sdtrig_load_action_o(), + .sdtrig_store_stall_o(), + .sdtrig_store_action_o(), + .sdtrig_commit_std_exception_valid_o(), + .sdtrig_commit_icount_valid_o(icount_valid), + .sdtrig_commit_action_o(icount_action), + .sdtrig_commit_icount_nr_instr_o(icount_nr) + ); + + localparam logic [XLEN-1:0] ICOUNT = XLEN'(3) << (XLEN - 4); + localparam logic [XLEN-1:0] ICOUNT_M = XLEN'(32'h200); + localparam logic [XLEN-1:0] ICOUNT_U = XLEN'(32'h40); + localparam logic [XLEN-1:0] PENDING = XLEN'(32'h100); + localparam logic [XLEN-1:0] HIT = XLEN'(32'h100_0000); + + function automatic logic [XLEN-1:0] count(input int c); + return XLEN'(c) << 10; + endfunction + + // The commit stage takes the trigger action in this cycle + function automatic logic fire_now(); + return icount_valid && icount_nr == '0; + endfunction + + task automatic write_tdata1(input logic [XLEN-1:0] value); + tdata1_i = value; + tdata1_we = 1; + @(posedge clk); + #0.1; + tdata1_we = 0; + // The write flushes the pipeline: nothing retires in the next cycle + @(posedge clk); + #0.1; + endtask + + // n instructions retire in one cycle + task automatic retire(input int n); + commit_ack = '0; + for (int p = 0; p < n; p++) commit_ack[p] = 1'b1; + @(posedge clk); + #0.1; + commit_ack = '0; + endtask + + // A trap with this cause is taken + task automatic take_trap(input logic [XLEN-1:0] cause); + ex.valid = 1; + ex.cause = cause; + @(posedge clk); + #0.1; + ex = '0; + endtask + + function automatic int read_count(); + return int'((tdata1_o >> 10) & XLEN'(14'h3fff)); + endfunction + + // The trigger action is taken: the commit stage raises the exception + task automatic take_fire(); + assert (fire_now()) else $fatal(1, "no fire to take"); + ex.valid = 1; + ex.cause = icount_action; + @(posedge clk); + #0.1; + ex = '0; + // The handler returns + mret = 1; + @(posedge clk); + #0.1; + mret = 0; + endtask + + task automatic check_no_fire(input int n, input string what); + repeat (n) begin + @(posedge clk); + #0.1; + assert (!fire_now()) else $fatal(1, "%s", what); + end + endtask + + initial begin + debug_mode = 0; + priv_lvl = riscv::PRIV_LVL_M; + ex = '0; + mret = 0; + commit_ack = '0; + tdata1_i = '0; + tdata1_we = 0; + repeat (2) @(posedge clk); + #0.1; + rst_n = 1; + + // count=0: the trigger does not fire + write_tdata1(ICOUNT | count(0) | ICOUNT_M); + repeat (4) retire(1); + check_no_fire(4, "count=0 fires"); + assert (!(tdata1_o & PENDING)) else $fatal(1, "count=0 sets pending"); + + // count=1: one instruction at a time retires. After one instruction, the + // trigger fires on the next instruction. The request stays until it is taken. + write_tdata1(ICOUNT | count(1) | ICOUNT_M); + @(posedge clk); + #0.1; + if (TestCfg.NrCommitPorts > 1) + assert (icount_valid && icount_nr == NrW'(1)) else $fatal(1, "count=1 does not limit commit"); + assert (!fire_now()) else $fatal(1, "count=1 fires before an instruction retires"); + retire(1); + @(posedge clk); + #0.1; + repeat (5) begin + assert (fire_now()) else $fatal(1, "pending trigger does not request the fire"); + assert (icount_action == riscv::BREAKPOINT) else $fatal(1, "fire action %0d", icount_action); + @(posedge clk); + #0.1; + end + take_fire(); + check_no_fire(4, "trigger fires twice"); + assert ((tdata1_o & (PENDING | HIT)) == HIT) else $fatal(1, "fire reads %h", tdata1_o); + + // pending is kept in a mode where the trigger is not enabled, and in Debug Mode. + // The trigger fires when the hart is back in an enabled mode. + priv_lvl = riscv::PRIV_LVL_U; + write_tdata1(ICOUNT | count(1) | ICOUNT_U); + retire(1); + priv_lvl = riscv::PRIV_LVL_M; + check_no_fire(4, "trigger fires in a mode that is not enabled"); + debug_mode = 1; + check_no_fire(4, "trigger fires in Debug Mode"); + debug_mode = 0; + assert (tdata1_o & PENDING) else $fatal(1, "pending is lost"); + priv_lvl = riscv::PRIV_LVL_U; + @(posedge clk); + #0.1; + take_fire(); + check_no_fire(4, "trigger fires twice"); + + $display("PASS: icount fires on the next instruction in an enabled mode (XLEN=%0d)", XLEN); + + // The instructions that retire in a mode where the trigger is not enabled, + // or in Debug Mode, do not decrement count + write_tdata1(ICOUNT | count(3) | ICOUNT_U); + priv_lvl = riscv::PRIV_LVL_M; + repeat (4) retire(1); + take_trap(XLEN'(11)); + debug_mode = 1; + repeat (2) retire(1); + debug_mode = 0; + assert (read_count() == 3) else $fatal(1, "count %0d after M-mode instructions", read_count()); + + // One U-mode instruction and the trap from U-mode match. The M-mode handler + // does not match. The trigger fires on the next U-mode instruction. + write_tdata1(ICOUNT | count(2) | ICOUNT_U); + priv_lvl = riscv::PRIV_LVL_U; + retire(1); + assert (read_count() == 1) else $fatal(1, "count %0d after one U-mode instruction", read_count()); + take_trap(XLEN'(8)); + priv_lvl = riscv::PRIV_LVL_M; + assert (tdata1_o & PENDING) else $fatal(1, "the trap from U-mode does not match"); + repeat (3) retire(1); + check_no_fire(2, "trigger fires in the M-mode handler"); + priv_lvl = riscv::PRIV_LVL_U; + @(posedge clk); + #0.1; + take_fire(); + + // A trap does not stop the count. The trap and the instructions of the + // handler match when the trigger is enabled in the mode of the handler. + priv_lvl = riscv::PRIV_LVL_M; + write_tdata1(ICOUNT | count(3) | ICOUNT_M); + take_trap(XLEN'(11)); + retire(1); + assert (read_count() == 1) else $fatal(1, "count %0d in the handler", read_count()); + retire(1); + @(posedge clk); + #0.1; + assert (fire_now()) else $fatal(1, "trigger does not fire in the handler"); + ex.valid = 1; + ex.cause = icount_action; + @(posedge clk); + #0.1; + ex = '0; + + // Two instructions that retire in one cycle are two matches + if (TestCfg.NrCommitPorts > 1) begin + write_tdata1(ICOUNT | count(4) | ICOUNT_M); + retire(2); + assert (read_count() == 2) else $fatal(1, "count %0d after two instructions", read_count()); + end + + $display("PASS: icount matches only in the enabled modes (XLEN=%0d)", XLEN); + $finish; + end +endmodule diff --git a/verif/tb/unit/trigger_loadaddr_test.sv b/verif/tb/unit/trigger_loadaddr_test.sv new file mode 100644 index 00000000000..7407f229c13 --- /dev/null +++ b/verif/tb/unit/trigger_loadaddr_test.sv @@ -0,0 +1,160 @@ +module trigger_loadaddr_test; + function automatic config_pkg::cva6_cfg_t test_config(); + config_pkg::cva6_cfg_t cfg; + cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg); + cfg.Sdtrig = 1; + cfg.SdtrigMcontrol6 = 1; + cfg.SdtrigMcontrol6LoadAddr = 1; + cfg.SdtrigNrTriggers = 2; + cfg.SdtrigSupportedActions = 2'b11; + cfg.SdtrigSupportedMatch = 10'b11_1111_1111; + return cfg; + endfunction + + localparam config_pkg::cva6_cfg_t TestCfg = test_config(); + + typedef struct packed { + logic valid; + logic [63:0] cause; + logic [63:0] tval; + logic [63:0] tval2; + logic [31:0] tinst; + logic gva; + logic timing; + } exception_t; + + logic clk = 0; + logic rst_n = 0; + logic [63:0] tdata1_i = 0; + logic [63:0] tdata2_i = 0; + logic [63:0] tselect_i = 0; + logic tdata1_we = 0; + logic tdata2_we = 0; + logic tselect_we = 0; + logic [63:0] tdata1_o; + logic lsu_valid = 0; + logic [63:0] lsu_vaddr = 0; + logic trigger_cancel; + logic [63:0] trigger_action; + + always #1 clk = !clk; + + trigger_module #( + .CVA6Cfg(TestCfg), + .exception_t(exception_t) + ) dut ( + .clk_i(clk), + .rst_ni(rst_n), + .commit_ack_i('0), + .ex_i('0), + .priv_lvl_i(riscv::PRIV_LVL_M), + .debug_mode_i(1'b0), + .mret_i(1'b0), + .sret_i(1'b0), + .mstatus_mie_i(1'b1), + .mstatus_sie_i(1'b1), + .medeleg_breakpoint_i(1'b0), + .sdtrig_lsu_inputs_vaddr_i(lsu_vaddr), + .sdtrig_lsu_inputs_data_i('0), + .sdtrig_lsu_inputs_fu_i(1'b0), + .sdtrig_lsu_inputs_op_i(ariane_pkg::ADD), + .sdtrig_lsu_inputs_valid_i(lsu_valid), + .sdtrig_load_data_i('0), + .sdtrig_load_valid_i(1'b0), + .scontext_i('0), + .tdata1_i(tdata1_i), + .tdata2_i(tdata2_i), + .tdata3_i('0), + .tselect_i(tselect_i), + .tselect_we(tselect_we), + .tdata1_we(tdata1_we), + .tdata2_we(tdata2_we), + .tdata3_we(1'b0), + .tselect_o(), + .tdata1_o(tdata1_o), + .tdata2_o(), + .tdata3_o(), + .flush_o(), + .mepc_i('0), + .mcause_i('0), + .mtval_i('0), + .etrigger_context_saved_valid_o(), + .etrigger_context_mepc_o(), + .etrigger_context_mcause_o(), + .etrigger_context_mtval_o(), + .fetch_sdtrig_pc_i('0), + .fetch_sdtrig_instr_i('0), + .sdtrig_decoder_action_o(), + .sdtrig_load_stall_o(), + .sdtrig_load_cancel_o(trigger_cancel), + .sdtrig_load_action_o(trigger_action), + .sdtrig_store_stall_o(), + .sdtrig_store_action_o(), + .sdtrig_commit_std_exception_valid_o(), + .sdtrig_commit_icount_valid_o(), + .sdtrig_commit_action_o(), + .sdtrig_commit_icount_nr_instr_o() + ); + + task automatic write_tdata1(input logic [63:0] value); + tdata1_i = value; + tdata1_we = 1; + @(posedge clk); + #1; + tdata1_we = 0; + endtask + + task automatic write_tselect(input logic [63:0] value); + tselect_i = value; + tselect_we = 1; + @(posedge clk); + #1; + tselect_we = 0; + endtask + + task automatic write_tdata2(input logic [63:0] value); + tdata2_i = value; + tdata2_we = 1; + @(posedge clk); + #1; + tdata2_we = 0; + endtask + + initial begin + repeat (2) @(posedge clk); + rst_n = 1; + + write_tselect(0); + write_tdata2(64'h1234); + write_tdata1(64'h6000_0000_0000_0041); + write_tselect(1); + write_tdata2(64'h5678); + write_tdata1(64'h6000_0000_0000_1041); + + lsu_vaddr = 64'h1234; + lsu_valid = 1; + @(posedge clk); + #1; + + assert (trigger_cancel) + else $fatal(1, "LoadAddr match did not produce cancel"); + assert (trigger_action == riscv::BREAKPOINT) + else $fatal(1, "cancel used an unrelated trigger action"); + + lsu_valid = 0; + @(posedge clk); + #1; + assert (!trigger_cancel) + else $fatal(1, "cancel pulse did not clear"); + + write_tselect(0); + assert (tdata1_o[22]) + else $fatal(1, "matching trigger did not record hit0"); + write_tselect(1); + assert (!tdata1_o[22]) + else $fatal(1, "unmatched trigger recorded hit0"); + + $display("PASS: LoadAddr cancel retains its trigger"); + $finish; + end +endmodule diff --git a/verif/tb/unit/trigger_napot_test.sv b/verif/tb/unit/trigger_napot_test.sv new file mode 100644 index 00000000000..f80c2d74f2c --- /dev/null +++ b/verif/tb/unit/trigger_napot_test.sv @@ -0,0 +1,12 @@ +module trigger_napot_test; + import triggers_pkg::*; + + initial begin + assert (napot_match32(32'h0000_0017, 32'h0000_0010)); + assert (napot_match32(32'h0000_0017, 32'h0000_001f)); + assert (!napot_match32(32'h0000_0017, 32'h0000_0020)); + assert (napot_match64(64'h0000_0000_8000_1007, 64'h0000_0000_8000_100f)); + assert (!napot_match64(64'h0000_0000_8000_1007, 64'h0000_0000_8000_1010)); + $finish; + end +endmodule diff --git a/verif/tb/unit/trigger_tdata1_test.sv b/verif/tb/unit/trigger_tdata1_test.sv new file mode 100644 index 00000000000..d015f8d1d93 --- /dev/null +++ b/verif/tb/unit/trigger_tdata1_test.sv @@ -0,0 +1,245 @@ +module trigger_tdata1_test; + timeunit 1ns; timeprecision 1ps; + localparam int unsigned XLEN = cva6_config_pkg::CVA6ConfigXlen; + + typedef struct packed { + logic valid; + logic [XLEN-1:0] cause; + } exception_t; + + function automatic config_pkg::cva6_cfg_t test_config(); + config_pkg::cva6_cfg_t cfg; + cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg); + cfg.Sdtrig = 1; + cfg.SdtrigMcontrol6 = 1; + cfg.SdtrigMcontrol6ExecAddr = 1; + cfg.SdtrigIcount = 1; + cfg.SdtrigEtrigger = 1; + cfg.SdtrigItrigger = 1; + cfg.SdtrigNrTriggers = 4; + cfg.SdtrigSupportedActions = 2'b11; + cfg.SdtrigSupportedMatch = 10'b11_1111_1111; + return cfg; + endfunction + + localparam config_pkg::cva6_cfg_t TestCfg = test_config(); + + logic clk = 0; + logic rst_n = 0; + logic debug_mode; + logic [XLEN-1:0] tdata1_i, tdata2_i, tselect_i; + logic tdata1_we, tdata2_we, tselect_we; + logic [XLEN-1:0] tdata1_o; + logic flush; + logic [TestCfg.NrIssuePorts-1:0][TestCfg.VLEN-1:0] fetch_pc; + logic [XLEN-1:0] decoder_action[TestCfg.NrIssuePorts]; + + always #1 clk = !clk; + + trigger_module #( + .CVA6Cfg(TestCfg), + .exception_t(exception_t) + ) dut ( + .clk_i(clk), + .rst_ni(rst_n), + .commit_ack_i('0), + .ex_i('0), + .priv_lvl_i(riscv::PRIV_LVL_M), + .debug_mode_i(debug_mode), + .mret_i(1'b0), + .sret_i(1'b0), + .mstatus_mie_i(1'b1), + .mstatus_sie_i(1'b1), + .medeleg_breakpoint_i(1'b0), + .sdtrig_lsu_inputs_vaddr_i('0), + .sdtrig_lsu_inputs_data_i('0), + .sdtrig_lsu_inputs_fu_i(1'b0), + .sdtrig_lsu_inputs_op_i(ariane_pkg::ADD), + .sdtrig_lsu_inputs_valid_i(1'b0), + .sdtrig_load_data_i('0), + .sdtrig_load_valid_i(1'b0), + .scontext_i('0), + .tdata1_i(tdata1_i), + .tdata2_i(tdata2_i), + .tdata3_i('0), + .tselect_i(tselect_i), + .tselect_we(tselect_we), + .tdata1_we(tdata1_we), + .tdata2_we(tdata2_we), + .tdata3_we(1'b0), + .tselect_o(), + .tdata1_o(tdata1_o), + .tdata2_o(), + .tdata3_o(), + .flush_o(flush), + .mepc_i('0), + .mcause_i('0), + .mtval_i('0), + .etrigger_context_saved_valid_o(), + .etrigger_context_mepc_o(), + .etrigger_context_mcause_o(), + .etrigger_context_mtval_o(), + .fetch_sdtrig_pc_i(fetch_pc), + .fetch_sdtrig_instr_i('0), + .sdtrig_decoder_action_o(decoder_action), + .sdtrig_load_stall_o(), + .sdtrig_load_cancel_o(), + .sdtrig_load_action_o(), + .sdtrig_store_stall_o(), + .sdtrig_store_action_o(), + .sdtrig_commit_std_exception_valid_o(), + .sdtrig_commit_icount_valid_o(), + .sdtrig_commit_action_o(), + .sdtrig_commit_icount_nr_instr_o() + ); + + function automatic logic [XLEN-1:0] tdata1_type(input logic [3:0] t); + return XLEN'(t) << (XLEN - 4); + endfunction + + localparam logic [XLEN-1:0] DMODE = XLEN'(1) << (XLEN - 5); + localparam logic [XLEN-1:0] DISABLED = XLEN'(15) << (XLEN - 4); + + // Write tdata1. Return the value of flush_o in the write cycle. + task automatic write_tdata1(input logic [XLEN-1:0] value, output logic flushed); + tdata1_i = value; + tdata1_we = 1; + #0.5; + flushed = flush; + @(posedge clk); + #0.1; + tdata1_we = 0; + endtask + + task automatic write_tdata2(input logic [XLEN-1:0] value); + tdata2_i = value; + tdata2_we = 1; + @(posedge clk); + #0.1; + tdata2_we = 0; + endtask + + task automatic write_tselect(input logic [XLEN-1:0] value); + tselect_i = value; + tselect_we = 1; + @(posedge clk); + #0.1; + tselect_we = 0; + endtask + + logic flushed; + + initial begin + debug_mode = 0; + tdata1_i = '0; + tdata2_i = '0; + tselect_i = '0; + tdata1_we = 0; + tdata2_we = 0; + tselect_we = 0; + fetch_pc = '0; + repeat (2) @(posedge clk); + #0.1; + rst_n = 1; + + // After reset, every trigger is disabled (type 15), not "no trigger" (type 0) + for (int i = 0; i < 4; i++) begin + write_tselect(XLEN'(i)); + assert (tdata1_o == DISABLED) + else $fatal(1, "trigger %0d reads %h after reset", i, tdata1_o); + end + write_tselect('0); + + // An execute trigger on 0x80000000 matches the fetched PC + write_tdata2(XLEN'(64'h8000_0000)); + write_tdata1(tdata1_type(4'd6) | XLEN'(32'h44), flushed); + fetch_pc[0] = TestCfg.VLEN'(64'h8000_0000); + #0.5; + assert (decoder_action[0] == riscv::BREAKPOINT) + else $fatal(1, "execute trigger does not match"); + + // A write of 0 disables the trigger: type 15, no match, pipeline flush + write_tdata1('0, flushed); + assert (flushed) else $fatal(1, "a write of 0 does not flush"); + assert (tdata1_o == DISABLED) else $fatal(1, "a write of 0 reads %h", tdata1_o); + #0.5; + assert (decoder_action[0] == '0) else $fatal(1, "disabled trigger still matches"); + + // A write of type 15 reads back as type 15 + write_tdata1(tdata1_type(4'd6) | XLEN'(32'h44), flushed); + write_tdata1(DISABLED | XLEN'(32'h44), flushed); + assert (tdata1_o == DISABLED) else $fatal(1, "a write of type 15 reads %h", tdata1_o); + #0.5; + assert (decoder_action[0] == '0) else $fatal(1, "type 15 trigger matches"); + + // A write of a type that is not supported (2) disables the trigger + write_tdata1(tdata1_type(4'd2) | XLEN'(32'h44), flushed); + assert (tdata1_o == DISABLED) else $fatal(1, "a write of type 2 reads %h", tdata1_o); + + // A write of 0 from Debug Mode keeps dmode=0. A write of type 15 with + // dmode=1 from Debug Mode keeps dmode=1. + debug_mode = 1; + write_tdata1(DISABLED | DMODE, flushed); + assert (tdata1_o == (DISABLED | DMODE)) + else $fatal(1, "type 15 with dmode reads %h", tdata1_o); + // dmode=1 blocks the writes from M-mode + debug_mode = 0; + write_tdata1(tdata1_type(4'd6) | XLEN'(32'h44), flushed); + assert (tdata1_o == (DISABLED | DMODE)) else $fatal(1, "dmode=1 trigger written from M-mode"); + debug_mode = 1; + write_tdata1('0, flushed); + assert (tdata1_o == DISABLED) else $fatal(1, "a write of 0 from Debug Mode reads %h", tdata1_o); + debug_mode = 0; + + // A write from M-mode cannot set dmode. Thus action=1 becomes action=0. + // mcontrol6: action is bits 15:12. icount, etrigger, itrigger: bits 5:0. + write_tdata1(tdata1_type(4'd6) | DMODE | XLEN'(32'h1044), flushed); + assert (tdata1_o == (tdata1_type(4'd6) | XLEN'(32'h44))) + else $fatal(1, "mcontrol6 dmode=1 action=1 from M-mode reads %h", tdata1_o); + #0.5; + assert (decoder_action[0] == riscv::BREAKPOINT) + else $fatal(1, "legalized mcontrol6 does not give a breakpoint"); + write_tdata1(tdata1_type(4'd6) | XLEN'(32'h1044), flushed); + assert (tdata1_o == (tdata1_type(4'd6) | XLEN'(32'h44))) + else $fatal(1, "mcontrol6 dmode=0 action=1 reads %h", tdata1_o); + write_tdata1(tdata1_type(4'd3) | DMODE | XLEN'(32'h1641), flushed); + assert (tdata1_o == (tdata1_type(4'd3) | XLEN'(32'h1640))) + else $fatal(1, "icount action=1 from M-mode reads %h", tdata1_o); + write_tdata1(tdata1_type(4'd5) | XLEN'(32'h241), flushed); + assert (tdata1_o == (tdata1_type(4'd5) | XLEN'(32'h240))) + else $fatal(1, "etrigger action=1 from M-mode reads %h", tdata1_o); + write_tdata1(tdata1_type(4'd4) | XLEN'(32'h241), flushed); + assert (tdata1_o == (tdata1_type(4'd4) | XLEN'(32'h240))) + else $fatal(1, "itrigger action=1 from M-mode reads %h", tdata1_o); + // An action that is not supported (5) becomes 0 + write_tdata1(tdata1_type(4'd5) | XLEN'(32'h245), flushed); + assert (tdata1_o == (tdata1_type(4'd5) | XLEN'(32'h240))) + else $fatal(1, "etrigger action=5 reads %h", tdata1_o); + + // From Debug Mode, dmode=1 keeps action=1. dmode=0 gives action=0. + debug_mode = 1; + write_tdata1(tdata1_type(4'd6) | XLEN'(32'h1044), flushed); + assert (tdata1_o == (tdata1_type(4'd6) | XLEN'(32'h44))) + else $fatal(1, "mcontrol6 dmode=0 action=1 from Debug Mode reads %h", tdata1_o); + write_tdata1(tdata1_type(4'd3) | DMODE | XLEN'(32'h1641), flushed); + assert (tdata1_o == (tdata1_type(4'd3) | DMODE | XLEN'(32'h1641))) + else $fatal(1, "icount dmode=1 action=1 from Debug Mode reads %h", tdata1_o); + write_tdata1(tdata1_type(4'd6) | DMODE | XLEN'(32'h1044), flushed); + assert (tdata1_o == (tdata1_type(4'd6) | DMODE | XLEN'(32'h1044))) + else $fatal(1, "mcontrol6 dmode=1 action=1 from Debug Mode reads %h", tdata1_o); + // A trigger with action=1 requests Debug Mode with the trigger cause, + // not with the cause of a halt request. + debug_mode = 0; + #0.5; + assert (decoder_action[0] == riscv::DEBUG_TRIGGER) + else $fatal(1, "action=1 trigger gives cause %0d", decoder_action[0]); + debug_mode = 1; + write_tdata1('0, flushed); + debug_mode = 0; + + $display("PASS: tdata1 write of 0 disables the trigger (XLEN=%0d)", XLEN); + $display("PASS: tdata1 never holds dmode=0 with action=1 (XLEN=%0d)", XLEN); + $display("PASS: an action=1 trigger requests Debug Mode with the trigger cause (XLEN=%0d)", XLEN); + $finish; + end +endmodule diff --git a/verif/tb/unit/trigger_xtrigger_test.sv b/verif/tb/unit/trigger_xtrigger_test.sv new file mode 100644 index 00000000000..38d8ee8fe49 --- /dev/null +++ b/verif/tb/unit/trigger_xtrigger_test.sv @@ -0,0 +1,287 @@ +module trigger_xtrigger_test; + timeunit 1ns; timeprecision 1ps; + localparam int unsigned XLEN = cva6_config_pkg::CVA6ConfigXlen; + + typedef struct packed { + logic valid; + logic [XLEN-1:0] cause; + } exception_t; + + function automatic config_pkg::cva6_cfg_t test_config(); + config_pkg::cva6_cfg_t cfg; + cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg); + cfg.Sdtrig = 1; + cfg.SdtrigEtrigger = 1; + cfg.SdtrigItrigger = 1; + cfg.SdtrigNrTriggers = 4; + cfg.SdtrigSupportedActions = 2'b11; + return cfg; + endfunction + + localparam config_pkg::cva6_cfg_t TestCfg = test_config(); + + logic clk = 0; + logic rst_n = 0; + logic debug_mode; + riscv::priv_lvl_t priv_lvl; + exception_t ex; + logic mret; + logic [TestCfg.NrCommitPorts-1:0] commit_ack; + logic [XLEN-1:0] tdata1_i, tdata2_i, tselect_i; + logic tdata1_we, tdata2_we, tselect_we; + logic [XLEN-1:0] tdata1_o; + logic fire; + logic [XLEN-1:0] fire_action; + + always #1 clk = !clk; + + trigger_module #( + .CVA6Cfg(TestCfg), + .exception_t(exception_t) + ) dut ( + .clk_i(clk), + .rst_ni(rst_n), + .commit_ack_i(commit_ack), + .ex_i(ex), + .priv_lvl_i(priv_lvl), + .debug_mode_i(debug_mode), + .mret_i(mret), + .sret_i(1'b0), + .mstatus_mie_i(1'b1), + .mstatus_sie_i(1'b1), + .medeleg_breakpoint_i(1'b0), + .sdtrig_lsu_inputs_vaddr_i('0), + .sdtrig_lsu_inputs_data_i('0), + .sdtrig_lsu_inputs_fu_i(1'b0), + .sdtrig_lsu_inputs_op_i(ariane_pkg::ADD), + .sdtrig_lsu_inputs_valid_i(1'b0), + .sdtrig_load_data_i('0), + .sdtrig_load_valid_i(1'b0), + .scontext_i('0), + .tdata1_i(tdata1_i), + .tdata2_i(tdata2_i), + .tdata3_i('0), + .tselect_i(tselect_i), + .tselect_we(tselect_we), + .tdata1_we(tdata1_we), + .tdata2_we(tdata2_we), + .tdata3_we(1'b0), + .tselect_o(), + .tdata1_o(tdata1_o), + .tdata2_o(), + .tdata3_o(), + .flush_o(), + .mepc_i('0), + .mcause_i('0), + .mtval_i('0), + .etrigger_context_saved_valid_o(), + .etrigger_context_mepc_o(), + .etrigger_context_mcause_o(), + .etrigger_context_mtval_o(), + .fetch_sdtrig_pc_i('0), + .fetch_sdtrig_instr_i('0), + .sdtrig_decoder_action_o(), + .sdtrig_load_stall_o(), + .sdtrig_load_cancel_o(), + .sdtrig_load_action_o(), + .sdtrig_store_stall_o(), + .sdtrig_store_action_o(), + .sdtrig_commit_std_exception_valid_o(fire), + .sdtrig_commit_icount_valid_o(), + .sdtrig_commit_action_o(fire_action), + .sdtrig_commit_icount_nr_instr_o() + ); + + function automatic logic [XLEN-1:0] tdata1_type(input logic [3:0] t); + return XLEN'(t) << (XLEN - 4); + endfunction + + localparam logic [XLEN-1:0] DMODE = XLEN'(1) << (XLEN - 5); + localparam logic [XLEN-1:0] INTERRUPT = XLEN'(1) << (XLEN - 1); + localparam logic [XLEN-1:0] XTRIG_M = XLEN'(32'h200); + + task automatic write_csr(input int csr, input logic [XLEN-1:0] value); + case (csr) + 0: begin tselect_i = value; tselect_we = 1; end + 1: begin tdata1_i = value; tdata1_we = 1; end + 2: begin tdata2_i = value; tdata2_we = 1; end + default: ; + endcase + @(posedge clk); + #0.1; + tselect_we = 0; + tdata1_we = 0; + tdata2_we = 0; + endtask + + // A trap with this cause is taken in one cycle + task automatic take_trap(input logic [XLEN-1:0] cause); + ex.valid = 1; + ex.cause = cause; + @(posedge clk); + #0.1; + ex = '0; + endtask + + // The trigger module does not request a fire in the next n cycles + task automatic check_no_fire(input int n, input string what); + repeat (n) begin + @(posedge clk); + #0.1; + assert (!fire) else $fatal(1, "%s", what); + end + endtask + + // The trigger module requests a fire with this action in the next n cycles + task automatic check_fire(input int n, input logic [XLEN-1:0] action, input string what); + logic seen = 0; + repeat (n) begin + @(posedge clk); + #0.1; + if (fire) begin + seen = 1; + assert (fire_action == action) + else $fatal(1, "%s: action %0d, expected %0d", what, fire_action, action); + end + end + assert (seen) else $fatal(1, "%s: no fire", what); + endtask + + // The breakpoint (or the Debug Mode entry) of the fire is taken + task automatic take_fire(input logic [XLEN-1:0] cause); + wait (fire); + take_trap(cause); + check_no_fire(4, "fire is not cleared"); + endtask + + initial begin + debug_mode = 0; + priv_lvl = riscv::PRIV_LVL_M; + ex = '0; + mret = 0; + commit_ack = '0; + tdata1_i = '0; + tdata2_i = '0; + tselect_i = '0; + tdata1_we = 0; + tdata2_we = 0; + tselect_we = 0; + repeat (2) @(posedge clk); + #0.1; + rst_n = 1; + + // etrigger on exception code 0. No trap: ex_i.cause is 0, ex_i.valid is 0. + write_csr(0, 0); + write_csr(2, XLEN'(1)); + write_csr(1, tdata1_type(4'd5) | XTRIG_M); + check_no_fire(8, "etrigger fires with no trap"); + + // etrigger on exception code 7. An interrupt with code 7 does not match. + write_csr(2, XLEN'(1) << 7); + take_trap(INTERRUPT | XLEN'(7)); + check_no_fire(8, "etrigger fires on an interrupt"); + + // A Debug Mode entry is not a trap + write_csr(2, XLEN'(1) << 24); + take_trap(riscv::DEBUG_REQUEST); + check_no_fire(8, "etrigger fires on a halt request"); + + // An exception with code 7 matches. The trigger fires with a breakpoint. + write_csr(2, XLEN'(1) << 7); + take_trap(XLEN'(7)); + check_fire(3, riscv::BREAKPOINT, "etrigger on exception 7"); + take_fire(riscv::BREAKPOINT); + mret = 1; + @(posedge clk); + #0.1; + mret = 0; + + // An exception from S-mode matches a trigger with s=1 + priv_lvl = riscv::PRIV_LVL_S; + write_csr(1, tdata1_type(4'd5) | XLEN'(32'h80)); + take_trap(XLEN'(7)); + check_fire(3, riscv::BREAKPOINT, "etrigger on an exception from S-mode"); + take_fire(riscv::BREAKPOINT); + priv_lvl = riscv::PRIV_LVL_M; + mret = 1; + @(posedge clk); + #0.1; + mret = 0; + + // An exception with code 2 is not selected + write_csr(1, tdata1_type(4'd5) | XTRIG_M); + take_trap(XLEN'(2)); + check_no_fire(8, "etrigger fires on a code that is not selected"); + + // An exception from a mode that is not enabled does not match + priv_lvl = riscv::PRIV_LVL_U; + take_trap(XLEN'(7)); + check_no_fire(8, "etrigger fires on a trap from a mode that is not enabled"); + priv_lvl = riscv::PRIV_LVL_M; + + // Trigger 0 is an etrigger on code 7, trigger 1 an etrigger on code 2. + // Exception 7 fires trigger 0 only. Trigger 1 does not record a hit. + write_csr(1, tdata1_type(4'd5) | XTRIG_M); + write_csr(2, XLEN'(1) << 7); + write_csr(0, 1); + write_csr(1, tdata1_type(4'd5) | XTRIG_M); + write_csr(2, XLEN'(1) << 2); + take_trap(XLEN'(7)); + check_fire(3, riscv::BREAKPOINT, "etrigger 0 on exception 7"); + take_fire(riscv::BREAKPOINT); + assert (tdata1_o[XLEN-6] == 1'b0) else $fatal(1, "etrigger 1 fired on exception 7"); + write_csr(0, 0); + assert (tdata1_o[XLEN-6] == 1'b1) else $fatal(1, "etrigger 0 did not record a hit"); + mret = 1; + @(posedge clk); + #0.1; + mret = 0; + + $display("PASS: etrigger fires only on a selected exception (XLEN=%0d)", XLEN); + + // itrigger on interrupt 7: it fires after the trap, before the first + // instruction of the handler. It does not wait for an mret. + write_csr(1, tdata1_type(4'd4) | XTRIG_M); + write_csr(2, XLEN'(1) << 7); + take_trap(INTERRUPT | XLEN'(7)); + check_fire(3, riscv::BREAKPOINT, "itrigger on interrupt 7"); + take_fire(riscv::BREAKPOINT); + mret = 1; + @(posedge clk); + #0.1; + mret = 0; + + // An exception with code 7 does not match an itrigger + write_csr(1, tdata1_type(4'd4) | XTRIG_M); + take_trap(XLEN'(7)); + check_no_fire(8, "itrigger fires on an exception"); + + // An interrupt taken from S-mode matches an itrigger with s=1 + priv_lvl = riscv::PRIV_LVL_S; + write_csr(1, tdata1_type(4'd4) | XLEN'(32'h80)); + take_trap(INTERRUPT | XLEN'(7)); + check_fire(3, riscv::BREAKPOINT, "itrigger on an interrupt from S-mode"); + take_fire(riscv::BREAKPOINT); + priv_lvl = riscv::PRIV_LVL_M; + mret = 1; + @(posedge clk); + #0.1; + mret = 0; + + // Trigger 0 is an itrigger, trigger 1 is an etrigger, both on code 7. + // An interrupt fires only the itrigger. The etrigger does not record a hit. + write_csr(1, tdata1_type(4'd4) | XTRIG_M); + write_csr(0, 1); + write_csr(1, tdata1_type(4'd5) | XTRIG_M); + write_csr(2, XLEN'(1) << 7); + take_trap(INTERRUPT | XLEN'(7)); + check_fire(3, riscv::BREAKPOINT, "itrigger with an etrigger on the same code"); + take_fire(riscv::BREAKPOINT); + assert (tdata1_o[XLEN-6] == 1'b0) else $fatal(1, "etrigger fired on an interrupt"); + write_csr(0, 0); + assert (tdata1_o[XLEN-6] == 1'b1) else $fatal(1, "itrigger did not record a hit"); + + $display("PASS: itrigger fires before the first instruction of the handler (XLEN=%0d)", XLEN); + $finish; + end +endmodule diff --git a/verif/tb/uvmt/cva6_tb_wrapper.sv b/verif/tb/uvmt/cva6_tb_wrapper.sv index 708267b960e..09b3b8c034e 100644 --- a/verif/tb/uvmt/cva6_tb_wrapper.sv +++ b/verif/tb/uvmt/cva6_tb_wrapper.sv @@ -34,10 +34,13 @@ import uvm_pkg::*; `ifndef DPI_FESVR_SPIKE_UTILS `define DPI_FESVR_SPIKE_UTILS +`ifndef READ_ELF_T +`define READ_ELF_T import "DPI-C" function void read_elf(input string filename); import "DPI-C" function byte read_symbol(input string symbol_name, inout longint unsigned address); import "DPI-C" function byte get_section(output longint address, output longint len); -import "DPI-C" context function read_section_sv(input longint address, inout byte buffer[]); +import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]); +`endif `endif module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( @@ -48,6 +51,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( parameter type rvfi_probes_instr_t = logic, parameter type rvfi_probes_csr_t = logic, parameter type rvfi_probes_t = logic, + parameter type rvfi_to_iti_t = logic, // CVXIF Types localparam type readregflags_t = `READREGFLAGS_T(CVA6Cfg), localparam type writeregflags_t = `WRITEREGFLAGS_T(CVA6Cfg), @@ -55,12 +59,12 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( localparam type hartid_t = `HARTID_T(CVA6Cfg), localparam type x_compressed_req_t = `X_COMPRESSED_REQ_T(CVA6Cfg, hartid_t), localparam type x_compressed_resp_t = `X_COMPRESSED_RESP_T(CVA6Cfg), - localparam type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartit_t, id_t), + localparam type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartid_t, id_t), localparam type x_issue_resp_t = `X_ISSUE_RESP_T(CVA6Cfg, writeregflags_t, readregflags_t), localparam type x_register_t = `X_REGISTER_T(CVA6Cfg, hartid_t, id_t, readregflags_t), localparam type x_commit_t = `X_COMMIT_T(CVA6Cfg, hartid_t, id_t), localparam type x_result_t = `X_RESULT_T(CVA6Cfg, hartid_t, id_t, writeregflags_t), - localparam type cvxif_req_t = `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t), + localparam type cvxif_req_t = `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_t, x_commit_t), localparam type cvxif_resp_t = `CVXIF_RESP_T(CVA6Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t), // parameter int unsigned AXI_USER_EN = 0, @@ -88,6 +92,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr; rvfi_probes_t rvfi_probes; + rvfi_to_iti_t rvfi_to_iti; rvfi_csr_t rvfi_csr; assign rvfi_o = rvfi_instr; assign rvfi_csr_o = rvfi_csr; @@ -126,12 +131,14 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( .rvfi_csr_t(rvfi_csr_t), .rvfi_probes_instr_t(rvfi_probes_instr_t), .rvfi_probes_csr_t(rvfi_probes_csr_t), - .rvfi_probes_t(rvfi_probes_t) + .rvfi_probes_t(rvfi_probes_t), + .rvfi_to_iti_t(rvfi_to_iti_t) ) i_cva6_rvfi ( .clk_i (clk_i), .rst_ni (rst_ni), .rvfi_probes_i(rvfi_probes), .rvfi_instr_o(rvfi_instr), + .rvfi_to_iti_o (rvfi_to_iti), .rvfi_csr_o(rvfi_csr) ); diff --git a/verif/tb/uvmt/uvmt_axi_assert.sv b/verif/tb/uvmt/uvmt_axi_assert.sv index 06097c2e069..319d6e4eaad 100644 --- a/verif/tb/uvmt/uvmt_axi_assert.sv +++ b/verif/tb/uvmt/uvmt_axi_assert.sv @@ -18,7 +18,7 @@ module uvmt_axi_assert#(int HPDCache=2) uvma_axi_ar_assert axi_ar_assert(.axi_assert(axi_assert_if)); - uvma_axi_w_assert axi_w_assert(.axi_assert(axi_assert_if)); + uvma_axi_w_assert #(.CHECK_STROBE(1)) axi_w_assert(.axi_assert(axi_assert_if)); uvma_axi_r_assert axi_r_assert(.axi_assert(axi_assert_if)); diff --git a/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv index e82e80652aa..5a9f023e269 100644 --- a/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv +++ b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv @@ -22,6 +22,7 @@ module uvmt_cva6_dut_wrap # ( parameter type rvfi_probes_instr_t = logic, parameter type rvfi_probes_csr_t = logic, parameter type rvfi_probes_t = logic, + parameter type rvfi_to_iti_t = logic, // parameter int unsigned AXI_USER_EN = 0, parameter int unsigned NUM_WORDS = 2**25 @@ -52,6 +53,7 @@ module uvmt_cva6_dut_wrap # ( .rvfi_probes_instr_t(rvfi_probes_instr_t), .rvfi_probes_csr_t ( rvfi_probes_csr_t ), .rvfi_probes_t ( rvfi_probes_t ), + .rvfi_to_iti_t ( rvfi_to_iti_t ), // .AXI_USER_EN (AXI_USER_EN), .NUM_WORDS (NUM_WORDS) diff --git a/verif/tb/uvmt/uvmt_cva6_pkg.sv b/verif/tb/uvmt/uvmt_cva6_pkg.sv index 9641dfc41c4..1a2c14caa8c 100644 --- a/verif/tb/uvmt/uvmt_cva6_pkg.sv +++ b/verif/tb/uvmt/uvmt_cva6_pkg.sv @@ -59,9 +59,9 @@ package uvmt_cva6_pkg; // Base test case `include "uvmt_cva6_test_cfg.sv" `include "uvmt_cva6_base_test.sv" // all testcases should extend from this testcase - //`include "uvmt_cva6_smoke_test.sv" // smoke test has multile XMRs that are illegal according to the LRM + //`include "uvmt_cva6_smoke_test.sv" // smoke test has multiple XMRs that are illegal according to the LRM - // Compilance tests + // Compliance tests `include "uvmt_cva6_firmware_test.sv" endpackage : uvmt_cva6_pkg diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv index 0bde61c74a3..ce05745c9fd 100644 --- a/verif/tb/uvmt/uvmt_cva6_tb.sv +++ b/verif/tb/uvmt/uvmt_cva6_tb.sv @@ -41,6 +41,7 @@ module uvmt_cva6_tb; localparam type rvfi_instr_t = `RVFI_INSTR_T(CVA6Cfg); localparam type rvfi_csr_elmt_t = `RVFI_CSR_ELMT_T(CVA6Cfg); localparam type rvfi_csr_t = `RVFI_CSR_T(CVA6Cfg, rvfi_csr_elmt_t); + localparam type rvfi_to_iti_t = `RVFI_TO_ITI_T(CVA6Cfg); // RVFI PROBES localparam type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg); @@ -120,6 +121,7 @@ module uvmt_cva6_tb; .rvfi_probes_instr_t(rvfi_probes_instr_t ), .rvfi_probes_csr_t ( rvfi_probes_csr_t ), .rvfi_probes_t ( rvfi_probes_t ), + .rvfi_to_iti_t ( rvfi_to_iti_t ), // .AXI_USER_EN (CVA6Cfg.AXI_USER_EN), .NUM_WORDS (NUM_WORDS) diff --git a/verif/tests/custom/CSR/csr_access_tests/readme.md b/verif/tests/custom/CSR/csr_access_tests/readme.md index e3b22ca98f0..f63526c5f1a 100644 --- a/verif/tests/custom/CSR/csr_access_tests/readme.md +++ b/verif/tests/custom/CSR/csr_access_tests/readme.md @@ -2,8 +2,8 @@ Highlights: This directory includes test programs for the RISCV CVA6 CSR Access, which are divided into Machine read-write, Machine read-only, Supervisor read-write, and Machine Mode counter CSR tests. -1.Each CSR access has been verified in all priviliged modes(M,S and U). +1.Each CSR access has been verified in all privilege modes(M,S and U). -2.The behavior of counter CSRs has been verified in all priviliged modes (M,S and U). +2.The behavior of counter CSRs has been verified in all privilege modes (M,S and U). 3.Checked the behavior of the RISC-V Machine mode counter CSRs when it reaches to maximum value. diff --git a/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml b/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml index 0dac6a3bdef..9964660f295 100644 --- a/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml +++ b/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml @@ -72,7 +72,7 @@ lsb: 15 - field_name: FS description: > - use to reduce the cost of context save and restore by setting and tracking the current state + use to reduce the cost of context save and restore by setting and tracking the current state type: RW reset_val: 0 msb: 14 @@ -492,7 +492,7 @@ lsb: 1 - field_name: USIE description: > - enable U-mode software interrrupts + enable U-mode software interrupts type: R reset_val: 0 msb: 0 @@ -716,7 +716,7 @@ lsb: 1 - field_name: USIE description: > - enable U-mode software interrrupts + enable U-mode software interrupts type: R reset_val: 0 msb: 0 diff --git a/verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml b/verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml index c6d4cd7e96e..3e4a7806b78 100644 --- a/verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml +++ b/verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml @@ -51,7 +51,7 @@ lsb: 15 - field_name: FS description: > - Floationd point State + Floating point State type: RW reset_val: 0 msb: 14 @@ -79,7 +79,7 @@ lsb: 6 - field_name: SPIE description: > - The SPIE bit indicates whether supervisor interrupts were enabled prior to trappin into supervisor mode. + The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. type: RW reset_val: 0 msb: 5 @@ -248,7 +248,7 @@ - csr: CSR_SSCRATCH description: > - Scartch Register for supervisor trap handlers + Scratch Register for supervisor trap handlers address: 0x140 privilege_mode: S rv32: @@ -373,7 +373,7 @@ lsb: 1 - field_name: USIP description: > - A user-level software interrupt is triggered on the current hart by riting 1 to its user software interrupt-pending (USIP) bit + A user-level software interrupt is triggered on the current hart by writing 1 to its user software interrupt-pending (USIP) bit type: R reset_val: 0 msb: 0 diff --git a/verif/tests/custom/ITI/iti_asm.S b/verif/tests/custom/ITI/iti_asm.S new file mode 100644 index 00000000000..de4e8674f3c --- /dev/null +++ b/verif/tests/custom/ITI/iti_asm.S @@ -0,0 +1,35 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 20/03/2025 +// Contributors: +// Darshak Sheladiya, SYSGO GmbH +// Umberto Laghi, UNIBO + +.section .text +.align 1 +.align 4 +.global branch_test +.type branch_test, @function + + +branch_test: + li x12,10 + loop: + bne x13,x13, branch_test + bne x13,x13, branch_test + bne x13,x13, branch_test + bne x13,x13, branch_test + la x11, branch_test + lw x10, 0(x11) + bne x13,x13, branch_test + bne x13,x13, branch_test + bne x13,x13, branch_test + bne x13,x13, branch_test + bne x13,x13, branch_test + bne x13,x13, branch_test + addi x12,x12, -1 + bne x12, x0, loop + + + jalr x0,0(ra) diff --git a/verif/tests/custom/ITI/test_iti_asm.c b/verif/tests/custom/ITI/test_iti_asm.c new file mode 100644 index 00000000000..bbb506395ef --- /dev/null +++ b/verif/tests/custom/ITI/test_iti_asm.c @@ -0,0 +1,16 @@ +// Copyright (c) 2025 Thales DIS design services SAS +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// Author: Maxime Colson - Thales +// Date: 20/03/2025 +// Contributors: +// Darshak Sheladiya, SYSGO GmbH +// Umberto Laghi, UNIBO + +//This test will be improved by taking into account other scenarios + +void branch_test(); + +int main(int argc, char* arg[]) { + branch_test(); + return 0; +} diff --git a/verif/tests/custom/ITI/test_iti_asm.o b/verif/tests/custom/ITI/test_iti_asm.o new file mode 100755 index 00000000000..3aeb07aa9ae Binary files /dev/null and b/verif/tests/custom/ITI/test_iti_asm.o differ diff --git a/verif/tests/custom/Zcmp/cm_mva01s_equal_regs_test.S b/verif/tests/custom/Zcmp/cm_mva01s_equal_regs_test.S new file mode 100644 index 00000000000..ee076ccc5b1 --- /dev/null +++ b/verif/tests/custom/Zcmp/cm_mva01s_equal_regs_test.S @@ -0,0 +1,33 @@ +#include "riscv_test.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + li s1, 9 + .2byte 0xace6 # cm.mva01s s1, s1 + + bne a0, s1, failure + bne a1, s1, failure + + j success +failure: + li x1, 1 + slli x1, x1, 1 + addi x1, x1, 1 + sw x1, tohost, t5 + self_loop_2: j self_loop_2 + +success: + li x1, 0 + slli x1, x1, 1 + addi x1, x1, 1 + sw x1, tohost, t5 + self_loop: j self_loop + +RVTEST_CODE_END + +.data + +RVTEST_DATA_BEGIN + +RVTEST_DATA_END diff --git a/verif/tests/custom/Zcmp/cm_reserved_rlist_test.S b/verif/tests/custom/Zcmp/cm_reserved_rlist_test.S new file mode 100644 index 00000000000..b64a7546fef --- /dev/null +++ b/verif/tests/custom/Zcmp/cm_reserved_rlist_test.S @@ -0,0 +1,72 @@ +#include "riscv_test.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + # Count the number of expected illegal-instruction traps. + li s0, 0 + + # Zcmp reserves rlist values 0 through 3 for the + # cm.push/cm.pop/cm.popretz/cm.popret instruction families. + # + # rlist occupies bits [7:4]. + # spimm is kept at zero because this test targets rlist legality. + + # cm.push, rlist = 0..3 + .2byte 0xb802 + .2byte 0xb812 + .2byte 0xb822 + .2byte 0xb832 + + # cm.pop, rlist = 0..3 + .2byte 0xba02 + .2byte 0xba12 + .2byte 0xba22 + .2byte 0xba32 + + # cm.popretz, rlist = 0..3 + .2byte 0xbc02 + .2byte 0xbc12 + .2byte 0xbc22 + .2byte 0xbc32 + + # cm.popret, rlist = 0..3 + .2byte 0xbe02 + .2byte 0xbe12 + .2byte 0xbe22 + .2byte 0xbe32 + + # Every reserved instruction above must have trapped. + li t0, 16 + bne s0, t0, failure + + RVTEST_PASS + +failure: + li TESTNUM, 1 + RVTEST_FAIL + +mtvec_handler: + # Only illegal-instruction exceptions are expected. + csrr t0, mcause + li t1, CAUSE_ILLEGAL_INSTRUCTION + bne t0, t1, failure + + # Record this expected trap. + addi s0, s0, 1 + + # Every injected instruction is a 16-bit compressed instruction. + # Advance mepc so execution continues at the following encoding. + csrr t0, mepc + addi t0, t0, 2 + csrw mepc, t0 + + mret + +RVTEST_CODE_END + +.data + +RVTEST_DATA_BEGIN + +RVTEST_DATA_END diff --git a/verif/tests/custom/common/syscalls.c b/verif/tests/custom/common/syscalls.c index e19e3cd5bc8..045f35c4d1b 100644 --- a/verif/tests/custom/common/syscalls.c +++ b/verif/tests/custom/common/syscalls.c @@ -15,6 +15,8 @@ extern volatile uint64_t tohost; extern volatile uint64_t fromhost; +register void *thread_pointer asm("tp"); + // tohost is 64 bits wide, irrespective of XLEN. The structure expected in Spike is: // - tohost[63:56] == device (syscall: 0) // - tohost[55:48] == command (syscall: 0) @@ -134,7 +136,6 @@ int __attribute__((weak)) main(int argc, char** argv) static void init_tls() { - register void* thread_pointer asm("tp"); extern char _tdata_begin, _tdata_end, _tbss_end; size_t tdata_size = &_tdata_end - &_tdata_begin; memcpy(thread_pointer, &_tdata_begin, tdata_size); diff --git a/verif/tests/custom/coremark/coremark_main.c b/verif/tests/custom/coremark/coremark_main.c index 5ae1331fa67..d2ba3dd6204 100644 --- a/verif/tests/custom/coremark/coremark_main.c +++ b/verif/tests/custom/coremark/coremark_main.c @@ -281,6 +281,7 @@ for (i = 0; i < MULTITHREAD; i++) divisor = 1; results[0].iterations *= 1 + 10 / divisor; } + iterate(&results[0]); /* perform actual benchmark */ start_time(); #if (MULTITHREAD > 1) diff --git a/verif/tests/custom/coremark/uart.h b/verif/tests/custom/coremark/uart.h index 6505c6bb0e5..03045ec20b9 100644 --- a/verif/tests/custom/coremark/uart.h +++ b/verif/tests/custom/coremark/uart.h @@ -16,7 +16,7 @@ #define UART_DLAB_LSB UART_BASE + 0 #define UART_DLAB_MSB UART_BASE + 4 -void init_uart(); +void init_uart(uint32_t freq, uint32_t baud); void print_uart(const char* str); diff --git a/verif/tests/custom/dcache_csr_test/dcache_csr_test.c b/verif/tests/custom/dcache_csr_test/dcache_csr_test.c new file mode 100644 index 00000000000..be5b4752018 --- /dev/null +++ b/verif/tests/custom/dcache_csr_test/dcache_csr_test.c @@ -0,0 +1,118 @@ +// vim: ts=4 : sts=4 : sw=4 : et +/* +** Copyright 2026 Inria, Universite Grenoble-Alpes +** +** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +** you may not use this file except in compliance with the License. +** You may obtain a copy of the License at +** +** https://solderpad.org/licenses/ +** +** Unless required by applicable law or agreed to in writing, software +** distributed under the License is distributed on an "AS IS" BASIS, +** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +** See the License for the specific language governing permissions and +** limitations under the License. +*/ +/* +** Author: Cesar Fuguet - Inria, Univ. Grenoble-Alpes +**/ +#include +#include + +static const unsigned int TEST_TIMEOUT = 10000; + +/* DCACHE CSR + * XLEN-1 XLEN-2 XLEN-3 .. 28 27 .. 24 23 .. 20 + * ----------------------------------------------------------------------- + * eccPresent | eccScrubberPresent | RESERVED | dirCorErr | dirUncErr + * ----------------------------------------------------------------------- + * + * 19 .. 16 15 .. 12 11 .. 8 7 .. 2 1 0 + * ----------------------------------------------------------------------- + * datCorErr | datUncErr | scrubCycles | scrubPeriod | scrubEn | cacheEn + * ----------------------------------------------------------------------- + */ +static const unsigned int CSR_DCACHE = 0x7c1u; + +#define __csr_rw(opcode, val) ({ \ + register uintptr_t ret; \ + asm volatile( \ + #opcode " %[rd], %[rs1], %[rs2]\n" \ + : [rd]"=r"(ret) \ + : [rs1]"i"(CSR_DCACHE), [rs2]"r"(val) \ + : "memory"); \ + ret; \ + }) + +static inline uintptr_t csr_dcache_read_wr(uintptr_t val) +{ + return __csr_rw(csrrw, val); +} + +static inline uintptr_t csr_dcache_read_set(uintptr_t mask) +{ + return __csr_rw(csrrs, mask); +} + +static inline uintptr_t csr_dcache_read_clr(uintptr_t mask) +{ + return __csr_rw(csrrc, mask); +} + + +static int testScrubPeriod(int period, int max_cycles) +{ + // program scrubEn and scrubPeriod (clear then set) + csr_dcache_read_clr(0x7f << 1); + csr_dcache_read_clr(0xf << 8); // clear scrubCycles counter + csr_dcache_read_set((period << 2) | 0x2); + + // wait for a given number of scrub cycles + int ret = 1; + for (int i = 0; i < TEST_TIMEOUT; i++) { + uintptr_t scrubCycles; + uintptr_t tmp = csr_dcache_read_set(0); + scrubCycles = (tmp >> 8) & 0xf; + if (scrubCycles >= max_cycles) { + ret = 0; + break; + } + } + csr_dcache_read_clr(0x2); // disable scrubber + return ret; +} + +int main(int argc, char* arg[]) +{ + int scrubPeriod; // Power of two value (2**N) -> 32 if period=5 + const int xlen = sizeof(uintptr_t) * 8; + uintptr_t tmp; + int ret = 0; + + printf("[BEG] Test DCACHE CSR\n"); + tmp = csr_dcache_read_set(0); + + // check that eccPresent bit is set + if (((tmp >> (xlen - 1)) & 0x1) == 0) { + printf("[WARNING] DCACHE ECC not supported\n"); + goto exitTest; + } + + // check that eccScrubberPresent bit is set + if (((tmp >> (xlen - 2)) & 0x1) == 0) { + printf("[WARNING] DCACHE Scrubbing mechanism not supported\n"); + goto exitTest; + } + + // start tests + printf("Enabling scrubbing (period=%d)\n", scrubPeriod); + ret = testScrubPeriod(5/*32*/, 3); + if (ret > 0) goto exitTest; + ret = testScrubPeriod(4/*16*/, 5); + +exitTest: + if (ret > 0) printf("[FAILURE] Test DCACHE CSR\n"); + else printf("[SUCCESS] Test DCACHE CSR\n"); + return ret; +} diff --git a/verif/tests/custom/debug_test/debug_test.c b/verif/tests/custom/debug_test/debug_test.c index 5111d735c41..084072d32c1 100644 --- a/verif/tests/custom/debug_test/debug_test.c +++ b/verif/tests/custom/debug_test/debug_test.c @@ -495,7 +495,7 @@ int main(int argc, char *argv[]) glb_expect_irq_entry = 1; glb_hart_status = 20; DEBUG_REQ_CONTROL_REG = debug_req_control.bits; - // 170 halts on first instuction in interrupt handler + // 170 halts on first instruction in interrupt handler // 175 gives same timing for interrupt and debug_req_i mm_ram_assert_irq(0x40000000, 175+20); diff --git a/verif/tests/custom/dhrystone/dhrystone_main.c b/verif/tests/custom/dhrystone/dhrystone_main.c index 9c7bcf544ff..038a7d4f0a0 100644 --- a/verif/tests/custom/dhrystone/dhrystone_main.c +++ b/verif/tests/custom/dhrystone/dhrystone_main.c @@ -28,7 +28,7 @@ char Ch_1_Glob, int Arr_1_Glob [50]; int Arr_2_Glob [50] [50]; -Enumeration Func_1 (); +Enumeration Func_1 (Capital_Letter, Capital_Letter); /* forward declaration necessary since Enumeration may not simply be int */ #ifndef REG diff --git a/verif/tests/custom/hgatp_warl/hgatp_mode_warl.S b/verif/tests/custom/hgatp_warl/hgatp_mode_warl.S new file mode 100644 index 00000000000..3596e2bf836 --- /dev/null +++ b/verif/tests/custom/hgatp_warl/hgatp_mode_warl.S @@ -0,0 +1,55 @@ +#include "riscv_test.h" +#include "test_macros.h" + +.option arch, +h + +#define CSR_HGATP 0x680 +#define HGATP_MODE_SV39X4 8 +#define HGATP_MODE_UNSUPPORTED 1 + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + li TESTNUM, 1 + + # Install an initial legal value: + # MODE = Sv39x4 + # PPN = 0x100 + li t0, HGATP_MODE_SV39X4 + slli t0, t0, 60 + ori t0, t0, 0x100 + + csrw CSR_HGATP, t0 + csrr t1, CSR_HGATP + + bne t1, t0, fail + + li TESTNUM, 2 + + # Write an unsupported MODE with a different PPN. + # MODE must be legalized, but PPN must still update. + li t2, HGATP_MODE_UNSUPPORTED + slli t2, t2, 60 + ori t2, t2, 0x200 + + csrw CSR_HGATP, t2 + csrr t3, CSR_HGATP + + # Expected: + # MODE remains Sv39x4 + # PPN changes to 0x200 + li t4, HGATP_MODE_SV39X4 + slli t4, t4, 60 + ori t4, t4, 0x200 + + bne t3, t4, fail + + j pass + + TEST_PASSFAIL + +RVTEST_CODE_END + +RVTEST_DATA_BEGIN + TEST_DATA +RVTEST_DATA_END diff --git a/verif/tests/custom/hlvx_gstage/hlvx_gstage_repro.S b/verif/tests/custom/hlvx_gstage/hlvx_gstage_repro.S new file mode 100644 index 00000000000..3dd80950c44 --- /dev/null +++ b/verif/tests/custom/hlvx_gstage/hlvx_gstage_repro.S @@ -0,0 +1,252 @@ +# See LICENSE for license details. + +#***************************************************************************** +# hlvx_gstage_repro.S +#----------------------------------------------------------------------------- +# +# Reproducer for the HLVX permission rule being applied to the G-stage check +# on a VS-stage page-table read (core/cva6_mmu/cva6_ptw.sv, data-path +# permission test). +# +# During a two-stage walk, when the PTW is at G_INTERMED_STAGE it is +# G-stage-translating the guest physical address of a VS-stage page table. +# That access is an IMPLICIT LOAD, so it requires pte.r and must NOT require +# pte.x. The data-path permission test applies hlvx_inst_i unconditionally, +# which switches the pte.r term off and makes pte.x mandatory, so an HLVX +# access faults on any G-stage mapping of guest page-table memory that is +# R=1, X=0. The instruction path just above already carries the stage +# condition. +# +# Mapping under test: +# G-stage : identity 4 KiB leaves over [DRAM_BASE, DRAM_BASE + 2 MiB), +# V R W X U A D everywhere, EXCEPT the three pages holding +# vs_root / vs_l1 / vs_l0, which are V R W U A D (X=0). +# That is the normal W^X hypervisor mapping: guest page tables +# are data, not code. +# VS-stage : GVA 0x1000 -> GPA target_page, V R W X A D (U=0, SPVP=1). +# +# The target page is executable at BOTH stages, so HLVX is legal here. The +# only non-executable pages in the whole setup are the guest's own page +# tables, which no correct implementation should require to be executable. +# +# probe 1 (control) : hlv.d t1, (0x1000) -- uses the pte.r term, must pass +# hfence.vvma / hfence.gvma / sfence.vma -- force a FRESH walk +# probe 2 : hlvx.hu t2, (0x1000) -- same address, same tables +# +# GSTAGE_PT_EXEC variant: identical program with PTE_X added to the G-stage +# leaves that map vs_root / vs_l1 / vs_l0. It must pass on unmodified RTL, +# which isolates the X bit on the guest page tables as the only variable. +# +# tohost = 21 (TESTNUM 21) is the defect: probe 2 took a LOAD_GUEST_PAGE_FAULT. +# Any other trap reports its own mcause as tohost. +# + +#include "riscv_test.h" +#include "test_macros.h" + +.option arch, +h + +#define CSR_HSTATUS 0x600 +#define CSR_VSSTATUS 0x200 +#define CSR_VSATP 0x280 +#define CSR_HEDELEG 0x602 +#define CSR_HGATP 0x680 + +#define HGATP_MODE_SV39X4 8 +#define HSTATUS_SPVP (1 << 8) +#define CAUSE_LOAD_GUEST_PAGE_FAULT 21 + +#define GVA_TARGET 0x1000 +#define TARGET_VALUE 0x00c0ffee0badf00d + +/* Ordinary G-stage leaf: identity, executable. */ +#define G_LEAF (PTE_V | PTE_R | PTE_W | PTE_X | PTE_U | PTE_A | PTE_D) + +/* G-stage leaf for the pages that HOLD the VS-stage page tables. */ +#ifdef GSTAGE_PT_EXEC +# define G_LEAF_PT (PTE_V | PTE_R | PTE_W | PTE_X | PTE_U | PTE_A | PTE_D) +#else +# define G_LEAF_PT (PTE_V | PTE_R | PTE_W | PTE_U | PTE_A | PTE_D) +#endif + +/* VS-stage leaf: readable AND executable, so HLVX is legal at the VS stage. */ +#define VS_LEAF (PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D) + +/* Map the 4 KiB page holding \sym in g_l0 with G_LEAF_PT (X=0 by default). */ +.macro GMAP_PT sym + la t0, \sym + srli t1, t0, 12 /* PPN of the page holding the table */ + slli t2, t1, 10 + li t3, G_LEAF_PT + or t2, t2, t3 /* the PTE */ + li t3, (DRAM_BASE >> 12) + sub t1, t1, t3 /* page index within the mapped 2 MiB */ + slli t1, t1, 3 + la t3, g_l0 + add t1, t3, t1 + sd t2, 0(t1) +.endm + +/* tmp0 = PTE pointing at \sym's page, with permission bits \perm. */ +.macro PTE_FOR sym, perm + la t0, \sym + srli t0, t0, 12 + slli t0, t0, 10 + li t1, \perm + or t0, t0, t1 +.endm + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + csrw CSR_HEDELEG, zero + csrw medeleg, zero + + # ------------------------------------------------------------------ + # G-stage l0: identity 4 KiB leaves over [DRAM_BASE, DRAM_BASE + 2 MiB). + # Everything the guest touches is inside this window. + # ------------------------------------------------------------------ + la a4, g_l0 + li a5, DRAM_BASE + li a6, 0 +1: + slli t0, a6, 12 + add t0, t0, a5 /* physical address of this page */ + srli t1, t0, 12 + slli t1, t1, 10 + li t2, G_LEAF + or t1, t1, t2 + slli t2, a6, 3 + add t2, a4, t2 + sd t1, 0(t2) + addi a6, a6, 1 + li t0, 512 + blt a6, t0, 1b + + # ------------------------------------------------------------------ + # The three pages holding the VS-stage tables are DATA: X=0. + # This is the only thing the control variant changes. + # ------------------------------------------------------------------ + GMAP_PT vs_root + GMAP_PT vs_l1 + GMAP_PT vs_l0 + + # ---- G-stage upper levels: g_root[GPA[40:30]] -> g_l1[GPA[29:21]] -> g_l0 + PTE_FOR g_l0, PTE_V + la t2, g_l1 + li t3, ((DRAM_BASE >> 21) & 0x1ff) + slli t3, t3, 3 + add t2, t2, t3 + sd t0, 0(t2) + + PTE_FOR g_l1, PTE_V + la t2, g_root + li t3, (DRAM_BASE >> 30) /* Sv39x4 root index, 2048 entries */ + slli t3, t3, 3 + add t2, t2, t3 + sd t0, 0(t2) + + # ---- VS-stage (Sv39): GVA_TARGET -> target_page. VPN2 = VPN1 = 0. + PTE_FOR vs_l1, PTE_V + la t2, vs_root + sd t0, (((GVA_TARGET >> 30) & 0x1ff) * 8)(t2) + + PTE_FOR vs_l0, PTE_V + la t2, vs_l1 + sd t0, (((GVA_TARGET >> 21) & 0x1ff) * 8)(t2) + + /* GPA == PA here, because the G-stage window is an identity map. */ + PTE_FOR target_page, VS_LEAF + la t2, vs_l0 + sd t0, (((GVA_TARGET >> 12) & 0x1ff) * 8)(t2) + + # ---- turn translation on + la t0, g_root + srli t0, t0, 12 + li t1, HGATP_MODE_SV39X4 + slli t1, t1, 60 + or t0, t0, t1 + csrw CSR_HGATP, t0 + + la t0, vs_root + srli t0, t0, 12 + li t1, SATP_MODE_SV39 + slli t1, t1, 60 + or t0, t0, t1 + csrw CSR_VSATP, t0 + + li t0, HSTATUS_SPVP /* HLV/HLVX run at effective privilege S */ + csrw CSR_HSTATUS, t0 + csrw CSR_VSSTATUS, zero /* vsstatus.MXR = 0 */ + li t0, SSTATUS_MXR + csrc sstatus, t0 /* sstatus.MXR = 0 */ + sfence.vma + hfence.gvma + hfence.vvma + + # ================================================================== + # probe 1 (control): ordinary guest load. Uses the pte.r term at every + # stage, so it is unaffected by the defect. Any trap here is a setup + # problem, not a result. + # ================================================================== + li TESTNUM, 1 + li a0, GVA_TARGET + hlv.d t1, (a0) + li t0, TARGET_VALUE + bne t1, t0, fail + + # Force a fresh walk: no DTLB or G-stage entry may survive into probe 2. + hfence.vvma + hfence.gvma + sfence.vma + + # ================================================================== + # probe 2: same address, same tables, HLVX. The target page is + # executable at both stages, so this must retire. + # ================================================================== + li TESTNUM, 2 + li t2, 0 + hlvx.hu t2, (a0) + li t0, (TARGET_VALUE & 0xffff) + bne t2, t0, fail + j pass + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + csrr t5, mcause + li t6, 2 + bne TESTNUM, t6, 1f + li t6, CAUSE_LOAD_GUEST_PAGE_FAULT + bne t5, t6, 1f + li TESTNUM, 21 /* THE DEFECT: HLVX faulted on the */ + j fail /* G-stage read of a VS page table */ +1: + mv TESTNUM, t5 /* anything else: report the cause */ + j fail + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + TEST_DATA + +.align 12 +vs_root: .fill 512, 8, 0 +.align 12 +vs_l1: .fill 512, 8, 0 +.align 12 +vs_l0: .fill 512, 8, 0 +.align 14 +g_root: .fill 2048, 8, 0 /* 16 KiB Sv39x4 root */ +.align 12 +g_l1: .fill 512, 8, 0 +.align 12 +g_l0: .fill 512, 8, 0 +.align 12 +target_page: + .dword TARGET_VALUE + .fill 511, 8, 0 +RVTEST_DATA_END diff --git a/verif/tests/custom/issues/decoder-zip-unzip-rv64.S b/verif/tests/custom/issues/decoder-zip-unzip-rv64.S new file mode 100644 index 00000000000..da3a7a2526f --- /dev/null +++ b/verif/tests/custom/issues/decoder-zip-unzip-rv64.S @@ -0,0 +1,35 @@ +# SUCCESS(a0=0) iff BOTH zip (0x08f31293) and unzip (0x08f35293) trap with +# mcause==2 on RV64. FAIL if either retires (bug) or wrong cause. + .section .text + .align 2 + .option norvc + .globl main +main: + la t0, th + csrw mtvec, t0 + csrw medeleg, zero + li s1, 0 # 0 = expecting zip trap, 1 = expecting unzip trap + .word 0x08f31293 # zip x5,x6 + li a0, 10 # retired -> bug + j fin +phase1: + li s1, 1 + .word 0x08f35293 # unzip x5,x6 + li a0, 11 # retired -> bug + j fin + .align 2 +th: + csrr t0, mcause + li t1, 2 + bne t0, t1, wc + bnez s1, pass_all # unzip trapped correctly -> done + la t1, phase1 + csrw mepc, t1 + mret +pass_all: + li a0, 0 + j fin +wc: + ori a0, t0, 0x40 +fin: + jal exit diff --git a/verif/tests/custom/issues/fcvt-rv64-only-rv32.S b/verif/tests/custom/issues/fcvt-rv64-only-rv32.S new file mode 100644 index 00000000000..289f5b8882e --- /dev/null +++ b/verif/tests/custom/issues/fcvt-rv64-only-rv32.S @@ -0,0 +1,97 @@ +# Copyright 2026 +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +.section .text + +.globl main +main: + la t0, trap_count + sw zero, 0(t0) + + # Legal RV32 F conversions. These must not trap. + # + # fcvt.w.s x0, f0 + .word 0xc0000053 + + # fcvt.wu.s x0, f0 + .word 0xc0100053 + + # fcvt.s.w f0, x0 + .word 0xd0000053 + + # fcvt.s.wu f0, x0 + .word 0xd0100053 + + # RV64-only conversions. Each must raise an + # illegal-instruction exception when XLEN=32. + # +rv64_only_begin: + # fcvt.l.s x0, f0 + .word 0xc0200053 + + # fcvt.lu.s x0, f0 + .word 0xc0300053 + + # fcvt.s.l f0, x0 + .word 0xd0200053 + + # fcvt.s.lu f0, x0 + .word 0xd0300053 + + # Exactly the four RV64-only instructions above + # must have trapped. + la t0, trap_count + lw t1, 0(t0) + li t2, 4 + bne t1, t2, failure + + li a0, 0 + ret + +failure: + li a0, 1 + ret + + +.globl handle_trap +handle_trap: + # crt.S passes: + # a0 = mcause + # a1 = mepc + # + # Only illegal-instruction exceptions are expected. + li t0, 2 + bne a0, t0, unexpected_trap + + la t0, trap_count + lw t1, 0(t0) + + # Reject extra traps and traps from any other instruction. + li t2, 4 + bgeu t1, t2, unexpected_trap + + # The four expected instructions occupy consecutive 4-byte slots. + la t2, rv64_only_begin + slli t3, t1, 2 + add t2, t2, t3 + bne a1, t2, unexpected_trap + + addi t1, t1, 1 + sw t1, 0(t0) + + # Skip the injected 32-bit instruction. + addi a0, a1, 4 + ret + +unexpected_trap: + # Resume at the failure path. + la a0, failure + ret + + +.section .data +.align 2 + +trap_count: + .word 0 diff --git a/verif/tests/custom/issues/htval-mtval2-warl-rv64.S b/verif/tests/custom/issues/htval-mtval2-warl-rv64.S new file mode 100644 index 00000000000..c3f519cad64 --- /dev/null +++ b/verif/tests/custom/issues/htval-mtval2-warl-rv64.S @@ -0,0 +1,65 @@ +# Copyright 2026 Keerthivasan +# +# Licensed under the Solderpad Hardware Licence, Version 2.0. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# +# Regression test for CVA6 issue #3537. +# +# On RV64 Sv39x4, guest physical addresses are 41 bits. htval and +# mtval2 store the guest physical address shifted right by two, so +# only bits [38:0] of these CSRs are meaningful. + + .section .text + .align 2 + + .equ CSR_MTVAL2, 0x34b + .equ CSR_HTVAL, 0x643 + + .equ SHIFTED_GPA_MASK_SV39X4, 0x0000007fffffffff + + .globl main + +main: + li t0, -1 + li t2, SHIFTED_GPA_MASK_SV39X4 + + # htval must legalize values outside the implemented shifted-GPA width. + csrw CSR_HTVAL, t0 + csrr t1, CSR_HTVAL + bne t1, t2, fail_htval + + # mtval2 must follow the same WARL behavior. + csrw CSR_MTVAL2, t0 + csrr t1, CSR_MTVAL2 + bne t1, t2, fail_mtval2 + + # Both WARL registers must be capable of holding zero. + csrw CSR_HTVAL, zero + csrr t1, CSR_HTVAL + bnez t1, fail_htval_zero + + csrw CSR_MTVAL2, zero + csrr t1, CSR_MTVAL2 + bnez t1, fail_mtval2_zero + +pass: + li a0, 0 + j finish + +fail_htval: + li a0, 1 + j finish + +fail_mtval2: + li a0, 2 + j finish + +fail_htval_zero: + li a0, 3 + j finish + +fail_mtval2_zero: + li a0, 4 + +finish: + jal exit diff --git a/verif/tests/custom/issues/i3317_reg_write.S b/verif/tests/custom/issues/i3317_reg_write.S new file mode 100644 index 00000000000..762ecc513da --- /dev/null +++ b/verif/tests/custom/issues/i3317_reg_write.S @@ -0,0 +1,27 @@ + .section .text + .align 2 + .option norvc + .globl main +main: + csrr t0, mideleg + li t1, 0x444 + and t2, t0, t1 + bne t2, t1, fail # RO-1 bits (2,6,10) are set after reset + csrw mideleg, zero + csrr t0, mideleg + and t2, t0, t1 + bne t2, t1, fail # RO-1 bits (2,6,10) survive a zero write + li t3, 0x200 # SEIP delegation (bit 9) - a real writable mideleg bit + csrw mideleg, t3 + csrr t0, mideleg + and t2, t0, t3 + bne t2, t3, fail # writable bit takes + li t1, 0x444 + and t2, t0, t1 + bne t2, t1, fail # RO-1 bits still set alongside + li a0, 0 + j fin +fail: + li a0, 1 +fin: + jal exit diff --git a/verif/tests/custom/issues/load-misaligned-warning.S b/verif/tests/custom/issues/load-misaligned-warning.S new file mode 100644 index 00000000000..ff1aa18b128 --- /dev/null +++ b/verif/tests/custom/issues/load-misaligned-warning.S @@ -0,0 +1,72 @@ +.section .text + +.globl main +main: + la t0, data_buf + + # Word load at byte offset 5. + # This is architecturally misaligned and also triggers addr_offset0. + addi t1, t0, 5 + lw t2, 0(t1) + + # Unsigned word load at the same offset. + addi t1, t0, 5 + lwu t2, 0(t1) + + # Halfword load at byte offset 7. + # This is architecturally misaligned and also triggers addr_offset1. + addi t1, t0, 7 + lh t2, 0(t1) + + # Unsigned halfword load at the same offset. + addi t1, t0, 7 + lhu t2, 0(t1) + + # All four loads must have trapped. + la t0, trap_count + lw t1, 0(t0) + li t2, 4 + bne t1, t2, fail + + li a0, 0 + ret + +fail: + li a0, 1 + ret + + +.globl handle_trap +handle_trap: + # crt.S passes: + # a0 = mcause + # a1 = mepc + # and expects the return value in a0 to be the resume PC. + + li t0, 4 + bne a0, t0, unexpected_trap + + la t0, trap_count + lw t1, 0(t0) + addi t1, t1, 1 + sw t1, 0(t0) + + # All faulting loads in this test are 32-bit instructions. + addi a0, a1, 4 + ret + +unexpected_trap: + li a0, 2 + j _exit + + +.section .data +.align 3 + +data_buf: + .dword 0x1122334455667788 + .dword 0x99aabbccddeeff00 + +.align 2 +trap_count: + .word 0 diff --git a/verif/tests/custom/issues/misaligned-branch-rvc-disabled.S b/verif/tests/custom/issues/misaligned-branch-rvc-disabled.S new file mode 100644 index 00000000000..b3468732460 --- /dev/null +++ b/verif/tests/custom/issues/misaligned-branch-rvc-disabled.S @@ -0,0 +1,28 @@ + .option norvc + .globl main + +main: + .balign 4 +branch_site: + beq zero, zero, misaligned_target + j fail + + .2byte 0 +misaligned_target: + j fail # Reaching here means the expected trap did not occur + + .2byte 0 + .globl handle_trap +handle_trap: + bnez a0, fail # mcause must be 0: instruction-address-misaligned + j pass + +.balign 4 +fail: + li a0, 1 + call exit + +.balign 4 +pass: + li a0, 0 + call exit diff --git a/verif/tests/custom/issues/mret-mpv-rv64.S b/verif/tests/custom/issues/mret-mpv-rv64.S new file mode 100644 index 00000000000..3fc0fd9f9ea --- /dev/null +++ b/verif/tests/custom/issues/mret-mpv-rv64.S @@ -0,0 +1,116 @@ +# Copyright 2026 Keerthivasan +# +# Licensed under the Solderpad Hardware Licence, Version 2.0. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# +# Regression test for CVA6 issue #3313. +# +# When MRET returns to M-mode, virtualization mode V must remain zero, +# regardless of the value previously stored in mstatus.MPV. +# +# V is internal architectural state and cannot be read directly. +# A subsequent trap to M-mode saves V into mstatus.MPV, allowing the +# post-MRET V state to be checked. + + .section .text + .align 2 + + .equ MSTATUS_MPP_MASK, 0x0000000000001800 + .equ MSTATUS_MPP_M, 0x0000000000001800 + .equ MSTATUS_MPV, 0x0000008000000000 + + .equ CAUSE_ECALL_M, 11 + + .globl main + +main: + # Send all exceptions used by this test to M-mode. + la t0, trap_handler + csrw mtvec, t0 + + csrw medeleg, zero + csrw mideleg, zero + csrw hedeleg, zero + csrw hideleg, zero + + # Configure MRET to return to M-mode. + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + + li t0, MSTATUS_MPP_M + csrs mstatus, t0 + + # Deliberately set MPV before MRET. + # + # The Hypervisor specification requires MRET to ignore MPV when + # MPP=M and to keep virtualization mode V equal to zero. + li t0, MSTATUS_MPV + csrc mstatus, t0 + csrs mstatus, t0 + + # Confirm that MPV was writable so the test exercises the intended case. + csrr t0, mstatus + li t1, MSTATUS_MPV + and t2, t0, t1 + beqz t2, fail_2 + + la t0, m_entry + csrw mepc, t0 + mret + +m_entry: + # Trap entry saves the current V state into mstatus.MPV. + ecall + + # ECALL must trap. + li a0, 1 + j finish + + .align 2 +trap_handler: + csrr t0, mstatus + + # Main regression check. + # + # On the buggy RTL, MRET copies MPV=1 into V even though MPP=M. + # Trap entry then saves that incorrect V=1 value back into MPV. + li t1, MSTATUS_MPV + and t2, t0, t1 + bnez t2, fail_8 + + # The trap must originate from M-mode. + li t1, MSTATUS_MPP_MASK + and t2, t0, t1 + li t3, MSTATUS_MPP_M + bne t2, t3, fail_9 + + # ECALL from M-mode must report exception cause 11. + csrr t0, mcause + li t1, CAUSE_ECALL_M + bne t0, t1, fail_3 + +pass: + li a0, 0 + j finish + +fail_2: + # MPV was unavailable or not writable. + li a0, 2 + j finish + +fail_3: + # Unexpected trap cause. + li a0, 3 + j finish + +fail_8: + # Issue #3313 reproduced: V remained set after MRET to M-mode. + li a0, 8 + j finish + +fail_9: + # Trap did not originate from M-mode. + li a0, 9 + +finish: + jal exit diff --git a/verif/tests/custom/issues/pmp-misalign-priority-over-access-fault.S b/verif/tests/custom/issues/pmp-misalign-priority-over-access-fault.S new file mode 100644 index 00000000000..0454ae24a3e --- /dev/null +++ b/verif/tests/custom/issues/pmp-misalign-priority-over-access-fault.S @@ -0,0 +1,41 @@ + .section .text + .align 2 + .option norvc + .globl main +main: + la t0, th + csrw mtvec, t0 + csrw medeleg, zero + csrw vsatp, zero + li s4, 0 + li a2, 0x80100003 + li a3, 0x1122334455667788 + hsv.d a3, (a2) + li a0, 10 + j fin +phase1: + li s4, 1 + hlv.d a4, (a2) + li a0, 11 + j fin + .align 2 +th: + csrr t0, mcause + csrr t1, mepc + addi t1, t1, 4 + csrw mepc, t1 + bnez s4, 1f + li t2, 6 + bne t0, t2, bad + la t1, phase1 + csrw mepc, t1 + mret +1: + li t2, 4 + bne t0, t2, bad + li a0, 0 + j fin +bad: + ori a0, t0, 0x40 +fin: + jal exit diff --git a/verif/tests/custom/issues/pmp-tor-grain-rv64.S b/verif/tests/custom/issues/pmp-tor-grain-rv64.S new file mode 100644 index 00000000000..26cf28b6d82 --- /dev/null +++ b/verif/tests/custom/issues/pmp-tor-grain-rv64.S @@ -0,0 +1,191 @@ +# Regression test for CVA6 issue #3342. +# +# CVA6 implements an eight-byte PMP grain (G=1), so pmpaddr[0] must not +# affect either boundary of a TOR region. Check a denied partial boundary, +# an allowed complete doubleword, and a lower boundary shared by two entries. + +#include "encoding.h" + + .equ MSTATUS_MPP_S, (PRV_S << 11) + .equ CAUSE_LOAD_ACCESS_FAULT, 5 + .equ PMP_RWX_TOR, (PMP_TOR | PMP_R | PMP_W | PMP_X) + .equ PMP_X_TOR, (PMP_TOR | PMP_X) + .equ PMP_RW_TOR, (PMP_TOR | PMP_R | PMP_W) + .equ SECRET, 0x89abcdef01234567 + + # Keep this complete test in the first load segment. This makes the PMP + # regression independent of ELF segment preloading in the test harness. + .section .text.init, "ax", @progbits + .align 2 + .globl main + +main: + la t0, trap_handler + csrw mtvec, t0 + csrw medeleg, zero + csrw mideleg, zero + csrw satp, zero + sfence.vma + + li t0, 1 + csrw mscratch, t0 + j setup_partial_top + +# Phase 1: pmpaddr0 contains (target + 4) >> 2. Its low bit must be ignored, +# so the effective top is target and an S-mode load at target must fault. +setup_partial_top: + csrw pmpcfg0, zero + + la t0, target + addi t0, t0, 4 + srli t0, t0, PMP_SHIFT + csrw pmpaddr0, t0 + + la t0, target_end + srli t0, t0, PMP_SHIFT + csrw pmpaddr1, t0 + + li t0, (PMP_TOR << 8) | PMP_RWX_TOR + csrw pmpcfg0, t0 + fence + + la t0, probe_partial_top + j enter_s_mode + +probe_partial_top: + li a0, 11 + la t0, target + ld t1, 0(t0) + ecall + +# Phase 2: moving the effective top to target + 8 must allow the complete, +# naturally aligned doubleword. +setup_complete_top: + csrw pmpcfg0, zero + + la t0, target + addi t0, t0, 8 + srli t0, t0, PMP_SHIFT + csrw pmpaddr0, t0 + csrw pmpaddr1, t0 + + li t0, (PMP_TOR << 8) | PMP_RWX_TOR + csrw pmpcfg0, t0 + fence + + la t0, probe_complete_top + j enter_s_mode + +probe_complete_top: + li a0, 21 + la t0, target + ld t1, 0(t0) + li t2, SECRET + bne t1, t2, report_complete_top + li a0, 0 +report_complete_top: + ecall + +# Phase 3: the same raw pmpaddr0 value is the top of an execute-only entry +# and the bottom of a read/write entry. Both uses must ignore bit 0, making +# target readable through entry 1 rather than denied by entry 0. +setup_shared_boundary: + csrw pmpcfg0, zero + + la t0, target + addi t0, t0, 4 + srli t0, t0, PMP_SHIFT + csrw pmpaddr0, t0 + + la t0, target_end + srli t0, t0, PMP_SHIFT + csrw pmpaddr1, t0 + + li t0, (PMP_RW_TOR << 8) | PMP_X_TOR + csrw pmpcfg0, t0 + fence + + la t0, probe_shared_boundary + j enter_s_mode + +probe_shared_boundary: + li a0, 31 + la t0, target + ld t1, 0(t0) + li t2, SECRET + bne t1, t2, report_shared_boundary + li a0, 0 +report_shared_boundary: + ecall + +enter_s_mode: + li t1, MSTATUS_MPP + csrc mstatus, t1 + li t1, MSTATUS_MPP_S + csrs mstatus, t1 + csrw mepc, t0 + mret + + .align 2 +trap_handler: + csrr t0, mscratch + li t1, 1 + beq t0, t1, handle_partial_top + li t1, 2 + beq t0, t1, handle_complete_top + li t1, 3 + beq t0, t1, handle_shared_boundary + li a0, 40 + j finish + +handle_partial_top: + csrr t0, mcause + li t1, CAUSE_LOAD_ACCESS_FAULT + bne t0, t1, finish + + li t0, 2 + csrw mscratch, t0 + j setup_complete_top + +handle_complete_top: + csrr t0, mcause + li t1, CAUSE_SUPERVISOR_ECALL + bne t0, t1, fail_complete_top + bnez a0, finish + + li t0, 3 + csrw mscratch, t0 + j setup_shared_boundary + +fail_complete_top: + li a0, 22 + j finish + +handle_shared_boundary: + csrr t0, mcause + li t1, CAUSE_SUPERVISOR_ECALL + bne t0, t1, fail_shared_boundary + bnez a0, finish + li a0, 0 + j finish + +fail_shared_boundary: + li a0, 32 + +finish: + csrw pmpcfg0, zero + fence + + # Encode a0 using the RISC-V test convention and terminate through tohost. + slli a0, a0, 1 + ori a0, a0, 1 + la t0, tohost + sd a0, 0(t0) +1: + j 1b + + .align 3 +target: + .dword SECRET +target_end: + .dword 0 diff --git a/verif/tests/custom/issues/vsmode_counterh_cause.S b/verif/tests/custom/issues/vsmode_counterh_cause.S new file mode 100644 index 00000000000..1a885160ec6 --- /dev/null +++ b/verif/tests/custom/issues/vsmode_counterh_cause.S @@ -0,0 +1,79 @@ +# vsmode_counterh_cause.S +# Directed test for openhwgroup/cva6#3466: +# "RV64+H: high-half counter CSR access from VS-mode reports cause 22 +# instead of cause 2" +# +# Per spec, on RV64 (XLEN=64) an access to a high-half counter CSR (cycleh, +# instreth, hpmcounterNh) is always illegal (cause 2), regardless of mode or +# counter-enable bits -- high-half CSRs only exist on RV32. CVA6 currently +# gates cycleh/instreth using the same counter-enable privilege logic as the +# low CSRs, with no RV64 guard, so from VS-mode with mcounteren enabled but +# hcounteren disabled, the access instead raises a virtual-instruction +# exception (cause 22) via virtual_privilege_violation. +# +# This test: from M-mode, enables mcounteren bit0 (cycle/cycleh), leaves +# hcounteren bit0 clear (default), enters VS-mode via mret (mstatus.MPP=S, mstatus.MPV=1), +# and executes a cycleh read. The resulting trap (delivered +# to M-mode, no H-delegation configured) must report mcause=2, not 22. + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + .align 2 + .option norvc + + li TESTNUM, 2 + + la t0, mtvec_handler + csrw mtvec, t0 + + # enable mcounteren bit0 (cycle/cycleh gating) -- leaves hcounteren bit0 + # clear (its reset value), so accessing from V=1,S-mode should hit the + # virtual_privilege_violation path in the buggy RTL. + li t0, 1 + csrs mcounteren, t0 + + # mstatus.MPP = S (2'b01, bits [12:11]) and mstatus.MPV = 1 (bit 39) -- + # MRET (unlike SRET, which uses hstatus.SPV) uses mstatus.MPV to decide + # the new virtualization mode, so it lands in VS-mode (S-mode, V=1). + csrr t0, mstatus + li t1, ~(3 << 11) + and t0, t0, t1 + li t1, (1 << 11) + or t0, t0, t1 + li t1, 1 + slli t1, t1, 39 + or t0, t0, t1 + csrw mstatus, t0 + + la t0, vs_mode_entry + csrw mepc, t0 + mret + +vs_mode_entry: + csrr t0, 0xC80 # cycleh -- must trap, cause must be 2 + + # should never retire past the csrr above + j fail + + TEST_PASSFAIL + + .align 8 + .global mtvec_handler +mtvec_handler: + csrr t0, mcause + li t1, 2 + beq t0, t1, 1f + j fail +1: + j pass + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + TEST_DATA +RVTEST_DATA_END diff --git a/verif/tests/custom/issues/xret-mprv-clear-rv64.S b/verif/tests/custom/issues/xret-mprv-clear-rv64.S new file mode 100644 index 00000000000..561eb2f5c76 --- /dev/null +++ b/verif/tests/custom/issues/xret-mprv-clear-rv64.S @@ -0,0 +1,228 @@ +# Copyright 2026 Keerthivasan +# +# Licensed under the Solderpad Hardware Licence, Version 2.0. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# +# Regression test for CVA6 issue #3294. +# +# MRET and SRET must clear mstatus.MPRV when returning to a +# privilege mode below M-mode, independently of RVH. + + .section .text + .align 2 + + .equ MSTATUS_SPP, 0x00000100 + .equ MSTATUS_MPP_MASK, 0x00001800 + .equ MSTATUS_MPP_S, 0x00000800 + .equ MSTATUS_MPP_M, 0x00001800 + .equ MSTATUS_MPRV, 0x00020000 + + .equ CAUSE_ECALL_U, 8 + .equ CAUSE_ECALL_S, 9 + + .globl main + +main: + # Route the ECALLs used by this test to M-mode. + la t0, trap_handler + csrw mtvec, t0 + csrw medeleg, zero + csrw mideleg, zero + + # Run the lower-privilege portions of this regression in Bare mode. + # The test exercises xRET privilege state, not virtual-memory setup. + csrw satp, zero + sfence.vma + + # Permit S/U-mode execution of the test image. + # + # PMP entry 0 is configured as a TOR region from address zero to the + # highest representable physical address, with read/write/execute + # permissions enabled. The target implements PMP and otherwise resets + # all entries with address matching disabled. + li t0, -1 + csrw pmpaddr0, t0 + li t0, 0x0f + csrw pmpcfg0, t0 + fence + + # ------------------------------------------------------------------ + # Phase 0: MRET from M-mode to M-mode. + # + # MPRV must be preserved when MRET returns to M-mode. + # ------------------------------------------------------------------ + li t0, MSTATUS_MPRV + csrs mstatus, t0 + + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + + li t0, MSTATUS_MPP_M + csrs mstatus, t0 + + # Verify MPRV is set before MRET. + csrr t0, mstatus + li t1, MSTATUS_MPRV + and t2, t0, t1 + beqz t2, fail_mprv_write_mret + + la t0, mret_m_entry + csrw mepc, t0 + mret + +mret_m_entry: + # MRET to M-mode must preserve MPRV. + csrr t0, mstatus + li t1, MSTATUS_MPRV + and t2, t0, t1 + beqz t2, fail_mret_mprv_preserve + + # ------------------------------------------------------------------ + # Phase 1: MRET from M-mode to S-mode. + # ------------------------------------------------------------------ + li s0, 1 + + # Configure MPRV=1 and MPP=S. + li t0, MSTATUS_MPRV + csrc mstatus, t0 + + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + + li t0, MSTATUS_MPRV + csrs mstatus, t0 + + li t0, MSTATUS_MPP_S + csrs mstatus, t0 + + # Ensure MPRV was actually writable. + csrr t0, mstatus + li t1, MSTATUS_MPRV + and t2, t0, t1 + beqz t2, fail_mprv_write_mret + + # MRET must clear MPRV because the target privilege is S-mode. + la t0, mret_s_entry + csrw mepc, t0 + mret + +mret_s_entry: + # Return to M-mode so the trap handler can inspect mstatus.MPRV. + ecall + + # ECALL must not return here. + li a0, 7 + j finish + + # ------------------------------------------------------------------ + # Phase 2: SRET from M-mode to U-mode. + # ------------------------------------------------------------------ +sret_setup: + li s0, 2 + + # Set MPRV=1 again. + li t0, MSTATUS_MPRV + csrs mstatus, t0 + + # Configure SRET to return to U-mode by clearing SPP. + li t0, MSTATUS_SPP + csrc mstatus, t0 + + # Ensure MPRV is set before SRET. + csrr t0, mstatus + li t1, MSTATUS_MPRV + and t2, t0, t1 + beqz t2, fail_mprv_write_sret + + la t0, sret_u_entry + csrw sepc, t0 + sret + +sret_u_entry: + # Return to M-mode so the trap handler can inspect MPRV. + ecall + + # ECALL must not return here. + li a0, 8 + j finish + + .align 2 +trap_handler: + li t0, 1 + beq s0, t0, check_mret + + li t0, 2 + beq s0, t0, check_sret + + li a0, 9 + j finish + +check_mret: + # ECALL must have originated from S-mode. + csrr t0, mcause + li t1, CAUSE_ECALL_S + bne t0, t1, fail_mret_cause + + # Main MRET regression check. + csrr t0, mstatus + li t1, MSTATUS_MPRV + and t2, t0, t1 + bnez t2, fail_mret_mprv + + # Return from this M-mode trap to M-mode and start the SRET phase. + la t0, sret_setup + csrw mepc, t0 + + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + + li t0, MSTATUS_MPP_M + csrs mstatus, t0 + + mret + +check_sret: + # ECALL must have originated from U-mode. + csrr t0, mcause + li t1, CAUSE_ECALL_U + bne t0, t1, fail_sret_cause + + # Main SRET regression check. + csrr t0, mstatus + li t1, MSTATUS_MPRV + and t2, t0, t1 + bnez t2, fail_sret_mprv + +pass: + li a0, 0 + j finish + +fail_mprv_write_mret: + li a0, 1 + j finish + +fail_mret_cause: + li a0, 2 + j finish + +fail_mret_mprv: + li a0, 3 + j finish + +fail_mprv_write_sret: + li a0, 4 + j finish + +fail_sret_cause: + li a0, 5 + j finish + +fail_sret_mprv: + li a0, 6 + j finish + +fail_mret_mprv_preserve: + li a0, 10 + +finish: + jal exit diff --git a/verif/tests/custom/lsu/false_4k_alias.S b/verif/tests/custom/lsu/false_4k_alias.S new file mode 100644 index 00000000000..d9fa6077dd5 --- /dev/null +++ b/verif/tests/custom/lsu/false_4k_alias.S @@ -0,0 +1,39 @@ +# Copyright 2026 Srinidhi-Magesh +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +# Check that a conservative 4 KiB alias never forwards data from another page. + + .globl main +main: + la t0, page_a + la t1, page_b + + # page_a + 0x18 and page_b + 0x18 intentionally have identical [11:3] + # address bits, but page_a and page_b are distinct 4 KiB-aligned pages. + li t2, 0x13579bdf + sw t2, 0x18(t1) + fence rw, rw + + # Keep the store and load adjacent so the older store can still be pending. + li a2, 0x55667788 + sw a2, 0x18(t0) + lw a3, 0x18(t1) + bne a3, t2, fail + +pass: + li a0, 0 + jal exit + +fail: + li a0, 1 + jal exit + + .section .data,"aw",@progbits + .balign 4096 +page_a: + .space 4096 +page_b: + .space 4096 diff --git a/verif/tests/custom/pmp/amo_access_fault_test.S b/verif/tests/custom/pmp/amo_access_fault_test.S new file mode 100644 index 00000000000..5f2ec45d6f6 --- /dev/null +++ b/verif/tests/custom/pmp/amo_access_fault_test.S @@ -0,0 +1,100 @@ +// Copyright 2026 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + .equ STORE_AMO_ACCESS_FAULT, 7 + .equ AMO_RESULT_SENTINEL, 0x5a5a5a5a5a5a5a5a + + .section .text + .globl main +main: + // Entry 0 is a locked four-KiB NAPOT region with no permissions. Entry 1 + // covers the remaining address space so that the load adjacent to the AMO + // is allowed. + la t0, target_no_access + srli t0, t0, 2 + ori t0, t0, 0x1ff + csrw pmpaddr0, t0 + li t0, -1 + csrw pmpaddr1, t0 + li t0, 0x00001f98 + csrw pmpcfg0, t0 + + la t0, trap_count + sw zero, 0(t0) + + // A PMP-denied AMO must report a store/AMO access fault, not a load + // access fault. Keep an allowed load immediately behind it to expose + // request/response access-type and tval misalignment. + la t0, target_no_access + call set_expected_tval + li t1, 1 + li t3, AMO_RESULT_SENTINEL + la t2, allowed_data + .option push + .option norvc + amoadd.d t3, t1, (t0) + ld t4, 0(t2) + .option pop + li t0, 1 + call check_trap_count + li t0, AMO_RESULT_SENTINEL + bne t3, t0, fail + +pass: + li a0, 0 + tail exit + +fail: + li a0, 1 + tail exit + +set_expected_tval: + la t1, expected_tval + sd t0, 0(t1) + ret + +check_trap_count: + la t1, trap_count + lw t1, 0(t1) + bne t0, t1, fail + ret + + .globl handle_trap +handle_trap: + li t0, STORE_AMO_ACCESS_FAULT + bne a0, t0, trap_fail + + csrr t0, mtval + la t1, expected_tval + ld t1, 0(t1) + bne t0, t1, trap_fail + + la t0, trap_count + lw t1, 0(t0) + addi t1, t1, 1 + sw t1, 0(t0) + + // crt.S writes the returned address to mepc before executing mret. + addi a0, a1, 4 + ret + +trap_fail: + li a0, 1 + tail exit + + .section .data, "aw", @progbits + .align 3 +expected_tval: + .dword 0 +trap_count: + .word 0 + .align 3 +allowed_data: + .dword 0 + + .balign 4096 +target_no_access: + .dword 0 diff --git a/verif/tests/custom/pmp/decreasing_entries_test.S b/verif/tests/custom/pmp/decreasing_entries_test.S new file mode 100644 index 00000000000..9ad2c3dc7c8 --- /dev/null +++ b/verif/tests/custom/pmp/decreasing_entries_test.S @@ -0,0 +1,98 @@ +# ------------------------------------------------------------------------------ +# Copyright 2024 Robert Bosch GmbH +# +# SPDX-License-Identifier: SHL-0.51 +# +# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS +# ------------------------------------------------------------------------------ +# decreasing_entries_test.S (TST04-4) +# ------------------------------------------------------------------------------ + + .text + .globl main +main: + + # Configure PMP using decreasing entries of TOR. + + # From 0xB000_0000 to 0xC000_0000 Read-Write-Execute. + li t0, 0x30000000 + csrw pmpaddr7, t0 + + # From 0xA000_0000 to 0xB000_0000 Read-Write-Execute. + li t0, 0x2c000000 + csrw pmpaddr6, t0 + + # From 0x9000_0000 to 0xA000_0000 Read-Write-Execute. + li t0, 0x28000000 + csrw pmpaddr5, t0 + + # From 0x8000_0000 to 0x9000_0000 Read-Write-Execute. + li t0, 0x24000000 + csrw pmpaddr4, t0 + + # From 0x0002_0000 to 0x8000_0000 no Permissions. + li t0, 0x20000000 + csrw pmpaddr3, t0 + + # From 0x0001_0000 to 0x0002_0000 only Execute. + li t0, 0x00008000 + csrw pmpaddr2, t0 + + # From 0x0000_1000 to 0x0001_0000 no Permissions. + li t0, 0x00004000 + csrw pmpaddr1, t0 + + # From 0x0000_0000 to 0x0000_1000 only Execute. + li t0, 0x00000400 + csrw pmpaddr0, t0 + + + # Addr 4-7 configs, written in cfg1, with LOCK OFF, and TOR. + li t0, 0x0f0f0f0f + csrw pmpcfg1, t0 + + # Addr 0-3 configs, written in cfg0, with LOCK OFF, and TOR. + li t0, 0x080c080c + csrw pmpcfg0, t0 + + + # Do the READ-WRITE test. + + # Check 1 read-write test, at 0x8800_0000. + li t1, 0x88000000 + li t2, 0xEFFACED1 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check 2 read-write test, at 0x9800_0000. + li t1, 0x98000000 + li t2, 0xACCEDED2 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check 3 read-write test, at 0xA800_0000. + li t1, 0xA8000000 + li t2, 0xDEFACED3 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check 4 read-write test, at 0xB800_0000. + li t1, 0xB8000000 + li t2, 0xDEC0DED4 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + +pass: + # Success post-processing + li a0, 0x0; + jal exit; + +fail: + # Failure post-processing + li a0, 0x1; + jal exit; diff --git a/verif/tests/custom/pmp/defined_matches_test.S b/verif/tests/custom/pmp/defined_matches_test.S new file mode 100644 index 00000000000..2df2a845122 --- /dev/null +++ b/verif/tests/custom/pmp/defined_matches_test.S @@ -0,0 +1,48 @@ +# ------------------------------------------------------------------------------ +# Copyright 2024 Robert Bosch GmbH +# +# SPDX-License-Identifier: SHL-0.51 +# +# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS +# ------------------------------------------------------------------------------ +# defined_matches_test.S (TST10-1, TST10-2) +# ------------------------------------------------------------------------------ + + .text + .globl main +main: + + # Check a Memory Access succeeds if no PMP entry is defined. + li t1, 0x90000000 + li t2, 0xC0D1F1ED + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Set up a PMP entry using NAPOT, from 0x8000_0000 to 0xA0000_0000, Read-Write-Execute. + li t0, 0x0000001f + csrw pmpcfg0, t0 + csrr t1, pmpcfg0 + bne t0, t1, fail + li t0, 0x23ffffff + csrw pmpaddr0, t0 + csrr t1, pmpaddr0 + bne t0, t1, fail + + # Check a memory access succeeds if no PMP entry matches. + li t1, 0xB0000000 + li t2, 0xCA5CADED + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + +pass: + # Success post-processing + li a0, 0x0; + jal exit; + +fail: + # Failure post-processing + li a0, 0x1; + jal exit; diff --git a/verif/tests/custom/pmp/double_entries_test.S b/verif/tests/custom/pmp/double_entries_test.S new file mode 100644 index 00000000000..a7e7ef988da --- /dev/null +++ b/verif/tests/custom/pmp/double_entries_test.S @@ -0,0 +1,72 @@ +# ------------------------------------------------------------------------------ +# Copyright 2024 Robert Bosch GmbH +# +# SPDX-License-Identifier: SHL-0.51 +# +# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS +# ------------------------------------------------------------------------------ +# double_entries_test.S (TST04-2) +# ------------------------------------------------------------------------------ + + .text + .globl main +main: + + # Set up PMP using NAPOT, from 0xB000_0000 to 0xC000_0000, Read-Write. + li t0, 0x001b0000 + csrw pmpcfg1, t0 + csrr t1, pmpcfg1 + bne t0, t1, fail + li t0, 0x2dffffff + csrw pmpaddr6, t0 + csrr t1, pmpaddr6 + bne t0, t1, fail + + # Set up PMP using NAPOT, from 0x8000_0000 to 0x9000_0000, Read-Write. + li t0, 0x001b0000 + csrw pmpcfg0, t0 + csrr t1, pmpcfg0 + bne t0, t1, fail + li t0, 0x21ffffff + csrw pmpaddr2, t0 + csrr t1, pmpaddr2 + bne t0, t1, fail + + # Read-Write check in 0xB800_0000. + li t1, 0xB8000000 + li t2, 0xC0D1F1ED + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Read-Write check in 0x8800_0000. + li t1, 0x88000000 + li t2, 0xCA5CADED + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check that all other addr / cfg are zero. + csrr t0, pmpaddr0 + bne t0, zero, fail + csrr t0, pmpaddr1 + bne t0, zero, fail + csrr t0, pmpaddr3 + bne t0, zero, fail + csrr t0, pmpaddr4 + bne t0, zero, fail + csrr t0, pmpaddr5 + bne t0, zero, fail + csrr t0, pmpaddr7 + bne t0, zero, fail + + +pass: + # Success post-processing + li a0, 0x0; + jal exit; + +fail: + # Failure post-processing + li a0, 0x1; + jal exit; diff --git a/verif/tests/custom/pmp/exact_csrr_test.S b/verif/tests/custom/pmp/exact_csrr_test.S new file mode 100644 index 00000000000..965d9f2e889 --- /dev/null +++ b/verif/tests/custom/pmp/exact_csrr_test.S @@ -0,0 +1,106 @@ +# ------------------------------------------------------------------------------ +# Copyright 2024 Robert Bosch GmbH +# +# SPDX-License-Identifier: SHL-0.51 +# +# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS +# ------------------------------------------------------------------------------ +# exact_csrr_test.S (TST05-1) +# ------------------------------------------------------------------------------ + + .text + .globl main +main: + + # Write in addresses and check what is written. + + # Checking PMP ADDR 0 + li t0, 0xFACADE00 + csrw pmpaddr0, t0 + csrr t1, pmpaddr0 + bne t0, t1, fail + csrw pmpaddr0, zero + + # Checking PMP ADDR 1 + li t0, 0xFACADE02 + csrw pmpaddr1, t0 + csrr t1, pmpaddr1 + bne t0, t1, fail + csrw pmpaddr1, zero + + # Checking PMP ADDR 2 + li t0, 0xFACADE04 + csrw pmpaddr2, t0 + csrr t1, pmpaddr2 + bne t0, t1, fail + csrw pmpaddr2, zero + + # Checking PMP ADDR 3 + li t0, 0xFACADE06 + csrw pmpaddr3, t0 + csrr t1, pmpaddr3 + bne t0, t1, fail + csrw pmpaddr3, zero + + # Checking PMP ADDR 4 + li t0, 0xFACADE08 + csrw pmpaddr4, t0 + csrr t1, pmpaddr4 + bne t0, t1, fail + csrw pmpaddr4, zero + + # Checking PMP ADDR 5 + li t0, 0xFACADE0A + csrw pmpaddr5, t0 + csrr t1, pmpaddr5 + bne t0, t1, fail + csrw pmpaddr5, zero + + # Checking PMP ADDR 6 + li t0, 0xFACADE0C + csrw pmpaddr6, t0 + csrr t1, pmpaddr6 + bne t0, t1, fail + csrw pmpaddr6, zero + + # Checking PMP ADDR 7 + li t0, 0xFACADE0E + csrw pmpaddr7, t0 + csrr t1, pmpaddr7 + bne t0, t1, fail + csrw pmpaddr7, zero + + # Checking PMP ADDR 63 boundary + li t0, 0xFACADE7E + csrw pmpaddr63, t0 + csrr t1, pmpaddr63 + bnez t1, fail + csrw pmpaddr63, zero + + + # Write in configurations and check what is written, except for the reserved combinations with R=0 and W=1. + + # Checking PMP CFG 0 + li t0, 0x01030304 + csrw pmpcfg0, t0 + csrr t1, pmpcfg0 + bne t0, t1, fail + csrw pmpcfg0, zero + + # Checking PMP CFG 1 + li t0, 0x04050507 + csrw pmpcfg1, t0 + csrr t1, pmpcfg1 + bne t0, t1, fail + csrw pmpcfg1, zero + + +pass: + # Success post-processing + li a0, 0x0; + jal exit; + +fail: + # Failure post-processing + li a0, 0x1; + jal exit; diff --git a/verif/tests/custom/pmp/granularity_test.S b/verif/tests/custom/pmp/granularity_test.S new file mode 100644 index 00000000000..e341d0c8ad4 --- /dev/null +++ b/verif/tests/custom/pmp/granularity_test.S @@ -0,0 +1,44 @@ +# ------------------------------------------------------------------------------ +# Copyright 2024 Robert Bosch GmbH +# +# SPDX-License-Identifier: SHL-0.51 +# +# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS +# ------------------------------------------------------------------------------ +# granularity_test.S (TST01) +# ------------------------------------------------------------------------------ + + .text + .globl main +main: + + # Configure PMP to find its granularity. + + # Write all zeroes in cfg0. + li t0, 0 + csrw pmpcfg0, t0 + + # Write all ones in addr0. + li t1, -1 + csrw pmpaddr0, t1 + + # Read the value back. + csrr t2, pmpaddr0 + + # Check for granularity 8 = 2^(1+2) <=> G = 1. + # As per: https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/PMP.html + # Which states: The PMP grain is 2**G+2. Only a PMP granularity of 8 bytes (G=1) is supported in CVA6. + # And from the RISC-V Spec: G is the index of the least-significant bit set, the PMP granularity is 2^(G+2) bytes. + li t3, 0xFFFFFFFE + bne t2, t3, fail + + +pass: + # Success post-processing + li a0, 0x0; + jal exit; + +fail: + # Failure post-processing + li a0, 0x1; + jal exit; diff --git a/verif/tests/custom/pmp/hlvx_access_fault_test.S b/verif/tests/custom/pmp/hlvx_access_fault_test.S new file mode 100644 index 00000000000..84e125c71ed --- /dev/null +++ b/verif/tests/custom/pmp/hlvx_access_fault_test.S @@ -0,0 +1,116 @@ +// Copyright 2026 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + .equ LOAD_ACCESS_FAULT, 5 + .equ HLVX_RESULT_SENTINEL, 0x5a5a5a5a5a5a5a5a + + .option arch, +h + .section .text + .globl main +main: + // Entry 0 is a locked, read-only four-KiB NAPOT region. Entry 1 + // allows all other accesses. HLVX must require execute permission even + // with address translation disabled and the instruction running in M-mode. + la t0, target_read_only + srli t0, t0, 2 + ori t0, t0, 0x1ff + csrw pmpaddr0, t0 + li t0, -1 + csrw pmpaddr1, t0 + li t0, 0x00001f99 + csrw pmpcfg0, t0 + + la t0, trap_count + sw zero, 0(t0) + + // Ordinary loads from the read-only region must still succeed when an + // executable HLVX request follows immediately. This checks that a later + // request cannot impose execute permission on the earlier response. + la t0, target_read_only + la t2, allowed_data + .option push + .option norvc + ld t3, 0(t0) + hlvx.hu t4, (t2) + .option pop + li t0, 0x1234 + bne t3, t0, fail + li t0, 0x5678 + bne t4, t0, fail + li t0, 0 + call check_trap_count + + // A denied HLVX must fault with its own tval and leave its destination + // unchanged, even when the next request is an ordinary allowed load. + la t0, target_read_only + call set_expected_tval + li t3, HLVX_RESULT_SENTINEL + la t2, allowed_data + .option push + .option norvc + hlvx.hu t3, (t0) + ld t4, 0(t2) + .option pop + li t0, 1 + call check_trap_count + li t0, HLVX_RESULT_SENTINEL + bne t3, t0, fail + +pass: + li a0, 0 + tail exit + +fail: + li a0, 1 + tail exit + +set_expected_tval: + la t1, expected_tval + sd t0, 0(t1) + ret + +check_trap_count: + la t1, trap_count + lw t1, 0(t1) + bne t0, t1, fail + ret + + .globl handle_trap +handle_trap: + li t0, LOAD_ACCESS_FAULT + bne a0, t0, trap_fail + + csrr t0, mtval + la t1, expected_tval + ld t1, 0(t1) + bne t0, t1, trap_fail + + la t0, trap_count + lw t1, 0(t0) + addi t1, t1, 1 + sw t1, 0(t0) + + // crt.S writes the returned address to mepc before executing mret. + addi a0, a1, 4 + ret + +trap_fail: + li a0, 1 + tail exit + + .section .data, "aw", @progbits + .align 3 +expected_tval: + .dword 0 +trap_count: + .word 0 + .align 3 +allowed_data: + .dword 0x5678 + + .balign 4096 +target_read_only: + .dword 0x1234 diff --git a/verif/tests/custom/pmp/locked_outside_napot_test.S b/verif/tests/custom/pmp/locked_outside_napot_test.S new file mode 100644 index 00000000000..cc653b1cff2 --- /dev/null +++ b/verif/tests/custom/pmp/locked_outside_napot_test.S @@ -0,0 +1,45 @@ +# ------------------------------------------------------------------------------ +# Copyright 2024 Robert Bosch GmbH +# +# SPDX-License-Identifier: SHL-0.51 +# +# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS +# ------------------------------------------------------------------------------ +# locked_outside_napot_test.S (TST14-26, TST14-36) +# ------------------------------------------------------------------------------ + + .text + .globl main +main: + + # Set up PMP using NAPOT, from 0x8000_0000 to 0xB000_0000. + li t2, 0x25ffffff + csrw pmpaddr0, t2 + + # Configure it with LOCK ON, Read-Write-Execute. + li t0, 0x0000009f + csrw pmpcfg0, t0 + csrr t1, pmpcfg0 + bne t0, t1, fail + + # Check pmpaddr after switching to NAPOT (and lock) + csrr t0, pmpaddr0 + bne t0, t2, fail + + # Check a memory access succeeds when outside the LOCKED entry. + li t1, 0xB8000000 + li t2, 0xC0D1F1ED + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + +pass: + # Success post-processing + li a0, 0x0; + jal exit; + +fail: + # Failure post-processing + li a0, 0x1; + jal exit; diff --git a/verif/tests/custom/pmp/locked_outside_tor_test.S b/verif/tests/custom/pmp/locked_outside_tor_test.S new file mode 100644 index 00000000000..6db06b95661 --- /dev/null +++ b/verif/tests/custom/pmp/locked_outside_tor_test.S @@ -0,0 +1,61 @@ +# ------------------------------------------------------------------------------ +# Copyright 2024 Robert Bosch GmbH +# +# SPDX-License-Identifier: SHL-0.51 +# +# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS +# ------------------------------------------------------------------------------ +# locked_outside_tor_test.S (TST16-26, TST16-36) +# ------------------------------------------------------------------------------ + + .text + .globl main +main: + + # From 0x0000_0000 to 0x0000_1000 only Execute. + li t0, 0x00000400 + csrw pmpaddr0, t0 + + # From 0x0000_1000 to 0x0001_0000 no Permissions. + li t0, 0x00004000 + csrw pmpaddr1, t0 + + # From 0x0001_0000 to 0x0002_0000 only Execute. + li t0, 0x00008000 + csrw pmpaddr2, t0 + + # From 0x0002_0000 to 0x8000_0000 no Permissions. + li t0, 0x20000000 + csrw pmpaddr3, t0 + + # From 0x8000_0000 to 0xB000_0000 Read-Write-Execute. + li t0, 0x2C000000 + csrw pmpaddr4, t0 + + # Configure the TOR areas with LOCK ON. + li t0, 0x888c888c + csrw pmpcfg0, t0 + csrr t1, pmpcfg0 + bne t0, t1, fail + li t0, 0x0000008f + csrw pmpcfg1, t0 + csrr t1, pmpcfg1 + bne t0, t1, fail + + # Check a memory access succeeds when outside the LOCKED entry. + li t1, 0xB8000000 + li t2, 0xC0D1F1ED + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + +pass: + # Success post-processing + li a0, 0x0; + jal exit; + +fail: + # Failure post-processing + li a0, 0x1; + jal exit; diff --git a/verif/tests/custom/pmp/lsu_napot_test.S b/verif/tests/custom/pmp/lsu_napot_test.S new file mode 100644 index 00000000000..9a7c97fb4e9 --- /dev/null +++ b/verif/tests/custom/pmp/lsu_napot_test.S @@ -0,0 +1,111 @@ +# ------------------------------------------------------------------------------ +# Copyright 2024 Robert Bosch GmbH +# +# SPDX-License-Identifier: SHL-0.51 +# +# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS +# ------------------------------------------------------------------------------ +# lsu_napot_test.S (TST14-11, TST14-21, TST14-31) +# ------------------------------------------------------------------------------ + + .text + .globl main +main: + + # Configure PMP using NAPOT. + + # From 0x0000_0000 to 0x0000_1000 only Execute. + li t0, 0x000001ff + csrw pmpaddr0, t0 + + # From 0x0001_0000 to 0x0002_0000 only Execute. + li t0, 0x00005fff + csrw pmpaddr1, t0 + + # From 0x8000_0000 to 0xC000_0000 Read-Write-Execute. + li t0, 0x27ffffff + csrw pmpaddr2, t0 + + + # Addr 0-2 configs, written in cfg0, with LOCK OFF, and NAPOT. + li t0, 0x001f1c1c + csrw pmpcfg0, t0 + csrr t1, pmpcfg0 + bne t0, t1, fail + + + # Do the READ-WRITE test. + + # Check 1 read-write test, at 0x8000_0000. + li t1, 0x80000000 + li t2, 0xEFFACED1 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check 2 read-write test, at 0x9000_0000. + li t1, 0x90000000 + li t2, 0xACCEDED2 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check 3 read-write test, at 0xA000_0000. + li t1, 0xA0000000 + li t2, 0xDEFACED3 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check 4 read-write test, at 0xB000_0000. + li t1, 0xB0000000 + li t2, 0xDEC0DED4 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + + # Do the EXEC "RET" test. + + # Exec test 1, at 0x0000_0800. + li t0, 0x00000800 + li t1, 0x8082 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + jalr t0 + + # Exec test 2, at 0x0001_8000. + li t0, 0x00018000 + li t1, 0x8082 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + jalr t0 + + # Exec test 3, at 0x9800_0000. + li t0, 0x98000000 + li t1, 0x8082 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + jalr t0 + + # Exec test 4, at 0xA800_0000. + li t0, 0xA8000000 + li t1, 0x8082 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + jalr t0 + + +pass: + # Success post-processing + li a0, 0x0; + jal exit; + +fail: + # Failure post-processing + li a0, 0x1; + jal exit; diff --git a/verif/tests/custom/pmp/lsu_pipeline_store_no_mmu_test.S b/verif/tests/custom/pmp/lsu_pipeline_store_no_mmu_test.S new file mode 100644 index 00000000000..1fba672ce1a --- /dev/null +++ b/verif/tests/custom/pmp/lsu_pipeline_store_no_mmu_test.S @@ -0,0 +1,8 @@ +// Copyright 2026 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +#define PMP_NO_MMU +#include "lsu_pipeline_store_test.S" diff --git a/verif/tests/custom/pmp/lsu_pipeline_store_test.S b/verif/tests/custom/pmp/lsu_pipeline_store_test.S new file mode 100644 index 00000000000..f6ee2ed8453 --- /dev/null +++ b/verif/tests/custom/pmp/lsu_pipeline_store_test.S @@ -0,0 +1,183 @@ +// Copyright 2026 OpenHW Group +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + + .equ STORE_ACCESS_FAULT, 7 + .equ MSTATUS_MPP, 0x00001800 + .equ MSTATUS_MPRV, 0x00020000 + .equ MSTATUS_MPP_S, 0x00000800 + .equ SATP_MODE_SV39, 0x8000000000000000 + + .equ DENIED_PADDR, 0x90000000 + .equ ALLOWED_PADDR, 0x80000000 + .equ DENIED_VADDR, 0x50000000 + .equ ALLOWED_VADDR, 0x40000000 + .equ INITIAL_VALUE, 0x13579bdf + .equ STORE_VALUE, 0x2468ace0 + + .section .text + .globl main +main: + // Initialize the location before locking its PMP entry. + li t1, DENIED_PADDR + li t2, INITIAL_VALUE + sw t2, 0(t1) + + // Entry 0 allows [0, 0x90000000), entry 1 makes + // [0x90000000, 0x90001000) locked and read-only, and entry 2 allows the + // remainder through 0xc0000000. The surrounding entries allow S-mode + // page-table walks and the load paired with each denied store. + li t0, 0x24000000 + csrw pmpaddr0, t0 + li t0, 0x24000400 + csrw pmpaddr1, t0 + li t0, 0x30000000 + csrw pmpaddr2, t0 + li t0, 0x000f890f + csrw pmpcfg0, t0 + + la t0, trap_count + sw zero, 0(t0) + +#ifdef PMP_NO_MMU + // Exercise the no-MMU response path. + li t0, DENIED_PADDR + call set_expected_tval + li t1, DENIED_PADDR + li t2, STORE_VALUE + li t4, ALLOWED_PADDR + .option push + .option norvc + sw t2, 0(t1) + lw t3, 0(t4) + .option pop + li t0, 1 + call check_result +#else + // Install a one-GiB Sv39 leaf mapping [0x40000000, 0x80000000) to + // [0x80000000, 0xc0000000). DENIED_VADDR therefore translates to the + // PMP-protected DENIED_PADDR. + la t0, root_page_table + srli t0, t0, 12 + li t1, SATP_MODE_SV39 + or t0, t0, t1 + csrw satp, t0 + + // Flush the DTLB so that the denied store itself takes the miss/PTW path. + sfence.vma + li t0, DENIED_VADDR + call set_expected_tval + call enable_s_data_translation + li t1, DENIED_VADDR + li t2, STORE_VALUE + li t4, ALLOWED_VADDR + .option push + .option norvc + sw t2, 0(t1) + lw t3, 0(t4) + .option pop + call disable_data_translation + li t0, 1 + call check_result + + // Refill the DTLB with an allowed read, then repeat the adjacent + // denied-store/allowed-load sequence on the hit path. + sfence.vma + li t0, DENIED_VADDR + call set_expected_tval + call enable_s_data_translation + li t1, DENIED_VADDR + lw t3, 0(t1) + li t2, STORE_VALUE + li t4, ALLOWED_VADDR + .option push + .option norvc + sw t2, 0(t1) + lw t3, 0(t4) + .option pop + call disable_data_translation + li t0, 2 + call check_result +#endif + +pass: + li a0, 0 + tail exit + +fail: + li a0, 1 + tail exit + +set_expected_tval: + la t1, expected_tval + sd t0, 0(t1) + ret + +enable_s_data_translation: + li t0, MSTATUS_MPP | MSTATUS_MPRV + csrc mstatus, t0 + li t0, MSTATUS_MPP_S | MSTATUS_MPRV + csrs mstatus, t0 + ret + +disable_data_translation: + li t0, MSTATUS_MPRV + csrc mstatus, t0 + ret + +check_result: + la t1, trap_count + lw t1, 0(t1) + bne t0, t1, fail + li t1, DENIED_PADDR + lw t1, 0(t1) + li t2, INITIAL_VALUE + bne t1, t2, fail + ret + + .globl handle_trap +handle_trap: + li t0, MSTATUS_MPRV + csrc mstatus, t0 + + li t0, STORE_ACCESS_FAULT + bne a0, t0, trap_fail + + csrr t0, mtval + la t1, expected_tval + ld t1, 0(t1) + bne t0, t1, trap_fail + + la t0, trap_count + lw t1, 0(t0) + addi t1, t1, 1 + sw t1, 0(t0) + + // crt.S writes the returned address to mepc before executing mret. + addi a0, a1, 4 + ret + +trap_fail: + li a0, 1 + tail exit + + .section .data + .align 3 +expected_tval: + .dword 0 +trap_count: + .word 0 + +#ifndef PMP_NO_MMU + // Sv39 root entry 1 is a one-GiB leaf with PPN 0x80000 and V/R/W/X/A/D. + .section .page_table, "aw", @progbits + .balign 4096 +root_page_table: + .dword 0 + .dword 0x00000000200000cf + .rept 510 + .dword 0 + .endr +#endif diff --git a/verif/tests/custom/pmp/lsu_tor_test.S b/verif/tests/custom/pmp/lsu_tor_test.S new file mode 100644 index 00000000000..7989e662394 --- /dev/null +++ b/verif/tests/custom/pmp/lsu_tor_test.S @@ -0,0 +1,125 @@ +# ------------------------------------------------------------------------------ +# Copyright 2024 Robert Bosch GmbH +# +# SPDX-License-Identifier: SHL-0.51 +# +# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS +# ------------------------------------------------------------------------------ +# lsu_tor_test.S (TST16-11, TST16-21, TST16-31) +# ------------------------------------------------------------------------------ + + .text + .globl main +main: + + # Configure PMP using TOR. + + # From 0x0000_0000 to 0x0000_1000 only Execute. + li t0, 0x00000400 + csrw pmpaddr0, t0 + + # From 0x0000_1000 to 0x0001_0000 no Permissions. + li t0, 0x00004000 + csrw pmpaddr1, t0 + + # From 0x0001_0000 to 0x0002_0000 only Execute. + li t0, 0x00008000 + csrw pmpaddr2, t0 + + # From 0x0002_0000 to 0x8000_0000 no Permissions. + li t0, 0x20000000 + csrw pmpaddr3, t0 + + # From 0x8000_0000 to 0xC000_0000 Read-Write-Execute. + li t0, 0x30000000 + csrw pmpaddr4, t0 + + + # Addr 0-3 configs, written in cfg0, with LOCK OFF, and TOR. + li t0, 0x080c080c + csrw pmpcfg0, t0 + csrr t1, pmpcfg0 + bne t0, t1, fail + + # Addr 4 config, written in cfg1, with LOCK OFF, and TOR. + li t0, 0x0000000f + csrw pmpcfg1, t0 + csrr t1, pmpcfg1 + bne t0, t1, fail + + + # Do the READ-WRITE test. + + # Check 1 read-write test, at 0x8000_0000. + li t1, 0x80000000 + li t2, 0xEFFACED1 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check 2 read-write test, at 0x9000_0000. + li t1, 0x90000000 + li t2, 0xACCEDED2 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check 3 read-write test, at 0xA000_0000. + li t1, 0xA0000000 + li t2, 0xDEFACED3 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + # Check 4 read-write test, at 0xB000_0000. + li t1, 0xB0000000 + li t2, 0xDEC0DED4 + sw t2, 0(t1) + lw t3, 0(t1) + bne t2, t3, fail + + + # Do the EXEC "RET" test. + + # Exec test 1, at 0x0000_0800. + li t0, 0xA0000800 + li t1, 0x8082 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + jalr t0 + + # Exec test 2, at 0x0001_8000. + li t0, 0xB0018000 + li t1, 0x8082 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + jalr t0 + + # Exec test 3, at 0x9800_0000. + li t0, 0x98000000 + li t1, 0x8082 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + jalr t0 + + # Exec test 4, at 0xA800_0000. + li t0, 0xA8000000 + li t1, 0x8082 + sw t1, 0(t0) + lw t2, 0(t0) + bne t1, t2, fail + jalr t0 + + +pass: + # Success post-processing + li a0, 0x0; + jal exit; + +fail: + # Failure post-processing + li a0, 0x1; + jal exit; diff --git a/verif/tests/custom/sv32/vm_access_bit_level_0.S b/verif/tests/custom/sv32/vm_access_bit_level_0.S index 33b23aee17c..5cf565c6884 100644 --- a/verif/tests/custom/sv32/vm_access_bit_level_0.S +++ b/verif/tests/custom/sv32/vm_access_bit_level_0.S @@ -8,7 +8,7 @@ # and PTE has pte.A=0, then accessing it would raise page fault # exception of the corresponding access type. # -# - Set pte.r=1 & pte.a=0 and test the read acces. +# - Set pte.r=1 & pte.a=0 and test the read access. # - Set pte.w=1 & pte.a=0 and test the write access. # - Set pte.x=1 & pte.a=0 and test the execute access. # diff --git a/verif/tests/custom/sv32/vm_access_bit_level_1.S b/verif/tests/custom/sv32/vm_access_bit_level_1.S index 048b0276454..64a4e6b7ab7 100644 --- a/verif/tests/custom/sv32/vm_access_bit_level_1.S +++ b/verif/tests/custom/sv32/vm_access_bit_level_1.S @@ -8,7 +8,7 @@ # and PTE has pte.A=0, then accessing it would raise page fault # exception of the corresponding access type. # -# - Set pte.r=1 & pte.a=0 and test the read acces. +# - Set pte.r=1 & pte.a=0 and test the read access. # - Set pte.w=1 & pte.a=0 and test the write access. # - Set pte.x=1 & pte.a=0 and test the execute access. # diff --git a/verif/tests/custom/sv32/vm_mxr_clear_level_0.S b/verif/tests/custom/sv32/vm_mxr_clear_level_0.S index d78caff8abc..76656534e7e 100644 --- a/verif/tests/custom/sv32/vm_mxr_clear_level_0.S +++ b/verif/tests/custom/sv32/vm_mxr_clear_level_0.S @@ -8,7 +8,7 @@ # then read access on that PTE should raise load page fault exception. # # - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=0 and test the -# read acces. +# read access. # #======================================================================= diff --git a/verif/tests/custom/sv32/vm_mxr_clear_level_1.S b/verif/tests/custom/sv32/vm_mxr_clear_level_1.S index 93a41ab5bd0..da50e8d223d 100644 --- a/verif/tests/custom/sv32/vm_mxr_clear_level_1.S +++ b/verif/tests/custom/sv32/vm_mxr_clear_level_1.S @@ -8,7 +8,7 @@ # then read access on that PTE should raise load page fault exception. # # - Set pte.r=0 & pte.w=0 & pte.x=1 & s/mstatus.MXR=0 and test the -# read acces. +# read access. # #======================================================================= diff --git a/verif/tests/custom/sv32/vm_pmp_check_level_0.S b/verif/tests/custom/sv32/vm_pmp_check_level_0.S index 84de67468e4..f8311f0f59c 100644 --- a/verif/tests/custom/sv32/vm_pmp_check_level_0.S +++ b/verif/tests/custom/sv32/vm_pmp_check_level_0.S @@ -10,7 +10,7 @@ # raise access fault exception. # # - Remove read PMP permission of translated Physical Address in pmpcfg -# and test the read acces. +# and test the read access. # - Remvoe write PMP permission of translated Physical Address in pmpcfg # and test the write access. # - Remove execute PMP permission of translated Physical Address in diff --git a/verif/tests/custom/sv32/vm_pmp_check_level_1.S b/verif/tests/custom/sv32/vm_pmp_check_level_1.S index 5ff2915e03f..9c55281047c 100644 --- a/verif/tests/custom/sv32/vm_pmp_check_level_1.S +++ b/verif/tests/custom/sv32/vm_pmp_check_level_1.S @@ -10,7 +10,7 @@ # raise access fault exception. # # - Remove read PMP permission of translated Physical Address in pmpcfg -# and test the read acces. +# and test the read access. # - Remvoe write PMP permission of translated Physical Address in pmpcfg # and test the write access. # - Remove execute PMP permission of translated Physical Address in diff --git a/verif/tests/custom/sv32/vm_sum_clear_level_0.S b/verif/tests/custom/sv32/vm_sum_clear_level_0.S index 9d5e87cb830..8b7c109e288 100644 --- a/verif/tests/custom/sv32/vm_sum_clear_level_0.S +++ b/verif/tests/custom/sv32/vm_sum_clear_level_0.S @@ -8,7 +8,7 @@ # supervisor mode would raise page fault exception of the # corresponding access type. # -# - Set pte.u=1 & s/mstatus.SUM = 0 and test the read acces. +# - Set pte.u=1 & s/mstatus.SUM = 0 and test the read access. # - Set pte.u=1 & s/mstatus.SUM = 0 and test the write access. # - Set pte.u=1 & s/mstatus.SUM = 0 and test the execute access. # diff --git a/verif/tests/custom/sv32/vm_sum_clear_level_1.S b/verif/tests/custom/sv32/vm_sum_clear_level_1.S index 5ffde1f9c33..3ff1061de69 100644 --- a/verif/tests/custom/sv32/vm_sum_clear_level_1.S +++ b/verif/tests/custom/sv32/vm_sum_clear_level_1.S @@ -8,7 +8,7 @@ # supervisor mode would raise page fault exception of the # corresponding access type. # -# - Set pte.u=1 & s/mstatus.SUM = 0 and test the read acces. +# - Set pte.u=1 & s/mstatus.SUM = 0 and test the read access. # - Set pte.u=1 & s/mstatus.SUM = 0 and test the write access. # - Set pte.u=1 & s/mstatus.SUM = 0 and test the execute access. # diff --git a/verif/tests/custom/sv32/vm_sum_set_level_0.S b/verif/tests/custom/sv32/vm_sum_set_level_0.S index 4b30fe81818..e782b36e7d0 100644 --- a/verif/tests/custom/sv32/vm_sum_set_level_0.S +++ b/verif/tests/custom/sv32/vm_sum_set_level_0.S @@ -11,7 +11,7 @@ # When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX # encoding, and pte.v=1, then test the following in supervisor mode for level0 PTE. # -# - Set pte.r=1 & pte.u=1 & s/mstatus.SUM = 1 and test the read acces. +# - Set pte.r=1 & pte.u=1 & s/mstatus.SUM = 1 and test the read access. # - Set pte.w=1 & pte.u=1 & s/mstatus.SUM = 1 and test the write access. # - Set pte.x=1 & pte.u=1 & s/mstatus.SUM = 1 and test the execute access. # diff --git a/verif/tests/custom/sv32/vm_sum_set_level_1.S b/verif/tests/custom/sv32/vm_sum_set_level_1.S index e28100643a5..f565d310b4e 100644 --- a/verif/tests/custom/sv32/vm_sum_set_level_1.S +++ b/verif/tests/custom/sv32/vm_sum_set_level_1.S @@ -11,7 +11,7 @@ # When satp.mode=sv32, PTE has (r,w,x) PMP permissions, PTE has non-reserved RWX # encoding, and pte.v=1, then test the following in supervisor mode for level1 PTE. # -# - Set pte.r=1 & pte.u=1 & s/mstatus.SUM = 1 and test the read acces. +# - Set pte.r=1 & pte.u=1 & s/mstatus.SUM = 1 and test the read access. # - Set pte.w=1 & pte.u=1 & s/mstatus.SUM = 1 and test the write access. # - Set pte.x=1 & pte.u=1 & s/mstatus.SUM = 1 and test the execute access. # diff --git a/verif/tests/custom/sv39/noncanonical.S b/verif/tests/custom/sv39/noncanonical.S new file mode 100644 index 00000000000..1c100a8ea01 --- /dev/null +++ b/verif/tests/custom/sv39/noncanonical.S @@ -0,0 +1,141 @@ +# See LICENSE for license details. + +#***************************************************************************** +# noncanonical.S +#----------------------------------------------------------------------------- +# +# Test that non-canonical SV39 virtual addresses generate page-fault +# exceptions. In SV39, bits [63:39] of a virtual address must all equal +# bit [38]. When they do not, the hardware must raise: +# +# - LOAD_PAGE_FAULT (mcause 13) for loads, +# - STORE_PAGE_FAULT (mcause 15) for stores, +# - FETCH_PAGE_FAULT (mcause 12) for instruction fetches. +# +# See: https://github.com/openhwgroup/cva6/issues/371 +# + +#include "riscv_test.h" +#include "test_macros.h" + +#if (DRAM_BASE >> 30 << 30) != DRAM_BASE +# error This test requires DRAM_BASE be SV39 superpage-aligned +#endif + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # ------------------------------------------------------------------ + # Set up SV39 with a 1 GiB identity-mapped superpage at DRAM_BASE. + # The page table entry has full permissions so that only the + # non-canonical address check can cause a fault. + # ------------------------------------------------------------------ + li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39 + la a1, page_table_1 + srl a1, a1, RISCV_PGSHIFT + or a1, a1, a0 + csrw satp, a1 + sfence.vma + + # Build a non-canonical virtual address: 0x0000_0080_0000_0000. + # Bit 39 = 1, bit 38 = 0 -> bits [63:39] != bit [38]. + li s1, 1 + slli s1, s1, 39 + + # ================================================================== + # Test 2 -- Load from non-canonical address (expect LOAD_PAGE_FAULT) + # ================================================================== + li TESTNUM, 2 + + # Enable S-mode address translation for loads/stores while staying + # in M-mode, by setting MPRV=1 and MPP=S. + li t0, MSTATUS_MPP | MSTATUS_MPRV + csrc mstatus, t0 + li t0, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV + csrs mstatus, t0 + + lb t0, 0(s1) + j fail # should not be reached + + # ================================================================== + # Test 3 -- Store to non-canonical address (expect STORE_PAGE_FAULT) + # ================================================================== +test_3: + li TESTNUM, 3 + + sb t0, 0(s1) + j fail # should not be reached + + # ================================================================== + # Test 4 -- Fetch from non-canonical address (expect FETCH_PAGE_FAULT) + # ================================================================== +test_4: + li TESTNUM, 4 + + # Clear MPRV so subsequent instructions use M-mode for data access. + li t0, MSTATUS_MPRV + csrc mstatus, t0 + + # Prepare to enter S-mode via mret: set MPP = S. + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t0, (MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S + csrs mstatus, t0 + + # Set the return address to the non-canonical address and mret. + # The CPU will attempt an instruction fetch from s1 in S-mode + # with SV39 translation active, triggering FETCH_PAGE_FAULT. + csrw mepc, s1 + mret + # (control never reaches here -- the fetch itself faults) + + TEST_PASSFAIL + + # ------------------------------------------------------------------ + # M-mode trap handler + # ------------------------------------------------------------------ + .align 2 + .global mtvec_handler +mtvec_handler: + csrr t0, mcause + + # --- Test 2: expect LOAD_PAGE_FAULT --- + li t1, 2 + bne TESTNUM, t1, 1f + li t1, CAUSE_LOAD_PAGE_FAULT + bne t0, t1, fail + + # Re-establish MPRV + MPP=S for the store test and jump to test_3. + li t0, MSTATUS_MPP | MSTATUS_MPRV + csrc mstatus, t0 + li t0, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV + csrs mstatus, t0 + j test_3 + +1: + # --- Test 3: expect STORE_PAGE_FAULT --- + li t1, 3 + bne TESTNUM, t1, 1f + li t1, CAUSE_STORE_PAGE_FAULT + bne t0, t1, fail + j test_4 + +1: + # --- Test 4: expect FETCH_PAGE_FAULT --- + li t1, 4 + bne TESTNUM, t1, fail + li t1, CAUSE_FETCH_PAGE_FAULT + bne t0, t1, fail + j pass + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +.align 12 +page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D + +RVTEST_DATA_END diff --git a/verif/tests/custom/trigger_tests/etrigger_test.S b/verif/tests/custom/trigger_tests/etrigger_test.S new file mode 100644 index 00000000000..0ec024f84f5 --- /dev/null +++ b/verif/tests/custom/trigger_tests/etrigger_test.S @@ -0,0 +1,51 @@ +.section .text +.globl _start +_start: + la t0, trap_handler + csrw mtvec, t0 + + li t1, 0x8 + csrs mstatus, t1 + + li x2, 1 + csrw tselect, x2 + + li x3, 0x00000008 # match value for ebreak loaded here + csrw tdata2, x3 + + li x4, 0x50000201 # match exception value with tdata2 and enter debug mode + csrw tdata1, x4 + + # dummy instructions + csrr x5, tdata1 + nop + nop + nop + ebreak // match here + nop + nop + nop + nop + nop + +exit: + li a1, 1 + la t2, tohost + sw a1, 0(t2) + j exit + +trap_handler: + csrr t3, mcause + csrr t4, mepc + + addi t4, t4, 4 + csrw mepc, t4 + + mret + +.data +.align 4 +.global tohost +tohost: .word 0 +.global fromhost +fromhost: .word 0 diff --git a/verif/tests/custom/trigger_tests/icount_break_test.S b/verif/tests/custom/trigger_tests/icount_break_test.S new file mode 100644 index 00000000000..fffb64cc635 --- /dev/null +++ b/verif/tests/custom/trigger_tests/icount_break_test.S @@ -0,0 +1,63 @@ +.text +.globl _start +_start: + # Ensure DebugEn is disabled when using action 0 i.e. breakpoint action + la t0, trap_handler + csrw mtvec, t0 + + li t1, 0x8 + csrs mstatus, t1 + + li x2, 0 + csrw tselect, x2 + + + li x2, 0x30003e00 # count 15 instructions and go into breakpoint exception + nop + nop + nop + csrw tdata1, x2 + + # dummy instructions to count + csrr x7, tdata1 + csrr x7, tdata1 + csrr x7, tdata1 + csrr x7, tdata1 + li x3, 1 + nop + nop + nop + li x4, 2 + nop + nop + nop + li x5, 3 + nop + nop + nop + li x2, 0 + nop + li x2, 1 + li x2, 2 + +exit: + li a1, 1 + la t2, tohost + sw a1, 0(t2) + j exit + +trap_handler: + csrr t3, mcause + csrr t4, mepc + + addi t4, t4, 4 + csrw mepc, t4 + + mret + +.data +.align 4 +.global tohost +tohost: .word 0 +.global fromhost +fromhost: .word 0 diff --git a/verif/tests/custom/trigger_tests/icount_debug_test.S b/verif/tests/custom/trigger_tests/icount_debug_test.S new file mode 100644 index 00000000000..65ac846ffc6 --- /dev/null +++ b/verif/tests/custom/trigger_tests/icount_debug_test.S @@ -0,0 +1,47 @@ +.text +.globl _start +_start: + li x2, 0 + csrw tselect, x2 + + + li x2, 0x30003e01 # count 15 instructions and enter debug mode + nop + nop + nop + csrw tdata1, x2 + + # dummy instructions to count + csrr x7, tdata1 + csrr x7, tdata1 + csrr x7, tdata1 + csrr x7, tdata1 + li x3, 1 + nop + nop + nop + li x4, 2 + nop + nop + nop + li x5, 3 + nop + nop + nop + li x2, 0 + nop + li x2, 1 + li x2, 2 + +exit: + li a1, 1 + la t2, tohost + sw a1, 0(t2) + j exit + +.data +.align 4 +.global tohost +tohost: .word 0 +.global fromhost +fromhost: .word 0 diff --git a/verif/tests/custom/trigger_tests/itrigger_test.S b/verif/tests/custom/trigger_tests/itrigger_test.S new file mode 100644 index 00000000000..ad3813eb8e6 --- /dev/null +++ b/verif/tests/custom/trigger_tests/itrigger_test.S @@ -0,0 +1,58 @@ +.section .text +.globl _start +_start: + # For emulating a software interrupt + la t0, trap_handler + csrw mtvec, t0 + + li t1, 0x8 + csrs mie, t1 + csrs mstatus, t1 + + # Trigger setup + li x2, 1 + csrw tselect, x2 + + li x3, 0x00000008 # match on software interrupt + csrw tdata2, x3 + + li x4, 0x40000201 # match on software interrupt and enter debug mode + csrw tdata1, x4 + csrr x5, tdata1 + + # For emulating a software interrupt + li t2, 0x02000000 # msip (clint) base address + li t3, 1 + sw t3, 0(t2) + fence + wfi + nop + nop + nop + nop + nop + nop + +exit: + li a1, 1 + la t2, tohost + sw a1, 0(t2) + j exit + +trap_handler: + # For emulating a software interrupt + csrr a0, mcause + csrr a1, mepc + + li t0, 0x02000000 + sw zero, 0(t0) # clear MSIP (for software interrupt) + fence + + mret + +.data +.align 4 +.global tohost +tohost: .word 0 +.global fromhost +fromhost: .word 0 diff --git a/verif/tests/custom/trigger_tests/mcontrol6_tests.S b/verif/tests/custom/trigger_tests/mcontrol6_tests.S new file mode 100644 index 00000000000..fd71722e35e --- /dev/null +++ b/verif/tests/custom/trigger_tests/mcontrol6_tests.S @@ -0,0 +1,85 @@ +.text +.globl _start +_start: + # Mcontrol6 trigger only supports action = 1 i.e. enter debug mode + li x2, 0 + csrw tselect, x2 + + li x5, 0x80003000 ## test address for matching + li x6, 0x12345678 ## test data for matching + + li x3, 0x12345678 # match value loaded here + csrw tdata2, x3 + + ## Trigger Configuration + ## Test 1): store with data match + li x4, 0x60201042 + csrw tdata1, x4 + nop + nop + nop + nop + sw x6, 0(x5) + + ##Test 2): load with data match + # li x4, 0x60201041 + # csrw tdata1, x4 + # nop + # nop + # nop + # nop + # nop + # lw x7, 0(x5) + + ## Test 3): store with address match + # li x4, 0x60001042 + # csrw tdata1, x4 + # sw x6, 4(x5) + # nop + # nop + # nop + + ## Test 4): load with address match + # li x4, 0x60001041 + # csrw tdata1, x4 + # lw x7, 4(x5) + # nop + # nop + # nop + + ## Test 5): execute with instruction match + # li x4, 0x60201044 + # csrw tdata1, x4 + # add x8, x2, x3 + # nop + # nop + + # # Test 6): execute with address match + # li x4, 0x60001044 + # csrw tdata1, x4 + # csrr x7, tdata1 + # nop + # nop + # nop + # nop + # nop + # nop + + nop + nop + nop + nop + nop + +exit: + li x1, 1 + la t0, tohost + sw x1, 0(t0) + j exit + +.data +.align 4 +.global tohost +tohost: .word 0 +.global fromhost +fromhost: .word 0 \ No newline at end of file diff --git a/verif/tests/custom/trigger_tests/sdtrig_action_legal.S b/verif/tests/custom/trigger_tests/sdtrig_action_legal.S new file mode 100644 index 00000000000..bb6eb1f784a --- /dev/null +++ b/verif/tests/custom/trigger_tests/sdtrig_action_legal.S @@ -0,0 +1,76 @@ +// Copyright 2026 10x Engineers +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Issue #3622: tdata1 never holds dmode=0 with action=1. +// A write from M-mode cannot set dmode. Thus action=1 becomes action=0. + +#include "sdtrig_test.h" + +#define WRITE_READ_CHECK(wval, rval, n) \ + li t0, wval; \ + csrw tdata1, t0; \ + csrr t1, tdata1; \ + li t2, rval; \ + CHECK_EQ(t1, t2, n) + + .option norvc + .section .text.init + .global _start +_start: + la t0, trap_handler + csrw mtvec, t0 + // MIE=1 lets a breakpoint fire in M-mode on harts that use the MIE + // reentrancy rule. No interrupt is enabled in mie. + csrsi mstatus, MSTATUS_MIE + csrw tselect, zero + + // 1. mcontrol6 with dmode=1 and action=1 + WRITE_READ_CHECK(TDATA1_TYPE(TYPE_MCONTROL6) | TDATA1_DMODE | MC6_ACTION(1) | MC6_M | MC6_EXECUTE, + TDATA1_TYPE(TYPE_MCONTROL6) | MC6_M | MC6_EXECUTE, 1) + // 2. mcontrol6 with dmode=0 and action=1 + WRITE_READ_CHECK(TDATA1_TYPE(TYPE_MCONTROL6) | MC6_ACTION(1) | MC6_M | MC6_EXECUTE, + TDATA1_TYPE(TYPE_MCONTROL6) | MC6_M | MC6_EXECUTE, 2) + // 3. icount with dmode=1 and action=1 + WRITE_READ_CHECK(TDATA1_TYPE(TYPE_ICOUNT) | TDATA1_DMODE | ICOUNT_COUNT(5) | ICOUNT_U | ACTION(1), + TDATA1_TYPE(TYPE_ICOUNT) | ICOUNT_COUNT(5) | ICOUNT_U, 3) + // 4. etrigger with dmode=0 and action=1 + WRITE_READ_CHECK(TDATA1_TYPE(TYPE_ETRIGGER) | XTRIG_U | ACTION(1), + TDATA1_TYPE(TYPE_ETRIGGER) | XTRIG_U, 4) + // 5. itrigger with dmode=1 and action=1 + WRITE_READ_CHECK(TDATA1_TYPE(TYPE_ITRIGGER) | TDATA1_DMODE | XTRIG_U | ACTION(1), + TDATA1_TYPE(TYPE_ITRIGGER) | XTRIG_U, 5) + + // 6. An execute trigger written with action=1 from M-mode gives a + // breakpoint exception on "target". It does not enter Debug Mode. + la t0, target + csrw tdata2, t0 + li t0, TDATA1_TYPE(TYPE_MCONTROL6) | MC6_ACTION(1) | MC6_M | MC6_EXECUTE + csrw tdata1, t0 + li s0, 0 +target: + nop + // The trap handler sets s0 to 1. + li t2, 1 + CHECK_EQ(s0, t2, 6) + j test_pass + + .align 4 +trap_handler: + // Disable the trigger, then do the checks of the trap. + csrw tdata1, zero + csrr t1, mcause + li t2, CAUSE_BREAKPOINT + CHECK_EQ(t1, t2, 7) + csrr t1, mepc + la t2, target + CHECK_EQ(t1, t2, 8) + li s0, 1 + mret + +TEST_PASS_FAIL + +TEST_DATA diff --git a/verif/tests/custom/trigger_tests/sdtrig_etrigger.S b/verif/tests/custom/trigger_tests/sdtrig_etrigger.S new file mode 100644 index 00000000000..ca03d464009 --- /dev/null +++ b/verif/tests/custom/trigger_tests/sdtrig_etrigger.S @@ -0,0 +1,139 @@ +// Copyright 2026 10x Engineers +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Issue #3620: an etrigger fires only after an exception trap. +// It does not fire when no trap occurs. It does not fire on an interrupt. + +#include "sdtrig_test.h" + + .option norvc + .section .text.init + .global _start +_start: + la t0, m_handler + csrw mtvec, t0 + la t0, s_handler + csrw stvec, t0 + csrw medeleg, zero + csrw mideleg, zero + csrw satp, zero + PMP_ALLOW_ALL + li s1, 0 // number of M-mode traps + + // 1. Exception code 0 is selected. No trap occurs. The trigger does not fire. + csrw tselect, zero + li t0, 1 + csrw tdata2, t0 + li t0, TDATA1_TYPE(TYPE_ETRIGGER) | XTRIG_M + csrw tdata1, t0 + .rept 20 + nop + .endr + CHECK_EQ(s1, zero, 1) + + // 2. Exception code 7 is selected. A machine timer interrupt (code 7) + // occurs. The trigger does not fire. + li t0, 1 << 7 + csrw tdata2, t0 + li t0, CLINT_MTIMECMP + sw zero, 0(t0) + sw zero, 4(t0) + li t0, MIP_MTIP + csrw mie, t0 + csrsi mstatus, MSTATUS_MIE + li t3, 200 +1: + addi t3, t3, -1 + bnez t3, 1b + csrci mstatus, MSTATUS_MIE + csrw mie, zero + // One trap only: the interrupt. + li t2, 1 + CHECK_EQ(s1, t2, 2) + li t2, MCAUSE_INT | 7 + CHECK_EQ(s2, t2, 3) + + // 3. Exception code 2 is selected for U-mode. An illegal instruction in + // U-mode traps to S-mode. The trigger fires just before the first + // instruction of the S-mode handler. The breakpoint goes to M-mode. + li s1, 0 + li s3, 0 // 0: part 3, 1: part 4 + li t0, 1 << CAUSE_ILLEGAL + csrw tdata2, t0 + li t0, TDATA1_TYPE(TYPE_ETRIGGER) | XTRIG_U + csrw tdata1, t0 + li t0, 1 << CAUSE_ILLEGAL + csrw medeleg, t0 + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + la t0, u_code + csrw mepc, t0 + mret + +u_code: + .word 0 // illegal instruction + li a0, 4 + j test_fail + +s_code: + .word 0 // illegal instruction + li a0, 11 + j test_fail + + .align 4 +s_handler: + li a0, 5 + j test_fail + + .align 4 +m_handler: + addi s1, s1, 1 + csrr s2, mcause + bltz s2, m_interrupt + csrw tdata1, zero + li t2, CAUSE_BREAKPOINT + CHECK_EQ(s2, t2, 6) + csrr t1, mepc + la t2, s_handler + CHECK_EQ(t1, t2, 7) + csrr t1, mtval + CHECK_EQ(t1, zero, 10) + csrr t1, scause + li t2, CAUSE_ILLEGAL + CHECK_EQ(t1, t2, 8) + csrr t1, sepc + la t2, u_code + beqz s3, 1f + la t2, s_code +1: + CHECK_EQ(t1, t2, 9) + bnez s3, test_pass + + // 4. Exception code 2 is selected for S-mode. An illegal instruction in + // S-mode traps to S-mode. The trigger fires just before the first + // instruction of the S-mode handler. The breakpoint goes to M-mode. + li s3, 1 + li t0, TDATA1_TYPE(TYPE_ETRIGGER) | XTRIG_S + csrw tdata1, t0 + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + li t0, MSTATUS_MPP_S + csrs mstatus, t0 + la t0, s_code + csrw mepc, t0 + mret + +m_interrupt: + li t0, CLINT_MTIMECMP + li t1, -1 + sw t1, 0(t0) + sw t1, 4(t0) + mret + +TEST_PASS_FAIL + +TEST_DATA diff --git a/verif/tests/custom/trigger_tests/sdtrig_icount_fire.S b/verif/tests/custom/trigger_tests/sdtrig_icount_fire.S new file mode 100644 index 00000000000..3399bc030c3 --- /dev/null +++ b/verif/tests/custom/trigger_tests/sdtrig_icount_fire.S @@ -0,0 +1,89 @@ +// Copyright 2026 10x Engineers +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Issue #3647: icount fires on the next instruction to execute. mepc holds +// the address of this instruction. A trigger with count=0 does not fire. + +#include "sdtrig_test.h" + + .option norvc + .section .text.init + .global _start +_start: + la t0, m_handler + csrw mtvec, t0 + // MIE=1 lets a breakpoint fire in M-mode on harts that use the MIE + // reentrancy rule. No interrupt is enabled in mie. + csrsi mstatus, MSTATUS_MIE + li s0, 0x80 + csrw tselect, zero + li s1, 0 // test phase + la s5, scratch + + // 1. count=0. The trigger does not fire. + li t0, TDATA1_TYPE(TYPE_ICOUNT) | ICOUNT_COUNT(0) | ICOUNT_M + csrw tdata1, t0 + .rept 20 + nop + .endr + csrw tdata1, zero + + // 2. count=1. The write to tdata1 does not count. The csrr counts. + // The trigger fires before the store. + li s1, 2 + li t0, TDATA1_TYPE(TYPE_ICOUNT) | ICOUNT_COUNT(1) | ICOUNT_M + csrw tdata1, t0 + csrr t1, mstatus +p2_fire: + SREG t1, 0(s5) + li a0, 1 + j test_fail + +phase3: + // 3. count=2. The trigger fires before the second addi. + li s1, 3 + li t0, TDATA1_TYPE(TYPE_ICOUNT) | ICOUNT_COUNT(2) | ICOUNT_M + csrw tdata1, t0 + csrr t1, mstatus + addi s4, s4, 1 +p3_fire: + addi s4, s4, 1 + li a0, 2 + j test_fail + + .align 4 +m_handler: + csrr s2, mcause + csrr s3, mepc + csrr s6, mtval + csrw tdata1, zero + li t2, CAUSE_BREAKPOINT + CHECK_EQ(s2, t2, 3) + CHECK_EQ(s6, zero, 4) + li t2, 2 + bne s1, t2, m_phase3 + la t2, p2_fire + CHECK_EQ(s3, t2, 5) + la t0, phase3 + csrw mepc, t0 + mret + +m_phase3: + li t2, 3 + CHECK_EQ(s1, t2, 6) + la t2, p3_fire + CHECK_EQ(s3, t2, 7) + j test_pass + +TEST_PASS_FAIL + + .data + .align 3 +scratch: + .dword 0 + +TEST_DATA diff --git a/verif/tests/custom/trigger_tests/sdtrig_icount_modes.S b/verif/tests/custom/trigger_tests/sdtrig_icount_modes.S new file mode 100644 index 00000000000..9f538124ea5 --- /dev/null +++ b/verif/tests/custom/trigger_tests/sdtrig_icount_modes.S @@ -0,0 +1,149 @@ +// Copyright 2026 10x Engineers +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Issue #3619: icount counts only the instructions and the traps of the +// privilege modes where the trigger is enabled. + +#include "sdtrig_test.h" + + .option norvc + .section .text.init + .global _start +_start: + la t0, m_handler + csrw mtvec, t0 + csrw medeleg, zero + csrw mideleg, zero + csrw satp, zero + PMP_ALLOW_ALL + li s1, 0 // test phase + csrw tselect, zero + + // 1. count=3, u=1. The M-mode instructions and the mret do not count. + // The trigger fires before the fourth U-mode instruction. + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + la t0, u1_code + csrw mepc, t0 + li t0, TDATA1_TYPE(TYPE_ICOUNT) | ICOUNT_COUNT(3) | ICOUNT_U + csrw tdata1, t0 + addi x0, x0, 1 + addi x0, x0, 1 + addi x0, x0, 1 + mret +u1_code: + addi s4, s4, 1 + addi s4, s4, 1 + addi s4, s4, 1 +u1_fire: + addi s4, s4, 1 + li a0, 1 + j test_fail + +phase2: + // 2. count=2, u=1. One U-mode instruction and the ecall trap from U-mode + // count. The M-mode handler does not count. The trigger fires before + // the next U-mode instruction. + li s1, 2 + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + la t0, u2_code + csrw mepc, t0 + li t0, TDATA1_TYPE(TYPE_ICOUNT) | ICOUNT_COUNT(2) | ICOUNT_U + csrw tdata1, t0 + mret +u2_code: + addi s4, s4, 1 + ecall +u2_fire: + addi s4, s4, 1 + li a0, 2 + j test_fail + +phase3: + // 3. count=3, s=1. An illegal instruction in S-mode traps to S-mode. The + // trap and the instructions of the S-mode handler count. The trigger + // fires before the third instruction of the handler. The breakpoint goes + // to M-mode. + li s1, 3 + la t0, s_handler + csrw stvec, t0 + li t0, 1 << CAUSE_ILLEGAL + csrw medeleg, t0 + li t0, TDATA1_TYPE(TYPE_ICOUNT) | ICOUNT_COUNT(3) | ICOUNT_S + csrw tdata1, t0 + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + li t0, MSTATUS_MPP_S + csrs mstatus, t0 + la t0, s3_code + csrw mepc, t0 + mret +s3_code: + .word 0 // illegal instruction + li a0, 3 + j test_fail + + .align 4 +s_handler: + csrr s2, scause + csrr s3, sepc +s_handler_3: + li a0, 10 // the trigger did not fire in the handler + j test_fail + + .align 4 +m_handler: + csrr s2, mcause + csrr s3, mepc + li t2, 3 + beq s1, t2, m_phase3 + li t2, CAUSE_ECALL_U + beq s2, t2, m_ecall_u + csrw tdata1, zero + li t2, CAUSE_BREAKPOINT + CHECK_EQ(s2, t2, 4) + csrr t1, mtval + CHECK_EQ(t1, zero, 5) + bnez s1, m_phase2 + + // Phase 1 + la t2, u1_fire + CHECK_EQ(s3, t2, 6) + li t0, MSTATUS_MPP_MASK + csrs mstatus, t0 + la t0, phase2 + csrw mepc, t0 + mret + +m_ecall_u: + // Phase 2: the ecall. Go back to U-mode after the ecall. + addi s3, s3, 4 + csrw mepc, s3 + mret + +m_phase2: + la t2, u2_fire + CHECK_EQ(s3, t2, 7) + li t0, MSTATUS_MPP_MASK + csrs mstatus, t0 + la t0, phase3 + csrw mepc, t0 + mret + +m_phase3: + // The trigger fires before s_handler_3 + csrw tdata1, zero + li t2, CAUSE_BREAKPOINT + CHECK_EQ(s2, t2, 8) + la t2, s_handler_3 + CHECK_EQ(s3, t2, 9) + j test_pass + +TEST_PASS_FAIL + +TEST_DATA diff --git a/verif/tests/custom/trigger_tests/sdtrig_itrigger.S b/verif/tests/custom/trigger_tests/sdtrig_itrigger.S new file mode 100644 index 00000000000..35a5a309286 --- /dev/null +++ b/verif/tests/custom/trigger_tests/sdtrig_itrigger.S @@ -0,0 +1,100 @@ +// Copyright 2026 10x Engineers +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Issue #3646: an itrigger fires after the interrupt trap, just before the +// first instruction of the trap handler. The breakpoint writes 0 to tval. + +#include "sdtrig_test.h" + + .option norvc + .section .text.init + .global _start +_start: + la t0, m_handler + csrw mtvec, t0 + la t0, s_handler + csrw stvec, t0 + csrw medeleg, zero + csrw satp, zero + PMP_ALLOW_ALL + li s1, 0 // test phase + + // 1. Interrupt 1 (supervisor software) is selected for U-mode. The + // interrupt is delegated to S-mode. The trigger fires just before the + // first instruction of the S-mode handler. The breakpoint goes to M-mode. + csrw tselect, zero + li t0, 1 << 1 + csrw tdata2, t0 + li t0, TDATA1_TYPE(TYPE_ITRIGGER) | XTRIG_U + csrw tdata1, t0 + li t0, MIP_SSIP + csrw mideleg, t0 + csrw mie, t0 + csrs mip, t0 + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + la t0, u_code + csrw mepc, t0 + mret + +u_code: + nop + li a0, 1 + j test_fail + +s_code: + nop + li a0, 9 + j test_fail + + .align 4 +s_handler: + li a0, 2 + j test_fail + + .align 4 +m_handler: + csrr s2, mcause + csrr s3, mepc + csrr s4, mtval + csrw tdata1, zero + li t2, CAUSE_BREAKPOINT + CHECK_EQ(s2, t2, 4) + CHECK_EQ(s4, zero, 5) + + // Phase 1 and 1b: the breakpoint is on the first instruction of the S-mode handler. + la t2, s_handler + CHECK_EQ(s3, t2, 6) + csrr t1, scause + li t2, MCAUSE_INT | 1 + CHECK_EQ(t1, t2, 7) + bnez s1, 1f + + // 1b. The same interrupt is taken from S-mode to S-mode. The trigger with + // s=1 fires just before the first instruction of the S-mode handler. + li s1, 1 + li t0, TDATA1_TYPE(TYPE_ITRIGGER) | XTRIG_S + csrw tdata1, t0 + li t0, MSTATUS_MPP_MASK + csrc mstatus, t0 + li t0, MSTATUS_MPP_S | MSTATUS_SIE + csrs mstatus, t0 + la t0, s_code + csrw mepc, t0 + mret + +1: + li t0, MSTATUS_SIE + csrc mstatus, t0 + li t0, MIP_SSIP + csrc mip, t0 + csrw mie, zero + j test_pass + +TEST_PASS_FAIL + +TEST_DATA diff --git a/verif/tests/custom/trigger_tests/sdtrig_tdata1_disable.S b/verif/tests/custom/trigger_tests/sdtrig_tdata1_disable.S new file mode 100644 index 00000000000..0abe2377b48 --- /dev/null +++ b/verif/tests/custom/trigger_tests/sdtrig_tdata1_disable.S @@ -0,0 +1,78 @@ +// Copyright 2026 10x Engineers +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Issue #3618: a write of 0 to tdata1 disables the trigger. +// A trigger that exists never reads back as type 0 ("no trigger"). + +#include "sdtrig_test.h" + + .option norvc + .section .text.init + .global _start +_start: + la t0, trap_handler + csrw mtvec, t0 + + // 1. After reset, the type of trigger 0 to 3 is not 0. + li s0, 0 + li s1, 4 +1: + csrw tselect, s0 + csrr t1, tselect + CHECK_EQ(t1, s0, 1) + csrr t1, tdata1 + srli t1, t1, XLEN - 4 + li a0, 2 + beqz t1, test_fail + addi s0, s0, 1 + bne s0, s1, 1b + + // 2. Arm an execute trigger on "target", then write 0 to tdata1. + csrw tselect, zero + la t0, target + csrw tdata2, t0 + li t0, TDATA1_TYPE(TYPE_MCONTROL6) | MC6_M | MC6_EXECUTE + csrw tdata1, t0 + csrw tdata1, zero + + // 3. The trigger reads back as disabled (type 15). + csrr t1, tdata1 + li t2, TDATA1_TYPE(TYPE_DISABLED) + CHECK_EQ(t1, t2, 3) + + // 4. The trigger does not fire on "target". + la t0, target + jr t0 + .align 3 +target: + nop + + // 5. A write of type 15 reads back as type 15. + li t0, TDATA1_TYPE(TYPE_DISABLED) + csrw tdata1, t0 + csrr t1, tdata1 + CHECK_EQ(t1, t0, 5) + + // 6. A write of type 2 (not supported) does not give type 0. + li t0, TDATA1_TYPE(2) | MC6_M | MC6_EXECUTE + csrw tdata1, t0 + csrr t1, tdata1 + srli t1, t1, XLEN - 4 + li a0, 6 + beqz t1, test_fail + + j test_pass + + .align 4 +trap_handler: + // A trap is a fail. Code 7 gives the trap. + li a0, 7 + j test_fail + +TEST_PASS_FAIL + +TEST_DATA diff --git a/verif/tests/custom/trigger_tests/sdtrig_test.h b/verif/tests/custom/trigger_tests/sdtrig_test.h new file mode 100644 index 00000000000..7b9c810a21e --- /dev/null +++ b/verif/tests/custom/trigger_tests/sdtrig_test.h @@ -0,0 +1,112 @@ +// Copyright 2026 10x Engineers +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Common definitions for the Sdtrig tests. The tests are the same for RV32 +// and RV64. A test writes 1 to tohost when it passes. When check N fails, it +// writes (N << 1) | 1 to tohost. + +#ifndef SDTRIG_TEST_H +#define SDTRIG_TEST_H + +#if __riscv_xlen == 64 +#define XLEN 64 +#define SREG sd +#define LREG ld +#else +#define XLEN 32 +#define SREG sw +#define LREG lw +#endif + +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 + +// tdata1 fields common to all types +#define TDATA1_TYPE(t) ((t) << (XLEN - 4)) +#define TDATA1_DMODE (1 << (XLEN - 5)) +#define TYPE_ICOUNT 3 +#define TYPE_ITRIGGER 4 +#define TYPE_ETRIGGER 5 +#define TYPE_MCONTROL6 6 +#define TYPE_DISABLED 15 + +// mcontrol6 +#define MC6_ACTION(a) ((a) << 12) +#define MC6_M (1 << 6) +#define MC6_S (1 << 4) +#define MC6_U (1 << 3) +#define MC6_EXECUTE (1 << 2) + +// icount +#define ICOUNT_COUNT(c) ((c) << 10) +#define ICOUNT_M (1 << 9) +#define ICOUNT_S (1 << 7) +#define ICOUNT_U (1 << 6) + +// itrigger and etrigger +#define XTRIG_M (1 << 9) +#define XTRIG_S (1 << 7) +#define XTRIG_U (1 << 6) + +// action field of icount, itrigger and etrigger +#define ACTION(a) (a) + +#define MSTATUS_MIE (1 << 3) +#define MSTATUS_SIE (1 << 1) +#define MSTATUS_SPP (1 << 8) +#define MSTATUS_MPP_MASK (3 << 11) +#define MSTATUS_MPP_S (1 << 11) +#define MIP_SSIP (1 << 1) +#define MIP_MTIP (1 << 7) +#define MCAUSE_INT (1 << (XLEN - 1)) + +#define CAUSE_ILLEGAL 2 +#define CAUSE_BREAKPOINT 3 +#define CAUSE_ECALL_U 8 +#define CAUSE_ECALL_M 11 + +#define CLINT_MTIMECMP 0x02004000 +#define CLINT_MTIME 0x0200bff8 + +// Check a condition. When it is not true, stop the test with code n. +#define CHECK_EQ(r1, r2, n) \ + li a0, n; \ + bne r1, r2, test_fail + +// Give all of the address space to S-mode and U-mode with one PMP entry. +#define PMP_ALLOW_ALL \ + li t0, -1; \ + csrw pmpaddr0, t0; \ + li t0, 0x1f; \ + csrw pmpcfg0, t0 + +// Write the result to tohost. The test stops here. +#define TEST_PASS_FAIL \ +test_pass: \ + li a0, 1; \ + j test_end; \ +test_fail: \ + slli a0, a0, 1; \ + ori a0, a0, 1; \ +test_end: \ + la t0, tohost; \ + sw a0, 0(t0); \ + sw zero, 4(t0); \ +1: \ + j 1b + +#define TEST_DATA \ + .section .tohost, "aw", @progbits; \ + .align 6; \ + .global tohost; \ +tohost: .dword 0; \ + .align 6; \ + .global fromhost; \ +fromhost: .dword 0 + +#endif diff --git a/verif/tests/custom/trigger_tests/trigger_csrs_access.S b/verif/tests/custom/trigger_tests/trigger_csrs_access.S new file mode 100644 index 00000000000..a22738cc7dd --- /dev/null +++ b/verif/tests/custom/trigger_tests/trigger_csrs_access.S @@ -0,0 +1,37 @@ +.text +.globl _start +_start: + ## TM CSRs read write test. Since the fields are WARL, written data may not match read data. + # Check CSR TSELECT + li x2, 2 + csrw tselect, x2 + + # Check CSR TDATA2 + li x4, 0x00000008 + csrw tdata2, x4 + + # Check CSR TDATA1 + li x5, 0x50000201 + csrw tdata1, x5 + + # Check CSR TDATA3 + li x8, 0x50021090 + csrw tdata3, x8 + + csrr x3, tselect + csrr x6, tdata2 + csrr x7, tdata1 + csrr x9, tdata3 + +exit: + li a1, 1 + la t2, tohost + sw a1, 0(t2) + j exit + +.data +.align 4 +.global tohost +tohost: .word 0 +.global fromhost +fromhost: .word 0 diff --git a/verif/tests/custom/trigger_tests/trigger_main.S b/verif/tests/custom/trigger_tests/trigger_main.S new file mode 100644 index 00000000000..1e9a0c59df1 --- /dev/null +++ b/verif/tests/custom/trigger_tests/trigger_main.S @@ -0,0 +1,355 @@ +# Copyright 2022 Thales DIS design services SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Mounsaf YOUSFI (mounsaf.yousfi@thalesgroup.fr) + +#***************************************************************************** +# mcontrol6 trigger test for all trigger types +#----------------------------------------------------------------------------- + +.data +load_array: .word 0xBEEFBEEF, 0xBEEEBEEE, 0xBEEFDEAD +store_array: .word 0x00000000, 0x00000000, 0x00000000 + + .globl main +main: + #Load custom trap_handler in trap vector + la t0, trap_handler + csrw mtvec, t0 + + ############### + # FIRST BATCH # + ############### + + #Trigger 0 configuration : TRIGGER ON PC EXECUTION + li x2, 0 + csrw tselect, x2 + #compare value encoding : here it's the PC we want to trigger on + la x3, trig0 + csrw tdata2, x3 + #tdata1 encoding + li x4, 0x60000044 //or : 0x60001044 for debug mode + csrw tdata1, x4 +trig0: + j fail + j fail + j fail + j fail +handler_return0: + # Trigger 1 configuration : TRIGGER ON INSTRUCTION + li x2, 1 + csrw tselect, x2 + #compare value encoding : here it's the instruction we want to trigger on + li x3, 0xFFFF4104 //uses masked low match type + csrw tdata2, x3 + #tdata1 encoding + li x4, 0x60200244 + csrw tdata1, x4 + + # Trigger 2 : TRIGGER ON STORE DATA + li x2, 2 + csrw tselect, x2 + li x3, 0xBEEFBEEF //Data to match + csrw tdata2, x3 + li x4, 0x60200042 //Config for store with data match + csrw tdata1, x4 + + + # Trigger 3 : TRIGGER ON LOAD DATA + li x2, 3 + csrw tselect, x2 + li x3, 0xBEEEBEEE //Data to match + csrw tdata2, x3 + li x4, 0x60200041 //Config for load with data match + csrw tdata1, x4 + + #Random useless instruction + li x5, 0xDEADDEAD + #If the triggers were effectively raised and the trap handler correctly handled every one of them, + #we should never jump to fail + beq x5, x5, trig1 #introduce some challenge for speculation handling units + j fail + +trig1: + lw x9, 0(x10) +handler_return1: + beq x4, x5, fail + li x6, 0xBEEFBEEF + la x5, store_array +trig2: + sw x6, 0(x5) + lw x6, 0(x5) + j fail +handler_return2: + bne x6, x5, resume_test + j fail +resume_test: + li x6, 0xBEEEBEEE + addi x9, x9, 4 + sw x6, 0(x9) + la x1, store_array + lw x3, 0(x1) + lw x3, 0(x1) + lw x3, 0(x1) + lw x3, 0(x1)//flood with loads to see if we don't infinite loop on break generation logic(tests if load unit is stalled) + lw x3, 0(x1) + lw x3, 0(x8) +trig3: + lw x6, 0(x9) +instruction_on_which_breakpoint_is_generated: + # addi x13, x13, 2 + sw x6, 0(x9) + lw x3, 0(x1) + lw x3, 0(x1) + addi x6, x6, -1 + j fail + +second_batch: + + ############### + # 2ND BATCH # + ############### + #Trigger 4 configuration : TRIGGER ON STORE ADDR + li x2, 0 + csrw tselect, x2 + la x3, store_array //Address to match + addi x3, x3, 8 + csrw tdata2, x3 + li x4, 0x60000042 //Config for store with address match + csrw tdata1, x4 + + #Trigger 5 configuration : TRIGGER ON LOAD ADDR + li x2, 1 + csrw tselect, x2 + la x3, load_array //Address to match + addi x3, x3, 8 + csrw tdata2, x3 + li x4, 0x60000041 //Config for load with address match + csrw tdata1, x4 + + la x3, store_array //Address to match + li x6, 0x11110000 +trig4: + sw x6, 8(x3) + j fail +handler_return4: + lw x6, 8(x3) + la x5, load_array + addi x5, x5, 8 + li x6, 0 +trig5: + lw x6, 0(x5) + +trigger_chain_test: + sw x6, 0(x5) + + # Trigger 0 CHAIN + li x2, 0 + csrw tselect, x2 + la x5, 0x0002a303 + csrw tdata2, x5 + li x4, 0x60200844 + csrw tdata1, x4 + + + # Trigger 1 CHAIN + li x2, 2 + csrw tselect, x2 + la x5, 0xBEEFBEEF + csrw tdata2, x5 + li x4, 0x60200841 + csrw tdata1, x4 + + # Trigger 2 CHAIN + li x2, 1 + csrw tselect, x2 + #compare value encoding (address to match) + la x5, load_array + csrw tdata2, x5 + li x4, 0x60000041 + csrw tdata1, x4 + + la x5, load_array +trig6: + lw x6, 0(x5) + j fail + +icountplusetrigger: + li x2, 1 + csrw tselect, x2 + li x3, 0x00000008 # Icount will gen break (ex cause 3) + csrw tdata2, x3 + li x4, 0x50000200 # match exception value with tdata2 and another break + csrw tdata1, x4 + + li x2, 0 + csrw tselect, x2 + li x2, 0x30003e00 # count 15 instructions break : ICOUNT + csrw tdata1, x2 +icount: + j icount + +itrigger: + # Trigger setup + li x2, 1 + csrw tselect, x2 + + li x3, 0xFFFFFFFF # match on software interrupt + csrw tdata2, x3 + + li x4, 0x40000200 # match on software interrupt and gen break + csrw tdata1, x4 + csrr x5, tdata1 + + li a1, 0xFFFFFFFF + csrw mie, a1 + csrr a2, mie + li a1, 0x8 + csrw mstatus, a1 +it_trigg: + j fail + +.align 4 +trap_handler: + csrr a0, mcause + csrr a1, mepc + + la a2, 0x80000000 + srli a0, a0, 28 + slli a0, a0, 28 //4 MSBs isolation + bne a2, a0, skipDisableInt //checks if its an interrupt that caused trap handling if yes, disable them, if not, skip disabling + li a1, 0x0 + csrw mie, a1 + csrr a2, mie + li a1, 0x0 + csrw mstatus, a1 +skipDisableInt: + csrr a0, mcause + la a2, icount + beq a2, a1, default_ret_plus_offset + li t3, 3 + bne a0, t3, default_ret #if we arent in trap handler for a breakpoint exception, resume execution + la a2, trap_handler + bne a2, a1, disable_trigger0 + li a3, 1 + csrw tselect, a3 + li a4, 0x00000000 + csrw tdata1, a4 + beq a2, a1, default_ret #we are here because of etrigger so icount worked, disable both and go to itrigger test +disable_trigger0: + la a2, trig0 + bne a1, a2, disable_trigger1 //if pc != trig address, it means we aren't here for this trigger (i could keep only this if and remove the prior one) + li a3, 0 //else + csrw tselect, a3 //select trigger 0 + li a4, 0x00000000 + csrw tdata1, a4 //disable trigger 0 + li a4, 0 //wipe compare value + csrw tdata2, a4 + la a3, handler_return0 + csrw mepc, a3 + beq a1, a2, default_ret //resume +disable_trigger1: + la a2, trig1 + bne a1, a2, disable_trigger2 + li a3, 1 + csrw tselect, a3 + li a4, 0x00000000 + csrw tdata1, a4 + csrr a4, tdata1 //disable trigger 1 + li a4, 0 + csrw tdata2, a4 + la a3, handler_return1 + csrw mepc, a3 + beq a1, a2, default_ret +disable_trigger2: + la a2, trig2 + bne a1, a2, disable_trigger3 + li a3, 2 + csrw tselect, a3 + li a4, 0x00000000 + csrw tdata1, a4 //disable trigger 2 + la a3, handler_return2 + csrw mepc, a3 + beq a1, a2, default_ret +disable_trigger3: + la a2, instruction_on_which_breakpoint_is_generated + bne a1, a2, disable_trigger4 + li a3, 3 + csrw tselect, a3 + li a4, 0x00000000 + csrw tdata1, a4 //disable trigger 3 + la a3, second_batch + csrw mepc, a3 + beq a1, a2, default_ret #if load is complete and then trigger happened then jump to second batch of triggers +disable_trigger4: + la a2, trig4 + bne a1, a2, disable_trigger5 + li a3, 0 + csrw tselect, a3 + li a4, 0x00000000 + csrw tdata1, a4 //disable trigger 4 + la a3, handler_return4 + csrw mepc, a3 + beq a1, a2, default_ret +disable_trigger5: + la a2, trig5 + bne a1, a2, disable_trigger6 + li a3, 1 + csrw tselect, a3 + li a4, 0x00000000 + csrw tdata1, a4 //disable trigger 4 + la a3, trigger_chain_test + csrw mepc, a3 + beq a1, a2, default_ret +disable_trigger6: + la a2, trig6 + bne a1, a2, disable_trigger7 + li a3, 0 + csrw tselect, a3 + li a4, 0x00000000 + csrw tdata1, a4 //disable chain + li a3, 1 + csrw tselect, a3 + li a4, 0x00000000 + csrw tdata1, a4 //disable chain + li a3, 2 + csrw tselect, a3 + li a4, 0x00000000 + csrw tdata1, a4 //disable chain + la a3, icountplusetrigger + csrw mepc, a3 + beq a1, a2, default_ret +disable_trigger7: + la a2, it_trigg + bne a1, a2, default_ret + la a3, pass + csrw mepc, a3 + beq a1, a2, default_ret + + j fail #if none of those condition is met, jump to fail + +default_ret: + mret + +default_ret_plus_offset: + la a2, itrigger + csrw mepc, a2 + mret + +pass: + li x1, 0 + slli x1, x1, 1 + addi x1, x1, 1 + sw x1, tohost, x30 + self_loop: j self_loop + +fail: + li x1, 1 + slli x1, x1, 1 + addi x1, x1, 1 + sw x1, tohost, x30 + self_loop_2: j self_loop_2 \ No newline at end of file diff --git a/verif/tests/custom/zcmt/cm_jalt_long.S b/verif/tests/custom/zcmt/cm_jalt_long.S index 51f0e3f0021..4a293ac53c0 100644 --- a/verif/tests/custom/zcmt/cm_jalt_long.S +++ b/verif/tests/custom/zcmt/cm_jalt_long.S @@ -1,59 +1,76 @@ .globl _start _start: - la t0, trap_handler - csrw mtvec, t0 + la t0, trap_handler + csrw mtvec, t0 - la a1, target1 + # Configure the Jump Vector Table. la t0, __jvt_base$ - sw a1, 128(t0) //cm.jalt entry start from index >=32 - - csrw jvt, t0 + # JVT CSR = 0x017. + # Use the numeric CSR address because the bundled assembler does not + # recognize the Zcmt CSR name. + csrw 0x017, t0 fence.i - # Perform jump using the index from JVT - cm.jalt 32 - li t1, 1 - addi x20,x20, 9 - j write_tohost + # cm.jalt 64 + # + # The bundled GNU assembler does not recognize the Zcmt mnemonic, so emit + # the architecturally defined 16-bit encoding directly. + # + # index = instruction[9:2] = 64 + # encoding = 0xa102 + .2byte 0xa102 + + # cm.jalt must not fall through. + j fail +target1: + j pass + +trap_handler: + j fail -exit: +pass: + # RISC-V test convention: tohost = 1 means success. + li x1, 1 j write_tohost +fail: + # An odd value greater than one represents failure. + li x1, 3 + write_tohost: - li x1, 1 - la t0, tohost - sw x1, 0(t0) - j write_tohost + la t0, tohost + sw x1, 0(t0) +1: + j 1b -# Jump Vector Table (JVT) Section -# Create a separate section for the JVT -.section .riscv.jvt, "ax" -.align 6 # Align the JVT on a 64-byte boundary (6 = 2^6 = 64) +# Jump Vector Table. +# +# Entry 0 deliberately points to the failure path. +# Entry 64 deliberately points to target1. +# +# With the buggy six-bit index calculation: +# index 64 aliases index 0 -> fail +# +# With the correct eight-bit calculation: +# index 64 -> target1 -> pass +.section .riscv.jvt, "a", @progbits +.align 6 __jvt_base$: - .word 0x80000054 - .word 0x80000800 - .word 0x80000802 - .word 0x80000804 - -# Target Addresses (Where cm.jalt will jump) -.align 20 -target1: - li x2, 99 - lui t0, %hi(write_tohost) # Load upper 20 bits of target address into t0 - addi t0, t0, %lo(write_tohost) # Add the lower 12 bits to t0 - jalr x0, 0(t0) - - - -trap_handler: - lui t0, %hi(write_tohost) # Load upper 20 bits of target address into t0 - addi t0, t0, %lo(write_tohost) # Add the lower 12 bits to t0 - jalr x0, 0(t0) + .word fail + .space 252 + .word target1 +.section .data +.align 6 +.global tohost +tohost: + .dword 0 -.align 6; .global tohost; tohost: .dword 0; -.align 6; .global fromhost; fromhost: .dword 0; \ No newline at end of file +.align 6 +.global fromhost +fromhost: + .dword 0 diff --git a/verif/tests/custom/zcmt/cm_jalt_target_lsb.S b/verif/tests/custom/zcmt/cm_jalt_target_lsb.S new file mode 100644 index 00000000000..ea507dff344 --- /dev/null +++ b/verif/tests/custom/zcmt/cm_jalt_target_lsb.S @@ -0,0 +1,78 @@ +.globl _start +_start: + la t0, trap_handler + csrw mtvec, t0 + + # Configure the Jump Vector Table. + la t0, __jvt_base$ + + # JVT CSR = 0x017. + # Use the numeric CSR address so this test does not depend on + # assembler support for the Zcmt CSR name. + csrw 0x017, t0 + + fence.i + + # JVT entry 64 contains cm_jalt_target + 1. cm.jalt must clear bit 0 + # before using the loaded value as the jump target. + # + # cm.jalt 64 encoding = 0xa102 + li s0, 0 + .2byte 0xa102 + +after_cm_jalt: + # The target must have executed and returned here. + beqz s0, fail + j pass + +.balign 2 +cm_jalt_target: + # Verify that the architectural PC has bit 0 cleared. + auipc t1, 0 + andi t1, t1, 1 + bnez t1, fail + + li s0, 1 + + # cm.jalt links to the instruction following the compressed jump. + ret + +.balign 4 +trap_handler: + j fail + +pass: + # RISC-V test convention: tohost = 1 means success. + li x1, 1 + j write_tohost + +fail: + # An odd value greater than one represents failure. + li x1, 3 + +write_tohost: + la t0, tohost + sw x1, 0(t0) + +1: + j 1b + +.section .riscv.jvt, "a", @progbits +.align 6 +__jvt_base$: + # Entries 0 through 63 are unused by this test. + .space 256 + + # Entry 64. + .word cm_jalt_target + 1 + +.section .data +.align 6 +.global tohost +tohost: + .dword 0 + +.align 6 +.global fromhost +fromhost: + .dword 0 diff --git a/verif/tests/custom/zcmt/cm_jt_target_lsb.S b/verif/tests/custom/zcmt/cm_jt_target_lsb.S new file mode 100644 index 00000000000..d1cfa898079 --- /dev/null +++ b/verif/tests/custom/zcmt/cm_jt_target_lsb.S @@ -0,0 +1,68 @@ +.globl _start +_start: + la t0, trap_handler + csrw mtvec, t0 + + # Configure the Jump Vector Table. + la t0, __jvt_base$ + + # JVT CSR = 0x017. + # Use the numeric CSR address so this test does not depend on + # assembler support for the Zcmt CSR name. + csrw 0x017, t0 + + fence.i + + # JVT entry 0 contains cm_jt_target + 1. cm.jt must clear bit 0 + # before using the loaded value as the jump target. + # + # cm.jt 0 encoding = 0xa002 + .2byte 0xa002 + + # cm.jt must not fall through. + j fail + +.balign 2 +cm_jt_target: + # Verify that the architectural PC has bit 0 cleared. + auipc t1, 0 + andi t1, t1, 1 + bnez t1, fail + + j pass + +.balign 4 +trap_handler: + j fail + +pass: + # RISC-V test convention: tohost = 1 means success. + li x1, 1 + j write_tohost + +fail: + # An odd value greater than one represents failure. + li x1, 3 + +write_tohost: + la t0, tohost + sw x1, 0(t0) + +1: + j 1b + +.section .riscv.jvt, "a", @progbits +.align 6 +__jvt_base$: + .word cm_jt_target + 1 + +.section .data +.align 6 +.global tohost +tohost: + .dword 0 + +.align 6 +.global fromhost +fromhost: + .dword 0 diff --git a/verif/tests/testlist_custom.yaml b/verif/tests/testlist_custom.yaml index 7f3c125cbc2..b90b48a5f5f 100644 --- a/verif/tests/testlist_custom.yaml +++ b/verif/tests/testlist_custom.yaml @@ -41,3 +41,7 @@ testlist: <<: *common_test_config asm_tests: /custom/hello_world/custom_test_template.S + - test: false_4k_alias + iterations: 1 + <<: *common_test_config + asm_tests: /custom/lsu/false_4k_alias.S diff --git a/verif/tests/testlist_hgatp_warl.yaml b/verif/tests/testlist_hgatp_warl.yaml new file mode 100644 index 00000000000..1594cfead77 --- /dev/null +++ b/verif/tests/testlist_hgatp_warl.yaml @@ -0,0 +1,8 @@ +# Regression for unsupported hgatp.MODE WARL handling. + +testlist: + - test: rv64h-p-hgatp-mode-warl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-tests/isa/macros/scalar/ -I/riscv-tests/env/p/ -I/riscv-tests/riscv-target/spike/" + asm_tests: /custom/hgatp_warl/hgatp_mode_warl.S diff --git a/verif/tests/testlist_hlvx_gstage.yaml b/verif/tests/testlist_hlvx_gstage.yaml new file mode 100644 index 00000000000..5adcf020d71 --- /dev/null +++ b/verif/tests/testlist_hlvx_gstage.yaml @@ -0,0 +1,14 @@ +# Testlist for the HLVX / G-stage page-table-read reproducer (cv64a6_imafdch_sv39). + +testlist: + - test: rv64h-p-hlvx-gstage + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-tests/isa/macros/scalar/ -I/riscv-tests/env/p/ -I/riscv-tests/riscv-target/spike/" + asm_tests: /custom/hlvx_gstage/hlvx_gstage_repro.S + + - test: rv64h-p-hlvx-gstage-ctrl + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-DGSTAGE_PT_EXEC -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/riscv-tests/isa/macros/scalar/ -I/riscv-tests/env/p/ -I/riscv-tests/riscv-target/spike/" + asm_tests: /custom/hlvx_gstage/hlvx_gstage_repro.S diff --git a/verif/tests/testlist_issues.yaml b/verif/tests/testlist_issues.yaml index 92913456ce9..1538b41fe67 100644 --- a/verif/tests/testlist_issues.yaml +++ b/verif/tests/testlist_issues.yaml @@ -34,7 +34,51 @@ common_test_config: &common_test_config path_var: TESTS_PATH gcc_opts: "-static -misa-spec=2.2 -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../../config/gen_from_riscv_config/linker/link.ld -lgcc" +pmp_test_config: &pmp_test_config + <<: *common_test_config + iterations: 1 + gcc_opts: >- + -static + -misa-spec=2.2 + -mcmodel=medany + -fvisibility=hidden + -nostdlib + -nostartfiles + ../tests/custom/common/syscalls.c + ../tests/custom/common/crt.S + -I../tests/custom/env + -I../tests/custom/common + -lgcc + testlist: + - test: pmp-lsu-transaction-rv64 + description: > + Check that PMP uses the access type and virtual address belonging to the + MMU response on DTLB-miss and DTLB-hit store transactions. + <<: *pmp_test_config + asm_tests: /custom/pmp/lsu_pipeline_store_test.S + + - test: pmp-lsu-transaction-no-mmu-rv64 + description: > + Check that the no-MMU LSU response keeps PMP address, access type, and + valid metadata aligned. + <<: *pmp_test_config + asm_tests: /custom/pmp/lsu_pipeline_store_no_mmu_test.S + + - test: pmp-amo-access-fault-rv64 + description: > + Check that a PMP-denied AMO reports a store/AMO access fault with the + matching tval and does not update its destination register. + <<: *pmp_test_config + asm_tests: /custom/pmp/amo_access_fault_test.S + + - test: pmp-hlvx-access-fault-rv64 + description: > + Check that HLVX execute permission and fault metadata belong to the + response transaction when ordinary loads and HLVX requests are adjacent. + <<: *pmp_test_config + asm_tests: /custom/pmp/hlvx_access_fault_test.S + - test: compressed-fpreg-commits-rv64 <<: *common_test_config iterations: 1 @@ -45,3 +89,152 @@ testlist: iterations: 1 asm_tests: /custom/issues/compressed-fpreg-commits-rv32.S + - test: misaligned-branch-rvc-disabled + <<: *common_test_config + iterations: 1 + gen_opts: +disable_compressed_instr=1 + gcc_opts: "-static -misa-spec=2.2 -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../../config/gen_from_riscv_config/linker/link.ld -lgcc -march=rv32im_zba_zbb_zbs_zbc_zicsr_zifencei -mabi=ilp32" + asm_tests: /custom/issues/misaligned-branch-rvc-disabled.S + - test: mret-mpv-rv64 + <<: *common_test_config + iterations: 1 + asm_tests: /custom/issues/mret-mpv-rv64.S + + - test: pmp-tor-grain-rv64 + <<: *common_test_config + description: > + Check that pmpaddr bit 0 does not affect either TOR boundary when the + PMP grain is eight bytes. + iterations: 1 + asm_tests: /custom/issues/pmp-tor-grain-rv64.S + + - test: zcmt-jvt-index-rv32 + description: > + Check that cm.jalt uses the complete eight-bit JVT table index. + iterations: 1 + path_var: TESTS_PATH + asm_tests: /custom/zcmt/cm_jalt_long.S + gcc_opts: >- + -static + -mcmodel=medany + -fvisibility=hidden + -nostdlib + -nostartfiles + + - test: decoder-zip-unzip-rv64 + <<: *common_test_config + iterations: 1 + asm_tests: /custom/issues/decoder-zip-unzip-rv64.S + + - test: pmp-misalign-priority-over-access-fault + description: > + Misaligned hsv.d/hlv.d to a PMP-denied paddr must report + address-misaligned (mcause 6/4), not access-fault (5/7). + iterations: 1 + path_var: TESTS_PATH + asm_tests: /custom/issues/pmp-misalign-priority-over-access-fault.S + gcc_opts: >- + -static -misa-spec=2.2 -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + /custom/common/crt.S + -I/custom/env -I/custom/common + -T ../../config/gen_from_riscv_config/linker/link.ld -lgcc -march=rv64gh + - test: vsmode-counterh-cause + description: > + RV64+H: a high-half counter CSR access from VS-mode must raise + illegal-instruction (mcause=2), not virtual-instruction (mcause=22). + iterations: 1 + path_var: TESTS_PATH + asm_tests: /custom/issues/vsmode_counterh_cause.S + gcc_opts: >- + -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + -I/riscv-tests/isa/macros/scalar/ + -I/riscv-tests/env/p/ + -march=rv64gh + + - test: zcmp-mva01s-equal-regs-rv32 + description: > + Check that cm.mva01s accepts equal r1s' and r2s' encodings. + iterations: 1 + path_var: TESTS_PATH + asm_tests: /custom/Zcmp/cm_mva01s_equal_regs_test.S + gcc_opts: >- + -static + -mcmodel=medany + -fvisibility=hidden + -nostdlib + -nostartfiles + -I../tests/custom/env + + - test: zcmt-jt-target-lsb-rv32 + description: > + Check that cm.jt clears bit 0 of the loaded JVT target. + iterations: 1 + path_var: TESTS_PATH + asm_tests: /custom/zcmt/cm_jt_target_lsb.S + gcc_opts: >- + -static + -mcmodel=medany + -fvisibility=hidden + -nostdlib + -nostartfiles + + - test: zcmt-jalt-target-lsb-rv32 + description: > + Check that cm.jalt clears bit 0 of the loaded JVT target. + iterations: 1 + path_var: TESTS_PATH + asm_tests: /custom/zcmt/cm_jalt_target_lsb.S + gcc_opts: >- + -static + -mcmodel=medany + -fvisibility=hidden + -nostdlib + -nostartfiles + + - test: load-misaligned-warning + <<: *common_test_config + description: > + Check that misaligned word and halfword loads raise load-address- + misaligned exceptions without terminating simulation in load_unit + offset assertions. + iterations: 1 + asm_tests: /custom/issues/load-misaligned-warning.S + + - test: zcmp-reserved-rlist-rv32 + description: > + Check that reserved Zcmp push/pop rlist values 0 through 3 + raise illegal-instruction exceptions. + iterations: 1 + path_var: TESTS_PATH + asm_tests: /custom/Zcmp/cm_reserved_rlist_test.S + gcc_opts: >- + -static + -mcmodel=medany + -fvisibility=hidden + -nostdlib + -nostartfiles + -I../tests/custom/env + + - test: fcvt-rv64-only-rv32 + <<: *common_test_config + description: > + Check that RV64-only FCVT L/LU conversions raise + illegal-instruction exceptions on RV32. + iterations: 1 + asm_tests: /custom/issues/fcvt-rv64-only-rv32.S + + - test: htval-mtval2-warl-rv64 + <<: *common_test_config + description: > + Check that RV64 Sv39x4 htval and mtval2 retain only the implemented + 2-bit-shifted guest-physical-address bits. + iterations: 1 + asm_tests: /custom/issues/htval-mtval2-warl-rv64.S + - test: xret-mprv-clear-rv64 + <<: *common_test_config + description: > + Check xRET mstatus.MPRV handling in an RVH-disabled configuration, + including MRET preservation when returning to M-mode and clearing + when MRET or SRET returns below M-mode. + iterations: 1 + asm_tests: /custom/issues/xret-mprv-clear-rv64.S diff --git a/verif/tests/testlist_pmp-cv32a65x.yaml b/verif/tests/testlist_pmp-cv32a65x.yaml new file mode 100644 index 00000000000..fa3da4cdd5a --- /dev/null +++ b/verif/tests/testlist_pmp-cv32a65x.yaml @@ -0,0 +1,77 @@ +# Copyright 2025 Thales CDI +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https:#solderpad.org/licenses/ +# +# Original Author: Valentin Thomazic (valentin.thomazic@thalesgroup.com) + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# testlist : Assembly test list +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- + +common_test_config: &common_test_config + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc" + +testlist: + - test: decreasing_entries_test + <<: *common_test_config + iterations: 1 + asm_tests: /custom/pmp/decreasing_entries_test.S + + - test: defined_matches + <<: *common_test_config + iterations: 0 + asm_tests: /custom/pmp/defined_matches.S + + - test: double_entries_test + <<: *common_test_config + iterations: 0 + asm_tests: /custom/pmp/double_entries_test.S + + - test: exact_csrr_test + <<: *common_test_config + iterations: 1 + asm_tests: /custom/pmp/exact_csrr_test.S + + - test: granularity_test + <<: *common_test_config + iterations: 1 + asm_tests: /custom/pmp/granularity_test.S + + - test: locked_outside_napot_test + <<: *common_test_config + iterations: 0 + asm_tests: /custom/pmp/locked_outside_napot_test.S + + - test: locked_outside_tor_test + <<: *common_test_config + iterations: 1 + asm_tests: /custom/pmp/locked_outside_tor_test.S + + - test: lsu_napot_test + <<: *common_test_config + iterations: 0 + asm_tests: /custom/pmp/lsu_napot_test.S + + - test: lsu_tor_test + <<: *common_test_config + iterations: 1 + asm_tests: /custom/pmp/lsu_tor_test.S diff --git a/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml index 94dc5f79416..2744949d774 100644 --- a/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml +++ b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml @@ -262,15 +262,15 @@ testlist: iterations: 1 asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S - - test: rv32im-lui-01 + - test: rv32im-lw-align-01 <<: *common_test_config iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S - - test: rv32im-lw-align-01 + - test: rv32im-lui-01 <<: *common_test_config iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S - test: rv32im-or-01 <<: *common_test_config @@ -292,6 +292,11 @@ testlist: iterations: 1 asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S + - test: rv32im-sw-align-01 + <<: *common_test_config + iterations: 1 + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S + - test: rv32im-sll-01 <<: *common_test_config iterations: 1 @@ -347,11 +352,6 @@ testlist: iterations: 1 asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S - - test: rv32im-sw-align-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S - - test: rv32im-xor-01 <<: *common_test_config iterations: 1 @@ -562,49 +562,4 @@ testlist: <<: *common_test_config iterations: 1 asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/B/src/zext.h_32-01.S - - ##A - - test: rv32im-amoadd.w-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoadd.w-01.S - - - test: rv32im-amoand.w-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoand.w-01.S - - - test: rv32im-amomax.w-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amomax.w-01.S - - - test: rv32im-amomaxu.w-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amomaxu.w-01.S - - - test: rv32im-amomin.w-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amomin.w-01.S - - - test: rv32im-amominu.w-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amominu.w-01.S - - - test: rv32im-amoor.w-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoor.w-01.S - - - test: rv32im-amoswap.w-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoswap.w-01.S - - - test: rv32im-amoxor.w-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S + ## NOTE: rv32i_m/A (Atomic/AMO) tests intentionally excluded - cv32a60x has RVA=0 diff --git a/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml b/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml index 21e2b91430d..14967eff082 100644 --- a/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml +++ b/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml @@ -262,15 +262,15 @@ testlist: <<: *common_test_config asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S - - test: rv32im-lui-01 + - test: rv32im-lw-align-01 iterations: 1 <<: *common_test_config - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S - - test: rv32im-lw-align-01 + - test: rv32im-lui-01 iterations: 1 <<: *common_test_config - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S - test: rv32im-or-01 iterations: 1 @@ -292,6 +292,11 @@ testlist: <<: *common_test_config asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S + - test: rv32im-sw-align-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S + - test: rv32im-sll-01 iterations: 1 <<: *common_test_config @@ -347,11 +352,6 @@ testlist: <<: *common_test_config asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S - - test: rv32im-sw-align-01 - iterations: 1 - <<: *common_test_config - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S - - test: rv32im-xor-01 iterations: 1 <<: *common_test_config diff --git a/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml index 1550d1f22c6..2a3ba79e062 100644 --- a/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml +++ b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml @@ -133,11 +133,6 @@ testlist: <<: *common_test_config asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lbu-align-01.S - - test: rv64i_m-ld-align01 - iterations: 1 - <<: *common_test_config - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ld-align-01.S - - test: rv64i_m-lh-align01 iterations: 1 <<: *common_test_config @@ -148,20 +143,20 @@ testlist: <<: *common_test_config asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lhu-align-01.S - - test: rv64i_m-lui + - test: rv64i_m-lw-align01 iterations: 1 <<: *common_test_config - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lui-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lw-align-01.S - - test: rv64i_m-lw-align01 + - test: rv64i_m-ld-align01 iterations: 1 <<: *common_test_config - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lw-align-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/ld-align-01.S - - test: rv64i_m-lb-align01 + - test: rv64i_m-lui iterations: 1 <<: *common_test_config - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lb-align-01.S + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/lui-01.S - test: rv64i_m-or iterations: 1 @@ -178,11 +173,6 @@ testlist: <<: *common_test_config asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sb-align-01.S - - test: rv64i_m-sd-align01 - iterations: 1 - <<: *common_test_config - asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sd-align-01.S - - test: rv64i_m-sh-align01 iterations: 1 <<: *common_test_config @@ -193,6 +183,11 @@ testlist: <<: *common_test_config asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sw-align-01.S + - test: rv64i_m-sd-align01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/I/src/sd-align-01.S + - test: rv64i_m-sll iterations: 1 <<: *common_test_config @@ -968,6 +963,7 @@ testlist: <<: *common_test_config asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S + #K - test: rv64im-pack-01 <<: *common_test_config iterations: 1 @@ -987,3 +983,168 @@ testlist: <<: *common_test_config iterations: 1 asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/brev8-01.S + + - test: rv64i_m-xperm8-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/xperm8-01.S + + - test: rv64i_m-xperm4-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/xperm4-01.S + + - test: rv64i_m-aes64es-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/aes64es-01.S + + - test: rv64i_m-aes64esm-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/aes64esm-01.S + + - test: rv64i_m-aes64ks2-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/aes64ks2-01.S + + - test: rv64i_m-aes64ks1i-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/aes64ks1i-01.S + + - test: rv64i_m-aes64ds-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/aes64ds-01.S + + - test: rv64i_m-aes64dsm-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/aes64dsm-01.S + + - test: rv64i_m-aes64im-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/aes64im-01.S + + - test: rv64i_m-sha256sig0-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sig0-01.S + + - test: rv64i_m-sha256sig0-rwp1 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sig0-rwp1.S + + - test: rv64i_m-sha256sig0-rwp2 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sig0-rwp2.S + + - test: rv64i_m-sha256sig1-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sig1-01.S + + - test: rv64i_m-sha256sig1-rwp1 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sig1-rwp1.S + + - test: rv64i_m-sha256sig1-rwp2 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sig1-rwp2.S + + - test: rv64i_m-sha256sum0-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sum0-01.S + + - test: rv64i_m-sha256sum0-rwp1 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sum0-rwp1.S + + - test: rv64i_m-sha256sum0-rwp2 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sum0-rwp2.S + + - test: rv64i_m-sha256sum1-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sum1-01.S + + - test: rv64i_m-sha256sum1-rwp1 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sum1-rwp1.S + + - test: rv64i_m-sha256sum1-rwp2 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha256sum1-rwp2.S + + - test: rv64i_m-sha512sig0-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sig0-01.S + + - test: rv64i_m-sha512sig0-rwp1 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sig0-rwp1.S + + - test: rv64i_m-sha512sig0-rwp2 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sig0-rwp2.S + + - test: rv64i_m-sha512sig1-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sig1-01.S + + - test: rv64i_m-sha512sig1-rwp1 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sig1-rwp1.S + + - test: rv64i_m-sha512sig1-rwp2 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sig1-rwp2.S + + - test: rv64i_m-sha512sum0-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sum0-01.S + + - test: rv64i_m-sha512sum0-rwp1 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sum0-rwp1.S + + - test: rv64i_m-sha512sum0-rwp2 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sum0-rwp2.S + + - test: rv64i_m-sha512sum1-01 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sum1-01.S + + - test: rv64i_m-sha512sum1-rwp1 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sum1-rwp1.S + + - test: rv64i_m-sha512sum1-rwp2 + iterations: 1 + <<: *common_test_config + asm_tests: /riscv-arch-test/riscv-test-suite/rv64i_m/K/src/sha512sum1-rwp2.S diff --git a/verif/tests/testlist_riscv-compliance-cv32a60x.yaml b/verif/tests/testlist_riscv-compliance-cv32a60x.yaml index 918be9d58c9..08e1cbe0cf8 100644 --- a/verif/tests/testlist_riscv-compliance-cv32a60x.yaml +++ b/verif/tests/testlist_riscv-compliance-cv32a60x.yaml @@ -355,7 +355,7 @@ testlist: - test: rv32mi-ma_addr <<: *common_test_config - iterations: 1 + iterations: 0 # spike needs to be configured with tval_en=1; cv32a60x has TvalEn=0 asm_tests: /riscv-compliance/riscv-test-suite/rv32mi/src/ma_addr.S - test: rv32mi-mcsr @@ -410,7 +410,7 @@ testlist: - test: rv32i-I-MISALIGN_LDST-01 <<: *common_test_config - iterations: 1 + iterations: 0 # spike needs to be configured with tval_en=1; cv32a60x has TvalEn=0 asm_tests: /riscv-compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S - test: rv32i-I-ECALL-01 @@ -625,22 +625,22 @@ testlist: - test: rv32si-sbreak <<: *common_test_config - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 asm_tests: /riscv-compliance/riscv-test-suite/rv32si/src/sbreak.S - test: rv32si-scall <<: *common_test_config - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 asm_tests: /riscv-compliance/riscv-test-suite/rv32si/src/scall.S - test: rv32si-ma_fetch <<: *common_test_config - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 asm_tests: /riscv-compliance/riscv-test-suite/rv32si/src/ma_fetch.S - test: rv32si-wfi <<: *common_test_config - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 asm_tests: /riscv-compliance/riscv-test-suite/rv32si/src/wfi.S - test: rv32si-dirty @@ -650,7 +650,7 @@ testlist: - test: rv32si-csr <<: *common_test_config - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 asm_tests: /riscv-compliance/riscv-test-suite/rv32si/src/csr.S - test: rv32imc-C-LW diff --git a/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml b/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml index bdafab5f59d..2a0a0f5d4ff 100644 --- a/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml +++ b/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml @@ -255,7 +255,7 @@ testlist: asm_tests: /riscv-tests/isa/rv32mi/illegal.S - test: rv32mi-p-ma_addr - iterations: 1 + iterations: 0 # cv32a60x has TvalEn=0; spike needs tval_en=1 for misaligned addr test <<: *common_test_config asm_tests: /riscv-tests/isa/rv32mi/ma_addr.S @@ -280,27 +280,27 @@ testlist: asm_tests: /riscv-tests/isa/rv32mi/shamt.S - test: rv32si-p-csr - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 (M-only) <<: *common_test_config asm_tests: /riscv-tests/isa/rv32si/csr.S - test: rv32si-p-ma_fetch - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 (M-only) <<: *common_test_config asm_tests: /riscv-tests/isa/rv32si/ma_fetch.S - test: rv32si-p-scall - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 (M-only) <<: *common_test_config asm_tests: /riscv-tests/isa/rv32si/scall.S - test: rv32si-p-wfi - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 (M-only) <<: *common_test_config asm_tests: /riscv-tests/isa/rv32si/wfi.S - test: rv32si-p-sbreak - iterations: 1 + iterations: 0 # needs supervisor mode; cv32a60x has RVS=0 (M-only) <<: *common_test_config asm_tests: /riscv-tests/isa/rv32si/sbreak.S diff --git a/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml b/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml index 258abb433af..acef5044861 100644 --- a/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml +++ b/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml @@ -349,6 +349,11 @@ testlist: <<: *common_test_config asm_tests: /riscv-tests/isa/rv64si/dirty.S + - test: rv64si-p-noncanonical + iterations: 1 + <<: *common_test_config + asm_tests: /custom/sv39/noncanonical.S + - test: rv64si-p-ma_fetch iterations: 1 <<: *common_test_config diff --git a/verif/tests/testlist_sdtrig-tests-cv32a60x.yaml b/verif/tests/testlist_sdtrig-tests-cv32a60x.yaml new file mode 100644 index 00000000000..1a42fb0d650 --- /dev/null +++ b/verif/tests/testlist_sdtrig-tests-cv32a60x.yaml @@ -0,0 +1,43 @@ +# Copyright Thales DIS SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# testlist : Assembly test list +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- +# + +common_test_config: &common_test_config + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostartfiles -g /custom/common/syscalls.c /custom/common/crt.S -I/custom/env -I/tests/custom/common " + +testlist: + - test: asic + iterations: 1 + <<: *common_test_config + asm_tests: /custom/trigger_tests/mcontrol6Asic.S \ No newline at end of file diff --git a/verif/tests/testlist_sdtrig-tests-cv32a65x.yaml b/verif/tests/testlist_sdtrig-tests-cv32a65x.yaml new file mode 100644 index 00000000000..5d8cef675d2 --- /dev/null +++ b/verif/tests/testlist_sdtrig-tests-cv32a65x.yaml @@ -0,0 +1,43 @@ +# Copyright Thales DIS SAS +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# ================================================================================ +# Regression test list format +# -------------------------------------------------------------------------------- +# testlist : Assembly test list +# test : Assembly test name +# description : Description of this test +# gen_opts : Instruction generator options +# iterations : Number of iterations of this test +# no_iss : Enable/disable ISS simulator (Optional) +# gen_test : Test name used by the instruction generator +# asm_tests : Path to directed, hand-coded assembly test file or directory +# rtl_test : RTL simulation test name +# cmp_opts : Compile options passed to the instruction generator +# sim_opts : Simulation options passed to the instruction generator +# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional) +# compare_opts : Options for the RTL & ISS trace comparison +# gcc_opts : gcc compile options +# -------------------------------------------------------------------------------- +# + +common_test_config: &common_test_config + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostartfiles -g /custom/common/syscalls.c /custom/common/crt.S -I/custom/env -I/tests/custom/common " + +testlist: + - test: complete + iterations: 1 + <<: *common_test_config + asm_tests: /custom/trigger_tests/mcontrol6complete.S \ No newline at end of file diff --git a/verif/tests/unit/csr_wfi/README.md b/verif/tests/unit/csr_wfi/README.md new file mode 100644 index 00000000000..37129cda523 --- /dev/null +++ b/verif/tests/unit/csr_wfi/README.md @@ -0,0 +1,63 @@ +# CSR WFI single-step regression + +This test instantiates the real `core/csr_regfile.sv` to reproduce CVA6 issue +#3497. It uses the `cv32a6_imac_sv32` configuration and a second instance of +that configuration with `DebugEn=0`. It does not force internal DUT state. + +The driver supplies decoded CSR operations, commit acknowledgements, and +exceptions at the CSR boundary. Debug entry is requested through the normal +CSR inputs; `dcsr` is programmed through CSR accesses, preserving its other +fields and selecting machine privilege, and execution resumes through `DRET`. + +Checks cover: + +- Stepped WFI with no interrupts or debug request, for both `stepie` values. +- Debug-entry redirect, single-step cause, saved privilege, and exact `DPC=PC+4`. +- No WFI halt immediately after debug re-entry or on following clocks. +- Continued debug CSR accesses and ordinary WFI after single-step is disabled. +- WFI in Debug Mode, with single-step clear and set. +- Ordinary WFI stall and wake through an enabled pending software interrupt, + `irq_i[1]`, and a debug request, including the debug-disabled case. +- Exception suppression of the WFI wait state and reset state. + +This is a CSR unit regression. It does not execute instructions through the +decoder/pipeline, execute the Debug ROM, validate trigger priority, run the +VCS/UVM debug suite, or claim coverage of other configurations. The minimal +scoreboard type includes the fields consumed by this module with triggers +disabled; the driver checks that the selected configuration disables triggers. + +## Requirements + +Use a Verilator 5 installation supporting `--binary --timing`, GNU Make, and +a C++20 compiler. The `core/cvfpu` submodule must be initialized for its package. +No RISC-V compiler, Spike libraries, or VCS license is needed. + +## Run + +From the repository root: + +```bash +bash verif/tests/unit/csr_wfi/run.sh /tmp/cva6-csr-wfi +``` + +The runner accepts an optional second argument selecting a different CSR RTL +file. `VERILATOR` may select an alternative Verilator executable. All generated +files go into the selected build directory, and compilation uses one job. + +To prove failure before the patch and success after it, supply an unpatched +baseline commit compatible with the remaining source tree: + +```bash +bash verif/tests/unit/csr_wfi/compare.sh \ + /tmp/cva6-3497-regression 40ac92ccc09534fb0c6b139a613f65868af9f499 +``` + +The comparator obtains only the baseline CSR file with `git show`; it never +replaces the working-tree RTL. It requires the baseline to fail at the specific +issue-3497 assertion, then requires the working-tree test to exit successfully +with the final pass marker. A compile failure cannot count as a reproduction. +Logs are `before.log` and `after.log` in the specified build directory. Keep +this directory outside the repository and retain it for review. + +On a machine with limited memory, run the comparator inside a systemd scope +with suitable memory limits, as with the main Verilator build. diff --git a/verif/tests/unit/csr_wfi/compare.sh b/verif/tests/unit/csr_wfi/compare.sh new file mode 100644 index 00000000000..1ebf8dead92 --- /dev/null +++ b/verif/tests/unit/csr_wfi/compare.sh @@ -0,0 +1,45 @@ +#!/usr/bin/env bash +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +set -euo pipefail +script_dir=$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")" && pwd) +repo_dir=$(cd -- "$script_dir/../../../.." && pwd) +if [[ $# -ne 2 ]]; then + printf 'Usage: bash %s BUILD_DIRECTORY BASELINE_GIT_REF\n' "$0" >&2 + exit 2 +fi +mkdir -p -- "$1" +build_dir=$(cd -- "$1" && pwd) +baseline_ref=$2 +baseline_dir=$(mktemp -d "$build_dir/baseline-source.XXXXXX") +git -C "$repo_dir" show "$baseline_ref:core/csr_regfile.sv" > "$baseline_dir/csr_regfile.sv" +printf 'Baseline commit: %s\n' "$(git -C "$repo_dir" rev-parse "$baseline_ref^{commit}")" +printf 'Build logs: %s\n' "$build_dir" +printf 'Building and running the pre-fix CSR module (one build job)...\n' +if bash "$script_dir/run.sh" "$build_dir/before" "$baseline_dir/csr_regfile.sv" \ + > "$build_dir/before.log" 2>&1; then + printf 'FAIL: baseline unexpectedly passed; reproduction was not established.\n' >&2 + exit 1 +else + before_status=$? +fi +if ! grep -Fq 'ISSUE3497: stepped WFI leaked halt into Debug Mode' "$build_dir/before.log"; then + tail -n 40 "$build_dir/before.log" >&2 + printf 'FAIL: baseline failed for another reason (exit %s).\n' "$before_status" >&2 + exit 1 +fi +printf 'PASS: original RTL reproduced issue #3497 (exit %s).\n' "$before_status" +printf 'Building and running the working-tree CSR module (one build job)...\n' +if bash "$script_dir/run.sh" "$build_dir/after" "$repo_dir/core/csr_regfile.sv" \ + > "$build_dir/after.log" 2>&1; then + if ! grep -Fxq 'PASS: CVA6 CSR WFI regression' "$build_dir/after.log"; then + printf 'FAIL: simulator exited without the final pass marker.\n' >&2 + exit 1 + fi +else + after_status=$? + tail -n 40 "$build_dir/after.log" >&2 + printf 'FAIL: working-tree test exited with status %s.\n' "$after_status" >&2 + exit 1 +fi +grep '^PASS' "$build_dir/after.log" +printf 'PASS: before/after CSR WFI regression comparison\n' diff --git a/verif/tests/unit/csr_wfi/csr_wfi_tb.sv b/verif/tests/unit/csr_wfi/csr_wfi_tb.sv new file mode 100644 index 00000000000..27ff03fc198 --- /dev/null +++ b/verif/tests/unit/csr_wfi/csr_wfi_tb.sv @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// CSR-level regression for CVA6 issue #3497. No forced DUT state or UVM. +`include "rvfi_types.svh" + +module csr_wfi_case #( + parameter bit DebugEn = 1'b1 +) ( + output bit done_o +); + import ariane_pkg::*; + timeunit 1ns; timeprecision 1ps; + + function automatic config_pkg::cva6_cfg_t test_config(); + config_pkg::cva6_cfg_t cfg; + cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg); + cfg.DebugEn = DebugEn; + return cfg; + endfunction + localparam config_pkg::cva6_cfg_t Cfg = test_config(); + typedef logic [Cfg.XLEN-1:0] xlen_t; + typedef struct packed { + xlen_t cause; + xlen_t tval; + logic [Cfg.GPLEN-1:0] tval2; + logic [31:0] tinst; + logic gva; + logic valid; + logic timing; + } exception_t; + // Only the scoreboard fields consumed by csr_regfile (triggers disabled). + typedef struct packed { + logic [Cfg.VLEN-1:0] pc; + fu_t fu; + struct packed {logic [Cfg.VLEN-1:0] predict_address;} bp; + logic is_compressed; + } commit_t; + typedef struct packed { + logic [Cfg.XLEN-7:0] base; + logic [5:0] mode; + } jvt_t; + typedef struct packed { + xlen_t mie, mip, mideleg, hideleg; + logic sie, global_enable; + } irq_ctrl_t; + typedef `RVFI_PROBES_CSR_T(Cfg) rvfi_csr_t; + + bit clk = 0; + bit rst_n = 0; + fu_op op; + logic [11:0] addr; + xlen_t wdata, rdata; + logic [Cfg.VLEN-1:0] pc; + logic [Cfg.NrCommitPorts-1:0] ack; + commit_t instruction; + exception_t exception_in, exception_out; + logic [1:0] irq; + logic ipi, debug_req; + logic halt, debug_mode, single_step, set_debug_pc, eret; + riscv::priv_lvl_t privilege; + + csr_regfile #( + .CVA6Cfg(Cfg), + .exception_t(exception_t), + .jvt_t(jvt_t), + .irq_ctrl_t(irq_ctrl_t), + .scoreboard_entry_t(commit_t), + .rvfi_probes_csr_t(rvfi_csr_t) + ) dut ( + .clk_i(clk), + .rst_ni(rst_n), + .time_irq_i(1'b0), + .halt_csr_o(halt), + .commit_instr_i(instruction), + .commit_ack_i(ack), + .boot_addr_i(Cfg.VLEN'('h80000000)), + .hart_id_i('0), + .ex_i(exception_in), + .csr_op_i(op), + .csr_addr_i(addr), + .csr_wdata_i(wdata), + .csr_rdata_o(rdata), + .dirty_fp_state_i(1'b0), + .csr_write_fflags_i(1'b0), + .dirty_v_state_i(1'b0), + .pc_i(pc), + .csr_exception_o(exception_out), + .eret_o(eret), + .priv_lvl_o(privilege), + .acc_fflags_ex_i('0), + .acc_fflags_ex_valid_i(1'b0), + .csr_hs_ld_st_inst_i(1'b0), + .irq_i(irq), + .ipi_i(ipi), + .debug_req_i(debug_req), + .set_debug_pc_o(set_debug_pc), + .debug_mode_o(debug_mode), + .single_step_o(single_step), + .perf_data_i('0), + .sdtrig_lsu_inputs_vaddr_i('0), + .sdtrig_lsu_inputs_data_i('0), + .sdtrig_lsu_inputs_fu_i(1'b0), + .sdtrig_lsu_inputs_valid_i(1'b0), + .sdtrig_load_data_i('0), + .sdtrig_load_valid_i(1'b0), + .fetch_sdtrig_pc_i('0), + .fetch_sdtrig_instr_i('0) + ); + + task automatic check(input bit condition, input string message); + if (!condition) $fatal(1, "FAIL DebugEn=%0d: %s", DebugEn, message); + endtask + + task automatic tick(); + #5ns; + clk = 1; + #5ns; + clk = 0; + #1ns; + endtask + + task automatic idle(); + op = ADD; + addr = '0; + wdata = '0; + pc = '0; + ack = '0; + instruction = '0; + exception_in = '0; + #1ns; + endtask + + task automatic reset_dut(); + rst_n = 0; + irq = '0; + ipi = 0; + debug_req = 0; + idle(); + tick(); + rst_n = 1; + tick(); + check(!halt && !debug_mode && !single_step, "reset state"); + endtask + + task automatic write_csr(input logic [11:0] address, input xlen_t value); + check(!halt, "CSR write attempted while halted"); + op = CSR_WRITE; + addr = address; + wdata = value; + ack[0] = 1; + #1ns; + check(!exception_out.valid, "unexpected CSR write exception"); + tick(); + idle(); + endtask + + task automatic read_csr(input logic [11:0] address, output xlen_t value); + check(!halt, "CSR read attempted while halted"); + op = CSR_READ; + addr = address; + #1ns; + check(!exception_out.valid, "unexpected CSR read exception"); + value = rdata; + idle(); + endtask + + task automatic enter_debug(); + debug_req = 1; + exception_in.valid = 1; + exception_in.cause = riscv::DEBUG_REQUEST; + pc = Cfg.VLEN'('h80000020); + #1ns; + check(set_debug_pc, "debug-request redirect"); + tick(); + debug_req = 0; + idle(); + check(debug_mode && !halt, "debug-request entry"); + endtask + + task automatic configure_step(input bit step_enable, input bit stepie); + xlen_t dcsr; + read_csr(riscv::CSR_DCSR, dcsr); + dcsr[2] = step_enable; + dcsr[11] = stepie; + dcsr[1:0] = riscv::PRIV_LVL_M; + write_csr(riscv::CSR_DCSR, dcsr); + check(single_step == step_enable, "step CSR programming"); + endtask + + task automatic resume_mmode(); + op = DRET; + ack[0] = 1; + #1ns; + check(eret, "DRET return indication"); + tick(); + idle(); + check(!debug_mode && !halt && privilege == riscv::PRIV_LVL_M, + "DRET must resume running in M mode"); + endtask + + task automatic commit_wfi(input xlen_t address); + check(!halt, "WFI issued while already halted"); + op = WFI; + pc = Cfg.VLEN'(address); + instruction.pc = Cfg.VLEN'(address); + instruction.fu = CSR; + instruction.is_compressed = 0; + ack[0] = 1; + #1ns; + if (DebugEn && single_step && !debug_mode) + check(set_debug_pc, "stepped WFI must request debug redirect"); + tick(); + idle(); + endtask + + task automatic normal_wfi_tests(); + reset_dut(); + write_csr(riscv::CSR_MIE, xlen_t'(1 << 3)); + commit_wfi(xlen_t'('h80000040)); + repeat (3) begin + check(halt && !debug_mode, "ordinary WFI must wait"); + tick(); + end + // mip is registered; allow its update and the following wake clock. + ipi = 1; + repeat (2) tick(); + check(!halt, "enabled pending interrupt must wake WFI"); + + reset_dut(); + commit_wfi(xlen_t'('h80000040)); + irq[1] = 1; + tick(); + check(!halt, "irq_i[1] must wake WFI"); + + reset_dut(); + commit_wfi(xlen_t'('h80000040)); + debug_req = 1; + tick(); + check(halt == !DebugEn, "debug-request wake must respect DebugEn"); + + reset_dut(); + // Exercise the CSR module's exception guard without retirement. + op = WFI; + exception_in.valid = 1; + exception_in.cause = riscv::ILLEGAL_INSTR; + tick(); + idle(); + check(!halt, "exceptional WFI must not set the wait state"); + $display("PASS ordinary WFI/wake/exception DebugEn=%0d", DebugEn); + endtask + + task automatic stepped_wfi_test(input bit stepie); + xlen_t value; + reset_dut(); + enter_debug(); + // WFI must remain non-stalling in Debug Mode with step clear or set. + commit_wfi(xlen_t'('h80000024)); + check(debug_mode && !halt, "WFI in Debug Mode with step=0"); + configure_step(1, stepie); + commit_wfi(xlen_t'('h80000028)); + check(debug_mode && !halt, "WFI in Debug Mode with step=1"); + resume_mmode(); + check(irq == 0 && !ipi && !debug_req, "no wake event may mask the bug"); + commit_wfi(xlen_t'('h80000040)); + check(debug_mode, "stepped WFI must re-enter Debug Mode"); + check(!halt, "ISSUE3497: stepped WFI leaked halt into Debug Mode"); + read_csr(riscv::CSR_DCSR, value); + check(value[8:6] == CauseSingleStep, "single-step debug cause"); + check(value[1:0] == riscv::PRIV_LVL_M, "single-step saved privilege"); + read_csr(riscv::CSR_DPC, value); + check(value == xlen_t'('h80000044), "DPC must equal WFI PC + 4"); + repeat (4) begin + tick(); + check(debug_mode && !halt, "no delayed WFI halt in Debug Mode"); + end + // Demonstrate continued CSR access; this does not execute a Debug ROM. + write_csr(riscv::CSR_DSCRATCH0, xlen_t'('h13579bdf)); + read_csr(riscv::CSR_DSCRATCH0, value); + check(value == xlen_t'('h13579bdf), "debug CSR access after stepped WFI"); + configure_step(0, stepie); + resume_mmode(); + commit_wfi(xlen_t'('h80000044)); + check(halt && !debug_mode, "clearing step must restore ordinary WFI"); + $display("PASS stepped WFI stepie=%0d", stepie); + endtask + + initial begin + done_o = 0; + check(!Cfg.Sdtrig, "test requires a configuration with triggers disabled"); + normal_wfi_tests(); + if (DebugEn) begin + stepped_wfi_test(0); + stepped_wfi_test(1); + end + done_o = 1; + end +endmodule + +module csr_wfi_tb; + timeunit 1ns; timeprecision 1ps; + wire debug_done, no_debug_done; + csr_wfi_case #(.DebugEn(1)) debug_case (.done_o(debug_done)); + csr_wfi_case #(.DebugEn(0)) no_debug_case (.done_o(no_debug_done)); + initial begin + wait (debug_done && no_debug_done); + $display("PASS: CVA6 CSR WFI regression"); + $finish; + end + initial begin + #100us; + $fatal(1, "FAIL: CSR WFI regression timeout"); + end +endmodule diff --git a/verif/tests/unit/csr_wfi/run.sh b/verif/tests/unit/csr_wfi/run.sh new file mode 100644 index 00000000000..16e8486ec1e --- /dev/null +++ b/verif/tests/unit/csr_wfi/run.sh @@ -0,0 +1,25 @@ +#!/usr/bin/env bash +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +set -euo pipefail +# The expected pre-fix assertion must not leave a core dump. +ulimit -c 0 +script_dir=$(cd -- "$(dirname -- "${BASH_SOURCE[0]}")" && pwd) +repo_dir=$(cd -- "$script_dir/../../../.." && pwd) +build_dir=${1:-$(mktemp -d "${TMPDIR:-/tmp}/cva6-csr-wfi.XXXXXX")} +csr_source=${2:-"$repo_dir/core/csr_regfile.sv"} +mkdir -p -- "$build_dir" +build_dir=$(cd -- "$build_dir" && pwd) +csr_source=$(realpath -- "$csr_source") +verilator_bin=${VERILATOR:-verilator} +"$verilator_bin" --binary --timing --assert -j 1 -CFLAGS "-std=c++20" \ + --top-module csr_wfi_tb --Mdir "$build_dir" \ + -Wno-fatal -Wno-PINMISSING -Wno-TIMESCALEMOD \ + -I"$repo_dir/core/include" \ + "$repo_dir/core/include/config_pkg.sv" \ + "$repo_dir/core/include/cv32a6_imac_sv32_config_pkg.sv" \ + "$repo_dir/core/include/riscv_pkg.sv" \ + "$repo_dir/core/cvfpu/src/fpnew_pkg.sv" \ + "$repo_dir/core/include/ariane_pkg.sv" \ + "$repo_dir/core/include/build_config_pkg.sv" \ + "$csr_source" "$script_dir/csr_wfi_tb.sv" +"$build_dir/Vcsr_wfi_tb" diff --git a/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv b/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv index ffcac3a1848..e1a75c672e8 100644 --- a/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv +++ b/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv @@ -220,7 +220,7 @@ function uvmt_cva6_base_test_c::new(string name="uvmt_cva6_base_test", uvm_compo super.new(name, parent); // Replaces default report server - // Gives you short-and-sweet looger messages like this: + // Gives you short-and-sweet logger messages like this: // UVM_INFO @ 9.750 ns : uvmt_cva6_dut_wrap.sv(79) reporter [DUT_WRAP] load_instr_mem asserted! rs = new("rs"); diff --git a/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv b/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv index e45f4925043..b35bda97041 100644 --- a/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv +++ b/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv @@ -29,7 +29,7 @@ * translate the firmware into a "hexfile" that is read into the CVA6 * instruction memory in the testbench module. * - * This class doesn't care what the firmware does, it mearly compiles it. + * This class doesn't care what the firmware does, it merely compiles it. * */ class uvmt_cva6_firmware_test_c extends uvmt_cva6_base_test_c; @@ -143,7 +143,7 @@ task uvmt_cva6_firmware_test_c::run_phase(uvm_phase phase); `uvm_info("TEST", "Test FINISHED", UVM_NONE) // Set sim_finished (otherwise tb will flag that sim was aborted) uvm_config_db#(bit)::set(null, "", "sim_finished", 1); - uvm_config_db#(int)::set(null, "", "test_exit_code", { 0'b0, tb_exit_vif.tb_exit_o[31:1] }); + uvm_config_db#(int)::set(null, "", "test_exit_code", { 1'b0, tb_exit_vif.tb_exit_o[31:1] }); // Let the termination-triggering instruction appear in the log. @(posedge env_cntxt.clknrst_cntxt.vif.clk); // Let all pending AXI requests settle.