From 6e29a0224df564f2248e930f925f4b55fa9eb2f9 Mon Sep 17 00:00:00 2001 From: DEV TYAGI Date: Wed, 2 Sep 2026 00:11:38 +0530 Subject: [PATCH] rtl: Add missing reset to PC carry-in flops (#151) Fixes #151. The registers `pc_plus_offset_cy_r` and `pc_plus_4_cy_r` are used in carry feedback paths. Without an explicit reset, they propagate `X` states during the first cycle of computation in gate-level simulations. This commit explicitly zeros them based on the `RESET_STRATEGY` parameter. --- rtl/serv_ctrl.v | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/rtl/serv_ctrl.v b/rtl/serv_ctrl.v index 9a14711b..dde0e040 100644 --- a/rtl/serv_ctrl.v +++ b/rtl/serv_ctrl.v @@ -98,11 +98,20 @@ module serv_ctrl assign pc_plus_offset_cy_r_w[0] = pc_plus_offset_cy_r; assign pc_plus_4_cy_r_w[0] = pc_plus_4_cy_r; - initial if (RESET_STRATEGY == "NONE") o_ibus_adr = RESET_PC; + initial if (RESET_STRATEGY == "NONE") begin + o_ibus_adr = RESET_PC; + pc_plus_4_cy_r = 1'b0; + pc_plus_offset_cy_r = 1'b0; + end always @(posedge clk) begin - pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy; - pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy; + if (RESET_STRATEGY != "NONE" && i_rst) begin + pc_plus_4_cy_r <= 1'b0; + pc_plus_offset_cy_r <= 1'b0; + end else begin + pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy; + pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy; + end if (RESET_STRATEGY == "NONE") begin if (i_pc_en)