From 5781f9279b0056c29178ad1f31598edeb7eb5d5d Mon Sep 17 00:00:00 2001 From: 94xhn <87560781+94xhn@users.noreply.github.com> Date: Sat, 11 Jul 2026 22:55:06 +0800 Subject: [PATCH 1/2] fix(linker): correct cross-toolchain memory map inconsistencies on NUCLEO-U031R8 Cross-checked the GCC (STM32CubeIDE), IAR (EWARM) and Keil (MDK-ARM) memory maps of every NUCLEO-U031R8 project against each other and against the STM32U031R8Tx datasheet (64 KB Flash / 12 KB SRAM). Two real drifts were found and fixed: 1. Examples/FLASH/FLASH_FastProgram The README explicitly states "All the executable code is mapped in SRAM1 area", and both the IAR linker script (EWARM/stm32u031xx_sram.icf) and the Keil project (MDK-ARM/FLASH_FastProgram.uvprojx, OCR_RVCT4) place the code region at 0x20000000/8 KB in SRAM instead of at 0x08000000 in Flash. The STM32CubeIDE linker script (STM32U031R8TX_FLASH.ld) was never updated to match: it still places .isr_vector/.text/.rodata in the physical Flash region. Since STM32U031 Flash has no read-while-write capability, a GCC build of this example would execute from Flash while the demo itself erases/programs that same Flash bank, which is invalid on this device. Fixed by mirroring the SRAM execution layout already used by GCC in the equivalent FLASH_FastProgram example of the STM32G4 family (STM32CubeG4 NUCLEO-G431KB/G431RB, *_SRAM.ld): FLASH region moved to 0x20000000/8 KB (code), RAM region moved to 0x20002000/4 KB (data/stack/heap), for a total of 12 KB matching the device's physical SRAM. The Keil project's IRAM1 data region (OCR_RVCT9) was also wrong: it declared 0x4000 (16 KB) at 0x20002000, which together with the 8 KB code region exceeds the device's total 12 KB physical SRAM. Corrected to 0x1000 (4 KB) to match the IAR icf and the device's real SRAM size. 2. Examples/PWR/PWR_ModesSelection The Keil project (MDK-ARM/PWR_ModesSelection.uvprojx) declared the device memory map of a different, larger STM32U0 part: IROM 0x08000000/256 KB and IRAM 0x20000000/32 KB, along with a FlashDriverDll pointing at the STM32U0xx_256k.FLM algorithm. STM32U031R8Tx only has 64 KB Flash / 8 KB usable SRAM, as confirmed by every other Keil project for this same board (Templates, all other ~25 Examples/Examples_LL projects) and by the GCC/IAR linker scripts of this same example, which correctly use 64 KB/8 KB. Corrected the tag, FlashDriverDll (now STM32U0xx_64k.FLM / -FL010000), and the OnChipMemories IRAM/IROM/OCR_RVCT4/OCR_RVCT9 entries to the correct 0x08000000/64 KB and 0x20000000/8 KB values, matching every sibling example project. No local ARM toolchain was available to rebuild the projects; the fix was verified purely by address/size arithmetic and by cross-referencing sibling example projects and precedent from the equivalent example in the STM32CubeG4 repository. Signed-off-by: 94xhn <87560781+94xhn@users.noreply.github.com> --- .../MDK-ARM/FLASH_FastProgram.uvprojx | 2 +- .../STM32CubeIDE/STM32U031R8TX_FLASH.ld | 9 +++++---- .../MDK-ARM/PWR_ModesSelection.uvprojx | 12 ++++++------ 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/Projects/NUCLEO-U031R8/Examples/FLASH/FLASH_FastProgram/MDK-ARM/FLASH_FastProgram.uvprojx b/Projects/NUCLEO-U031R8/Examples/FLASH/FLASH_FastProgram/MDK-ARM/FLASH_FastProgram.uvprojx index 3346283f..a8a3f724 100644 --- a/Projects/NUCLEO-U031R8/Examples/FLASH/FLASH_FastProgram/MDK-ARM/FLASH_FastProgram.uvprojx +++ b/Projects/NUCLEO-U031R8/Examples/FLASH/FLASH_FastProgram/MDK-ARM/FLASH_FastProgram.uvprojx @@ -302,7 +302,7 @@ 0 0x20002000 - 0x4000 + 0x1000 0 diff --git a/Projects/NUCLEO-U031R8/Examples/FLASH/FLASH_FastProgram/STM32CubeIDE/STM32U031R8TX_FLASH.ld b/Projects/NUCLEO-U031R8/Examples/FLASH/FLASH_FastProgram/STM32CubeIDE/STM32U031R8TX_FLASH.ld index bdef353f..b2198940 100644 --- a/Projects/NUCLEO-U031R8/Examples/FLASH/FLASH_FastProgram/STM32CubeIDE/STM32U031R8TX_FLASH.ld +++ b/Projects/NUCLEO-U031R8/Examples/FLASH/FLASH_FastProgram/STM32CubeIDE/STM32U031R8TX_FLASH.ld @@ -6,8 +6,9 @@ ** @author : Auto-generated by STM32CubeIDE ** ** @brief : Linker script for STM32U031R8Tx Device from STM32U0 series -** 64KBytes FLASH -** 8KBytes RAM +** All the executable code is mapped in SRAM1 area +** (see readme.txt: this example runs entirely from RAM) +** 8Kbytes of SRAM1 used for code, 4Kbytes for data ** ** Set heap size, stack size and stack location according ** to application requirements. @@ -44,8 +45,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 4K + FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 8K } /* Sections */ diff --git a/Projects/NUCLEO-U031R8/Examples/PWR/PWR_ModesSelection/MDK-ARM/PWR_ModesSelection.uvprojx b/Projects/NUCLEO-U031R8/Examples/PWR/PWR_ModesSelection/MDK-ARM/PWR_ModesSelection.uvprojx index db237aab..47c8a1c4 100644 --- a/Projects/NUCLEO-U031R8/Examples/PWR/PWR_ModesSelection/MDK-ARM/PWR_ModesSelection.uvprojx +++ b/Projects/NUCLEO-U031R8/Examples/PWR/PWR_ModesSelection/MDK-ARM/PWR_ModesSelection.uvprojx @@ -18,10 +18,10 @@ STMicroelectronics Keil.STM32U0xx_DFP.0.1.0 https://www.keil.com/pack/ - IRAM(0x20000000,0x8000) IRAM2(0x20002000,0x2000) IROM(0x08000000,0x040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + IRAM(0x20000000-0x20001FFF) IROM(0x8000000-0x800FFFF) CLOCK(25000000) CPUTYPE("Cortex-M0+") TZ - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC2000 -FN1 -FF0STM32U0xx_256k -FS08000000 -FL040000 -FP0($$Device:STM32U031R8Tx$CMSIS\Flash\STM32U0xx_256k.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC2000 -FN1 -FF0STM32U0xx_64k -FS08000000 -FL010000 -FP0($$Device:STM32U031R8Tx$CMSIS\Flash\STM32U0xx_64k.FLM)) 0 @@ -247,12 +247,12 @@ 0 0x20000000 - 0x8000 + 0x2000 1 0x8000000 - 0x40000 + 0x10000 0 @@ -277,7 +277,7 @@ 1 0x8000000 - 0x40000 + 0x10000 1 @@ -302,7 +302,7 @@ 0 0x20000000 - 0x8000 + 0x2000 0 From 9f71975343bc3b11f6879dd3ecf84f706091391b Mon Sep 17 00:00:00 2001 From: 94xhn <87560781+94xhn@users.noreply.github.com> Date: Tue, 28 Jul 2026 15:05:40 +0800 Subject: [PATCH 2/2] Preserve both SRAM banks in the U031 MDK project The STM32U031R8 exposes an 8 KiB SRAM1 bank and a 4 KiB SRAM2 bank. Align the PWR example device metadata and on-chip memory regions with the repository's canonical U031R8 template while retaining the corrected 64 KiB Flash definition. Constraint: Match the same-device MDK template and the PWR example's SRAM2 retention scenario Rejected: Keep only SRAM1 | the project explicitly exercises SRAM2 retention and the device template exposes both banks Confidence: high Scope-risk: narrow Directive: Keep the two physical SRAM banks distinct in MDK memory metadata Tested: XML parse, exact field comparison with Templates/MDK-ARM, SRAM interval arithmetic, git diff --check Not-tested: MDK-ARM build is unavailable locally --- .../PWR_ModesSelection/MDK-ARM/PWR_ModesSelection.uvprojx | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Projects/NUCLEO-U031R8/Examples/PWR/PWR_ModesSelection/MDK-ARM/PWR_ModesSelection.uvprojx b/Projects/NUCLEO-U031R8/Examples/PWR/PWR_ModesSelection/MDK-ARM/PWR_ModesSelection.uvprojx index 47c8a1c4..4f90c2d0 100644 --- a/Projects/NUCLEO-U031R8/Examples/PWR/PWR_ModesSelection/MDK-ARM/PWR_ModesSelection.uvprojx +++ b/Projects/NUCLEO-U031R8/Examples/PWR/PWR_ModesSelection/MDK-ARM/PWR_ModesSelection.uvprojx @@ -18,7 +18,7 @@ STMicroelectronics Keil.STM32U0xx_DFP.0.1.0 https://www.keil.com/pack/ - IRAM(0x20000000-0x20001FFF) IROM(0x8000000-0x800FFFF) CLOCK(25000000) CPUTYPE("Cortex-M0+") TZ + IRAM(0x20000000,0x2000) IRAM2(0x20002000,0x1000) IROM(0x08000000,0x010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE UL2CM3(-S0 -C0 -P0 -FD20000000 -FC2000 -FN1 -FF0STM32U0xx_64k -FS08000000 -FL010000 -FP0($$Device:STM32U031R8Tx$CMSIS\Flash\STM32U0xx_64k.FLM)) @@ -306,8 +306,8 @@ 0 - 0x0 - 0x0 + 0x20002000 + 0x1000