From 8323cbe07977b59d3fef3c1ca7c224d6b9440510 Mon Sep 17 00:00:00 2001 From: 94xhn <87560781+94xhn@users.noreply.github.com> Date: Sat, 11 Jul 2026 22:54:13 +0800 Subject: [PATCH] fix(linker): correct cross-toolchain memory map inconsistencies Cross-referenced the GCC (SW4STM32/STM32CubeIDE), IAR (EWARM), and Keil (MDK-ARM) memory-map declarations against each other and against the Templates project (or ST's own documented flash partition figures) for every project under Projects/. Found and fixed five independent, verifiable inconsistencies: - STM32303E_EVAL/Applications/IAP/IAP_Binary_Template: IAR ROM_region and Keil OCR_RVCT4 (IROM1) both started the readonly region at 0x08000000/kept its full 512K size, instead of 0x08004000/496K as documented in IAP_Main/readme.txt ("maximum size of the image to be loaded is: 496 Kbytes") and already correctly implemented by the GCC linker script. - STM32373C_EVAL/Applications/IAP/IAP_Binary_Template: same bootloader reserved-area bug, this time reproduced in all three toolchains (GCC LENGTH, IAR ROM_region, Keil OCR_RVCT4 all kept the full 256K instead of shrinking to 240K), contradicting the 240 Kbytes figure documented in IAP_Main/readme.txt. - STM32F302R8-Nucleo/Examples/ADC/{ADC_AnalogWatchdog,ADC_Sequencer}: IAR .icf files declared ROM 0x08000000-0x0803FFFF (256K) and RAM 0x20000000-0x20009FFF (40K) plus a bogus CCMRAM region, while the actual part (STM32F302R8) only has 64K flash / 16K RAM and no CCM RAM at all, as correctly reflected by the GCC/Keil files in the same two example directories and by all 31 other .icf files under this board (confirmed by grep across the whole board). - STM32F3348-Discovery/Templates_LL (MDK-ARM only): IROM/IRAM device fields and the active OCR_RVCT4/OCR_RVCT9 linker regions declared 32K ROM / 192K RAM, versus the correct 64K ROM / 12K RAM already used by this project's own GCC ld and IAR icf files, and by the sibling Templates (non-LL) project's Keil configuration for the identical STM32F334C8 part. - STM32F3348-Discovery/Examples/HRTIM/{HRTIM_LLC_HalfBridge, HRTIM_Multiphase}: IAR RAM_end was 0x20003FFF (16K), 4K past the physical 12K SRAM on STM32F334C8, while both the GCC ld and the Keil Cpu/IRAM fields in the same two projects correctly declare 0x20002FFF (12K). Signed-off-by: 94xhn <87560781+94xhn@users.noreply.github.com> --- .../IAP_Binary_Template/EWARM/stm32f303xe_flash.icf | 2 +- .../IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx | 2 +- .../IAP_Binary_Template/EWARM/stm32f373xc_flash.icf | 2 +- .../IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx | 2 +- .../SW4STM32/STM32373C_EVAL/STM32F373VCTx_FLASH.ld | 2 +- .../ADC_AnalogWatchdog/EWARM/stm32f302x8_flash.icf | 11 ++++------- .../ADC/ADC_Sequencer/EWARM/stm32f302x8_flash.icf | 11 ++++------- .../HRTIM_LLC_HalfBridge/EWARM/stm32f334x8_flash.icf | 2 +- .../HRTIM_Multiphase/EWARM/stm32f334x8_flash.icf | 2 +- .../Templates_LL/MDK-ARM/Project.uvprojx | 8 ++++---- 10 files changed, 19 insertions(+), 25 deletions(-) diff --git a/Projects/STM32303E_EVAL/Applications/IAP/IAP_Binary_Template/EWARM/stm32f303xe_flash.icf b/Projects/STM32303E_EVAL/Applications/IAP/IAP_Binary_Template/EWARM/stm32f303xe_flash.icf index c0202d6bd..69e534eb3 100644 --- a/Projects/STM32303E_EVAL/Applications/IAP/IAP_Binary_Template/EWARM/stm32f303xe_flash.icf +++ b/Projects/STM32303E_EVAL/Applications/IAP/IAP_Binary_Template/EWARM/stm32f303xe_flash.icf @@ -4,7 +4,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x08004000; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_start__ = 0x08004000; define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; diff --git a/Projects/STM32303E_EVAL/Applications/IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx b/Projects/STM32303E_EVAL/Applications/IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx index df8af1915..48362b296 100644 --- a/Projects/STM32303E_EVAL/Applications/IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx +++ b/Projects/STM32303E_EVAL/Applications/IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx @@ -275,7 +275,7 @@ 1 0x8004000 - 0x80000 + 0x7c000 1 diff --git a/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/EWARM/stm32f373xc_flash.icf b/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/EWARM/stm32f373xc_flash.icf index 03f5cbea1..9b4af9023 100644 --- a/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/EWARM/stm32f373xc_flash.icf +++ b/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/EWARM/stm32f373xc_flash.icf @@ -4,7 +4,7 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x08004000; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_start__ = 0x08004000; define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; diff --git a/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx b/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx index e4b6b7917..f7924b7d8 100644 --- a/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx +++ b/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/MDK-ARM/Project.uvprojx @@ -314,7 +314,7 @@ 1 0x8004000 - 0x40000 + 0x3c000 1 diff --git a/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/SW4STM32/STM32373C_EVAL/STM32F373VCTx_FLASH.ld b/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/SW4STM32/STM32373C_EVAL/STM32F373VCTx_FLASH.ld index e54f65383..04d31f8fe 100644 --- a/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/SW4STM32/STM32373C_EVAL/STM32F373VCTx_FLASH.ld +++ b/Projects/STM32373C_EVAL/Applications/IAP/IAP_Binary_Template/SW4STM32/STM32373C_EVAL/STM32F373VCTx_FLASH.ld @@ -35,7 +35,7 @@ _Min_Stack_Size = 0x400;; /* required amount of stack */ /* Specify the memory areas */ MEMORY { -FLASH (rx) : ORIGIN = 0x08004000, LENGTH = 256K +FLASH (rx) : ORIGIN = 0x08004000, LENGTH = 240K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K } diff --git a/Projects/STM32F302R8-Nucleo/Examples/ADC/ADC_AnalogWatchdog/EWARM/stm32f302x8_flash.icf b/Projects/STM32F302R8-Nucleo/Examples/ADC/ADC_AnalogWatchdog/EWARM/stm32f302x8_flash.icf index 1ff118e9f..021a5dc2c 100644 --- a/Projects/STM32F302R8-Nucleo/Examples/ADC/ADC_AnalogWatchdog/EWARM/stm32f302x8_flash.icf +++ b/Projects/STM32F302R8-Nucleo/Examples/ADC/ADC_AnalogWatchdog/EWARM/stm32f302x8_flash.icf @@ -4,12 +4,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x08000000; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF; -define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; -define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10001FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x400; define symbol __ICFEDIT_size_heap__ = 0x200; @@ -19,7 +17,6 @@ define symbol __ICFEDIT_size_heap__ = 0x200; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; diff --git a/Projects/STM32F302R8-Nucleo/Examples/ADC/ADC_Sequencer/EWARM/stm32f302x8_flash.icf b/Projects/STM32F302R8-Nucleo/Examples/ADC/ADC_Sequencer/EWARM/stm32f302x8_flash.icf index 1ff118e9f..021a5dc2c 100644 --- a/Projects/STM32F302R8-Nucleo/Examples/ADC/ADC_Sequencer/EWARM/stm32f302x8_flash.icf +++ b/Projects/STM32F302R8-Nucleo/Examples/ADC/ADC_Sequencer/EWARM/stm32f302x8_flash.icf @@ -4,12 +4,10 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x08000000; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF; -define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; -define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10001FFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x400; define symbol __ICFEDIT_size_heap__ = 0x200; @@ -19,7 +17,6 @@ define symbol __ICFEDIT_size_heap__ = 0x200; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; diff --git a/Projects/STM32F3348-Discovery/Examples/HRTIM/HRTIM_LLC_HalfBridge/EWARM/stm32f334x8_flash.icf b/Projects/STM32F3348-Discovery/Examples/HRTIM/HRTIM_LLC_HalfBridge/EWARM/stm32f334x8_flash.icf index 1d766a6e3..07844448a 100644 --- a/Projects/STM32F3348-Discovery/Examples/HRTIM/HRTIM_LLC_HalfBridge/EWARM/stm32f334x8_flash.icf +++ b/Projects/STM32F3348-Discovery/Examples/HRTIM/HRTIM_LLC_HalfBridge/EWARM/stm32f334x8_flash.icf @@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000; define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF; define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10000FFF; /*-Sizes-*/ diff --git a/Projects/STM32F3348-Discovery/Examples/HRTIM/HRTIM_Multiphase/EWARM/stm32f334x8_flash.icf b/Projects/STM32F3348-Discovery/Examples/HRTIM/HRTIM_Multiphase/EWARM/stm32f334x8_flash.icf index 1d766a6e3..07844448a 100644 --- a/Projects/STM32F3348-Discovery/Examples/HRTIM/HRTIM_Multiphase/EWARM/stm32f334x8_flash.icf +++ b/Projects/STM32F3348-Discovery/Examples/HRTIM/HRTIM_Multiphase/EWARM/stm32f334x8_flash.icf @@ -7,7 +7,7 @@ define symbol __ICFEDIT_intvec_start__ = 0x08000000; define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF; define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; define symbol __ICFEDIT_region_CCMRAM_end__ = 0x10000FFF; /*-Sizes-*/ diff --git a/Projects/STM32F3348-Discovery/Templates_LL/MDK-ARM/Project.uvprojx b/Projects/STM32F3348-Discovery/Templates_LL/MDK-ARM/Project.uvprojx index 711970ae3..415e8a35e 100644 --- a/Projects/STM32F3348-Discovery/Templates_LL/MDK-ARM/Project.uvprojx +++ b/Projects/STM32F3348-Discovery/Templates_LL/MDK-ARM/Project.uvprojx @@ -243,12 +243,12 @@ 0 0x20000000 - 0x30000 + 0x3000 1 0x8000000 - 0x8000 + 0x10000 0 @@ -273,7 +273,7 @@ 1 0x8000000 - 0x8000 + 0x10000 1 @@ -298,7 +298,7 @@ 0 0x20000000 - 0x30000 + 0x3000 0